1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 #define regPC_CONFIG_CNTL_1 0x194d 64 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 103 }; 104 105 static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = { 106 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x8000b007), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f) 120 }; 121 122 #define DEFAULT_SH_MEM_CONFIG \ 123 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 124 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 125 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 126 127 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 128 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 129 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 130 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 131 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 132 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 133 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 134 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 135 struct amdgpu_cu_info *cu_info); 136 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 137 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 138 u32 sh_num, u32 instance, int xcc_id); 139 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 140 141 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 142 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 143 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 144 uint32_t val); 145 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 146 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 147 uint16_t pasid, uint32_t flush_type, 148 bool all_hub, uint8_t dst_sel); 149 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 150 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 151 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 152 bool enable); 153 154 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 155 { 156 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 157 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 158 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 159 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 160 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 161 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 162 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 163 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 164 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 165 } 166 167 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 168 struct amdgpu_ring *ring) 169 { 170 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 171 uint64_t wptr_addr = ring->wptr_gpu_addr; 172 uint32_t me = 0, eng_sel = 0; 173 174 switch (ring->funcs->type) { 175 case AMDGPU_RING_TYPE_COMPUTE: 176 me = 1; 177 eng_sel = 0; 178 break; 179 case AMDGPU_RING_TYPE_GFX: 180 me = 0; 181 eng_sel = 4; 182 break; 183 case AMDGPU_RING_TYPE_MES: 184 me = 2; 185 eng_sel = 5; 186 break; 187 default: 188 WARN_ON(1); 189 } 190 191 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 192 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 193 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 194 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 195 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 196 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 197 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 198 PACKET3_MAP_QUEUES_ME((me)) | 199 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 200 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 201 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 202 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 203 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 204 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 205 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 206 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 207 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 208 } 209 210 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 211 struct amdgpu_ring *ring, 212 enum amdgpu_unmap_queues_action action, 213 u64 gpu_addr, u64 seq) 214 { 215 struct amdgpu_device *adev = kiq_ring->adev; 216 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 217 218 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 219 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 220 return; 221 } 222 223 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 224 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 225 PACKET3_UNMAP_QUEUES_ACTION(action) | 226 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 227 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 228 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 229 amdgpu_ring_write(kiq_ring, 230 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 231 232 if (action == PREEMPT_QUEUES_NO_UNMAP) { 233 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 234 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 235 amdgpu_ring_write(kiq_ring, seq); 236 } else { 237 amdgpu_ring_write(kiq_ring, 0); 238 amdgpu_ring_write(kiq_ring, 0); 239 amdgpu_ring_write(kiq_ring, 0); 240 } 241 } 242 243 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 244 struct amdgpu_ring *ring, 245 u64 addr, 246 u64 seq) 247 { 248 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 249 250 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 251 amdgpu_ring_write(kiq_ring, 252 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 253 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 254 PACKET3_QUERY_STATUS_COMMAND(2)); 255 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 256 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 257 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 258 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 259 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 260 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 261 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 262 } 263 264 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 265 uint16_t pasid, uint32_t flush_type, 266 bool all_hub) 267 { 268 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 269 } 270 271 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 272 .kiq_set_resources = gfx11_kiq_set_resources, 273 .kiq_map_queues = gfx11_kiq_map_queues, 274 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 275 .kiq_query_status = gfx11_kiq_query_status, 276 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 277 .set_resources_size = 8, 278 .map_queues_size = 7, 279 .unmap_queues_size = 6, 280 .query_status_size = 7, 281 .invalidate_tlbs_size = 2, 282 }; 283 284 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 285 { 286 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 287 } 288 289 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 290 { 291 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 292 case IP_VERSION(11, 0, 1): 293 case IP_VERSION(11, 0, 4): 294 soc15_program_register_sequence(adev, 295 golden_settings_gc_11_0_1, 296 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 297 break; 298 case IP_VERSION(11, 5, 0): 299 soc15_program_register_sequence(adev, 300 golden_settings_gc_11_5_0, 301 (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0)); 302 break; 303 default: 304 break; 305 } 306 } 307 308 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 309 bool wc, uint32_t reg, uint32_t val) 310 { 311 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 312 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 313 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 314 amdgpu_ring_write(ring, reg); 315 amdgpu_ring_write(ring, 0); 316 amdgpu_ring_write(ring, val); 317 } 318 319 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 320 int mem_space, int opt, uint32_t addr0, 321 uint32_t addr1, uint32_t ref, uint32_t mask, 322 uint32_t inv) 323 { 324 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 325 amdgpu_ring_write(ring, 326 /* memory (1) or register (0) */ 327 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 328 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 329 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 330 WAIT_REG_MEM_ENGINE(eng_sel))); 331 332 if (mem_space) 333 BUG_ON(addr0 & 0x3); /* Dword align */ 334 amdgpu_ring_write(ring, addr0); 335 amdgpu_ring_write(ring, addr1); 336 amdgpu_ring_write(ring, ref); 337 amdgpu_ring_write(ring, mask); 338 amdgpu_ring_write(ring, inv); /* poll interval */ 339 } 340 341 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 342 { 343 struct amdgpu_device *adev = ring->adev; 344 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 345 uint32_t tmp = 0; 346 unsigned i; 347 int r; 348 349 WREG32(scratch, 0xCAFEDEAD); 350 r = amdgpu_ring_alloc(ring, 5); 351 if (r) { 352 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 353 ring->idx, r); 354 return r; 355 } 356 357 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 358 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 359 } else { 360 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 361 amdgpu_ring_write(ring, scratch - 362 PACKET3_SET_UCONFIG_REG_START); 363 amdgpu_ring_write(ring, 0xDEADBEEF); 364 } 365 amdgpu_ring_commit(ring); 366 367 for (i = 0; i < adev->usec_timeout; i++) { 368 tmp = RREG32(scratch); 369 if (tmp == 0xDEADBEEF) 370 break; 371 if (amdgpu_emu_mode == 1) 372 msleep(1); 373 else 374 udelay(1); 375 } 376 377 if (i >= adev->usec_timeout) 378 r = -ETIMEDOUT; 379 return r; 380 } 381 382 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 struct amdgpu_ib ib; 386 struct dma_fence *f = NULL; 387 unsigned index; 388 uint64_t gpu_addr; 389 volatile uint32_t *cpu_ptr; 390 long r; 391 392 /* MES KIQ fw hasn't indirect buffer support for now */ 393 if (adev->enable_mes_kiq && 394 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 395 return 0; 396 397 memset(&ib, 0, sizeof(ib)); 398 399 if (ring->is_mes_queue) { 400 uint32_t padding, offset; 401 402 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 403 padding = amdgpu_mes_ctx_get_offs(ring, 404 AMDGPU_MES_CTX_PADDING_OFFS); 405 406 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 407 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 408 409 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 410 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 411 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 412 } else { 413 r = amdgpu_device_wb_get(adev, &index); 414 if (r) 415 return r; 416 417 gpu_addr = adev->wb.gpu_addr + (index * 4); 418 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 419 cpu_ptr = &adev->wb.wb[index]; 420 421 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 422 if (r) { 423 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 424 goto err1; 425 } 426 } 427 428 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 429 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 430 ib.ptr[2] = lower_32_bits(gpu_addr); 431 ib.ptr[3] = upper_32_bits(gpu_addr); 432 ib.ptr[4] = 0xDEADBEEF; 433 ib.length_dw = 5; 434 435 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 436 if (r) 437 goto err2; 438 439 r = dma_fence_wait_timeout(f, false, timeout); 440 if (r == 0) { 441 r = -ETIMEDOUT; 442 goto err2; 443 } else if (r < 0) { 444 goto err2; 445 } 446 447 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 448 r = 0; 449 else 450 r = -EINVAL; 451 err2: 452 if (!ring->is_mes_queue) 453 amdgpu_ib_free(adev, &ib, NULL); 454 dma_fence_put(f); 455 err1: 456 if (!ring->is_mes_queue) 457 amdgpu_device_wb_free(adev, index); 458 return r; 459 } 460 461 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 462 { 463 amdgpu_ucode_release(&adev->gfx.pfp_fw); 464 amdgpu_ucode_release(&adev->gfx.me_fw); 465 amdgpu_ucode_release(&adev->gfx.rlc_fw); 466 amdgpu_ucode_release(&adev->gfx.mec_fw); 467 468 kfree(adev->gfx.rlc.register_list_format); 469 } 470 471 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 472 { 473 const struct psp_firmware_header_v1_0 *toc_hdr; 474 int err = 0; 475 char fw_name[40]; 476 477 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 478 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 479 if (err) 480 goto out; 481 482 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 483 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 484 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 485 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 486 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 487 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 488 return 0; 489 out: 490 amdgpu_ucode_release(&adev->psp.toc_fw); 491 return err; 492 } 493 494 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 495 { 496 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 497 case IP_VERSION(11, 0, 0): 498 case IP_VERSION(11, 0, 2): 499 case IP_VERSION(11, 0, 3): 500 if ((adev->gfx.me_fw_version >= 1505) && 501 (adev->gfx.pfp_fw_version >= 1600) && 502 (adev->gfx.mec_fw_version >= 512)) { 503 if (amdgpu_sriov_vf(adev)) 504 adev->gfx.cp_gfx_shadow = true; 505 else 506 adev->gfx.cp_gfx_shadow = false; 507 } 508 break; 509 default: 510 adev->gfx.cp_gfx_shadow = false; 511 break; 512 } 513 } 514 515 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 516 { 517 char fw_name[40]; 518 char ucode_prefix[30]; 519 int err; 520 const struct rlc_firmware_header_v2_0 *rlc_hdr; 521 uint16_t version_major; 522 uint16_t version_minor; 523 524 DRM_DEBUG("\n"); 525 526 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 527 528 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 529 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 530 if (err) 531 goto out; 532 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 533 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 534 (union amdgpu_firmware_header *) 535 adev->gfx.pfp_fw->data, 2, 0); 536 if (adev->gfx.rs64_enable) { 537 dev_info(adev->dev, "CP RS64 enable\n"); 538 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 539 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 540 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 541 } else { 542 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 543 } 544 545 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 546 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 547 if (err) 548 goto out; 549 if (adev->gfx.rs64_enable) { 550 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 551 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 552 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 553 } else { 554 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 555 } 556 557 if (!amdgpu_sriov_vf(adev)) { 558 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 559 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 560 if (err) 561 goto out; 562 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 563 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 564 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 565 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 566 if (err) 567 goto out; 568 } 569 570 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 572 if (err) 573 goto out; 574 if (adev->gfx.rs64_enable) { 575 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 576 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 577 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 578 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 579 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 580 } else { 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 583 } 584 585 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 586 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 587 588 /* only one MEC for gfx 11.0.0. */ 589 adev->gfx.mec2_fw = NULL; 590 591 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 592 out: 593 if (err) { 594 amdgpu_ucode_release(&adev->gfx.pfp_fw); 595 amdgpu_ucode_release(&adev->gfx.me_fw); 596 amdgpu_ucode_release(&adev->gfx.rlc_fw); 597 amdgpu_ucode_release(&adev->gfx.mec_fw); 598 } 599 600 return err; 601 } 602 603 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 604 { 605 u32 count = 0; 606 const struct cs_section_def *sect = NULL; 607 const struct cs_extent_def *ext = NULL; 608 609 /* begin clear state */ 610 count += 2; 611 /* context control state */ 612 count += 3; 613 614 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 615 for (ext = sect->section; ext->extent != NULL; ++ext) { 616 if (sect->id == SECT_CONTEXT) 617 count += 2 + ext->reg_count; 618 else 619 return 0; 620 } 621 } 622 623 /* set PA_SC_TILE_STEERING_OVERRIDE */ 624 count += 3; 625 /* end clear state */ 626 count += 2; 627 /* clear state */ 628 count += 2; 629 630 return count; 631 } 632 633 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 634 volatile u32 *buffer) 635 { 636 u32 count = 0, i; 637 const struct cs_section_def *sect = NULL; 638 const struct cs_extent_def *ext = NULL; 639 int ctx_reg_offset; 640 641 if (adev->gfx.rlc.cs_data == NULL) 642 return; 643 if (buffer == NULL) 644 return; 645 646 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 647 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 648 649 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 650 buffer[count++] = cpu_to_le32(0x80000000); 651 buffer[count++] = cpu_to_le32(0x80000000); 652 653 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 654 for (ext = sect->section; ext->extent != NULL; ++ext) { 655 if (sect->id == SECT_CONTEXT) { 656 buffer[count++] = 657 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 658 buffer[count++] = cpu_to_le32(ext->reg_index - 659 PACKET3_SET_CONTEXT_REG_START); 660 for (i = 0; i < ext->reg_count; i++) 661 buffer[count++] = cpu_to_le32(ext->extent[i]); 662 } else { 663 return; 664 } 665 } 666 } 667 668 ctx_reg_offset = 669 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 670 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 671 buffer[count++] = cpu_to_le32(ctx_reg_offset); 672 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 673 674 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 675 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 676 677 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 678 buffer[count++] = cpu_to_le32(0); 679 } 680 681 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 682 { 683 /* clear state block */ 684 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 685 &adev->gfx.rlc.clear_state_gpu_addr, 686 (void **)&adev->gfx.rlc.cs_ptr); 687 688 /* jump table block */ 689 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 690 &adev->gfx.rlc.cp_table_gpu_addr, 691 (void **)&adev->gfx.rlc.cp_table_ptr); 692 } 693 694 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 695 { 696 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 697 698 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 699 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 700 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 701 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 702 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 703 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 704 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 705 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 706 adev->gfx.rlc.rlcg_reg_access_supported = true; 707 } 708 709 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 710 { 711 const struct cs_section_def *cs_data; 712 int r; 713 714 adev->gfx.rlc.cs_data = gfx11_cs_data; 715 716 cs_data = adev->gfx.rlc.cs_data; 717 718 if (cs_data) { 719 /* init clear state block */ 720 r = amdgpu_gfx_rlc_init_csb(adev); 721 if (r) 722 return r; 723 } 724 725 /* init spm vmid with 0xf */ 726 if (adev->gfx.rlc.funcs->update_spm_vmid) 727 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 728 729 return 0; 730 } 731 732 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 733 { 734 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 735 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 736 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 737 } 738 739 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 740 { 741 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 742 743 amdgpu_gfx_graphics_queue_acquire(adev); 744 } 745 746 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 747 { 748 int r; 749 u32 *hpd; 750 size_t mec_hpd_size; 751 752 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 753 754 /* take ownership of the relevant compute queues */ 755 amdgpu_gfx_compute_queue_acquire(adev); 756 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 757 758 if (mec_hpd_size) { 759 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 760 AMDGPU_GEM_DOMAIN_GTT, 761 &adev->gfx.mec.hpd_eop_obj, 762 &adev->gfx.mec.hpd_eop_gpu_addr, 763 (void **)&hpd); 764 if (r) { 765 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 766 gfx_v11_0_mec_fini(adev); 767 return r; 768 } 769 770 memset(hpd, 0, mec_hpd_size); 771 772 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 773 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 774 } 775 776 return 0; 777 } 778 779 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 780 { 781 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 782 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 783 (address << SQ_IND_INDEX__INDEX__SHIFT)); 784 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 785 } 786 787 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 788 uint32_t thread, uint32_t regno, 789 uint32_t num, uint32_t *out) 790 { 791 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 792 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 793 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 794 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 795 (SQ_IND_INDEX__AUTO_INCR_MASK)); 796 while (num--) 797 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 798 } 799 800 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 801 { 802 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 803 * field when performing a select_se_sh so it should be 804 * zero here */ 805 WARN_ON(simd != 0); 806 807 /* type 3 wave data */ 808 dst[(*no_fields)++] = 3; 809 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 810 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 811 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 812 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 824 } 825 826 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 827 uint32_t wave, uint32_t start, 828 uint32_t size, uint32_t *dst) 829 { 830 WARN_ON(simd != 0); 831 832 wave_read_regs( 833 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 834 dst); 835 } 836 837 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 838 uint32_t wave, uint32_t thread, 839 uint32_t start, uint32_t size, 840 uint32_t *dst) 841 { 842 wave_read_regs( 843 adev, wave, thread, 844 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 845 } 846 847 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 848 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 849 { 850 soc21_grbm_select(adev, me, pipe, q, vm); 851 } 852 853 /* all sizes are in bytes */ 854 #define MQD_SHADOW_BASE_SIZE 73728 855 #define MQD_SHADOW_BASE_ALIGNMENT 256 856 #define MQD_FWWORKAREA_SIZE 484 857 #define MQD_FWWORKAREA_ALIGNMENT 256 858 859 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 860 struct amdgpu_gfx_shadow_info *shadow_info) 861 { 862 if (adev->gfx.cp_gfx_shadow) { 863 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 864 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 865 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 866 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 867 return 0; 868 } else { 869 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 870 return -ENOTSUPP; 871 } 872 } 873 874 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 875 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 876 .select_se_sh = &gfx_v11_0_select_se_sh, 877 .read_wave_data = &gfx_v11_0_read_wave_data, 878 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 879 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 880 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 881 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 882 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 883 }; 884 885 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 886 { 887 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 888 case IP_VERSION(11, 0, 0): 889 case IP_VERSION(11, 0, 2): 890 adev->gfx.config.max_hw_contexts = 8; 891 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 892 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 893 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 894 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 895 break; 896 case IP_VERSION(11, 0, 3): 897 adev->gfx.ras = &gfx_v11_0_3_ras; 898 adev->gfx.config.max_hw_contexts = 8; 899 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 900 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 901 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 902 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 903 break; 904 case IP_VERSION(11, 0, 1): 905 case IP_VERSION(11, 0, 4): 906 case IP_VERSION(11, 5, 0): 907 adev->gfx.config.max_hw_contexts = 8; 908 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 909 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 910 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 911 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 912 break; 913 default: 914 BUG(); 915 break; 916 } 917 918 return 0; 919 } 920 921 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 922 int me, int pipe, int queue) 923 { 924 int r; 925 struct amdgpu_ring *ring; 926 unsigned int irq_type; 927 928 ring = &adev->gfx.gfx_ring[ring_id]; 929 930 ring->me = me; 931 ring->pipe = pipe; 932 ring->queue = queue; 933 934 ring->ring_obj = NULL; 935 ring->use_doorbell = true; 936 937 if (!ring_id) 938 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 939 else 940 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 941 ring->vm_hub = AMDGPU_GFXHUB(0); 942 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 943 944 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 945 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 946 AMDGPU_RING_PRIO_DEFAULT, NULL); 947 if (r) 948 return r; 949 return 0; 950 } 951 952 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 953 int mec, int pipe, int queue) 954 { 955 int r; 956 unsigned irq_type; 957 struct amdgpu_ring *ring; 958 unsigned int hw_prio; 959 960 ring = &adev->gfx.compute_ring[ring_id]; 961 962 /* mec0 is me1 */ 963 ring->me = mec + 1; 964 ring->pipe = pipe; 965 ring->queue = queue; 966 967 ring->ring_obj = NULL; 968 ring->use_doorbell = true; 969 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 970 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 971 + (ring_id * GFX11_MEC_HPD_SIZE); 972 ring->vm_hub = AMDGPU_GFXHUB(0); 973 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 974 975 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 976 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 977 + ring->pipe; 978 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 979 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 980 /* type-2 packets are deprecated on MEC, use type-3 instead */ 981 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 982 hw_prio, NULL); 983 if (r) 984 return r; 985 986 return 0; 987 } 988 989 static struct { 990 SOC21_FIRMWARE_ID id; 991 unsigned int offset; 992 unsigned int size; 993 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 994 995 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 996 { 997 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 998 999 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1000 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1001 rlc_autoload_info[ucode->id].id = ucode->id; 1002 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1003 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1004 1005 ucode++; 1006 } 1007 } 1008 1009 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1010 { 1011 uint32_t total_size = 0; 1012 SOC21_FIRMWARE_ID id; 1013 1014 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1015 1016 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1017 total_size += rlc_autoload_info[id].size; 1018 1019 /* In case the offset in rlc toc ucode is aligned */ 1020 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1021 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1022 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1023 1024 return total_size; 1025 } 1026 1027 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1028 { 1029 int r; 1030 uint32_t total_size; 1031 1032 total_size = gfx_v11_0_calc_toc_total_size(adev); 1033 1034 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1035 AMDGPU_GEM_DOMAIN_VRAM | 1036 AMDGPU_GEM_DOMAIN_GTT, 1037 &adev->gfx.rlc.rlc_autoload_bo, 1038 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1039 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1040 1041 if (r) { 1042 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1043 return r; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1050 SOC21_FIRMWARE_ID id, 1051 const void *fw_data, 1052 uint32_t fw_size, 1053 uint32_t *fw_autoload_mask) 1054 { 1055 uint32_t toc_offset; 1056 uint32_t toc_fw_size; 1057 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1058 1059 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1060 return; 1061 1062 toc_offset = rlc_autoload_info[id].offset; 1063 toc_fw_size = rlc_autoload_info[id].size; 1064 1065 if (fw_size == 0) 1066 fw_size = toc_fw_size; 1067 1068 if (fw_size > toc_fw_size) 1069 fw_size = toc_fw_size; 1070 1071 memcpy(ptr + toc_offset, fw_data, fw_size); 1072 1073 if (fw_size < toc_fw_size) 1074 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1075 1076 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1077 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1078 } 1079 1080 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1081 uint32_t *fw_autoload_mask) 1082 { 1083 void *data; 1084 uint32_t size; 1085 uint64_t *toc_ptr; 1086 1087 *(uint64_t *)fw_autoload_mask |= 0x1; 1088 1089 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1090 1091 data = adev->psp.toc.start_addr; 1092 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1093 1094 toc_ptr = (uint64_t *)data + size / 8 - 1; 1095 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1096 1097 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1098 data, size, fw_autoload_mask); 1099 } 1100 1101 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1102 uint32_t *fw_autoload_mask) 1103 { 1104 const __le32 *fw_data; 1105 uint32_t fw_size; 1106 const struct gfx_firmware_header_v1_0 *cp_hdr; 1107 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1108 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1109 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1110 uint16_t version_major, version_minor; 1111 1112 if (adev->gfx.rs64_enable) { 1113 /* pfp ucode */ 1114 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1115 adev->gfx.pfp_fw->data; 1116 /* instruction */ 1117 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1118 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1119 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1120 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1121 fw_data, fw_size, fw_autoload_mask); 1122 /* data */ 1123 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1124 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1125 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1126 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1127 fw_data, fw_size, fw_autoload_mask); 1128 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1129 fw_data, fw_size, fw_autoload_mask); 1130 /* me ucode */ 1131 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1132 adev->gfx.me_fw->data; 1133 /* instruction */ 1134 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1135 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1136 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1137 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1138 fw_data, fw_size, fw_autoload_mask); 1139 /* data */ 1140 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1141 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1142 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1143 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1144 fw_data, fw_size, fw_autoload_mask); 1145 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1146 fw_data, fw_size, fw_autoload_mask); 1147 /* mec ucode */ 1148 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1149 adev->gfx.mec_fw->data; 1150 /* instruction */ 1151 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1152 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1153 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1154 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1155 fw_data, fw_size, fw_autoload_mask); 1156 /* data */ 1157 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1158 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1159 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1160 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1161 fw_data, fw_size, fw_autoload_mask); 1162 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1163 fw_data, fw_size, fw_autoload_mask); 1164 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1165 fw_data, fw_size, fw_autoload_mask); 1166 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1167 fw_data, fw_size, fw_autoload_mask); 1168 } else { 1169 /* pfp ucode */ 1170 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1171 adev->gfx.pfp_fw->data; 1172 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1173 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1174 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1175 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1176 fw_data, fw_size, fw_autoload_mask); 1177 1178 /* me ucode */ 1179 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1180 adev->gfx.me_fw->data; 1181 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1182 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1183 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1184 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1185 fw_data, fw_size, fw_autoload_mask); 1186 1187 /* mec ucode */ 1188 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1189 adev->gfx.mec_fw->data; 1190 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1191 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1192 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1193 cp_hdr->jt_size * 4; 1194 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1195 fw_data, fw_size, fw_autoload_mask); 1196 } 1197 1198 /* rlc ucode */ 1199 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1200 adev->gfx.rlc_fw->data; 1201 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1202 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1203 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1204 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1205 fw_data, fw_size, fw_autoload_mask); 1206 1207 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1208 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1209 if (version_major == 2) { 1210 if (version_minor >= 2) { 1211 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1212 1213 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1214 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1215 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1216 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1217 fw_data, fw_size, fw_autoload_mask); 1218 1219 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1220 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1221 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1222 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1223 fw_data, fw_size, fw_autoload_mask); 1224 } 1225 } 1226 } 1227 1228 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1229 uint32_t *fw_autoload_mask) 1230 { 1231 const __le32 *fw_data; 1232 uint32_t fw_size; 1233 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1234 1235 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1236 adev->sdma.instance[0].fw->data; 1237 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1238 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1239 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1240 1241 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1242 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1243 1244 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1245 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1246 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1247 1248 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1249 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1250 } 1251 1252 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1253 uint32_t *fw_autoload_mask) 1254 { 1255 const __le32 *fw_data; 1256 unsigned fw_size; 1257 const struct mes_firmware_header_v1_0 *mes_hdr; 1258 int pipe, ucode_id, data_id; 1259 1260 for (pipe = 0; pipe < 2; pipe++) { 1261 if (pipe==0) { 1262 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1263 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1264 } else { 1265 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1266 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1267 } 1268 1269 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1270 adev->mes.fw[pipe]->data; 1271 1272 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1273 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1274 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1275 1276 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1277 ucode_id, fw_data, fw_size, fw_autoload_mask); 1278 1279 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1280 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1281 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1282 1283 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1284 data_id, fw_data, fw_size, fw_autoload_mask); 1285 } 1286 } 1287 1288 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1289 { 1290 uint32_t rlc_g_offset, rlc_g_size; 1291 uint64_t gpu_addr; 1292 uint32_t autoload_fw_id[2]; 1293 1294 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1295 1296 /* RLC autoload sequence 2: copy ucode */ 1297 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1298 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1299 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1300 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1301 1302 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1303 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1304 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1305 1306 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1307 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1308 1309 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1310 1311 /* RLC autoload sequence 3: load IMU fw */ 1312 if (adev->gfx.imu.funcs->load_microcode) 1313 adev->gfx.imu.funcs->load_microcode(adev); 1314 /* RLC autoload sequence 4 init IMU fw */ 1315 if (adev->gfx.imu.funcs->setup_imu) 1316 adev->gfx.imu.funcs->setup_imu(adev); 1317 if (adev->gfx.imu.funcs->start_imu) 1318 adev->gfx.imu.funcs->start_imu(adev); 1319 1320 /* RLC autoload sequence 5 disable gpa mode */ 1321 gfx_v11_0_disable_gpa_mode(adev); 1322 1323 return 0; 1324 } 1325 1326 static int gfx_v11_0_sw_init(void *handle) 1327 { 1328 int i, j, k, r, ring_id = 0; 1329 struct amdgpu_kiq *kiq; 1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1331 1332 adev->gfxhub.funcs->init(adev); 1333 1334 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1335 case IP_VERSION(11, 0, 0): 1336 case IP_VERSION(11, 0, 2): 1337 case IP_VERSION(11, 0, 3): 1338 adev->gfx.me.num_me = 1; 1339 adev->gfx.me.num_pipe_per_me = 1; 1340 adev->gfx.me.num_queue_per_pipe = 1; 1341 adev->gfx.mec.num_mec = 2; 1342 adev->gfx.mec.num_pipe_per_mec = 4; 1343 adev->gfx.mec.num_queue_per_pipe = 4; 1344 break; 1345 case IP_VERSION(11, 0, 1): 1346 case IP_VERSION(11, 0, 4): 1347 case IP_VERSION(11, 5, 0): 1348 adev->gfx.me.num_me = 1; 1349 adev->gfx.me.num_pipe_per_me = 1; 1350 adev->gfx.me.num_queue_per_pipe = 1; 1351 adev->gfx.mec.num_mec = 1; 1352 adev->gfx.mec.num_pipe_per_mec = 4; 1353 adev->gfx.mec.num_queue_per_pipe = 4; 1354 break; 1355 default: 1356 adev->gfx.me.num_me = 1; 1357 adev->gfx.me.num_pipe_per_me = 1; 1358 adev->gfx.me.num_queue_per_pipe = 1; 1359 adev->gfx.mec.num_mec = 1; 1360 adev->gfx.mec.num_pipe_per_mec = 4; 1361 adev->gfx.mec.num_queue_per_pipe = 8; 1362 break; 1363 } 1364 1365 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1366 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1367 amdgpu_sriov_is_pp_one_vf(adev)) 1368 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1369 1370 /* EOP Event */ 1371 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1372 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1373 &adev->gfx.eop_irq); 1374 if (r) 1375 return r; 1376 1377 /* Privileged reg */ 1378 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1379 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1380 &adev->gfx.priv_reg_irq); 1381 if (r) 1382 return r; 1383 1384 /* Privileged inst */ 1385 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1386 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1387 &adev->gfx.priv_inst_irq); 1388 if (r) 1389 return r; 1390 1391 /* FED error */ 1392 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1393 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1394 &adev->gfx.rlc_gc_fed_irq); 1395 if (r) 1396 return r; 1397 1398 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1399 1400 if (adev->gfx.imu.funcs) { 1401 if (adev->gfx.imu.funcs->init_microcode) { 1402 r = adev->gfx.imu.funcs->init_microcode(adev); 1403 if (r) 1404 DRM_ERROR("Failed to load imu firmware!\n"); 1405 } 1406 } 1407 1408 gfx_v11_0_me_init(adev); 1409 1410 r = gfx_v11_0_rlc_init(adev); 1411 if (r) { 1412 DRM_ERROR("Failed to init rlc BOs!\n"); 1413 return r; 1414 } 1415 1416 r = gfx_v11_0_mec_init(adev); 1417 if (r) { 1418 DRM_ERROR("Failed to init MEC BOs!\n"); 1419 return r; 1420 } 1421 1422 /* set up the gfx ring */ 1423 for (i = 0; i < adev->gfx.me.num_me; i++) { 1424 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1425 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1426 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1427 continue; 1428 1429 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1430 i, k, j); 1431 if (r) 1432 return r; 1433 ring_id++; 1434 } 1435 } 1436 } 1437 1438 ring_id = 0; 1439 /* set up the compute queues - allocate horizontally across pipes */ 1440 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1441 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1442 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1443 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1444 k, j)) 1445 continue; 1446 1447 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1448 i, k, j); 1449 if (r) 1450 return r; 1451 1452 ring_id++; 1453 } 1454 } 1455 } 1456 1457 if (!adev->enable_mes_kiq) { 1458 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1459 if (r) { 1460 DRM_ERROR("Failed to init KIQ BOs!\n"); 1461 return r; 1462 } 1463 1464 kiq = &adev->gfx.kiq[0]; 1465 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 1466 if (r) 1467 return r; 1468 } 1469 1470 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1471 if (r) 1472 return r; 1473 1474 /* allocate visible FB for rlc auto-loading fw */ 1475 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1476 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1477 if (r) 1478 return r; 1479 } 1480 1481 r = gfx_v11_0_gpu_early_init(adev); 1482 if (r) 1483 return r; 1484 1485 if (amdgpu_gfx_ras_sw_init(adev)) { 1486 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1487 return -EINVAL; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1494 { 1495 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1496 &adev->gfx.pfp.pfp_fw_gpu_addr, 1497 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1498 1499 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1500 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1501 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1502 } 1503 1504 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1505 { 1506 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1507 &adev->gfx.me.me_fw_gpu_addr, 1508 (void **)&adev->gfx.me.me_fw_ptr); 1509 1510 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1511 &adev->gfx.me.me_fw_data_gpu_addr, 1512 (void **)&adev->gfx.me.me_fw_data_ptr); 1513 } 1514 1515 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1516 { 1517 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1518 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1519 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1520 } 1521 1522 static int gfx_v11_0_sw_fini(void *handle) 1523 { 1524 int i; 1525 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1526 1527 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1528 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1529 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1530 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1531 1532 amdgpu_gfx_mqd_sw_fini(adev, 0); 1533 1534 if (!adev->enable_mes_kiq) { 1535 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1536 amdgpu_gfx_kiq_fini(adev, 0); 1537 } 1538 1539 gfx_v11_0_pfp_fini(adev); 1540 gfx_v11_0_me_fini(adev); 1541 gfx_v11_0_rlc_fini(adev); 1542 gfx_v11_0_mec_fini(adev); 1543 1544 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1545 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1546 1547 gfx_v11_0_free_microcode(adev); 1548 1549 return 0; 1550 } 1551 1552 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1553 u32 sh_num, u32 instance, int xcc_id) 1554 { 1555 u32 data; 1556 1557 if (instance == 0xffffffff) 1558 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1559 INSTANCE_BROADCAST_WRITES, 1); 1560 else 1561 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1562 instance); 1563 1564 if (se_num == 0xffffffff) 1565 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1566 1); 1567 else 1568 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1569 1570 if (sh_num == 0xffffffff) 1571 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1572 1); 1573 else 1574 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1575 1576 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1577 } 1578 1579 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1580 { 1581 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1582 1583 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1584 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1585 CC_GC_SA_UNIT_DISABLE, 1586 SA_DISABLE); 1587 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1588 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1589 GC_USER_SA_UNIT_DISABLE, 1590 SA_DISABLE); 1591 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1592 adev->gfx.config.max_shader_engines); 1593 1594 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1595 } 1596 1597 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1598 { 1599 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1600 u32 rb_mask; 1601 1602 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1603 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1604 CC_RB_BACKEND_DISABLE, 1605 BACKEND_DISABLE); 1606 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1607 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1608 GC_USER_RB_BACKEND_DISABLE, 1609 BACKEND_DISABLE); 1610 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1611 adev->gfx.config.max_shader_engines); 1612 1613 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1614 } 1615 1616 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1617 { 1618 u32 rb_bitmap_width_per_sa; 1619 u32 max_sa; 1620 u32 active_sa_bitmap; 1621 u32 global_active_rb_bitmap; 1622 u32 active_rb_bitmap = 0; 1623 u32 i; 1624 1625 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1626 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1627 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1628 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1629 1630 /* generate active rb bitmap according to active sa bitmap */ 1631 max_sa = adev->gfx.config.max_shader_engines * 1632 adev->gfx.config.max_sh_per_se; 1633 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1634 adev->gfx.config.max_sh_per_se; 1635 for (i = 0; i < max_sa; i++) { 1636 if (active_sa_bitmap & (1 << i)) 1637 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1638 } 1639 1640 active_rb_bitmap |= global_active_rb_bitmap; 1641 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1642 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1643 } 1644 1645 #define DEFAULT_SH_MEM_BASES (0x6000) 1646 #define LDS_APP_BASE 0x1 1647 #define SCRATCH_APP_BASE 0x2 1648 1649 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1650 { 1651 int i; 1652 uint32_t sh_mem_bases; 1653 uint32_t data; 1654 1655 /* 1656 * Configure apertures: 1657 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1658 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1659 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1660 */ 1661 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1662 SCRATCH_APP_BASE; 1663 1664 mutex_lock(&adev->srbm_mutex); 1665 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1666 soc21_grbm_select(adev, 0, 0, 0, i); 1667 /* CP and shaders */ 1668 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1669 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1670 1671 /* Enable trap for each kfd vmid. */ 1672 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1673 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1674 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1675 } 1676 soc21_grbm_select(adev, 0, 0, 0, 0); 1677 mutex_unlock(&adev->srbm_mutex); 1678 1679 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1680 acccess. These should be enabled by FW for target VMIDs. */ 1681 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1682 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1683 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1684 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1685 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1686 } 1687 } 1688 1689 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1690 { 1691 int vmid; 1692 1693 /* 1694 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1695 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1696 * the driver can enable them for graphics. VMID0 should maintain 1697 * access so that HWS firmware can save/restore entries. 1698 */ 1699 for (vmid = 1; vmid < 16; vmid++) { 1700 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1701 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1702 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1703 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1704 } 1705 } 1706 1707 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1708 { 1709 /* TODO: harvest feature to be added later. */ 1710 } 1711 1712 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1713 { 1714 /* TCCs are global (not instanced). */ 1715 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1716 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1717 1718 adev->gfx.config.tcc_disabled_mask = 1719 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1720 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1721 } 1722 1723 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1724 { 1725 u32 tmp; 1726 int i; 1727 1728 if (!amdgpu_sriov_vf(adev)) 1729 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1730 1731 gfx_v11_0_setup_rb(adev); 1732 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1733 gfx_v11_0_get_tcc_info(adev); 1734 adev->gfx.config.pa_sc_tile_steering_override = 0; 1735 1736 /* Set whether texture coordinate truncation is conformant. */ 1737 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1738 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1739 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1740 1741 /* XXX SH_MEM regs */ 1742 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1743 mutex_lock(&adev->srbm_mutex); 1744 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1745 soc21_grbm_select(adev, 0, 0, 0, i); 1746 /* CP and shaders */ 1747 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1748 if (i != 0) { 1749 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1750 (adev->gmc.private_aperture_start >> 48)); 1751 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1752 (adev->gmc.shared_aperture_start >> 48)); 1753 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1754 } 1755 } 1756 soc21_grbm_select(adev, 0, 0, 0, 0); 1757 1758 mutex_unlock(&adev->srbm_mutex); 1759 1760 gfx_v11_0_init_compute_vmid(adev); 1761 gfx_v11_0_init_gds_vmid(adev); 1762 } 1763 1764 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1765 bool enable) 1766 { 1767 u32 tmp; 1768 1769 if (amdgpu_sriov_vf(adev)) 1770 return; 1771 1772 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1773 1774 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1775 enable ? 1 : 0); 1776 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1777 enable ? 1 : 0); 1778 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1779 enable ? 1 : 0); 1780 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1781 enable ? 1 : 0); 1782 1783 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1784 } 1785 1786 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1787 { 1788 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1789 1790 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1791 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1792 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1793 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1794 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1795 1796 return 0; 1797 } 1798 1799 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1800 { 1801 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1802 1803 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1804 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1805 } 1806 1807 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1808 { 1809 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1810 udelay(50); 1811 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1812 udelay(50); 1813 } 1814 1815 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1816 bool enable) 1817 { 1818 uint32_t rlc_pg_cntl; 1819 1820 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1821 1822 if (!enable) { 1823 /* RLC_PG_CNTL[23] = 0 (default) 1824 * RLC will wait for handshake acks with SMU 1825 * GFXOFF will be enabled 1826 * RLC_PG_CNTL[23] = 1 1827 * RLC will not issue any message to SMU 1828 * hence no handshake between SMU & RLC 1829 * GFXOFF will be disabled 1830 */ 1831 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1832 } else 1833 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1834 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1835 } 1836 1837 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1838 { 1839 /* TODO: enable rlc & smu handshake until smu 1840 * and gfxoff feature works as expected */ 1841 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1842 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1843 1844 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1845 udelay(50); 1846 } 1847 1848 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1849 { 1850 uint32_t tmp; 1851 1852 /* enable Save Restore Machine */ 1853 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1854 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1855 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1856 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1857 } 1858 1859 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1860 { 1861 const struct rlc_firmware_header_v2_0 *hdr; 1862 const __le32 *fw_data; 1863 unsigned i, fw_size; 1864 1865 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1866 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1867 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1868 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1869 1870 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1871 RLCG_UCODE_LOADING_START_ADDRESS); 1872 1873 for (i = 0; i < fw_size; i++) 1874 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1875 le32_to_cpup(fw_data++)); 1876 1877 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1878 } 1879 1880 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1881 { 1882 const struct rlc_firmware_header_v2_2 *hdr; 1883 const __le32 *fw_data; 1884 unsigned i, fw_size; 1885 u32 tmp; 1886 1887 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1888 1889 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1890 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1891 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1892 1893 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1894 1895 for (i = 0; i < fw_size; i++) { 1896 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1897 msleep(1); 1898 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1899 le32_to_cpup(fw_data++)); 1900 } 1901 1902 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1903 1904 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1905 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1906 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1907 1908 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1909 for (i = 0; i < fw_size; i++) { 1910 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1911 msleep(1); 1912 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1913 le32_to_cpup(fw_data++)); 1914 } 1915 1916 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1917 1918 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1919 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1920 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1921 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1922 } 1923 1924 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1925 { 1926 const struct rlc_firmware_header_v2_3 *hdr; 1927 const __le32 *fw_data; 1928 unsigned i, fw_size; 1929 u32 tmp; 1930 1931 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1932 1933 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1934 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1935 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1936 1937 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1938 1939 for (i = 0; i < fw_size; i++) { 1940 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1941 msleep(1); 1942 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1943 le32_to_cpup(fw_data++)); 1944 } 1945 1946 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1947 1948 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1949 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1950 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1951 1952 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1953 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1954 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1955 1956 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1957 1958 for (i = 0; i < fw_size; i++) { 1959 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1960 msleep(1); 1961 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1962 le32_to_cpup(fw_data++)); 1963 } 1964 1965 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1966 1967 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1968 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1969 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1970 } 1971 1972 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1973 { 1974 const struct rlc_firmware_header_v2_0 *hdr; 1975 uint16_t version_major; 1976 uint16_t version_minor; 1977 1978 if (!adev->gfx.rlc_fw) 1979 return -EINVAL; 1980 1981 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1982 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1983 1984 version_major = le16_to_cpu(hdr->header.header_version_major); 1985 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1986 1987 if (version_major == 2) { 1988 gfx_v11_0_load_rlcg_microcode(adev); 1989 if (amdgpu_dpm == 1) { 1990 if (version_minor >= 2) 1991 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1992 if (version_minor == 3) 1993 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1994 } 1995 1996 return 0; 1997 } 1998 1999 return -EINVAL; 2000 } 2001 2002 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2003 { 2004 int r; 2005 2006 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2007 gfx_v11_0_init_csb(adev); 2008 2009 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2010 gfx_v11_0_rlc_enable_srm(adev); 2011 } else { 2012 if (amdgpu_sriov_vf(adev)) { 2013 gfx_v11_0_init_csb(adev); 2014 return 0; 2015 } 2016 2017 adev->gfx.rlc.funcs->stop(adev); 2018 2019 /* disable CG */ 2020 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2021 2022 /* disable PG */ 2023 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2024 2025 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2026 /* legacy rlc firmware loading */ 2027 r = gfx_v11_0_rlc_load_microcode(adev); 2028 if (r) 2029 return r; 2030 } 2031 2032 gfx_v11_0_init_csb(adev); 2033 2034 adev->gfx.rlc.funcs->start(adev); 2035 } 2036 return 0; 2037 } 2038 2039 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2040 { 2041 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2042 uint32_t tmp; 2043 int i; 2044 2045 /* Trigger an invalidation of the L1 instruction caches */ 2046 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2047 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2048 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2049 2050 /* Wait for invalidation complete */ 2051 for (i = 0; i < usec_timeout; i++) { 2052 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2053 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2054 INVALIDATE_CACHE_COMPLETE)) 2055 break; 2056 udelay(1); 2057 } 2058 2059 if (i >= usec_timeout) { 2060 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2061 return -EINVAL; 2062 } 2063 2064 if (amdgpu_emu_mode == 1) 2065 adev->hdp.funcs->flush_hdp(adev, NULL); 2066 2067 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2068 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2069 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2070 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2071 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2072 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2073 2074 /* Program me ucode address into intruction cache address register */ 2075 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2076 lower_32_bits(addr) & 0xFFFFF000); 2077 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2078 upper_32_bits(addr)); 2079 2080 return 0; 2081 } 2082 2083 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2084 { 2085 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2086 uint32_t tmp; 2087 int i; 2088 2089 /* Trigger an invalidation of the L1 instruction caches */ 2090 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2091 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2092 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2093 2094 /* Wait for invalidation complete */ 2095 for (i = 0; i < usec_timeout; i++) { 2096 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2097 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2098 INVALIDATE_CACHE_COMPLETE)) 2099 break; 2100 udelay(1); 2101 } 2102 2103 if (i >= usec_timeout) { 2104 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2105 return -EINVAL; 2106 } 2107 2108 if (amdgpu_emu_mode == 1) 2109 adev->hdp.funcs->flush_hdp(adev, NULL); 2110 2111 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2112 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2113 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2114 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2115 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2116 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2117 2118 /* Program pfp ucode address into intruction cache address register */ 2119 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2120 lower_32_bits(addr) & 0xFFFFF000); 2121 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2122 upper_32_bits(addr)); 2123 2124 return 0; 2125 } 2126 2127 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2128 { 2129 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2130 uint32_t tmp; 2131 int i; 2132 2133 /* Trigger an invalidation of the L1 instruction caches */ 2134 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2135 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2136 2137 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2138 2139 /* Wait for invalidation complete */ 2140 for (i = 0; i < usec_timeout; i++) { 2141 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2142 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2143 INVALIDATE_CACHE_COMPLETE)) 2144 break; 2145 udelay(1); 2146 } 2147 2148 if (i >= usec_timeout) { 2149 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2150 return -EINVAL; 2151 } 2152 2153 if (amdgpu_emu_mode == 1) 2154 adev->hdp.funcs->flush_hdp(adev, NULL); 2155 2156 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2157 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2158 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2159 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2160 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2161 2162 /* Program mec1 ucode address into intruction cache address register */ 2163 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2164 lower_32_bits(addr) & 0xFFFFF000); 2165 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2166 upper_32_bits(addr)); 2167 2168 return 0; 2169 } 2170 2171 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2172 { 2173 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2174 uint32_t tmp; 2175 unsigned i, pipe_id; 2176 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2177 2178 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2179 adev->gfx.pfp_fw->data; 2180 2181 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2182 lower_32_bits(addr)); 2183 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2184 upper_32_bits(addr)); 2185 2186 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2187 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2188 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2189 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2190 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2191 2192 /* 2193 * Programming any of the CP_PFP_IC_BASE registers 2194 * forces invalidation of the ME L1 I$. Wait for the 2195 * invalidation complete 2196 */ 2197 for (i = 0; i < usec_timeout; i++) { 2198 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2199 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2200 INVALIDATE_CACHE_COMPLETE)) 2201 break; 2202 udelay(1); 2203 } 2204 2205 if (i >= usec_timeout) { 2206 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2207 return -EINVAL; 2208 } 2209 2210 /* Prime the L1 instruction caches */ 2211 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2212 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2213 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2214 /* Waiting for cache primed*/ 2215 for (i = 0; i < usec_timeout; i++) { 2216 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2217 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2218 ICACHE_PRIMED)) 2219 break; 2220 udelay(1); 2221 } 2222 2223 if (i >= usec_timeout) { 2224 dev_err(adev->dev, "failed to prime instruction cache\n"); 2225 return -EINVAL; 2226 } 2227 2228 mutex_lock(&adev->srbm_mutex); 2229 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2230 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2231 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2232 (pfp_hdr->ucode_start_addr_hi << 30) | 2233 (pfp_hdr->ucode_start_addr_lo >> 2)); 2234 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2235 pfp_hdr->ucode_start_addr_hi >> 2); 2236 2237 /* 2238 * Program CP_ME_CNTL to reset given PIPE to take 2239 * effect of CP_PFP_PRGRM_CNTR_START. 2240 */ 2241 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2242 if (pipe_id == 0) 2243 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2244 PFP_PIPE0_RESET, 1); 2245 else 2246 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2247 PFP_PIPE1_RESET, 1); 2248 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2249 2250 /* Clear pfp pipe0 reset bit. */ 2251 if (pipe_id == 0) 2252 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2253 PFP_PIPE0_RESET, 0); 2254 else 2255 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2256 PFP_PIPE1_RESET, 0); 2257 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2258 2259 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2260 lower_32_bits(addr2)); 2261 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2262 upper_32_bits(addr2)); 2263 } 2264 soc21_grbm_select(adev, 0, 0, 0, 0); 2265 mutex_unlock(&adev->srbm_mutex); 2266 2267 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2268 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2269 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2270 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2271 2272 /* Invalidate the data caches */ 2273 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2274 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2275 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2276 2277 for (i = 0; i < usec_timeout; i++) { 2278 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2279 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2280 INVALIDATE_DCACHE_COMPLETE)) 2281 break; 2282 udelay(1); 2283 } 2284 2285 if (i >= usec_timeout) { 2286 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2287 return -EINVAL; 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2294 { 2295 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2296 uint32_t tmp; 2297 unsigned i, pipe_id; 2298 const struct gfx_firmware_header_v2_0 *me_hdr; 2299 2300 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2301 adev->gfx.me_fw->data; 2302 2303 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2304 lower_32_bits(addr)); 2305 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2306 upper_32_bits(addr)); 2307 2308 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2309 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2310 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2311 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2312 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2313 2314 /* 2315 * Programming any of the CP_ME_IC_BASE registers 2316 * forces invalidation of the ME L1 I$. Wait for the 2317 * invalidation complete 2318 */ 2319 for (i = 0; i < usec_timeout; i++) { 2320 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2321 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2322 INVALIDATE_CACHE_COMPLETE)) 2323 break; 2324 udelay(1); 2325 } 2326 2327 if (i >= usec_timeout) { 2328 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2329 return -EINVAL; 2330 } 2331 2332 /* Prime the instruction caches */ 2333 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2334 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2335 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2336 2337 /* Waiting for instruction cache primed*/ 2338 for (i = 0; i < usec_timeout; i++) { 2339 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2340 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2341 ICACHE_PRIMED)) 2342 break; 2343 udelay(1); 2344 } 2345 2346 if (i >= usec_timeout) { 2347 dev_err(adev->dev, "failed to prime instruction cache\n"); 2348 return -EINVAL; 2349 } 2350 2351 mutex_lock(&adev->srbm_mutex); 2352 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2353 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2354 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2355 (me_hdr->ucode_start_addr_hi << 30) | 2356 (me_hdr->ucode_start_addr_lo >> 2) ); 2357 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2358 me_hdr->ucode_start_addr_hi>>2); 2359 2360 /* 2361 * Program CP_ME_CNTL to reset given PIPE to take 2362 * effect of CP_PFP_PRGRM_CNTR_START. 2363 */ 2364 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2365 if (pipe_id == 0) 2366 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2367 ME_PIPE0_RESET, 1); 2368 else 2369 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2370 ME_PIPE1_RESET, 1); 2371 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2372 2373 /* Clear pfp pipe0 reset bit. */ 2374 if (pipe_id == 0) 2375 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2376 ME_PIPE0_RESET, 0); 2377 else 2378 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2379 ME_PIPE1_RESET, 0); 2380 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2381 2382 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2383 lower_32_bits(addr2)); 2384 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2385 upper_32_bits(addr2)); 2386 } 2387 soc21_grbm_select(adev, 0, 0, 0, 0); 2388 mutex_unlock(&adev->srbm_mutex); 2389 2390 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2391 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2392 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2393 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2394 2395 /* Invalidate the data caches */ 2396 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2397 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2398 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2399 2400 for (i = 0; i < usec_timeout; i++) { 2401 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2402 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2403 INVALIDATE_DCACHE_COMPLETE)) 2404 break; 2405 udelay(1); 2406 } 2407 2408 if (i >= usec_timeout) { 2409 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2410 return -EINVAL; 2411 } 2412 2413 return 0; 2414 } 2415 2416 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2417 { 2418 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2419 uint32_t tmp; 2420 unsigned i; 2421 const struct gfx_firmware_header_v2_0 *mec_hdr; 2422 2423 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2424 adev->gfx.mec_fw->data; 2425 2426 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2427 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2428 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2429 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2430 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2431 2432 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2433 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2434 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2435 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2436 2437 mutex_lock(&adev->srbm_mutex); 2438 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2439 soc21_grbm_select(adev, 1, i, 0, 0); 2440 2441 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2442 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2443 upper_32_bits(addr2)); 2444 2445 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2446 mec_hdr->ucode_start_addr_lo >> 2 | 2447 mec_hdr->ucode_start_addr_hi << 30); 2448 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2449 mec_hdr->ucode_start_addr_hi >> 2); 2450 2451 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2452 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2453 upper_32_bits(addr)); 2454 } 2455 mutex_unlock(&adev->srbm_mutex); 2456 soc21_grbm_select(adev, 0, 0, 0, 0); 2457 2458 /* Trigger an invalidation of the L1 instruction caches */ 2459 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2460 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2461 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2462 2463 /* Wait for invalidation complete */ 2464 for (i = 0; i < usec_timeout; i++) { 2465 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2466 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2467 INVALIDATE_DCACHE_COMPLETE)) 2468 break; 2469 udelay(1); 2470 } 2471 2472 if (i >= usec_timeout) { 2473 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2474 return -EINVAL; 2475 } 2476 2477 /* Trigger an invalidation of the L1 instruction caches */ 2478 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2479 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2480 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2481 2482 /* Wait for invalidation complete */ 2483 for (i = 0; i < usec_timeout; i++) { 2484 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2485 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2486 INVALIDATE_CACHE_COMPLETE)) 2487 break; 2488 udelay(1); 2489 } 2490 2491 if (i >= usec_timeout) { 2492 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2493 return -EINVAL; 2494 } 2495 2496 return 0; 2497 } 2498 2499 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2500 { 2501 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2502 const struct gfx_firmware_header_v2_0 *me_hdr; 2503 const struct gfx_firmware_header_v2_0 *mec_hdr; 2504 uint32_t pipe_id, tmp; 2505 2506 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2507 adev->gfx.mec_fw->data; 2508 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2509 adev->gfx.me_fw->data; 2510 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2511 adev->gfx.pfp_fw->data; 2512 2513 /* config pfp program start addr */ 2514 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2515 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2516 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2517 (pfp_hdr->ucode_start_addr_hi << 30) | 2518 (pfp_hdr->ucode_start_addr_lo >> 2)); 2519 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2520 pfp_hdr->ucode_start_addr_hi >> 2); 2521 } 2522 soc21_grbm_select(adev, 0, 0, 0, 0); 2523 2524 /* reset pfp pipe */ 2525 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2526 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2527 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2528 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2529 2530 /* clear pfp pipe reset */ 2531 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2532 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2533 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2534 2535 /* config me program start addr */ 2536 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2537 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2538 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2539 (me_hdr->ucode_start_addr_hi << 30) | 2540 (me_hdr->ucode_start_addr_lo >> 2) ); 2541 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2542 me_hdr->ucode_start_addr_hi>>2); 2543 } 2544 soc21_grbm_select(adev, 0, 0, 0, 0); 2545 2546 /* reset me pipe */ 2547 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2548 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2549 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2550 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2551 2552 /* clear me pipe reset */ 2553 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2554 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2555 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2556 2557 /* config mec program start addr */ 2558 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2559 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2560 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2561 mec_hdr->ucode_start_addr_lo >> 2 | 2562 mec_hdr->ucode_start_addr_hi << 30); 2563 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2564 mec_hdr->ucode_start_addr_hi >> 2); 2565 } 2566 soc21_grbm_select(adev, 0, 0, 0, 0); 2567 2568 /* reset mec pipe */ 2569 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2570 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2571 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2572 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2573 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2574 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2575 2576 /* clear mec pipe reset */ 2577 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2578 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2579 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2580 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2581 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2582 } 2583 2584 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2585 { 2586 uint32_t cp_status; 2587 uint32_t bootload_status; 2588 int i, r; 2589 uint64_t addr, addr2; 2590 2591 for (i = 0; i < adev->usec_timeout; i++) { 2592 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2593 2594 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2595 IP_VERSION(11, 0, 1) || 2596 amdgpu_ip_version(adev, GC_HWIP, 0) == 2597 IP_VERSION(11, 0, 4) || 2598 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0)) 2599 bootload_status = RREG32_SOC15(GC, 0, 2600 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2601 else 2602 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2603 2604 if ((cp_status == 0) && 2605 (REG_GET_FIELD(bootload_status, 2606 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2607 break; 2608 } 2609 udelay(1); 2610 } 2611 2612 if (i >= adev->usec_timeout) { 2613 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2614 return -ETIMEDOUT; 2615 } 2616 2617 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2618 if (adev->gfx.rs64_enable) { 2619 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2620 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2621 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2622 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2623 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2624 if (r) 2625 return r; 2626 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2627 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2628 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2629 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2630 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2631 if (r) 2632 return r; 2633 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2634 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2635 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2636 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2637 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2638 if (r) 2639 return r; 2640 } else { 2641 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2642 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2643 r = gfx_v11_0_config_me_cache(adev, addr); 2644 if (r) 2645 return r; 2646 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2647 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2648 r = gfx_v11_0_config_pfp_cache(adev, addr); 2649 if (r) 2650 return r; 2651 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2652 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2653 r = gfx_v11_0_config_mec_cache(adev, addr); 2654 if (r) 2655 return r; 2656 } 2657 } 2658 2659 return 0; 2660 } 2661 2662 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2663 { 2664 int i; 2665 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2666 2667 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2668 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2669 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2670 2671 for (i = 0; i < adev->usec_timeout; i++) { 2672 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2673 break; 2674 udelay(1); 2675 } 2676 2677 if (i >= adev->usec_timeout) 2678 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2679 2680 return 0; 2681 } 2682 2683 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2684 { 2685 int r; 2686 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2687 const __le32 *fw_data; 2688 unsigned i, fw_size; 2689 2690 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2691 adev->gfx.pfp_fw->data; 2692 2693 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2694 2695 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2696 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2697 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2698 2699 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2700 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2701 &adev->gfx.pfp.pfp_fw_obj, 2702 &adev->gfx.pfp.pfp_fw_gpu_addr, 2703 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2704 if (r) { 2705 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2706 gfx_v11_0_pfp_fini(adev); 2707 return r; 2708 } 2709 2710 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2711 2712 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2713 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2714 2715 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2716 2717 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2718 2719 for (i = 0; i < pfp_hdr->jt_size; i++) 2720 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2721 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2722 2723 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2724 2725 return 0; 2726 } 2727 2728 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2729 { 2730 int r; 2731 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2732 const __le32 *fw_ucode, *fw_data; 2733 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2734 uint32_t tmp; 2735 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2736 2737 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2738 adev->gfx.pfp_fw->data; 2739 2740 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2741 2742 /* instruction */ 2743 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2744 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2745 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2746 /* data */ 2747 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2748 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2749 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2750 2751 /* 64kb align */ 2752 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2753 64 * 1024, 2754 AMDGPU_GEM_DOMAIN_VRAM | 2755 AMDGPU_GEM_DOMAIN_GTT, 2756 &adev->gfx.pfp.pfp_fw_obj, 2757 &adev->gfx.pfp.pfp_fw_gpu_addr, 2758 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2759 if (r) { 2760 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2761 gfx_v11_0_pfp_fini(adev); 2762 return r; 2763 } 2764 2765 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2766 64 * 1024, 2767 AMDGPU_GEM_DOMAIN_VRAM | 2768 AMDGPU_GEM_DOMAIN_GTT, 2769 &adev->gfx.pfp.pfp_fw_data_obj, 2770 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2771 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2772 if (r) { 2773 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2774 gfx_v11_0_pfp_fini(adev); 2775 return r; 2776 } 2777 2778 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2779 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2780 2781 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2782 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2783 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2784 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2785 2786 if (amdgpu_emu_mode == 1) 2787 adev->hdp.funcs->flush_hdp(adev, NULL); 2788 2789 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2790 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2791 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2792 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2793 2794 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2795 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2796 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2797 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2798 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2799 2800 /* 2801 * Programming any of the CP_PFP_IC_BASE registers 2802 * forces invalidation of the ME L1 I$. Wait for the 2803 * invalidation complete 2804 */ 2805 for (i = 0; i < usec_timeout; i++) { 2806 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2807 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2808 INVALIDATE_CACHE_COMPLETE)) 2809 break; 2810 udelay(1); 2811 } 2812 2813 if (i >= usec_timeout) { 2814 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2815 return -EINVAL; 2816 } 2817 2818 /* Prime the L1 instruction caches */ 2819 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2820 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2821 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2822 /* Waiting for cache primed*/ 2823 for (i = 0; i < usec_timeout; i++) { 2824 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2825 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2826 ICACHE_PRIMED)) 2827 break; 2828 udelay(1); 2829 } 2830 2831 if (i >= usec_timeout) { 2832 dev_err(adev->dev, "failed to prime instruction cache\n"); 2833 return -EINVAL; 2834 } 2835 2836 mutex_lock(&adev->srbm_mutex); 2837 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2838 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2839 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2840 (pfp_hdr->ucode_start_addr_hi << 30) | 2841 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2842 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2843 pfp_hdr->ucode_start_addr_hi>>2); 2844 2845 /* 2846 * Program CP_ME_CNTL to reset given PIPE to take 2847 * effect of CP_PFP_PRGRM_CNTR_START. 2848 */ 2849 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2850 if (pipe_id == 0) 2851 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2852 PFP_PIPE0_RESET, 1); 2853 else 2854 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2855 PFP_PIPE1_RESET, 1); 2856 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2857 2858 /* Clear pfp pipe0 reset bit. */ 2859 if (pipe_id == 0) 2860 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2861 PFP_PIPE0_RESET, 0); 2862 else 2863 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2864 PFP_PIPE1_RESET, 0); 2865 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2866 2867 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2868 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2869 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2870 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2871 } 2872 soc21_grbm_select(adev, 0, 0, 0, 0); 2873 mutex_unlock(&adev->srbm_mutex); 2874 2875 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2876 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2877 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2878 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2879 2880 /* Invalidate the data caches */ 2881 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2882 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2883 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2884 2885 for (i = 0; i < usec_timeout; i++) { 2886 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2887 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2888 INVALIDATE_DCACHE_COMPLETE)) 2889 break; 2890 udelay(1); 2891 } 2892 2893 if (i >= usec_timeout) { 2894 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2895 return -EINVAL; 2896 } 2897 2898 return 0; 2899 } 2900 2901 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2902 { 2903 int r; 2904 const struct gfx_firmware_header_v1_0 *me_hdr; 2905 const __le32 *fw_data; 2906 unsigned i, fw_size; 2907 2908 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2909 adev->gfx.me_fw->data; 2910 2911 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2912 2913 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2914 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2915 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2916 2917 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2918 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2919 &adev->gfx.me.me_fw_obj, 2920 &adev->gfx.me.me_fw_gpu_addr, 2921 (void **)&adev->gfx.me.me_fw_ptr); 2922 if (r) { 2923 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2924 gfx_v11_0_me_fini(adev); 2925 return r; 2926 } 2927 2928 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2929 2930 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2931 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2932 2933 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2934 2935 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2936 2937 for (i = 0; i < me_hdr->jt_size; i++) 2938 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2939 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2940 2941 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2942 2943 return 0; 2944 } 2945 2946 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2947 { 2948 int r; 2949 const struct gfx_firmware_header_v2_0 *me_hdr; 2950 const __le32 *fw_ucode, *fw_data; 2951 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2952 uint32_t tmp; 2953 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2954 2955 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2956 adev->gfx.me_fw->data; 2957 2958 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2959 2960 /* instruction */ 2961 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2962 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2963 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2964 /* data */ 2965 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2966 le32_to_cpu(me_hdr->data_offset_bytes)); 2967 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2968 2969 /* 64kb align*/ 2970 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2971 64 * 1024, 2972 AMDGPU_GEM_DOMAIN_VRAM | 2973 AMDGPU_GEM_DOMAIN_GTT, 2974 &adev->gfx.me.me_fw_obj, 2975 &adev->gfx.me.me_fw_gpu_addr, 2976 (void **)&adev->gfx.me.me_fw_ptr); 2977 if (r) { 2978 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2979 gfx_v11_0_me_fini(adev); 2980 return r; 2981 } 2982 2983 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2984 64 * 1024, 2985 AMDGPU_GEM_DOMAIN_VRAM | 2986 AMDGPU_GEM_DOMAIN_GTT, 2987 &adev->gfx.me.me_fw_data_obj, 2988 &adev->gfx.me.me_fw_data_gpu_addr, 2989 (void **)&adev->gfx.me.me_fw_data_ptr); 2990 if (r) { 2991 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2992 gfx_v11_0_pfp_fini(adev); 2993 return r; 2994 } 2995 2996 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2997 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2998 2999 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3000 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3001 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3002 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3003 3004 if (amdgpu_emu_mode == 1) 3005 adev->hdp.funcs->flush_hdp(adev, NULL); 3006 3007 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3008 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3009 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3010 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3011 3012 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3013 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3014 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3015 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3016 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3017 3018 /* 3019 * Programming any of the CP_ME_IC_BASE registers 3020 * forces invalidation of the ME L1 I$. Wait for the 3021 * invalidation complete 3022 */ 3023 for (i = 0; i < usec_timeout; i++) { 3024 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3025 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3026 INVALIDATE_CACHE_COMPLETE)) 3027 break; 3028 udelay(1); 3029 } 3030 3031 if (i >= usec_timeout) { 3032 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3033 return -EINVAL; 3034 } 3035 3036 /* Prime the instruction caches */ 3037 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3038 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3039 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3040 3041 /* Waiting for instruction cache primed*/ 3042 for (i = 0; i < usec_timeout; i++) { 3043 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3044 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3045 ICACHE_PRIMED)) 3046 break; 3047 udelay(1); 3048 } 3049 3050 if (i >= usec_timeout) { 3051 dev_err(adev->dev, "failed to prime instruction cache\n"); 3052 return -EINVAL; 3053 } 3054 3055 mutex_lock(&adev->srbm_mutex); 3056 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3057 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3058 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3059 (me_hdr->ucode_start_addr_hi << 30) | 3060 (me_hdr->ucode_start_addr_lo >> 2) ); 3061 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3062 me_hdr->ucode_start_addr_hi>>2); 3063 3064 /* 3065 * Program CP_ME_CNTL to reset given PIPE to take 3066 * effect of CP_PFP_PRGRM_CNTR_START. 3067 */ 3068 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3069 if (pipe_id == 0) 3070 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3071 ME_PIPE0_RESET, 1); 3072 else 3073 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3074 ME_PIPE1_RESET, 1); 3075 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3076 3077 /* Clear pfp pipe0 reset bit. */ 3078 if (pipe_id == 0) 3079 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3080 ME_PIPE0_RESET, 0); 3081 else 3082 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3083 ME_PIPE1_RESET, 0); 3084 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3085 3086 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3087 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3088 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3089 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3090 } 3091 soc21_grbm_select(adev, 0, 0, 0, 0); 3092 mutex_unlock(&adev->srbm_mutex); 3093 3094 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3095 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3096 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3097 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3098 3099 /* Invalidate the data caches */ 3100 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3101 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3102 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3103 3104 for (i = 0; i < usec_timeout; i++) { 3105 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3106 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3107 INVALIDATE_DCACHE_COMPLETE)) 3108 break; 3109 udelay(1); 3110 } 3111 3112 if (i >= usec_timeout) { 3113 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3114 return -EINVAL; 3115 } 3116 3117 return 0; 3118 } 3119 3120 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3121 { 3122 int r; 3123 3124 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3125 return -EINVAL; 3126 3127 gfx_v11_0_cp_gfx_enable(adev, false); 3128 3129 if (adev->gfx.rs64_enable) 3130 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3131 else 3132 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3133 if (r) { 3134 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3135 return r; 3136 } 3137 3138 if (adev->gfx.rs64_enable) 3139 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3140 else 3141 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3142 if (r) { 3143 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3144 return r; 3145 } 3146 3147 return 0; 3148 } 3149 3150 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3151 { 3152 struct amdgpu_ring *ring; 3153 const struct cs_section_def *sect = NULL; 3154 const struct cs_extent_def *ext = NULL; 3155 int r, i; 3156 int ctx_reg_offset; 3157 3158 /* init the CP */ 3159 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3160 adev->gfx.config.max_hw_contexts - 1); 3161 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3162 3163 if (!amdgpu_async_gfx_ring) 3164 gfx_v11_0_cp_gfx_enable(adev, true); 3165 3166 ring = &adev->gfx.gfx_ring[0]; 3167 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3168 if (r) { 3169 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3170 return r; 3171 } 3172 3173 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3174 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3175 3176 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3177 amdgpu_ring_write(ring, 0x80000000); 3178 amdgpu_ring_write(ring, 0x80000000); 3179 3180 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3181 for (ext = sect->section; ext->extent != NULL; ++ext) { 3182 if (sect->id == SECT_CONTEXT) { 3183 amdgpu_ring_write(ring, 3184 PACKET3(PACKET3_SET_CONTEXT_REG, 3185 ext->reg_count)); 3186 amdgpu_ring_write(ring, ext->reg_index - 3187 PACKET3_SET_CONTEXT_REG_START); 3188 for (i = 0; i < ext->reg_count; i++) 3189 amdgpu_ring_write(ring, ext->extent[i]); 3190 } 3191 } 3192 } 3193 3194 ctx_reg_offset = 3195 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3196 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3197 amdgpu_ring_write(ring, ctx_reg_offset); 3198 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3199 3200 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3201 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3202 3203 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3204 amdgpu_ring_write(ring, 0); 3205 3206 amdgpu_ring_commit(ring); 3207 3208 /* submit cs packet to copy state 0 to next available state */ 3209 if (adev->gfx.num_gfx_rings > 1) { 3210 /* maximum supported gfx ring is 2 */ 3211 ring = &adev->gfx.gfx_ring[1]; 3212 r = amdgpu_ring_alloc(ring, 2); 3213 if (r) { 3214 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3215 return r; 3216 } 3217 3218 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3219 amdgpu_ring_write(ring, 0); 3220 3221 amdgpu_ring_commit(ring); 3222 } 3223 return 0; 3224 } 3225 3226 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3227 CP_PIPE_ID pipe) 3228 { 3229 u32 tmp; 3230 3231 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3232 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3233 3234 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3235 } 3236 3237 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3238 struct amdgpu_ring *ring) 3239 { 3240 u32 tmp; 3241 3242 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3243 if (ring->use_doorbell) { 3244 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3245 DOORBELL_OFFSET, ring->doorbell_index); 3246 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3247 DOORBELL_EN, 1); 3248 } else { 3249 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3250 DOORBELL_EN, 0); 3251 } 3252 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3253 3254 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3255 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3256 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3257 3258 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3259 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3260 } 3261 3262 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3263 { 3264 struct amdgpu_ring *ring; 3265 u32 tmp; 3266 u32 rb_bufsz; 3267 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3268 3269 /* Set the write pointer delay */ 3270 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3271 3272 /* set the RB to use vmid 0 */ 3273 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3274 3275 /* Init gfx ring 0 for pipe 0 */ 3276 mutex_lock(&adev->srbm_mutex); 3277 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3278 3279 /* Set ring buffer size */ 3280 ring = &adev->gfx.gfx_ring[0]; 3281 rb_bufsz = order_base_2(ring->ring_size / 8); 3282 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3283 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3284 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3285 3286 /* Initialize the ring buffer's write pointers */ 3287 ring->wptr = 0; 3288 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3289 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3290 3291 /* set the wb address wether it's enabled or not */ 3292 rptr_addr = ring->rptr_gpu_addr; 3293 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3294 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3295 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3296 3297 wptr_gpu_addr = ring->wptr_gpu_addr; 3298 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3299 lower_32_bits(wptr_gpu_addr)); 3300 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3301 upper_32_bits(wptr_gpu_addr)); 3302 3303 mdelay(1); 3304 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3305 3306 rb_addr = ring->gpu_addr >> 8; 3307 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3308 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3309 3310 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3311 3312 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3313 mutex_unlock(&adev->srbm_mutex); 3314 3315 /* Init gfx ring 1 for pipe 1 */ 3316 if (adev->gfx.num_gfx_rings > 1) { 3317 mutex_lock(&adev->srbm_mutex); 3318 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3319 /* maximum supported gfx ring is 2 */ 3320 ring = &adev->gfx.gfx_ring[1]; 3321 rb_bufsz = order_base_2(ring->ring_size / 8); 3322 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3323 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3324 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3325 /* Initialize the ring buffer's write pointers */ 3326 ring->wptr = 0; 3327 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3328 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3329 /* Set the wb address wether it's enabled or not */ 3330 rptr_addr = ring->rptr_gpu_addr; 3331 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3332 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3333 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3334 wptr_gpu_addr = ring->wptr_gpu_addr; 3335 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3336 lower_32_bits(wptr_gpu_addr)); 3337 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3338 upper_32_bits(wptr_gpu_addr)); 3339 3340 mdelay(1); 3341 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3342 3343 rb_addr = ring->gpu_addr >> 8; 3344 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3345 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3346 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3347 3348 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3349 mutex_unlock(&adev->srbm_mutex); 3350 } 3351 /* Switch to pipe 0 */ 3352 mutex_lock(&adev->srbm_mutex); 3353 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3354 mutex_unlock(&adev->srbm_mutex); 3355 3356 /* start the ring */ 3357 gfx_v11_0_cp_gfx_start(adev); 3358 3359 return 0; 3360 } 3361 3362 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3363 { 3364 u32 data; 3365 3366 if (adev->gfx.rs64_enable) { 3367 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3368 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3369 enable ? 0 : 1); 3370 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3371 enable ? 0 : 1); 3372 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3373 enable ? 0 : 1); 3374 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3375 enable ? 0 : 1); 3376 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3377 enable ? 0 : 1); 3378 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3379 enable ? 1 : 0); 3380 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3381 enable ? 1 : 0); 3382 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3383 enable ? 1 : 0); 3384 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3385 enable ? 1 : 0); 3386 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3387 enable ? 0 : 1); 3388 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3389 } else { 3390 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3391 3392 if (enable) { 3393 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3394 if (!adev->enable_mes_kiq) 3395 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3396 MEC_ME2_HALT, 0); 3397 } else { 3398 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3399 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3400 } 3401 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3402 } 3403 3404 udelay(50); 3405 } 3406 3407 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3408 { 3409 const struct gfx_firmware_header_v1_0 *mec_hdr; 3410 const __le32 *fw_data; 3411 unsigned i, fw_size; 3412 u32 *fw = NULL; 3413 int r; 3414 3415 if (!adev->gfx.mec_fw) 3416 return -EINVAL; 3417 3418 gfx_v11_0_cp_compute_enable(adev, false); 3419 3420 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3421 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3422 3423 fw_data = (const __le32 *) 3424 (adev->gfx.mec_fw->data + 3425 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3426 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3427 3428 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3430 &adev->gfx.mec.mec_fw_obj, 3431 &adev->gfx.mec.mec_fw_gpu_addr, 3432 (void **)&fw); 3433 if (r) { 3434 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3435 gfx_v11_0_mec_fini(adev); 3436 return r; 3437 } 3438 3439 memcpy(fw, fw_data, fw_size); 3440 3441 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3442 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3443 3444 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3445 3446 /* MEC1 */ 3447 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3448 3449 for (i = 0; i < mec_hdr->jt_size; i++) 3450 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3451 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3452 3453 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3454 3455 return 0; 3456 } 3457 3458 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3459 { 3460 const struct gfx_firmware_header_v2_0 *mec_hdr; 3461 const __le32 *fw_ucode, *fw_data; 3462 u32 tmp, fw_ucode_size, fw_data_size; 3463 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3464 u32 *fw_ucode_ptr, *fw_data_ptr; 3465 int r; 3466 3467 if (!adev->gfx.mec_fw) 3468 return -EINVAL; 3469 3470 gfx_v11_0_cp_compute_enable(adev, false); 3471 3472 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3473 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3474 3475 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3476 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3477 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3478 3479 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3480 le32_to_cpu(mec_hdr->data_offset_bytes)); 3481 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3482 3483 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3484 64 * 1024, 3485 AMDGPU_GEM_DOMAIN_VRAM | 3486 AMDGPU_GEM_DOMAIN_GTT, 3487 &adev->gfx.mec.mec_fw_obj, 3488 &adev->gfx.mec.mec_fw_gpu_addr, 3489 (void **)&fw_ucode_ptr); 3490 if (r) { 3491 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3492 gfx_v11_0_mec_fini(adev); 3493 return r; 3494 } 3495 3496 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3497 64 * 1024, 3498 AMDGPU_GEM_DOMAIN_VRAM | 3499 AMDGPU_GEM_DOMAIN_GTT, 3500 &adev->gfx.mec.mec_fw_data_obj, 3501 &adev->gfx.mec.mec_fw_data_gpu_addr, 3502 (void **)&fw_data_ptr); 3503 if (r) { 3504 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3505 gfx_v11_0_mec_fini(adev); 3506 return r; 3507 } 3508 3509 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3510 memcpy(fw_data_ptr, fw_data, fw_data_size); 3511 3512 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3513 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3514 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3515 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3516 3517 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3518 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3519 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3520 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3521 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3522 3523 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3524 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3525 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3526 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3527 3528 mutex_lock(&adev->srbm_mutex); 3529 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3530 soc21_grbm_select(adev, 1, i, 0, 0); 3531 3532 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3533 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3534 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3535 3536 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3537 mec_hdr->ucode_start_addr_lo >> 2 | 3538 mec_hdr->ucode_start_addr_hi << 30); 3539 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3540 mec_hdr->ucode_start_addr_hi >> 2); 3541 3542 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3543 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3544 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3545 } 3546 mutex_unlock(&adev->srbm_mutex); 3547 soc21_grbm_select(adev, 0, 0, 0, 0); 3548 3549 /* Trigger an invalidation of the L1 instruction caches */ 3550 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3551 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3552 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3553 3554 /* Wait for invalidation complete */ 3555 for (i = 0; i < usec_timeout; i++) { 3556 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3557 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3558 INVALIDATE_DCACHE_COMPLETE)) 3559 break; 3560 udelay(1); 3561 } 3562 3563 if (i >= usec_timeout) { 3564 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3565 return -EINVAL; 3566 } 3567 3568 /* Trigger an invalidation of the L1 instruction caches */ 3569 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3570 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3571 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3572 3573 /* Wait for invalidation complete */ 3574 for (i = 0; i < usec_timeout; i++) { 3575 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3576 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3577 INVALIDATE_CACHE_COMPLETE)) 3578 break; 3579 udelay(1); 3580 } 3581 3582 if (i >= usec_timeout) { 3583 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3584 return -EINVAL; 3585 } 3586 3587 return 0; 3588 } 3589 3590 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3591 { 3592 uint32_t tmp; 3593 struct amdgpu_device *adev = ring->adev; 3594 3595 /* tell RLC which is KIQ queue */ 3596 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3597 tmp &= 0xffffff00; 3598 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3599 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3600 tmp |= 0x80; 3601 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3602 } 3603 3604 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3605 { 3606 /* set graphics engine doorbell range */ 3607 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3608 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3609 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3610 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3611 3612 /* set compute engine doorbell range */ 3613 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3614 (adev->doorbell_index.kiq * 2) << 2); 3615 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3616 (adev->doorbell_index.userqueue_end * 2) << 2); 3617 } 3618 3619 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3620 struct amdgpu_mqd_prop *prop) 3621 { 3622 struct v11_gfx_mqd *mqd = m; 3623 uint64_t hqd_gpu_addr, wb_gpu_addr; 3624 uint32_t tmp; 3625 uint32_t rb_bufsz; 3626 3627 /* set up gfx hqd wptr */ 3628 mqd->cp_gfx_hqd_wptr = 0; 3629 mqd->cp_gfx_hqd_wptr_hi = 0; 3630 3631 /* set the pointer to the MQD */ 3632 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3633 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3634 3635 /* set up mqd control */ 3636 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3637 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3638 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3639 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3640 mqd->cp_gfx_mqd_control = tmp; 3641 3642 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3643 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3644 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3645 mqd->cp_gfx_hqd_vmid = 0; 3646 3647 /* set up default queue priority level 3648 * 0x0 = low priority, 0x1 = high priority */ 3649 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3650 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3651 mqd->cp_gfx_hqd_queue_priority = tmp; 3652 3653 /* set up time quantum */ 3654 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3655 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3656 mqd->cp_gfx_hqd_quantum = tmp; 3657 3658 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3659 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3660 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3661 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3662 3663 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3664 wb_gpu_addr = prop->rptr_gpu_addr; 3665 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3666 mqd->cp_gfx_hqd_rptr_addr_hi = 3667 upper_32_bits(wb_gpu_addr) & 0xffff; 3668 3669 /* set up rb_wptr_poll addr */ 3670 wb_gpu_addr = prop->wptr_gpu_addr; 3671 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3672 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3673 3674 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3675 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3676 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3677 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3678 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3679 #ifdef __BIG_ENDIAN 3680 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3681 #endif 3682 mqd->cp_gfx_hqd_cntl = tmp; 3683 3684 /* set up cp_doorbell_control */ 3685 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3686 if (prop->use_doorbell) { 3687 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3688 DOORBELL_OFFSET, prop->doorbell_index); 3689 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3690 DOORBELL_EN, 1); 3691 } else 3692 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3693 DOORBELL_EN, 0); 3694 mqd->cp_rb_doorbell_control = tmp; 3695 3696 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3697 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3698 3699 /* active the queue */ 3700 mqd->cp_gfx_hqd_active = 1; 3701 3702 return 0; 3703 } 3704 3705 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3706 { 3707 struct amdgpu_device *adev = ring->adev; 3708 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3709 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3710 3711 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3712 memset((void *)mqd, 0, sizeof(*mqd)); 3713 mutex_lock(&adev->srbm_mutex); 3714 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3715 amdgpu_ring_init_mqd(ring); 3716 soc21_grbm_select(adev, 0, 0, 0, 0); 3717 mutex_unlock(&adev->srbm_mutex); 3718 if (adev->gfx.me.mqd_backup[mqd_idx]) 3719 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3720 } else { 3721 /* restore mqd with the backup copy */ 3722 if (adev->gfx.me.mqd_backup[mqd_idx]) 3723 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3724 /* reset the ring */ 3725 ring->wptr = 0; 3726 *ring->wptr_cpu_addr = 0; 3727 amdgpu_ring_clear_ring(ring); 3728 } 3729 3730 return 0; 3731 } 3732 3733 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3734 { 3735 int r, i; 3736 struct amdgpu_ring *ring; 3737 3738 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3739 ring = &adev->gfx.gfx_ring[i]; 3740 3741 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3742 if (unlikely(r != 0)) 3743 return r; 3744 3745 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3746 if (!r) { 3747 r = gfx_v11_0_gfx_init_queue(ring); 3748 amdgpu_bo_kunmap(ring->mqd_obj); 3749 ring->mqd_ptr = NULL; 3750 } 3751 amdgpu_bo_unreserve(ring->mqd_obj); 3752 if (r) 3753 return r; 3754 } 3755 3756 r = amdgpu_gfx_enable_kgq(adev, 0); 3757 if (r) 3758 return r; 3759 3760 return gfx_v11_0_cp_gfx_start(adev); 3761 } 3762 3763 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3764 struct amdgpu_mqd_prop *prop) 3765 { 3766 struct v11_compute_mqd *mqd = m; 3767 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3768 uint32_t tmp; 3769 3770 mqd->header = 0xC0310800; 3771 mqd->compute_pipelinestat_enable = 0x00000001; 3772 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3773 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3774 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3775 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3776 mqd->compute_misc_reserved = 0x00000007; 3777 3778 eop_base_addr = prop->eop_gpu_addr >> 8; 3779 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3780 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3781 3782 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3783 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3784 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3785 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3786 3787 mqd->cp_hqd_eop_control = tmp; 3788 3789 /* enable doorbell? */ 3790 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3791 3792 if (prop->use_doorbell) { 3793 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3794 DOORBELL_OFFSET, prop->doorbell_index); 3795 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3796 DOORBELL_EN, 1); 3797 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3798 DOORBELL_SOURCE, 0); 3799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3800 DOORBELL_HIT, 0); 3801 } else { 3802 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3803 DOORBELL_EN, 0); 3804 } 3805 3806 mqd->cp_hqd_pq_doorbell_control = tmp; 3807 3808 /* disable the queue if it's active */ 3809 mqd->cp_hqd_dequeue_request = 0; 3810 mqd->cp_hqd_pq_rptr = 0; 3811 mqd->cp_hqd_pq_wptr_lo = 0; 3812 mqd->cp_hqd_pq_wptr_hi = 0; 3813 3814 /* set the pointer to the MQD */ 3815 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3816 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3817 3818 /* set MQD vmid to 0 */ 3819 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3820 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3821 mqd->cp_mqd_control = tmp; 3822 3823 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3824 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3825 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3826 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3827 3828 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3829 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3831 (order_base_2(prop->queue_size / 4) - 1)); 3832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3833 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3836 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3838 mqd->cp_hqd_pq_control = tmp; 3839 3840 /* set the wb address whether it's enabled or not */ 3841 wb_gpu_addr = prop->rptr_gpu_addr; 3842 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3843 mqd->cp_hqd_pq_rptr_report_addr_hi = 3844 upper_32_bits(wb_gpu_addr) & 0xffff; 3845 3846 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3847 wb_gpu_addr = prop->wptr_gpu_addr; 3848 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3849 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3850 3851 tmp = 0; 3852 /* enable the doorbell if requested */ 3853 if (prop->use_doorbell) { 3854 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3856 DOORBELL_OFFSET, prop->doorbell_index); 3857 3858 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3859 DOORBELL_EN, 1); 3860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3861 DOORBELL_SOURCE, 0); 3862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3863 DOORBELL_HIT, 0); 3864 } 3865 3866 mqd->cp_hqd_pq_doorbell_control = tmp; 3867 3868 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3869 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3870 3871 /* set the vmid for the queue */ 3872 mqd->cp_hqd_vmid = 0; 3873 3874 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3875 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3876 mqd->cp_hqd_persistent_state = tmp; 3877 3878 /* set MIN_IB_AVAIL_SIZE */ 3879 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3880 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3881 mqd->cp_hqd_ib_control = tmp; 3882 3883 /* set static priority for a compute queue/ring */ 3884 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3885 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3886 3887 mqd->cp_hqd_active = prop->hqd_active; 3888 3889 return 0; 3890 } 3891 3892 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3893 { 3894 struct amdgpu_device *adev = ring->adev; 3895 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3896 int j; 3897 3898 /* inactivate the queue */ 3899 if (amdgpu_sriov_vf(adev)) 3900 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3901 3902 /* disable wptr polling */ 3903 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3904 3905 /* write the EOP addr */ 3906 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3907 mqd->cp_hqd_eop_base_addr_lo); 3908 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3909 mqd->cp_hqd_eop_base_addr_hi); 3910 3911 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3912 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3913 mqd->cp_hqd_eop_control); 3914 3915 /* enable doorbell? */ 3916 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3917 mqd->cp_hqd_pq_doorbell_control); 3918 3919 /* disable the queue if it's active */ 3920 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3921 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3922 for (j = 0; j < adev->usec_timeout; j++) { 3923 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3924 break; 3925 udelay(1); 3926 } 3927 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3928 mqd->cp_hqd_dequeue_request); 3929 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3930 mqd->cp_hqd_pq_rptr); 3931 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3932 mqd->cp_hqd_pq_wptr_lo); 3933 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3934 mqd->cp_hqd_pq_wptr_hi); 3935 } 3936 3937 /* set the pointer to the MQD */ 3938 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3939 mqd->cp_mqd_base_addr_lo); 3940 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3941 mqd->cp_mqd_base_addr_hi); 3942 3943 /* set MQD vmid to 0 */ 3944 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3945 mqd->cp_mqd_control); 3946 3947 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3948 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3949 mqd->cp_hqd_pq_base_lo); 3950 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3951 mqd->cp_hqd_pq_base_hi); 3952 3953 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3954 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3955 mqd->cp_hqd_pq_control); 3956 3957 /* set the wb address whether it's enabled or not */ 3958 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3959 mqd->cp_hqd_pq_rptr_report_addr_lo); 3960 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3961 mqd->cp_hqd_pq_rptr_report_addr_hi); 3962 3963 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3964 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3965 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3966 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3967 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3968 3969 /* enable the doorbell if requested */ 3970 if (ring->use_doorbell) { 3971 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3972 (adev->doorbell_index.kiq * 2) << 2); 3973 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3974 (adev->doorbell_index.userqueue_end * 2) << 2); 3975 } 3976 3977 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3978 mqd->cp_hqd_pq_doorbell_control); 3979 3980 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3981 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3982 mqd->cp_hqd_pq_wptr_lo); 3983 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3984 mqd->cp_hqd_pq_wptr_hi); 3985 3986 /* set the vmid for the queue */ 3987 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3988 3989 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3990 mqd->cp_hqd_persistent_state); 3991 3992 /* activate the queue */ 3993 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3994 mqd->cp_hqd_active); 3995 3996 if (ring->use_doorbell) 3997 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3998 3999 return 0; 4000 } 4001 4002 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4003 { 4004 struct amdgpu_device *adev = ring->adev; 4005 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4006 4007 gfx_v11_0_kiq_setting(ring); 4008 4009 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4010 /* reset MQD to a clean status */ 4011 if (adev->gfx.kiq[0].mqd_backup) 4012 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4013 4014 /* reset ring buffer */ 4015 ring->wptr = 0; 4016 amdgpu_ring_clear_ring(ring); 4017 4018 mutex_lock(&adev->srbm_mutex); 4019 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4020 gfx_v11_0_kiq_init_register(ring); 4021 soc21_grbm_select(adev, 0, 0, 0, 0); 4022 mutex_unlock(&adev->srbm_mutex); 4023 } else { 4024 memset((void *)mqd, 0, sizeof(*mqd)); 4025 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4026 amdgpu_ring_clear_ring(ring); 4027 mutex_lock(&adev->srbm_mutex); 4028 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4029 amdgpu_ring_init_mqd(ring); 4030 gfx_v11_0_kiq_init_register(ring); 4031 soc21_grbm_select(adev, 0, 0, 0, 0); 4032 mutex_unlock(&adev->srbm_mutex); 4033 4034 if (adev->gfx.kiq[0].mqd_backup) 4035 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4036 } 4037 4038 return 0; 4039 } 4040 4041 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4042 { 4043 struct amdgpu_device *adev = ring->adev; 4044 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4045 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4046 4047 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4048 memset((void *)mqd, 0, sizeof(*mqd)); 4049 mutex_lock(&adev->srbm_mutex); 4050 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4051 amdgpu_ring_init_mqd(ring); 4052 soc21_grbm_select(adev, 0, 0, 0, 0); 4053 mutex_unlock(&adev->srbm_mutex); 4054 4055 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4056 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4057 } else { 4058 /* restore MQD to a clean status */ 4059 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4060 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4061 /* reset ring buffer */ 4062 ring->wptr = 0; 4063 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4064 amdgpu_ring_clear_ring(ring); 4065 } 4066 4067 return 0; 4068 } 4069 4070 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4071 { 4072 struct amdgpu_ring *ring; 4073 int r; 4074 4075 ring = &adev->gfx.kiq[0].ring; 4076 4077 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4078 if (unlikely(r != 0)) 4079 return r; 4080 4081 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4082 if (unlikely(r != 0)) { 4083 amdgpu_bo_unreserve(ring->mqd_obj); 4084 return r; 4085 } 4086 4087 gfx_v11_0_kiq_init_queue(ring); 4088 amdgpu_bo_kunmap(ring->mqd_obj); 4089 ring->mqd_ptr = NULL; 4090 amdgpu_bo_unreserve(ring->mqd_obj); 4091 ring->sched.ready = true; 4092 return 0; 4093 } 4094 4095 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4096 { 4097 struct amdgpu_ring *ring = NULL; 4098 int r = 0, i; 4099 4100 if (!amdgpu_async_gfx_ring) 4101 gfx_v11_0_cp_compute_enable(adev, true); 4102 4103 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4104 ring = &adev->gfx.compute_ring[i]; 4105 4106 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4107 if (unlikely(r != 0)) 4108 goto done; 4109 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4110 if (!r) { 4111 r = gfx_v11_0_kcq_init_queue(ring); 4112 amdgpu_bo_kunmap(ring->mqd_obj); 4113 ring->mqd_ptr = NULL; 4114 } 4115 amdgpu_bo_unreserve(ring->mqd_obj); 4116 if (r) 4117 goto done; 4118 } 4119 4120 r = amdgpu_gfx_enable_kcq(adev, 0); 4121 done: 4122 return r; 4123 } 4124 4125 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4126 { 4127 int r, i; 4128 struct amdgpu_ring *ring; 4129 4130 if (!(adev->flags & AMD_IS_APU)) 4131 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4132 4133 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4134 /* legacy firmware loading */ 4135 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4136 if (r) 4137 return r; 4138 4139 if (adev->gfx.rs64_enable) 4140 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4141 else 4142 r = gfx_v11_0_cp_compute_load_microcode(adev); 4143 if (r) 4144 return r; 4145 } 4146 4147 gfx_v11_0_cp_set_doorbell_range(adev); 4148 4149 if (amdgpu_async_gfx_ring) { 4150 gfx_v11_0_cp_compute_enable(adev, true); 4151 gfx_v11_0_cp_gfx_enable(adev, true); 4152 } 4153 4154 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4155 r = amdgpu_mes_kiq_hw_init(adev); 4156 else 4157 r = gfx_v11_0_kiq_resume(adev); 4158 if (r) 4159 return r; 4160 4161 r = gfx_v11_0_kcq_resume(adev); 4162 if (r) 4163 return r; 4164 4165 if (!amdgpu_async_gfx_ring) { 4166 r = gfx_v11_0_cp_gfx_resume(adev); 4167 if (r) 4168 return r; 4169 } else { 4170 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4171 if (r) 4172 return r; 4173 } 4174 4175 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4176 ring = &adev->gfx.gfx_ring[i]; 4177 r = amdgpu_ring_test_helper(ring); 4178 if (r) 4179 return r; 4180 } 4181 4182 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4183 ring = &adev->gfx.compute_ring[i]; 4184 r = amdgpu_ring_test_helper(ring); 4185 if (r) 4186 return r; 4187 } 4188 4189 return 0; 4190 } 4191 4192 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4193 { 4194 gfx_v11_0_cp_gfx_enable(adev, enable); 4195 gfx_v11_0_cp_compute_enable(adev, enable); 4196 } 4197 4198 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4199 { 4200 int r; 4201 bool value; 4202 4203 r = adev->gfxhub.funcs->gart_enable(adev); 4204 if (r) 4205 return r; 4206 4207 adev->hdp.funcs->flush_hdp(adev, NULL); 4208 4209 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4210 false : true; 4211 4212 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4213 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4214 4215 return 0; 4216 } 4217 4218 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4219 { 4220 u32 tmp; 4221 4222 /* select RS64 */ 4223 if (adev->gfx.rs64_enable) { 4224 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4225 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4226 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4227 4228 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4229 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4230 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4231 } 4232 4233 if (amdgpu_emu_mode == 1) 4234 msleep(100); 4235 } 4236 4237 static int get_gb_addr_config(struct amdgpu_device * adev) 4238 { 4239 u32 gb_addr_config; 4240 4241 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4242 if (gb_addr_config == 0) 4243 return -EINVAL; 4244 4245 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4246 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4247 4248 adev->gfx.config.gb_addr_config = gb_addr_config; 4249 4250 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4251 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4252 GB_ADDR_CONFIG, NUM_PIPES); 4253 4254 adev->gfx.config.max_tile_pipes = 4255 adev->gfx.config.gb_addr_config_fields.num_pipes; 4256 4257 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4258 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4259 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4260 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4261 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4262 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4263 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4264 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4265 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4266 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4267 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4268 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4269 4270 return 0; 4271 } 4272 4273 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4274 { 4275 uint32_t data; 4276 4277 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4278 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4279 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4280 4281 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4282 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4283 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4284 } 4285 4286 static int gfx_v11_0_hw_init(void *handle) 4287 { 4288 int r; 4289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4290 4291 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4292 if (adev->gfx.imu.funcs) { 4293 /* RLC autoload sequence 1: Program rlc ram */ 4294 if (adev->gfx.imu.funcs->program_rlc_ram) 4295 adev->gfx.imu.funcs->program_rlc_ram(adev); 4296 } 4297 /* rlc autoload firmware */ 4298 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4299 if (r) 4300 return r; 4301 } else { 4302 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4303 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4304 if (adev->gfx.imu.funcs->load_microcode) 4305 adev->gfx.imu.funcs->load_microcode(adev); 4306 if (adev->gfx.imu.funcs->setup_imu) 4307 adev->gfx.imu.funcs->setup_imu(adev); 4308 if (adev->gfx.imu.funcs->start_imu) 4309 adev->gfx.imu.funcs->start_imu(adev); 4310 } 4311 4312 /* disable gpa mode in backdoor loading */ 4313 gfx_v11_0_disable_gpa_mode(adev); 4314 } 4315 } 4316 4317 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4318 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4319 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4320 if (r) { 4321 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4322 return r; 4323 } 4324 } 4325 4326 adev->gfx.is_poweron = true; 4327 4328 if(get_gb_addr_config(adev)) 4329 DRM_WARN("Invalid gb_addr_config !\n"); 4330 4331 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4332 adev->gfx.rs64_enable) 4333 gfx_v11_0_config_gfx_rs64(adev); 4334 4335 r = gfx_v11_0_gfxhub_enable(adev); 4336 if (r) 4337 return r; 4338 4339 if (!amdgpu_emu_mode) 4340 gfx_v11_0_init_golden_registers(adev); 4341 4342 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4343 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4344 /** 4345 * For gfx 11, rlc firmware loading relies on smu firmware is 4346 * loaded firstly, so in direct type, it has to load smc ucode 4347 * here before rlc. 4348 */ 4349 if (!(adev->flags & AMD_IS_APU)) { 4350 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4351 if (r) 4352 return r; 4353 } 4354 } 4355 4356 gfx_v11_0_constants_init(adev); 4357 4358 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4359 gfx_v11_0_select_cp_fw_arch(adev); 4360 4361 if (adev->nbio.funcs->gc_doorbell_init) 4362 adev->nbio.funcs->gc_doorbell_init(adev); 4363 4364 r = gfx_v11_0_rlc_resume(adev); 4365 if (r) 4366 return r; 4367 4368 /* 4369 * init golden registers and rlc resume may override some registers, 4370 * reconfig them here 4371 */ 4372 gfx_v11_0_tcp_harvest(adev); 4373 4374 r = gfx_v11_0_cp_resume(adev); 4375 if (r) 4376 return r; 4377 4378 return r; 4379 } 4380 4381 static int gfx_v11_0_hw_fini(void *handle) 4382 { 4383 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4384 4385 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4386 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4387 4388 if (!adev->no_hw_access) { 4389 if (amdgpu_async_gfx_ring) { 4390 if (amdgpu_gfx_disable_kgq(adev, 0)) 4391 DRM_ERROR("KGQ disable failed\n"); 4392 } 4393 4394 if (amdgpu_gfx_disable_kcq(adev, 0)) 4395 DRM_ERROR("KCQ disable failed\n"); 4396 4397 amdgpu_mes_kiq_hw_fini(adev); 4398 } 4399 4400 if (amdgpu_sriov_vf(adev)) 4401 /* Remove the steps disabling CPG and clearing KIQ position, 4402 * so that CP could perform IDLE-SAVE during switch. Those 4403 * steps are necessary to avoid a DMAR error in gfx9 but it is 4404 * not reproduced on gfx11. 4405 */ 4406 return 0; 4407 4408 gfx_v11_0_cp_enable(adev, false); 4409 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4410 4411 adev->gfxhub.funcs->gart_disable(adev); 4412 4413 adev->gfx.is_poweron = false; 4414 4415 return 0; 4416 } 4417 4418 static int gfx_v11_0_suspend(void *handle) 4419 { 4420 return gfx_v11_0_hw_fini(handle); 4421 } 4422 4423 static int gfx_v11_0_resume(void *handle) 4424 { 4425 return gfx_v11_0_hw_init(handle); 4426 } 4427 4428 static bool gfx_v11_0_is_idle(void *handle) 4429 { 4430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4431 4432 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4433 GRBM_STATUS, GUI_ACTIVE)) 4434 return false; 4435 else 4436 return true; 4437 } 4438 4439 static int gfx_v11_0_wait_for_idle(void *handle) 4440 { 4441 unsigned i; 4442 u32 tmp; 4443 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4444 4445 for (i = 0; i < adev->usec_timeout; i++) { 4446 /* read MC_STATUS */ 4447 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4448 GRBM_STATUS__GUI_ACTIVE_MASK; 4449 4450 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4451 return 0; 4452 udelay(1); 4453 } 4454 return -ETIMEDOUT; 4455 } 4456 4457 static int gfx_v11_0_soft_reset(void *handle) 4458 { 4459 u32 grbm_soft_reset = 0; 4460 u32 tmp; 4461 int i, j, k; 4462 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4463 4464 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4465 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4466 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4467 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4468 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4469 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4470 4471 gfx_v11_0_set_safe_mode(adev, 0); 4472 4473 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4474 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4475 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4476 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4477 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4478 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4479 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4480 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4481 4482 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4483 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4484 } 4485 } 4486 } 4487 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4488 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4489 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4490 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4491 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4492 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4493 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4494 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4495 4496 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4497 } 4498 } 4499 } 4500 4501 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4502 4503 // Read CP_VMID_RESET register three times. 4504 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4505 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4506 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4507 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4508 4509 for (i = 0; i < adev->usec_timeout; i++) { 4510 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4511 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4512 break; 4513 udelay(1); 4514 } 4515 if (i >= adev->usec_timeout) { 4516 printk("Failed to wait all pipes clean\n"); 4517 return -EINVAL; 4518 } 4519 4520 /********** trigger soft reset ***********/ 4521 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4522 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4523 SOFT_RESET_CP, 1); 4524 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4525 SOFT_RESET_GFX, 1); 4526 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4527 SOFT_RESET_CPF, 1); 4528 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4529 SOFT_RESET_CPC, 1); 4530 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4531 SOFT_RESET_CPG, 1); 4532 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4533 /********** exit soft reset ***********/ 4534 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4535 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4536 SOFT_RESET_CP, 0); 4537 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4538 SOFT_RESET_GFX, 0); 4539 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4540 SOFT_RESET_CPF, 0); 4541 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4542 SOFT_RESET_CPC, 0); 4543 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4544 SOFT_RESET_CPG, 0); 4545 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4546 4547 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4548 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4549 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4550 4551 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4552 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4553 4554 for (i = 0; i < adev->usec_timeout; i++) { 4555 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4556 break; 4557 udelay(1); 4558 } 4559 if (i >= adev->usec_timeout) { 4560 printk("Failed to wait CP_VMID_RESET to 0\n"); 4561 return -EINVAL; 4562 } 4563 4564 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4565 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4566 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4567 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4568 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4569 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4570 4571 gfx_v11_0_unset_safe_mode(adev, 0); 4572 4573 return gfx_v11_0_cp_resume(adev); 4574 } 4575 4576 static bool gfx_v11_0_check_soft_reset(void *handle) 4577 { 4578 int i, r; 4579 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4580 struct amdgpu_ring *ring; 4581 long tmo = msecs_to_jiffies(1000); 4582 4583 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4584 ring = &adev->gfx.gfx_ring[i]; 4585 r = amdgpu_ring_test_ib(ring, tmo); 4586 if (r) 4587 return true; 4588 } 4589 4590 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4591 ring = &adev->gfx.compute_ring[i]; 4592 r = amdgpu_ring_test_ib(ring, tmo); 4593 if (r) 4594 return true; 4595 } 4596 4597 return false; 4598 } 4599 4600 static int gfx_v11_0_post_soft_reset(void *handle) 4601 { 4602 /** 4603 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4604 */ 4605 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4606 } 4607 4608 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4609 { 4610 uint64_t clock; 4611 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4612 4613 if (amdgpu_sriov_vf(adev)) { 4614 amdgpu_gfx_off_ctrl(adev, false); 4615 mutex_lock(&adev->gfx.gpu_clock_mutex); 4616 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4617 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4618 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4619 if (clock_counter_hi_pre != clock_counter_hi_after) 4620 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4621 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4622 amdgpu_gfx_off_ctrl(adev, true); 4623 } else { 4624 preempt_disable(); 4625 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4626 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4627 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4628 if (clock_counter_hi_pre != clock_counter_hi_after) 4629 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4630 preempt_enable(); 4631 } 4632 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4633 4634 return clock; 4635 } 4636 4637 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4638 uint32_t vmid, 4639 uint32_t gds_base, uint32_t gds_size, 4640 uint32_t gws_base, uint32_t gws_size, 4641 uint32_t oa_base, uint32_t oa_size) 4642 { 4643 struct amdgpu_device *adev = ring->adev; 4644 4645 /* GDS Base */ 4646 gfx_v11_0_write_data_to_reg(ring, 0, false, 4647 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4648 gds_base); 4649 4650 /* GDS Size */ 4651 gfx_v11_0_write_data_to_reg(ring, 0, false, 4652 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4653 gds_size); 4654 4655 /* GWS */ 4656 gfx_v11_0_write_data_to_reg(ring, 0, false, 4657 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4658 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4659 4660 /* OA */ 4661 gfx_v11_0_write_data_to_reg(ring, 0, false, 4662 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4663 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4664 } 4665 4666 static int gfx_v11_0_early_init(void *handle) 4667 { 4668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4669 4670 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4671 4672 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4673 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4674 AMDGPU_MAX_COMPUTE_RINGS); 4675 4676 gfx_v11_0_set_kiq_pm4_funcs(adev); 4677 gfx_v11_0_set_ring_funcs(adev); 4678 gfx_v11_0_set_irq_funcs(adev); 4679 gfx_v11_0_set_gds_init(adev); 4680 gfx_v11_0_set_rlc_funcs(adev); 4681 gfx_v11_0_set_mqd_funcs(adev); 4682 gfx_v11_0_set_imu_funcs(adev); 4683 4684 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4685 4686 return gfx_v11_0_init_microcode(adev); 4687 } 4688 4689 static int gfx_v11_0_late_init(void *handle) 4690 { 4691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4692 int r; 4693 4694 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4695 if (r) 4696 return r; 4697 4698 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4699 if (r) 4700 return r; 4701 4702 return 0; 4703 } 4704 4705 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4706 { 4707 uint32_t rlc_cntl; 4708 4709 /* if RLC is not enabled, do nothing */ 4710 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4711 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4712 } 4713 4714 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4715 { 4716 uint32_t data; 4717 unsigned i; 4718 4719 data = RLC_SAFE_MODE__CMD_MASK; 4720 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4721 4722 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4723 4724 /* wait for RLC_SAFE_MODE */ 4725 for (i = 0; i < adev->usec_timeout; i++) { 4726 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4727 RLC_SAFE_MODE, CMD)) 4728 break; 4729 udelay(1); 4730 } 4731 } 4732 4733 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4734 { 4735 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4736 } 4737 4738 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4739 bool enable) 4740 { 4741 uint32_t def, data; 4742 4743 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4744 return; 4745 4746 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4747 4748 if (enable) 4749 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4750 else 4751 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4752 4753 if (def != data) 4754 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4755 } 4756 4757 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4758 bool enable) 4759 { 4760 uint32_t def, data; 4761 4762 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4763 return; 4764 4765 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4766 4767 if (enable) 4768 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4769 else 4770 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4771 4772 if (def != data) 4773 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4774 } 4775 4776 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4777 bool enable) 4778 { 4779 uint32_t def, data; 4780 4781 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4782 return; 4783 4784 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4785 4786 if (enable) 4787 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4788 else 4789 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4790 4791 if (def != data) 4792 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4793 } 4794 4795 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4796 bool enable) 4797 { 4798 uint32_t data, def; 4799 4800 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4801 return; 4802 4803 /* It is disabled by HW by default */ 4804 if (enable) { 4805 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4806 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4807 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4808 4809 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4810 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4811 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4812 4813 if (def != data) 4814 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4815 } 4816 } else { 4817 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4818 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4819 4820 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4821 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4822 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4823 4824 if (def != data) 4825 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4826 } 4827 } 4828 } 4829 4830 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4831 bool enable) 4832 { 4833 uint32_t def, data; 4834 4835 if (!(adev->cg_flags & 4836 (AMD_CG_SUPPORT_GFX_CGCG | 4837 AMD_CG_SUPPORT_GFX_CGLS | 4838 AMD_CG_SUPPORT_GFX_3D_CGCG | 4839 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4840 return; 4841 4842 if (enable) { 4843 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4844 4845 /* unset CGCG override */ 4846 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4847 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4849 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4850 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4851 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4852 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4853 4854 /* update CGCG override bits */ 4855 if (def != data) 4856 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4857 4858 /* enable cgcg FSM(0x0000363F) */ 4859 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4860 4861 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4862 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4863 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4864 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4865 } 4866 4867 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4868 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4869 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4870 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4871 } 4872 4873 if (def != data) 4874 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4875 4876 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4877 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4878 4879 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4880 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4881 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4882 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4883 } 4884 4885 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4886 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4887 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4888 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4889 } 4890 4891 if (def != data) 4892 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4893 4894 /* set IDLE_POLL_COUNT(0x00900100) */ 4895 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4896 4897 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4898 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4899 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4900 4901 if (def != data) 4902 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4903 4904 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4905 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4906 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4907 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4908 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4909 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4910 4911 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4912 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4913 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4914 4915 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4916 if (adev->sdma.num_instances > 1) { 4917 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4918 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4919 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4920 } 4921 } else { 4922 /* Program RLC_CGCG_CGLS_CTRL */ 4923 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4924 4925 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4926 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4927 4928 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4929 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4930 4931 if (def != data) 4932 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4933 4934 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4935 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4936 4937 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4938 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4939 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4940 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4941 4942 if (def != data) 4943 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4944 4945 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4946 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4947 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4948 4949 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4950 if (adev->sdma.num_instances > 1) { 4951 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4952 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4953 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4954 } 4955 } 4956 } 4957 4958 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4959 bool enable) 4960 { 4961 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4962 4963 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 4964 4965 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 4966 4967 gfx_v11_0_update_repeater_fgcg(adev, enable); 4968 4969 gfx_v11_0_update_sram_fgcg(adev, enable); 4970 4971 gfx_v11_0_update_perf_clk(adev, enable); 4972 4973 if (adev->cg_flags & 4974 (AMD_CG_SUPPORT_GFX_MGCG | 4975 AMD_CG_SUPPORT_GFX_CGLS | 4976 AMD_CG_SUPPORT_GFX_CGCG | 4977 AMD_CG_SUPPORT_GFX_3D_CGCG | 4978 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4979 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 4980 4981 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4982 4983 return 0; 4984 } 4985 4986 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4987 { 4988 u32 data; 4989 4990 amdgpu_gfx_off_ctrl(adev, false); 4991 4992 data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL); 4993 4994 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4995 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4996 4997 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 4998 4999 amdgpu_gfx_off_ctrl(adev, true); 5000 } 5001 5002 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5003 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5004 .set_safe_mode = gfx_v11_0_set_safe_mode, 5005 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5006 .init = gfx_v11_0_rlc_init, 5007 .get_csb_size = gfx_v11_0_get_csb_size, 5008 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5009 .resume = gfx_v11_0_rlc_resume, 5010 .stop = gfx_v11_0_rlc_stop, 5011 .reset = gfx_v11_0_rlc_reset, 5012 .start = gfx_v11_0_rlc_start, 5013 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5014 }; 5015 5016 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5017 { 5018 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5019 5020 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5021 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5022 else 5023 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5024 5025 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5026 5027 // Program RLC_PG_DELAY3 for CGPG hysteresis 5028 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5029 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5030 case IP_VERSION(11, 0, 1): 5031 case IP_VERSION(11, 0, 4): 5032 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5033 break; 5034 default: 5035 break; 5036 } 5037 } 5038 } 5039 5040 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5041 { 5042 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5043 5044 gfx_v11_cntl_power_gating(adev, enable); 5045 5046 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5047 } 5048 5049 static int gfx_v11_0_set_powergating_state(void *handle, 5050 enum amd_powergating_state state) 5051 { 5052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5053 bool enable = (state == AMD_PG_STATE_GATE); 5054 5055 if (amdgpu_sriov_vf(adev)) 5056 return 0; 5057 5058 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5059 case IP_VERSION(11, 0, 0): 5060 case IP_VERSION(11, 0, 2): 5061 case IP_VERSION(11, 0, 3): 5062 amdgpu_gfx_off_ctrl(adev, enable); 5063 break; 5064 case IP_VERSION(11, 0, 1): 5065 case IP_VERSION(11, 0, 4): 5066 if (!enable) 5067 amdgpu_gfx_off_ctrl(adev, false); 5068 5069 gfx_v11_cntl_pg(adev, enable); 5070 5071 if (enable) 5072 amdgpu_gfx_off_ctrl(adev, true); 5073 5074 break; 5075 default: 5076 break; 5077 } 5078 5079 return 0; 5080 } 5081 5082 static int gfx_v11_0_set_clockgating_state(void *handle, 5083 enum amd_clockgating_state state) 5084 { 5085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5086 5087 if (amdgpu_sriov_vf(adev)) 5088 return 0; 5089 5090 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5091 case IP_VERSION(11, 0, 0): 5092 case IP_VERSION(11, 0, 1): 5093 case IP_VERSION(11, 0, 2): 5094 case IP_VERSION(11, 0, 3): 5095 case IP_VERSION(11, 0, 4): 5096 gfx_v11_0_update_gfx_clock_gating(adev, 5097 state == AMD_CG_STATE_GATE); 5098 break; 5099 default: 5100 break; 5101 } 5102 5103 return 0; 5104 } 5105 5106 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5107 { 5108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5109 int data; 5110 5111 /* AMD_CG_SUPPORT_GFX_MGCG */ 5112 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5113 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5114 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5115 5116 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5117 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5118 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5119 5120 /* AMD_CG_SUPPORT_GFX_FGCG */ 5121 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5122 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5123 5124 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5125 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5126 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5127 5128 /* AMD_CG_SUPPORT_GFX_CGCG */ 5129 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5130 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5131 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5132 5133 /* AMD_CG_SUPPORT_GFX_CGLS */ 5134 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5135 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5136 5137 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5138 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5139 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5140 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5141 5142 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5143 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5144 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5145 } 5146 5147 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5148 { 5149 /* gfx11 is 32bit rptr*/ 5150 return *(uint32_t *)ring->rptr_cpu_addr; 5151 } 5152 5153 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5154 { 5155 struct amdgpu_device *adev = ring->adev; 5156 u64 wptr; 5157 5158 /* XXX check if swapping is necessary on BE */ 5159 if (ring->use_doorbell) { 5160 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5161 } else { 5162 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5163 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5164 } 5165 5166 return wptr; 5167 } 5168 5169 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5170 { 5171 struct amdgpu_device *adev = ring->adev; 5172 uint32_t *wptr_saved; 5173 uint32_t *is_queue_unmap; 5174 uint64_t aggregated_db_index; 5175 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5176 uint64_t wptr_tmp; 5177 5178 if (ring->is_mes_queue) { 5179 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5180 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5181 sizeof(uint32_t)); 5182 aggregated_db_index = 5183 amdgpu_mes_get_aggregated_doorbell_index(adev, 5184 ring->hw_prio); 5185 5186 wptr_tmp = ring->wptr & ring->buf_mask; 5187 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5188 *wptr_saved = wptr_tmp; 5189 /* assume doorbell always being used by mes mapped queue */ 5190 if (*is_queue_unmap) { 5191 WDOORBELL64(aggregated_db_index, wptr_tmp); 5192 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5193 } else { 5194 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5195 5196 if (*is_queue_unmap) 5197 WDOORBELL64(aggregated_db_index, wptr_tmp); 5198 } 5199 } else { 5200 if (ring->use_doorbell) { 5201 /* XXX check if swapping is necessary on BE */ 5202 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5203 ring->wptr); 5204 WDOORBELL64(ring->doorbell_index, ring->wptr); 5205 } else { 5206 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5207 lower_32_bits(ring->wptr)); 5208 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5209 upper_32_bits(ring->wptr)); 5210 } 5211 } 5212 } 5213 5214 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5215 { 5216 /* gfx11 hardware is 32bit rptr */ 5217 return *(uint32_t *)ring->rptr_cpu_addr; 5218 } 5219 5220 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5221 { 5222 u64 wptr; 5223 5224 /* XXX check if swapping is necessary on BE */ 5225 if (ring->use_doorbell) 5226 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5227 else 5228 BUG(); 5229 return wptr; 5230 } 5231 5232 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5233 { 5234 struct amdgpu_device *adev = ring->adev; 5235 uint32_t *wptr_saved; 5236 uint32_t *is_queue_unmap; 5237 uint64_t aggregated_db_index; 5238 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5239 uint64_t wptr_tmp; 5240 5241 if (ring->is_mes_queue) { 5242 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5243 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5244 sizeof(uint32_t)); 5245 aggregated_db_index = 5246 amdgpu_mes_get_aggregated_doorbell_index(adev, 5247 ring->hw_prio); 5248 5249 wptr_tmp = ring->wptr & ring->buf_mask; 5250 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5251 *wptr_saved = wptr_tmp; 5252 /* assume doorbell always used by mes mapped queue */ 5253 if (*is_queue_unmap) { 5254 WDOORBELL64(aggregated_db_index, wptr_tmp); 5255 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5256 } else { 5257 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5258 5259 if (*is_queue_unmap) 5260 WDOORBELL64(aggregated_db_index, wptr_tmp); 5261 } 5262 } else { 5263 /* XXX check if swapping is necessary on BE */ 5264 if (ring->use_doorbell) { 5265 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5266 ring->wptr); 5267 WDOORBELL64(ring->doorbell_index, ring->wptr); 5268 } else { 5269 BUG(); /* only DOORBELL method supported on gfx11 now */ 5270 } 5271 } 5272 } 5273 5274 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5275 { 5276 struct amdgpu_device *adev = ring->adev; 5277 u32 ref_and_mask, reg_mem_engine; 5278 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5279 5280 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5281 switch (ring->me) { 5282 case 1: 5283 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5284 break; 5285 case 2: 5286 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5287 break; 5288 default: 5289 return; 5290 } 5291 reg_mem_engine = 0; 5292 } else { 5293 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5294 reg_mem_engine = 1; /* pfp */ 5295 } 5296 5297 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5298 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5299 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5300 ref_and_mask, ref_and_mask, 0x20); 5301 } 5302 5303 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5304 struct amdgpu_job *job, 5305 struct amdgpu_ib *ib, 5306 uint32_t flags) 5307 { 5308 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5309 u32 header, control = 0; 5310 5311 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5312 5313 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5314 5315 control |= ib->length_dw | (vmid << 24); 5316 5317 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5318 control |= INDIRECT_BUFFER_PRE_ENB(1); 5319 5320 if (flags & AMDGPU_IB_PREEMPTED) 5321 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5322 5323 if (vmid) 5324 gfx_v11_0_ring_emit_de_meta(ring, 5325 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5326 } 5327 5328 if (ring->is_mes_queue) 5329 /* inherit vmid from mqd */ 5330 control |= 0x400000; 5331 5332 amdgpu_ring_write(ring, header); 5333 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5334 amdgpu_ring_write(ring, 5335 #ifdef __BIG_ENDIAN 5336 (2 << 0) | 5337 #endif 5338 lower_32_bits(ib->gpu_addr)); 5339 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5340 amdgpu_ring_write(ring, control); 5341 } 5342 5343 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5344 struct amdgpu_job *job, 5345 struct amdgpu_ib *ib, 5346 uint32_t flags) 5347 { 5348 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5349 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5350 5351 if (ring->is_mes_queue) 5352 /* inherit vmid from mqd */ 5353 control |= 0x40000000; 5354 5355 /* Currently, there is a high possibility to get wave ID mismatch 5356 * between ME and GDS, leading to a hw deadlock, because ME generates 5357 * different wave IDs than the GDS expects. This situation happens 5358 * randomly when at least 5 compute pipes use GDS ordered append. 5359 * The wave IDs generated by ME are also wrong after suspend/resume. 5360 * Those are probably bugs somewhere else in the kernel driver. 5361 * 5362 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5363 * GDS to 0 for this ring (me/pipe). 5364 */ 5365 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5366 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5367 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5368 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5369 } 5370 5371 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5372 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5373 amdgpu_ring_write(ring, 5374 #ifdef __BIG_ENDIAN 5375 (2 << 0) | 5376 #endif 5377 lower_32_bits(ib->gpu_addr)); 5378 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5379 amdgpu_ring_write(ring, control); 5380 } 5381 5382 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5383 u64 seq, unsigned flags) 5384 { 5385 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5386 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5387 5388 /* RELEASE_MEM - flush caches, send int */ 5389 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5390 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5391 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5392 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5393 PACKET3_RELEASE_MEM_GCR_GL2_US | 5394 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5395 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5396 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5397 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5398 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5399 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5400 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5401 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5402 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5403 5404 /* 5405 * the address should be Qword aligned if 64bit write, Dword 5406 * aligned if only send 32bit data low (discard data high) 5407 */ 5408 if (write64bit) 5409 BUG_ON(addr & 0x7); 5410 else 5411 BUG_ON(addr & 0x3); 5412 amdgpu_ring_write(ring, lower_32_bits(addr)); 5413 amdgpu_ring_write(ring, upper_32_bits(addr)); 5414 amdgpu_ring_write(ring, lower_32_bits(seq)); 5415 amdgpu_ring_write(ring, upper_32_bits(seq)); 5416 amdgpu_ring_write(ring, ring->is_mes_queue ? 5417 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5418 } 5419 5420 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5421 { 5422 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5423 uint32_t seq = ring->fence_drv.sync_seq; 5424 uint64_t addr = ring->fence_drv.gpu_addr; 5425 5426 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5427 upper_32_bits(addr), seq, 0xffffffff, 4); 5428 } 5429 5430 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5431 uint16_t pasid, uint32_t flush_type, 5432 bool all_hub, uint8_t dst_sel) 5433 { 5434 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5435 amdgpu_ring_write(ring, 5436 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5437 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5438 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5439 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5440 } 5441 5442 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5443 unsigned vmid, uint64_t pd_addr) 5444 { 5445 if (ring->is_mes_queue) 5446 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5447 else 5448 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5449 5450 /* compute doesn't have PFP */ 5451 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5452 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5453 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5454 amdgpu_ring_write(ring, 0x0); 5455 } 5456 } 5457 5458 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5459 u64 seq, unsigned int flags) 5460 { 5461 struct amdgpu_device *adev = ring->adev; 5462 5463 /* we only allocate 32bit for each seq wb address */ 5464 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5465 5466 /* write fence seq to the "addr" */ 5467 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5468 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5469 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5470 amdgpu_ring_write(ring, lower_32_bits(addr)); 5471 amdgpu_ring_write(ring, upper_32_bits(addr)); 5472 amdgpu_ring_write(ring, lower_32_bits(seq)); 5473 5474 if (flags & AMDGPU_FENCE_FLAG_INT) { 5475 /* set register to trigger INT */ 5476 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5477 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5478 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5479 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5480 amdgpu_ring_write(ring, 0); 5481 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5482 } 5483 } 5484 5485 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5486 uint32_t flags) 5487 { 5488 uint32_t dw2 = 0; 5489 5490 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5491 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5492 /* set load_global_config & load_global_uconfig */ 5493 dw2 |= 0x8001; 5494 /* set load_cs_sh_regs */ 5495 dw2 |= 0x01000000; 5496 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5497 dw2 |= 0x10002; 5498 } 5499 5500 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5501 amdgpu_ring_write(ring, dw2); 5502 amdgpu_ring_write(ring, 0); 5503 } 5504 5505 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5506 u64 shadow_va, u64 csa_va, 5507 u64 gds_va, bool init_shadow, 5508 int vmid) 5509 { 5510 struct amdgpu_device *adev = ring->adev; 5511 5512 if (!adev->gfx.cp_gfx_shadow) 5513 return; 5514 5515 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5516 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5517 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5518 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5519 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5520 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5521 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5522 amdgpu_ring_write(ring, shadow_va ? 5523 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5524 amdgpu_ring_write(ring, init_shadow ? 5525 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5526 } 5527 5528 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5529 { 5530 unsigned ret; 5531 5532 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5533 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5534 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5535 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5536 ret = ring->wptr & ring->buf_mask; 5537 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5538 5539 return ret; 5540 } 5541 5542 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5543 { 5544 unsigned cur; 5545 BUG_ON(offset > ring->buf_mask); 5546 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5547 5548 cur = (ring->wptr - 1) & ring->buf_mask; 5549 if (likely(cur > offset)) 5550 ring->ring[offset] = cur - offset; 5551 else 5552 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5553 } 5554 5555 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5556 { 5557 int i, r = 0; 5558 struct amdgpu_device *adev = ring->adev; 5559 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5560 struct amdgpu_ring *kiq_ring = &kiq->ring; 5561 unsigned long flags; 5562 5563 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5564 return -EINVAL; 5565 5566 spin_lock_irqsave(&kiq->ring_lock, flags); 5567 5568 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5569 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5570 return -ENOMEM; 5571 } 5572 5573 /* assert preemption condition */ 5574 amdgpu_ring_set_preempt_cond_exec(ring, false); 5575 5576 /* assert IB preemption, emit the trailing fence */ 5577 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5578 ring->trail_fence_gpu_addr, 5579 ++ring->trail_seq); 5580 amdgpu_ring_commit(kiq_ring); 5581 5582 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5583 5584 /* poll the trailing fence */ 5585 for (i = 0; i < adev->usec_timeout; i++) { 5586 if (ring->trail_seq == 5587 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5588 break; 5589 udelay(1); 5590 } 5591 5592 if (i >= adev->usec_timeout) { 5593 r = -EINVAL; 5594 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5595 } 5596 5597 /* deassert preemption condition */ 5598 amdgpu_ring_set_preempt_cond_exec(ring, true); 5599 return r; 5600 } 5601 5602 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5603 { 5604 struct amdgpu_device *adev = ring->adev; 5605 struct v10_de_ib_state de_payload = {0}; 5606 uint64_t offset, gds_addr, de_payload_gpu_addr; 5607 void *de_payload_cpu_addr; 5608 int cnt; 5609 5610 if (ring->is_mes_queue) { 5611 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5612 gfx[0].gfx_meta_data) + 5613 offsetof(struct v10_gfx_meta_data, de_payload); 5614 de_payload_gpu_addr = 5615 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5616 de_payload_cpu_addr = 5617 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5618 5619 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5620 gfx[0].gds_backup) + 5621 offsetof(struct v10_gfx_meta_data, de_payload); 5622 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5623 } else { 5624 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5625 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5626 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5627 5628 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5629 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5630 PAGE_SIZE); 5631 } 5632 5633 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5634 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5635 5636 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5637 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5638 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5639 WRITE_DATA_DST_SEL(8) | 5640 WR_CONFIRM) | 5641 WRITE_DATA_CACHE_POLICY(0)); 5642 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5643 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5644 5645 if (resume) 5646 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5647 sizeof(de_payload) >> 2); 5648 else 5649 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5650 sizeof(de_payload) >> 2); 5651 } 5652 5653 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5654 bool secure) 5655 { 5656 uint32_t v = secure ? FRAME_TMZ : 0; 5657 5658 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5659 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5660 } 5661 5662 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5663 uint32_t reg_val_offs) 5664 { 5665 struct amdgpu_device *adev = ring->adev; 5666 5667 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5668 amdgpu_ring_write(ring, 0 | /* src: register*/ 5669 (5 << 8) | /* dst: memory */ 5670 (1 << 20)); /* write confirm */ 5671 amdgpu_ring_write(ring, reg); 5672 amdgpu_ring_write(ring, 0); 5673 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5674 reg_val_offs * 4)); 5675 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5676 reg_val_offs * 4)); 5677 } 5678 5679 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5680 uint32_t val) 5681 { 5682 uint32_t cmd = 0; 5683 5684 switch (ring->funcs->type) { 5685 case AMDGPU_RING_TYPE_GFX: 5686 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5687 break; 5688 case AMDGPU_RING_TYPE_KIQ: 5689 cmd = (1 << 16); /* no inc addr */ 5690 break; 5691 default: 5692 cmd = WR_CONFIRM; 5693 break; 5694 } 5695 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5696 amdgpu_ring_write(ring, cmd); 5697 amdgpu_ring_write(ring, reg); 5698 amdgpu_ring_write(ring, 0); 5699 amdgpu_ring_write(ring, val); 5700 } 5701 5702 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5703 uint32_t val, uint32_t mask) 5704 { 5705 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5706 } 5707 5708 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5709 uint32_t reg0, uint32_t reg1, 5710 uint32_t ref, uint32_t mask) 5711 { 5712 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5713 5714 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5715 ref, mask, 0x20); 5716 } 5717 5718 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5719 unsigned vmid) 5720 { 5721 struct amdgpu_device *adev = ring->adev; 5722 uint32_t value = 0; 5723 5724 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5725 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5726 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5727 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5728 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5729 } 5730 5731 static void 5732 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5733 uint32_t me, uint32_t pipe, 5734 enum amdgpu_interrupt_state state) 5735 { 5736 uint32_t cp_int_cntl, cp_int_cntl_reg; 5737 5738 if (!me) { 5739 switch (pipe) { 5740 case 0: 5741 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5742 break; 5743 case 1: 5744 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5745 break; 5746 default: 5747 DRM_DEBUG("invalid pipe %d\n", pipe); 5748 return; 5749 } 5750 } else { 5751 DRM_DEBUG("invalid me %d\n", me); 5752 return; 5753 } 5754 5755 switch (state) { 5756 case AMDGPU_IRQ_STATE_DISABLE: 5757 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5758 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5759 TIME_STAMP_INT_ENABLE, 0); 5760 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5761 GENERIC0_INT_ENABLE, 0); 5762 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5763 break; 5764 case AMDGPU_IRQ_STATE_ENABLE: 5765 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5766 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5767 TIME_STAMP_INT_ENABLE, 1); 5768 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5769 GENERIC0_INT_ENABLE, 1); 5770 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5771 break; 5772 default: 5773 break; 5774 } 5775 } 5776 5777 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5778 int me, int pipe, 5779 enum amdgpu_interrupt_state state) 5780 { 5781 u32 mec_int_cntl, mec_int_cntl_reg; 5782 5783 /* 5784 * amdgpu controls only the first MEC. That's why this function only 5785 * handles the setting of interrupts for this specific MEC. All other 5786 * pipes' interrupts are set by amdkfd. 5787 */ 5788 5789 if (me == 1) { 5790 switch (pipe) { 5791 case 0: 5792 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5793 break; 5794 case 1: 5795 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5796 break; 5797 case 2: 5798 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5799 break; 5800 case 3: 5801 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5802 break; 5803 default: 5804 DRM_DEBUG("invalid pipe %d\n", pipe); 5805 return; 5806 } 5807 } else { 5808 DRM_DEBUG("invalid me %d\n", me); 5809 return; 5810 } 5811 5812 switch (state) { 5813 case AMDGPU_IRQ_STATE_DISABLE: 5814 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5815 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5816 TIME_STAMP_INT_ENABLE, 0); 5817 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5818 GENERIC0_INT_ENABLE, 0); 5819 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5820 break; 5821 case AMDGPU_IRQ_STATE_ENABLE: 5822 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5823 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5824 TIME_STAMP_INT_ENABLE, 1); 5825 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5826 GENERIC0_INT_ENABLE, 1); 5827 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5828 break; 5829 default: 5830 break; 5831 } 5832 } 5833 5834 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5835 struct amdgpu_irq_src *src, 5836 unsigned type, 5837 enum amdgpu_interrupt_state state) 5838 { 5839 switch (type) { 5840 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5841 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5842 break; 5843 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5844 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5845 break; 5846 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5847 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5848 break; 5849 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5850 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5851 break; 5852 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5853 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5854 break; 5855 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5856 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5857 break; 5858 default: 5859 break; 5860 } 5861 return 0; 5862 } 5863 5864 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5865 struct amdgpu_irq_src *source, 5866 struct amdgpu_iv_entry *entry) 5867 { 5868 int i; 5869 u8 me_id, pipe_id, queue_id; 5870 struct amdgpu_ring *ring; 5871 uint32_t mes_queue_id = entry->src_data[0]; 5872 5873 DRM_DEBUG("IH: CP EOP\n"); 5874 5875 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5876 struct amdgpu_mes_queue *queue; 5877 5878 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5879 5880 spin_lock(&adev->mes.queue_id_lock); 5881 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5882 if (queue) { 5883 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5884 amdgpu_fence_process(queue->ring); 5885 } 5886 spin_unlock(&adev->mes.queue_id_lock); 5887 } else { 5888 me_id = (entry->ring_id & 0x0c) >> 2; 5889 pipe_id = (entry->ring_id & 0x03) >> 0; 5890 queue_id = (entry->ring_id & 0x70) >> 4; 5891 5892 switch (me_id) { 5893 case 0: 5894 if (pipe_id == 0) 5895 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5896 else 5897 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5898 break; 5899 case 1: 5900 case 2: 5901 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5902 ring = &adev->gfx.compute_ring[i]; 5903 /* Per-queue interrupt is supported for MEC starting from VI. 5904 * The interrupt can only be enabled/disabled per pipe instead 5905 * of per queue. 5906 */ 5907 if ((ring->me == me_id) && 5908 (ring->pipe == pipe_id) && 5909 (ring->queue == queue_id)) 5910 amdgpu_fence_process(ring); 5911 } 5912 break; 5913 } 5914 } 5915 5916 return 0; 5917 } 5918 5919 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5920 struct amdgpu_irq_src *source, 5921 unsigned type, 5922 enum amdgpu_interrupt_state state) 5923 { 5924 switch (state) { 5925 case AMDGPU_IRQ_STATE_DISABLE: 5926 case AMDGPU_IRQ_STATE_ENABLE: 5927 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5928 PRIV_REG_INT_ENABLE, 5929 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5930 break; 5931 default: 5932 break; 5933 } 5934 5935 return 0; 5936 } 5937 5938 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5939 struct amdgpu_irq_src *source, 5940 unsigned type, 5941 enum amdgpu_interrupt_state state) 5942 { 5943 switch (state) { 5944 case AMDGPU_IRQ_STATE_DISABLE: 5945 case AMDGPU_IRQ_STATE_ENABLE: 5946 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5947 PRIV_INSTR_INT_ENABLE, 5948 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5949 break; 5950 default: 5951 break; 5952 } 5953 5954 return 0; 5955 } 5956 5957 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5958 struct amdgpu_iv_entry *entry) 5959 { 5960 u8 me_id, pipe_id, queue_id; 5961 struct amdgpu_ring *ring; 5962 int i; 5963 5964 me_id = (entry->ring_id & 0x0c) >> 2; 5965 pipe_id = (entry->ring_id & 0x03) >> 0; 5966 queue_id = (entry->ring_id & 0x70) >> 4; 5967 5968 switch (me_id) { 5969 case 0: 5970 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5971 ring = &adev->gfx.gfx_ring[i]; 5972 /* we only enabled 1 gfx queue per pipe for now */ 5973 if (ring->me == me_id && ring->pipe == pipe_id) 5974 drm_sched_fault(&ring->sched); 5975 } 5976 break; 5977 case 1: 5978 case 2: 5979 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5980 ring = &adev->gfx.compute_ring[i]; 5981 if (ring->me == me_id && ring->pipe == pipe_id && 5982 ring->queue == queue_id) 5983 drm_sched_fault(&ring->sched); 5984 } 5985 break; 5986 default: 5987 BUG(); 5988 break; 5989 } 5990 } 5991 5992 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 5993 struct amdgpu_irq_src *source, 5994 struct amdgpu_iv_entry *entry) 5995 { 5996 DRM_ERROR("Illegal register access in command stream\n"); 5997 gfx_v11_0_handle_priv_fault(adev, entry); 5998 return 0; 5999 } 6000 6001 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6002 struct amdgpu_irq_src *source, 6003 struct amdgpu_iv_entry *entry) 6004 { 6005 DRM_ERROR("Illegal instruction in command stream\n"); 6006 gfx_v11_0_handle_priv_fault(adev, entry); 6007 return 0; 6008 } 6009 6010 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6011 struct amdgpu_irq_src *source, 6012 struct amdgpu_iv_entry *entry) 6013 { 6014 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6015 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6016 6017 return 0; 6018 } 6019 6020 #if 0 6021 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6022 struct amdgpu_irq_src *src, 6023 unsigned int type, 6024 enum amdgpu_interrupt_state state) 6025 { 6026 uint32_t tmp, target; 6027 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6028 6029 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6030 target += ring->pipe; 6031 6032 switch (type) { 6033 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6034 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6035 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6036 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6037 GENERIC2_INT_ENABLE, 0); 6038 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6039 6040 tmp = RREG32_SOC15_IP(GC, target); 6041 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6042 GENERIC2_INT_ENABLE, 0); 6043 WREG32_SOC15_IP(GC, target, tmp); 6044 } else { 6045 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6046 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6047 GENERIC2_INT_ENABLE, 1); 6048 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6049 6050 tmp = RREG32_SOC15_IP(GC, target); 6051 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6052 GENERIC2_INT_ENABLE, 1); 6053 WREG32_SOC15_IP(GC, target, tmp); 6054 } 6055 break; 6056 default: 6057 BUG(); /* kiq only support GENERIC2_INT now */ 6058 break; 6059 } 6060 return 0; 6061 } 6062 #endif 6063 6064 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6065 { 6066 const unsigned int gcr_cntl = 6067 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6068 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6069 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6070 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6075 6076 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6077 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6078 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6079 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6080 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6081 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6082 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6083 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6084 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6085 } 6086 6087 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6088 .name = "gfx_v11_0", 6089 .early_init = gfx_v11_0_early_init, 6090 .late_init = gfx_v11_0_late_init, 6091 .sw_init = gfx_v11_0_sw_init, 6092 .sw_fini = gfx_v11_0_sw_fini, 6093 .hw_init = gfx_v11_0_hw_init, 6094 .hw_fini = gfx_v11_0_hw_fini, 6095 .suspend = gfx_v11_0_suspend, 6096 .resume = gfx_v11_0_resume, 6097 .is_idle = gfx_v11_0_is_idle, 6098 .wait_for_idle = gfx_v11_0_wait_for_idle, 6099 .soft_reset = gfx_v11_0_soft_reset, 6100 .check_soft_reset = gfx_v11_0_check_soft_reset, 6101 .post_soft_reset = gfx_v11_0_post_soft_reset, 6102 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6103 .set_powergating_state = gfx_v11_0_set_powergating_state, 6104 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6105 }; 6106 6107 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6108 .type = AMDGPU_RING_TYPE_GFX, 6109 .align_mask = 0xff, 6110 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6111 .support_64bit_ptrs = true, 6112 .secure_submission_supported = true, 6113 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6114 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6115 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6116 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6117 5 + /* COND_EXEC */ 6118 9 + /* SET_Q_PREEMPTION_MODE */ 6119 7 + /* PIPELINE_SYNC */ 6120 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6121 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6122 2 + /* VM_FLUSH */ 6123 8 + /* FENCE for VM_FLUSH */ 6124 20 + /* GDS switch */ 6125 5 + /* COND_EXEC */ 6126 7 + /* HDP_flush */ 6127 4 + /* VGT_flush */ 6128 31 + /* DE_META */ 6129 3 + /* CNTX_CTRL */ 6130 5 + /* HDP_INVL */ 6131 8 + 8 + /* FENCE x2 */ 6132 8, /* gfx_v11_0_emit_mem_sync */ 6133 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6134 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6135 .emit_fence = gfx_v11_0_ring_emit_fence, 6136 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6137 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6138 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6139 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6140 .test_ring = gfx_v11_0_ring_test_ring, 6141 .test_ib = gfx_v11_0_ring_test_ib, 6142 .insert_nop = amdgpu_ring_insert_nop, 6143 .pad_ib = amdgpu_ring_generic_pad_ib, 6144 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6145 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6146 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6147 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6148 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6149 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6150 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6151 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6152 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6153 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6154 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6155 }; 6156 6157 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6158 .type = AMDGPU_RING_TYPE_COMPUTE, 6159 .align_mask = 0xff, 6160 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6161 .support_64bit_ptrs = true, 6162 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6163 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6164 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6165 .emit_frame_size = 6166 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6167 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6168 5 + /* hdp invalidate */ 6169 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6170 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6171 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6172 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6173 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6174 8, /* gfx_v11_0_emit_mem_sync */ 6175 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6176 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6177 .emit_fence = gfx_v11_0_ring_emit_fence, 6178 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6179 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6180 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6181 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6182 .test_ring = gfx_v11_0_ring_test_ring, 6183 .test_ib = gfx_v11_0_ring_test_ib, 6184 .insert_nop = amdgpu_ring_insert_nop, 6185 .pad_ib = amdgpu_ring_generic_pad_ib, 6186 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6187 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6188 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6189 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6190 }; 6191 6192 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6193 .type = AMDGPU_RING_TYPE_KIQ, 6194 .align_mask = 0xff, 6195 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6196 .support_64bit_ptrs = true, 6197 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6198 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6199 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6200 .emit_frame_size = 6201 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6202 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6203 5 + /*hdp invalidate */ 6204 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6205 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6206 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6207 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6208 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6209 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6210 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6211 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6212 .test_ring = gfx_v11_0_ring_test_ring, 6213 .test_ib = gfx_v11_0_ring_test_ib, 6214 .insert_nop = amdgpu_ring_insert_nop, 6215 .pad_ib = amdgpu_ring_generic_pad_ib, 6216 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6217 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6218 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6219 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6220 }; 6221 6222 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6223 { 6224 int i; 6225 6226 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6227 6228 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6229 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6230 6231 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6232 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6233 } 6234 6235 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6236 .set = gfx_v11_0_set_eop_interrupt_state, 6237 .process = gfx_v11_0_eop_irq, 6238 }; 6239 6240 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6241 .set = gfx_v11_0_set_priv_reg_fault_state, 6242 .process = gfx_v11_0_priv_reg_irq, 6243 }; 6244 6245 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6246 .set = gfx_v11_0_set_priv_inst_fault_state, 6247 .process = gfx_v11_0_priv_inst_irq, 6248 }; 6249 6250 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6251 .process = gfx_v11_0_rlc_gc_fed_irq, 6252 }; 6253 6254 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6255 { 6256 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6257 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6258 6259 adev->gfx.priv_reg_irq.num_types = 1; 6260 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6261 6262 adev->gfx.priv_inst_irq.num_types = 1; 6263 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6264 6265 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6266 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6267 6268 } 6269 6270 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6271 { 6272 if (adev->flags & AMD_IS_APU) 6273 adev->gfx.imu.mode = MISSION_MODE; 6274 else 6275 adev->gfx.imu.mode = DEBUG_MODE; 6276 6277 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6278 } 6279 6280 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6281 { 6282 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6283 } 6284 6285 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6286 { 6287 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6288 adev->gfx.config.max_sh_per_se * 6289 adev->gfx.config.max_shader_engines; 6290 6291 adev->gds.gds_size = 0x1000; 6292 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6293 adev->gds.gws_size = 64; 6294 adev->gds.oa_size = 16; 6295 } 6296 6297 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6298 { 6299 /* set gfx eng mqd */ 6300 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6301 sizeof(struct v11_gfx_mqd); 6302 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6303 gfx_v11_0_gfx_mqd_init; 6304 /* set compute eng mqd */ 6305 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6306 sizeof(struct v11_compute_mqd); 6307 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6308 gfx_v11_0_compute_mqd_init; 6309 } 6310 6311 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6312 u32 bitmap) 6313 { 6314 u32 data; 6315 6316 if (!bitmap) 6317 return; 6318 6319 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6320 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6321 6322 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6323 } 6324 6325 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6326 { 6327 u32 data, wgp_bitmask; 6328 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6329 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6330 6331 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6332 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6333 6334 wgp_bitmask = 6335 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6336 6337 return (~data) & wgp_bitmask; 6338 } 6339 6340 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6341 { 6342 u32 wgp_idx, wgp_active_bitmap; 6343 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6344 6345 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6346 cu_active_bitmap = 0; 6347 6348 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6349 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6350 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6351 if (wgp_active_bitmap & (1 << wgp_idx)) 6352 cu_active_bitmap |= cu_bitmap_per_wgp; 6353 } 6354 6355 return cu_active_bitmap; 6356 } 6357 6358 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6359 struct amdgpu_cu_info *cu_info) 6360 { 6361 int i, j, k, counter, active_cu_number = 0; 6362 u32 mask, bitmap; 6363 unsigned disable_masks[8 * 2]; 6364 6365 if (!adev || !cu_info) 6366 return -EINVAL; 6367 6368 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6369 6370 mutex_lock(&adev->grbm_idx_mutex); 6371 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6372 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6373 mask = 1; 6374 counter = 0; 6375 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6376 if (i < 8 && j < 2) 6377 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6378 adev, disable_masks[i * 2 + j]); 6379 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6380 6381 /** 6382 * GFX11 could support more than 4 SEs, while the bitmap 6383 * in cu_info struct is 4x4 and ioctl interface struct 6384 * drm_amdgpu_info_device should keep stable. 6385 * So we use last two columns of bitmap to store cu mask for 6386 * SEs 4 to 7, the layout of the bitmap is as below: 6387 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6388 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6389 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6390 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6391 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6392 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6393 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6394 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6395 */ 6396 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 6397 6398 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6399 if (bitmap & mask) 6400 counter++; 6401 6402 mask <<= 1; 6403 } 6404 active_cu_number += counter; 6405 } 6406 } 6407 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6408 mutex_unlock(&adev->grbm_idx_mutex); 6409 6410 cu_info->number = active_cu_number; 6411 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6412 6413 return 0; 6414 } 6415 6416 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6417 { 6418 .type = AMD_IP_BLOCK_TYPE_GFX, 6419 .major = 11, 6420 .minor = 0, 6421 .rev = 0, 6422 .funcs = &gfx_v11_0_ip_funcs, 6423 }; 6424