1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 #define regPC_CONFIG_CNTL_1 0x194d 64 #define regPC_CONFIG_CNTL_1_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin"); 89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin"); 91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin"); 92 93 static const struct soc15_reg_golden golden_settings_gc_11_0[] = { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000) 95 }; 96 97 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 98 { 99 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 108 }; 109 110 #define DEFAULT_SH_MEM_CONFIG \ 111 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 112 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 113 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 114 115 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 116 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 117 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 118 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 119 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 120 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 121 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 122 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 123 struct amdgpu_cu_info *cu_info); 124 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 125 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 126 u32 sh_num, u32 instance, int xcc_id); 127 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 128 129 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 130 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 131 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 132 uint32_t val); 133 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 134 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 135 uint16_t pasid, uint32_t flush_type, 136 bool all_hub, uint8_t dst_sel); 137 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 138 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 139 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 140 bool enable); 141 142 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 143 { 144 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 145 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 146 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ 147 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 148 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 149 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 150 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 151 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 152 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 153 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 154 } 155 156 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 157 struct amdgpu_ring *ring) 158 { 159 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 160 uint64_t wptr_addr = ring->wptr_gpu_addr; 161 uint32_t me = 0, eng_sel = 0; 162 163 switch (ring->funcs->type) { 164 case AMDGPU_RING_TYPE_COMPUTE: 165 me = 1; 166 eng_sel = 0; 167 break; 168 case AMDGPU_RING_TYPE_GFX: 169 me = 0; 170 eng_sel = 4; 171 break; 172 case AMDGPU_RING_TYPE_MES: 173 me = 2; 174 eng_sel = 5; 175 break; 176 default: 177 WARN_ON(1); 178 } 179 180 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 181 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 182 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 183 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 184 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 185 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 186 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 187 PACKET3_MAP_QUEUES_ME((me)) | 188 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 189 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 190 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 191 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 192 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 193 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 194 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 195 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 196 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 197 } 198 199 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring, 201 enum amdgpu_unmap_queues_action action, 202 u64 gpu_addr, u64 seq) 203 { 204 struct amdgpu_device *adev = kiq_ring->adev; 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 208 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 209 return; 210 } 211 212 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 213 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 214 PACKET3_UNMAP_QUEUES_ACTION(action) | 215 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 216 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 217 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 218 amdgpu_ring_write(kiq_ring, 219 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 220 221 if (action == PREEMPT_QUEUES_NO_UNMAP) { 222 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 223 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 224 amdgpu_ring_write(kiq_ring, seq); 225 } else { 226 amdgpu_ring_write(kiq_ring, 0); 227 amdgpu_ring_write(kiq_ring, 0); 228 amdgpu_ring_write(kiq_ring, 0); 229 } 230 } 231 232 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 233 struct amdgpu_ring *ring, 234 u64 addr, 235 u64 seq) 236 { 237 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 238 239 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 240 amdgpu_ring_write(kiq_ring, 241 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 242 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 243 PACKET3_QUERY_STATUS_COMMAND(2)); 244 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 245 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 246 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 247 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 249 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 250 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 251 } 252 253 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 254 uint16_t pasid, uint32_t flush_type, 255 bool all_hub) 256 { 257 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 258 } 259 260 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 261 .kiq_set_resources = gfx11_kiq_set_resources, 262 .kiq_map_queues = gfx11_kiq_map_queues, 263 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 264 .kiq_query_status = gfx11_kiq_query_status, 265 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 266 .set_resources_size = 8, 267 .map_queues_size = 7, 268 .unmap_queues_size = 6, 269 .query_status_size = 7, 270 .invalidate_tlbs_size = 2, 271 }; 272 273 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 274 { 275 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 276 } 277 278 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 279 { 280 if (amdgpu_sriov_vf(adev)) 281 return; 282 283 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 284 case IP_VERSION(11, 0, 1): 285 case IP_VERSION(11, 0, 4): 286 soc15_program_register_sequence(adev, 287 golden_settings_gc_11_0_1, 288 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 289 break; 290 default: 291 break; 292 } 293 soc15_program_register_sequence(adev, 294 golden_settings_gc_11_0, 295 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 296 297 } 298 299 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 300 bool wc, uint32_t reg, uint32_t val) 301 { 302 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 303 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 304 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 305 amdgpu_ring_write(ring, reg); 306 amdgpu_ring_write(ring, 0); 307 amdgpu_ring_write(ring, val); 308 } 309 310 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 311 int mem_space, int opt, uint32_t addr0, 312 uint32_t addr1, uint32_t ref, uint32_t mask, 313 uint32_t inv) 314 { 315 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 316 amdgpu_ring_write(ring, 317 /* memory (1) or register (0) */ 318 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 319 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 320 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 321 WAIT_REG_MEM_ENGINE(eng_sel))); 322 323 if (mem_space) 324 BUG_ON(addr0 & 0x3); /* Dword align */ 325 amdgpu_ring_write(ring, addr0); 326 amdgpu_ring_write(ring, addr1); 327 amdgpu_ring_write(ring, ref); 328 amdgpu_ring_write(ring, mask); 329 amdgpu_ring_write(ring, inv); /* poll interval */ 330 } 331 332 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 333 { 334 struct amdgpu_device *adev = ring->adev; 335 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 336 uint32_t tmp = 0; 337 unsigned i; 338 int r; 339 340 WREG32(scratch, 0xCAFEDEAD); 341 r = amdgpu_ring_alloc(ring, 5); 342 if (r) { 343 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 344 ring->idx, r); 345 return r; 346 } 347 348 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 349 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 350 } else { 351 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 352 amdgpu_ring_write(ring, scratch - 353 PACKET3_SET_UCONFIG_REG_START); 354 amdgpu_ring_write(ring, 0xDEADBEEF); 355 } 356 amdgpu_ring_commit(ring); 357 358 for (i = 0; i < adev->usec_timeout; i++) { 359 tmp = RREG32(scratch); 360 if (tmp == 0xDEADBEEF) 361 break; 362 if (amdgpu_emu_mode == 1) 363 msleep(1); 364 else 365 udelay(1); 366 } 367 368 if (i >= adev->usec_timeout) 369 r = -ETIMEDOUT; 370 return r; 371 } 372 373 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 374 { 375 struct amdgpu_device *adev = ring->adev; 376 struct amdgpu_ib ib; 377 struct dma_fence *f = NULL; 378 unsigned index; 379 uint64_t gpu_addr; 380 volatile uint32_t *cpu_ptr; 381 long r; 382 383 /* MES KIQ fw hasn't indirect buffer support for now */ 384 if (adev->enable_mes_kiq && 385 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 386 return 0; 387 388 memset(&ib, 0, sizeof(ib)); 389 390 if (ring->is_mes_queue) { 391 uint32_t padding, offset; 392 393 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 394 padding = amdgpu_mes_ctx_get_offs(ring, 395 AMDGPU_MES_CTX_PADDING_OFFS); 396 397 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 398 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 399 400 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 401 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 402 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 403 } else { 404 r = amdgpu_device_wb_get(adev, &index); 405 if (r) 406 return r; 407 408 gpu_addr = adev->wb.gpu_addr + (index * 4); 409 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 410 cpu_ptr = &adev->wb.wb[index]; 411 412 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 413 if (r) { 414 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 415 goto err1; 416 } 417 } 418 419 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 420 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 421 ib.ptr[2] = lower_32_bits(gpu_addr); 422 ib.ptr[3] = upper_32_bits(gpu_addr); 423 ib.ptr[4] = 0xDEADBEEF; 424 ib.length_dw = 5; 425 426 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 427 if (r) 428 goto err2; 429 430 r = dma_fence_wait_timeout(f, false, timeout); 431 if (r == 0) { 432 r = -ETIMEDOUT; 433 goto err2; 434 } else if (r < 0) { 435 goto err2; 436 } 437 438 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 439 r = 0; 440 else 441 r = -EINVAL; 442 err2: 443 if (!ring->is_mes_queue) 444 amdgpu_ib_free(adev, &ib, NULL); 445 dma_fence_put(f); 446 err1: 447 if (!ring->is_mes_queue) 448 amdgpu_device_wb_free(adev, index); 449 return r; 450 } 451 452 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 453 { 454 amdgpu_ucode_release(&adev->gfx.pfp_fw); 455 amdgpu_ucode_release(&adev->gfx.me_fw); 456 amdgpu_ucode_release(&adev->gfx.rlc_fw); 457 amdgpu_ucode_release(&adev->gfx.mec_fw); 458 459 kfree(adev->gfx.rlc.register_list_format); 460 } 461 462 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 463 { 464 const struct psp_firmware_header_v1_0 *toc_hdr; 465 int err = 0; 466 char fw_name[40]; 467 468 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 469 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 470 if (err) 471 goto out; 472 473 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 474 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 475 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 476 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 477 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 478 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 479 return 0; 480 out: 481 amdgpu_ucode_release(&adev->psp.toc_fw); 482 return err; 483 } 484 485 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 486 { 487 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 488 case IP_VERSION(11, 0, 0): 489 case IP_VERSION(11, 0, 2): 490 case IP_VERSION(11, 0, 3): 491 if ((adev->gfx.me_fw_version >= 1505) && 492 (adev->gfx.pfp_fw_version >= 1600) && 493 (adev->gfx.mec_fw_version >= 512)) { 494 if (amdgpu_sriov_vf(adev)) 495 adev->gfx.cp_gfx_shadow = true; 496 else 497 adev->gfx.cp_gfx_shadow = false; 498 } 499 break; 500 default: 501 adev->gfx.cp_gfx_shadow = false; 502 break; 503 } 504 } 505 506 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 507 { 508 char fw_name[40]; 509 char ucode_prefix[30]; 510 int err; 511 const struct rlc_firmware_header_v2_0 *rlc_hdr; 512 uint16_t version_major; 513 uint16_t version_minor; 514 515 DRM_DEBUG("\n"); 516 517 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 518 519 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 520 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 521 if (err) 522 goto out; 523 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 524 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 525 (union amdgpu_firmware_header *) 526 adev->gfx.pfp_fw->data, 2, 0); 527 if (adev->gfx.rs64_enable) { 528 dev_info(adev->dev, "CP RS64 enable\n"); 529 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 530 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 531 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 532 } else { 533 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 534 } 535 536 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 537 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 538 if (err) 539 goto out; 540 if (adev->gfx.rs64_enable) { 541 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 542 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 543 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 544 } else { 545 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 546 } 547 548 if (!amdgpu_sriov_vf(adev)) { 549 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && 550 adev->pdev->revision == 0xCE) 551 snprintf(fw_name, sizeof(fw_name), "amdgpu/gc_11_0_0_rlc_1.bin"); 552 else 553 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 554 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 555 if (err) 556 goto out; 557 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 558 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 559 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 560 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 561 if (err) 562 goto out; 563 } 564 565 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 567 if (err) 568 goto out; 569 if (adev->gfx.rs64_enable) { 570 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 571 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 572 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 573 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 574 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 575 } else { 576 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 577 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 578 } 579 580 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 581 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 582 583 /* only one MEC for gfx 11.0.0. */ 584 adev->gfx.mec2_fw = NULL; 585 586 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 587 588 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { 589 err = adev->gfx.imu.funcs->init_microcode(adev); 590 if (err) 591 DRM_ERROR("Failed to init imu firmware!\n"); 592 return err; 593 } 594 595 out: 596 if (err) { 597 amdgpu_ucode_release(&adev->gfx.pfp_fw); 598 amdgpu_ucode_release(&adev->gfx.me_fw); 599 amdgpu_ucode_release(&adev->gfx.rlc_fw); 600 amdgpu_ucode_release(&adev->gfx.mec_fw); 601 } 602 603 return err; 604 } 605 606 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 607 { 608 u32 count = 0; 609 const struct cs_section_def *sect = NULL; 610 const struct cs_extent_def *ext = NULL; 611 612 /* begin clear state */ 613 count += 2; 614 /* context control state */ 615 count += 3; 616 617 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 618 for (ext = sect->section; ext->extent != NULL; ++ext) { 619 if (sect->id == SECT_CONTEXT) 620 count += 2 + ext->reg_count; 621 else 622 return 0; 623 } 624 } 625 626 /* set PA_SC_TILE_STEERING_OVERRIDE */ 627 count += 3; 628 /* end clear state */ 629 count += 2; 630 /* clear state */ 631 count += 2; 632 633 return count; 634 } 635 636 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 637 volatile u32 *buffer) 638 { 639 u32 count = 0, i; 640 const struct cs_section_def *sect = NULL; 641 const struct cs_extent_def *ext = NULL; 642 int ctx_reg_offset; 643 644 if (adev->gfx.rlc.cs_data == NULL) 645 return; 646 if (buffer == NULL) 647 return; 648 649 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 650 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 651 652 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 653 buffer[count++] = cpu_to_le32(0x80000000); 654 buffer[count++] = cpu_to_le32(0x80000000); 655 656 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 657 for (ext = sect->section; ext->extent != NULL; ++ext) { 658 if (sect->id == SECT_CONTEXT) { 659 buffer[count++] = 660 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 661 buffer[count++] = cpu_to_le32(ext->reg_index - 662 PACKET3_SET_CONTEXT_REG_START); 663 for (i = 0; i < ext->reg_count; i++) 664 buffer[count++] = cpu_to_le32(ext->extent[i]); 665 } else { 666 return; 667 } 668 } 669 } 670 671 ctx_reg_offset = 672 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 673 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 674 buffer[count++] = cpu_to_le32(ctx_reg_offset); 675 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 676 677 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 678 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 679 680 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 681 buffer[count++] = cpu_to_le32(0); 682 } 683 684 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 685 { 686 /* clear state block */ 687 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 688 &adev->gfx.rlc.clear_state_gpu_addr, 689 (void **)&adev->gfx.rlc.cs_ptr); 690 691 /* jump table block */ 692 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 693 &adev->gfx.rlc.cp_table_gpu_addr, 694 (void **)&adev->gfx.rlc.cp_table_ptr); 695 } 696 697 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 698 { 699 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 700 701 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 702 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 703 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 704 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 705 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 706 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 707 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 708 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 709 adev->gfx.rlc.rlcg_reg_access_supported = true; 710 } 711 712 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 713 { 714 const struct cs_section_def *cs_data; 715 int r; 716 717 adev->gfx.rlc.cs_data = gfx11_cs_data; 718 719 cs_data = adev->gfx.rlc.cs_data; 720 721 if (cs_data) { 722 /* init clear state block */ 723 r = amdgpu_gfx_rlc_init_csb(adev); 724 if (r) 725 return r; 726 } 727 728 /* init spm vmid with 0xf */ 729 if (adev->gfx.rlc.funcs->update_spm_vmid) 730 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 731 732 return 0; 733 } 734 735 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 736 { 737 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 738 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 739 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 740 } 741 742 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 743 { 744 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 745 746 amdgpu_gfx_graphics_queue_acquire(adev); 747 } 748 749 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 750 { 751 int r; 752 u32 *hpd; 753 size_t mec_hpd_size; 754 755 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 756 757 /* take ownership of the relevant compute queues */ 758 amdgpu_gfx_compute_queue_acquire(adev); 759 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 760 761 if (mec_hpd_size) { 762 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 763 AMDGPU_GEM_DOMAIN_GTT, 764 &adev->gfx.mec.hpd_eop_obj, 765 &adev->gfx.mec.hpd_eop_gpu_addr, 766 (void **)&hpd); 767 if (r) { 768 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 769 gfx_v11_0_mec_fini(adev); 770 return r; 771 } 772 773 memset(hpd, 0, mec_hpd_size); 774 775 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 776 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 777 } 778 779 return 0; 780 } 781 782 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 783 { 784 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 785 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 786 (address << SQ_IND_INDEX__INDEX__SHIFT)); 787 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 788 } 789 790 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 791 uint32_t thread, uint32_t regno, 792 uint32_t num, uint32_t *out) 793 { 794 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 795 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 796 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 797 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 798 (SQ_IND_INDEX__AUTO_INCR_MASK)); 799 while (num--) 800 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 801 } 802 803 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 804 { 805 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 806 * field when performing a select_se_sh so it should be 807 * zero here */ 808 WARN_ON(simd != 0); 809 810 /* type 3 wave data */ 811 dst[(*no_fields)++] = 3; 812 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 827 } 828 829 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 830 uint32_t wave, uint32_t start, 831 uint32_t size, uint32_t *dst) 832 { 833 WARN_ON(simd != 0); 834 835 wave_read_regs( 836 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 837 dst); 838 } 839 840 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 841 uint32_t wave, uint32_t thread, 842 uint32_t start, uint32_t size, 843 uint32_t *dst) 844 { 845 wave_read_regs( 846 adev, wave, thread, 847 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 848 } 849 850 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 851 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 852 { 853 soc21_grbm_select(adev, me, pipe, q, vm); 854 } 855 856 /* all sizes are in bytes */ 857 #define MQD_SHADOW_BASE_SIZE 73728 858 #define MQD_SHADOW_BASE_ALIGNMENT 256 859 #define MQD_FWWORKAREA_SIZE 484 860 #define MQD_FWWORKAREA_ALIGNMENT 256 861 862 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 863 struct amdgpu_gfx_shadow_info *shadow_info) 864 { 865 if (adev->gfx.cp_gfx_shadow) { 866 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 867 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 868 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 869 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 870 return 0; 871 } else { 872 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 873 return -ENOTSUPP; 874 } 875 } 876 877 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 878 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 879 .select_se_sh = &gfx_v11_0_select_se_sh, 880 .read_wave_data = &gfx_v11_0_read_wave_data, 881 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 882 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 883 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 884 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 885 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 886 }; 887 888 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 889 { 890 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 891 case IP_VERSION(11, 0, 0): 892 case IP_VERSION(11, 0, 2): 893 adev->gfx.config.max_hw_contexts = 8; 894 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 895 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 896 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 897 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 898 break; 899 case IP_VERSION(11, 0, 3): 900 adev->gfx.ras = &gfx_v11_0_3_ras; 901 adev->gfx.config.max_hw_contexts = 8; 902 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 903 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 904 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 905 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 906 break; 907 case IP_VERSION(11, 0, 1): 908 case IP_VERSION(11, 0, 4): 909 case IP_VERSION(11, 5, 0): 910 adev->gfx.config.max_hw_contexts = 8; 911 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 912 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 913 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 914 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 915 break; 916 default: 917 BUG(); 918 break; 919 } 920 921 return 0; 922 } 923 924 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 925 int me, int pipe, int queue) 926 { 927 int r; 928 struct amdgpu_ring *ring; 929 unsigned int irq_type; 930 931 ring = &adev->gfx.gfx_ring[ring_id]; 932 933 ring->me = me; 934 ring->pipe = pipe; 935 ring->queue = queue; 936 937 ring->ring_obj = NULL; 938 ring->use_doorbell = true; 939 940 if (!ring_id) 941 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 942 else 943 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 944 ring->vm_hub = AMDGPU_GFXHUB(0); 945 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 946 947 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 948 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 949 AMDGPU_RING_PRIO_DEFAULT, NULL); 950 if (r) 951 return r; 952 return 0; 953 } 954 955 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 956 int mec, int pipe, int queue) 957 { 958 int r; 959 unsigned irq_type; 960 struct amdgpu_ring *ring; 961 unsigned int hw_prio; 962 963 ring = &adev->gfx.compute_ring[ring_id]; 964 965 /* mec0 is me1 */ 966 ring->me = mec + 1; 967 ring->pipe = pipe; 968 ring->queue = queue; 969 970 ring->ring_obj = NULL; 971 ring->use_doorbell = true; 972 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 973 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 974 + (ring_id * GFX11_MEC_HPD_SIZE); 975 ring->vm_hub = AMDGPU_GFXHUB(0); 976 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 977 978 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 979 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 980 + ring->pipe; 981 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 982 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 983 /* type-2 packets are deprecated on MEC, use type-3 instead */ 984 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 985 hw_prio, NULL); 986 if (r) 987 return r; 988 989 return 0; 990 } 991 992 static struct { 993 SOC21_FIRMWARE_ID id; 994 unsigned int offset; 995 unsigned int size; 996 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 997 998 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 999 { 1000 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1001 1002 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1003 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1004 rlc_autoload_info[ucode->id].id = ucode->id; 1005 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1006 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1007 1008 ucode++; 1009 } 1010 } 1011 1012 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1013 { 1014 uint32_t total_size = 0; 1015 SOC21_FIRMWARE_ID id; 1016 1017 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1018 1019 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1020 total_size += rlc_autoload_info[id].size; 1021 1022 /* In case the offset in rlc toc ucode is aligned */ 1023 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1024 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1025 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1026 1027 return total_size; 1028 } 1029 1030 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1031 { 1032 int r; 1033 uint32_t total_size; 1034 1035 total_size = gfx_v11_0_calc_toc_total_size(adev); 1036 1037 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1038 AMDGPU_GEM_DOMAIN_VRAM | 1039 AMDGPU_GEM_DOMAIN_GTT, 1040 &adev->gfx.rlc.rlc_autoload_bo, 1041 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1042 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1043 1044 if (r) { 1045 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1046 return r; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1053 SOC21_FIRMWARE_ID id, 1054 const void *fw_data, 1055 uint32_t fw_size, 1056 uint32_t *fw_autoload_mask) 1057 { 1058 uint32_t toc_offset; 1059 uint32_t toc_fw_size; 1060 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1061 1062 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1063 return; 1064 1065 toc_offset = rlc_autoload_info[id].offset; 1066 toc_fw_size = rlc_autoload_info[id].size; 1067 1068 if (fw_size == 0) 1069 fw_size = toc_fw_size; 1070 1071 if (fw_size > toc_fw_size) 1072 fw_size = toc_fw_size; 1073 1074 memcpy(ptr + toc_offset, fw_data, fw_size); 1075 1076 if (fw_size < toc_fw_size) 1077 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1078 1079 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1080 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1081 } 1082 1083 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1084 uint32_t *fw_autoload_mask) 1085 { 1086 void *data; 1087 uint32_t size; 1088 uint64_t *toc_ptr; 1089 1090 *(uint64_t *)fw_autoload_mask |= 0x1; 1091 1092 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1093 1094 data = adev->psp.toc.start_addr; 1095 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1096 1097 toc_ptr = (uint64_t *)data + size / 8 - 1; 1098 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1099 1100 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1101 data, size, fw_autoload_mask); 1102 } 1103 1104 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1105 uint32_t *fw_autoload_mask) 1106 { 1107 const __le32 *fw_data; 1108 uint32_t fw_size; 1109 const struct gfx_firmware_header_v1_0 *cp_hdr; 1110 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1111 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1112 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1113 uint16_t version_major, version_minor; 1114 1115 if (adev->gfx.rs64_enable) { 1116 /* pfp ucode */ 1117 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1118 adev->gfx.pfp_fw->data; 1119 /* instruction */ 1120 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1121 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1122 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1123 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1124 fw_data, fw_size, fw_autoload_mask); 1125 /* data */ 1126 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1127 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1128 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1129 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1130 fw_data, fw_size, fw_autoload_mask); 1131 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1132 fw_data, fw_size, fw_autoload_mask); 1133 /* me ucode */ 1134 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1135 adev->gfx.me_fw->data; 1136 /* instruction */ 1137 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1138 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1139 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1140 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1141 fw_data, fw_size, fw_autoload_mask); 1142 /* data */ 1143 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1144 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1145 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1146 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1147 fw_data, fw_size, fw_autoload_mask); 1148 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1149 fw_data, fw_size, fw_autoload_mask); 1150 /* mec ucode */ 1151 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1152 adev->gfx.mec_fw->data; 1153 /* instruction */ 1154 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1155 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1156 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1157 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1158 fw_data, fw_size, fw_autoload_mask); 1159 /* data */ 1160 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1161 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1162 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1163 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1164 fw_data, fw_size, fw_autoload_mask); 1165 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1166 fw_data, fw_size, fw_autoload_mask); 1167 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1168 fw_data, fw_size, fw_autoload_mask); 1169 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1170 fw_data, fw_size, fw_autoload_mask); 1171 } else { 1172 /* pfp ucode */ 1173 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1174 adev->gfx.pfp_fw->data; 1175 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1176 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1177 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1178 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1179 fw_data, fw_size, fw_autoload_mask); 1180 1181 /* me ucode */ 1182 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1183 adev->gfx.me_fw->data; 1184 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1185 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1186 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1187 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1188 fw_data, fw_size, fw_autoload_mask); 1189 1190 /* mec ucode */ 1191 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1192 adev->gfx.mec_fw->data; 1193 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1194 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1195 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1196 cp_hdr->jt_size * 4; 1197 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1198 fw_data, fw_size, fw_autoload_mask); 1199 } 1200 1201 /* rlc ucode */ 1202 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1203 adev->gfx.rlc_fw->data; 1204 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1205 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1206 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1207 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1208 fw_data, fw_size, fw_autoload_mask); 1209 1210 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1211 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1212 if (version_major == 2) { 1213 if (version_minor >= 2) { 1214 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1215 1216 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1217 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1218 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1219 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1220 fw_data, fw_size, fw_autoload_mask); 1221 1222 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1223 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1224 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1225 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1226 fw_data, fw_size, fw_autoload_mask); 1227 } 1228 } 1229 } 1230 1231 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1232 uint32_t *fw_autoload_mask) 1233 { 1234 const __le32 *fw_data; 1235 uint32_t fw_size; 1236 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1237 1238 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1239 adev->sdma.instance[0].fw->data; 1240 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1241 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1242 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1243 1244 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1245 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1246 1247 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1248 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1249 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1250 1251 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1252 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1253 } 1254 1255 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1256 uint32_t *fw_autoload_mask) 1257 { 1258 const __le32 *fw_data; 1259 unsigned fw_size; 1260 const struct mes_firmware_header_v1_0 *mes_hdr; 1261 int pipe, ucode_id, data_id; 1262 1263 for (pipe = 0; pipe < 2; pipe++) { 1264 if (pipe==0) { 1265 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1266 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1267 } else { 1268 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1269 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1270 } 1271 1272 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1273 adev->mes.fw[pipe]->data; 1274 1275 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1276 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1277 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1278 1279 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1280 ucode_id, fw_data, fw_size, fw_autoload_mask); 1281 1282 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1283 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1284 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1285 1286 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1287 data_id, fw_data, fw_size, fw_autoload_mask); 1288 } 1289 } 1290 1291 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1292 { 1293 uint32_t rlc_g_offset, rlc_g_size; 1294 uint64_t gpu_addr; 1295 uint32_t autoload_fw_id[2]; 1296 1297 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1298 1299 /* RLC autoload sequence 2: copy ucode */ 1300 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1301 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1302 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1303 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1304 1305 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1306 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1307 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1308 1309 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1310 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1311 1312 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1313 1314 /* RLC autoload sequence 3: load IMU fw */ 1315 if (adev->gfx.imu.funcs->load_microcode) 1316 adev->gfx.imu.funcs->load_microcode(adev); 1317 /* RLC autoload sequence 4 init IMU fw */ 1318 if (adev->gfx.imu.funcs->setup_imu) 1319 adev->gfx.imu.funcs->setup_imu(adev); 1320 if (adev->gfx.imu.funcs->start_imu) 1321 adev->gfx.imu.funcs->start_imu(adev); 1322 1323 /* RLC autoload sequence 5 disable gpa mode */ 1324 gfx_v11_0_disable_gpa_mode(adev); 1325 1326 return 0; 1327 } 1328 1329 static int gfx_v11_0_sw_init(void *handle) 1330 { 1331 int i, j, k, r, ring_id = 0; 1332 int xcc_id = 0; 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1336 case IP_VERSION(11, 0, 0): 1337 case IP_VERSION(11, 0, 2): 1338 case IP_VERSION(11, 0, 3): 1339 adev->gfx.me.num_me = 1; 1340 adev->gfx.me.num_pipe_per_me = 1; 1341 adev->gfx.me.num_queue_per_pipe = 1; 1342 adev->gfx.mec.num_mec = 2; 1343 adev->gfx.mec.num_pipe_per_mec = 4; 1344 adev->gfx.mec.num_queue_per_pipe = 4; 1345 break; 1346 case IP_VERSION(11, 0, 1): 1347 case IP_VERSION(11, 0, 4): 1348 case IP_VERSION(11, 5, 0): 1349 adev->gfx.me.num_me = 1; 1350 adev->gfx.me.num_pipe_per_me = 1; 1351 adev->gfx.me.num_queue_per_pipe = 1; 1352 adev->gfx.mec.num_mec = 1; 1353 adev->gfx.mec.num_pipe_per_mec = 4; 1354 adev->gfx.mec.num_queue_per_pipe = 4; 1355 break; 1356 default: 1357 adev->gfx.me.num_me = 1; 1358 adev->gfx.me.num_pipe_per_me = 1; 1359 adev->gfx.me.num_queue_per_pipe = 1; 1360 adev->gfx.mec.num_mec = 1; 1361 adev->gfx.mec.num_pipe_per_mec = 4; 1362 adev->gfx.mec.num_queue_per_pipe = 8; 1363 break; 1364 } 1365 1366 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1367 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && 1368 amdgpu_sriov_is_pp_one_vf(adev)) 1369 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1370 1371 /* EOP Event */ 1372 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1373 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1374 &adev->gfx.eop_irq); 1375 if (r) 1376 return r; 1377 1378 /* Privileged reg */ 1379 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1380 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1381 &adev->gfx.priv_reg_irq); 1382 if (r) 1383 return r; 1384 1385 /* Privileged inst */ 1386 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1387 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1388 &adev->gfx.priv_inst_irq); 1389 if (r) 1390 return r; 1391 1392 /* FED error */ 1393 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1394 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1395 &adev->gfx.rlc_gc_fed_irq); 1396 if (r) 1397 return r; 1398 1399 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1400 1401 gfx_v11_0_me_init(adev); 1402 1403 r = gfx_v11_0_rlc_init(adev); 1404 if (r) { 1405 DRM_ERROR("Failed to init rlc BOs!\n"); 1406 return r; 1407 } 1408 1409 r = gfx_v11_0_mec_init(adev); 1410 if (r) { 1411 DRM_ERROR("Failed to init MEC BOs!\n"); 1412 return r; 1413 } 1414 1415 /* set up the gfx ring */ 1416 for (i = 0; i < adev->gfx.me.num_me; i++) { 1417 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1418 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1419 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1420 continue; 1421 1422 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1423 i, k, j); 1424 if (r) 1425 return r; 1426 ring_id++; 1427 } 1428 } 1429 } 1430 1431 ring_id = 0; 1432 /* set up the compute queues - allocate horizontally across pipes */ 1433 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1434 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1435 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1436 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1437 k, j)) 1438 continue; 1439 1440 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1441 i, k, j); 1442 if (r) 1443 return r; 1444 1445 ring_id++; 1446 } 1447 } 1448 } 1449 1450 if (!adev->enable_mes_kiq) { 1451 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1452 if (r) { 1453 DRM_ERROR("Failed to init KIQ BOs!\n"); 1454 return r; 1455 } 1456 1457 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1458 if (r) 1459 return r; 1460 } 1461 1462 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1463 if (r) 1464 return r; 1465 1466 /* allocate visible FB for rlc auto-loading fw */ 1467 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1468 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1469 if (r) 1470 return r; 1471 } 1472 1473 r = gfx_v11_0_gpu_early_init(adev); 1474 if (r) 1475 return r; 1476 1477 if (amdgpu_gfx_ras_sw_init(adev)) { 1478 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1479 return -EINVAL; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1486 { 1487 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1488 &adev->gfx.pfp.pfp_fw_gpu_addr, 1489 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1490 1491 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1492 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1493 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1494 } 1495 1496 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1497 { 1498 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1499 &adev->gfx.me.me_fw_gpu_addr, 1500 (void **)&adev->gfx.me.me_fw_ptr); 1501 1502 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1503 &adev->gfx.me.me_fw_data_gpu_addr, 1504 (void **)&adev->gfx.me.me_fw_data_ptr); 1505 } 1506 1507 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1508 { 1509 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1510 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1511 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1512 } 1513 1514 static int gfx_v11_0_sw_fini(void *handle) 1515 { 1516 int i; 1517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1518 1519 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1520 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1521 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1522 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1523 1524 amdgpu_gfx_mqd_sw_fini(adev, 0); 1525 1526 if (!adev->enable_mes_kiq) { 1527 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1528 amdgpu_gfx_kiq_fini(adev, 0); 1529 } 1530 1531 gfx_v11_0_pfp_fini(adev); 1532 gfx_v11_0_me_fini(adev); 1533 gfx_v11_0_rlc_fini(adev); 1534 gfx_v11_0_mec_fini(adev); 1535 1536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1537 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1538 1539 gfx_v11_0_free_microcode(adev); 1540 1541 return 0; 1542 } 1543 1544 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1545 u32 sh_num, u32 instance, int xcc_id) 1546 { 1547 u32 data; 1548 1549 if (instance == 0xffffffff) 1550 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1551 INSTANCE_BROADCAST_WRITES, 1); 1552 else 1553 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1554 instance); 1555 1556 if (se_num == 0xffffffff) 1557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1558 1); 1559 else 1560 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1561 1562 if (sh_num == 0xffffffff) 1563 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1564 1); 1565 else 1566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1567 1568 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1569 } 1570 1571 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1572 { 1573 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1574 1575 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1576 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1577 CC_GC_SA_UNIT_DISABLE, 1578 SA_DISABLE); 1579 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1580 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1581 GC_USER_SA_UNIT_DISABLE, 1582 SA_DISABLE); 1583 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1584 adev->gfx.config.max_shader_engines); 1585 1586 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1587 } 1588 1589 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1590 { 1591 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1592 u32 rb_mask; 1593 1594 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1595 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1596 CC_RB_BACKEND_DISABLE, 1597 BACKEND_DISABLE); 1598 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1599 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1600 GC_USER_RB_BACKEND_DISABLE, 1601 BACKEND_DISABLE); 1602 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1603 adev->gfx.config.max_shader_engines); 1604 1605 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1606 } 1607 1608 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1609 { 1610 u32 rb_bitmap_width_per_sa; 1611 u32 max_sa; 1612 u32 active_sa_bitmap; 1613 u32 global_active_rb_bitmap; 1614 u32 active_rb_bitmap = 0; 1615 u32 i; 1616 1617 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1618 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1619 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1620 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1621 1622 /* generate active rb bitmap according to active sa bitmap */ 1623 max_sa = adev->gfx.config.max_shader_engines * 1624 adev->gfx.config.max_sh_per_se; 1625 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1626 adev->gfx.config.max_sh_per_se; 1627 for (i = 0; i < max_sa; i++) { 1628 if (active_sa_bitmap & (1 << i)) 1629 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1630 } 1631 1632 active_rb_bitmap |= global_active_rb_bitmap; 1633 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1634 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1635 } 1636 1637 #define DEFAULT_SH_MEM_BASES (0x6000) 1638 #define LDS_APP_BASE 0x1 1639 #define SCRATCH_APP_BASE 0x2 1640 1641 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1642 { 1643 int i; 1644 uint32_t sh_mem_bases; 1645 uint32_t data; 1646 1647 /* 1648 * Configure apertures: 1649 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1650 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1651 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1652 */ 1653 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1654 SCRATCH_APP_BASE; 1655 1656 mutex_lock(&adev->srbm_mutex); 1657 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1658 soc21_grbm_select(adev, 0, 0, 0, i); 1659 /* CP and shaders */ 1660 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1661 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1662 1663 /* Enable trap for each kfd vmid. */ 1664 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1665 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1666 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1667 } 1668 soc21_grbm_select(adev, 0, 0, 0, 0); 1669 mutex_unlock(&adev->srbm_mutex); 1670 1671 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1672 acccess. These should be enabled by FW for target VMIDs. */ 1673 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1674 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1675 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1676 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1677 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1678 } 1679 } 1680 1681 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1682 { 1683 int vmid; 1684 1685 /* 1686 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1687 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1688 * the driver can enable them for graphics. VMID0 should maintain 1689 * access so that HWS firmware can save/restore entries. 1690 */ 1691 for (vmid = 1; vmid < 16; vmid++) { 1692 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1693 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1694 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1695 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1696 } 1697 } 1698 1699 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1700 { 1701 /* TODO: harvest feature to be added later. */ 1702 } 1703 1704 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1705 { 1706 /* TCCs are global (not instanced). */ 1707 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1708 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1709 1710 adev->gfx.config.tcc_disabled_mask = 1711 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1712 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1713 } 1714 1715 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1716 { 1717 u32 tmp; 1718 int i; 1719 1720 if (!amdgpu_sriov_vf(adev)) 1721 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1722 1723 gfx_v11_0_setup_rb(adev); 1724 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1725 gfx_v11_0_get_tcc_info(adev); 1726 adev->gfx.config.pa_sc_tile_steering_override = 0; 1727 1728 /* Set whether texture coordinate truncation is conformant. */ 1729 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1730 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1731 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1732 1733 /* XXX SH_MEM regs */ 1734 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1735 mutex_lock(&adev->srbm_mutex); 1736 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1737 soc21_grbm_select(adev, 0, 0, 0, i); 1738 /* CP and shaders */ 1739 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1740 if (i != 0) { 1741 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1742 (adev->gmc.private_aperture_start >> 48)); 1743 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1744 (adev->gmc.shared_aperture_start >> 48)); 1745 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1746 } 1747 } 1748 soc21_grbm_select(adev, 0, 0, 0, 0); 1749 1750 mutex_unlock(&adev->srbm_mutex); 1751 1752 gfx_v11_0_init_compute_vmid(adev); 1753 gfx_v11_0_init_gds_vmid(adev); 1754 } 1755 1756 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1757 bool enable) 1758 { 1759 u32 tmp; 1760 1761 if (amdgpu_sriov_vf(adev)) 1762 return; 1763 1764 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1765 1766 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1767 enable ? 1 : 0); 1768 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1769 enable ? 1 : 0); 1770 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1771 enable ? 1 : 0); 1772 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1773 enable ? 1 : 0); 1774 1775 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1776 } 1777 1778 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1779 { 1780 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1781 1782 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1783 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1784 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1785 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1786 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1787 1788 return 0; 1789 } 1790 1791 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1792 { 1793 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1794 1795 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1796 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1797 } 1798 1799 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1800 { 1801 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1802 udelay(50); 1803 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1804 udelay(50); 1805 } 1806 1807 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1808 bool enable) 1809 { 1810 uint32_t rlc_pg_cntl; 1811 1812 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1813 1814 if (!enable) { 1815 /* RLC_PG_CNTL[23] = 0 (default) 1816 * RLC will wait for handshake acks with SMU 1817 * GFXOFF will be enabled 1818 * RLC_PG_CNTL[23] = 1 1819 * RLC will not issue any message to SMU 1820 * hence no handshake between SMU & RLC 1821 * GFXOFF will be disabled 1822 */ 1823 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1824 } else 1825 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1826 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1827 } 1828 1829 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1830 { 1831 /* TODO: enable rlc & smu handshake until smu 1832 * and gfxoff feature works as expected */ 1833 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1834 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1835 1836 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1837 udelay(50); 1838 } 1839 1840 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1841 { 1842 uint32_t tmp; 1843 1844 /* enable Save Restore Machine */ 1845 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1846 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1847 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1848 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1849 } 1850 1851 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1852 { 1853 const struct rlc_firmware_header_v2_0 *hdr; 1854 const __le32 *fw_data; 1855 unsigned i, fw_size; 1856 1857 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1858 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1859 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1860 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1861 1862 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1863 RLCG_UCODE_LOADING_START_ADDRESS); 1864 1865 for (i = 0; i < fw_size; i++) 1866 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1867 le32_to_cpup(fw_data++)); 1868 1869 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1870 } 1871 1872 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1873 { 1874 const struct rlc_firmware_header_v2_2 *hdr; 1875 const __le32 *fw_data; 1876 unsigned i, fw_size; 1877 u32 tmp; 1878 1879 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1880 1881 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1882 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1883 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1884 1885 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1886 1887 for (i = 0; i < fw_size; i++) { 1888 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1889 msleep(1); 1890 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1891 le32_to_cpup(fw_data++)); 1892 } 1893 1894 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1895 1896 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1897 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1898 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1899 1900 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1901 for (i = 0; i < fw_size; i++) { 1902 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1903 msleep(1); 1904 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1905 le32_to_cpup(fw_data++)); 1906 } 1907 1908 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1909 1910 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1911 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1912 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1913 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1914 } 1915 1916 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1917 { 1918 const struct rlc_firmware_header_v2_3 *hdr; 1919 const __le32 *fw_data; 1920 unsigned i, fw_size; 1921 u32 tmp; 1922 1923 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1924 1925 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1926 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1927 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1928 1929 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1930 1931 for (i = 0; i < fw_size; i++) { 1932 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1933 msleep(1); 1934 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1935 le32_to_cpup(fw_data++)); 1936 } 1937 1938 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1939 1940 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1941 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1942 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1943 1944 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1945 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1946 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1947 1948 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1949 1950 for (i = 0; i < fw_size; i++) { 1951 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1952 msleep(1); 1953 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1954 le32_to_cpup(fw_data++)); 1955 } 1956 1957 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1958 1959 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1960 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1961 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1962 } 1963 1964 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1965 { 1966 const struct rlc_firmware_header_v2_0 *hdr; 1967 uint16_t version_major; 1968 uint16_t version_minor; 1969 1970 if (!adev->gfx.rlc_fw) 1971 return -EINVAL; 1972 1973 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1974 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1975 1976 version_major = le16_to_cpu(hdr->header.header_version_major); 1977 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1978 1979 if (version_major == 2) { 1980 gfx_v11_0_load_rlcg_microcode(adev); 1981 if (amdgpu_dpm == 1) { 1982 if (version_minor >= 2) 1983 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1984 if (version_minor == 3) 1985 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1986 } 1987 1988 return 0; 1989 } 1990 1991 return -EINVAL; 1992 } 1993 1994 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1995 { 1996 int r; 1997 1998 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1999 gfx_v11_0_init_csb(adev); 2000 2001 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2002 gfx_v11_0_rlc_enable_srm(adev); 2003 } else { 2004 if (amdgpu_sriov_vf(adev)) { 2005 gfx_v11_0_init_csb(adev); 2006 return 0; 2007 } 2008 2009 adev->gfx.rlc.funcs->stop(adev); 2010 2011 /* disable CG */ 2012 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2013 2014 /* disable PG */ 2015 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2016 2017 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2018 /* legacy rlc firmware loading */ 2019 r = gfx_v11_0_rlc_load_microcode(adev); 2020 if (r) 2021 return r; 2022 } 2023 2024 gfx_v11_0_init_csb(adev); 2025 2026 adev->gfx.rlc.funcs->start(adev); 2027 } 2028 return 0; 2029 } 2030 2031 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2032 { 2033 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2034 uint32_t tmp; 2035 int i; 2036 2037 /* Trigger an invalidation of the L1 instruction caches */ 2038 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2039 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2040 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2041 2042 /* Wait for invalidation complete */ 2043 for (i = 0; i < usec_timeout; i++) { 2044 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2045 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2046 INVALIDATE_CACHE_COMPLETE)) 2047 break; 2048 udelay(1); 2049 } 2050 2051 if (i >= usec_timeout) { 2052 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2053 return -EINVAL; 2054 } 2055 2056 if (amdgpu_emu_mode == 1) 2057 adev->hdp.funcs->flush_hdp(adev, NULL); 2058 2059 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2060 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2061 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2062 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2063 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2064 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2065 2066 /* Program me ucode address into intruction cache address register */ 2067 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2068 lower_32_bits(addr) & 0xFFFFF000); 2069 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2070 upper_32_bits(addr)); 2071 2072 return 0; 2073 } 2074 2075 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2076 { 2077 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2078 uint32_t tmp; 2079 int i; 2080 2081 /* Trigger an invalidation of the L1 instruction caches */ 2082 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2083 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2084 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2085 2086 /* Wait for invalidation complete */ 2087 for (i = 0; i < usec_timeout; i++) { 2088 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2089 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2090 INVALIDATE_CACHE_COMPLETE)) 2091 break; 2092 udelay(1); 2093 } 2094 2095 if (i >= usec_timeout) { 2096 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2097 return -EINVAL; 2098 } 2099 2100 if (amdgpu_emu_mode == 1) 2101 adev->hdp.funcs->flush_hdp(adev, NULL); 2102 2103 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2104 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2105 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2106 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2107 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2108 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2109 2110 /* Program pfp ucode address into intruction cache address register */ 2111 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2112 lower_32_bits(addr) & 0xFFFFF000); 2113 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2114 upper_32_bits(addr)); 2115 2116 return 0; 2117 } 2118 2119 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2120 { 2121 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2122 uint32_t tmp; 2123 int i; 2124 2125 /* Trigger an invalidation of the L1 instruction caches */ 2126 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2127 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2128 2129 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2130 2131 /* Wait for invalidation complete */ 2132 for (i = 0; i < usec_timeout; i++) { 2133 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2134 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2135 INVALIDATE_CACHE_COMPLETE)) 2136 break; 2137 udelay(1); 2138 } 2139 2140 if (i >= usec_timeout) { 2141 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2142 return -EINVAL; 2143 } 2144 2145 if (amdgpu_emu_mode == 1) 2146 adev->hdp.funcs->flush_hdp(adev, NULL); 2147 2148 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2149 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2150 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2151 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2152 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2153 2154 /* Program mec1 ucode address into intruction cache address register */ 2155 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2156 lower_32_bits(addr) & 0xFFFFF000); 2157 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2158 upper_32_bits(addr)); 2159 2160 return 0; 2161 } 2162 2163 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2164 { 2165 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2166 uint32_t tmp; 2167 unsigned i, pipe_id; 2168 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2169 2170 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2171 adev->gfx.pfp_fw->data; 2172 2173 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2174 lower_32_bits(addr)); 2175 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2176 upper_32_bits(addr)); 2177 2178 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2179 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2180 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2181 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2182 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2183 2184 /* 2185 * Programming any of the CP_PFP_IC_BASE registers 2186 * forces invalidation of the ME L1 I$. Wait for the 2187 * invalidation complete 2188 */ 2189 for (i = 0; i < usec_timeout; i++) { 2190 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2191 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2192 INVALIDATE_CACHE_COMPLETE)) 2193 break; 2194 udelay(1); 2195 } 2196 2197 if (i >= usec_timeout) { 2198 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2199 return -EINVAL; 2200 } 2201 2202 /* Prime the L1 instruction caches */ 2203 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2204 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2205 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2206 /* Waiting for cache primed*/ 2207 for (i = 0; i < usec_timeout; i++) { 2208 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2209 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2210 ICACHE_PRIMED)) 2211 break; 2212 udelay(1); 2213 } 2214 2215 if (i >= usec_timeout) { 2216 dev_err(adev->dev, "failed to prime instruction cache\n"); 2217 return -EINVAL; 2218 } 2219 2220 mutex_lock(&adev->srbm_mutex); 2221 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2222 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2223 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2224 (pfp_hdr->ucode_start_addr_hi << 30) | 2225 (pfp_hdr->ucode_start_addr_lo >> 2)); 2226 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2227 pfp_hdr->ucode_start_addr_hi >> 2); 2228 2229 /* 2230 * Program CP_ME_CNTL to reset given PIPE to take 2231 * effect of CP_PFP_PRGRM_CNTR_START. 2232 */ 2233 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2234 if (pipe_id == 0) 2235 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2236 PFP_PIPE0_RESET, 1); 2237 else 2238 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2239 PFP_PIPE1_RESET, 1); 2240 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2241 2242 /* Clear pfp pipe0 reset bit. */ 2243 if (pipe_id == 0) 2244 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2245 PFP_PIPE0_RESET, 0); 2246 else 2247 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2248 PFP_PIPE1_RESET, 0); 2249 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2250 2251 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2252 lower_32_bits(addr2)); 2253 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2254 upper_32_bits(addr2)); 2255 } 2256 soc21_grbm_select(adev, 0, 0, 0, 0); 2257 mutex_unlock(&adev->srbm_mutex); 2258 2259 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2260 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2261 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2262 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2263 2264 /* Invalidate the data caches */ 2265 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2266 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2267 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2268 2269 for (i = 0; i < usec_timeout; i++) { 2270 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2271 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2272 INVALIDATE_DCACHE_COMPLETE)) 2273 break; 2274 udelay(1); 2275 } 2276 2277 if (i >= usec_timeout) { 2278 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2279 return -EINVAL; 2280 } 2281 2282 return 0; 2283 } 2284 2285 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2286 { 2287 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2288 uint32_t tmp; 2289 unsigned i, pipe_id; 2290 const struct gfx_firmware_header_v2_0 *me_hdr; 2291 2292 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2293 adev->gfx.me_fw->data; 2294 2295 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2296 lower_32_bits(addr)); 2297 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2298 upper_32_bits(addr)); 2299 2300 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2301 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2302 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2303 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2304 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2305 2306 /* 2307 * Programming any of the CP_ME_IC_BASE registers 2308 * forces invalidation of the ME L1 I$. Wait for the 2309 * invalidation complete 2310 */ 2311 for (i = 0; i < usec_timeout; i++) { 2312 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2313 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2314 INVALIDATE_CACHE_COMPLETE)) 2315 break; 2316 udelay(1); 2317 } 2318 2319 if (i >= usec_timeout) { 2320 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2321 return -EINVAL; 2322 } 2323 2324 /* Prime the instruction caches */ 2325 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2326 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2327 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2328 2329 /* Waiting for instruction cache primed*/ 2330 for (i = 0; i < usec_timeout; i++) { 2331 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2332 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2333 ICACHE_PRIMED)) 2334 break; 2335 udelay(1); 2336 } 2337 2338 if (i >= usec_timeout) { 2339 dev_err(adev->dev, "failed to prime instruction cache\n"); 2340 return -EINVAL; 2341 } 2342 2343 mutex_lock(&adev->srbm_mutex); 2344 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2345 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2346 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2347 (me_hdr->ucode_start_addr_hi << 30) | 2348 (me_hdr->ucode_start_addr_lo >> 2) ); 2349 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2350 me_hdr->ucode_start_addr_hi>>2); 2351 2352 /* 2353 * Program CP_ME_CNTL to reset given PIPE to take 2354 * effect of CP_PFP_PRGRM_CNTR_START. 2355 */ 2356 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2357 if (pipe_id == 0) 2358 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2359 ME_PIPE0_RESET, 1); 2360 else 2361 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2362 ME_PIPE1_RESET, 1); 2363 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2364 2365 /* Clear pfp pipe0 reset bit. */ 2366 if (pipe_id == 0) 2367 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2368 ME_PIPE0_RESET, 0); 2369 else 2370 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2371 ME_PIPE1_RESET, 0); 2372 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2373 2374 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2375 lower_32_bits(addr2)); 2376 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2377 upper_32_bits(addr2)); 2378 } 2379 soc21_grbm_select(adev, 0, 0, 0, 0); 2380 mutex_unlock(&adev->srbm_mutex); 2381 2382 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2383 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2384 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2385 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2386 2387 /* Invalidate the data caches */ 2388 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2389 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2390 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2391 2392 for (i = 0; i < usec_timeout; i++) { 2393 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2394 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2395 INVALIDATE_DCACHE_COMPLETE)) 2396 break; 2397 udelay(1); 2398 } 2399 2400 if (i >= usec_timeout) { 2401 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2402 return -EINVAL; 2403 } 2404 2405 return 0; 2406 } 2407 2408 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2409 { 2410 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2411 uint32_t tmp; 2412 unsigned i; 2413 const struct gfx_firmware_header_v2_0 *mec_hdr; 2414 2415 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2416 adev->gfx.mec_fw->data; 2417 2418 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2419 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2420 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2421 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2422 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2423 2424 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2425 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2426 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2427 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2428 2429 mutex_lock(&adev->srbm_mutex); 2430 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2431 soc21_grbm_select(adev, 1, i, 0, 0); 2432 2433 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2434 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2435 upper_32_bits(addr2)); 2436 2437 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2438 mec_hdr->ucode_start_addr_lo >> 2 | 2439 mec_hdr->ucode_start_addr_hi << 30); 2440 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2441 mec_hdr->ucode_start_addr_hi >> 2); 2442 2443 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2444 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2445 upper_32_bits(addr)); 2446 } 2447 mutex_unlock(&adev->srbm_mutex); 2448 soc21_grbm_select(adev, 0, 0, 0, 0); 2449 2450 /* Trigger an invalidation of the L1 instruction caches */ 2451 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2452 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2453 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2454 2455 /* Wait for invalidation complete */ 2456 for (i = 0; i < usec_timeout; i++) { 2457 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2458 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2459 INVALIDATE_DCACHE_COMPLETE)) 2460 break; 2461 udelay(1); 2462 } 2463 2464 if (i >= usec_timeout) { 2465 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2466 return -EINVAL; 2467 } 2468 2469 /* Trigger an invalidation of the L1 instruction caches */ 2470 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2471 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2472 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2473 2474 /* Wait for invalidation complete */ 2475 for (i = 0; i < usec_timeout; i++) { 2476 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2477 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2478 INVALIDATE_CACHE_COMPLETE)) 2479 break; 2480 udelay(1); 2481 } 2482 2483 if (i >= usec_timeout) { 2484 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2485 return -EINVAL; 2486 } 2487 2488 return 0; 2489 } 2490 2491 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2492 { 2493 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2494 const struct gfx_firmware_header_v2_0 *me_hdr; 2495 const struct gfx_firmware_header_v2_0 *mec_hdr; 2496 uint32_t pipe_id, tmp; 2497 2498 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2499 adev->gfx.mec_fw->data; 2500 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2501 adev->gfx.me_fw->data; 2502 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2503 adev->gfx.pfp_fw->data; 2504 2505 /* config pfp program start addr */ 2506 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2507 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2508 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2509 (pfp_hdr->ucode_start_addr_hi << 30) | 2510 (pfp_hdr->ucode_start_addr_lo >> 2)); 2511 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2512 pfp_hdr->ucode_start_addr_hi >> 2); 2513 } 2514 soc21_grbm_select(adev, 0, 0, 0, 0); 2515 2516 /* reset pfp pipe */ 2517 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2518 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2519 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2520 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2521 2522 /* clear pfp pipe reset */ 2523 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2524 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2525 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2526 2527 /* config me program start addr */ 2528 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2529 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2530 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2531 (me_hdr->ucode_start_addr_hi << 30) | 2532 (me_hdr->ucode_start_addr_lo >> 2) ); 2533 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2534 me_hdr->ucode_start_addr_hi>>2); 2535 } 2536 soc21_grbm_select(adev, 0, 0, 0, 0); 2537 2538 /* reset me pipe */ 2539 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2540 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2541 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2542 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2543 2544 /* clear me pipe reset */ 2545 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2546 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2547 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2548 2549 /* config mec program start addr */ 2550 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2551 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2552 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2553 mec_hdr->ucode_start_addr_lo >> 2 | 2554 mec_hdr->ucode_start_addr_hi << 30); 2555 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2556 mec_hdr->ucode_start_addr_hi >> 2); 2557 } 2558 soc21_grbm_select(adev, 0, 0, 0, 0); 2559 2560 /* reset mec pipe */ 2561 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2562 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2563 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2564 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2565 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2566 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2567 2568 /* clear mec pipe reset */ 2569 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2570 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2571 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2572 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2573 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2574 } 2575 2576 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2577 { 2578 uint32_t cp_status; 2579 uint32_t bootload_status; 2580 int i, r; 2581 uint64_t addr, addr2; 2582 2583 for (i = 0; i < adev->usec_timeout; i++) { 2584 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2585 2586 if (amdgpu_ip_version(adev, GC_HWIP, 0) == 2587 IP_VERSION(11, 0, 1) || 2588 amdgpu_ip_version(adev, GC_HWIP, 0) == 2589 IP_VERSION(11, 0, 4) || 2590 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0)) 2591 bootload_status = RREG32_SOC15(GC, 0, 2592 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2593 else 2594 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2595 2596 if ((cp_status == 0) && 2597 (REG_GET_FIELD(bootload_status, 2598 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2599 break; 2600 } 2601 udelay(1); 2602 } 2603 2604 if (i >= adev->usec_timeout) { 2605 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2606 return -ETIMEDOUT; 2607 } 2608 2609 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2610 if (adev->gfx.rs64_enable) { 2611 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2612 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2613 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2614 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2615 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2616 if (r) 2617 return r; 2618 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2619 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2620 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2621 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2622 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2623 if (r) 2624 return r; 2625 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2626 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2627 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2628 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2629 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2630 if (r) 2631 return r; 2632 } else { 2633 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2634 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2635 r = gfx_v11_0_config_me_cache(adev, addr); 2636 if (r) 2637 return r; 2638 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2639 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2640 r = gfx_v11_0_config_pfp_cache(adev, addr); 2641 if (r) 2642 return r; 2643 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2644 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2645 r = gfx_v11_0_config_mec_cache(adev, addr); 2646 if (r) 2647 return r; 2648 } 2649 } 2650 2651 return 0; 2652 } 2653 2654 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2655 { 2656 int i; 2657 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2658 2659 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2660 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2661 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2662 2663 for (i = 0; i < adev->usec_timeout; i++) { 2664 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2665 break; 2666 udelay(1); 2667 } 2668 2669 if (i >= adev->usec_timeout) 2670 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2671 2672 return 0; 2673 } 2674 2675 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2676 { 2677 int r; 2678 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2679 const __le32 *fw_data; 2680 unsigned i, fw_size; 2681 2682 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2683 adev->gfx.pfp_fw->data; 2684 2685 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2686 2687 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2688 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2689 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2690 2691 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2692 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2693 &adev->gfx.pfp.pfp_fw_obj, 2694 &adev->gfx.pfp.pfp_fw_gpu_addr, 2695 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2696 if (r) { 2697 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2698 gfx_v11_0_pfp_fini(adev); 2699 return r; 2700 } 2701 2702 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2703 2704 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2705 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2706 2707 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2708 2709 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2710 2711 for (i = 0; i < pfp_hdr->jt_size; i++) 2712 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2713 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2714 2715 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2716 2717 return 0; 2718 } 2719 2720 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2721 { 2722 int r; 2723 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2724 const __le32 *fw_ucode, *fw_data; 2725 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2726 uint32_t tmp; 2727 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2728 2729 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2730 adev->gfx.pfp_fw->data; 2731 2732 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2733 2734 /* instruction */ 2735 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2736 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2737 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2738 /* data */ 2739 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2740 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2741 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2742 2743 /* 64kb align */ 2744 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2745 64 * 1024, 2746 AMDGPU_GEM_DOMAIN_VRAM | 2747 AMDGPU_GEM_DOMAIN_GTT, 2748 &adev->gfx.pfp.pfp_fw_obj, 2749 &adev->gfx.pfp.pfp_fw_gpu_addr, 2750 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2751 if (r) { 2752 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2753 gfx_v11_0_pfp_fini(adev); 2754 return r; 2755 } 2756 2757 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2758 64 * 1024, 2759 AMDGPU_GEM_DOMAIN_VRAM | 2760 AMDGPU_GEM_DOMAIN_GTT, 2761 &adev->gfx.pfp.pfp_fw_data_obj, 2762 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2763 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2764 if (r) { 2765 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2766 gfx_v11_0_pfp_fini(adev); 2767 return r; 2768 } 2769 2770 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2771 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2772 2773 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2774 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2775 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2776 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2777 2778 if (amdgpu_emu_mode == 1) 2779 adev->hdp.funcs->flush_hdp(adev, NULL); 2780 2781 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2782 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2783 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2784 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2785 2786 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2787 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2788 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2789 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2790 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2791 2792 /* 2793 * Programming any of the CP_PFP_IC_BASE registers 2794 * forces invalidation of the ME L1 I$. Wait for the 2795 * invalidation complete 2796 */ 2797 for (i = 0; i < usec_timeout; i++) { 2798 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2799 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2800 INVALIDATE_CACHE_COMPLETE)) 2801 break; 2802 udelay(1); 2803 } 2804 2805 if (i >= usec_timeout) { 2806 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2807 return -EINVAL; 2808 } 2809 2810 /* Prime the L1 instruction caches */ 2811 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2812 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2813 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2814 /* Waiting for cache primed*/ 2815 for (i = 0; i < usec_timeout; i++) { 2816 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2817 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2818 ICACHE_PRIMED)) 2819 break; 2820 udelay(1); 2821 } 2822 2823 if (i >= usec_timeout) { 2824 dev_err(adev->dev, "failed to prime instruction cache\n"); 2825 return -EINVAL; 2826 } 2827 2828 mutex_lock(&adev->srbm_mutex); 2829 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2830 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2831 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2832 (pfp_hdr->ucode_start_addr_hi << 30) | 2833 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2834 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2835 pfp_hdr->ucode_start_addr_hi>>2); 2836 2837 /* 2838 * Program CP_ME_CNTL to reset given PIPE to take 2839 * effect of CP_PFP_PRGRM_CNTR_START. 2840 */ 2841 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2842 if (pipe_id == 0) 2843 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2844 PFP_PIPE0_RESET, 1); 2845 else 2846 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2847 PFP_PIPE1_RESET, 1); 2848 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2849 2850 /* Clear pfp pipe0 reset bit. */ 2851 if (pipe_id == 0) 2852 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2853 PFP_PIPE0_RESET, 0); 2854 else 2855 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2856 PFP_PIPE1_RESET, 0); 2857 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2858 2859 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2860 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2861 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2862 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2863 } 2864 soc21_grbm_select(adev, 0, 0, 0, 0); 2865 mutex_unlock(&adev->srbm_mutex); 2866 2867 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2868 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2869 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2870 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2871 2872 /* Invalidate the data caches */ 2873 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2874 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2875 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2876 2877 for (i = 0; i < usec_timeout; i++) { 2878 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2879 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2880 INVALIDATE_DCACHE_COMPLETE)) 2881 break; 2882 udelay(1); 2883 } 2884 2885 if (i >= usec_timeout) { 2886 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2887 return -EINVAL; 2888 } 2889 2890 return 0; 2891 } 2892 2893 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2894 { 2895 int r; 2896 const struct gfx_firmware_header_v1_0 *me_hdr; 2897 const __le32 *fw_data; 2898 unsigned i, fw_size; 2899 2900 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2901 adev->gfx.me_fw->data; 2902 2903 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2904 2905 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2906 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2907 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2908 2909 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2910 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2911 &adev->gfx.me.me_fw_obj, 2912 &adev->gfx.me.me_fw_gpu_addr, 2913 (void **)&adev->gfx.me.me_fw_ptr); 2914 if (r) { 2915 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2916 gfx_v11_0_me_fini(adev); 2917 return r; 2918 } 2919 2920 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2921 2922 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2923 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2924 2925 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2926 2927 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2928 2929 for (i = 0; i < me_hdr->jt_size; i++) 2930 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2931 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2932 2933 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2934 2935 return 0; 2936 } 2937 2938 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2939 { 2940 int r; 2941 const struct gfx_firmware_header_v2_0 *me_hdr; 2942 const __le32 *fw_ucode, *fw_data; 2943 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2944 uint32_t tmp; 2945 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2946 2947 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2948 adev->gfx.me_fw->data; 2949 2950 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2951 2952 /* instruction */ 2953 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2954 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2955 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2956 /* data */ 2957 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2958 le32_to_cpu(me_hdr->data_offset_bytes)); 2959 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2960 2961 /* 64kb align*/ 2962 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2963 64 * 1024, 2964 AMDGPU_GEM_DOMAIN_VRAM | 2965 AMDGPU_GEM_DOMAIN_GTT, 2966 &adev->gfx.me.me_fw_obj, 2967 &adev->gfx.me.me_fw_gpu_addr, 2968 (void **)&adev->gfx.me.me_fw_ptr); 2969 if (r) { 2970 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2971 gfx_v11_0_me_fini(adev); 2972 return r; 2973 } 2974 2975 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2976 64 * 1024, 2977 AMDGPU_GEM_DOMAIN_VRAM | 2978 AMDGPU_GEM_DOMAIN_GTT, 2979 &adev->gfx.me.me_fw_data_obj, 2980 &adev->gfx.me.me_fw_data_gpu_addr, 2981 (void **)&adev->gfx.me.me_fw_data_ptr); 2982 if (r) { 2983 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2984 gfx_v11_0_pfp_fini(adev); 2985 return r; 2986 } 2987 2988 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2989 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2990 2991 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2992 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2993 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2994 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2995 2996 if (amdgpu_emu_mode == 1) 2997 adev->hdp.funcs->flush_hdp(adev, NULL); 2998 2999 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3000 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3001 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3002 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3003 3004 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3005 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3006 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3007 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3008 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3009 3010 /* 3011 * Programming any of the CP_ME_IC_BASE registers 3012 * forces invalidation of the ME L1 I$. Wait for the 3013 * invalidation complete 3014 */ 3015 for (i = 0; i < usec_timeout; i++) { 3016 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3017 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3018 INVALIDATE_CACHE_COMPLETE)) 3019 break; 3020 udelay(1); 3021 } 3022 3023 if (i >= usec_timeout) { 3024 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3025 return -EINVAL; 3026 } 3027 3028 /* Prime the instruction caches */ 3029 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3030 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3031 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3032 3033 /* Waiting for instruction cache primed*/ 3034 for (i = 0; i < usec_timeout; i++) { 3035 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3036 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3037 ICACHE_PRIMED)) 3038 break; 3039 udelay(1); 3040 } 3041 3042 if (i >= usec_timeout) { 3043 dev_err(adev->dev, "failed to prime instruction cache\n"); 3044 return -EINVAL; 3045 } 3046 3047 mutex_lock(&adev->srbm_mutex); 3048 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3049 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3050 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3051 (me_hdr->ucode_start_addr_hi << 30) | 3052 (me_hdr->ucode_start_addr_lo >> 2) ); 3053 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3054 me_hdr->ucode_start_addr_hi>>2); 3055 3056 /* 3057 * Program CP_ME_CNTL to reset given PIPE to take 3058 * effect of CP_PFP_PRGRM_CNTR_START. 3059 */ 3060 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3061 if (pipe_id == 0) 3062 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3063 ME_PIPE0_RESET, 1); 3064 else 3065 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3066 ME_PIPE1_RESET, 1); 3067 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3068 3069 /* Clear pfp pipe0 reset bit. */ 3070 if (pipe_id == 0) 3071 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3072 ME_PIPE0_RESET, 0); 3073 else 3074 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3075 ME_PIPE1_RESET, 0); 3076 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3077 3078 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3079 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3080 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3081 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3082 } 3083 soc21_grbm_select(adev, 0, 0, 0, 0); 3084 mutex_unlock(&adev->srbm_mutex); 3085 3086 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3087 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3088 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3089 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3090 3091 /* Invalidate the data caches */ 3092 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3093 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3094 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3095 3096 for (i = 0; i < usec_timeout; i++) { 3097 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3098 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3099 INVALIDATE_DCACHE_COMPLETE)) 3100 break; 3101 udelay(1); 3102 } 3103 3104 if (i >= usec_timeout) { 3105 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3106 return -EINVAL; 3107 } 3108 3109 return 0; 3110 } 3111 3112 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3113 { 3114 int r; 3115 3116 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3117 return -EINVAL; 3118 3119 gfx_v11_0_cp_gfx_enable(adev, false); 3120 3121 if (adev->gfx.rs64_enable) 3122 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3123 else 3124 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3125 if (r) { 3126 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3127 return r; 3128 } 3129 3130 if (adev->gfx.rs64_enable) 3131 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3132 else 3133 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3134 if (r) { 3135 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3136 return r; 3137 } 3138 3139 return 0; 3140 } 3141 3142 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3143 { 3144 struct amdgpu_ring *ring; 3145 const struct cs_section_def *sect = NULL; 3146 const struct cs_extent_def *ext = NULL; 3147 int r, i; 3148 int ctx_reg_offset; 3149 3150 /* init the CP */ 3151 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3152 adev->gfx.config.max_hw_contexts - 1); 3153 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3154 3155 if (!amdgpu_async_gfx_ring) 3156 gfx_v11_0_cp_gfx_enable(adev, true); 3157 3158 ring = &adev->gfx.gfx_ring[0]; 3159 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3160 if (r) { 3161 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3162 return r; 3163 } 3164 3165 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3166 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3167 3168 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3169 amdgpu_ring_write(ring, 0x80000000); 3170 amdgpu_ring_write(ring, 0x80000000); 3171 3172 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3173 for (ext = sect->section; ext->extent != NULL; ++ext) { 3174 if (sect->id == SECT_CONTEXT) { 3175 amdgpu_ring_write(ring, 3176 PACKET3(PACKET3_SET_CONTEXT_REG, 3177 ext->reg_count)); 3178 amdgpu_ring_write(ring, ext->reg_index - 3179 PACKET3_SET_CONTEXT_REG_START); 3180 for (i = 0; i < ext->reg_count; i++) 3181 amdgpu_ring_write(ring, ext->extent[i]); 3182 } 3183 } 3184 } 3185 3186 ctx_reg_offset = 3187 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3188 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3189 amdgpu_ring_write(ring, ctx_reg_offset); 3190 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3191 3192 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3193 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3194 3195 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3196 amdgpu_ring_write(ring, 0); 3197 3198 amdgpu_ring_commit(ring); 3199 3200 /* submit cs packet to copy state 0 to next available state */ 3201 if (adev->gfx.num_gfx_rings > 1) { 3202 /* maximum supported gfx ring is 2 */ 3203 ring = &adev->gfx.gfx_ring[1]; 3204 r = amdgpu_ring_alloc(ring, 2); 3205 if (r) { 3206 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3207 return r; 3208 } 3209 3210 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3211 amdgpu_ring_write(ring, 0); 3212 3213 amdgpu_ring_commit(ring); 3214 } 3215 return 0; 3216 } 3217 3218 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3219 CP_PIPE_ID pipe) 3220 { 3221 u32 tmp; 3222 3223 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3224 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3225 3226 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3227 } 3228 3229 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3230 struct amdgpu_ring *ring) 3231 { 3232 u32 tmp; 3233 3234 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3235 if (ring->use_doorbell) { 3236 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3237 DOORBELL_OFFSET, ring->doorbell_index); 3238 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3239 DOORBELL_EN, 1); 3240 } else { 3241 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3242 DOORBELL_EN, 0); 3243 } 3244 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3245 3246 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3247 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3248 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3249 3250 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3251 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3252 } 3253 3254 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3255 { 3256 struct amdgpu_ring *ring; 3257 u32 tmp; 3258 u32 rb_bufsz; 3259 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3260 3261 /* Set the write pointer delay */ 3262 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3263 3264 /* set the RB to use vmid 0 */ 3265 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3266 3267 /* Init gfx ring 0 for pipe 0 */ 3268 mutex_lock(&adev->srbm_mutex); 3269 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3270 3271 /* Set ring buffer size */ 3272 ring = &adev->gfx.gfx_ring[0]; 3273 rb_bufsz = order_base_2(ring->ring_size / 8); 3274 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3275 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3276 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3277 3278 /* Initialize the ring buffer's write pointers */ 3279 ring->wptr = 0; 3280 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3281 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3282 3283 /* set the wb address wether it's enabled or not */ 3284 rptr_addr = ring->rptr_gpu_addr; 3285 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3286 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3287 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3288 3289 wptr_gpu_addr = ring->wptr_gpu_addr; 3290 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3291 lower_32_bits(wptr_gpu_addr)); 3292 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3293 upper_32_bits(wptr_gpu_addr)); 3294 3295 mdelay(1); 3296 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3297 3298 rb_addr = ring->gpu_addr >> 8; 3299 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3300 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3301 3302 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3303 3304 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3305 mutex_unlock(&adev->srbm_mutex); 3306 3307 /* Init gfx ring 1 for pipe 1 */ 3308 if (adev->gfx.num_gfx_rings > 1) { 3309 mutex_lock(&adev->srbm_mutex); 3310 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3311 /* maximum supported gfx ring is 2 */ 3312 ring = &adev->gfx.gfx_ring[1]; 3313 rb_bufsz = order_base_2(ring->ring_size / 8); 3314 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3315 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3316 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3317 /* Initialize the ring buffer's write pointers */ 3318 ring->wptr = 0; 3319 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3320 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3321 /* Set the wb address wether it's enabled or not */ 3322 rptr_addr = ring->rptr_gpu_addr; 3323 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3324 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3325 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3326 wptr_gpu_addr = ring->wptr_gpu_addr; 3327 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3328 lower_32_bits(wptr_gpu_addr)); 3329 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3330 upper_32_bits(wptr_gpu_addr)); 3331 3332 mdelay(1); 3333 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3334 3335 rb_addr = ring->gpu_addr >> 8; 3336 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3337 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3338 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3339 3340 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3341 mutex_unlock(&adev->srbm_mutex); 3342 } 3343 /* Switch to pipe 0 */ 3344 mutex_lock(&adev->srbm_mutex); 3345 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3346 mutex_unlock(&adev->srbm_mutex); 3347 3348 /* start the ring */ 3349 gfx_v11_0_cp_gfx_start(adev); 3350 3351 return 0; 3352 } 3353 3354 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3355 { 3356 u32 data; 3357 3358 if (adev->gfx.rs64_enable) { 3359 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3360 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3361 enable ? 0 : 1); 3362 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3363 enable ? 0 : 1); 3364 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3365 enable ? 0 : 1); 3366 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3367 enable ? 0 : 1); 3368 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3369 enable ? 0 : 1); 3370 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3371 enable ? 1 : 0); 3372 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3373 enable ? 1 : 0); 3374 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3375 enable ? 1 : 0); 3376 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3377 enable ? 1 : 0); 3378 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3379 enable ? 0 : 1); 3380 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3381 } else { 3382 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3383 3384 if (enable) { 3385 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3386 if (!adev->enable_mes_kiq) 3387 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3388 MEC_ME2_HALT, 0); 3389 } else { 3390 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3391 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3392 } 3393 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3394 } 3395 3396 udelay(50); 3397 } 3398 3399 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3400 { 3401 const struct gfx_firmware_header_v1_0 *mec_hdr; 3402 const __le32 *fw_data; 3403 unsigned i, fw_size; 3404 u32 *fw = NULL; 3405 int r; 3406 3407 if (!adev->gfx.mec_fw) 3408 return -EINVAL; 3409 3410 gfx_v11_0_cp_compute_enable(adev, false); 3411 3412 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3413 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3414 3415 fw_data = (const __le32 *) 3416 (adev->gfx.mec_fw->data + 3417 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3418 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3419 3420 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3421 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3422 &adev->gfx.mec.mec_fw_obj, 3423 &adev->gfx.mec.mec_fw_gpu_addr, 3424 (void **)&fw); 3425 if (r) { 3426 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3427 gfx_v11_0_mec_fini(adev); 3428 return r; 3429 } 3430 3431 memcpy(fw, fw_data, fw_size); 3432 3433 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3434 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3435 3436 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3437 3438 /* MEC1 */ 3439 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3440 3441 for (i = 0; i < mec_hdr->jt_size; i++) 3442 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3443 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3444 3445 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3446 3447 return 0; 3448 } 3449 3450 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3451 { 3452 const struct gfx_firmware_header_v2_0 *mec_hdr; 3453 const __le32 *fw_ucode, *fw_data; 3454 u32 tmp, fw_ucode_size, fw_data_size; 3455 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3456 u32 *fw_ucode_ptr, *fw_data_ptr; 3457 int r; 3458 3459 if (!adev->gfx.mec_fw) 3460 return -EINVAL; 3461 3462 gfx_v11_0_cp_compute_enable(adev, false); 3463 3464 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3465 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3466 3467 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3468 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3469 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3470 3471 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3472 le32_to_cpu(mec_hdr->data_offset_bytes)); 3473 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3474 3475 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3476 64 * 1024, 3477 AMDGPU_GEM_DOMAIN_VRAM | 3478 AMDGPU_GEM_DOMAIN_GTT, 3479 &adev->gfx.mec.mec_fw_obj, 3480 &adev->gfx.mec.mec_fw_gpu_addr, 3481 (void **)&fw_ucode_ptr); 3482 if (r) { 3483 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3484 gfx_v11_0_mec_fini(adev); 3485 return r; 3486 } 3487 3488 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3489 64 * 1024, 3490 AMDGPU_GEM_DOMAIN_VRAM | 3491 AMDGPU_GEM_DOMAIN_GTT, 3492 &adev->gfx.mec.mec_fw_data_obj, 3493 &adev->gfx.mec.mec_fw_data_gpu_addr, 3494 (void **)&fw_data_ptr); 3495 if (r) { 3496 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3497 gfx_v11_0_mec_fini(adev); 3498 return r; 3499 } 3500 3501 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3502 memcpy(fw_data_ptr, fw_data, fw_data_size); 3503 3504 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3505 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3506 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3507 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3508 3509 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3510 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3511 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3512 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3513 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3514 3515 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3516 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3517 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3518 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3519 3520 mutex_lock(&adev->srbm_mutex); 3521 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3522 soc21_grbm_select(adev, 1, i, 0, 0); 3523 3524 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3525 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3526 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3527 3528 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3529 mec_hdr->ucode_start_addr_lo >> 2 | 3530 mec_hdr->ucode_start_addr_hi << 30); 3531 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3532 mec_hdr->ucode_start_addr_hi >> 2); 3533 3534 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3535 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3536 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3537 } 3538 mutex_unlock(&adev->srbm_mutex); 3539 soc21_grbm_select(adev, 0, 0, 0, 0); 3540 3541 /* Trigger an invalidation of the L1 instruction caches */ 3542 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3543 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3544 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3545 3546 /* Wait for invalidation complete */ 3547 for (i = 0; i < usec_timeout; i++) { 3548 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3549 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3550 INVALIDATE_DCACHE_COMPLETE)) 3551 break; 3552 udelay(1); 3553 } 3554 3555 if (i >= usec_timeout) { 3556 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3557 return -EINVAL; 3558 } 3559 3560 /* Trigger an invalidation of the L1 instruction caches */ 3561 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3562 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3563 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3564 3565 /* Wait for invalidation complete */ 3566 for (i = 0; i < usec_timeout; i++) { 3567 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3568 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3569 INVALIDATE_CACHE_COMPLETE)) 3570 break; 3571 udelay(1); 3572 } 3573 3574 if (i >= usec_timeout) { 3575 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3576 return -EINVAL; 3577 } 3578 3579 return 0; 3580 } 3581 3582 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3583 { 3584 uint32_t tmp; 3585 struct amdgpu_device *adev = ring->adev; 3586 3587 /* tell RLC which is KIQ queue */ 3588 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3589 tmp &= 0xffffff00; 3590 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3591 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3592 tmp |= 0x80; 3593 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3594 } 3595 3596 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3597 { 3598 /* set graphics engine doorbell range */ 3599 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3600 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3601 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3602 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3603 3604 /* set compute engine doorbell range */ 3605 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3606 (adev->doorbell_index.kiq * 2) << 2); 3607 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3608 (adev->doorbell_index.userqueue_end * 2) << 2); 3609 } 3610 3611 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3612 struct amdgpu_mqd_prop *prop) 3613 { 3614 struct v11_gfx_mqd *mqd = m; 3615 uint64_t hqd_gpu_addr, wb_gpu_addr; 3616 uint32_t tmp; 3617 uint32_t rb_bufsz; 3618 3619 /* set up gfx hqd wptr */ 3620 mqd->cp_gfx_hqd_wptr = 0; 3621 mqd->cp_gfx_hqd_wptr_hi = 0; 3622 3623 /* set the pointer to the MQD */ 3624 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3625 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3626 3627 /* set up mqd control */ 3628 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3629 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3630 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3631 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3632 mqd->cp_gfx_mqd_control = tmp; 3633 3634 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3635 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3636 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3637 mqd->cp_gfx_hqd_vmid = 0; 3638 3639 /* set up default queue priority level 3640 * 0x0 = low priority, 0x1 = high priority */ 3641 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3642 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3643 mqd->cp_gfx_hqd_queue_priority = tmp; 3644 3645 /* set up time quantum */ 3646 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3647 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3648 mqd->cp_gfx_hqd_quantum = tmp; 3649 3650 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3651 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3652 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3653 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3654 3655 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3656 wb_gpu_addr = prop->rptr_gpu_addr; 3657 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3658 mqd->cp_gfx_hqd_rptr_addr_hi = 3659 upper_32_bits(wb_gpu_addr) & 0xffff; 3660 3661 /* set up rb_wptr_poll addr */ 3662 wb_gpu_addr = prop->wptr_gpu_addr; 3663 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3664 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3665 3666 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3667 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3668 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3669 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3670 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3671 #ifdef __BIG_ENDIAN 3672 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3673 #endif 3674 mqd->cp_gfx_hqd_cntl = tmp; 3675 3676 /* set up cp_doorbell_control */ 3677 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3678 if (prop->use_doorbell) { 3679 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3680 DOORBELL_OFFSET, prop->doorbell_index); 3681 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3682 DOORBELL_EN, 1); 3683 } else 3684 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3685 DOORBELL_EN, 0); 3686 mqd->cp_rb_doorbell_control = tmp; 3687 3688 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3689 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3690 3691 /* active the queue */ 3692 mqd->cp_gfx_hqd_active = 1; 3693 3694 return 0; 3695 } 3696 3697 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3698 { 3699 struct amdgpu_device *adev = ring->adev; 3700 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3701 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3702 3703 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3704 memset((void *)mqd, 0, sizeof(*mqd)); 3705 mutex_lock(&adev->srbm_mutex); 3706 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3707 amdgpu_ring_init_mqd(ring); 3708 soc21_grbm_select(adev, 0, 0, 0, 0); 3709 mutex_unlock(&adev->srbm_mutex); 3710 if (adev->gfx.me.mqd_backup[mqd_idx]) 3711 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3712 } else { 3713 /* restore mqd with the backup copy */ 3714 if (adev->gfx.me.mqd_backup[mqd_idx]) 3715 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3716 /* reset the ring */ 3717 ring->wptr = 0; 3718 *ring->wptr_cpu_addr = 0; 3719 amdgpu_ring_clear_ring(ring); 3720 } 3721 3722 return 0; 3723 } 3724 3725 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3726 { 3727 int r, i; 3728 struct amdgpu_ring *ring; 3729 3730 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3731 ring = &adev->gfx.gfx_ring[i]; 3732 3733 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3734 if (unlikely(r != 0)) 3735 return r; 3736 3737 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3738 if (!r) { 3739 r = gfx_v11_0_gfx_init_queue(ring); 3740 amdgpu_bo_kunmap(ring->mqd_obj); 3741 ring->mqd_ptr = NULL; 3742 } 3743 amdgpu_bo_unreserve(ring->mqd_obj); 3744 if (r) 3745 return r; 3746 } 3747 3748 r = amdgpu_gfx_enable_kgq(adev, 0); 3749 if (r) 3750 return r; 3751 3752 return gfx_v11_0_cp_gfx_start(adev); 3753 } 3754 3755 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3756 struct amdgpu_mqd_prop *prop) 3757 { 3758 struct v11_compute_mqd *mqd = m; 3759 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3760 uint32_t tmp; 3761 3762 mqd->header = 0xC0310800; 3763 mqd->compute_pipelinestat_enable = 0x00000001; 3764 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3765 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3766 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3767 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3768 mqd->compute_misc_reserved = 0x00000007; 3769 3770 eop_base_addr = prop->eop_gpu_addr >> 8; 3771 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3772 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3773 3774 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3775 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3776 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3777 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3778 3779 mqd->cp_hqd_eop_control = tmp; 3780 3781 /* enable doorbell? */ 3782 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3783 3784 if (prop->use_doorbell) { 3785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3786 DOORBELL_OFFSET, prop->doorbell_index); 3787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3788 DOORBELL_EN, 1); 3789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3790 DOORBELL_SOURCE, 0); 3791 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3792 DOORBELL_HIT, 0); 3793 } else { 3794 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3795 DOORBELL_EN, 0); 3796 } 3797 3798 mqd->cp_hqd_pq_doorbell_control = tmp; 3799 3800 /* disable the queue if it's active */ 3801 mqd->cp_hqd_dequeue_request = 0; 3802 mqd->cp_hqd_pq_rptr = 0; 3803 mqd->cp_hqd_pq_wptr_lo = 0; 3804 mqd->cp_hqd_pq_wptr_hi = 0; 3805 3806 /* set the pointer to the MQD */ 3807 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3808 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3809 3810 /* set MQD vmid to 0 */ 3811 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3812 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3813 mqd->cp_mqd_control = tmp; 3814 3815 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3816 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3817 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3818 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3819 3820 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3821 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3823 (order_base_2(prop->queue_size / 4) - 1)); 3824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3825 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 3828 prop->allow_tunneling); 3829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3831 mqd->cp_hqd_pq_control = tmp; 3832 3833 /* set the wb address whether it's enabled or not */ 3834 wb_gpu_addr = prop->rptr_gpu_addr; 3835 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3836 mqd->cp_hqd_pq_rptr_report_addr_hi = 3837 upper_32_bits(wb_gpu_addr) & 0xffff; 3838 3839 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3840 wb_gpu_addr = prop->wptr_gpu_addr; 3841 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3842 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3843 3844 tmp = 0; 3845 /* enable the doorbell if requested */ 3846 if (prop->use_doorbell) { 3847 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3848 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3849 DOORBELL_OFFSET, prop->doorbell_index); 3850 3851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3852 DOORBELL_EN, 1); 3853 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3854 DOORBELL_SOURCE, 0); 3855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3856 DOORBELL_HIT, 0); 3857 } 3858 3859 mqd->cp_hqd_pq_doorbell_control = tmp; 3860 3861 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3862 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3863 3864 /* set the vmid for the queue */ 3865 mqd->cp_hqd_vmid = 0; 3866 3867 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3868 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3869 mqd->cp_hqd_persistent_state = tmp; 3870 3871 /* set MIN_IB_AVAIL_SIZE */ 3872 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3873 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3874 mqd->cp_hqd_ib_control = tmp; 3875 3876 /* set static priority for a compute queue/ring */ 3877 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3878 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3879 3880 mqd->cp_hqd_active = prop->hqd_active; 3881 3882 return 0; 3883 } 3884 3885 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3886 { 3887 struct amdgpu_device *adev = ring->adev; 3888 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3889 int j; 3890 3891 /* inactivate the queue */ 3892 if (amdgpu_sriov_vf(adev)) 3893 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3894 3895 /* disable wptr polling */ 3896 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3897 3898 /* write the EOP addr */ 3899 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3900 mqd->cp_hqd_eop_base_addr_lo); 3901 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3902 mqd->cp_hqd_eop_base_addr_hi); 3903 3904 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3905 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3906 mqd->cp_hqd_eop_control); 3907 3908 /* enable doorbell? */ 3909 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3910 mqd->cp_hqd_pq_doorbell_control); 3911 3912 /* disable the queue if it's active */ 3913 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3914 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3915 for (j = 0; j < adev->usec_timeout; j++) { 3916 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3917 break; 3918 udelay(1); 3919 } 3920 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3921 mqd->cp_hqd_dequeue_request); 3922 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3923 mqd->cp_hqd_pq_rptr); 3924 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3925 mqd->cp_hqd_pq_wptr_lo); 3926 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3927 mqd->cp_hqd_pq_wptr_hi); 3928 } 3929 3930 /* set the pointer to the MQD */ 3931 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3932 mqd->cp_mqd_base_addr_lo); 3933 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3934 mqd->cp_mqd_base_addr_hi); 3935 3936 /* set MQD vmid to 0 */ 3937 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3938 mqd->cp_mqd_control); 3939 3940 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3941 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3942 mqd->cp_hqd_pq_base_lo); 3943 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3944 mqd->cp_hqd_pq_base_hi); 3945 3946 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3947 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3948 mqd->cp_hqd_pq_control); 3949 3950 /* set the wb address whether it's enabled or not */ 3951 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3952 mqd->cp_hqd_pq_rptr_report_addr_lo); 3953 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3954 mqd->cp_hqd_pq_rptr_report_addr_hi); 3955 3956 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3957 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3958 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3959 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3960 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3961 3962 /* enable the doorbell if requested */ 3963 if (ring->use_doorbell) { 3964 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3965 (adev->doorbell_index.kiq * 2) << 2); 3966 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3967 (adev->doorbell_index.userqueue_end * 2) << 2); 3968 } 3969 3970 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3971 mqd->cp_hqd_pq_doorbell_control); 3972 3973 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3974 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3975 mqd->cp_hqd_pq_wptr_lo); 3976 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3977 mqd->cp_hqd_pq_wptr_hi); 3978 3979 /* set the vmid for the queue */ 3980 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3981 3982 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3983 mqd->cp_hqd_persistent_state); 3984 3985 /* activate the queue */ 3986 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3987 mqd->cp_hqd_active); 3988 3989 if (ring->use_doorbell) 3990 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3991 3992 return 0; 3993 } 3994 3995 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 3996 { 3997 struct amdgpu_device *adev = ring->adev; 3998 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3999 4000 gfx_v11_0_kiq_setting(ring); 4001 4002 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4003 /* reset MQD to a clean status */ 4004 if (adev->gfx.kiq[0].mqd_backup) 4005 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4006 4007 /* reset ring buffer */ 4008 ring->wptr = 0; 4009 amdgpu_ring_clear_ring(ring); 4010 4011 mutex_lock(&adev->srbm_mutex); 4012 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4013 gfx_v11_0_kiq_init_register(ring); 4014 soc21_grbm_select(adev, 0, 0, 0, 0); 4015 mutex_unlock(&adev->srbm_mutex); 4016 } else { 4017 memset((void *)mqd, 0, sizeof(*mqd)); 4018 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4019 amdgpu_ring_clear_ring(ring); 4020 mutex_lock(&adev->srbm_mutex); 4021 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4022 amdgpu_ring_init_mqd(ring); 4023 gfx_v11_0_kiq_init_register(ring); 4024 soc21_grbm_select(adev, 0, 0, 0, 0); 4025 mutex_unlock(&adev->srbm_mutex); 4026 4027 if (adev->gfx.kiq[0].mqd_backup) 4028 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4029 } 4030 4031 return 0; 4032 } 4033 4034 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4035 { 4036 struct amdgpu_device *adev = ring->adev; 4037 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4038 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4039 4040 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4041 memset((void *)mqd, 0, sizeof(*mqd)); 4042 mutex_lock(&adev->srbm_mutex); 4043 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4044 amdgpu_ring_init_mqd(ring); 4045 soc21_grbm_select(adev, 0, 0, 0, 0); 4046 mutex_unlock(&adev->srbm_mutex); 4047 4048 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4049 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4050 } else { 4051 /* restore MQD to a clean status */ 4052 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4053 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4054 /* reset ring buffer */ 4055 ring->wptr = 0; 4056 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4057 amdgpu_ring_clear_ring(ring); 4058 } 4059 4060 return 0; 4061 } 4062 4063 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4064 { 4065 struct amdgpu_ring *ring; 4066 int r; 4067 4068 ring = &adev->gfx.kiq[0].ring; 4069 4070 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4071 if (unlikely(r != 0)) 4072 return r; 4073 4074 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4075 if (unlikely(r != 0)) { 4076 amdgpu_bo_unreserve(ring->mqd_obj); 4077 return r; 4078 } 4079 4080 gfx_v11_0_kiq_init_queue(ring); 4081 amdgpu_bo_kunmap(ring->mqd_obj); 4082 ring->mqd_ptr = NULL; 4083 amdgpu_bo_unreserve(ring->mqd_obj); 4084 ring->sched.ready = true; 4085 return 0; 4086 } 4087 4088 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4089 { 4090 struct amdgpu_ring *ring = NULL; 4091 int r = 0, i; 4092 4093 if (!amdgpu_async_gfx_ring) 4094 gfx_v11_0_cp_compute_enable(adev, true); 4095 4096 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4097 ring = &adev->gfx.compute_ring[i]; 4098 4099 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4100 if (unlikely(r != 0)) 4101 goto done; 4102 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4103 if (!r) { 4104 r = gfx_v11_0_kcq_init_queue(ring); 4105 amdgpu_bo_kunmap(ring->mqd_obj); 4106 ring->mqd_ptr = NULL; 4107 } 4108 amdgpu_bo_unreserve(ring->mqd_obj); 4109 if (r) 4110 goto done; 4111 } 4112 4113 r = amdgpu_gfx_enable_kcq(adev, 0); 4114 done: 4115 return r; 4116 } 4117 4118 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4119 { 4120 int r, i; 4121 struct amdgpu_ring *ring; 4122 4123 if (!(adev->flags & AMD_IS_APU)) 4124 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4125 4126 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4127 /* legacy firmware loading */ 4128 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4129 if (r) 4130 return r; 4131 4132 if (adev->gfx.rs64_enable) 4133 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4134 else 4135 r = gfx_v11_0_cp_compute_load_microcode(adev); 4136 if (r) 4137 return r; 4138 } 4139 4140 gfx_v11_0_cp_set_doorbell_range(adev); 4141 4142 if (amdgpu_async_gfx_ring) { 4143 gfx_v11_0_cp_compute_enable(adev, true); 4144 gfx_v11_0_cp_gfx_enable(adev, true); 4145 } 4146 4147 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4148 r = amdgpu_mes_kiq_hw_init(adev); 4149 else 4150 r = gfx_v11_0_kiq_resume(adev); 4151 if (r) 4152 return r; 4153 4154 r = gfx_v11_0_kcq_resume(adev); 4155 if (r) 4156 return r; 4157 4158 if (!amdgpu_async_gfx_ring) { 4159 r = gfx_v11_0_cp_gfx_resume(adev); 4160 if (r) 4161 return r; 4162 } else { 4163 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4164 if (r) 4165 return r; 4166 } 4167 4168 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4169 ring = &adev->gfx.gfx_ring[i]; 4170 r = amdgpu_ring_test_helper(ring); 4171 if (r) 4172 return r; 4173 } 4174 4175 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4176 ring = &adev->gfx.compute_ring[i]; 4177 r = amdgpu_ring_test_helper(ring); 4178 if (r) 4179 return r; 4180 } 4181 4182 return 0; 4183 } 4184 4185 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4186 { 4187 gfx_v11_0_cp_gfx_enable(adev, enable); 4188 gfx_v11_0_cp_compute_enable(adev, enable); 4189 } 4190 4191 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4192 { 4193 int r; 4194 bool value; 4195 4196 r = adev->gfxhub.funcs->gart_enable(adev); 4197 if (r) 4198 return r; 4199 4200 adev->hdp.funcs->flush_hdp(adev, NULL); 4201 4202 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4203 false : true; 4204 4205 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4206 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4207 4208 return 0; 4209 } 4210 4211 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4212 { 4213 u32 tmp; 4214 4215 /* select RS64 */ 4216 if (adev->gfx.rs64_enable) { 4217 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4218 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4219 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4220 4221 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4222 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4223 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4224 } 4225 4226 if (amdgpu_emu_mode == 1) 4227 msleep(100); 4228 } 4229 4230 static int get_gb_addr_config(struct amdgpu_device * adev) 4231 { 4232 u32 gb_addr_config; 4233 4234 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4235 if (gb_addr_config == 0) 4236 return -EINVAL; 4237 4238 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4239 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4240 4241 adev->gfx.config.gb_addr_config = gb_addr_config; 4242 4243 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4244 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4245 GB_ADDR_CONFIG, NUM_PIPES); 4246 4247 adev->gfx.config.max_tile_pipes = 4248 adev->gfx.config.gb_addr_config_fields.num_pipes; 4249 4250 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4251 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4252 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4253 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4254 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4255 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4256 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4257 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4258 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4259 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4260 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4261 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4262 4263 return 0; 4264 } 4265 4266 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4267 { 4268 uint32_t data; 4269 4270 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4271 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4272 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4273 4274 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4275 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4276 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4277 } 4278 4279 static int gfx_v11_0_hw_init(void *handle) 4280 { 4281 int r; 4282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4283 4284 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4285 if (adev->gfx.imu.funcs) { 4286 /* RLC autoload sequence 1: Program rlc ram */ 4287 if (adev->gfx.imu.funcs->program_rlc_ram) 4288 adev->gfx.imu.funcs->program_rlc_ram(adev); 4289 } 4290 /* rlc autoload firmware */ 4291 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4292 if (r) 4293 return r; 4294 } else { 4295 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4296 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4297 if (adev->gfx.imu.funcs->load_microcode) 4298 adev->gfx.imu.funcs->load_microcode(adev); 4299 if (adev->gfx.imu.funcs->setup_imu) 4300 adev->gfx.imu.funcs->setup_imu(adev); 4301 if (adev->gfx.imu.funcs->start_imu) 4302 adev->gfx.imu.funcs->start_imu(adev); 4303 } 4304 4305 /* disable gpa mode in backdoor loading */ 4306 gfx_v11_0_disable_gpa_mode(adev); 4307 } 4308 } 4309 4310 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4311 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4312 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4313 if (r) { 4314 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4315 return r; 4316 } 4317 } 4318 4319 adev->gfx.is_poweron = true; 4320 4321 if(get_gb_addr_config(adev)) 4322 DRM_WARN("Invalid gb_addr_config !\n"); 4323 4324 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4325 adev->gfx.rs64_enable) 4326 gfx_v11_0_config_gfx_rs64(adev); 4327 4328 r = gfx_v11_0_gfxhub_enable(adev); 4329 if (r) 4330 return r; 4331 4332 if (!amdgpu_emu_mode) 4333 gfx_v11_0_init_golden_registers(adev); 4334 4335 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4336 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4337 /** 4338 * For gfx 11, rlc firmware loading relies on smu firmware is 4339 * loaded firstly, so in direct type, it has to load smc ucode 4340 * here before rlc. 4341 */ 4342 if (!(adev->flags & AMD_IS_APU)) { 4343 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4344 if (r) 4345 return r; 4346 } 4347 } 4348 4349 gfx_v11_0_constants_init(adev); 4350 4351 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4352 gfx_v11_0_select_cp_fw_arch(adev); 4353 4354 if (adev->nbio.funcs->gc_doorbell_init) 4355 adev->nbio.funcs->gc_doorbell_init(adev); 4356 4357 r = gfx_v11_0_rlc_resume(adev); 4358 if (r) 4359 return r; 4360 4361 /* 4362 * init golden registers and rlc resume may override some registers, 4363 * reconfig them here 4364 */ 4365 gfx_v11_0_tcp_harvest(adev); 4366 4367 r = gfx_v11_0_cp_resume(adev); 4368 if (r) 4369 return r; 4370 4371 /* get IMU version from HW if it's not set */ 4372 if (!adev->gfx.imu_fw_version) 4373 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); 4374 4375 return r; 4376 } 4377 4378 static int gfx_v11_0_hw_fini(void *handle) 4379 { 4380 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4381 4382 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4383 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4384 4385 if (!adev->no_hw_access) { 4386 if (amdgpu_async_gfx_ring) { 4387 if (amdgpu_gfx_disable_kgq(adev, 0)) 4388 DRM_ERROR("KGQ disable failed\n"); 4389 } 4390 4391 if (amdgpu_gfx_disable_kcq(adev, 0)) 4392 DRM_ERROR("KCQ disable failed\n"); 4393 4394 amdgpu_mes_kiq_hw_fini(adev); 4395 } 4396 4397 if (amdgpu_sriov_vf(adev)) 4398 /* Remove the steps disabling CPG and clearing KIQ position, 4399 * so that CP could perform IDLE-SAVE during switch. Those 4400 * steps are necessary to avoid a DMAR error in gfx9 but it is 4401 * not reproduced on gfx11. 4402 */ 4403 return 0; 4404 4405 gfx_v11_0_cp_enable(adev, false); 4406 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4407 4408 adev->gfxhub.funcs->gart_disable(adev); 4409 4410 adev->gfx.is_poweron = false; 4411 4412 return 0; 4413 } 4414 4415 static int gfx_v11_0_suspend(void *handle) 4416 { 4417 return gfx_v11_0_hw_fini(handle); 4418 } 4419 4420 static int gfx_v11_0_resume(void *handle) 4421 { 4422 return gfx_v11_0_hw_init(handle); 4423 } 4424 4425 static bool gfx_v11_0_is_idle(void *handle) 4426 { 4427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4428 4429 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4430 GRBM_STATUS, GUI_ACTIVE)) 4431 return false; 4432 else 4433 return true; 4434 } 4435 4436 static int gfx_v11_0_wait_for_idle(void *handle) 4437 { 4438 unsigned i; 4439 u32 tmp; 4440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4441 4442 for (i = 0; i < adev->usec_timeout; i++) { 4443 /* read MC_STATUS */ 4444 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4445 GRBM_STATUS__GUI_ACTIVE_MASK; 4446 4447 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4448 return 0; 4449 udelay(1); 4450 } 4451 return -ETIMEDOUT; 4452 } 4453 4454 static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, 4455 int req) 4456 { 4457 u32 i, tmp, val; 4458 4459 for (i = 0; i < adev->usec_timeout; i++) { 4460 /* Request with MeId=2, PipeId=0 */ 4461 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); 4462 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4); 4463 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); 4464 4465 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); 4466 if (req) { 4467 if (val == tmp) 4468 break; 4469 } else { 4470 tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, 4471 REQUEST, 1); 4472 4473 /* unlocked or locked by firmware */ 4474 if (val != tmp) 4475 break; 4476 } 4477 udelay(1); 4478 } 4479 4480 if (i >= adev->usec_timeout) 4481 return -EINVAL; 4482 4483 return 0; 4484 } 4485 4486 static int gfx_v11_0_soft_reset(void *handle) 4487 { 4488 u32 grbm_soft_reset = 0; 4489 u32 tmp; 4490 int r, i, j, k; 4491 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4492 4493 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4494 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4495 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4496 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4497 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4498 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4499 4500 gfx_v11_0_set_safe_mode(adev, 0); 4501 4502 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4503 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4504 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4505 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4506 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4507 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4508 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4509 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4510 4511 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4512 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4513 } 4514 } 4515 } 4516 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4517 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4518 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4519 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4520 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4521 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4522 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4523 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4524 4525 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4526 } 4527 } 4528 } 4529 4530 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ 4531 r = gfx_v11_0_request_gfx_index_mutex(adev, 1); 4532 if (r) { 4533 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); 4534 return r; 4535 } 4536 4537 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4538 4539 // Read CP_VMID_RESET register three times. 4540 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4541 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4542 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4543 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4544 4545 /* release the gfx mutex */ 4546 r = gfx_v11_0_request_gfx_index_mutex(adev, 0); 4547 if (r) { 4548 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); 4549 return r; 4550 } 4551 4552 for (i = 0; i < adev->usec_timeout; i++) { 4553 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4554 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4555 break; 4556 udelay(1); 4557 } 4558 if (i >= adev->usec_timeout) { 4559 printk("Failed to wait all pipes clean\n"); 4560 return -EINVAL; 4561 } 4562 4563 /********** trigger soft reset ***********/ 4564 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4565 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4566 SOFT_RESET_CP, 1); 4567 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4568 SOFT_RESET_GFX, 1); 4569 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4570 SOFT_RESET_CPF, 1); 4571 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4572 SOFT_RESET_CPC, 1); 4573 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4574 SOFT_RESET_CPG, 1); 4575 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4576 /********** exit soft reset ***********/ 4577 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4578 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4579 SOFT_RESET_CP, 0); 4580 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4581 SOFT_RESET_GFX, 0); 4582 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4583 SOFT_RESET_CPF, 0); 4584 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4585 SOFT_RESET_CPC, 0); 4586 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4587 SOFT_RESET_CPG, 0); 4588 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4589 4590 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4591 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4592 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4593 4594 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4595 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4596 4597 for (i = 0; i < adev->usec_timeout; i++) { 4598 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4599 break; 4600 udelay(1); 4601 } 4602 if (i >= adev->usec_timeout) { 4603 printk("Failed to wait CP_VMID_RESET to 0\n"); 4604 return -EINVAL; 4605 } 4606 4607 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4608 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4609 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4610 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4611 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4612 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4613 4614 gfx_v11_0_unset_safe_mode(adev, 0); 4615 4616 return gfx_v11_0_cp_resume(adev); 4617 } 4618 4619 static bool gfx_v11_0_check_soft_reset(void *handle) 4620 { 4621 int i, r; 4622 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4623 struct amdgpu_ring *ring; 4624 long tmo = msecs_to_jiffies(1000); 4625 4626 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4627 ring = &adev->gfx.gfx_ring[i]; 4628 r = amdgpu_ring_test_ib(ring, tmo); 4629 if (r) 4630 return true; 4631 } 4632 4633 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4634 ring = &adev->gfx.compute_ring[i]; 4635 r = amdgpu_ring_test_ib(ring, tmo); 4636 if (r) 4637 return true; 4638 } 4639 4640 return false; 4641 } 4642 4643 static int gfx_v11_0_post_soft_reset(void *handle) 4644 { 4645 /** 4646 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4647 */ 4648 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4649 } 4650 4651 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4652 { 4653 uint64_t clock; 4654 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4655 4656 if (amdgpu_sriov_vf(adev)) { 4657 amdgpu_gfx_off_ctrl(adev, false); 4658 mutex_lock(&adev->gfx.gpu_clock_mutex); 4659 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4660 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4661 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4662 if (clock_counter_hi_pre != clock_counter_hi_after) 4663 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4664 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4665 amdgpu_gfx_off_ctrl(adev, true); 4666 } else { 4667 preempt_disable(); 4668 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4669 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4670 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4671 if (clock_counter_hi_pre != clock_counter_hi_after) 4672 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4673 preempt_enable(); 4674 } 4675 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4676 4677 return clock; 4678 } 4679 4680 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4681 uint32_t vmid, 4682 uint32_t gds_base, uint32_t gds_size, 4683 uint32_t gws_base, uint32_t gws_size, 4684 uint32_t oa_base, uint32_t oa_size) 4685 { 4686 struct amdgpu_device *adev = ring->adev; 4687 4688 /* GDS Base */ 4689 gfx_v11_0_write_data_to_reg(ring, 0, false, 4690 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4691 gds_base); 4692 4693 /* GDS Size */ 4694 gfx_v11_0_write_data_to_reg(ring, 0, false, 4695 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4696 gds_size); 4697 4698 /* GWS */ 4699 gfx_v11_0_write_data_to_reg(ring, 0, false, 4700 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4701 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4702 4703 /* OA */ 4704 gfx_v11_0_write_data_to_reg(ring, 0, false, 4705 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4706 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4707 } 4708 4709 static int gfx_v11_0_early_init(void *handle) 4710 { 4711 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4712 4713 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4714 4715 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4716 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4717 AMDGPU_MAX_COMPUTE_RINGS); 4718 4719 gfx_v11_0_set_kiq_pm4_funcs(adev); 4720 gfx_v11_0_set_ring_funcs(adev); 4721 gfx_v11_0_set_irq_funcs(adev); 4722 gfx_v11_0_set_gds_init(adev); 4723 gfx_v11_0_set_rlc_funcs(adev); 4724 gfx_v11_0_set_mqd_funcs(adev); 4725 gfx_v11_0_set_imu_funcs(adev); 4726 4727 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4728 4729 return gfx_v11_0_init_microcode(adev); 4730 } 4731 4732 static int gfx_v11_0_late_init(void *handle) 4733 { 4734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4735 int r; 4736 4737 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4738 if (r) 4739 return r; 4740 4741 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4742 if (r) 4743 return r; 4744 4745 return 0; 4746 } 4747 4748 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4749 { 4750 uint32_t rlc_cntl; 4751 4752 /* if RLC is not enabled, do nothing */ 4753 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4754 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4755 } 4756 4757 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4758 { 4759 uint32_t data; 4760 unsigned i; 4761 4762 data = RLC_SAFE_MODE__CMD_MASK; 4763 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4764 4765 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4766 4767 /* wait for RLC_SAFE_MODE */ 4768 for (i = 0; i < adev->usec_timeout; i++) { 4769 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4770 RLC_SAFE_MODE, CMD)) 4771 break; 4772 udelay(1); 4773 } 4774 } 4775 4776 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4777 { 4778 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4779 } 4780 4781 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4782 bool enable) 4783 { 4784 uint32_t def, data; 4785 4786 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4787 return; 4788 4789 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4790 4791 if (enable) 4792 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4793 else 4794 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4795 4796 if (def != data) 4797 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4798 } 4799 4800 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4801 bool enable) 4802 { 4803 uint32_t def, data; 4804 4805 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4806 return; 4807 4808 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4809 4810 if (enable) 4811 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4812 else 4813 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4814 4815 if (def != data) 4816 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4817 } 4818 4819 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4820 bool enable) 4821 { 4822 uint32_t def, data; 4823 4824 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4825 return; 4826 4827 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4828 4829 if (enable) 4830 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4831 else 4832 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4833 4834 if (def != data) 4835 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4836 } 4837 4838 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4839 bool enable) 4840 { 4841 uint32_t data, def; 4842 4843 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4844 return; 4845 4846 /* It is disabled by HW by default */ 4847 if (enable) { 4848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4849 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4850 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4851 4852 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4853 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4854 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4855 4856 if (def != data) 4857 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4858 } 4859 } else { 4860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4861 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4862 4863 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4864 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4865 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4866 4867 if (def != data) 4868 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4869 } 4870 } 4871 } 4872 4873 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4874 bool enable) 4875 { 4876 uint32_t def, data; 4877 4878 if (!(adev->cg_flags & 4879 (AMD_CG_SUPPORT_GFX_CGCG | 4880 AMD_CG_SUPPORT_GFX_CGLS | 4881 AMD_CG_SUPPORT_GFX_3D_CGCG | 4882 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4883 return; 4884 4885 if (enable) { 4886 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4887 4888 /* unset CGCG override */ 4889 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4890 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4891 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4892 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4893 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4894 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4895 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4896 4897 /* update CGCG override bits */ 4898 if (def != data) 4899 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4900 4901 /* enable cgcg FSM(0x0000363F) */ 4902 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4903 4904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4905 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4906 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4907 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4908 } 4909 4910 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4911 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4912 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4913 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4914 } 4915 4916 if (def != data) 4917 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4918 4919 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4920 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4921 4922 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4923 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4924 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4925 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4926 } 4927 4928 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4929 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4930 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4931 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4932 } 4933 4934 if (def != data) 4935 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4936 4937 /* set IDLE_POLL_COUNT(0x00900100) */ 4938 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4939 4940 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4941 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4942 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4943 4944 if (def != data) 4945 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4946 4947 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4948 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4949 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4950 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4951 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4952 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4953 4954 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4955 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4956 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4957 4958 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4959 if (adev->sdma.num_instances > 1) { 4960 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4961 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4962 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4963 } 4964 } else { 4965 /* Program RLC_CGCG_CGLS_CTRL */ 4966 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4967 4968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4969 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4970 4971 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4972 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4973 4974 if (def != data) 4975 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4976 4977 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4978 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4979 4980 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4981 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4982 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4983 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4984 4985 if (def != data) 4986 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4987 4988 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4989 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4990 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4991 4992 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4993 if (adev->sdma.num_instances > 1) { 4994 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4995 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4996 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4997 } 4998 } 4999 } 5000 5001 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5002 bool enable) 5003 { 5004 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5005 5006 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5007 5008 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5009 5010 gfx_v11_0_update_repeater_fgcg(adev, enable); 5011 5012 gfx_v11_0_update_sram_fgcg(adev, enable); 5013 5014 gfx_v11_0_update_perf_clk(adev, enable); 5015 5016 if (adev->cg_flags & 5017 (AMD_CG_SUPPORT_GFX_MGCG | 5018 AMD_CG_SUPPORT_GFX_CGLS | 5019 AMD_CG_SUPPORT_GFX_CGCG | 5020 AMD_CG_SUPPORT_GFX_3D_CGCG | 5021 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5022 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5023 5024 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5025 5026 return 0; 5027 } 5028 5029 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) 5030 { 5031 u32 data; 5032 5033 amdgpu_gfx_off_ctrl(adev, false); 5034 5035 data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL); 5036 5037 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5038 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5039 5040 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5041 5042 amdgpu_gfx_off_ctrl(adev, true); 5043 5044 if (ring 5045 && amdgpu_sriov_is_pp_one_vf(adev) 5046 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 5047 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 5048 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5049 amdgpu_ring_emit_wreg(ring, reg, data); 5050 } 5051 } 5052 5053 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5054 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5055 .set_safe_mode = gfx_v11_0_set_safe_mode, 5056 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5057 .init = gfx_v11_0_rlc_init, 5058 .get_csb_size = gfx_v11_0_get_csb_size, 5059 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5060 .resume = gfx_v11_0_rlc_resume, 5061 .stop = gfx_v11_0_rlc_stop, 5062 .reset = gfx_v11_0_rlc_reset, 5063 .start = gfx_v11_0_rlc_start, 5064 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5065 }; 5066 5067 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5068 { 5069 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5070 5071 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5072 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5073 else 5074 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5075 5076 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5077 5078 // Program RLC_PG_DELAY3 for CGPG hysteresis 5079 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5080 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5081 case IP_VERSION(11, 0, 1): 5082 case IP_VERSION(11, 0, 4): 5083 case IP_VERSION(11, 5, 0): 5084 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5085 break; 5086 default: 5087 break; 5088 } 5089 } 5090 } 5091 5092 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5093 { 5094 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5095 5096 gfx_v11_cntl_power_gating(adev, enable); 5097 5098 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5099 } 5100 5101 static int gfx_v11_0_set_powergating_state(void *handle, 5102 enum amd_powergating_state state) 5103 { 5104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5105 bool enable = (state == AMD_PG_STATE_GATE); 5106 5107 if (amdgpu_sriov_vf(adev)) 5108 return 0; 5109 5110 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5111 case IP_VERSION(11, 0, 0): 5112 case IP_VERSION(11, 0, 2): 5113 case IP_VERSION(11, 0, 3): 5114 amdgpu_gfx_off_ctrl(adev, enable); 5115 break; 5116 case IP_VERSION(11, 0, 1): 5117 case IP_VERSION(11, 0, 4): 5118 case IP_VERSION(11, 5, 0): 5119 if (!enable) 5120 amdgpu_gfx_off_ctrl(adev, false); 5121 5122 gfx_v11_cntl_pg(adev, enable); 5123 5124 if (enable) 5125 amdgpu_gfx_off_ctrl(adev, true); 5126 5127 break; 5128 default: 5129 break; 5130 } 5131 5132 return 0; 5133 } 5134 5135 static int gfx_v11_0_set_clockgating_state(void *handle, 5136 enum amd_clockgating_state state) 5137 { 5138 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5139 5140 if (amdgpu_sriov_vf(adev)) 5141 return 0; 5142 5143 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 5144 case IP_VERSION(11, 0, 0): 5145 case IP_VERSION(11, 0, 1): 5146 case IP_VERSION(11, 0, 2): 5147 case IP_VERSION(11, 0, 3): 5148 case IP_VERSION(11, 0, 4): 5149 case IP_VERSION(11, 5, 0): 5150 gfx_v11_0_update_gfx_clock_gating(adev, 5151 state == AMD_CG_STATE_GATE); 5152 break; 5153 default: 5154 break; 5155 } 5156 5157 return 0; 5158 } 5159 5160 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5161 { 5162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5163 int data; 5164 5165 /* AMD_CG_SUPPORT_GFX_MGCG */ 5166 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5167 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5168 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5169 5170 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5171 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5172 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5173 5174 /* AMD_CG_SUPPORT_GFX_FGCG */ 5175 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5176 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5177 5178 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5179 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5180 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5181 5182 /* AMD_CG_SUPPORT_GFX_CGCG */ 5183 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5184 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5185 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5186 5187 /* AMD_CG_SUPPORT_GFX_CGLS */ 5188 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5189 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5190 5191 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5192 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5193 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5194 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5195 5196 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5197 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5198 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5199 } 5200 5201 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5202 { 5203 /* gfx11 is 32bit rptr*/ 5204 return *(uint32_t *)ring->rptr_cpu_addr; 5205 } 5206 5207 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5208 { 5209 struct amdgpu_device *adev = ring->adev; 5210 u64 wptr; 5211 5212 /* XXX check if swapping is necessary on BE */ 5213 if (ring->use_doorbell) { 5214 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5215 } else { 5216 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5217 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5218 } 5219 5220 return wptr; 5221 } 5222 5223 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5224 { 5225 struct amdgpu_device *adev = ring->adev; 5226 5227 if (ring->use_doorbell) { 5228 /* XXX check if swapping is necessary on BE */ 5229 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5230 ring->wptr); 5231 WDOORBELL64(ring->doorbell_index, ring->wptr); 5232 } else { 5233 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5234 lower_32_bits(ring->wptr)); 5235 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5236 upper_32_bits(ring->wptr)); 5237 } 5238 } 5239 5240 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5241 { 5242 /* gfx11 hardware is 32bit rptr */ 5243 return *(uint32_t *)ring->rptr_cpu_addr; 5244 } 5245 5246 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5247 { 5248 u64 wptr; 5249 5250 /* XXX check if swapping is necessary on BE */ 5251 if (ring->use_doorbell) 5252 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5253 else 5254 BUG(); 5255 return wptr; 5256 } 5257 5258 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5259 { 5260 struct amdgpu_device *adev = ring->adev; 5261 5262 /* XXX check if swapping is necessary on BE */ 5263 if (ring->use_doorbell) { 5264 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5265 ring->wptr); 5266 WDOORBELL64(ring->doorbell_index, ring->wptr); 5267 } else { 5268 BUG(); /* only DOORBELL method supported on gfx11 now */ 5269 } 5270 } 5271 5272 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5273 { 5274 struct amdgpu_device *adev = ring->adev; 5275 u32 ref_and_mask, reg_mem_engine; 5276 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5277 5278 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5279 switch (ring->me) { 5280 case 1: 5281 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5282 break; 5283 case 2: 5284 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5285 break; 5286 default: 5287 return; 5288 } 5289 reg_mem_engine = 0; 5290 } else { 5291 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5292 reg_mem_engine = 1; /* pfp */ 5293 } 5294 5295 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5296 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5297 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5298 ref_and_mask, ref_and_mask, 0x20); 5299 } 5300 5301 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5302 struct amdgpu_job *job, 5303 struct amdgpu_ib *ib, 5304 uint32_t flags) 5305 { 5306 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5307 u32 header, control = 0; 5308 5309 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5310 5311 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5312 5313 control |= ib->length_dw | (vmid << 24); 5314 5315 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5316 control |= INDIRECT_BUFFER_PRE_ENB(1); 5317 5318 if (flags & AMDGPU_IB_PREEMPTED) 5319 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5320 5321 if (vmid) 5322 gfx_v11_0_ring_emit_de_meta(ring, 5323 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5324 } 5325 5326 if (ring->is_mes_queue) 5327 /* inherit vmid from mqd */ 5328 control |= 0x400000; 5329 5330 amdgpu_ring_write(ring, header); 5331 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5332 amdgpu_ring_write(ring, 5333 #ifdef __BIG_ENDIAN 5334 (2 << 0) | 5335 #endif 5336 lower_32_bits(ib->gpu_addr)); 5337 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5338 amdgpu_ring_write(ring, control); 5339 } 5340 5341 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5342 struct amdgpu_job *job, 5343 struct amdgpu_ib *ib, 5344 uint32_t flags) 5345 { 5346 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5347 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5348 5349 if (ring->is_mes_queue) 5350 /* inherit vmid from mqd */ 5351 control |= 0x40000000; 5352 5353 /* Currently, there is a high possibility to get wave ID mismatch 5354 * between ME and GDS, leading to a hw deadlock, because ME generates 5355 * different wave IDs than the GDS expects. This situation happens 5356 * randomly when at least 5 compute pipes use GDS ordered append. 5357 * The wave IDs generated by ME are also wrong after suspend/resume. 5358 * Those are probably bugs somewhere else in the kernel driver. 5359 * 5360 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5361 * GDS to 0 for this ring (me/pipe). 5362 */ 5363 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5364 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5365 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5366 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5367 } 5368 5369 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5370 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5371 amdgpu_ring_write(ring, 5372 #ifdef __BIG_ENDIAN 5373 (2 << 0) | 5374 #endif 5375 lower_32_bits(ib->gpu_addr)); 5376 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5377 amdgpu_ring_write(ring, control); 5378 } 5379 5380 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5381 u64 seq, unsigned flags) 5382 { 5383 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5384 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5385 5386 /* RELEASE_MEM - flush caches, send int */ 5387 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5388 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5389 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5390 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5391 PACKET3_RELEASE_MEM_GCR_GL2_US | 5392 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5393 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5394 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5395 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5396 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5397 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5398 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5399 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5400 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5401 5402 /* 5403 * the address should be Qword aligned if 64bit write, Dword 5404 * aligned if only send 32bit data low (discard data high) 5405 */ 5406 if (write64bit) 5407 BUG_ON(addr & 0x7); 5408 else 5409 BUG_ON(addr & 0x3); 5410 amdgpu_ring_write(ring, lower_32_bits(addr)); 5411 amdgpu_ring_write(ring, upper_32_bits(addr)); 5412 amdgpu_ring_write(ring, lower_32_bits(seq)); 5413 amdgpu_ring_write(ring, upper_32_bits(seq)); 5414 amdgpu_ring_write(ring, ring->is_mes_queue ? 5415 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5416 } 5417 5418 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5419 { 5420 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5421 uint32_t seq = ring->fence_drv.sync_seq; 5422 uint64_t addr = ring->fence_drv.gpu_addr; 5423 5424 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5425 upper_32_bits(addr), seq, 0xffffffff, 4); 5426 } 5427 5428 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5429 uint16_t pasid, uint32_t flush_type, 5430 bool all_hub, uint8_t dst_sel) 5431 { 5432 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5433 amdgpu_ring_write(ring, 5434 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5435 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5436 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5437 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5438 } 5439 5440 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5441 unsigned vmid, uint64_t pd_addr) 5442 { 5443 if (ring->is_mes_queue) 5444 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5445 else 5446 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5447 5448 /* compute doesn't have PFP */ 5449 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5450 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5451 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5452 amdgpu_ring_write(ring, 0x0); 5453 } 5454 } 5455 5456 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5457 u64 seq, unsigned int flags) 5458 { 5459 struct amdgpu_device *adev = ring->adev; 5460 5461 /* we only allocate 32bit for each seq wb address */ 5462 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5463 5464 /* write fence seq to the "addr" */ 5465 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5466 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5467 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5468 amdgpu_ring_write(ring, lower_32_bits(addr)); 5469 amdgpu_ring_write(ring, upper_32_bits(addr)); 5470 amdgpu_ring_write(ring, lower_32_bits(seq)); 5471 5472 if (flags & AMDGPU_FENCE_FLAG_INT) { 5473 /* set register to trigger INT */ 5474 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5475 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5476 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5477 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5478 amdgpu_ring_write(ring, 0); 5479 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5480 } 5481 } 5482 5483 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5484 uint32_t flags) 5485 { 5486 uint32_t dw2 = 0; 5487 5488 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5489 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5490 /* set load_global_config & load_global_uconfig */ 5491 dw2 |= 0x8001; 5492 /* set load_cs_sh_regs */ 5493 dw2 |= 0x01000000; 5494 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5495 dw2 |= 0x10002; 5496 } 5497 5498 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5499 amdgpu_ring_write(ring, dw2); 5500 amdgpu_ring_write(ring, 0); 5501 } 5502 5503 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5504 u64 shadow_va, u64 csa_va, 5505 u64 gds_va, bool init_shadow, 5506 int vmid) 5507 { 5508 struct amdgpu_device *adev = ring->adev; 5509 5510 if (!adev->gfx.cp_gfx_shadow) 5511 return; 5512 5513 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5514 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5515 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5516 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5517 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5518 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5519 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5520 amdgpu_ring_write(ring, shadow_va ? 5521 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5522 amdgpu_ring_write(ring, init_shadow ? 5523 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5524 } 5525 5526 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5527 { 5528 unsigned ret; 5529 5530 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5531 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5532 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5533 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5534 ret = ring->wptr & ring->buf_mask; 5535 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5536 5537 return ret; 5538 } 5539 5540 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5541 { 5542 unsigned cur; 5543 BUG_ON(offset > ring->buf_mask); 5544 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5545 5546 cur = (ring->wptr - 1) & ring->buf_mask; 5547 if (likely(cur > offset)) 5548 ring->ring[offset] = cur - offset; 5549 else 5550 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5551 } 5552 5553 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5554 { 5555 int i, r = 0; 5556 struct amdgpu_device *adev = ring->adev; 5557 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5558 struct amdgpu_ring *kiq_ring = &kiq->ring; 5559 unsigned long flags; 5560 5561 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5562 return -EINVAL; 5563 5564 spin_lock_irqsave(&kiq->ring_lock, flags); 5565 5566 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5567 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5568 return -ENOMEM; 5569 } 5570 5571 /* assert preemption condition */ 5572 amdgpu_ring_set_preempt_cond_exec(ring, false); 5573 5574 /* assert IB preemption, emit the trailing fence */ 5575 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5576 ring->trail_fence_gpu_addr, 5577 ++ring->trail_seq); 5578 amdgpu_ring_commit(kiq_ring); 5579 5580 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5581 5582 /* poll the trailing fence */ 5583 for (i = 0; i < adev->usec_timeout; i++) { 5584 if (ring->trail_seq == 5585 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5586 break; 5587 udelay(1); 5588 } 5589 5590 if (i >= adev->usec_timeout) { 5591 r = -EINVAL; 5592 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5593 } 5594 5595 /* deassert preemption condition */ 5596 amdgpu_ring_set_preempt_cond_exec(ring, true); 5597 return r; 5598 } 5599 5600 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5601 { 5602 struct amdgpu_device *adev = ring->adev; 5603 struct v10_de_ib_state de_payload = {0}; 5604 uint64_t offset, gds_addr, de_payload_gpu_addr; 5605 void *de_payload_cpu_addr; 5606 int cnt; 5607 5608 if (ring->is_mes_queue) { 5609 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5610 gfx[0].gfx_meta_data) + 5611 offsetof(struct v10_gfx_meta_data, de_payload); 5612 de_payload_gpu_addr = 5613 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5614 de_payload_cpu_addr = 5615 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5616 5617 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5618 gfx[0].gds_backup) + 5619 offsetof(struct v10_gfx_meta_data, de_payload); 5620 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5621 } else { 5622 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5623 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5624 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5625 5626 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5627 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5628 PAGE_SIZE); 5629 } 5630 5631 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5632 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5633 5634 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5635 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5636 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5637 WRITE_DATA_DST_SEL(8) | 5638 WR_CONFIRM) | 5639 WRITE_DATA_CACHE_POLICY(0)); 5640 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5641 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5642 5643 if (resume) 5644 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5645 sizeof(de_payload) >> 2); 5646 else 5647 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5648 sizeof(de_payload) >> 2); 5649 } 5650 5651 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5652 bool secure) 5653 { 5654 uint32_t v = secure ? FRAME_TMZ : 0; 5655 5656 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5657 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5658 } 5659 5660 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5661 uint32_t reg_val_offs) 5662 { 5663 struct amdgpu_device *adev = ring->adev; 5664 5665 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5666 amdgpu_ring_write(ring, 0 | /* src: register*/ 5667 (5 << 8) | /* dst: memory */ 5668 (1 << 20)); /* write confirm */ 5669 amdgpu_ring_write(ring, reg); 5670 amdgpu_ring_write(ring, 0); 5671 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5672 reg_val_offs * 4)); 5673 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5674 reg_val_offs * 4)); 5675 } 5676 5677 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5678 uint32_t val) 5679 { 5680 uint32_t cmd = 0; 5681 5682 switch (ring->funcs->type) { 5683 case AMDGPU_RING_TYPE_GFX: 5684 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5685 break; 5686 case AMDGPU_RING_TYPE_KIQ: 5687 cmd = (1 << 16); /* no inc addr */ 5688 break; 5689 default: 5690 cmd = WR_CONFIRM; 5691 break; 5692 } 5693 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5694 amdgpu_ring_write(ring, cmd); 5695 amdgpu_ring_write(ring, reg); 5696 amdgpu_ring_write(ring, 0); 5697 amdgpu_ring_write(ring, val); 5698 } 5699 5700 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5701 uint32_t val, uint32_t mask) 5702 { 5703 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5704 } 5705 5706 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5707 uint32_t reg0, uint32_t reg1, 5708 uint32_t ref, uint32_t mask) 5709 { 5710 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5711 5712 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5713 ref, mask, 0x20); 5714 } 5715 5716 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5717 unsigned vmid) 5718 { 5719 struct amdgpu_device *adev = ring->adev; 5720 uint32_t value = 0; 5721 5722 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5723 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5724 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5725 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5726 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5727 } 5728 5729 static void 5730 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5731 uint32_t me, uint32_t pipe, 5732 enum amdgpu_interrupt_state state) 5733 { 5734 uint32_t cp_int_cntl, cp_int_cntl_reg; 5735 5736 if (!me) { 5737 switch (pipe) { 5738 case 0: 5739 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5740 break; 5741 case 1: 5742 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5743 break; 5744 default: 5745 DRM_DEBUG("invalid pipe %d\n", pipe); 5746 return; 5747 } 5748 } else { 5749 DRM_DEBUG("invalid me %d\n", me); 5750 return; 5751 } 5752 5753 switch (state) { 5754 case AMDGPU_IRQ_STATE_DISABLE: 5755 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5756 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5757 TIME_STAMP_INT_ENABLE, 0); 5758 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5759 GENERIC0_INT_ENABLE, 0); 5760 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5761 break; 5762 case AMDGPU_IRQ_STATE_ENABLE: 5763 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5764 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5765 TIME_STAMP_INT_ENABLE, 1); 5766 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5767 GENERIC0_INT_ENABLE, 1); 5768 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5769 break; 5770 default: 5771 break; 5772 } 5773 } 5774 5775 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5776 int me, int pipe, 5777 enum amdgpu_interrupt_state state) 5778 { 5779 u32 mec_int_cntl, mec_int_cntl_reg; 5780 5781 /* 5782 * amdgpu controls only the first MEC. That's why this function only 5783 * handles the setting of interrupts for this specific MEC. All other 5784 * pipes' interrupts are set by amdkfd. 5785 */ 5786 5787 if (me == 1) { 5788 switch (pipe) { 5789 case 0: 5790 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5791 break; 5792 case 1: 5793 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5794 break; 5795 case 2: 5796 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5797 break; 5798 case 3: 5799 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5800 break; 5801 default: 5802 DRM_DEBUG("invalid pipe %d\n", pipe); 5803 return; 5804 } 5805 } else { 5806 DRM_DEBUG("invalid me %d\n", me); 5807 return; 5808 } 5809 5810 switch (state) { 5811 case AMDGPU_IRQ_STATE_DISABLE: 5812 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5813 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5814 TIME_STAMP_INT_ENABLE, 0); 5815 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5816 GENERIC0_INT_ENABLE, 0); 5817 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5818 break; 5819 case AMDGPU_IRQ_STATE_ENABLE: 5820 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5821 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5822 TIME_STAMP_INT_ENABLE, 1); 5823 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5824 GENERIC0_INT_ENABLE, 1); 5825 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5826 break; 5827 default: 5828 break; 5829 } 5830 } 5831 5832 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5833 struct amdgpu_irq_src *src, 5834 unsigned type, 5835 enum amdgpu_interrupt_state state) 5836 { 5837 switch (type) { 5838 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5839 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5840 break; 5841 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5842 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5843 break; 5844 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5845 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5846 break; 5847 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5848 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5849 break; 5850 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5851 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5852 break; 5853 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5854 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5855 break; 5856 default: 5857 break; 5858 } 5859 return 0; 5860 } 5861 5862 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5863 struct amdgpu_irq_src *source, 5864 struct amdgpu_iv_entry *entry) 5865 { 5866 int i; 5867 u8 me_id, pipe_id, queue_id; 5868 struct amdgpu_ring *ring; 5869 uint32_t mes_queue_id = entry->src_data[0]; 5870 5871 DRM_DEBUG("IH: CP EOP\n"); 5872 5873 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5874 struct amdgpu_mes_queue *queue; 5875 5876 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5877 5878 spin_lock(&adev->mes.queue_id_lock); 5879 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5880 if (queue) { 5881 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5882 amdgpu_fence_process(queue->ring); 5883 } 5884 spin_unlock(&adev->mes.queue_id_lock); 5885 } else { 5886 me_id = (entry->ring_id & 0x0c) >> 2; 5887 pipe_id = (entry->ring_id & 0x03) >> 0; 5888 queue_id = (entry->ring_id & 0x70) >> 4; 5889 5890 switch (me_id) { 5891 case 0: 5892 if (pipe_id == 0) 5893 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5894 else 5895 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5896 break; 5897 case 1: 5898 case 2: 5899 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5900 ring = &adev->gfx.compute_ring[i]; 5901 /* Per-queue interrupt is supported for MEC starting from VI. 5902 * The interrupt can only be enabled/disabled per pipe instead 5903 * of per queue. 5904 */ 5905 if ((ring->me == me_id) && 5906 (ring->pipe == pipe_id) && 5907 (ring->queue == queue_id)) 5908 amdgpu_fence_process(ring); 5909 } 5910 break; 5911 } 5912 } 5913 5914 return 0; 5915 } 5916 5917 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5918 struct amdgpu_irq_src *source, 5919 unsigned type, 5920 enum amdgpu_interrupt_state state) 5921 { 5922 switch (state) { 5923 case AMDGPU_IRQ_STATE_DISABLE: 5924 case AMDGPU_IRQ_STATE_ENABLE: 5925 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5926 PRIV_REG_INT_ENABLE, 5927 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5928 break; 5929 default: 5930 break; 5931 } 5932 5933 return 0; 5934 } 5935 5936 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5937 struct amdgpu_irq_src *source, 5938 unsigned type, 5939 enum amdgpu_interrupt_state state) 5940 { 5941 switch (state) { 5942 case AMDGPU_IRQ_STATE_DISABLE: 5943 case AMDGPU_IRQ_STATE_ENABLE: 5944 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5945 PRIV_INSTR_INT_ENABLE, 5946 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5947 break; 5948 default: 5949 break; 5950 } 5951 5952 return 0; 5953 } 5954 5955 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5956 struct amdgpu_iv_entry *entry) 5957 { 5958 u8 me_id, pipe_id, queue_id; 5959 struct amdgpu_ring *ring; 5960 int i; 5961 5962 me_id = (entry->ring_id & 0x0c) >> 2; 5963 pipe_id = (entry->ring_id & 0x03) >> 0; 5964 queue_id = (entry->ring_id & 0x70) >> 4; 5965 5966 switch (me_id) { 5967 case 0: 5968 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5969 ring = &adev->gfx.gfx_ring[i]; 5970 /* we only enabled 1 gfx queue per pipe for now */ 5971 if (ring->me == me_id && ring->pipe == pipe_id) 5972 drm_sched_fault(&ring->sched); 5973 } 5974 break; 5975 case 1: 5976 case 2: 5977 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5978 ring = &adev->gfx.compute_ring[i]; 5979 if (ring->me == me_id && ring->pipe == pipe_id && 5980 ring->queue == queue_id) 5981 drm_sched_fault(&ring->sched); 5982 } 5983 break; 5984 default: 5985 BUG(); 5986 break; 5987 } 5988 } 5989 5990 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 5991 struct amdgpu_irq_src *source, 5992 struct amdgpu_iv_entry *entry) 5993 { 5994 DRM_ERROR("Illegal register access in command stream\n"); 5995 gfx_v11_0_handle_priv_fault(adev, entry); 5996 return 0; 5997 } 5998 5999 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6000 struct amdgpu_irq_src *source, 6001 struct amdgpu_iv_entry *entry) 6002 { 6003 DRM_ERROR("Illegal instruction in command stream\n"); 6004 gfx_v11_0_handle_priv_fault(adev, entry); 6005 return 0; 6006 } 6007 6008 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6009 struct amdgpu_irq_src *source, 6010 struct amdgpu_iv_entry *entry) 6011 { 6012 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6013 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6014 6015 return 0; 6016 } 6017 6018 #if 0 6019 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6020 struct amdgpu_irq_src *src, 6021 unsigned int type, 6022 enum amdgpu_interrupt_state state) 6023 { 6024 uint32_t tmp, target; 6025 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6026 6027 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6028 target += ring->pipe; 6029 6030 switch (type) { 6031 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6032 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6033 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6034 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6035 GENERIC2_INT_ENABLE, 0); 6036 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6037 6038 tmp = RREG32_SOC15_IP(GC, target); 6039 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6040 GENERIC2_INT_ENABLE, 0); 6041 WREG32_SOC15_IP(GC, target, tmp); 6042 } else { 6043 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6044 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6045 GENERIC2_INT_ENABLE, 1); 6046 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6047 6048 tmp = RREG32_SOC15_IP(GC, target); 6049 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6050 GENERIC2_INT_ENABLE, 1); 6051 WREG32_SOC15_IP(GC, target, tmp); 6052 } 6053 break; 6054 default: 6055 BUG(); /* kiq only support GENERIC2_INT now */ 6056 break; 6057 } 6058 return 0; 6059 } 6060 #endif 6061 6062 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6063 { 6064 const unsigned int gcr_cntl = 6065 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6066 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6067 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6068 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6069 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6070 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6073 6074 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6075 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6076 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6077 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6078 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6079 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6080 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6081 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6082 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6083 } 6084 6085 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6086 .name = "gfx_v11_0", 6087 .early_init = gfx_v11_0_early_init, 6088 .late_init = gfx_v11_0_late_init, 6089 .sw_init = gfx_v11_0_sw_init, 6090 .sw_fini = gfx_v11_0_sw_fini, 6091 .hw_init = gfx_v11_0_hw_init, 6092 .hw_fini = gfx_v11_0_hw_fini, 6093 .suspend = gfx_v11_0_suspend, 6094 .resume = gfx_v11_0_resume, 6095 .is_idle = gfx_v11_0_is_idle, 6096 .wait_for_idle = gfx_v11_0_wait_for_idle, 6097 .soft_reset = gfx_v11_0_soft_reset, 6098 .check_soft_reset = gfx_v11_0_check_soft_reset, 6099 .post_soft_reset = gfx_v11_0_post_soft_reset, 6100 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6101 .set_powergating_state = gfx_v11_0_set_powergating_state, 6102 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6103 }; 6104 6105 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6106 .type = AMDGPU_RING_TYPE_GFX, 6107 .align_mask = 0xff, 6108 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6109 .support_64bit_ptrs = true, 6110 .secure_submission_supported = true, 6111 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6112 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6113 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6114 .emit_frame_size = /* totally 247 maximum if 16 IBs */ 6115 5 + /* update_spm_vmid */ 6116 5 + /* COND_EXEC */ 6117 9 + /* SET_Q_PREEMPTION_MODE */ 6118 7 + /* PIPELINE_SYNC */ 6119 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6120 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6121 2 + /* VM_FLUSH */ 6122 8 + /* FENCE for VM_FLUSH */ 6123 20 + /* GDS switch */ 6124 5 + /* COND_EXEC */ 6125 7 + /* HDP_flush */ 6126 4 + /* VGT_flush */ 6127 31 + /* DE_META */ 6128 3 + /* CNTX_CTRL */ 6129 5 + /* HDP_INVL */ 6130 8 + 8 + /* FENCE x2 */ 6131 8, /* gfx_v11_0_emit_mem_sync */ 6132 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6133 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6134 .emit_fence = gfx_v11_0_ring_emit_fence, 6135 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6136 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6137 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6138 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6139 .test_ring = gfx_v11_0_ring_test_ring, 6140 .test_ib = gfx_v11_0_ring_test_ib, 6141 .insert_nop = amdgpu_ring_insert_nop, 6142 .pad_ib = amdgpu_ring_generic_pad_ib, 6143 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6144 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6145 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6146 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6147 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6148 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6149 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6150 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6151 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6152 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6153 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6154 }; 6155 6156 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6157 .type = AMDGPU_RING_TYPE_COMPUTE, 6158 .align_mask = 0xff, 6159 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6160 .support_64bit_ptrs = true, 6161 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6162 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6163 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6164 .emit_frame_size = 6165 5 + /* update_spm_vmid */ 6166 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6167 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6168 5 + /* hdp invalidate */ 6169 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6170 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6171 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6172 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6173 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6174 8, /* gfx_v11_0_emit_mem_sync */ 6175 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6176 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6177 .emit_fence = gfx_v11_0_ring_emit_fence, 6178 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6179 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6180 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6181 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6182 .test_ring = gfx_v11_0_ring_test_ring, 6183 .test_ib = gfx_v11_0_ring_test_ib, 6184 .insert_nop = amdgpu_ring_insert_nop, 6185 .pad_ib = amdgpu_ring_generic_pad_ib, 6186 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6187 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6188 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6189 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6190 }; 6191 6192 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6193 .type = AMDGPU_RING_TYPE_KIQ, 6194 .align_mask = 0xff, 6195 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6196 .support_64bit_ptrs = true, 6197 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6198 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6199 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6200 .emit_frame_size = 6201 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6202 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6203 5 + /*hdp invalidate */ 6204 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6205 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6206 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6207 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6208 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6209 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6210 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6211 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6212 .test_ring = gfx_v11_0_ring_test_ring, 6213 .test_ib = gfx_v11_0_ring_test_ib, 6214 .insert_nop = amdgpu_ring_insert_nop, 6215 .pad_ib = amdgpu_ring_generic_pad_ib, 6216 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6217 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6218 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6219 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6220 }; 6221 6222 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6223 { 6224 int i; 6225 6226 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6227 6228 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6229 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6230 6231 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6232 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6233 } 6234 6235 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6236 .set = gfx_v11_0_set_eop_interrupt_state, 6237 .process = gfx_v11_0_eop_irq, 6238 }; 6239 6240 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6241 .set = gfx_v11_0_set_priv_reg_fault_state, 6242 .process = gfx_v11_0_priv_reg_irq, 6243 }; 6244 6245 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6246 .set = gfx_v11_0_set_priv_inst_fault_state, 6247 .process = gfx_v11_0_priv_inst_irq, 6248 }; 6249 6250 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6251 .process = gfx_v11_0_rlc_gc_fed_irq, 6252 }; 6253 6254 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6255 { 6256 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6257 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6258 6259 adev->gfx.priv_reg_irq.num_types = 1; 6260 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6261 6262 adev->gfx.priv_inst_irq.num_types = 1; 6263 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6264 6265 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6266 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6267 6268 } 6269 6270 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6271 { 6272 if (adev->flags & AMD_IS_APU) 6273 adev->gfx.imu.mode = MISSION_MODE; 6274 else 6275 adev->gfx.imu.mode = DEBUG_MODE; 6276 6277 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6278 } 6279 6280 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6281 { 6282 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6283 } 6284 6285 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6286 { 6287 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6288 adev->gfx.config.max_sh_per_se * 6289 adev->gfx.config.max_shader_engines; 6290 6291 adev->gds.gds_size = 0x1000; 6292 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6293 adev->gds.gws_size = 64; 6294 adev->gds.oa_size = 16; 6295 } 6296 6297 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6298 { 6299 /* set gfx eng mqd */ 6300 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6301 sizeof(struct v11_gfx_mqd); 6302 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6303 gfx_v11_0_gfx_mqd_init; 6304 /* set compute eng mqd */ 6305 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6306 sizeof(struct v11_compute_mqd); 6307 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6308 gfx_v11_0_compute_mqd_init; 6309 } 6310 6311 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6312 u32 bitmap) 6313 { 6314 u32 data; 6315 6316 if (!bitmap) 6317 return; 6318 6319 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6320 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6321 6322 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6323 } 6324 6325 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6326 { 6327 u32 data, wgp_bitmask; 6328 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6329 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6330 6331 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6332 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6333 6334 wgp_bitmask = 6335 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6336 6337 return (~data) & wgp_bitmask; 6338 } 6339 6340 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6341 { 6342 u32 wgp_idx, wgp_active_bitmap; 6343 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6344 6345 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6346 cu_active_bitmap = 0; 6347 6348 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6349 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6350 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6351 if (wgp_active_bitmap & (1 << wgp_idx)) 6352 cu_active_bitmap |= cu_bitmap_per_wgp; 6353 } 6354 6355 return cu_active_bitmap; 6356 } 6357 6358 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6359 struct amdgpu_cu_info *cu_info) 6360 { 6361 int i, j, k, counter, active_cu_number = 0; 6362 u32 mask, bitmap; 6363 unsigned disable_masks[8 * 2]; 6364 6365 if (!adev || !cu_info) 6366 return -EINVAL; 6367 6368 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6369 6370 mutex_lock(&adev->grbm_idx_mutex); 6371 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6372 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6373 bitmap = i * adev->gfx.config.max_sh_per_se + j; 6374 if (!((gfx_v11_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 6375 continue; 6376 mask = 1; 6377 counter = 0; 6378 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6379 if (i < 8 && j < 2) 6380 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6381 adev, disable_masks[i * 2 + j]); 6382 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6383 6384 /** 6385 * GFX11 could support more than 4 SEs, while the bitmap 6386 * in cu_info struct is 4x4 and ioctl interface struct 6387 * drm_amdgpu_info_device should keep stable. 6388 * So we use last two columns of bitmap to store cu mask for 6389 * SEs 4 to 7, the layout of the bitmap is as below: 6390 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6391 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6392 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6393 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6394 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6395 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6396 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6397 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6398 */ 6399 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 6400 6401 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6402 if (bitmap & mask) 6403 counter++; 6404 6405 mask <<= 1; 6406 } 6407 active_cu_number += counter; 6408 } 6409 } 6410 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6411 mutex_unlock(&adev->grbm_idx_mutex); 6412 6413 cu_info->number = active_cu_number; 6414 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6415 6416 return 0; 6417 } 6418 6419 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6420 { 6421 .type = AMD_IP_BLOCK_TYPE_GFX, 6422 .major = 11, 6423 .minor = 0, 6424 .rev = 0, 6425 .funcs = &gfx_v11_0_ip_funcs, 6426 }; 6427