1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 57 58 #define regCGTT_WD_CLK_CTRL 0x5086 59 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 62 63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 84 85 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 86 { 87 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 96 }; 97 98 #define DEFAULT_SH_MEM_CONFIG \ 99 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 100 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 101 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 102 103 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 104 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 105 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 106 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 107 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 110 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 111 struct amdgpu_cu_info *cu_info); 112 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 113 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 114 u32 sh_num, u32 instance); 115 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 116 117 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 118 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 119 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 120 uint32_t val); 121 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 122 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 123 uint16_t pasid, uint32_t flush_type, 124 bool all_hub, uint8_t dst_sel); 125 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev); 126 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev); 127 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 128 bool enable); 129 130 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 131 { 132 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 133 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 134 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 135 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 136 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 137 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 139 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 140 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 141 } 142 143 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 144 struct amdgpu_ring *ring) 145 { 146 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 147 uint64_t wptr_addr = ring->wptr_gpu_addr; 148 uint32_t me = 0, eng_sel = 0; 149 150 switch (ring->funcs->type) { 151 case AMDGPU_RING_TYPE_COMPUTE: 152 me = 1; 153 eng_sel = 0; 154 break; 155 case AMDGPU_RING_TYPE_GFX: 156 me = 0; 157 eng_sel = 4; 158 break; 159 case AMDGPU_RING_TYPE_MES: 160 me = 2; 161 eng_sel = 5; 162 break; 163 default: 164 WARN_ON(1); 165 } 166 167 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 168 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 169 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 170 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 171 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 172 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 173 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 174 PACKET3_MAP_QUEUES_ME((me)) | 175 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 176 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 177 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 178 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 179 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 180 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 181 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 182 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 183 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 184 } 185 186 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 187 struct amdgpu_ring *ring, 188 enum amdgpu_unmap_queues_action action, 189 u64 gpu_addr, u64 seq) 190 { 191 struct amdgpu_device *adev = kiq_ring->adev; 192 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 193 194 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 195 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 196 return; 197 } 198 199 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 200 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 201 PACKET3_UNMAP_QUEUES_ACTION(action) | 202 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 203 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 204 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 205 amdgpu_ring_write(kiq_ring, 206 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 207 208 if (action == PREEMPT_QUEUES_NO_UNMAP) { 209 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 210 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 211 amdgpu_ring_write(kiq_ring, seq); 212 } else { 213 amdgpu_ring_write(kiq_ring, 0); 214 amdgpu_ring_write(kiq_ring, 0); 215 amdgpu_ring_write(kiq_ring, 0); 216 } 217 } 218 219 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 220 struct amdgpu_ring *ring, 221 u64 addr, 222 u64 seq) 223 { 224 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 225 226 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 227 amdgpu_ring_write(kiq_ring, 228 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 229 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 230 PACKET3_QUERY_STATUS_COMMAND(2)); 231 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 232 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 233 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 234 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 235 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 236 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 237 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 238 } 239 240 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 241 uint16_t pasid, uint32_t flush_type, 242 bool all_hub) 243 { 244 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 245 } 246 247 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 248 .kiq_set_resources = gfx11_kiq_set_resources, 249 .kiq_map_queues = gfx11_kiq_map_queues, 250 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 251 .kiq_query_status = gfx11_kiq_query_status, 252 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 253 .set_resources_size = 8, 254 .map_queues_size = 7, 255 .unmap_queues_size = 6, 256 .query_status_size = 7, 257 .invalidate_tlbs_size = 2, 258 }; 259 260 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 261 { 262 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 263 } 264 265 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 266 { 267 switch (adev->ip_versions[GC_HWIP][0]) { 268 case IP_VERSION(11, 0, 1): 269 case IP_VERSION(11, 0, 4): 270 soc15_program_register_sequence(adev, 271 golden_settings_gc_11_0_1, 272 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 273 break; 274 default: 275 break; 276 } 277 } 278 279 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 280 bool wc, uint32_t reg, uint32_t val) 281 { 282 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 283 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 284 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 285 amdgpu_ring_write(ring, reg); 286 amdgpu_ring_write(ring, 0); 287 amdgpu_ring_write(ring, val); 288 } 289 290 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 291 int mem_space, int opt, uint32_t addr0, 292 uint32_t addr1, uint32_t ref, uint32_t mask, 293 uint32_t inv) 294 { 295 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 296 amdgpu_ring_write(ring, 297 /* memory (1) or register (0) */ 298 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 299 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 300 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 301 WAIT_REG_MEM_ENGINE(eng_sel))); 302 303 if (mem_space) 304 BUG_ON(addr0 & 0x3); /* Dword align */ 305 amdgpu_ring_write(ring, addr0); 306 amdgpu_ring_write(ring, addr1); 307 amdgpu_ring_write(ring, ref); 308 amdgpu_ring_write(ring, mask); 309 amdgpu_ring_write(ring, inv); /* poll interval */ 310 } 311 312 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 313 { 314 struct amdgpu_device *adev = ring->adev; 315 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 316 uint32_t tmp = 0; 317 unsigned i; 318 int r; 319 320 WREG32(scratch, 0xCAFEDEAD); 321 r = amdgpu_ring_alloc(ring, 5); 322 if (r) { 323 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 324 ring->idx, r); 325 return r; 326 } 327 328 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 329 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 330 } else { 331 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 332 amdgpu_ring_write(ring, scratch - 333 PACKET3_SET_UCONFIG_REG_START); 334 amdgpu_ring_write(ring, 0xDEADBEEF); 335 } 336 amdgpu_ring_commit(ring); 337 338 for (i = 0; i < adev->usec_timeout; i++) { 339 tmp = RREG32(scratch); 340 if (tmp == 0xDEADBEEF) 341 break; 342 if (amdgpu_emu_mode == 1) 343 msleep(1); 344 else 345 udelay(1); 346 } 347 348 if (i >= adev->usec_timeout) 349 r = -ETIMEDOUT; 350 return r; 351 } 352 353 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 354 { 355 struct amdgpu_device *adev = ring->adev; 356 struct amdgpu_ib ib; 357 struct dma_fence *f = NULL; 358 unsigned index; 359 uint64_t gpu_addr; 360 volatile uint32_t *cpu_ptr; 361 long r; 362 363 /* MES KIQ fw hasn't indirect buffer support for now */ 364 if (adev->enable_mes_kiq && 365 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 366 return 0; 367 368 memset(&ib, 0, sizeof(ib)); 369 370 if (ring->is_mes_queue) { 371 uint32_t padding, offset; 372 373 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 374 padding = amdgpu_mes_ctx_get_offs(ring, 375 AMDGPU_MES_CTX_PADDING_OFFS); 376 377 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 378 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 379 380 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 381 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 382 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 383 } else { 384 r = amdgpu_device_wb_get(adev, &index); 385 if (r) 386 return r; 387 388 gpu_addr = adev->wb.gpu_addr + (index * 4); 389 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 390 cpu_ptr = &adev->wb.wb[index]; 391 392 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 393 if (r) { 394 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 395 goto err1; 396 } 397 } 398 399 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 400 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 401 ib.ptr[2] = lower_32_bits(gpu_addr); 402 ib.ptr[3] = upper_32_bits(gpu_addr); 403 ib.ptr[4] = 0xDEADBEEF; 404 ib.length_dw = 5; 405 406 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 407 if (r) 408 goto err2; 409 410 r = dma_fence_wait_timeout(f, false, timeout); 411 if (r == 0) { 412 r = -ETIMEDOUT; 413 goto err2; 414 } else if (r < 0) { 415 goto err2; 416 } 417 418 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 419 r = 0; 420 else 421 r = -EINVAL; 422 err2: 423 if (!ring->is_mes_queue) 424 amdgpu_ib_free(adev, &ib, NULL); 425 dma_fence_put(f); 426 err1: 427 if (!ring->is_mes_queue) 428 amdgpu_device_wb_free(adev, index); 429 return r; 430 } 431 432 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 433 { 434 release_firmware(adev->gfx.pfp_fw); 435 adev->gfx.pfp_fw = NULL; 436 release_firmware(adev->gfx.me_fw); 437 adev->gfx.me_fw = NULL; 438 release_firmware(adev->gfx.rlc_fw); 439 adev->gfx.rlc_fw = NULL; 440 release_firmware(adev->gfx.mec_fw); 441 adev->gfx.mec_fw = NULL; 442 443 kfree(adev->gfx.rlc.register_list_format); 444 } 445 446 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 447 { 448 char fw_name[40]; 449 char ucode_prefix[30]; 450 int err; 451 const struct rlc_firmware_header_v2_0 *rlc_hdr; 452 uint16_t version_major; 453 uint16_t version_minor; 454 455 DRM_DEBUG("\n"); 456 457 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 458 459 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 460 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 461 if (err) 462 goto out; 463 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 464 if (err) 465 goto out; 466 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 467 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 468 (union amdgpu_firmware_header *) 469 adev->gfx.pfp_fw->data, 2, 0); 470 if (adev->gfx.rs64_enable) { 471 dev_info(adev->dev, "CP RS64 enable\n"); 472 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 473 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 474 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 475 } else { 476 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 477 } 478 479 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 480 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 481 if (err) 482 goto out; 483 err = amdgpu_ucode_validate(adev->gfx.me_fw); 484 if (err) 485 goto out; 486 if (adev->gfx.rs64_enable) { 487 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 488 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 489 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 490 } else { 491 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 492 } 493 494 if (!amdgpu_sriov_vf(adev)) { 495 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 496 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 497 if (err) 498 goto out; 499 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 500 if (err) 501 goto out; 502 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 503 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 504 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 505 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 506 if (err) 507 goto out; 508 } 509 510 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 511 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 512 if (err) 513 goto out; 514 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 515 if (err) 516 goto out; 517 if (adev->gfx.rs64_enable) { 518 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 519 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 520 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 521 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 522 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 523 } else { 524 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 525 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 526 } 527 528 /* only one MEC for gfx 11.0.0. */ 529 adev->gfx.mec2_fw = NULL; 530 531 out: 532 if (err) { 533 dev_err(adev->dev, 534 "gfx11: Failed to init firmware \"%s\"\n", 535 fw_name); 536 release_firmware(adev->gfx.pfp_fw); 537 adev->gfx.pfp_fw = NULL; 538 release_firmware(adev->gfx.me_fw); 539 adev->gfx.me_fw = NULL; 540 release_firmware(adev->gfx.rlc_fw); 541 adev->gfx.rlc_fw = NULL; 542 release_firmware(adev->gfx.mec_fw); 543 adev->gfx.mec_fw = NULL; 544 } 545 546 return err; 547 } 548 549 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 550 { 551 const struct psp_firmware_header_v1_0 *toc_hdr; 552 int err = 0; 553 char fw_name[40]; 554 char ucode_prefix[30]; 555 556 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 557 558 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 559 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 560 if (err) 561 goto out; 562 563 err = amdgpu_ucode_validate(adev->psp.toc_fw); 564 if (err) 565 goto out; 566 567 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 568 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 569 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 570 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 571 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 572 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 573 return 0; 574 out: 575 dev_err(adev->dev, "Failed to load TOC microcode\n"); 576 release_firmware(adev->psp.toc_fw); 577 adev->psp.toc_fw = NULL; 578 return err; 579 } 580 581 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 582 { 583 u32 count = 0; 584 const struct cs_section_def *sect = NULL; 585 const struct cs_extent_def *ext = NULL; 586 587 /* begin clear state */ 588 count += 2; 589 /* context control state */ 590 count += 3; 591 592 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 593 for (ext = sect->section; ext->extent != NULL; ++ext) { 594 if (sect->id == SECT_CONTEXT) 595 count += 2 + ext->reg_count; 596 else 597 return 0; 598 } 599 } 600 601 /* set PA_SC_TILE_STEERING_OVERRIDE */ 602 count += 3; 603 /* end clear state */ 604 count += 2; 605 /* clear state */ 606 count += 2; 607 608 return count; 609 } 610 611 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 612 volatile u32 *buffer) 613 { 614 u32 count = 0, i; 615 const struct cs_section_def *sect = NULL; 616 const struct cs_extent_def *ext = NULL; 617 int ctx_reg_offset; 618 619 if (adev->gfx.rlc.cs_data == NULL) 620 return; 621 if (buffer == NULL) 622 return; 623 624 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 625 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 626 627 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 628 buffer[count++] = cpu_to_le32(0x80000000); 629 buffer[count++] = cpu_to_le32(0x80000000); 630 631 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 632 for (ext = sect->section; ext->extent != NULL; ++ext) { 633 if (sect->id == SECT_CONTEXT) { 634 buffer[count++] = 635 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 636 buffer[count++] = cpu_to_le32(ext->reg_index - 637 PACKET3_SET_CONTEXT_REG_START); 638 for (i = 0; i < ext->reg_count; i++) 639 buffer[count++] = cpu_to_le32(ext->extent[i]); 640 } else { 641 return; 642 } 643 } 644 } 645 646 ctx_reg_offset = 647 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 648 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 649 buffer[count++] = cpu_to_le32(ctx_reg_offset); 650 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 651 652 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 653 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 654 655 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 656 buffer[count++] = cpu_to_le32(0); 657 } 658 659 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 660 { 661 /* clear state block */ 662 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 663 &adev->gfx.rlc.clear_state_gpu_addr, 664 (void **)&adev->gfx.rlc.cs_ptr); 665 666 /* jump table block */ 667 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 668 &adev->gfx.rlc.cp_table_gpu_addr, 669 (void **)&adev->gfx.rlc.cp_table_ptr); 670 } 671 672 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 673 { 674 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 675 676 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 677 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 678 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 679 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 680 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 681 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 682 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 683 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 684 adev->gfx.rlc.rlcg_reg_access_supported = true; 685 } 686 687 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 688 { 689 const struct cs_section_def *cs_data; 690 int r; 691 692 adev->gfx.rlc.cs_data = gfx11_cs_data; 693 694 cs_data = adev->gfx.rlc.cs_data; 695 696 if (cs_data) { 697 /* init clear state block */ 698 r = amdgpu_gfx_rlc_init_csb(adev); 699 if (r) 700 return r; 701 } 702 703 /* init spm vmid with 0xf */ 704 if (adev->gfx.rlc.funcs->update_spm_vmid) 705 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 706 707 return 0; 708 } 709 710 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 711 { 712 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 713 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 714 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 715 } 716 717 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 718 { 719 int r; 720 721 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 722 723 amdgpu_gfx_graphics_queue_acquire(adev); 724 725 r = gfx_v11_0_init_microcode(adev); 726 if (r) 727 DRM_ERROR("Failed to load gfx firmware!\n"); 728 729 return r; 730 } 731 732 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 733 { 734 int r; 735 u32 *hpd; 736 size_t mec_hpd_size; 737 738 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 739 740 /* take ownership of the relevant compute queues */ 741 amdgpu_gfx_compute_queue_acquire(adev); 742 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 743 744 if (mec_hpd_size) { 745 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 746 AMDGPU_GEM_DOMAIN_GTT, 747 &adev->gfx.mec.hpd_eop_obj, 748 &adev->gfx.mec.hpd_eop_gpu_addr, 749 (void **)&hpd); 750 if (r) { 751 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 752 gfx_v11_0_mec_fini(adev); 753 return r; 754 } 755 756 memset(hpd, 0, mec_hpd_size); 757 758 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 759 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 760 } 761 762 return 0; 763 } 764 765 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 766 { 767 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 768 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 769 (address << SQ_IND_INDEX__INDEX__SHIFT)); 770 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 771 } 772 773 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 774 uint32_t thread, uint32_t regno, 775 uint32_t num, uint32_t *out) 776 { 777 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 778 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 779 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 780 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 781 (SQ_IND_INDEX__AUTO_INCR_MASK)); 782 while (num--) 783 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 784 } 785 786 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 787 { 788 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 789 * field when performing a select_se_sh so it should be 790 * zero here */ 791 WARN_ON(simd != 0); 792 793 /* type 2 wave data */ 794 dst[(*no_fields)++] = 2; 795 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 796 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 797 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 798 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 799 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 800 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 801 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 802 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 803 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 804 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 805 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 806 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 807 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 808 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 809 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 810 } 811 812 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 813 uint32_t wave, uint32_t start, 814 uint32_t size, uint32_t *dst) 815 { 816 WARN_ON(simd != 0); 817 818 wave_read_regs( 819 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 820 dst); 821 } 822 823 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 824 uint32_t wave, uint32_t thread, 825 uint32_t start, uint32_t size, 826 uint32_t *dst) 827 { 828 wave_read_regs( 829 adev, wave, thread, 830 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 831 } 832 833 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 834 u32 me, u32 pipe, u32 q, u32 vm) 835 { 836 soc21_grbm_select(adev, me, pipe, q, vm); 837 } 838 839 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 840 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 841 .select_se_sh = &gfx_v11_0_select_se_sh, 842 .read_wave_data = &gfx_v11_0_read_wave_data, 843 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 844 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 845 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 846 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 847 }; 848 849 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 850 { 851 852 switch (adev->ip_versions[GC_HWIP][0]) { 853 case IP_VERSION(11, 0, 0): 854 case IP_VERSION(11, 0, 2): 855 case IP_VERSION(11, 0, 3): 856 adev->gfx.config.max_hw_contexts = 8; 857 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 858 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 859 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 860 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 861 break; 862 case IP_VERSION(11, 0, 1): 863 case IP_VERSION(11, 0, 4): 864 adev->gfx.config.max_hw_contexts = 8; 865 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 866 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 867 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 868 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 869 break; 870 default: 871 BUG(); 872 break; 873 } 874 875 return 0; 876 } 877 878 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 879 int me, int pipe, int queue) 880 { 881 int r; 882 struct amdgpu_ring *ring; 883 unsigned int irq_type; 884 885 ring = &adev->gfx.gfx_ring[ring_id]; 886 887 ring->me = me; 888 ring->pipe = pipe; 889 ring->queue = queue; 890 891 ring->ring_obj = NULL; 892 ring->use_doorbell = true; 893 894 if (!ring_id) 895 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 896 else 897 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 898 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 899 900 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 901 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 902 AMDGPU_RING_PRIO_DEFAULT, NULL); 903 if (r) 904 return r; 905 return 0; 906 } 907 908 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 909 int mec, int pipe, int queue) 910 { 911 int r; 912 unsigned irq_type; 913 struct amdgpu_ring *ring; 914 unsigned int hw_prio; 915 916 ring = &adev->gfx.compute_ring[ring_id]; 917 918 /* mec0 is me1 */ 919 ring->me = mec + 1; 920 ring->pipe = pipe; 921 ring->queue = queue; 922 923 ring->ring_obj = NULL; 924 ring->use_doorbell = true; 925 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 926 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 927 + (ring_id * GFX11_MEC_HPD_SIZE); 928 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 929 930 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 931 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 932 + ring->pipe; 933 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 934 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 935 /* type-2 packets are deprecated on MEC, use type-3 instead */ 936 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 937 hw_prio, NULL); 938 if (r) 939 return r; 940 941 return 0; 942 } 943 944 static struct { 945 SOC21_FIRMWARE_ID id; 946 unsigned int offset; 947 unsigned int size; 948 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 949 950 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 951 { 952 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 953 954 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 955 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 956 rlc_autoload_info[ucode->id].id = ucode->id; 957 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 958 rlc_autoload_info[ucode->id].size = ucode->size * 4; 959 960 ucode++; 961 } 962 } 963 964 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 965 { 966 uint32_t total_size = 0; 967 SOC21_FIRMWARE_ID id; 968 969 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 970 971 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 972 total_size += rlc_autoload_info[id].size; 973 974 /* In case the offset in rlc toc ucode is aligned */ 975 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 976 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 977 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 978 979 return total_size; 980 } 981 982 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 983 { 984 int r; 985 uint32_t total_size; 986 987 total_size = gfx_v11_0_calc_toc_total_size(adev); 988 989 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 990 AMDGPU_GEM_DOMAIN_VRAM | 991 AMDGPU_GEM_DOMAIN_GTT, 992 &adev->gfx.rlc.rlc_autoload_bo, 993 &adev->gfx.rlc.rlc_autoload_gpu_addr, 994 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 995 996 if (r) { 997 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 998 return r; 999 } 1000 1001 return 0; 1002 } 1003 1004 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1005 SOC21_FIRMWARE_ID id, 1006 const void *fw_data, 1007 uint32_t fw_size, 1008 uint32_t *fw_autoload_mask) 1009 { 1010 uint32_t toc_offset; 1011 uint32_t toc_fw_size; 1012 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1013 1014 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1015 return; 1016 1017 toc_offset = rlc_autoload_info[id].offset; 1018 toc_fw_size = rlc_autoload_info[id].size; 1019 1020 if (fw_size == 0) 1021 fw_size = toc_fw_size; 1022 1023 if (fw_size > toc_fw_size) 1024 fw_size = toc_fw_size; 1025 1026 memcpy(ptr + toc_offset, fw_data, fw_size); 1027 1028 if (fw_size < toc_fw_size) 1029 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1030 1031 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1032 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1033 } 1034 1035 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1036 uint32_t *fw_autoload_mask) 1037 { 1038 void *data; 1039 uint32_t size; 1040 uint64_t *toc_ptr; 1041 1042 *(uint64_t *)fw_autoload_mask |= 0x1; 1043 1044 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1045 1046 data = adev->psp.toc.start_addr; 1047 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1048 1049 toc_ptr = (uint64_t *)data + size / 8 - 1; 1050 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1051 1052 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1053 data, size, fw_autoload_mask); 1054 } 1055 1056 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1057 uint32_t *fw_autoload_mask) 1058 { 1059 const __le32 *fw_data; 1060 uint32_t fw_size; 1061 const struct gfx_firmware_header_v1_0 *cp_hdr; 1062 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1063 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1064 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1065 uint16_t version_major, version_minor; 1066 1067 if (adev->gfx.rs64_enable) { 1068 /* pfp ucode */ 1069 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1070 adev->gfx.pfp_fw->data; 1071 /* instruction */ 1072 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1073 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1074 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1075 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1076 fw_data, fw_size, fw_autoload_mask); 1077 /* data */ 1078 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1079 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1080 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1081 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1082 fw_data, fw_size, fw_autoload_mask); 1083 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1084 fw_data, fw_size, fw_autoload_mask); 1085 /* me ucode */ 1086 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1087 adev->gfx.me_fw->data; 1088 /* instruction */ 1089 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1090 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1091 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1092 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1093 fw_data, fw_size, fw_autoload_mask); 1094 /* data */ 1095 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1096 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1097 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1098 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1099 fw_data, fw_size, fw_autoload_mask); 1100 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1101 fw_data, fw_size, fw_autoload_mask); 1102 /* mec ucode */ 1103 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1104 adev->gfx.mec_fw->data; 1105 /* instruction */ 1106 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1107 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1108 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1109 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1110 fw_data, fw_size, fw_autoload_mask); 1111 /* data */ 1112 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1113 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1114 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1115 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1116 fw_data, fw_size, fw_autoload_mask); 1117 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1118 fw_data, fw_size, fw_autoload_mask); 1119 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1120 fw_data, fw_size, fw_autoload_mask); 1121 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1122 fw_data, fw_size, fw_autoload_mask); 1123 } else { 1124 /* pfp ucode */ 1125 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1126 adev->gfx.pfp_fw->data; 1127 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1128 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1129 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1130 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1131 fw_data, fw_size, fw_autoload_mask); 1132 1133 /* me ucode */ 1134 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1135 adev->gfx.me_fw->data; 1136 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1137 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1138 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1139 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1140 fw_data, fw_size, fw_autoload_mask); 1141 1142 /* mec ucode */ 1143 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1144 adev->gfx.mec_fw->data; 1145 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1146 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1147 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1148 cp_hdr->jt_size * 4; 1149 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1150 fw_data, fw_size, fw_autoload_mask); 1151 } 1152 1153 /* rlc ucode */ 1154 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1155 adev->gfx.rlc_fw->data; 1156 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1157 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1158 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1159 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1160 fw_data, fw_size, fw_autoload_mask); 1161 1162 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1163 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1164 if (version_major == 2) { 1165 if (version_minor >= 2) { 1166 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1167 1168 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1169 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1170 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1171 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1172 fw_data, fw_size, fw_autoload_mask); 1173 1174 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1175 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1176 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1177 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1178 fw_data, fw_size, fw_autoload_mask); 1179 } 1180 } 1181 } 1182 1183 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1184 uint32_t *fw_autoload_mask) 1185 { 1186 const __le32 *fw_data; 1187 uint32_t fw_size; 1188 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1189 1190 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1191 adev->sdma.instance[0].fw->data; 1192 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1193 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1194 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1195 1196 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1197 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1198 1199 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1200 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1201 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1202 1203 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1204 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1205 } 1206 1207 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1208 uint32_t *fw_autoload_mask) 1209 { 1210 const __le32 *fw_data; 1211 unsigned fw_size; 1212 const struct mes_firmware_header_v1_0 *mes_hdr; 1213 int pipe, ucode_id, data_id; 1214 1215 for (pipe = 0; pipe < 2; pipe++) { 1216 if (pipe==0) { 1217 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1218 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1219 } else { 1220 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1221 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1222 } 1223 1224 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1225 adev->mes.fw[pipe]->data; 1226 1227 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1228 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1229 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1230 1231 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1232 ucode_id, fw_data, fw_size, fw_autoload_mask); 1233 1234 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1235 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1236 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1237 1238 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1239 data_id, fw_data, fw_size, fw_autoload_mask); 1240 } 1241 } 1242 1243 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1244 { 1245 uint32_t rlc_g_offset, rlc_g_size; 1246 uint64_t gpu_addr; 1247 uint32_t autoload_fw_id[2]; 1248 1249 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1250 1251 /* RLC autoload sequence 2: copy ucode */ 1252 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1253 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1254 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1255 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1256 1257 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1258 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1259 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1260 1261 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1262 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1263 1264 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1265 1266 /* RLC autoload sequence 3: load IMU fw */ 1267 if (adev->gfx.imu.funcs->load_microcode) 1268 adev->gfx.imu.funcs->load_microcode(adev); 1269 /* RLC autoload sequence 4 init IMU fw */ 1270 if (adev->gfx.imu.funcs->setup_imu) 1271 adev->gfx.imu.funcs->setup_imu(adev); 1272 if (adev->gfx.imu.funcs->start_imu) 1273 adev->gfx.imu.funcs->start_imu(adev); 1274 1275 /* RLC autoload sequence 5 disable gpa mode */ 1276 gfx_v11_0_disable_gpa_mode(adev); 1277 1278 return 0; 1279 } 1280 1281 static int gfx_v11_0_sw_init(void *handle) 1282 { 1283 int i, j, k, r, ring_id = 0; 1284 struct amdgpu_kiq *kiq; 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 1287 adev->gfxhub.funcs->init(adev); 1288 1289 switch (adev->ip_versions[GC_HWIP][0]) { 1290 case IP_VERSION(11, 0, 0): 1291 case IP_VERSION(11, 0, 1): 1292 case IP_VERSION(11, 0, 2): 1293 case IP_VERSION(11, 0, 3): 1294 case IP_VERSION(11, 0, 4): 1295 adev->gfx.me.num_me = 1; 1296 adev->gfx.me.num_pipe_per_me = 1; 1297 adev->gfx.me.num_queue_per_pipe = 1; 1298 adev->gfx.mec.num_mec = 2; 1299 adev->gfx.mec.num_pipe_per_mec = 4; 1300 adev->gfx.mec.num_queue_per_pipe = 4; 1301 break; 1302 default: 1303 adev->gfx.me.num_me = 1; 1304 adev->gfx.me.num_pipe_per_me = 1; 1305 adev->gfx.me.num_queue_per_pipe = 1; 1306 adev->gfx.mec.num_mec = 1; 1307 adev->gfx.mec.num_pipe_per_mec = 4; 1308 adev->gfx.mec.num_queue_per_pipe = 8; 1309 break; 1310 } 1311 1312 /* EOP Event */ 1313 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1314 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1315 &adev->gfx.eop_irq); 1316 if (r) 1317 return r; 1318 1319 /* Privileged reg */ 1320 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1321 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1322 &adev->gfx.priv_reg_irq); 1323 if (r) 1324 return r; 1325 1326 /* Privileged inst */ 1327 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1328 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1329 &adev->gfx.priv_inst_irq); 1330 if (r) 1331 return r; 1332 1333 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1334 1335 if (adev->gfx.imu.funcs) { 1336 if (adev->gfx.imu.funcs->init_microcode) { 1337 r = adev->gfx.imu.funcs->init_microcode(adev); 1338 if (r) 1339 DRM_ERROR("Failed to load imu firmware!\n"); 1340 } 1341 } 1342 1343 r = gfx_v11_0_me_init(adev); 1344 if (r) 1345 return r; 1346 1347 r = gfx_v11_0_rlc_init(adev); 1348 if (r) { 1349 DRM_ERROR("Failed to init rlc BOs!\n"); 1350 return r; 1351 } 1352 1353 r = gfx_v11_0_mec_init(adev); 1354 if (r) { 1355 DRM_ERROR("Failed to init MEC BOs!\n"); 1356 return r; 1357 } 1358 1359 /* set up the gfx ring */ 1360 for (i = 0; i < adev->gfx.me.num_me; i++) { 1361 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1362 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1363 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1364 continue; 1365 1366 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1367 i, k, j); 1368 if (r) 1369 return r; 1370 ring_id++; 1371 } 1372 } 1373 } 1374 1375 ring_id = 0; 1376 /* set up the compute queues - allocate horizontally across pipes */ 1377 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1378 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1379 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1380 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1381 j)) 1382 continue; 1383 1384 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1385 i, k, j); 1386 if (r) 1387 return r; 1388 1389 ring_id++; 1390 } 1391 } 1392 } 1393 1394 if (!adev->enable_mes_kiq) { 1395 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1396 if (r) { 1397 DRM_ERROR("Failed to init KIQ BOs!\n"); 1398 return r; 1399 } 1400 1401 kiq = &adev->gfx.kiq; 1402 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1403 if (r) 1404 return r; 1405 } 1406 1407 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1408 if (r) 1409 return r; 1410 1411 /* allocate visible FB for rlc auto-loading fw */ 1412 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1413 r = gfx_v11_0_init_toc_microcode(adev); 1414 if (r) 1415 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1416 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1417 if (r) 1418 return r; 1419 } 1420 1421 r = gfx_v11_0_gpu_early_init(adev); 1422 if (r) 1423 return r; 1424 1425 return 0; 1426 } 1427 1428 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1429 { 1430 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1431 &adev->gfx.pfp.pfp_fw_gpu_addr, 1432 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1433 1434 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1435 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1436 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1437 } 1438 1439 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1440 { 1441 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1442 &adev->gfx.me.me_fw_gpu_addr, 1443 (void **)&adev->gfx.me.me_fw_ptr); 1444 1445 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1446 &adev->gfx.me.me_fw_data_gpu_addr, 1447 (void **)&adev->gfx.me.me_fw_data_ptr); 1448 } 1449 1450 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1451 { 1452 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1453 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1454 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1455 } 1456 1457 static int gfx_v11_0_sw_fini(void *handle) 1458 { 1459 int i; 1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1461 1462 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1463 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1464 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1465 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1466 1467 amdgpu_gfx_mqd_sw_fini(adev); 1468 1469 if (!adev->enable_mes_kiq) { 1470 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1471 amdgpu_gfx_kiq_fini(adev); 1472 } 1473 1474 gfx_v11_0_pfp_fini(adev); 1475 gfx_v11_0_me_fini(adev); 1476 gfx_v11_0_rlc_fini(adev); 1477 gfx_v11_0_mec_fini(adev); 1478 1479 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1480 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1481 1482 gfx_v11_0_free_microcode(adev); 1483 1484 return 0; 1485 } 1486 1487 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1488 u32 sh_num, u32 instance) 1489 { 1490 u32 data; 1491 1492 if (instance == 0xffffffff) 1493 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1494 INSTANCE_BROADCAST_WRITES, 1); 1495 else 1496 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1497 instance); 1498 1499 if (se_num == 0xffffffff) 1500 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1501 1); 1502 else 1503 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1504 1505 if (sh_num == 0xffffffff) 1506 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1507 1); 1508 else 1509 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1510 1511 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1512 } 1513 1514 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1515 { 1516 u32 data, mask; 1517 1518 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1519 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1520 1521 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1522 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1523 1524 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1525 adev->gfx.config.max_sh_per_se); 1526 1527 return (~data) & mask; 1528 } 1529 1530 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1531 { 1532 int i, j; 1533 u32 data; 1534 u32 active_rbs = 0; 1535 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1536 adev->gfx.config.max_sh_per_se; 1537 1538 mutex_lock(&adev->grbm_idx_mutex); 1539 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1540 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1541 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1542 data = gfx_v11_0_get_rb_active_bitmap(adev); 1543 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1544 rb_bitmap_width_per_sh); 1545 } 1546 } 1547 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1548 mutex_unlock(&adev->grbm_idx_mutex); 1549 1550 adev->gfx.config.backend_enable_mask = active_rbs; 1551 adev->gfx.config.num_rbs = hweight32(active_rbs); 1552 } 1553 1554 #define DEFAULT_SH_MEM_BASES (0x6000) 1555 #define LDS_APP_BASE 0x1 1556 #define SCRATCH_APP_BASE 0x2 1557 1558 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1559 { 1560 int i; 1561 uint32_t sh_mem_bases; 1562 uint32_t data; 1563 1564 /* 1565 * Configure apertures: 1566 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1567 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1568 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1569 */ 1570 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1571 SCRATCH_APP_BASE; 1572 1573 mutex_lock(&adev->srbm_mutex); 1574 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1575 soc21_grbm_select(adev, 0, 0, 0, i); 1576 /* CP and shaders */ 1577 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1578 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1579 1580 /* Enable trap for each kfd vmid. */ 1581 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1582 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1583 } 1584 soc21_grbm_select(adev, 0, 0, 0, 0); 1585 mutex_unlock(&adev->srbm_mutex); 1586 1587 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1588 acccess. These should be enabled by FW for target VMIDs. */ 1589 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1590 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1591 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1592 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1593 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1594 } 1595 } 1596 1597 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1598 { 1599 int vmid; 1600 1601 /* 1602 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1603 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1604 * the driver can enable them for graphics. VMID0 should maintain 1605 * access so that HWS firmware can save/restore entries. 1606 */ 1607 for (vmid = 1; vmid < 16; vmid++) { 1608 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1609 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1610 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1611 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1612 } 1613 } 1614 1615 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1616 { 1617 /* TODO: harvest feature to be added later. */ 1618 } 1619 1620 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1621 { 1622 /* TCCs are global (not instanced). */ 1623 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1624 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1625 1626 adev->gfx.config.tcc_disabled_mask = 1627 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1628 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1629 } 1630 1631 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1632 { 1633 u32 tmp; 1634 int i; 1635 1636 if (!amdgpu_sriov_vf(adev)) 1637 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1638 1639 gfx_v11_0_setup_rb(adev); 1640 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1641 gfx_v11_0_get_tcc_info(adev); 1642 adev->gfx.config.pa_sc_tile_steering_override = 0; 1643 1644 /* XXX SH_MEM regs */ 1645 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1646 mutex_lock(&adev->srbm_mutex); 1647 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1648 soc21_grbm_select(adev, 0, 0, 0, i); 1649 /* CP and shaders */ 1650 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1651 if (i != 0) { 1652 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1653 (adev->gmc.private_aperture_start >> 48)); 1654 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1655 (adev->gmc.shared_aperture_start >> 48)); 1656 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1657 } 1658 } 1659 soc21_grbm_select(adev, 0, 0, 0, 0); 1660 1661 mutex_unlock(&adev->srbm_mutex); 1662 1663 gfx_v11_0_init_compute_vmid(adev); 1664 gfx_v11_0_init_gds_vmid(adev); 1665 } 1666 1667 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1668 bool enable) 1669 { 1670 u32 tmp; 1671 1672 if (amdgpu_sriov_vf(adev)) 1673 return; 1674 1675 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1676 1677 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1678 enable ? 1 : 0); 1679 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1680 enable ? 1 : 0); 1681 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1682 enable ? 1 : 0); 1683 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1684 enable ? 1 : 0); 1685 1686 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1687 } 1688 1689 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1690 { 1691 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1692 1693 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1694 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1695 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1696 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1697 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1698 1699 return 0; 1700 } 1701 1702 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1703 { 1704 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1705 1706 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1707 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1708 } 1709 1710 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1711 { 1712 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1713 udelay(50); 1714 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1715 udelay(50); 1716 } 1717 1718 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1719 bool enable) 1720 { 1721 uint32_t rlc_pg_cntl; 1722 1723 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1724 1725 if (!enable) { 1726 /* RLC_PG_CNTL[23] = 0 (default) 1727 * RLC will wait for handshake acks with SMU 1728 * GFXOFF will be enabled 1729 * RLC_PG_CNTL[23] = 1 1730 * RLC will not issue any message to SMU 1731 * hence no handshake between SMU & RLC 1732 * GFXOFF will be disabled 1733 */ 1734 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1735 } else 1736 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1737 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1738 } 1739 1740 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1741 { 1742 /* TODO: enable rlc & smu handshake until smu 1743 * and gfxoff feature works as expected */ 1744 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1745 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1746 1747 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1748 udelay(50); 1749 } 1750 1751 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1752 { 1753 uint32_t tmp; 1754 1755 /* enable Save Restore Machine */ 1756 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1757 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1758 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1759 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1760 } 1761 1762 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1763 { 1764 const struct rlc_firmware_header_v2_0 *hdr; 1765 const __le32 *fw_data; 1766 unsigned i, fw_size; 1767 1768 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1769 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1770 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1771 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1772 1773 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1774 RLCG_UCODE_LOADING_START_ADDRESS); 1775 1776 for (i = 0; i < fw_size; i++) 1777 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1778 le32_to_cpup(fw_data++)); 1779 1780 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1781 } 1782 1783 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1784 { 1785 const struct rlc_firmware_header_v2_2 *hdr; 1786 const __le32 *fw_data; 1787 unsigned i, fw_size; 1788 u32 tmp; 1789 1790 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1791 1792 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1793 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1794 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1795 1796 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1797 1798 for (i = 0; i < fw_size; i++) { 1799 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1800 msleep(1); 1801 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1802 le32_to_cpup(fw_data++)); 1803 } 1804 1805 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1806 1807 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1808 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1809 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1810 1811 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1812 for (i = 0; i < fw_size; i++) { 1813 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1814 msleep(1); 1815 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1816 le32_to_cpup(fw_data++)); 1817 } 1818 1819 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1820 1821 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1822 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1823 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1824 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1825 } 1826 1827 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1828 { 1829 const struct rlc_firmware_header_v2_3 *hdr; 1830 const __le32 *fw_data; 1831 unsigned i, fw_size; 1832 u32 tmp; 1833 1834 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1835 1836 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1837 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1838 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1839 1840 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1841 1842 for (i = 0; i < fw_size; i++) { 1843 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1844 msleep(1); 1845 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1846 le32_to_cpup(fw_data++)); 1847 } 1848 1849 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1850 1851 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1852 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1853 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1854 1855 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1856 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1857 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1858 1859 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1860 1861 for (i = 0; i < fw_size; i++) { 1862 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1863 msleep(1); 1864 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1865 le32_to_cpup(fw_data++)); 1866 } 1867 1868 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1869 1870 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1871 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1872 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1873 } 1874 1875 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1876 { 1877 const struct rlc_firmware_header_v2_0 *hdr; 1878 uint16_t version_major; 1879 uint16_t version_minor; 1880 1881 if (!adev->gfx.rlc_fw) 1882 return -EINVAL; 1883 1884 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1885 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1886 1887 version_major = le16_to_cpu(hdr->header.header_version_major); 1888 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1889 1890 if (version_major == 2) { 1891 gfx_v11_0_load_rlcg_microcode(adev); 1892 if (amdgpu_dpm == 1) { 1893 if (version_minor >= 2) 1894 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1895 if (version_minor == 3) 1896 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1897 } 1898 1899 return 0; 1900 } 1901 1902 return -EINVAL; 1903 } 1904 1905 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1906 { 1907 int r; 1908 1909 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1910 gfx_v11_0_init_csb(adev); 1911 1912 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1913 gfx_v11_0_rlc_enable_srm(adev); 1914 } else { 1915 if (amdgpu_sriov_vf(adev)) { 1916 gfx_v11_0_init_csb(adev); 1917 return 0; 1918 } 1919 1920 adev->gfx.rlc.funcs->stop(adev); 1921 1922 /* disable CG */ 1923 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1924 1925 /* disable PG */ 1926 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1927 1928 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1929 /* legacy rlc firmware loading */ 1930 r = gfx_v11_0_rlc_load_microcode(adev); 1931 if (r) 1932 return r; 1933 } 1934 1935 gfx_v11_0_init_csb(adev); 1936 1937 adev->gfx.rlc.funcs->start(adev); 1938 } 1939 return 0; 1940 } 1941 1942 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 1943 { 1944 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1945 uint32_t tmp; 1946 int i; 1947 1948 /* Trigger an invalidation of the L1 instruction caches */ 1949 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1950 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1951 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 1952 1953 /* Wait for invalidation complete */ 1954 for (i = 0; i < usec_timeout; i++) { 1955 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1956 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 1957 INVALIDATE_CACHE_COMPLETE)) 1958 break; 1959 udelay(1); 1960 } 1961 1962 if (i >= usec_timeout) { 1963 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 1964 return -EINVAL; 1965 } 1966 1967 if (amdgpu_emu_mode == 1) 1968 adev->hdp.funcs->flush_hdp(adev, NULL); 1969 1970 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 1971 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 1972 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 1973 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 1974 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 1975 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 1976 1977 /* Program me ucode address into intruction cache address register */ 1978 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 1979 lower_32_bits(addr) & 0xFFFFF000); 1980 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 1981 upper_32_bits(addr)); 1982 1983 return 0; 1984 } 1985 1986 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 1987 { 1988 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1989 uint32_t tmp; 1990 int i; 1991 1992 /* Trigger an invalidation of the L1 instruction caches */ 1993 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 1994 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1995 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 1996 1997 /* Wait for invalidation complete */ 1998 for (i = 0; i < usec_timeout; i++) { 1999 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2000 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2001 INVALIDATE_CACHE_COMPLETE)) 2002 break; 2003 udelay(1); 2004 } 2005 2006 if (i >= usec_timeout) { 2007 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2008 return -EINVAL; 2009 } 2010 2011 if (amdgpu_emu_mode == 1) 2012 adev->hdp.funcs->flush_hdp(adev, NULL); 2013 2014 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2015 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2016 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2017 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2018 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2019 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2020 2021 /* Program pfp ucode address into intruction cache address register */ 2022 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2023 lower_32_bits(addr) & 0xFFFFF000); 2024 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2025 upper_32_bits(addr)); 2026 2027 return 0; 2028 } 2029 2030 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2031 { 2032 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2033 uint32_t tmp; 2034 int i; 2035 2036 /* Trigger an invalidation of the L1 instruction caches */ 2037 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2038 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2039 2040 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2041 2042 /* Wait for invalidation complete */ 2043 for (i = 0; i < usec_timeout; i++) { 2044 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2045 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2046 INVALIDATE_CACHE_COMPLETE)) 2047 break; 2048 udelay(1); 2049 } 2050 2051 if (i >= usec_timeout) { 2052 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2053 return -EINVAL; 2054 } 2055 2056 if (amdgpu_emu_mode == 1) 2057 adev->hdp.funcs->flush_hdp(adev, NULL); 2058 2059 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2060 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2061 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2062 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2063 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2064 2065 /* Program mec1 ucode address into intruction cache address register */ 2066 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2067 lower_32_bits(addr) & 0xFFFFF000); 2068 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2069 upper_32_bits(addr)); 2070 2071 return 0; 2072 } 2073 2074 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2075 { 2076 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2077 uint32_t tmp; 2078 unsigned i, pipe_id; 2079 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2080 2081 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2082 adev->gfx.pfp_fw->data; 2083 2084 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2085 lower_32_bits(addr)); 2086 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2087 upper_32_bits(addr)); 2088 2089 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2090 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2091 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2092 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2093 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2094 2095 /* 2096 * Programming any of the CP_PFP_IC_BASE registers 2097 * forces invalidation of the ME L1 I$. Wait for the 2098 * invalidation complete 2099 */ 2100 for (i = 0; i < usec_timeout; i++) { 2101 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2102 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2103 INVALIDATE_CACHE_COMPLETE)) 2104 break; 2105 udelay(1); 2106 } 2107 2108 if (i >= usec_timeout) { 2109 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2110 return -EINVAL; 2111 } 2112 2113 /* Prime the L1 instruction caches */ 2114 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2115 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2116 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2117 /* Waiting for cache primed*/ 2118 for (i = 0; i < usec_timeout; i++) { 2119 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2120 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2121 ICACHE_PRIMED)) 2122 break; 2123 udelay(1); 2124 } 2125 2126 if (i >= usec_timeout) { 2127 dev_err(adev->dev, "failed to prime instruction cache\n"); 2128 return -EINVAL; 2129 } 2130 2131 mutex_lock(&adev->srbm_mutex); 2132 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2133 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2134 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2135 (pfp_hdr->ucode_start_addr_hi << 30) | 2136 (pfp_hdr->ucode_start_addr_lo >> 2)); 2137 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2138 pfp_hdr->ucode_start_addr_hi >> 2); 2139 2140 /* 2141 * Program CP_ME_CNTL to reset given PIPE to take 2142 * effect of CP_PFP_PRGRM_CNTR_START. 2143 */ 2144 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2145 if (pipe_id == 0) 2146 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2147 PFP_PIPE0_RESET, 1); 2148 else 2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2150 PFP_PIPE1_RESET, 1); 2151 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2152 2153 /* Clear pfp pipe0 reset bit. */ 2154 if (pipe_id == 0) 2155 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2156 PFP_PIPE0_RESET, 0); 2157 else 2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2159 PFP_PIPE1_RESET, 0); 2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2161 2162 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2163 lower_32_bits(addr2)); 2164 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2165 upper_32_bits(addr2)); 2166 } 2167 soc21_grbm_select(adev, 0, 0, 0, 0); 2168 mutex_unlock(&adev->srbm_mutex); 2169 2170 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2171 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2172 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2173 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2174 2175 /* Invalidate the data caches */ 2176 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2177 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2178 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2179 2180 for (i = 0; i < usec_timeout; i++) { 2181 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2182 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2183 INVALIDATE_DCACHE_COMPLETE)) 2184 break; 2185 udelay(1); 2186 } 2187 2188 if (i >= usec_timeout) { 2189 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2190 return -EINVAL; 2191 } 2192 2193 return 0; 2194 } 2195 2196 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2197 { 2198 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2199 uint32_t tmp; 2200 unsigned i, pipe_id; 2201 const struct gfx_firmware_header_v2_0 *me_hdr; 2202 2203 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2204 adev->gfx.me_fw->data; 2205 2206 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2207 lower_32_bits(addr)); 2208 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2209 upper_32_bits(addr)); 2210 2211 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2212 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2213 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2214 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2215 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2216 2217 /* 2218 * Programming any of the CP_ME_IC_BASE registers 2219 * forces invalidation of the ME L1 I$. Wait for the 2220 * invalidation complete 2221 */ 2222 for (i = 0; i < usec_timeout; i++) { 2223 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2224 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2225 INVALIDATE_CACHE_COMPLETE)) 2226 break; 2227 udelay(1); 2228 } 2229 2230 if (i >= usec_timeout) { 2231 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2232 return -EINVAL; 2233 } 2234 2235 /* Prime the instruction caches */ 2236 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2237 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2238 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2239 2240 /* Waiting for instruction cache primed*/ 2241 for (i = 0; i < usec_timeout; i++) { 2242 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2243 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2244 ICACHE_PRIMED)) 2245 break; 2246 udelay(1); 2247 } 2248 2249 if (i >= usec_timeout) { 2250 dev_err(adev->dev, "failed to prime instruction cache\n"); 2251 return -EINVAL; 2252 } 2253 2254 mutex_lock(&adev->srbm_mutex); 2255 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2256 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2257 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2258 (me_hdr->ucode_start_addr_hi << 30) | 2259 (me_hdr->ucode_start_addr_lo >> 2) ); 2260 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2261 me_hdr->ucode_start_addr_hi>>2); 2262 2263 /* 2264 * Program CP_ME_CNTL to reset given PIPE to take 2265 * effect of CP_PFP_PRGRM_CNTR_START. 2266 */ 2267 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2268 if (pipe_id == 0) 2269 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2270 ME_PIPE0_RESET, 1); 2271 else 2272 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2273 ME_PIPE1_RESET, 1); 2274 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2275 2276 /* Clear pfp pipe0 reset bit. */ 2277 if (pipe_id == 0) 2278 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2279 ME_PIPE0_RESET, 0); 2280 else 2281 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2282 ME_PIPE1_RESET, 0); 2283 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2284 2285 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2286 lower_32_bits(addr2)); 2287 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2288 upper_32_bits(addr2)); 2289 } 2290 soc21_grbm_select(adev, 0, 0, 0, 0); 2291 mutex_unlock(&adev->srbm_mutex); 2292 2293 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2294 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2295 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2296 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2297 2298 /* Invalidate the data caches */ 2299 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2300 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2301 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2302 2303 for (i = 0; i < usec_timeout; i++) { 2304 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2305 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2306 INVALIDATE_DCACHE_COMPLETE)) 2307 break; 2308 udelay(1); 2309 } 2310 2311 if (i >= usec_timeout) { 2312 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2313 return -EINVAL; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2320 { 2321 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2322 uint32_t tmp; 2323 unsigned i; 2324 const struct gfx_firmware_header_v2_0 *mec_hdr; 2325 2326 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2327 adev->gfx.mec_fw->data; 2328 2329 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2330 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2331 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2332 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2333 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2334 2335 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2336 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2337 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2338 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2339 2340 mutex_lock(&adev->srbm_mutex); 2341 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2342 soc21_grbm_select(adev, 1, i, 0, 0); 2343 2344 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2345 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2346 upper_32_bits(addr2)); 2347 2348 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2349 mec_hdr->ucode_start_addr_lo >> 2 | 2350 mec_hdr->ucode_start_addr_hi << 30); 2351 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2352 mec_hdr->ucode_start_addr_hi >> 2); 2353 2354 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2355 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2356 upper_32_bits(addr)); 2357 } 2358 mutex_unlock(&adev->srbm_mutex); 2359 soc21_grbm_select(adev, 0, 0, 0, 0); 2360 2361 /* Trigger an invalidation of the L1 instruction caches */ 2362 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2363 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2364 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2365 2366 /* Wait for invalidation complete */ 2367 for (i = 0; i < usec_timeout; i++) { 2368 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2369 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2370 INVALIDATE_DCACHE_COMPLETE)) 2371 break; 2372 udelay(1); 2373 } 2374 2375 if (i >= usec_timeout) { 2376 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2377 return -EINVAL; 2378 } 2379 2380 /* Trigger an invalidation of the L1 instruction caches */ 2381 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2382 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2383 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2384 2385 /* Wait for invalidation complete */ 2386 for (i = 0; i < usec_timeout; i++) { 2387 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2388 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2389 INVALIDATE_CACHE_COMPLETE)) 2390 break; 2391 udelay(1); 2392 } 2393 2394 if (i >= usec_timeout) { 2395 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2396 return -EINVAL; 2397 } 2398 2399 return 0; 2400 } 2401 2402 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2403 { 2404 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2405 const struct gfx_firmware_header_v2_0 *me_hdr; 2406 const struct gfx_firmware_header_v2_0 *mec_hdr; 2407 uint32_t pipe_id, tmp; 2408 2409 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2410 adev->gfx.mec_fw->data; 2411 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2412 adev->gfx.me_fw->data; 2413 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2414 adev->gfx.pfp_fw->data; 2415 2416 /* config pfp program start addr */ 2417 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2418 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2419 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2420 (pfp_hdr->ucode_start_addr_hi << 30) | 2421 (pfp_hdr->ucode_start_addr_lo >> 2)); 2422 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2423 pfp_hdr->ucode_start_addr_hi >> 2); 2424 } 2425 soc21_grbm_select(adev, 0, 0, 0, 0); 2426 2427 /* reset pfp pipe */ 2428 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2429 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2430 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2431 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2432 2433 /* clear pfp pipe reset */ 2434 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2435 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2436 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2437 2438 /* config me program start addr */ 2439 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2440 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2441 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2442 (me_hdr->ucode_start_addr_hi << 30) | 2443 (me_hdr->ucode_start_addr_lo >> 2) ); 2444 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2445 me_hdr->ucode_start_addr_hi>>2); 2446 } 2447 soc21_grbm_select(adev, 0, 0, 0, 0); 2448 2449 /* reset me pipe */ 2450 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2451 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2452 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2453 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2454 2455 /* clear me pipe reset */ 2456 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2457 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2458 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2459 2460 /* config mec program start addr */ 2461 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2462 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2463 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2464 mec_hdr->ucode_start_addr_lo >> 2 | 2465 mec_hdr->ucode_start_addr_hi << 30); 2466 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2467 mec_hdr->ucode_start_addr_hi >> 2); 2468 } 2469 soc21_grbm_select(adev, 0, 0, 0, 0); 2470 2471 /* reset mec pipe */ 2472 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2473 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2474 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2475 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2476 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2477 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2478 2479 /* clear mec pipe reset */ 2480 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2481 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2482 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2483 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2484 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2485 } 2486 2487 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2488 { 2489 uint32_t cp_status; 2490 uint32_t bootload_status; 2491 int i, r; 2492 uint64_t addr, addr2; 2493 2494 for (i = 0; i < adev->usec_timeout; i++) { 2495 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2496 2497 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || 2498 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) 2499 bootload_status = RREG32_SOC15(GC, 0, 2500 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2501 else 2502 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2503 2504 if ((cp_status == 0) && 2505 (REG_GET_FIELD(bootload_status, 2506 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2507 break; 2508 } 2509 udelay(1); 2510 } 2511 2512 if (i >= adev->usec_timeout) { 2513 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2514 return -ETIMEDOUT; 2515 } 2516 2517 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2518 if (adev->gfx.rs64_enable) { 2519 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2520 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2521 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2522 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2523 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2524 if (r) 2525 return r; 2526 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2527 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2528 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2529 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2530 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2531 if (r) 2532 return r; 2533 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2534 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2535 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2536 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2537 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2538 if (r) 2539 return r; 2540 } else { 2541 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2542 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2543 r = gfx_v11_0_config_me_cache(adev, addr); 2544 if (r) 2545 return r; 2546 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2547 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2548 r = gfx_v11_0_config_pfp_cache(adev, addr); 2549 if (r) 2550 return r; 2551 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2552 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2553 r = gfx_v11_0_config_mec_cache(adev, addr); 2554 if (r) 2555 return r; 2556 } 2557 } 2558 2559 return 0; 2560 } 2561 2562 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2563 { 2564 int i; 2565 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2566 2567 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2568 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2569 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2570 2571 for (i = 0; i < adev->usec_timeout; i++) { 2572 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2573 break; 2574 udelay(1); 2575 } 2576 2577 if (i >= adev->usec_timeout) 2578 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2579 2580 return 0; 2581 } 2582 2583 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2584 { 2585 int r; 2586 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2587 const __le32 *fw_data; 2588 unsigned i, fw_size; 2589 2590 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2591 adev->gfx.pfp_fw->data; 2592 2593 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2594 2595 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2596 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2597 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2598 2599 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2600 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2601 &adev->gfx.pfp.pfp_fw_obj, 2602 &adev->gfx.pfp.pfp_fw_gpu_addr, 2603 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2604 if (r) { 2605 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2606 gfx_v11_0_pfp_fini(adev); 2607 return r; 2608 } 2609 2610 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2611 2612 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2613 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2614 2615 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2616 2617 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2618 2619 for (i = 0; i < pfp_hdr->jt_size; i++) 2620 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2621 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2622 2623 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2624 2625 return 0; 2626 } 2627 2628 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2629 { 2630 int r; 2631 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2632 const __le32 *fw_ucode, *fw_data; 2633 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2634 uint32_t tmp; 2635 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2636 2637 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2638 adev->gfx.pfp_fw->data; 2639 2640 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2641 2642 /* instruction */ 2643 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2644 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2645 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2646 /* data */ 2647 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2648 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2649 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2650 2651 /* 64kb align */ 2652 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2653 64 * 1024, 2654 AMDGPU_GEM_DOMAIN_VRAM | 2655 AMDGPU_GEM_DOMAIN_GTT, 2656 &adev->gfx.pfp.pfp_fw_obj, 2657 &adev->gfx.pfp.pfp_fw_gpu_addr, 2658 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2659 if (r) { 2660 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2661 gfx_v11_0_pfp_fini(adev); 2662 return r; 2663 } 2664 2665 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2666 64 * 1024, 2667 AMDGPU_GEM_DOMAIN_VRAM | 2668 AMDGPU_GEM_DOMAIN_GTT, 2669 &adev->gfx.pfp.pfp_fw_data_obj, 2670 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2671 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2672 if (r) { 2673 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2674 gfx_v11_0_pfp_fini(adev); 2675 return r; 2676 } 2677 2678 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2679 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2680 2681 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2682 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2683 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2684 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2685 2686 if (amdgpu_emu_mode == 1) 2687 adev->hdp.funcs->flush_hdp(adev, NULL); 2688 2689 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2690 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2691 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2692 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2693 2694 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2695 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2696 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2697 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2698 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2699 2700 /* 2701 * Programming any of the CP_PFP_IC_BASE registers 2702 * forces invalidation of the ME L1 I$. Wait for the 2703 * invalidation complete 2704 */ 2705 for (i = 0; i < usec_timeout; i++) { 2706 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2707 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2708 INVALIDATE_CACHE_COMPLETE)) 2709 break; 2710 udelay(1); 2711 } 2712 2713 if (i >= usec_timeout) { 2714 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2715 return -EINVAL; 2716 } 2717 2718 /* Prime the L1 instruction caches */ 2719 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2720 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2721 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2722 /* Waiting for cache primed*/ 2723 for (i = 0; i < usec_timeout; i++) { 2724 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2725 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2726 ICACHE_PRIMED)) 2727 break; 2728 udelay(1); 2729 } 2730 2731 if (i >= usec_timeout) { 2732 dev_err(adev->dev, "failed to prime instruction cache\n"); 2733 return -EINVAL; 2734 } 2735 2736 mutex_lock(&adev->srbm_mutex); 2737 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2738 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2739 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2740 (pfp_hdr->ucode_start_addr_hi << 30) | 2741 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2742 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2743 pfp_hdr->ucode_start_addr_hi>>2); 2744 2745 /* 2746 * Program CP_ME_CNTL to reset given PIPE to take 2747 * effect of CP_PFP_PRGRM_CNTR_START. 2748 */ 2749 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2750 if (pipe_id == 0) 2751 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2752 PFP_PIPE0_RESET, 1); 2753 else 2754 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2755 PFP_PIPE1_RESET, 1); 2756 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2757 2758 /* Clear pfp pipe0 reset bit. */ 2759 if (pipe_id == 0) 2760 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2761 PFP_PIPE0_RESET, 0); 2762 else 2763 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2764 PFP_PIPE1_RESET, 0); 2765 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2766 2767 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2768 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2769 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2770 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2771 } 2772 soc21_grbm_select(adev, 0, 0, 0, 0); 2773 mutex_unlock(&adev->srbm_mutex); 2774 2775 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2776 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2777 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2778 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2779 2780 /* Invalidate the data caches */ 2781 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2782 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2783 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2784 2785 for (i = 0; i < usec_timeout; i++) { 2786 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2787 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2788 INVALIDATE_DCACHE_COMPLETE)) 2789 break; 2790 udelay(1); 2791 } 2792 2793 if (i >= usec_timeout) { 2794 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2795 return -EINVAL; 2796 } 2797 2798 return 0; 2799 } 2800 2801 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2802 { 2803 int r; 2804 const struct gfx_firmware_header_v1_0 *me_hdr; 2805 const __le32 *fw_data; 2806 unsigned i, fw_size; 2807 2808 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2809 adev->gfx.me_fw->data; 2810 2811 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2812 2813 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2814 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2815 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2816 2817 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2818 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2819 &adev->gfx.me.me_fw_obj, 2820 &adev->gfx.me.me_fw_gpu_addr, 2821 (void **)&adev->gfx.me.me_fw_ptr); 2822 if (r) { 2823 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2824 gfx_v11_0_me_fini(adev); 2825 return r; 2826 } 2827 2828 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2829 2830 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2831 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2832 2833 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2834 2835 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2836 2837 for (i = 0; i < me_hdr->jt_size; i++) 2838 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2839 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2840 2841 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2842 2843 return 0; 2844 } 2845 2846 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2847 { 2848 int r; 2849 const struct gfx_firmware_header_v2_0 *me_hdr; 2850 const __le32 *fw_ucode, *fw_data; 2851 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2852 uint32_t tmp; 2853 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2854 2855 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2856 adev->gfx.me_fw->data; 2857 2858 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2859 2860 /* instruction */ 2861 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2862 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2863 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2864 /* data */ 2865 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2866 le32_to_cpu(me_hdr->data_offset_bytes)); 2867 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2868 2869 /* 64kb align*/ 2870 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2871 64 * 1024, 2872 AMDGPU_GEM_DOMAIN_VRAM | 2873 AMDGPU_GEM_DOMAIN_GTT, 2874 &adev->gfx.me.me_fw_obj, 2875 &adev->gfx.me.me_fw_gpu_addr, 2876 (void **)&adev->gfx.me.me_fw_ptr); 2877 if (r) { 2878 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2879 gfx_v11_0_me_fini(adev); 2880 return r; 2881 } 2882 2883 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2884 64 * 1024, 2885 AMDGPU_GEM_DOMAIN_VRAM | 2886 AMDGPU_GEM_DOMAIN_GTT, 2887 &adev->gfx.me.me_fw_data_obj, 2888 &adev->gfx.me.me_fw_data_gpu_addr, 2889 (void **)&adev->gfx.me.me_fw_data_ptr); 2890 if (r) { 2891 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2892 gfx_v11_0_pfp_fini(adev); 2893 return r; 2894 } 2895 2896 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2897 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2898 2899 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2900 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2901 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2902 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2903 2904 if (amdgpu_emu_mode == 1) 2905 adev->hdp.funcs->flush_hdp(adev, NULL); 2906 2907 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2908 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2909 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2910 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2911 2912 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2913 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2914 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2915 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2916 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2917 2918 /* 2919 * Programming any of the CP_ME_IC_BASE registers 2920 * forces invalidation of the ME L1 I$. Wait for the 2921 * invalidation complete 2922 */ 2923 for (i = 0; i < usec_timeout; i++) { 2924 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2925 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2926 INVALIDATE_CACHE_COMPLETE)) 2927 break; 2928 udelay(1); 2929 } 2930 2931 if (i >= usec_timeout) { 2932 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2933 return -EINVAL; 2934 } 2935 2936 /* Prime the instruction caches */ 2937 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2938 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2939 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2940 2941 /* Waiting for instruction cache primed*/ 2942 for (i = 0; i < usec_timeout; i++) { 2943 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2944 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2945 ICACHE_PRIMED)) 2946 break; 2947 udelay(1); 2948 } 2949 2950 if (i >= usec_timeout) { 2951 dev_err(adev->dev, "failed to prime instruction cache\n"); 2952 return -EINVAL; 2953 } 2954 2955 mutex_lock(&adev->srbm_mutex); 2956 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2957 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2958 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2959 (me_hdr->ucode_start_addr_hi << 30) | 2960 (me_hdr->ucode_start_addr_lo >> 2) ); 2961 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2962 me_hdr->ucode_start_addr_hi>>2); 2963 2964 /* 2965 * Program CP_ME_CNTL to reset given PIPE to take 2966 * effect of CP_PFP_PRGRM_CNTR_START. 2967 */ 2968 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2969 if (pipe_id == 0) 2970 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2971 ME_PIPE0_RESET, 1); 2972 else 2973 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2974 ME_PIPE1_RESET, 1); 2975 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2976 2977 /* Clear pfp pipe0 reset bit. */ 2978 if (pipe_id == 0) 2979 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2980 ME_PIPE0_RESET, 0); 2981 else 2982 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2983 ME_PIPE1_RESET, 0); 2984 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2985 2986 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2987 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2988 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2989 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2990 } 2991 soc21_grbm_select(adev, 0, 0, 0, 0); 2992 mutex_unlock(&adev->srbm_mutex); 2993 2994 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2995 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2996 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2997 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2998 2999 /* Invalidate the data caches */ 3000 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3001 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3002 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3003 3004 for (i = 0; i < usec_timeout; i++) { 3005 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3006 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3007 INVALIDATE_DCACHE_COMPLETE)) 3008 break; 3009 udelay(1); 3010 } 3011 3012 if (i >= usec_timeout) { 3013 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3014 return -EINVAL; 3015 } 3016 3017 return 0; 3018 } 3019 3020 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3021 { 3022 int r; 3023 3024 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3025 return -EINVAL; 3026 3027 gfx_v11_0_cp_gfx_enable(adev, false); 3028 3029 if (adev->gfx.rs64_enable) 3030 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3031 else 3032 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3033 if (r) { 3034 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3035 return r; 3036 } 3037 3038 if (adev->gfx.rs64_enable) 3039 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3040 else 3041 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3042 if (r) { 3043 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3044 return r; 3045 } 3046 3047 return 0; 3048 } 3049 3050 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3051 { 3052 struct amdgpu_ring *ring; 3053 const struct cs_section_def *sect = NULL; 3054 const struct cs_extent_def *ext = NULL; 3055 int r, i; 3056 int ctx_reg_offset; 3057 3058 /* init the CP */ 3059 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3060 adev->gfx.config.max_hw_contexts - 1); 3061 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3062 3063 if (!amdgpu_async_gfx_ring) 3064 gfx_v11_0_cp_gfx_enable(adev, true); 3065 3066 ring = &adev->gfx.gfx_ring[0]; 3067 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3068 if (r) { 3069 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3070 return r; 3071 } 3072 3073 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3074 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3075 3076 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3077 amdgpu_ring_write(ring, 0x80000000); 3078 amdgpu_ring_write(ring, 0x80000000); 3079 3080 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3081 for (ext = sect->section; ext->extent != NULL; ++ext) { 3082 if (sect->id == SECT_CONTEXT) { 3083 amdgpu_ring_write(ring, 3084 PACKET3(PACKET3_SET_CONTEXT_REG, 3085 ext->reg_count)); 3086 amdgpu_ring_write(ring, ext->reg_index - 3087 PACKET3_SET_CONTEXT_REG_START); 3088 for (i = 0; i < ext->reg_count; i++) 3089 amdgpu_ring_write(ring, ext->extent[i]); 3090 } 3091 } 3092 } 3093 3094 ctx_reg_offset = 3095 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3096 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3097 amdgpu_ring_write(ring, ctx_reg_offset); 3098 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3099 3100 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3101 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3102 3103 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3104 amdgpu_ring_write(ring, 0); 3105 3106 amdgpu_ring_commit(ring); 3107 3108 /* submit cs packet to copy state 0 to next available state */ 3109 if (adev->gfx.num_gfx_rings > 1) { 3110 /* maximum supported gfx ring is 2 */ 3111 ring = &adev->gfx.gfx_ring[1]; 3112 r = amdgpu_ring_alloc(ring, 2); 3113 if (r) { 3114 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3115 return r; 3116 } 3117 3118 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3119 amdgpu_ring_write(ring, 0); 3120 3121 amdgpu_ring_commit(ring); 3122 } 3123 return 0; 3124 } 3125 3126 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3127 CP_PIPE_ID pipe) 3128 { 3129 u32 tmp; 3130 3131 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3132 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3133 3134 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3135 } 3136 3137 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3138 struct amdgpu_ring *ring) 3139 { 3140 u32 tmp; 3141 3142 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3143 if (ring->use_doorbell) { 3144 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3145 DOORBELL_OFFSET, ring->doorbell_index); 3146 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3147 DOORBELL_EN, 1); 3148 } else { 3149 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3150 DOORBELL_EN, 0); 3151 } 3152 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3153 3154 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3155 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3156 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3157 3158 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3159 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3160 } 3161 3162 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3163 { 3164 struct amdgpu_ring *ring; 3165 u32 tmp; 3166 u32 rb_bufsz; 3167 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3168 u32 i; 3169 3170 /* Set the write pointer delay */ 3171 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3172 3173 /* set the RB to use vmid 0 */ 3174 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3175 3176 /* Init gfx ring 0 for pipe 0 */ 3177 mutex_lock(&adev->srbm_mutex); 3178 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3179 3180 /* Set ring buffer size */ 3181 ring = &adev->gfx.gfx_ring[0]; 3182 rb_bufsz = order_base_2(ring->ring_size / 8); 3183 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3184 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3185 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3186 3187 /* Initialize the ring buffer's write pointers */ 3188 ring->wptr = 0; 3189 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3190 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3191 3192 /* set the wb address wether it's enabled or not */ 3193 rptr_addr = ring->rptr_gpu_addr; 3194 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3195 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3196 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3197 3198 wptr_gpu_addr = ring->wptr_gpu_addr; 3199 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3200 lower_32_bits(wptr_gpu_addr)); 3201 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3202 upper_32_bits(wptr_gpu_addr)); 3203 3204 mdelay(1); 3205 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3206 3207 rb_addr = ring->gpu_addr >> 8; 3208 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3209 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3210 3211 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3212 3213 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3214 mutex_unlock(&adev->srbm_mutex); 3215 3216 /* Init gfx ring 1 for pipe 1 */ 3217 if (adev->gfx.num_gfx_rings > 1) { 3218 mutex_lock(&adev->srbm_mutex); 3219 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3220 /* maximum supported gfx ring is 2 */ 3221 ring = &adev->gfx.gfx_ring[1]; 3222 rb_bufsz = order_base_2(ring->ring_size / 8); 3223 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3224 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3225 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3226 /* Initialize the ring buffer's write pointers */ 3227 ring->wptr = 0; 3228 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3229 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3230 /* Set the wb address wether it's enabled or not */ 3231 rptr_addr = ring->rptr_gpu_addr; 3232 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3233 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3234 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3235 wptr_gpu_addr = ring->wptr_gpu_addr; 3236 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3237 lower_32_bits(wptr_gpu_addr)); 3238 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3239 upper_32_bits(wptr_gpu_addr)); 3240 3241 mdelay(1); 3242 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3243 3244 rb_addr = ring->gpu_addr >> 8; 3245 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3246 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3247 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3248 3249 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3250 mutex_unlock(&adev->srbm_mutex); 3251 } 3252 /* Switch to pipe 0 */ 3253 mutex_lock(&adev->srbm_mutex); 3254 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3255 mutex_unlock(&adev->srbm_mutex); 3256 3257 /* start the ring */ 3258 gfx_v11_0_cp_gfx_start(adev); 3259 3260 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3261 ring = &adev->gfx.gfx_ring[i]; 3262 ring->sched.ready = true; 3263 } 3264 3265 return 0; 3266 } 3267 3268 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3269 { 3270 u32 data; 3271 3272 if (adev->gfx.rs64_enable) { 3273 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3274 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3275 enable ? 0 : 1); 3276 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3277 enable ? 0 : 1); 3278 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3279 enable ? 0 : 1); 3280 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3281 enable ? 0 : 1); 3282 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3283 enable ? 0 : 1); 3284 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3285 enable ? 1 : 0); 3286 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3287 enable ? 1 : 0); 3288 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3289 enable ? 1 : 0); 3290 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3291 enable ? 1 : 0); 3292 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3293 enable ? 0 : 1); 3294 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3295 } else { 3296 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3297 3298 if (enable) { 3299 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3300 if (!adev->enable_mes_kiq) 3301 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3302 MEC_ME2_HALT, 0); 3303 } else { 3304 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3305 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3306 } 3307 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3308 } 3309 3310 adev->gfx.kiq.ring.sched.ready = enable; 3311 3312 udelay(50); 3313 } 3314 3315 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3316 { 3317 const struct gfx_firmware_header_v1_0 *mec_hdr; 3318 const __le32 *fw_data; 3319 unsigned i, fw_size; 3320 u32 *fw = NULL; 3321 int r; 3322 3323 if (!adev->gfx.mec_fw) 3324 return -EINVAL; 3325 3326 gfx_v11_0_cp_compute_enable(adev, false); 3327 3328 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3329 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3330 3331 fw_data = (const __le32 *) 3332 (adev->gfx.mec_fw->data + 3333 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3334 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3335 3336 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3337 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3338 &adev->gfx.mec.mec_fw_obj, 3339 &adev->gfx.mec.mec_fw_gpu_addr, 3340 (void **)&fw); 3341 if (r) { 3342 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3343 gfx_v11_0_mec_fini(adev); 3344 return r; 3345 } 3346 3347 memcpy(fw, fw_data, fw_size); 3348 3349 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3350 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3351 3352 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3353 3354 /* MEC1 */ 3355 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3356 3357 for (i = 0; i < mec_hdr->jt_size; i++) 3358 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3359 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3360 3361 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3362 3363 return 0; 3364 } 3365 3366 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3367 { 3368 const struct gfx_firmware_header_v2_0 *mec_hdr; 3369 const __le32 *fw_ucode, *fw_data; 3370 u32 tmp, fw_ucode_size, fw_data_size; 3371 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3372 u32 *fw_ucode_ptr, *fw_data_ptr; 3373 int r; 3374 3375 if (!adev->gfx.mec_fw) 3376 return -EINVAL; 3377 3378 gfx_v11_0_cp_compute_enable(adev, false); 3379 3380 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3381 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3382 3383 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3384 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3385 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3386 3387 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3388 le32_to_cpu(mec_hdr->data_offset_bytes)); 3389 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3390 3391 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3392 64 * 1024, 3393 AMDGPU_GEM_DOMAIN_VRAM | 3394 AMDGPU_GEM_DOMAIN_GTT, 3395 &adev->gfx.mec.mec_fw_obj, 3396 &adev->gfx.mec.mec_fw_gpu_addr, 3397 (void **)&fw_ucode_ptr); 3398 if (r) { 3399 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3400 gfx_v11_0_mec_fini(adev); 3401 return r; 3402 } 3403 3404 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3405 64 * 1024, 3406 AMDGPU_GEM_DOMAIN_VRAM | 3407 AMDGPU_GEM_DOMAIN_GTT, 3408 &adev->gfx.mec.mec_fw_data_obj, 3409 &adev->gfx.mec.mec_fw_data_gpu_addr, 3410 (void **)&fw_data_ptr); 3411 if (r) { 3412 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3413 gfx_v11_0_mec_fini(adev); 3414 return r; 3415 } 3416 3417 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3418 memcpy(fw_data_ptr, fw_data, fw_data_size); 3419 3420 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3421 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3422 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3423 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3424 3425 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3426 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3427 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3428 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3429 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3430 3431 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3432 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3433 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3434 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3435 3436 mutex_lock(&adev->srbm_mutex); 3437 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3438 soc21_grbm_select(adev, 1, i, 0, 0); 3439 3440 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3441 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3442 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3443 3444 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3445 mec_hdr->ucode_start_addr_lo >> 2 | 3446 mec_hdr->ucode_start_addr_hi << 30); 3447 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3448 mec_hdr->ucode_start_addr_hi >> 2); 3449 3450 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3451 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3452 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3453 } 3454 mutex_unlock(&adev->srbm_mutex); 3455 soc21_grbm_select(adev, 0, 0, 0, 0); 3456 3457 /* Trigger an invalidation of the L1 instruction caches */ 3458 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3459 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3460 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3461 3462 /* Wait for invalidation complete */ 3463 for (i = 0; i < usec_timeout; i++) { 3464 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3465 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3466 INVALIDATE_DCACHE_COMPLETE)) 3467 break; 3468 udelay(1); 3469 } 3470 3471 if (i >= usec_timeout) { 3472 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3473 return -EINVAL; 3474 } 3475 3476 /* Trigger an invalidation of the L1 instruction caches */ 3477 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3478 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3479 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3480 3481 /* Wait for invalidation complete */ 3482 for (i = 0; i < usec_timeout; i++) { 3483 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3484 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3485 INVALIDATE_CACHE_COMPLETE)) 3486 break; 3487 udelay(1); 3488 } 3489 3490 if (i >= usec_timeout) { 3491 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3492 return -EINVAL; 3493 } 3494 3495 return 0; 3496 } 3497 3498 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3499 { 3500 uint32_t tmp; 3501 struct amdgpu_device *adev = ring->adev; 3502 3503 /* tell RLC which is KIQ queue */ 3504 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3505 tmp &= 0xffffff00; 3506 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3507 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3508 tmp |= 0x80; 3509 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3510 } 3511 3512 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3513 { 3514 /* set graphics engine doorbell range */ 3515 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3516 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3517 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3518 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3519 3520 /* set compute engine doorbell range */ 3521 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3522 (adev->doorbell_index.kiq * 2) << 2); 3523 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3524 (adev->doorbell_index.userqueue_end * 2) << 2); 3525 } 3526 3527 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3528 struct amdgpu_mqd_prop *prop) 3529 { 3530 struct v11_gfx_mqd *mqd = m; 3531 uint64_t hqd_gpu_addr, wb_gpu_addr; 3532 uint32_t tmp; 3533 uint32_t rb_bufsz; 3534 3535 /* set up gfx hqd wptr */ 3536 mqd->cp_gfx_hqd_wptr = 0; 3537 mqd->cp_gfx_hqd_wptr_hi = 0; 3538 3539 /* set the pointer to the MQD */ 3540 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3541 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3542 3543 /* set up mqd control */ 3544 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3545 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3546 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3547 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3548 mqd->cp_gfx_mqd_control = tmp; 3549 3550 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3551 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3552 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3553 mqd->cp_gfx_hqd_vmid = 0; 3554 3555 /* set up default queue priority level 3556 * 0x0 = low priority, 0x1 = high priority */ 3557 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3558 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3559 mqd->cp_gfx_hqd_queue_priority = tmp; 3560 3561 /* set up time quantum */ 3562 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3563 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3564 mqd->cp_gfx_hqd_quantum = tmp; 3565 3566 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3567 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3568 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3569 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3570 3571 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3572 wb_gpu_addr = prop->rptr_gpu_addr; 3573 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3574 mqd->cp_gfx_hqd_rptr_addr_hi = 3575 upper_32_bits(wb_gpu_addr) & 0xffff; 3576 3577 /* set up rb_wptr_poll addr */ 3578 wb_gpu_addr = prop->wptr_gpu_addr; 3579 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3580 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3581 3582 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3583 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3584 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3585 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3586 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3587 #ifdef __BIG_ENDIAN 3588 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3589 #endif 3590 mqd->cp_gfx_hqd_cntl = tmp; 3591 3592 /* set up cp_doorbell_control */ 3593 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3594 if (prop->use_doorbell) { 3595 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3596 DOORBELL_OFFSET, prop->doorbell_index); 3597 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3598 DOORBELL_EN, 1); 3599 } else 3600 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3601 DOORBELL_EN, 0); 3602 mqd->cp_rb_doorbell_control = tmp; 3603 3604 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3605 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3606 3607 /* active the queue */ 3608 mqd->cp_gfx_hqd_active = 1; 3609 3610 return 0; 3611 } 3612 3613 #ifdef BRING_UP_DEBUG 3614 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3615 { 3616 struct amdgpu_device *adev = ring->adev; 3617 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3618 3619 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3620 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3621 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3622 3623 /* set GFX_MQD_BASE */ 3624 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3625 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3626 3627 /* set GFX_MQD_CONTROL */ 3628 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3629 3630 /* set GFX_HQD_VMID to 0 */ 3631 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3632 3633 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3634 mqd->cp_gfx_hqd_queue_priority); 3635 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3636 3637 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3638 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3639 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3640 3641 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3642 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3643 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3644 3645 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3646 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3647 3648 /* set RB_WPTR_POLL_ADDR */ 3649 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3650 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3651 3652 /* set RB_DOORBELL_CONTROL */ 3653 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3654 3655 /* active the queue */ 3656 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3657 3658 return 0; 3659 } 3660 #endif 3661 3662 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3663 { 3664 struct amdgpu_device *adev = ring->adev; 3665 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3666 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3667 3668 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3669 memset((void *)mqd, 0, sizeof(*mqd)); 3670 mutex_lock(&adev->srbm_mutex); 3671 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3672 amdgpu_ring_init_mqd(ring); 3673 #ifdef BRING_UP_DEBUG 3674 gfx_v11_0_gfx_queue_init_register(ring); 3675 #endif 3676 soc21_grbm_select(adev, 0, 0, 0, 0); 3677 mutex_unlock(&adev->srbm_mutex); 3678 if (adev->gfx.me.mqd_backup[mqd_idx]) 3679 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3680 } else if (amdgpu_in_reset(adev)) { 3681 /* reset mqd with the backup copy */ 3682 if (adev->gfx.me.mqd_backup[mqd_idx]) 3683 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3684 /* reset the ring */ 3685 ring->wptr = 0; 3686 *ring->wptr_cpu_addr = 0; 3687 amdgpu_ring_clear_ring(ring); 3688 #ifdef BRING_UP_DEBUG 3689 mutex_lock(&adev->srbm_mutex); 3690 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3691 gfx_v11_0_gfx_queue_init_register(ring); 3692 soc21_grbm_select(adev, 0, 0, 0, 0); 3693 mutex_unlock(&adev->srbm_mutex); 3694 #endif 3695 } else { 3696 amdgpu_ring_clear_ring(ring); 3697 } 3698 3699 return 0; 3700 } 3701 3702 #ifndef BRING_UP_DEBUG 3703 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3704 { 3705 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3706 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3707 int r, i; 3708 3709 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3710 return -EINVAL; 3711 3712 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3713 adev->gfx.num_gfx_rings); 3714 if (r) { 3715 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3716 return r; 3717 } 3718 3719 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3720 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3721 3722 return amdgpu_ring_test_helper(kiq_ring); 3723 } 3724 #endif 3725 3726 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3727 { 3728 int r, i; 3729 struct amdgpu_ring *ring; 3730 3731 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3732 ring = &adev->gfx.gfx_ring[i]; 3733 3734 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3735 if (unlikely(r != 0)) 3736 goto done; 3737 3738 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3739 if (!r) { 3740 r = gfx_v11_0_gfx_init_queue(ring); 3741 amdgpu_bo_kunmap(ring->mqd_obj); 3742 ring->mqd_ptr = NULL; 3743 } 3744 amdgpu_bo_unreserve(ring->mqd_obj); 3745 if (r) 3746 goto done; 3747 } 3748 #ifndef BRING_UP_DEBUG 3749 r = gfx_v11_0_kiq_enable_kgq(adev); 3750 if (r) 3751 goto done; 3752 #endif 3753 r = gfx_v11_0_cp_gfx_start(adev); 3754 if (r) 3755 goto done; 3756 3757 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3758 ring = &adev->gfx.gfx_ring[i]; 3759 ring->sched.ready = true; 3760 } 3761 done: 3762 return r; 3763 } 3764 3765 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3766 struct amdgpu_mqd_prop *prop) 3767 { 3768 struct v11_compute_mqd *mqd = m; 3769 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3770 uint32_t tmp; 3771 3772 mqd->header = 0xC0310800; 3773 mqd->compute_pipelinestat_enable = 0x00000001; 3774 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3775 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3776 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3777 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3778 mqd->compute_misc_reserved = 0x00000007; 3779 3780 eop_base_addr = prop->eop_gpu_addr >> 8; 3781 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3782 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3783 3784 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3785 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3786 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3787 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3788 3789 mqd->cp_hqd_eop_control = tmp; 3790 3791 /* enable doorbell? */ 3792 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3793 3794 if (prop->use_doorbell) { 3795 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3796 DOORBELL_OFFSET, prop->doorbell_index); 3797 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3798 DOORBELL_EN, 1); 3799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3800 DOORBELL_SOURCE, 0); 3801 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3802 DOORBELL_HIT, 0); 3803 } else { 3804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3805 DOORBELL_EN, 0); 3806 } 3807 3808 mqd->cp_hqd_pq_doorbell_control = tmp; 3809 3810 /* disable the queue if it's active */ 3811 mqd->cp_hqd_dequeue_request = 0; 3812 mqd->cp_hqd_pq_rptr = 0; 3813 mqd->cp_hqd_pq_wptr_lo = 0; 3814 mqd->cp_hqd_pq_wptr_hi = 0; 3815 3816 /* set the pointer to the MQD */ 3817 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3818 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3819 3820 /* set MQD vmid to 0 */ 3821 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3822 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3823 mqd->cp_mqd_control = tmp; 3824 3825 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3826 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3827 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3828 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3829 3830 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3831 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3833 (order_base_2(prop->queue_size / 4) - 1)); 3834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3835 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3836 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3839 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3840 mqd->cp_hqd_pq_control = tmp; 3841 3842 /* set the wb address whether it's enabled or not */ 3843 wb_gpu_addr = prop->rptr_gpu_addr; 3844 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3845 mqd->cp_hqd_pq_rptr_report_addr_hi = 3846 upper_32_bits(wb_gpu_addr) & 0xffff; 3847 3848 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3849 wb_gpu_addr = prop->wptr_gpu_addr; 3850 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3851 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3852 3853 tmp = 0; 3854 /* enable the doorbell if requested */ 3855 if (prop->use_doorbell) { 3856 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3857 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3858 DOORBELL_OFFSET, prop->doorbell_index); 3859 3860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3861 DOORBELL_EN, 1); 3862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3863 DOORBELL_SOURCE, 0); 3864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3865 DOORBELL_HIT, 0); 3866 } 3867 3868 mqd->cp_hqd_pq_doorbell_control = tmp; 3869 3870 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3871 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3872 3873 /* set the vmid for the queue */ 3874 mqd->cp_hqd_vmid = 0; 3875 3876 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3877 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3878 mqd->cp_hqd_persistent_state = tmp; 3879 3880 /* set MIN_IB_AVAIL_SIZE */ 3881 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3882 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3883 mqd->cp_hqd_ib_control = tmp; 3884 3885 /* set static priority for a compute queue/ring */ 3886 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3887 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3888 3889 mqd->cp_hqd_active = prop->hqd_active; 3890 3891 return 0; 3892 } 3893 3894 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3895 { 3896 struct amdgpu_device *adev = ring->adev; 3897 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3898 int j; 3899 3900 /* inactivate the queue */ 3901 if (amdgpu_sriov_vf(adev)) 3902 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3903 3904 /* disable wptr polling */ 3905 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3906 3907 /* write the EOP addr */ 3908 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3909 mqd->cp_hqd_eop_base_addr_lo); 3910 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3911 mqd->cp_hqd_eop_base_addr_hi); 3912 3913 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3914 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3915 mqd->cp_hqd_eop_control); 3916 3917 /* enable doorbell? */ 3918 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3919 mqd->cp_hqd_pq_doorbell_control); 3920 3921 /* disable the queue if it's active */ 3922 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3923 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3924 for (j = 0; j < adev->usec_timeout; j++) { 3925 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3926 break; 3927 udelay(1); 3928 } 3929 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3930 mqd->cp_hqd_dequeue_request); 3931 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3932 mqd->cp_hqd_pq_rptr); 3933 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3934 mqd->cp_hqd_pq_wptr_lo); 3935 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3936 mqd->cp_hqd_pq_wptr_hi); 3937 } 3938 3939 /* set the pointer to the MQD */ 3940 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3941 mqd->cp_mqd_base_addr_lo); 3942 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3943 mqd->cp_mqd_base_addr_hi); 3944 3945 /* set MQD vmid to 0 */ 3946 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3947 mqd->cp_mqd_control); 3948 3949 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3950 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3951 mqd->cp_hqd_pq_base_lo); 3952 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3953 mqd->cp_hqd_pq_base_hi); 3954 3955 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3956 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3957 mqd->cp_hqd_pq_control); 3958 3959 /* set the wb address whether it's enabled or not */ 3960 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3961 mqd->cp_hqd_pq_rptr_report_addr_lo); 3962 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3963 mqd->cp_hqd_pq_rptr_report_addr_hi); 3964 3965 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3966 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3967 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3968 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3969 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3970 3971 /* enable the doorbell if requested */ 3972 if (ring->use_doorbell) { 3973 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3974 (adev->doorbell_index.kiq * 2) << 2); 3975 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3976 (adev->doorbell_index.userqueue_end * 2) << 2); 3977 } 3978 3979 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3980 mqd->cp_hqd_pq_doorbell_control); 3981 3982 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3983 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3984 mqd->cp_hqd_pq_wptr_lo); 3985 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3986 mqd->cp_hqd_pq_wptr_hi); 3987 3988 /* set the vmid for the queue */ 3989 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3990 3991 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3992 mqd->cp_hqd_persistent_state); 3993 3994 /* activate the queue */ 3995 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3996 mqd->cp_hqd_active); 3997 3998 if (ring->use_doorbell) 3999 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4000 4001 return 0; 4002 } 4003 4004 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4005 { 4006 struct amdgpu_device *adev = ring->adev; 4007 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4008 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4009 4010 gfx_v11_0_kiq_setting(ring); 4011 4012 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4013 /* reset MQD to a clean status */ 4014 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4015 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4016 4017 /* reset ring buffer */ 4018 ring->wptr = 0; 4019 amdgpu_ring_clear_ring(ring); 4020 4021 mutex_lock(&adev->srbm_mutex); 4022 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4023 gfx_v11_0_kiq_init_register(ring); 4024 soc21_grbm_select(adev, 0, 0, 0, 0); 4025 mutex_unlock(&adev->srbm_mutex); 4026 } else { 4027 memset((void *)mqd, 0, sizeof(*mqd)); 4028 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4029 amdgpu_ring_clear_ring(ring); 4030 mutex_lock(&adev->srbm_mutex); 4031 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4032 amdgpu_ring_init_mqd(ring); 4033 gfx_v11_0_kiq_init_register(ring); 4034 soc21_grbm_select(adev, 0, 0, 0, 0); 4035 mutex_unlock(&adev->srbm_mutex); 4036 4037 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4038 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4039 } 4040 4041 return 0; 4042 } 4043 4044 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4045 { 4046 struct amdgpu_device *adev = ring->adev; 4047 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4048 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4049 4050 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4051 memset((void *)mqd, 0, sizeof(*mqd)); 4052 mutex_lock(&adev->srbm_mutex); 4053 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4054 amdgpu_ring_init_mqd(ring); 4055 soc21_grbm_select(adev, 0, 0, 0, 0); 4056 mutex_unlock(&adev->srbm_mutex); 4057 4058 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4059 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4060 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4061 /* reset MQD to a clean status */ 4062 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4063 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4064 4065 /* reset ring buffer */ 4066 ring->wptr = 0; 4067 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4068 amdgpu_ring_clear_ring(ring); 4069 } else { 4070 amdgpu_ring_clear_ring(ring); 4071 } 4072 4073 return 0; 4074 } 4075 4076 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4077 { 4078 struct amdgpu_ring *ring; 4079 int r; 4080 4081 ring = &adev->gfx.kiq.ring; 4082 4083 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4084 if (unlikely(r != 0)) 4085 return r; 4086 4087 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4088 if (unlikely(r != 0)) { 4089 amdgpu_bo_unreserve(ring->mqd_obj); 4090 return r; 4091 } 4092 4093 gfx_v11_0_kiq_init_queue(ring); 4094 amdgpu_bo_kunmap(ring->mqd_obj); 4095 ring->mqd_ptr = NULL; 4096 amdgpu_bo_unreserve(ring->mqd_obj); 4097 ring->sched.ready = true; 4098 return 0; 4099 } 4100 4101 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4102 { 4103 struct amdgpu_ring *ring = NULL; 4104 int r = 0, i; 4105 4106 if (!amdgpu_async_gfx_ring) 4107 gfx_v11_0_cp_compute_enable(adev, true); 4108 4109 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4110 ring = &adev->gfx.compute_ring[i]; 4111 4112 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4113 if (unlikely(r != 0)) 4114 goto done; 4115 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4116 if (!r) { 4117 r = gfx_v11_0_kcq_init_queue(ring); 4118 amdgpu_bo_kunmap(ring->mqd_obj); 4119 ring->mqd_ptr = NULL; 4120 } 4121 amdgpu_bo_unreserve(ring->mqd_obj); 4122 if (r) 4123 goto done; 4124 } 4125 4126 r = amdgpu_gfx_enable_kcq(adev); 4127 done: 4128 return r; 4129 } 4130 4131 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4132 { 4133 int r, i; 4134 struct amdgpu_ring *ring; 4135 4136 if (!(adev->flags & AMD_IS_APU)) 4137 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4138 4139 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4140 /* legacy firmware loading */ 4141 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4142 if (r) 4143 return r; 4144 4145 if (adev->gfx.rs64_enable) 4146 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4147 else 4148 r = gfx_v11_0_cp_compute_load_microcode(adev); 4149 if (r) 4150 return r; 4151 } 4152 4153 gfx_v11_0_cp_set_doorbell_range(adev); 4154 4155 if (amdgpu_async_gfx_ring) { 4156 gfx_v11_0_cp_compute_enable(adev, true); 4157 gfx_v11_0_cp_gfx_enable(adev, true); 4158 } 4159 4160 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4161 r = amdgpu_mes_kiq_hw_init(adev); 4162 else 4163 r = gfx_v11_0_kiq_resume(adev); 4164 if (r) 4165 return r; 4166 4167 r = gfx_v11_0_kcq_resume(adev); 4168 if (r) 4169 return r; 4170 4171 if (!amdgpu_async_gfx_ring) { 4172 r = gfx_v11_0_cp_gfx_resume(adev); 4173 if (r) 4174 return r; 4175 } else { 4176 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4177 if (r) 4178 return r; 4179 } 4180 4181 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4182 ring = &adev->gfx.gfx_ring[i]; 4183 r = amdgpu_ring_test_helper(ring); 4184 if (r) 4185 return r; 4186 } 4187 4188 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4189 ring = &adev->gfx.compute_ring[i]; 4190 r = amdgpu_ring_test_helper(ring); 4191 if (r) 4192 return r; 4193 } 4194 4195 return 0; 4196 } 4197 4198 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4199 { 4200 gfx_v11_0_cp_gfx_enable(adev, enable); 4201 gfx_v11_0_cp_compute_enable(adev, enable); 4202 } 4203 4204 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4205 { 4206 int r; 4207 bool value; 4208 4209 r = adev->gfxhub.funcs->gart_enable(adev); 4210 if (r) 4211 return r; 4212 4213 adev->hdp.funcs->flush_hdp(adev, NULL); 4214 4215 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4216 false : true; 4217 4218 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4219 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4220 4221 return 0; 4222 } 4223 4224 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4225 { 4226 u32 tmp; 4227 4228 /* select RS64 */ 4229 if (adev->gfx.rs64_enable) { 4230 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4231 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4232 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4233 4234 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4235 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4236 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4237 } 4238 4239 if (amdgpu_emu_mode == 1) 4240 msleep(100); 4241 } 4242 4243 static int get_gb_addr_config(struct amdgpu_device * adev) 4244 { 4245 u32 gb_addr_config; 4246 4247 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4248 if (gb_addr_config == 0) 4249 return -EINVAL; 4250 4251 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4252 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4253 4254 adev->gfx.config.gb_addr_config = gb_addr_config; 4255 4256 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4257 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4258 GB_ADDR_CONFIG, NUM_PIPES); 4259 4260 adev->gfx.config.max_tile_pipes = 4261 adev->gfx.config.gb_addr_config_fields.num_pipes; 4262 4263 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4264 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4265 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4266 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4267 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4268 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4269 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4270 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4271 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4272 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4273 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4274 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4275 4276 return 0; 4277 } 4278 4279 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4280 { 4281 uint32_t data; 4282 4283 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4284 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4285 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4286 4287 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4288 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4289 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4290 } 4291 4292 static int gfx_v11_0_hw_init(void *handle) 4293 { 4294 int r; 4295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4296 4297 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4298 if (adev->gfx.imu.funcs) { 4299 /* RLC autoload sequence 1: Program rlc ram */ 4300 if (adev->gfx.imu.funcs->program_rlc_ram) 4301 adev->gfx.imu.funcs->program_rlc_ram(adev); 4302 } 4303 /* rlc autoload firmware */ 4304 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4305 if (r) 4306 return r; 4307 } else { 4308 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4309 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4310 if (adev->gfx.imu.funcs->load_microcode) 4311 adev->gfx.imu.funcs->load_microcode(adev); 4312 if (adev->gfx.imu.funcs->setup_imu) 4313 adev->gfx.imu.funcs->setup_imu(adev); 4314 if (adev->gfx.imu.funcs->start_imu) 4315 adev->gfx.imu.funcs->start_imu(adev); 4316 } 4317 4318 /* disable gpa mode in backdoor loading */ 4319 gfx_v11_0_disable_gpa_mode(adev); 4320 } 4321 } 4322 4323 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4324 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4325 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4326 if (r) { 4327 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4328 return r; 4329 } 4330 } 4331 4332 adev->gfx.is_poweron = true; 4333 4334 if(get_gb_addr_config(adev)) 4335 DRM_WARN("Invalid gb_addr_config !\n"); 4336 4337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4338 adev->gfx.rs64_enable) 4339 gfx_v11_0_config_gfx_rs64(adev); 4340 4341 r = gfx_v11_0_gfxhub_enable(adev); 4342 if (r) 4343 return r; 4344 4345 if (!amdgpu_emu_mode) 4346 gfx_v11_0_init_golden_registers(adev); 4347 4348 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4349 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4350 /** 4351 * For gfx 11, rlc firmware loading relies on smu firmware is 4352 * loaded firstly, so in direct type, it has to load smc ucode 4353 * here before rlc. 4354 */ 4355 if (!(adev->flags & AMD_IS_APU)) { 4356 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4357 if (r) 4358 return r; 4359 } 4360 } 4361 4362 gfx_v11_0_constants_init(adev); 4363 4364 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4365 gfx_v11_0_select_cp_fw_arch(adev); 4366 4367 if (adev->nbio.funcs->gc_doorbell_init) 4368 adev->nbio.funcs->gc_doorbell_init(adev); 4369 4370 r = gfx_v11_0_rlc_resume(adev); 4371 if (r) 4372 return r; 4373 4374 /* 4375 * init golden registers and rlc resume may override some registers, 4376 * reconfig them here 4377 */ 4378 gfx_v11_0_tcp_harvest(adev); 4379 4380 r = gfx_v11_0_cp_resume(adev); 4381 if (r) 4382 return r; 4383 4384 return r; 4385 } 4386 4387 #ifndef BRING_UP_DEBUG 4388 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4389 { 4390 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4391 struct amdgpu_ring *kiq_ring = &kiq->ring; 4392 int i, r = 0; 4393 4394 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4395 return -EINVAL; 4396 4397 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4398 adev->gfx.num_gfx_rings)) 4399 return -ENOMEM; 4400 4401 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4402 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4403 PREEMPT_QUEUES, 0, 0); 4404 4405 if (adev->gfx.kiq.ring.sched.ready) 4406 r = amdgpu_ring_test_helper(kiq_ring); 4407 4408 return r; 4409 } 4410 #endif 4411 4412 static int gfx_v11_0_hw_fini(void *handle) 4413 { 4414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4415 int r; 4416 4417 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4418 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4419 4420 if (!adev->no_hw_access) { 4421 #ifndef BRING_UP_DEBUG 4422 if (amdgpu_async_gfx_ring) { 4423 r = gfx_v11_0_kiq_disable_kgq(adev); 4424 if (r) 4425 DRM_ERROR("KGQ disable failed\n"); 4426 } 4427 #endif 4428 if (amdgpu_gfx_disable_kcq(adev)) 4429 DRM_ERROR("KCQ disable failed\n"); 4430 4431 amdgpu_mes_kiq_hw_fini(adev); 4432 } 4433 4434 if (amdgpu_sriov_vf(adev)) 4435 /* Remove the steps disabling CPG and clearing KIQ position, 4436 * so that CP could perform IDLE-SAVE during switch. Those 4437 * steps are necessary to avoid a DMAR error in gfx9 but it is 4438 * not reproduced on gfx11. 4439 */ 4440 return 0; 4441 4442 gfx_v11_0_cp_enable(adev, false); 4443 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4444 4445 adev->gfxhub.funcs->gart_disable(adev); 4446 4447 adev->gfx.is_poweron = false; 4448 4449 return 0; 4450 } 4451 4452 static int gfx_v11_0_suspend(void *handle) 4453 { 4454 return gfx_v11_0_hw_fini(handle); 4455 } 4456 4457 static int gfx_v11_0_resume(void *handle) 4458 { 4459 return gfx_v11_0_hw_init(handle); 4460 } 4461 4462 static bool gfx_v11_0_is_idle(void *handle) 4463 { 4464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4465 4466 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4467 GRBM_STATUS, GUI_ACTIVE)) 4468 return false; 4469 else 4470 return true; 4471 } 4472 4473 static int gfx_v11_0_wait_for_idle(void *handle) 4474 { 4475 unsigned i; 4476 u32 tmp; 4477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4478 4479 for (i = 0; i < adev->usec_timeout; i++) { 4480 /* read MC_STATUS */ 4481 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4482 GRBM_STATUS__GUI_ACTIVE_MASK; 4483 4484 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4485 return 0; 4486 udelay(1); 4487 } 4488 return -ETIMEDOUT; 4489 } 4490 4491 static int gfx_v11_0_soft_reset(void *handle) 4492 { 4493 u32 grbm_soft_reset = 0; 4494 u32 tmp; 4495 int i, j, k; 4496 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4497 4498 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4499 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4500 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4501 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4502 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4503 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4504 4505 gfx_v11_0_set_safe_mode(adev); 4506 4507 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4508 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4509 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4510 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4511 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4512 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4513 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4514 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4515 4516 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4517 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4518 } 4519 } 4520 } 4521 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4522 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4523 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4524 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4525 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4526 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4527 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4528 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4529 4530 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4531 } 4532 } 4533 } 4534 4535 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4536 4537 // Read CP_VMID_RESET register three times. 4538 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4539 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4540 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4541 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4542 4543 for (i = 0; i < adev->usec_timeout; i++) { 4544 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4545 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4546 break; 4547 udelay(1); 4548 } 4549 if (i >= adev->usec_timeout) { 4550 printk("Failed to wait all pipes clean\n"); 4551 return -EINVAL; 4552 } 4553 4554 /********** trigger soft reset ***********/ 4555 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4556 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4557 SOFT_RESET_CP, 1); 4558 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4559 SOFT_RESET_GFX, 1); 4560 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4561 SOFT_RESET_CPF, 1); 4562 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4563 SOFT_RESET_CPC, 1); 4564 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4565 SOFT_RESET_CPG, 1); 4566 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4567 /********** exit soft reset ***********/ 4568 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4569 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4570 SOFT_RESET_CP, 0); 4571 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4572 SOFT_RESET_GFX, 0); 4573 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4574 SOFT_RESET_CPF, 0); 4575 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4576 SOFT_RESET_CPC, 0); 4577 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4578 SOFT_RESET_CPG, 0); 4579 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4580 4581 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4582 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4583 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4584 4585 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4586 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4587 4588 for (i = 0; i < adev->usec_timeout; i++) { 4589 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4590 break; 4591 udelay(1); 4592 } 4593 if (i >= adev->usec_timeout) { 4594 printk("Failed to wait CP_VMID_RESET to 0\n"); 4595 return -EINVAL; 4596 } 4597 4598 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4599 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4600 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4601 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4602 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4603 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4604 4605 gfx_v11_0_unset_safe_mode(adev); 4606 4607 return gfx_v11_0_cp_resume(adev); 4608 } 4609 4610 static bool gfx_v11_0_check_soft_reset(void *handle) 4611 { 4612 int i, r; 4613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4614 struct amdgpu_ring *ring; 4615 long tmo = msecs_to_jiffies(1000); 4616 4617 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4618 ring = &adev->gfx.gfx_ring[i]; 4619 r = amdgpu_ring_test_ib(ring, tmo); 4620 if (r) 4621 return true; 4622 } 4623 4624 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4625 ring = &adev->gfx.compute_ring[i]; 4626 r = amdgpu_ring_test_ib(ring, tmo); 4627 if (r) 4628 return true; 4629 } 4630 4631 return false; 4632 } 4633 4634 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4635 { 4636 uint64_t clock; 4637 4638 amdgpu_gfx_off_ctrl(adev, false); 4639 mutex_lock(&adev->gfx.gpu_clock_mutex); 4640 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4641 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4642 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4643 amdgpu_gfx_off_ctrl(adev, true); 4644 return clock; 4645 } 4646 4647 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4648 uint32_t vmid, 4649 uint32_t gds_base, uint32_t gds_size, 4650 uint32_t gws_base, uint32_t gws_size, 4651 uint32_t oa_base, uint32_t oa_size) 4652 { 4653 struct amdgpu_device *adev = ring->adev; 4654 4655 /* GDS Base */ 4656 gfx_v11_0_write_data_to_reg(ring, 0, false, 4657 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4658 gds_base); 4659 4660 /* GDS Size */ 4661 gfx_v11_0_write_data_to_reg(ring, 0, false, 4662 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4663 gds_size); 4664 4665 /* GWS */ 4666 gfx_v11_0_write_data_to_reg(ring, 0, false, 4667 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4668 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4669 4670 /* OA */ 4671 gfx_v11_0_write_data_to_reg(ring, 0, false, 4672 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4673 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4674 } 4675 4676 static int gfx_v11_0_early_init(void *handle) 4677 { 4678 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4679 4680 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4681 4682 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4683 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4684 AMDGPU_MAX_COMPUTE_RINGS); 4685 4686 gfx_v11_0_set_kiq_pm4_funcs(adev); 4687 gfx_v11_0_set_ring_funcs(adev); 4688 gfx_v11_0_set_irq_funcs(adev); 4689 gfx_v11_0_set_gds_init(adev); 4690 gfx_v11_0_set_rlc_funcs(adev); 4691 gfx_v11_0_set_mqd_funcs(adev); 4692 gfx_v11_0_set_imu_funcs(adev); 4693 4694 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4695 4696 return 0; 4697 } 4698 4699 static int gfx_v11_0_ras_late_init(void *handle) 4700 { 4701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4702 struct ras_common_if *gfx_common_if; 4703 int ret; 4704 4705 gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL); 4706 if (!gfx_common_if) 4707 return -ENOMEM; 4708 4709 gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX; 4710 4711 ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true); 4712 if (ret) 4713 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n"); 4714 4715 kfree(gfx_common_if); 4716 return 0; 4717 } 4718 4719 static int gfx_v11_0_late_init(void *handle) 4720 { 4721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4722 int r; 4723 4724 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4725 if (r) 4726 return r; 4727 4728 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4729 if (r) 4730 return r; 4731 4732 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { 4733 r = gfx_v11_0_ras_late_init(handle); 4734 if (r) 4735 return r; 4736 } 4737 4738 return 0; 4739 } 4740 4741 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4742 { 4743 uint32_t rlc_cntl; 4744 4745 /* if RLC is not enabled, do nothing */ 4746 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4747 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4748 } 4749 4750 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4751 { 4752 uint32_t data; 4753 unsigned i; 4754 4755 data = RLC_SAFE_MODE__CMD_MASK; 4756 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4757 4758 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4759 4760 /* wait for RLC_SAFE_MODE */ 4761 for (i = 0; i < adev->usec_timeout; i++) { 4762 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4763 RLC_SAFE_MODE, CMD)) 4764 break; 4765 udelay(1); 4766 } 4767 } 4768 4769 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4770 { 4771 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4772 } 4773 4774 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4775 bool enable) 4776 { 4777 uint32_t def, data; 4778 4779 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4780 return; 4781 4782 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4783 4784 if (enable) 4785 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4786 else 4787 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4788 4789 if (def != data) 4790 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4791 } 4792 4793 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4794 bool enable) 4795 { 4796 uint32_t def, data; 4797 4798 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4799 return; 4800 4801 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4802 4803 if (enable) 4804 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4805 else 4806 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4807 4808 if (def != data) 4809 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4810 } 4811 4812 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4813 bool enable) 4814 { 4815 uint32_t def, data; 4816 4817 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4818 return; 4819 4820 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4821 4822 if (enable) 4823 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4824 else 4825 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4826 4827 if (def != data) 4828 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4829 } 4830 4831 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4832 bool enable) 4833 { 4834 uint32_t data, def; 4835 4836 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4837 return; 4838 4839 /* It is disabled by HW by default */ 4840 if (enable) { 4841 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4842 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4843 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4844 4845 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4846 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4847 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4848 4849 if (def != data) 4850 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4851 } 4852 } else { 4853 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4854 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4855 4856 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4857 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4858 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4859 4860 if (def != data) 4861 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4862 } 4863 } 4864 } 4865 4866 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4867 bool enable) 4868 { 4869 uint32_t def, data; 4870 4871 if (!(adev->cg_flags & 4872 (AMD_CG_SUPPORT_GFX_CGCG | 4873 AMD_CG_SUPPORT_GFX_CGLS | 4874 AMD_CG_SUPPORT_GFX_3D_CGCG | 4875 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4876 return; 4877 4878 if (enable) { 4879 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4880 4881 /* unset CGCG override */ 4882 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4883 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4884 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4885 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4886 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4887 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4888 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4889 4890 /* update CGCG override bits */ 4891 if (def != data) 4892 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4893 4894 /* enable cgcg FSM(0x0000363F) */ 4895 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4896 4897 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4898 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4899 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4900 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4901 } 4902 4903 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4904 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4905 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4906 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4907 } 4908 4909 if (def != data) 4910 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4911 4912 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4913 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4914 4915 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4916 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4917 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4918 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4919 } 4920 4921 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4922 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4923 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4924 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4925 } 4926 4927 if (def != data) 4928 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4929 4930 /* set IDLE_POLL_COUNT(0x00900100) */ 4931 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4932 4933 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4934 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4935 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4936 4937 if (def != data) 4938 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4939 4940 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4941 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4942 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4943 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4944 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4945 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4946 4947 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4948 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4949 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4950 4951 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4952 if (adev->sdma.num_instances > 1) { 4953 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4954 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4955 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4956 } 4957 } else { 4958 /* Program RLC_CGCG_CGLS_CTRL */ 4959 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4960 4961 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4962 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4963 4964 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4965 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4966 4967 if (def != data) 4968 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4969 4970 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4971 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4972 4973 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4974 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4975 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4976 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4977 4978 if (def != data) 4979 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4980 4981 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4982 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4983 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4984 4985 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4986 if (adev->sdma.num_instances > 1) { 4987 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4988 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4989 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4990 } 4991 } 4992 } 4993 4994 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4995 bool enable) 4996 { 4997 amdgpu_gfx_rlc_enter_safe_mode(adev); 4998 4999 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5000 5001 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5002 5003 gfx_v11_0_update_repeater_fgcg(adev, enable); 5004 5005 gfx_v11_0_update_sram_fgcg(adev, enable); 5006 5007 gfx_v11_0_update_perf_clk(adev, enable); 5008 5009 if (adev->cg_flags & 5010 (AMD_CG_SUPPORT_GFX_MGCG | 5011 AMD_CG_SUPPORT_GFX_CGLS | 5012 AMD_CG_SUPPORT_GFX_CGCG | 5013 AMD_CG_SUPPORT_GFX_3D_CGCG | 5014 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5015 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5016 5017 amdgpu_gfx_rlc_exit_safe_mode(adev); 5018 5019 return 0; 5020 } 5021 5022 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5023 { 5024 u32 reg, data; 5025 5026 amdgpu_gfx_off_ctrl(adev, false); 5027 5028 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5029 if (amdgpu_sriov_is_pp_one_vf(adev)) 5030 data = RREG32_NO_KIQ(reg); 5031 else 5032 data = RREG32(reg); 5033 5034 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5035 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5036 5037 if (amdgpu_sriov_is_pp_one_vf(adev)) 5038 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5039 else 5040 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5041 5042 amdgpu_gfx_off_ctrl(adev, true); 5043 } 5044 5045 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5046 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5047 .set_safe_mode = gfx_v11_0_set_safe_mode, 5048 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5049 .init = gfx_v11_0_rlc_init, 5050 .get_csb_size = gfx_v11_0_get_csb_size, 5051 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5052 .resume = gfx_v11_0_rlc_resume, 5053 .stop = gfx_v11_0_rlc_stop, 5054 .reset = gfx_v11_0_rlc_reset, 5055 .start = gfx_v11_0_rlc_start, 5056 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5057 }; 5058 5059 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5060 { 5061 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5062 5063 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5064 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5065 else 5066 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5067 5068 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5069 5070 // Program RLC_PG_DELAY3 for CGPG hysteresis 5071 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5072 switch (adev->ip_versions[GC_HWIP][0]) { 5073 case IP_VERSION(11, 0, 1): 5074 case IP_VERSION(11, 0, 4): 5075 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5076 break; 5077 default: 5078 break; 5079 } 5080 } 5081 } 5082 5083 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5084 { 5085 amdgpu_gfx_rlc_enter_safe_mode(adev); 5086 5087 gfx_v11_cntl_power_gating(adev, enable); 5088 5089 amdgpu_gfx_rlc_exit_safe_mode(adev); 5090 } 5091 5092 static int gfx_v11_0_set_powergating_state(void *handle, 5093 enum amd_powergating_state state) 5094 { 5095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5096 bool enable = (state == AMD_PG_STATE_GATE); 5097 5098 if (amdgpu_sriov_vf(adev)) 5099 return 0; 5100 5101 switch (adev->ip_versions[GC_HWIP][0]) { 5102 case IP_VERSION(11, 0, 0): 5103 case IP_VERSION(11, 0, 2): 5104 case IP_VERSION(11, 0, 3): 5105 amdgpu_gfx_off_ctrl(adev, enable); 5106 break; 5107 case IP_VERSION(11, 0, 1): 5108 case IP_VERSION(11, 0, 4): 5109 gfx_v11_cntl_pg(adev, enable); 5110 amdgpu_gfx_off_ctrl(adev, enable); 5111 break; 5112 default: 5113 break; 5114 } 5115 5116 return 0; 5117 } 5118 5119 static int gfx_v11_0_set_clockgating_state(void *handle, 5120 enum amd_clockgating_state state) 5121 { 5122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5123 5124 if (amdgpu_sriov_vf(adev)) 5125 return 0; 5126 5127 switch (adev->ip_versions[GC_HWIP][0]) { 5128 case IP_VERSION(11, 0, 0): 5129 case IP_VERSION(11, 0, 1): 5130 case IP_VERSION(11, 0, 2): 5131 case IP_VERSION(11, 0, 3): 5132 case IP_VERSION(11, 0, 4): 5133 gfx_v11_0_update_gfx_clock_gating(adev, 5134 state == AMD_CG_STATE_GATE); 5135 break; 5136 default: 5137 break; 5138 } 5139 5140 return 0; 5141 } 5142 5143 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5144 { 5145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5146 int data; 5147 5148 /* AMD_CG_SUPPORT_GFX_MGCG */ 5149 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5150 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5151 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5152 5153 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5154 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5155 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5156 5157 /* AMD_CG_SUPPORT_GFX_FGCG */ 5158 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5159 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5160 5161 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5162 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5163 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5164 5165 /* AMD_CG_SUPPORT_GFX_CGCG */ 5166 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5167 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5168 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5169 5170 /* AMD_CG_SUPPORT_GFX_CGLS */ 5171 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5172 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5173 5174 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5175 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5176 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5177 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5178 5179 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5180 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5181 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5182 } 5183 5184 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5185 { 5186 /* gfx11 is 32bit rptr*/ 5187 return *(uint32_t *)ring->rptr_cpu_addr; 5188 } 5189 5190 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5191 { 5192 struct amdgpu_device *adev = ring->adev; 5193 u64 wptr; 5194 5195 /* XXX check if swapping is necessary on BE */ 5196 if (ring->use_doorbell) { 5197 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5198 } else { 5199 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5200 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5201 } 5202 5203 return wptr; 5204 } 5205 5206 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5207 { 5208 struct amdgpu_device *adev = ring->adev; 5209 uint32_t *wptr_saved; 5210 uint32_t *is_queue_unmap; 5211 uint64_t aggregated_db_index; 5212 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5213 uint64_t wptr_tmp; 5214 5215 if (ring->is_mes_queue) { 5216 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5217 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5218 sizeof(uint32_t)); 5219 aggregated_db_index = 5220 amdgpu_mes_get_aggregated_doorbell_index(adev, 5221 ring->hw_prio); 5222 5223 wptr_tmp = ring->wptr & ring->buf_mask; 5224 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5225 *wptr_saved = wptr_tmp; 5226 /* assume doorbell always being used by mes mapped queue */ 5227 if (*is_queue_unmap) { 5228 WDOORBELL64(aggregated_db_index, wptr_tmp); 5229 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5230 } else { 5231 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5232 5233 if (*is_queue_unmap) 5234 WDOORBELL64(aggregated_db_index, wptr_tmp); 5235 } 5236 } else { 5237 if (ring->use_doorbell) { 5238 /* XXX check if swapping is necessary on BE */ 5239 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5240 ring->wptr); 5241 WDOORBELL64(ring->doorbell_index, ring->wptr); 5242 } else { 5243 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5244 lower_32_bits(ring->wptr)); 5245 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5246 upper_32_bits(ring->wptr)); 5247 } 5248 } 5249 } 5250 5251 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5252 { 5253 /* gfx11 hardware is 32bit rptr */ 5254 return *(uint32_t *)ring->rptr_cpu_addr; 5255 } 5256 5257 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5258 { 5259 u64 wptr; 5260 5261 /* XXX check if swapping is necessary on BE */ 5262 if (ring->use_doorbell) 5263 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5264 else 5265 BUG(); 5266 return wptr; 5267 } 5268 5269 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5270 { 5271 struct amdgpu_device *adev = ring->adev; 5272 uint32_t *wptr_saved; 5273 uint32_t *is_queue_unmap; 5274 uint64_t aggregated_db_index; 5275 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5276 uint64_t wptr_tmp; 5277 5278 if (ring->is_mes_queue) { 5279 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5280 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5281 sizeof(uint32_t)); 5282 aggregated_db_index = 5283 amdgpu_mes_get_aggregated_doorbell_index(adev, 5284 ring->hw_prio); 5285 5286 wptr_tmp = ring->wptr & ring->buf_mask; 5287 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5288 *wptr_saved = wptr_tmp; 5289 /* assume doorbell always used by mes mapped queue */ 5290 if (*is_queue_unmap) { 5291 WDOORBELL64(aggregated_db_index, wptr_tmp); 5292 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5293 } else { 5294 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5295 5296 if (*is_queue_unmap) 5297 WDOORBELL64(aggregated_db_index, wptr_tmp); 5298 } 5299 } else { 5300 /* XXX check if swapping is necessary on BE */ 5301 if (ring->use_doorbell) { 5302 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5303 ring->wptr); 5304 WDOORBELL64(ring->doorbell_index, ring->wptr); 5305 } else { 5306 BUG(); /* only DOORBELL method supported on gfx11 now */ 5307 } 5308 } 5309 } 5310 5311 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5312 { 5313 struct amdgpu_device *adev = ring->adev; 5314 u32 ref_and_mask, reg_mem_engine; 5315 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5316 5317 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5318 switch (ring->me) { 5319 case 1: 5320 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5321 break; 5322 case 2: 5323 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5324 break; 5325 default: 5326 return; 5327 } 5328 reg_mem_engine = 0; 5329 } else { 5330 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5331 reg_mem_engine = 1; /* pfp */ 5332 } 5333 5334 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5335 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5336 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5337 ref_and_mask, ref_and_mask, 0x20); 5338 } 5339 5340 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5341 struct amdgpu_job *job, 5342 struct amdgpu_ib *ib, 5343 uint32_t flags) 5344 { 5345 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5346 u32 header, control = 0; 5347 5348 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5349 5350 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5351 5352 control |= ib->length_dw | (vmid << 24); 5353 5354 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5355 control |= INDIRECT_BUFFER_PRE_ENB(1); 5356 5357 if (flags & AMDGPU_IB_PREEMPTED) 5358 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5359 5360 if (vmid) 5361 gfx_v11_0_ring_emit_de_meta(ring, 5362 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5363 } 5364 5365 if (ring->is_mes_queue) 5366 /* inherit vmid from mqd */ 5367 control |= 0x400000; 5368 5369 amdgpu_ring_write(ring, header); 5370 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5371 amdgpu_ring_write(ring, 5372 #ifdef __BIG_ENDIAN 5373 (2 << 0) | 5374 #endif 5375 lower_32_bits(ib->gpu_addr)); 5376 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5377 amdgpu_ring_write(ring, control); 5378 } 5379 5380 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5381 struct amdgpu_job *job, 5382 struct amdgpu_ib *ib, 5383 uint32_t flags) 5384 { 5385 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5386 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5387 5388 if (ring->is_mes_queue) 5389 /* inherit vmid from mqd */ 5390 control |= 0x40000000; 5391 5392 /* Currently, there is a high possibility to get wave ID mismatch 5393 * between ME and GDS, leading to a hw deadlock, because ME generates 5394 * different wave IDs than the GDS expects. This situation happens 5395 * randomly when at least 5 compute pipes use GDS ordered append. 5396 * The wave IDs generated by ME are also wrong after suspend/resume. 5397 * Those are probably bugs somewhere else in the kernel driver. 5398 * 5399 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5400 * GDS to 0 for this ring (me/pipe). 5401 */ 5402 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5403 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5404 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5405 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5406 } 5407 5408 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5409 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5410 amdgpu_ring_write(ring, 5411 #ifdef __BIG_ENDIAN 5412 (2 << 0) | 5413 #endif 5414 lower_32_bits(ib->gpu_addr)); 5415 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5416 amdgpu_ring_write(ring, control); 5417 } 5418 5419 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5420 u64 seq, unsigned flags) 5421 { 5422 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5423 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5424 5425 /* RELEASE_MEM - flush caches, send int */ 5426 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5427 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5428 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5429 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5430 PACKET3_RELEASE_MEM_GCR_GL2_US | 5431 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5432 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5433 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5434 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5435 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5436 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5437 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5438 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5439 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5440 5441 /* 5442 * the address should be Qword aligned if 64bit write, Dword 5443 * aligned if only send 32bit data low (discard data high) 5444 */ 5445 if (write64bit) 5446 BUG_ON(addr & 0x7); 5447 else 5448 BUG_ON(addr & 0x3); 5449 amdgpu_ring_write(ring, lower_32_bits(addr)); 5450 amdgpu_ring_write(ring, upper_32_bits(addr)); 5451 amdgpu_ring_write(ring, lower_32_bits(seq)); 5452 amdgpu_ring_write(ring, upper_32_bits(seq)); 5453 amdgpu_ring_write(ring, ring->is_mes_queue ? 5454 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5455 } 5456 5457 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5458 { 5459 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5460 uint32_t seq = ring->fence_drv.sync_seq; 5461 uint64_t addr = ring->fence_drv.gpu_addr; 5462 5463 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5464 upper_32_bits(addr), seq, 0xffffffff, 4); 5465 } 5466 5467 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5468 uint16_t pasid, uint32_t flush_type, 5469 bool all_hub, uint8_t dst_sel) 5470 { 5471 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5472 amdgpu_ring_write(ring, 5473 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5474 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5475 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5476 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5477 } 5478 5479 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5480 unsigned vmid, uint64_t pd_addr) 5481 { 5482 if (ring->is_mes_queue) 5483 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5484 else 5485 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5486 5487 /* compute doesn't have PFP */ 5488 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5489 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5490 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5491 amdgpu_ring_write(ring, 0x0); 5492 } 5493 } 5494 5495 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5496 u64 seq, unsigned int flags) 5497 { 5498 struct amdgpu_device *adev = ring->adev; 5499 5500 /* we only allocate 32bit for each seq wb address */ 5501 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5502 5503 /* write fence seq to the "addr" */ 5504 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5505 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5506 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5507 amdgpu_ring_write(ring, lower_32_bits(addr)); 5508 amdgpu_ring_write(ring, upper_32_bits(addr)); 5509 amdgpu_ring_write(ring, lower_32_bits(seq)); 5510 5511 if (flags & AMDGPU_FENCE_FLAG_INT) { 5512 /* set register to trigger INT */ 5513 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5514 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5515 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5516 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5517 amdgpu_ring_write(ring, 0); 5518 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5519 } 5520 } 5521 5522 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5523 uint32_t flags) 5524 { 5525 uint32_t dw2 = 0; 5526 5527 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5528 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5529 /* set load_global_config & load_global_uconfig */ 5530 dw2 |= 0x8001; 5531 /* set load_cs_sh_regs */ 5532 dw2 |= 0x01000000; 5533 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5534 dw2 |= 0x10002; 5535 } 5536 5537 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5538 amdgpu_ring_write(ring, dw2); 5539 amdgpu_ring_write(ring, 0); 5540 } 5541 5542 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5543 { 5544 unsigned ret; 5545 5546 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5547 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5548 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5549 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5550 ret = ring->wptr & ring->buf_mask; 5551 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5552 5553 return ret; 5554 } 5555 5556 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5557 { 5558 unsigned cur; 5559 BUG_ON(offset > ring->buf_mask); 5560 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5561 5562 cur = (ring->wptr - 1) & ring->buf_mask; 5563 if (likely(cur > offset)) 5564 ring->ring[offset] = cur - offset; 5565 else 5566 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5567 } 5568 5569 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5570 { 5571 int i, r = 0; 5572 struct amdgpu_device *adev = ring->adev; 5573 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5574 struct amdgpu_ring *kiq_ring = &kiq->ring; 5575 unsigned long flags; 5576 5577 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5578 return -EINVAL; 5579 5580 spin_lock_irqsave(&kiq->ring_lock, flags); 5581 5582 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5583 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5584 return -ENOMEM; 5585 } 5586 5587 /* assert preemption condition */ 5588 amdgpu_ring_set_preempt_cond_exec(ring, false); 5589 5590 /* assert IB preemption, emit the trailing fence */ 5591 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5592 ring->trail_fence_gpu_addr, 5593 ++ring->trail_seq); 5594 amdgpu_ring_commit(kiq_ring); 5595 5596 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5597 5598 /* poll the trailing fence */ 5599 for (i = 0; i < adev->usec_timeout; i++) { 5600 if (ring->trail_seq == 5601 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5602 break; 5603 udelay(1); 5604 } 5605 5606 if (i >= adev->usec_timeout) { 5607 r = -EINVAL; 5608 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5609 } 5610 5611 /* deassert preemption condition */ 5612 amdgpu_ring_set_preempt_cond_exec(ring, true); 5613 return r; 5614 } 5615 5616 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5617 { 5618 struct amdgpu_device *adev = ring->adev; 5619 struct v10_de_ib_state de_payload = {0}; 5620 uint64_t offset, gds_addr, de_payload_gpu_addr; 5621 void *de_payload_cpu_addr; 5622 int cnt; 5623 5624 if (ring->is_mes_queue) { 5625 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5626 gfx[0].gfx_meta_data) + 5627 offsetof(struct v10_gfx_meta_data, de_payload); 5628 de_payload_gpu_addr = 5629 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5630 de_payload_cpu_addr = 5631 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5632 5633 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5634 gfx[0].gds_backup) + 5635 offsetof(struct v10_gfx_meta_data, de_payload); 5636 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5637 } else { 5638 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5639 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5640 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5641 5642 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5643 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5644 PAGE_SIZE); 5645 } 5646 5647 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5648 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5649 5650 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5651 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5652 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5653 WRITE_DATA_DST_SEL(8) | 5654 WR_CONFIRM) | 5655 WRITE_DATA_CACHE_POLICY(0)); 5656 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5657 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5658 5659 if (resume) 5660 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5661 sizeof(de_payload) >> 2); 5662 else 5663 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5664 sizeof(de_payload) >> 2); 5665 } 5666 5667 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5668 bool secure) 5669 { 5670 uint32_t v = secure ? FRAME_TMZ : 0; 5671 5672 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5673 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5674 } 5675 5676 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5677 uint32_t reg_val_offs) 5678 { 5679 struct amdgpu_device *adev = ring->adev; 5680 5681 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5682 amdgpu_ring_write(ring, 0 | /* src: register*/ 5683 (5 << 8) | /* dst: memory */ 5684 (1 << 20)); /* write confirm */ 5685 amdgpu_ring_write(ring, reg); 5686 amdgpu_ring_write(ring, 0); 5687 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5688 reg_val_offs * 4)); 5689 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5690 reg_val_offs * 4)); 5691 } 5692 5693 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5694 uint32_t val) 5695 { 5696 uint32_t cmd = 0; 5697 5698 switch (ring->funcs->type) { 5699 case AMDGPU_RING_TYPE_GFX: 5700 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5701 break; 5702 case AMDGPU_RING_TYPE_KIQ: 5703 cmd = (1 << 16); /* no inc addr */ 5704 break; 5705 default: 5706 cmd = WR_CONFIRM; 5707 break; 5708 } 5709 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5710 amdgpu_ring_write(ring, cmd); 5711 amdgpu_ring_write(ring, reg); 5712 amdgpu_ring_write(ring, 0); 5713 amdgpu_ring_write(ring, val); 5714 } 5715 5716 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5717 uint32_t val, uint32_t mask) 5718 { 5719 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5720 } 5721 5722 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5723 uint32_t reg0, uint32_t reg1, 5724 uint32_t ref, uint32_t mask) 5725 { 5726 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5727 5728 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5729 ref, mask, 0x20); 5730 } 5731 5732 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5733 unsigned vmid) 5734 { 5735 struct amdgpu_device *adev = ring->adev; 5736 uint32_t value = 0; 5737 5738 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5739 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5740 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5741 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5742 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5743 } 5744 5745 static void 5746 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5747 uint32_t me, uint32_t pipe, 5748 enum amdgpu_interrupt_state state) 5749 { 5750 uint32_t cp_int_cntl, cp_int_cntl_reg; 5751 5752 if (!me) { 5753 switch (pipe) { 5754 case 0: 5755 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5756 break; 5757 case 1: 5758 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5759 break; 5760 default: 5761 DRM_DEBUG("invalid pipe %d\n", pipe); 5762 return; 5763 } 5764 } else { 5765 DRM_DEBUG("invalid me %d\n", me); 5766 return; 5767 } 5768 5769 switch (state) { 5770 case AMDGPU_IRQ_STATE_DISABLE: 5771 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5772 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5773 TIME_STAMP_INT_ENABLE, 0); 5774 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5775 GENERIC0_INT_ENABLE, 0); 5776 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5777 break; 5778 case AMDGPU_IRQ_STATE_ENABLE: 5779 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5780 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5781 TIME_STAMP_INT_ENABLE, 1); 5782 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5783 GENERIC0_INT_ENABLE, 1); 5784 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5785 break; 5786 default: 5787 break; 5788 } 5789 } 5790 5791 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5792 int me, int pipe, 5793 enum amdgpu_interrupt_state state) 5794 { 5795 u32 mec_int_cntl, mec_int_cntl_reg; 5796 5797 /* 5798 * amdgpu controls only the first MEC. That's why this function only 5799 * handles the setting of interrupts for this specific MEC. All other 5800 * pipes' interrupts are set by amdkfd. 5801 */ 5802 5803 if (me == 1) { 5804 switch (pipe) { 5805 case 0: 5806 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5807 break; 5808 case 1: 5809 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5810 break; 5811 case 2: 5812 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5813 break; 5814 case 3: 5815 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5816 break; 5817 default: 5818 DRM_DEBUG("invalid pipe %d\n", pipe); 5819 return; 5820 } 5821 } else { 5822 DRM_DEBUG("invalid me %d\n", me); 5823 return; 5824 } 5825 5826 switch (state) { 5827 case AMDGPU_IRQ_STATE_DISABLE: 5828 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5829 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5830 TIME_STAMP_INT_ENABLE, 0); 5831 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5832 GENERIC0_INT_ENABLE, 0); 5833 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5834 break; 5835 case AMDGPU_IRQ_STATE_ENABLE: 5836 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5837 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5838 TIME_STAMP_INT_ENABLE, 1); 5839 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5840 GENERIC0_INT_ENABLE, 1); 5841 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5842 break; 5843 default: 5844 break; 5845 } 5846 } 5847 5848 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5849 struct amdgpu_irq_src *src, 5850 unsigned type, 5851 enum amdgpu_interrupt_state state) 5852 { 5853 switch (type) { 5854 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5855 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5856 break; 5857 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5858 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5859 break; 5860 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5861 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5862 break; 5863 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5864 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5865 break; 5866 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5867 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5868 break; 5869 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5870 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5871 break; 5872 default: 5873 break; 5874 } 5875 return 0; 5876 } 5877 5878 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5879 struct amdgpu_irq_src *source, 5880 struct amdgpu_iv_entry *entry) 5881 { 5882 int i; 5883 u8 me_id, pipe_id, queue_id; 5884 struct amdgpu_ring *ring; 5885 uint32_t mes_queue_id = entry->src_data[0]; 5886 5887 DRM_DEBUG("IH: CP EOP\n"); 5888 5889 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5890 struct amdgpu_mes_queue *queue; 5891 5892 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5893 5894 spin_lock(&adev->mes.queue_id_lock); 5895 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5896 if (queue) { 5897 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5898 amdgpu_fence_process(queue->ring); 5899 } 5900 spin_unlock(&adev->mes.queue_id_lock); 5901 } else { 5902 me_id = (entry->ring_id & 0x0c) >> 2; 5903 pipe_id = (entry->ring_id & 0x03) >> 0; 5904 queue_id = (entry->ring_id & 0x70) >> 4; 5905 5906 switch (me_id) { 5907 case 0: 5908 if (pipe_id == 0) 5909 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5910 else 5911 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5912 break; 5913 case 1: 5914 case 2: 5915 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5916 ring = &adev->gfx.compute_ring[i]; 5917 /* Per-queue interrupt is supported for MEC starting from VI. 5918 * The interrupt can only be enabled/disabled per pipe instead 5919 * of per queue. 5920 */ 5921 if ((ring->me == me_id) && 5922 (ring->pipe == pipe_id) && 5923 (ring->queue == queue_id)) 5924 amdgpu_fence_process(ring); 5925 } 5926 break; 5927 } 5928 } 5929 5930 return 0; 5931 } 5932 5933 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5934 struct amdgpu_irq_src *source, 5935 unsigned type, 5936 enum amdgpu_interrupt_state state) 5937 { 5938 switch (state) { 5939 case AMDGPU_IRQ_STATE_DISABLE: 5940 case AMDGPU_IRQ_STATE_ENABLE: 5941 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5942 PRIV_REG_INT_ENABLE, 5943 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5944 break; 5945 default: 5946 break; 5947 } 5948 5949 return 0; 5950 } 5951 5952 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5953 struct amdgpu_irq_src *source, 5954 unsigned type, 5955 enum amdgpu_interrupt_state state) 5956 { 5957 switch (state) { 5958 case AMDGPU_IRQ_STATE_DISABLE: 5959 case AMDGPU_IRQ_STATE_ENABLE: 5960 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5961 PRIV_INSTR_INT_ENABLE, 5962 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5963 break; 5964 default: 5965 break; 5966 } 5967 5968 return 0; 5969 } 5970 5971 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5972 struct amdgpu_iv_entry *entry) 5973 { 5974 u8 me_id, pipe_id, queue_id; 5975 struct amdgpu_ring *ring; 5976 int i; 5977 5978 me_id = (entry->ring_id & 0x0c) >> 2; 5979 pipe_id = (entry->ring_id & 0x03) >> 0; 5980 queue_id = (entry->ring_id & 0x70) >> 4; 5981 5982 switch (me_id) { 5983 case 0: 5984 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5985 ring = &adev->gfx.gfx_ring[i]; 5986 /* we only enabled 1 gfx queue per pipe for now */ 5987 if (ring->me == me_id && ring->pipe == pipe_id) 5988 drm_sched_fault(&ring->sched); 5989 } 5990 break; 5991 case 1: 5992 case 2: 5993 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5994 ring = &adev->gfx.compute_ring[i]; 5995 if (ring->me == me_id && ring->pipe == pipe_id && 5996 ring->queue == queue_id) 5997 drm_sched_fault(&ring->sched); 5998 } 5999 break; 6000 default: 6001 BUG(); 6002 break; 6003 } 6004 } 6005 6006 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6007 struct amdgpu_irq_src *source, 6008 struct amdgpu_iv_entry *entry) 6009 { 6010 DRM_ERROR("Illegal register access in command stream\n"); 6011 gfx_v11_0_handle_priv_fault(adev, entry); 6012 return 0; 6013 } 6014 6015 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6016 struct amdgpu_irq_src *source, 6017 struct amdgpu_iv_entry *entry) 6018 { 6019 DRM_ERROR("Illegal instruction in command stream\n"); 6020 gfx_v11_0_handle_priv_fault(adev, entry); 6021 return 0; 6022 } 6023 6024 #if 0 6025 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6026 struct amdgpu_irq_src *src, 6027 unsigned int type, 6028 enum amdgpu_interrupt_state state) 6029 { 6030 uint32_t tmp, target; 6031 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6032 6033 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6034 target += ring->pipe; 6035 6036 switch (type) { 6037 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6038 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6039 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6040 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6041 GENERIC2_INT_ENABLE, 0); 6042 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6043 6044 tmp = RREG32_SOC15_IP(GC, target); 6045 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6046 GENERIC2_INT_ENABLE, 0); 6047 WREG32_SOC15_IP(GC, target, tmp); 6048 } else { 6049 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6050 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6051 GENERIC2_INT_ENABLE, 1); 6052 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6053 6054 tmp = RREG32_SOC15_IP(GC, target); 6055 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6056 GENERIC2_INT_ENABLE, 1); 6057 WREG32_SOC15_IP(GC, target, tmp); 6058 } 6059 break; 6060 default: 6061 BUG(); /* kiq only support GENERIC2_INT now */ 6062 break; 6063 } 6064 return 0; 6065 } 6066 #endif 6067 6068 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6069 { 6070 const unsigned int gcr_cntl = 6071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6079 6080 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6081 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6082 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6083 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6084 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6085 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6086 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6087 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6088 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6089 } 6090 6091 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6092 .name = "gfx_v11_0", 6093 .early_init = gfx_v11_0_early_init, 6094 .late_init = gfx_v11_0_late_init, 6095 .sw_init = gfx_v11_0_sw_init, 6096 .sw_fini = gfx_v11_0_sw_fini, 6097 .hw_init = gfx_v11_0_hw_init, 6098 .hw_fini = gfx_v11_0_hw_fini, 6099 .suspend = gfx_v11_0_suspend, 6100 .resume = gfx_v11_0_resume, 6101 .is_idle = gfx_v11_0_is_idle, 6102 .wait_for_idle = gfx_v11_0_wait_for_idle, 6103 .soft_reset = gfx_v11_0_soft_reset, 6104 .check_soft_reset = gfx_v11_0_check_soft_reset, 6105 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6106 .set_powergating_state = gfx_v11_0_set_powergating_state, 6107 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6108 }; 6109 6110 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6111 .type = AMDGPU_RING_TYPE_GFX, 6112 .align_mask = 0xff, 6113 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6114 .support_64bit_ptrs = true, 6115 .secure_submission_supported = true, 6116 .vmhub = AMDGPU_GFXHUB_0, 6117 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6118 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6119 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6120 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6121 5 + /* COND_EXEC */ 6122 7 + /* PIPELINE_SYNC */ 6123 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6124 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6125 2 + /* VM_FLUSH */ 6126 8 + /* FENCE for VM_FLUSH */ 6127 20 + /* GDS switch */ 6128 5 + /* COND_EXEC */ 6129 7 + /* HDP_flush */ 6130 4 + /* VGT_flush */ 6131 31 + /* DE_META */ 6132 3 + /* CNTX_CTRL */ 6133 5 + /* HDP_INVL */ 6134 8 + 8 + /* FENCE x2 */ 6135 8, /* gfx_v11_0_emit_mem_sync */ 6136 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6137 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6138 .emit_fence = gfx_v11_0_ring_emit_fence, 6139 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6140 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6141 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6142 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6143 .test_ring = gfx_v11_0_ring_test_ring, 6144 .test_ib = gfx_v11_0_ring_test_ib, 6145 .insert_nop = amdgpu_ring_insert_nop, 6146 .pad_ib = amdgpu_ring_generic_pad_ib, 6147 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6148 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6149 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6150 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6151 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6152 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6153 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6154 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6155 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6156 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6157 }; 6158 6159 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6160 .type = AMDGPU_RING_TYPE_COMPUTE, 6161 .align_mask = 0xff, 6162 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6163 .support_64bit_ptrs = true, 6164 .vmhub = AMDGPU_GFXHUB_0, 6165 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6166 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6167 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6168 .emit_frame_size = 6169 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6170 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6171 5 + /* hdp invalidate */ 6172 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6173 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6174 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6175 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6176 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6177 8, /* gfx_v11_0_emit_mem_sync */ 6178 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6179 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6180 .emit_fence = gfx_v11_0_ring_emit_fence, 6181 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6182 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6183 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6184 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6185 .test_ring = gfx_v11_0_ring_test_ring, 6186 .test_ib = gfx_v11_0_ring_test_ib, 6187 .insert_nop = amdgpu_ring_insert_nop, 6188 .pad_ib = amdgpu_ring_generic_pad_ib, 6189 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6190 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6191 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6192 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6193 }; 6194 6195 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6196 .type = AMDGPU_RING_TYPE_KIQ, 6197 .align_mask = 0xff, 6198 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6199 .support_64bit_ptrs = true, 6200 .vmhub = AMDGPU_GFXHUB_0, 6201 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6202 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6203 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6204 .emit_frame_size = 6205 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6206 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6207 5 + /*hdp invalidate */ 6208 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6209 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6210 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6211 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6212 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6213 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6214 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6215 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6216 .test_ring = gfx_v11_0_ring_test_ring, 6217 .test_ib = gfx_v11_0_ring_test_ib, 6218 .insert_nop = amdgpu_ring_insert_nop, 6219 .pad_ib = amdgpu_ring_generic_pad_ib, 6220 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6221 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6222 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6223 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6224 }; 6225 6226 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6227 { 6228 int i; 6229 6230 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6231 6232 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6233 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6234 6235 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6236 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6237 } 6238 6239 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6240 .set = gfx_v11_0_set_eop_interrupt_state, 6241 .process = gfx_v11_0_eop_irq, 6242 }; 6243 6244 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6245 .set = gfx_v11_0_set_priv_reg_fault_state, 6246 .process = gfx_v11_0_priv_reg_irq, 6247 }; 6248 6249 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6250 .set = gfx_v11_0_set_priv_inst_fault_state, 6251 .process = gfx_v11_0_priv_inst_irq, 6252 }; 6253 6254 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6255 { 6256 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6257 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6258 6259 adev->gfx.priv_reg_irq.num_types = 1; 6260 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6261 6262 adev->gfx.priv_inst_irq.num_types = 1; 6263 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6264 } 6265 6266 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6267 { 6268 if (adev->flags & AMD_IS_APU) 6269 adev->gfx.imu.mode = MISSION_MODE; 6270 else 6271 adev->gfx.imu.mode = DEBUG_MODE; 6272 6273 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6274 } 6275 6276 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6277 { 6278 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6279 } 6280 6281 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6282 { 6283 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6284 adev->gfx.config.max_sh_per_se * 6285 adev->gfx.config.max_shader_engines; 6286 6287 adev->gds.gds_size = 0x1000; 6288 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6289 adev->gds.gws_size = 64; 6290 adev->gds.oa_size = 16; 6291 } 6292 6293 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6294 { 6295 /* set gfx eng mqd */ 6296 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6297 sizeof(struct v11_gfx_mqd); 6298 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6299 gfx_v11_0_gfx_mqd_init; 6300 /* set compute eng mqd */ 6301 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6302 sizeof(struct v11_compute_mqd); 6303 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6304 gfx_v11_0_compute_mqd_init; 6305 } 6306 6307 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6308 u32 bitmap) 6309 { 6310 u32 data; 6311 6312 if (!bitmap) 6313 return; 6314 6315 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6316 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6317 6318 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6319 } 6320 6321 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6322 { 6323 u32 data, wgp_bitmask; 6324 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6325 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6326 6327 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6328 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6329 6330 wgp_bitmask = 6331 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6332 6333 return (~data) & wgp_bitmask; 6334 } 6335 6336 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6337 { 6338 u32 wgp_idx, wgp_active_bitmap; 6339 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6340 6341 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6342 cu_active_bitmap = 0; 6343 6344 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6345 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6346 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6347 if (wgp_active_bitmap & (1 << wgp_idx)) 6348 cu_active_bitmap |= cu_bitmap_per_wgp; 6349 } 6350 6351 return cu_active_bitmap; 6352 } 6353 6354 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6355 struct amdgpu_cu_info *cu_info) 6356 { 6357 int i, j, k, counter, active_cu_number = 0; 6358 u32 mask, bitmap; 6359 unsigned disable_masks[8 * 2]; 6360 6361 if (!adev || !cu_info) 6362 return -EINVAL; 6363 6364 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6365 6366 mutex_lock(&adev->grbm_idx_mutex); 6367 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6368 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6369 mask = 1; 6370 counter = 0; 6371 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6372 if (i < 8 && j < 2) 6373 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6374 adev, disable_masks[i * 2 + j]); 6375 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6376 6377 /** 6378 * GFX11 could support more than 4 SEs, while the bitmap 6379 * in cu_info struct is 4x4 and ioctl interface struct 6380 * drm_amdgpu_info_device should keep stable. 6381 * So we use last two columns of bitmap to store cu mask for 6382 * SEs 4 to 7, the layout of the bitmap is as below: 6383 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6384 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6385 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6386 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6387 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6388 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6389 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6390 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6391 */ 6392 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6393 6394 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6395 if (bitmap & mask) 6396 counter++; 6397 6398 mask <<= 1; 6399 } 6400 active_cu_number += counter; 6401 } 6402 } 6403 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6404 mutex_unlock(&adev->grbm_idx_mutex); 6405 6406 cu_info->number = active_cu_number; 6407 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6408 6409 return 0; 6410 } 6411 6412 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6413 { 6414 .type = AMD_IP_BLOCK_TYPE_GFX, 6415 .major = 11, 6416 .minor = 0, 6417 .rev = 0, 6418 .funcs = &gfx_v11_0_ip_funcs, 6419 }; 6420