1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "gfx_v10_0_cleaner_shader.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 372 /* SE status registers */ 373 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 374 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 375 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 376 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 377 }; 378 379 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 380 /* compute registers */ 381 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 382 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 383 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 384 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 385 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS), 420 /* cp header registers */ 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 425 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 426 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 427 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 428 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 429 }; 430 431 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 432 /* gfx queue registers */ 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 452 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 453 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 454 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 455 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), 456 /* gfx header registers */ 457 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 458 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 459 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 460 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 461 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 462 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 463 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 464 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 465 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 466 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 467 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 468 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 469 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 470 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 471 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 472 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 473 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 474 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 475 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 476 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 477 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 478 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 479 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 480 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 481 }; 482 483 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 524 }; 525 526 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 527 /* Pending on emulation bring up */ 528 }; 529 530 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1583 }; 1584 1585 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1624 }; 1625 1626 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1669 }; 1670 1671 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1672 /* Pending on emulation bring up */ 1673 }; 1674 1675 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2296 }; 2297 2298 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2299 /* Pending on emulation bring up */ 2300 }; 2301 2302 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3355 }; 3356 3357 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3401 }; 3402 3403 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3404 /* Pending on emulation bring up */ 3405 }; 3406 3407 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3449 3450 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3452 }; 3453 3454 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3479 3480 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3482 }; 3483 3484 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3505 }; 3506 3507 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3544 }; 3545 3546 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3579 }; 3580 3581 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3616 }; 3617 3618 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3641 }; 3642 3643 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3666 }; 3667 3668 #define DEFAULT_SH_MEM_CONFIG \ 3669 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3670 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3671 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3672 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3673 3674 /* TODO: pending on golden setting value of gb address config */ 3675 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3676 3677 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3678 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3679 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3680 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3681 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3682 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3683 struct amdgpu_cu_info *cu_info); 3684 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3685 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3686 u32 sh_num, u32 instance, int xcc_id); 3687 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3688 3689 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3690 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3691 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3692 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3693 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3694 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3695 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3696 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3697 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3698 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3699 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3700 uint16_t pasid, uint32_t flush_type, 3701 bool all_hub, uint8_t dst_sel); 3702 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3703 unsigned int vmid); 3704 3705 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3706 enum amd_powergating_state state); 3707 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3708 { 3709 struct amdgpu_device *adev = kiq_ring->adev; 3710 u64 shader_mc_addr; 3711 3712 /* Cleaner shader MC address */ 3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 3714 3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3717 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3724 } 3725 3726 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3727 struct amdgpu_ring *ring) 3728 { 3729 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3730 uint64_t wptr_addr = ring->wptr_gpu_addr; 3731 uint32_t eng_sel = 0; 3732 3733 switch (ring->funcs->type) { 3734 case AMDGPU_RING_TYPE_COMPUTE: 3735 eng_sel = 0; 3736 break; 3737 case AMDGPU_RING_TYPE_GFX: 3738 eng_sel = 4; 3739 break; 3740 case AMDGPU_RING_TYPE_MES: 3741 eng_sel = 5; 3742 break; 3743 default: 3744 WARN_ON(1); 3745 } 3746 3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3748 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3750 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3751 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3752 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3753 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3754 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3755 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3756 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3757 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3758 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3759 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3760 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3761 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3762 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3763 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3764 } 3765 3766 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3767 struct amdgpu_ring *ring, 3768 enum amdgpu_unmap_queues_action action, 3769 u64 gpu_addr, u64 seq) 3770 { 3771 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3772 3773 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3774 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3775 PACKET3_UNMAP_QUEUES_ACTION(action) | 3776 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3777 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3778 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3779 amdgpu_ring_write(kiq_ring, 3780 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3781 3782 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3783 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3784 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3785 amdgpu_ring_write(kiq_ring, seq); 3786 } else { 3787 amdgpu_ring_write(kiq_ring, 0); 3788 amdgpu_ring_write(kiq_ring, 0); 3789 amdgpu_ring_write(kiq_ring, 0); 3790 } 3791 } 3792 3793 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3794 struct amdgpu_ring *ring, 3795 u64 addr, 3796 u64 seq) 3797 { 3798 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3799 3800 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3801 amdgpu_ring_write(kiq_ring, 3802 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3803 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3804 PACKET3_QUERY_STATUS_COMMAND(2)); 3805 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3806 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3807 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3808 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3809 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3810 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3811 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3812 } 3813 3814 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3815 uint16_t pasid, uint32_t flush_type, 3816 bool all_hub) 3817 { 3818 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3819 } 3820 3821 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 3822 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 3823 uint32_t xcc_id, uint32_t vmid) 3824 { 3825 struct amdgpu_device *adev = kiq_ring->adev; 3826 unsigned i; 3827 uint32_t tmp; 3828 3829 /* enter save mode */ 3830 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3831 mutex_lock(&adev->srbm_mutex); 3832 nv_grbm_select(adev, me_id, pipe_id, queue_id, 0); 3833 3834 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 3835 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2); 3836 WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1); 3837 /* wait till dequeue take effects */ 3838 for (i = 0; i < adev->usec_timeout; i++) { 3839 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3840 break; 3841 udelay(1); 3842 } 3843 if (i >= adev->usec_timeout) 3844 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 3845 } else if (queue_type == AMDGPU_RING_TYPE_GFX) { 3846 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 3847 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 3848 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 3849 if (pipe_id == 0) 3850 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 3851 else 3852 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 3853 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp); 3854 3855 /* wait till dequeue take effects */ 3856 for (i = 0; i < adev->usec_timeout; i++) { 3857 if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1)) 3858 break; 3859 udelay(1); 3860 } 3861 if (i >= adev->usec_timeout) 3862 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 3863 } else { 3864 dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type); 3865 } 3866 3867 nv_grbm_select(adev, 0, 0, 0, 0); 3868 mutex_unlock(&adev->srbm_mutex); 3869 /* exit safe mode */ 3870 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 3871 } 3872 3873 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3874 .kiq_set_resources = gfx10_kiq_set_resources, 3875 .kiq_map_queues = gfx10_kiq_map_queues, 3876 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3877 .kiq_query_status = gfx10_kiq_query_status, 3878 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3879 .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue, 3880 .set_resources_size = 8, 3881 .map_queues_size = 7, 3882 .unmap_queues_size = 6, 3883 .query_status_size = 7, 3884 .invalidate_tlbs_size = 2, 3885 }; 3886 3887 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3888 { 3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3890 } 3891 3892 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3893 { 3894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3895 case IP_VERSION(10, 1, 10): 3896 soc15_program_register_sequence(adev, 3897 golden_settings_gc_rlc_spm_10_0_nv10, 3898 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3899 break; 3900 case IP_VERSION(10, 1, 1): 3901 soc15_program_register_sequence(adev, 3902 golden_settings_gc_rlc_spm_10_1_nv14, 3903 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3904 break; 3905 case IP_VERSION(10, 1, 2): 3906 soc15_program_register_sequence(adev, 3907 golden_settings_gc_rlc_spm_10_1_2_nv12, 3908 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3909 break; 3910 default: 3911 break; 3912 } 3913 } 3914 3915 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3916 { 3917 if (amdgpu_sriov_vf(adev)) 3918 return; 3919 3920 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3921 case IP_VERSION(10, 1, 10): 3922 soc15_program_register_sequence(adev, 3923 golden_settings_gc_10_1, 3924 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3925 soc15_program_register_sequence(adev, 3926 golden_settings_gc_10_0_nv10, 3927 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3928 break; 3929 case IP_VERSION(10, 1, 1): 3930 soc15_program_register_sequence(adev, 3931 golden_settings_gc_10_1_1, 3932 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3933 soc15_program_register_sequence(adev, 3934 golden_settings_gc_10_1_nv14, 3935 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3936 break; 3937 case IP_VERSION(10, 1, 2): 3938 soc15_program_register_sequence(adev, 3939 golden_settings_gc_10_1_2, 3940 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3941 soc15_program_register_sequence(adev, 3942 golden_settings_gc_10_1_2_nv12, 3943 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3944 break; 3945 case IP_VERSION(10, 3, 0): 3946 soc15_program_register_sequence(adev, 3947 golden_settings_gc_10_3, 3948 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3949 soc15_program_register_sequence(adev, 3950 golden_settings_gc_10_3_sienna_cichlid, 3951 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3952 break; 3953 case IP_VERSION(10, 3, 2): 3954 soc15_program_register_sequence(adev, 3955 golden_settings_gc_10_3_2, 3956 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3957 break; 3958 case IP_VERSION(10, 3, 1): 3959 soc15_program_register_sequence(adev, 3960 golden_settings_gc_10_3_vangogh, 3961 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3962 break; 3963 case IP_VERSION(10, 3, 3): 3964 soc15_program_register_sequence(adev, 3965 golden_settings_gc_10_3_3, 3966 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3967 break; 3968 case IP_VERSION(10, 3, 4): 3969 soc15_program_register_sequence(adev, 3970 golden_settings_gc_10_3_4, 3971 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3972 break; 3973 case IP_VERSION(10, 3, 5): 3974 soc15_program_register_sequence(adev, 3975 golden_settings_gc_10_3_5, 3976 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3977 break; 3978 case IP_VERSION(10, 1, 3): 3979 case IP_VERSION(10, 1, 4): 3980 soc15_program_register_sequence(adev, 3981 golden_settings_gc_10_0_cyan_skillfish, 3982 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3983 break; 3984 case IP_VERSION(10, 3, 6): 3985 soc15_program_register_sequence(adev, 3986 golden_settings_gc_10_3_6, 3987 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3988 break; 3989 case IP_VERSION(10, 3, 7): 3990 soc15_program_register_sequence(adev, 3991 golden_settings_gc_10_3_7, 3992 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3993 break; 3994 default: 3995 break; 3996 } 3997 gfx_v10_0_init_spm_golden_registers(adev); 3998 } 3999 4000 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 4001 bool wc, uint32_t reg, uint32_t val) 4002 { 4003 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4004 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 4006 amdgpu_ring_write(ring, reg); 4007 amdgpu_ring_write(ring, 0); 4008 amdgpu_ring_write(ring, val); 4009 } 4010 4011 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 4012 int mem_space, int opt, uint32_t addr0, 4013 uint32_t addr1, uint32_t ref, uint32_t mask, 4014 uint32_t inv) 4015 { 4016 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4017 amdgpu_ring_write(ring, 4018 /* memory (1) or register (0) */ 4019 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 4020 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 4021 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 4022 WAIT_REG_MEM_ENGINE(eng_sel))); 4023 4024 if (mem_space) 4025 BUG_ON(addr0 & 0x3); /* Dword align */ 4026 amdgpu_ring_write(ring, addr0); 4027 amdgpu_ring_write(ring, addr1); 4028 amdgpu_ring_write(ring, ref); 4029 amdgpu_ring_write(ring, mask); 4030 amdgpu_ring_write(ring, inv); /* poll interval */ 4031 } 4032 4033 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 4034 { 4035 struct amdgpu_device *adev = ring->adev; 4036 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4037 uint32_t tmp = 0; 4038 unsigned int i; 4039 int r; 4040 4041 WREG32(scratch, 0xCAFEDEAD); 4042 r = amdgpu_ring_alloc(ring, 3); 4043 if (r) { 4044 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 4045 ring->idx, r); 4046 return r; 4047 } 4048 4049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 4050 amdgpu_ring_write(ring, scratch - 4051 PACKET3_SET_UCONFIG_REG_START); 4052 amdgpu_ring_write(ring, 0xDEADBEEF); 4053 amdgpu_ring_commit(ring); 4054 4055 for (i = 0; i < adev->usec_timeout; i++) { 4056 tmp = RREG32(scratch); 4057 if (tmp == 0xDEADBEEF) 4058 break; 4059 if (amdgpu_emu_mode == 1) 4060 msleep(1); 4061 else 4062 udelay(1); 4063 } 4064 4065 if (i >= adev->usec_timeout) 4066 r = -ETIMEDOUT; 4067 4068 return r; 4069 } 4070 4071 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 4072 { 4073 struct amdgpu_device *adev = ring->adev; 4074 struct amdgpu_ib ib; 4075 struct dma_fence *f = NULL; 4076 unsigned int index; 4077 uint64_t gpu_addr; 4078 volatile uint32_t *cpu_ptr; 4079 long r; 4080 4081 memset(&ib, 0, sizeof(ib)); 4082 4083 r = amdgpu_device_wb_get(adev, &index); 4084 if (r) 4085 return r; 4086 4087 gpu_addr = adev->wb.gpu_addr + (index * 4); 4088 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4089 cpu_ptr = &adev->wb.wb[index]; 4090 4091 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4092 if (r) { 4093 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 4094 goto err1; 4095 } 4096 4097 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4099 ib.ptr[2] = lower_32_bits(gpu_addr); 4100 ib.ptr[3] = upper_32_bits(gpu_addr); 4101 ib.ptr[4] = 0xDEADBEEF; 4102 ib.length_dw = 5; 4103 4104 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4105 if (r) 4106 goto err2; 4107 4108 r = dma_fence_wait_timeout(f, false, timeout); 4109 if (r == 0) { 4110 r = -ETIMEDOUT; 4111 goto err2; 4112 } else if (r < 0) { 4113 goto err2; 4114 } 4115 4116 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4117 r = 0; 4118 else 4119 r = -EINVAL; 4120 err2: 4121 amdgpu_ib_free(&ib, NULL); 4122 dma_fence_put(f); 4123 err1: 4124 amdgpu_device_wb_free(adev, index); 4125 return r; 4126 } 4127 4128 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4129 { 4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4131 amdgpu_ucode_release(&adev->gfx.me_fw); 4132 amdgpu_ucode_release(&adev->gfx.ce_fw); 4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4134 amdgpu_ucode_release(&adev->gfx.mec_fw); 4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4136 4137 kfree(adev->gfx.rlc.register_list_format); 4138 } 4139 4140 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4141 { 4142 adev->gfx.cp_fw_write_wait = false; 4143 4144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4145 case IP_VERSION(10, 1, 10): 4146 case IP_VERSION(10, 1, 2): 4147 case IP_VERSION(10, 1, 1): 4148 case IP_VERSION(10, 1, 3): 4149 case IP_VERSION(10, 1, 4): 4150 if ((adev->gfx.me_fw_version >= 0x00000046) && 4151 (adev->gfx.me_feature_version >= 27) && 4152 (adev->gfx.pfp_fw_version >= 0x00000068) && 4153 (adev->gfx.pfp_feature_version >= 27) && 4154 (adev->gfx.mec_fw_version >= 0x0000005b) && 4155 (adev->gfx.mec_feature_version >= 27)) 4156 adev->gfx.cp_fw_write_wait = true; 4157 break; 4158 case IP_VERSION(10, 3, 0): 4159 case IP_VERSION(10, 3, 2): 4160 case IP_VERSION(10, 3, 1): 4161 case IP_VERSION(10, 3, 4): 4162 case IP_VERSION(10, 3, 5): 4163 case IP_VERSION(10, 3, 6): 4164 case IP_VERSION(10, 3, 3): 4165 case IP_VERSION(10, 3, 7): 4166 adev->gfx.cp_fw_write_wait = true; 4167 break; 4168 default: 4169 break; 4170 } 4171 4172 if (!adev->gfx.cp_fw_write_wait) 4173 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4174 } 4175 4176 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4177 { 4178 bool ret = false; 4179 4180 switch (adev->pdev->revision) { 4181 case 0xc2: 4182 case 0xc3: 4183 ret = true; 4184 break; 4185 default: 4186 ret = false; 4187 break; 4188 } 4189 4190 return ret; 4191 } 4192 4193 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4194 { 4195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4196 case IP_VERSION(10, 1, 10): 4197 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4198 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4199 break; 4200 default: 4201 break; 4202 } 4203 } 4204 4205 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4206 { 4207 char fw_name[53]; 4208 char ucode_prefix[30]; 4209 const char *wks = ""; 4210 int err; 4211 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4212 uint16_t version_major; 4213 uint16_t version_minor; 4214 4215 DRM_DEBUG("\n"); 4216 4217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4218 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4219 wks = "_wks"; 4220 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4221 4222 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4223 AMDGPU_UCODE_REQUIRED, 4224 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4225 if (err) 4226 goto out; 4227 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4228 4229 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4230 AMDGPU_UCODE_REQUIRED, 4231 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4232 if (err) 4233 goto out; 4234 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4235 4236 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4237 AMDGPU_UCODE_REQUIRED, 4238 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4239 if (err) 4240 goto out; 4241 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4242 4243 if (!amdgpu_sriov_vf(adev)) { 4244 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4245 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4246 if (err) 4247 goto out; 4248 4249 /* don't validate this firmware. There are apparently firmwares 4250 * in the wild with incorrect size in the header 4251 */ 4252 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4253 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4254 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4255 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4256 if (err) 4257 goto out; 4258 } 4259 4260 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4261 AMDGPU_UCODE_REQUIRED, 4262 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4263 if (err) 4264 goto out; 4265 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4266 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4267 4268 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4269 AMDGPU_UCODE_REQUIRED, 4270 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4271 if (!err) { 4272 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4274 } else { 4275 err = 0; 4276 adev->gfx.mec2_fw = NULL; 4277 } 4278 4279 gfx_v10_0_check_fw_write_wait(adev); 4280 out: 4281 if (err) { 4282 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4283 amdgpu_ucode_release(&adev->gfx.me_fw); 4284 amdgpu_ucode_release(&adev->gfx.ce_fw); 4285 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4286 amdgpu_ucode_release(&adev->gfx.mec_fw); 4287 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4288 } 4289 4290 gfx_v10_0_check_gfxoff_flag(adev); 4291 4292 return err; 4293 } 4294 4295 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4296 { 4297 u32 count = 0; 4298 const struct cs_section_def *sect = NULL; 4299 const struct cs_extent_def *ext = NULL; 4300 4301 /* begin clear state */ 4302 count += 2; 4303 /* context control state */ 4304 count += 3; 4305 4306 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4307 for (ext = sect->section; ext->extent != NULL; ++ext) { 4308 if (sect->id == SECT_CONTEXT) 4309 count += 2 + ext->reg_count; 4310 else 4311 return 0; 4312 } 4313 } 4314 4315 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4316 count += 3; 4317 /* end clear state */ 4318 count += 2; 4319 /* clear state */ 4320 count += 2; 4321 4322 return count; 4323 } 4324 4325 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4326 volatile u32 *buffer) 4327 { 4328 u32 count = 0, i; 4329 const struct cs_section_def *sect = NULL; 4330 const struct cs_extent_def *ext = NULL; 4331 int ctx_reg_offset; 4332 4333 if (adev->gfx.rlc.cs_data == NULL) 4334 return; 4335 if (buffer == NULL) 4336 return; 4337 4338 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4339 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4340 4341 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4342 buffer[count++] = cpu_to_le32(0x80000000); 4343 buffer[count++] = cpu_to_le32(0x80000000); 4344 4345 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4346 for (ext = sect->section; ext->extent != NULL; ++ext) { 4347 if (sect->id == SECT_CONTEXT) { 4348 buffer[count++] = 4349 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4350 buffer[count++] = cpu_to_le32(ext->reg_index - 4351 PACKET3_SET_CONTEXT_REG_START); 4352 for (i = 0; i < ext->reg_count; i++) 4353 buffer[count++] = cpu_to_le32(ext->extent[i]); 4354 } 4355 } 4356 } 4357 4358 ctx_reg_offset = 4359 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4360 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4361 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4362 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4363 4364 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4365 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4366 4367 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4368 buffer[count++] = cpu_to_le32(0); 4369 } 4370 4371 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4372 { 4373 /* clear state block */ 4374 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4375 &adev->gfx.rlc.clear_state_gpu_addr, 4376 (void **)&adev->gfx.rlc.cs_ptr); 4377 4378 /* jump table block */ 4379 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4380 &adev->gfx.rlc.cp_table_gpu_addr, 4381 (void **)&adev->gfx.rlc.cp_table_ptr); 4382 } 4383 4384 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4385 { 4386 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4387 4388 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4389 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4390 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4391 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4392 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4393 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4394 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4395 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4396 case IP_VERSION(10, 3, 0): 4397 reg_access_ctrl->spare_int = 4398 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4399 break; 4400 default: 4401 reg_access_ctrl->spare_int = 4402 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4403 break; 4404 } 4405 adev->gfx.rlc.rlcg_reg_access_supported = true; 4406 } 4407 4408 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4409 { 4410 const struct cs_section_def *cs_data; 4411 int r; 4412 4413 adev->gfx.rlc.cs_data = gfx10_cs_data; 4414 4415 cs_data = adev->gfx.rlc.cs_data; 4416 4417 if (cs_data) { 4418 /* init clear state block */ 4419 r = amdgpu_gfx_rlc_init_csb(adev); 4420 if (r) 4421 return r; 4422 } 4423 4424 return 0; 4425 } 4426 4427 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4428 { 4429 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4430 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4431 } 4432 4433 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4434 { 4435 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4436 4437 amdgpu_gfx_graphics_queue_acquire(adev); 4438 } 4439 4440 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4441 { 4442 int r; 4443 u32 *hpd; 4444 const __le32 *fw_data = NULL; 4445 unsigned int fw_size; 4446 u32 *fw = NULL; 4447 size_t mec_hpd_size; 4448 4449 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4450 4451 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4452 4453 /* take ownership of the relevant compute queues */ 4454 amdgpu_gfx_compute_queue_acquire(adev); 4455 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4456 4457 if (mec_hpd_size) { 4458 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4459 AMDGPU_GEM_DOMAIN_GTT, 4460 &adev->gfx.mec.hpd_eop_obj, 4461 &adev->gfx.mec.hpd_eop_gpu_addr, 4462 (void **)&hpd); 4463 if (r) { 4464 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4465 gfx_v10_0_mec_fini(adev); 4466 return r; 4467 } 4468 4469 memset(hpd, 0, mec_hpd_size); 4470 4471 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4472 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4473 } 4474 4475 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4476 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4477 4478 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4479 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4480 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4481 4482 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4483 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4484 &adev->gfx.mec.mec_fw_obj, 4485 &adev->gfx.mec.mec_fw_gpu_addr, 4486 (void **)&fw); 4487 if (r) { 4488 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4489 gfx_v10_0_mec_fini(adev); 4490 return r; 4491 } 4492 4493 memcpy(fw, fw_data, fw_size); 4494 4495 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4496 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4497 } 4498 4499 return 0; 4500 } 4501 4502 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4503 { 4504 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4505 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4506 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4507 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4508 } 4509 4510 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4511 uint32_t thread, uint32_t regno, 4512 uint32_t num, uint32_t *out) 4513 { 4514 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4515 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4516 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4517 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4518 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4519 while (num--) 4520 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4521 } 4522 4523 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4524 { 4525 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4526 * field when performing a select_se_sh so it should be 4527 * zero here 4528 */ 4529 WARN_ON(simd != 0); 4530 4531 /* type 2 wave data */ 4532 dst[(*no_fields)++] = 2; 4533 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4534 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4535 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4536 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4537 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4538 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4539 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4540 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4541 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4542 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4543 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4544 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4545 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4546 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4547 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4548 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4549 } 4550 4551 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4552 uint32_t wave, uint32_t start, 4553 uint32_t size, uint32_t *dst) 4554 { 4555 WARN_ON(simd != 0); 4556 4557 wave_read_regs( 4558 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4559 dst); 4560 } 4561 4562 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4563 uint32_t wave, uint32_t thread, 4564 uint32_t start, uint32_t size, 4565 uint32_t *dst) 4566 { 4567 wave_read_regs( 4568 adev, wave, thread, 4569 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4570 } 4571 4572 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4573 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4574 { 4575 nv_grbm_select(adev, me, pipe, q, vm); 4576 } 4577 4578 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4579 bool enable) 4580 { 4581 uint32_t data, def; 4582 4583 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4584 4585 if (enable) 4586 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4587 else 4588 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4589 4590 if (data != def) 4591 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4592 } 4593 4594 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4595 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4596 .select_se_sh = &gfx_v10_0_select_se_sh, 4597 .read_wave_data = &gfx_v10_0_read_wave_data, 4598 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4599 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4600 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4601 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4602 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4603 }; 4604 4605 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4606 { 4607 u32 gb_addr_config; 4608 4609 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4610 case IP_VERSION(10, 1, 10): 4611 case IP_VERSION(10, 1, 1): 4612 case IP_VERSION(10, 1, 2): 4613 adev->gfx.config.max_hw_contexts = 8; 4614 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4615 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4616 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4617 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4618 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4619 break; 4620 case IP_VERSION(10, 3, 0): 4621 case IP_VERSION(10, 3, 2): 4622 case IP_VERSION(10, 3, 1): 4623 case IP_VERSION(10, 3, 4): 4624 case IP_VERSION(10, 3, 5): 4625 case IP_VERSION(10, 3, 6): 4626 case IP_VERSION(10, 3, 3): 4627 case IP_VERSION(10, 3, 7): 4628 adev->gfx.config.max_hw_contexts = 8; 4629 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4630 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4631 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4632 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4633 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4634 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4635 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4636 break; 4637 case IP_VERSION(10, 1, 3): 4638 case IP_VERSION(10, 1, 4): 4639 adev->gfx.config.max_hw_contexts = 8; 4640 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4641 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4642 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4643 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4644 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4645 break; 4646 default: 4647 BUG(); 4648 break; 4649 } 4650 4651 adev->gfx.config.gb_addr_config = gb_addr_config; 4652 4653 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4654 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4655 GB_ADDR_CONFIG, NUM_PIPES); 4656 4657 adev->gfx.config.max_tile_pipes = 4658 adev->gfx.config.gb_addr_config_fields.num_pipes; 4659 4660 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4661 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4662 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4663 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4664 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4665 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4666 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4667 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4668 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4669 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4670 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4671 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4672 } 4673 4674 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4675 int me, int pipe, int queue) 4676 { 4677 struct amdgpu_ring *ring; 4678 unsigned int irq_type; 4679 unsigned int hw_prio; 4680 4681 ring = &adev->gfx.gfx_ring[ring_id]; 4682 4683 ring->me = me; 4684 ring->pipe = pipe; 4685 ring->queue = queue; 4686 4687 ring->ring_obj = NULL; 4688 ring->use_doorbell = true; 4689 4690 if (!ring_id) 4691 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4692 else 4693 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4694 ring->vm_hub = AMDGPU_GFXHUB(0); 4695 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4696 4697 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4698 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4699 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4700 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4701 hw_prio, NULL); 4702 } 4703 4704 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4705 int mec, int pipe, int queue) 4706 { 4707 unsigned int irq_type; 4708 struct amdgpu_ring *ring; 4709 unsigned int hw_prio; 4710 4711 ring = &adev->gfx.compute_ring[ring_id]; 4712 4713 /* mec0 is me1 */ 4714 ring->me = mec + 1; 4715 ring->pipe = pipe; 4716 ring->queue = queue; 4717 4718 ring->ring_obj = NULL; 4719 ring->use_doorbell = true; 4720 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4721 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4722 + (ring_id * GFX10_MEC_HPD_SIZE); 4723 ring->vm_hub = AMDGPU_GFXHUB(0); 4724 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4725 4726 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4727 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4728 + ring->pipe; 4729 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4730 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4731 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4732 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4733 hw_prio, NULL); 4734 } 4735 4736 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4737 { 4738 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4739 uint32_t *ptr; 4740 uint32_t inst; 4741 4742 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4743 if (!ptr) { 4744 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4745 adev->gfx.ip_dump_core = NULL; 4746 } else { 4747 adev->gfx.ip_dump_core = ptr; 4748 } 4749 4750 /* Allocate memory for compute queue registers for all the instances */ 4751 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4752 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4753 adev->gfx.mec.num_queue_per_pipe; 4754 4755 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4756 if (!ptr) { 4757 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4758 adev->gfx.ip_dump_compute_queues = NULL; 4759 } else { 4760 adev->gfx.ip_dump_compute_queues = ptr; 4761 } 4762 4763 /* Allocate memory for gfx queue registers for all the instances */ 4764 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4765 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4766 adev->gfx.me.num_queue_per_pipe; 4767 4768 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4769 if (!ptr) { 4770 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4771 adev->gfx.ip_dump_gfx_queues = NULL; 4772 } else { 4773 adev->gfx.ip_dump_gfx_queues = ptr; 4774 } 4775 } 4776 4777 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 4778 { 4779 int i, j, k, r, ring_id = 0; 4780 int xcc_id = 0; 4781 struct amdgpu_device *adev = ip_block->adev; 4782 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 4783 4784 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 4785 4786 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4787 case IP_VERSION(10, 1, 10): 4788 case IP_VERSION(10, 1, 1): 4789 case IP_VERSION(10, 1, 2): 4790 case IP_VERSION(10, 1, 3): 4791 case IP_VERSION(10, 1, 4): 4792 adev->gfx.me.num_me = 1; 4793 adev->gfx.me.num_pipe_per_me = 1; 4794 adev->gfx.me.num_queue_per_pipe = 8; 4795 adev->gfx.mec.num_mec = 2; 4796 adev->gfx.mec.num_pipe_per_mec = 4; 4797 adev->gfx.mec.num_queue_per_pipe = 8; 4798 break; 4799 case IP_VERSION(10, 3, 0): 4800 case IP_VERSION(10, 3, 2): 4801 case IP_VERSION(10, 3, 1): 4802 case IP_VERSION(10, 3, 4): 4803 case IP_VERSION(10, 3, 5): 4804 case IP_VERSION(10, 3, 6): 4805 case IP_VERSION(10, 3, 3): 4806 case IP_VERSION(10, 3, 7): 4807 adev->gfx.me.num_me = 1; 4808 adev->gfx.me.num_pipe_per_me = 2; 4809 adev->gfx.me.num_queue_per_pipe = 2; 4810 adev->gfx.mec.num_mec = 2; 4811 adev->gfx.mec.num_pipe_per_mec = 4; 4812 adev->gfx.mec.num_queue_per_pipe = 4; 4813 break; 4814 default: 4815 adev->gfx.me.num_me = 1; 4816 adev->gfx.me.num_pipe_per_me = 1; 4817 adev->gfx.me.num_queue_per_pipe = 1; 4818 adev->gfx.mec.num_mec = 1; 4819 adev->gfx.mec.num_pipe_per_mec = 4; 4820 adev->gfx.mec.num_queue_per_pipe = 8; 4821 break; 4822 } 4823 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4824 case IP_VERSION(10, 1, 10): 4825 case IP_VERSION(10, 1, 1): 4826 case IP_VERSION(10, 1, 2): 4827 adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex; 4828 adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex); 4829 if (adev->gfx.me_fw_version >= 101 && 4830 adev->gfx.pfp_fw_version >= 158 && 4831 adev->gfx.mec_fw_version >= 152) { 4832 adev->gfx.enable_cleaner_shader = true; 4833 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4834 if (r) { 4835 adev->gfx.enable_cleaner_shader = false; 4836 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4837 } 4838 } 4839 break; 4840 case IP_VERSION(10, 3, 0): 4841 case IP_VERSION(10, 3, 1): 4842 case IP_VERSION(10, 3, 2): 4843 case IP_VERSION(10, 3, 3): 4844 case IP_VERSION(10, 3, 4): 4845 case IP_VERSION(10, 3, 5): 4846 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4847 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4848 if (adev->gfx.me_fw_version >= 64 && 4849 adev->gfx.pfp_fw_version >= 100 && 4850 adev->gfx.mec_fw_version >= 122) { 4851 adev->gfx.enable_cleaner_shader = true; 4852 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4853 if (r) { 4854 adev->gfx.enable_cleaner_shader = false; 4855 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4856 } 4857 } 4858 break; 4859 case IP_VERSION(10, 3, 6): 4860 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4861 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4862 if (adev->gfx.me_fw_version >= 14 && 4863 adev->gfx.pfp_fw_version >= 17 && 4864 adev->gfx.mec_fw_version >= 24) { 4865 adev->gfx.enable_cleaner_shader = true; 4866 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4867 if (r) { 4868 adev->gfx.enable_cleaner_shader = false; 4869 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4870 } 4871 } 4872 break; 4873 case IP_VERSION(10, 3, 7): 4874 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4875 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4876 if (adev->gfx.me_fw_version >= 4 && 4877 adev->gfx.pfp_fw_version >= 9 && 4878 adev->gfx.mec_fw_version >= 12) { 4879 adev->gfx.enable_cleaner_shader = true; 4880 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4881 if (r) { 4882 adev->gfx.enable_cleaner_shader = false; 4883 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4884 } 4885 } 4886 break; 4887 default: 4888 adev->gfx.enable_cleaner_shader = false; 4889 break; 4890 } 4891 4892 /* KIQ event */ 4893 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4894 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4895 &adev->gfx.kiq[0].irq); 4896 if (r) 4897 return r; 4898 4899 /* EOP Event */ 4900 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4901 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4902 &adev->gfx.eop_irq); 4903 if (r) 4904 return r; 4905 4906 /* Bad opcode Event */ 4907 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4908 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4909 &adev->gfx.bad_op_irq); 4910 if (r) 4911 return r; 4912 4913 /* Privileged reg */ 4914 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4915 &adev->gfx.priv_reg_irq); 4916 if (r) 4917 return r; 4918 4919 /* Privileged inst */ 4920 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4921 &adev->gfx.priv_inst_irq); 4922 if (r) 4923 return r; 4924 4925 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4926 4927 gfx_v10_0_me_init(adev); 4928 4929 if (adev->gfx.rlc.funcs) { 4930 if (adev->gfx.rlc.funcs->init) { 4931 r = adev->gfx.rlc.funcs->init(adev); 4932 if (r) { 4933 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4934 return r; 4935 } 4936 } 4937 } 4938 4939 r = gfx_v10_0_mec_init(adev); 4940 if (r) { 4941 DRM_ERROR("Failed to init MEC BOs!\n"); 4942 return r; 4943 } 4944 4945 /* set up the gfx ring */ 4946 for (i = 0; i < adev->gfx.me.num_me; i++) { 4947 for (j = 0; j < num_queue_per_pipe; j++) { 4948 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4949 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4950 continue; 4951 4952 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4953 i, k, j); 4954 if (r) 4955 return r; 4956 ring_id++; 4957 } 4958 } 4959 } 4960 4961 ring_id = 0; 4962 /* set up the compute queues - allocate horizontally across pipes */ 4963 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4964 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4965 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4966 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4967 k, j)) 4968 continue; 4969 4970 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4971 i, k, j); 4972 if (r) 4973 return r; 4974 4975 ring_id++; 4976 } 4977 } 4978 } 4979 /* TODO: Add queue reset mask when FW fully supports it */ 4980 adev->gfx.gfx_supported_reset = 4981 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4982 adev->gfx.compute_supported_reset = 4983 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4984 4985 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4986 if (r) { 4987 DRM_ERROR("Failed to init KIQ BOs!\n"); 4988 return r; 4989 } 4990 4991 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4992 if (r) 4993 return r; 4994 4995 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4996 if (r) 4997 return r; 4998 4999 /* allocate visible FB for rlc auto-loading fw */ 5000 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5001 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 5002 if (r) 5003 return r; 5004 } 5005 5006 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 5007 5008 gfx_v10_0_gpu_early_init(adev); 5009 5010 gfx_v10_0_alloc_ip_dump(adev); 5011 5012 r = amdgpu_gfx_sysfs_init(adev); 5013 if (r) 5014 return r; 5015 5016 return 0; 5017 } 5018 5019 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 5020 { 5021 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 5022 &adev->gfx.pfp.pfp_fw_gpu_addr, 5023 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5024 } 5025 5026 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 5027 { 5028 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 5029 &adev->gfx.ce.ce_fw_gpu_addr, 5030 (void **)&adev->gfx.ce.ce_fw_ptr); 5031 } 5032 5033 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 5034 { 5035 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 5036 &adev->gfx.me.me_fw_gpu_addr, 5037 (void **)&adev->gfx.me.me_fw_ptr); 5038 } 5039 5040 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 5041 { 5042 int i; 5043 struct amdgpu_device *adev = ip_block->adev; 5044 5045 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5046 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 5047 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5048 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 5049 5050 amdgpu_gfx_mqd_sw_fini(adev, 0); 5051 5052 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 5053 amdgpu_gfx_kiq_fini(adev, 0); 5054 5055 amdgpu_gfx_cleaner_shader_sw_fini(adev); 5056 5057 gfx_v10_0_pfp_fini(adev); 5058 gfx_v10_0_ce_fini(adev); 5059 gfx_v10_0_me_fini(adev); 5060 gfx_v10_0_rlc_fini(adev); 5061 gfx_v10_0_mec_fini(adev); 5062 5063 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 5064 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 5065 5066 gfx_v10_0_free_microcode(adev); 5067 amdgpu_gfx_sysfs_fini(adev); 5068 5069 kfree(adev->gfx.ip_dump_core); 5070 kfree(adev->gfx.ip_dump_compute_queues); 5071 kfree(adev->gfx.ip_dump_gfx_queues); 5072 5073 return 0; 5074 } 5075 5076 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 5077 u32 sh_num, u32 instance, int xcc_id) 5078 { 5079 u32 data; 5080 5081 if (instance == 0xffffffff) 5082 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 5083 INSTANCE_BROADCAST_WRITES, 1); 5084 else 5085 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 5086 instance); 5087 5088 if (se_num == 0xffffffff) 5089 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 5090 1); 5091 else 5092 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 5093 5094 if (sh_num == 0xffffffff) 5095 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 5096 1); 5097 else 5098 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 5099 5100 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 5101 } 5102 5103 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 5104 { 5105 u32 data, mask; 5106 5107 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5108 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5109 5110 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5111 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5112 5113 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5114 adev->gfx.config.max_sh_per_se); 5115 5116 return (~data) & mask; 5117 } 5118 5119 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5120 { 5121 int i, j; 5122 u32 data; 5123 u32 active_rbs = 0; 5124 u32 bitmap; 5125 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5126 adev->gfx.config.max_sh_per_se; 5127 5128 mutex_lock(&adev->grbm_idx_mutex); 5129 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5130 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5131 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5132 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 5133 IP_VERSION(10, 3, 0)) || 5134 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5135 IP_VERSION(10, 3, 3)) || 5136 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5137 IP_VERSION(10, 3, 6))) && 5138 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5139 continue; 5140 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5141 data = gfx_v10_0_get_rb_active_bitmap(adev); 5142 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5143 rb_bitmap_width_per_sh); 5144 } 5145 } 5146 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5147 mutex_unlock(&adev->grbm_idx_mutex); 5148 5149 adev->gfx.config.backend_enable_mask = active_rbs; 5150 adev->gfx.config.num_rbs = hweight32(active_rbs); 5151 } 5152 5153 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5154 { 5155 uint32_t num_sc; 5156 uint32_t enabled_rb_per_sh; 5157 uint32_t active_rb_bitmap; 5158 uint32_t num_rb_per_sc; 5159 uint32_t num_packer_per_sc; 5160 uint32_t pa_sc_tile_steering_override; 5161 5162 /* for ASICs that integrates GFX v10.3 5163 * pa_sc_tile_steering_override should be set to 0 5164 */ 5165 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 5166 return 0; 5167 5168 /* init num_sc */ 5169 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5170 adev->gfx.config.num_sc_per_sh; 5171 /* init num_rb_per_sc */ 5172 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5173 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5174 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5175 /* init num_packer_per_sc */ 5176 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5177 5178 pa_sc_tile_steering_override = 0; 5179 pa_sc_tile_steering_override |= 5180 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5181 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5182 pa_sc_tile_steering_override |= 5183 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5184 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5185 pa_sc_tile_steering_override |= 5186 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5187 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5188 5189 return pa_sc_tile_steering_override; 5190 } 5191 5192 #define DEFAULT_SH_MEM_BASES (0x6000) 5193 5194 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5195 uint32_t first_vmid, 5196 uint32_t last_vmid) 5197 { 5198 uint32_t data; 5199 uint32_t trap_config_vmid_mask = 0; 5200 int i; 5201 5202 /* Calculate trap config vmid mask */ 5203 for (i = first_vmid; i < last_vmid; i++) 5204 trap_config_vmid_mask |= (1 << i); 5205 5206 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5207 VMID_SEL, trap_config_vmid_mask); 5208 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5209 TRAP_EN, 1); 5210 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5211 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5212 5213 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5214 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5215 } 5216 5217 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5218 { 5219 int i; 5220 uint32_t sh_mem_bases; 5221 5222 /* 5223 * Configure apertures: 5224 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5225 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5226 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5227 */ 5228 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5229 5230 mutex_lock(&adev->srbm_mutex); 5231 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5232 nv_grbm_select(adev, 0, 0, 0, i); 5233 /* CP and shaders */ 5234 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5235 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5236 } 5237 nv_grbm_select(adev, 0, 0, 0, 0); 5238 mutex_unlock(&adev->srbm_mutex); 5239 5240 /* 5241 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5242 * access. These should be enabled by FW for target VMIDs. 5243 */ 5244 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5245 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5246 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5247 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5248 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5249 } 5250 5251 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5252 AMDGPU_NUM_VMID); 5253 } 5254 5255 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5256 { 5257 int vmid; 5258 5259 /* 5260 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5261 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5262 * the driver can enable them for graphics. VMID0 should maintain 5263 * access so that HWS firmware can save/restore entries. 5264 */ 5265 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5266 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5267 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5268 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5269 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5270 } 5271 } 5272 5273 5274 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5275 { 5276 int i, j, k; 5277 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5278 u32 tmp, wgp_active_bitmap = 0; 5279 u32 gcrd_targets_disable_tcp = 0; 5280 u32 utcl_invreq_disable = 0; 5281 /* 5282 * GCRD_TARGETS_DISABLE field contains 5283 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5284 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5285 */ 5286 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5287 2 * max_wgp_per_sh + /* TCP */ 5288 max_wgp_per_sh + /* SQC */ 5289 4); /* GL1C */ 5290 /* 5291 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5292 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5293 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5294 */ 5295 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5296 2 * max_wgp_per_sh + /* TCP */ 5297 2 * max_wgp_per_sh + /* SQC */ 5298 4 + /* RMI */ 5299 1); /* SQG */ 5300 5301 mutex_lock(&adev->grbm_idx_mutex); 5302 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5303 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5304 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5305 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5306 /* 5307 * Set corresponding TCP bits for the inactive WGPs in 5308 * GCRD_SA_TARGETS_DISABLE 5309 */ 5310 gcrd_targets_disable_tcp = 0; 5311 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5312 utcl_invreq_disable = 0; 5313 5314 for (k = 0; k < max_wgp_per_sh; k++) { 5315 if (!(wgp_active_bitmap & (1 << k))) { 5316 gcrd_targets_disable_tcp |= 3 << (2 * k); 5317 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5318 utcl_invreq_disable |= (3 << (2 * k)) | 5319 (3 << (2 * (max_wgp_per_sh + k))); 5320 } 5321 } 5322 5323 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5324 /* only override TCP & SQC bits */ 5325 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5326 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5327 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5328 5329 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5330 /* only override TCP & SQC bits */ 5331 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5332 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5333 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5334 } 5335 } 5336 5337 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5338 mutex_unlock(&adev->grbm_idx_mutex); 5339 } 5340 5341 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5342 { 5343 /* TCCs are global (not instanced). */ 5344 uint32_t tcc_disable; 5345 5346 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5347 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5348 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5349 } else { 5350 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5351 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5352 } 5353 5354 adev->gfx.config.tcc_disabled_mask = 5355 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5356 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5357 } 5358 5359 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5360 { 5361 u32 tmp; 5362 int i; 5363 5364 if (!amdgpu_sriov_vf(adev)) 5365 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5366 5367 gfx_v10_0_setup_rb(adev); 5368 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5369 gfx_v10_0_get_tcc_info(adev); 5370 adev->gfx.config.pa_sc_tile_steering_override = 5371 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5372 5373 /* XXX SH_MEM regs */ 5374 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5375 mutex_lock(&adev->srbm_mutex); 5376 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5377 nv_grbm_select(adev, 0, 0, 0, i); 5378 /* CP and shaders */ 5379 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5380 if (i != 0) { 5381 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5382 (adev->gmc.private_aperture_start >> 48)); 5383 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5384 (adev->gmc.shared_aperture_start >> 48)); 5385 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5386 } 5387 } 5388 nv_grbm_select(adev, 0, 0, 0, 0); 5389 5390 mutex_unlock(&adev->srbm_mutex); 5391 5392 gfx_v10_0_init_compute_vmid(adev); 5393 gfx_v10_0_init_gds_vmid(adev); 5394 5395 } 5396 5397 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5398 int me, int pipe) 5399 { 5400 if (me != 0) 5401 return 0; 5402 5403 switch (pipe) { 5404 case 0: 5405 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5406 case 1: 5407 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5408 default: 5409 return 0; 5410 } 5411 } 5412 5413 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5414 int me, int pipe) 5415 { 5416 /* 5417 * amdgpu controls only the first MEC. That's why this function only 5418 * handles the setting of interrupts for this specific MEC. All other 5419 * pipes' interrupts are set by amdkfd. 5420 */ 5421 if (me != 1) 5422 return 0; 5423 5424 switch (pipe) { 5425 case 0: 5426 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5427 case 1: 5428 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5429 case 2: 5430 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5431 case 3: 5432 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5433 default: 5434 return 0; 5435 } 5436 } 5437 5438 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5439 bool enable) 5440 { 5441 u32 tmp, cp_int_cntl_reg; 5442 int i, j; 5443 5444 if (amdgpu_sriov_vf(adev)) 5445 return; 5446 5447 for (i = 0; i < adev->gfx.me.num_me; i++) { 5448 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5449 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5450 5451 if (cp_int_cntl_reg) { 5452 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5453 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5454 enable ? 1 : 0); 5455 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5456 enable ? 1 : 0); 5457 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5458 enable ? 1 : 0); 5459 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5460 enable ? 1 : 0); 5461 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5462 } 5463 } 5464 } 5465 } 5466 5467 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5468 { 5469 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5470 5471 /* csib */ 5472 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5473 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5474 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5475 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5476 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5477 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5478 } else { 5479 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5480 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5481 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5482 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5483 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5484 } 5485 return 0; 5486 } 5487 5488 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5489 { 5490 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5491 5492 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5493 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5494 } 5495 5496 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5497 { 5498 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5499 udelay(50); 5500 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5501 udelay(50); 5502 } 5503 5504 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5505 bool enable) 5506 { 5507 uint32_t rlc_pg_cntl; 5508 5509 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5510 5511 if (!enable) { 5512 /* RLC_PG_CNTL[23] = 0 (default) 5513 * RLC will wait for handshake acks with SMU 5514 * GFXOFF will be enabled 5515 * RLC_PG_CNTL[23] = 1 5516 * RLC will not issue any message to SMU 5517 * hence no handshake between SMU & RLC 5518 * GFXOFF will be disabled 5519 */ 5520 rlc_pg_cntl |= 0x800000; 5521 } else 5522 rlc_pg_cntl &= ~0x800000; 5523 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5524 } 5525 5526 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5527 { 5528 /* 5529 * TODO: enable rlc & smu handshake until smu 5530 * and gfxoff feature works as expected 5531 */ 5532 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5533 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5534 5535 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5536 udelay(50); 5537 } 5538 5539 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5540 { 5541 uint32_t tmp; 5542 5543 /* enable Save Restore Machine */ 5544 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5545 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5546 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5547 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5548 } 5549 5550 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5551 { 5552 const struct rlc_firmware_header_v2_0 *hdr; 5553 const __le32 *fw_data; 5554 unsigned int i, fw_size; 5555 5556 if (!adev->gfx.rlc_fw) 5557 return -EINVAL; 5558 5559 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5560 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5561 5562 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5563 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5564 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5565 5566 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5567 RLCG_UCODE_LOADING_START_ADDRESS); 5568 5569 for (i = 0; i < fw_size; i++) 5570 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5571 le32_to_cpup(fw_data++)); 5572 5573 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5574 5575 return 0; 5576 } 5577 5578 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5579 { 5580 int r; 5581 5582 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5583 adev->psp.autoload_supported) { 5584 5585 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5586 if (r) 5587 return r; 5588 5589 gfx_v10_0_init_csb(adev); 5590 5591 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5592 5593 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5594 gfx_v10_0_rlc_enable_srm(adev); 5595 } else { 5596 if (amdgpu_sriov_vf(adev)) { 5597 gfx_v10_0_init_csb(adev); 5598 return 0; 5599 } 5600 5601 adev->gfx.rlc.funcs->stop(adev); 5602 5603 /* disable CG */ 5604 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5605 5606 /* disable PG */ 5607 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5608 5609 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5610 /* legacy rlc firmware loading */ 5611 r = gfx_v10_0_rlc_load_microcode(adev); 5612 if (r) 5613 return r; 5614 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5615 /* rlc backdoor autoload firmware */ 5616 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5617 if (r) 5618 return r; 5619 } 5620 5621 gfx_v10_0_init_csb(adev); 5622 5623 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5624 5625 adev->gfx.rlc.funcs->start(adev); 5626 5627 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5628 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5629 if (r) 5630 return r; 5631 } 5632 } 5633 5634 return 0; 5635 } 5636 5637 static struct { 5638 FIRMWARE_ID id; 5639 unsigned int offset; 5640 unsigned int size; 5641 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5642 5643 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5644 { 5645 int ret; 5646 RLC_TABLE_OF_CONTENT *rlc_toc; 5647 5648 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5649 AMDGPU_GEM_DOMAIN_GTT, 5650 &adev->gfx.rlc.rlc_toc_bo, 5651 &adev->gfx.rlc.rlc_toc_gpu_addr, 5652 (void **)&adev->gfx.rlc.rlc_toc_buf); 5653 if (ret) { 5654 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5655 return ret; 5656 } 5657 5658 /* Copy toc from psp sos fw to rlc toc buffer */ 5659 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5660 5661 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5662 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5663 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5664 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5665 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5666 /* Offset needs 4KB alignment */ 5667 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5668 } 5669 5670 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5671 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5672 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5673 5674 rlc_toc++; 5675 } 5676 5677 return 0; 5678 } 5679 5680 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5681 { 5682 uint32_t total_size = 0; 5683 FIRMWARE_ID id; 5684 int ret; 5685 5686 ret = gfx_v10_0_parse_rlc_toc(adev); 5687 if (ret) { 5688 dev_err(adev->dev, "failed to parse rlc toc\n"); 5689 return 0; 5690 } 5691 5692 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5693 total_size += rlc_autoload_info[id].size; 5694 5695 /* In case the offset in rlc toc ucode is aligned */ 5696 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5697 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5698 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5699 5700 return total_size; 5701 } 5702 5703 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5704 { 5705 int r; 5706 uint32_t total_size; 5707 5708 total_size = gfx_v10_0_calc_toc_total_size(adev); 5709 5710 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5711 AMDGPU_GEM_DOMAIN_GTT, 5712 &adev->gfx.rlc.rlc_autoload_bo, 5713 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5714 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5715 if (r) { 5716 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5717 return r; 5718 } 5719 5720 return 0; 5721 } 5722 5723 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5724 { 5725 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5726 &adev->gfx.rlc.rlc_toc_gpu_addr, 5727 (void **)&adev->gfx.rlc.rlc_toc_buf); 5728 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5729 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5730 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5731 } 5732 5733 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5734 FIRMWARE_ID id, 5735 const void *fw_data, 5736 uint32_t fw_size) 5737 { 5738 uint32_t toc_offset; 5739 uint32_t toc_fw_size; 5740 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5741 5742 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5743 return; 5744 5745 toc_offset = rlc_autoload_info[id].offset; 5746 toc_fw_size = rlc_autoload_info[id].size; 5747 5748 if (fw_size == 0) 5749 fw_size = toc_fw_size; 5750 5751 if (fw_size > toc_fw_size) 5752 fw_size = toc_fw_size; 5753 5754 memcpy(ptr + toc_offset, fw_data, fw_size); 5755 5756 if (fw_size < toc_fw_size) 5757 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5758 } 5759 5760 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5761 { 5762 void *data; 5763 uint32_t size; 5764 5765 data = adev->gfx.rlc.rlc_toc_buf; 5766 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5767 5768 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5769 FIRMWARE_ID_RLC_TOC, 5770 data, size); 5771 } 5772 5773 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5774 { 5775 const __le32 *fw_data; 5776 uint32_t fw_size; 5777 const struct gfx_firmware_header_v1_0 *cp_hdr; 5778 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5779 5780 /* pfp ucode */ 5781 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5782 adev->gfx.pfp_fw->data; 5783 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5784 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5785 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5786 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5787 FIRMWARE_ID_CP_PFP, 5788 fw_data, fw_size); 5789 5790 /* ce ucode */ 5791 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5792 adev->gfx.ce_fw->data; 5793 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5794 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5795 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5796 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5797 FIRMWARE_ID_CP_CE, 5798 fw_data, fw_size); 5799 5800 /* me ucode */ 5801 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5802 adev->gfx.me_fw->data; 5803 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5804 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5805 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5806 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5807 FIRMWARE_ID_CP_ME, 5808 fw_data, fw_size); 5809 5810 /* rlc ucode */ 5811 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5812 adev->gfx.rlc_fw->data; 5813 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5814 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5815 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5816 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5817 FIRMWARE_ID_RLC_G_UCODE, 5818 fw_data, fw_size); 5819 5820 /* mec1 ucode */ 5821 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5822 adev->gfx.mec_fw->data; 5823 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5824 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5825 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5826 cp_hdr->jt_size * 4; 5827 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5828 FIRMWARE_ID_CP_MEC, 5829 fw_data, fw_size); 5830 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5831 } 5832 5833 /* Temporarily put sdma part here */ 5834 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5835 { 5836 const __le32 *fw_data; 5837 uint32_t fw_size; 5838 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5839 int i; 5840 5841 for (i = 0; i < adev->sdma.num_instances; i++) { 5842 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5843 adev->sdma.instance[i].fw->data; 5844 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5845 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5846 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5847 5848 if (i == 0) { 5849 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5850 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5851 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5852 FIRMWARE_ID_SDMA0_JT, 5853 (uint32_t *)fw_data + 5854 sdma_hdr->jt_offset, 5855 sdma_hdr->jt_size * 4); 5856 } else if (i == 1) { 5857 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5858 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5859 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5860 FIRMWARE_ID_SDMA1_JT, 5861 (uint32_t *)fw_data + 5862 sdma_hdr->jt_offset, 5863 sdma_hdr->jt_size * 4); 5864 } 5865 } 5866 } 5867 5868 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5869 { 5870 uint32_t rlc_g_offset, rlc_g_size, tmp; 5871 uint64_t gpu_addr; 5872 5873 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5874 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5875 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5876 5877 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5878 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5879 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5880 5881 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5882 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5883 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5884 5885 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5886 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5887 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5888 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5889 return -EINVAL; 5890 } 5891 5892 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5893 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5894 DRM_ERROR("RLC ROM should halt itself\n"); 5895 return -EINVAL; 5896 } 5897 5898 return 0; 5899 } 5900 5901 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5902 { 5903 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5904 uint32_t tmp; 5905 int i; 5906 uint64_t addr; 5907 5908 /* Trigger an invalidation of the L1 instruction caches */ 5909 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5910 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5911 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5912 5913 /* Wait for invalidation complete */ 5914 for (i = 0; i < usec_timeout; i++) { 5915 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5916 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5917 INVALIDATE_CACHE_COMPLETE)) 5918 break; 5919 udelay(1); 5920 } 5921 5922 if (i >= usec_timeout) { 5923 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5924 return -EINVAL; 5925 } 5926 5927 /* Program me ucode address into intruction cache address register */ 5928 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5929 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5930 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5931 lower_32_bits(addr) & 0xFFFFF000); 5932 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5933 upper_32_bits(addr)); 5934 5935 return 0; 5936 } 5937 5938 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5939 { 5940 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5941 uint32_t tmp; 5942 int i; 5943 uint64_t addr; 5944 5945 /* Trigger an invalidation of the L1 instruction caches */ 5946 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5947 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5948 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5949 5950 /* Wait for invalidation complete */ 5951 for (i = 0; i < usec_timeout; i++) { 5952 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5953 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5954 INVALIDATE_CACHE_COMPLETE)) 5955 break; 5956 udelay(1); 5957 } 5958 5959 if (i >= usec_timeout) { 5960 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5961 return -EINVAL; 5962 } 5963 5964 /* Program ce ucode address into intruction cache address register */ 5965 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5966 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5967 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5968 lower_32_bits(addr) & 0xFFFFF000); 5969 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5970 upper_32_bits(addr)); 5971 5972 return 0; 5973 } 5974 5975 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5976 { 5977 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5978 uint32_t tmp; 5979 int i; 5980 uint64_t addr; 5981 5982 /* Trigger an invalidation of the L1 instruction caches */ 5983 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5984 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5985 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5986 5987 /* Wait for invalidation complete */ 5988 for (i = 0; i < usec_timeout; i++) { 5989 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5990 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5991 INVALIDATE_CACHE_COMPLETE)) 5992 break; 5993 udelay(1); 5994 } 5995 5996 if (i >= usec_timeout) { 5997 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5998 return -EINVAL; 5999 } 6000 6001 /* Program pfp ucode address into intruction cache address register */ 6002 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 6003 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 6004 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6005 lower_32_bits(addr) & 0xFFFFF000); 6006 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6007 upper_32_bits(addr)); 6008 6009 return 0; 6010 } 6011 6012 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 6013 { 6014 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6015 uint32_t tmp; 6016 int i; 6017 uint64_t addr; 6018 6019 /* Trigger an invalidation of the L1 instruction caches */ 6020 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6021 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6022 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6023 6024 /* Wait for invalidation complete */ 6025 for (i = 0; i < usec_timeout; i++) { 6026 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6027 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6028 INVALIDATE_CACHE_COMPLETE)) 6029 break; 6030 udelay(1); 6031 } 6032 6033 if (i >= usec_timeout) { 6034 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6035 return -EINVAL; 6036 } 6037 6038 /* Program mec1 ucode address into intruction cache address register */ 6039 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 6040 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 6041 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 6042 lower_32_bits(addr) & 0xFFFFF000); 6043 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6044 upper_32_bits(addr)); 6045 6046 return 0; 6047 } 6048 6049 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 6050 { 6051 uint32_t cp_status; 6052 uint32_t bootload_status; 6053 int i, r; 6054 6055 for (i = 0; i < adev->usec_timeout; i++) { 6056 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 6057 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 6058 if ((cp_status == 0) && 6059 (REG_GET_FIELD(bootload_status, 6060 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 6061 break; 6062 } 6063 udelay(1); 6064 } 6065 6066 if (i >= adev->usec_timeout) { 6067 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 6068 return -ETIMEDOUT; 6069 } 6070 6071 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 6072 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 6073 if (r) 6074 return r; 6075 6076 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 6077 if (r) 6078 return r; 6079 6080 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 6081 if (r) 6082 return r; 6083 6084 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 6085 if (r) 6086 return r; 6087 } 6088 6089 return 0; 6090 } 6091 6092 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 6093 { 6094 int i; 6095 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 6096 6097 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 6098 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 6099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 6100 6101 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 6102 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 6103 else 6104 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 6105 6106 if (amdgpu_in_reset(adev) && !enable) 6107 return 0; 6108 6109 for (i = 0; i < adev->usec_timeout; i++) { 6110 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 6111 break; 6112 udelay(1); 6113 } 6114 6115 if (i >= adev->usec_timeout) 6116 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 6117 6118 return 0; 6119 } 6120 6121 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 6122 { 6123 int r; 6124 const struct gfx_firmware_header_v1_0 *pfp_hdr; 6125 const __le32 *fw_data; 6126 unsigned int i, fw_size; 6127 uint32_t tmp; 6128 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6129 6130 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 6131 adev->gfx.pfp_fw->data; 6132 6133 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 6134 6135 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 6136 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 6137 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 6138 6139 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 6140 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6141 &adev->gfx.pfp.pfp_fw_obj, 6142 &adev->gfx.pfp.pfp_fw_gpu_addr, 6143 (void **)&adev->gfx.pfp.pfp_fw_ptr); 6144 if (r) { 6145 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 6146 gfx_v10_0_pfp_fini(adev); 6147 return r; 6148 } 6149 6150 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6151 6152 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6153 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6154 6155 /* Trigger an invalidation of the L1 instruction caches */ 6156 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6157 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6158 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6159 6160 /* Wait for invalidation complete */ 6161 for (i = 0; i < usec_timeout; i++) { 6162 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6163 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6164 INVALIDATE_CACHE_COMPLETE)) 6165 break; 6166 udelay(1); 6167 } 6168 6169 if (i >= usec_timeout) { 6170 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6171 return -EINVAL; 6172 } 6173 6174 if (amdgpu_emu_mode == 1) 6175 adev->hdp.funcs->flush_hdp(adev, NULL); 6176 6177 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6178 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6179 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6180 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6181 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6182 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6183 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6184 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6185 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6186 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6187 6188 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6189 6190 for (i = 0; i < pfp_hdr->jt_size; i++) 6191 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6192 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6193 6194 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6195 6196 return 0; 6197 } 6198 6199 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6200 { 6201 int r; 6202 const struct gfx_firmware_header_v1_0 *ce_hdr; 6203 const __le32 *fw_data; 6204 unsigned int i, fw_size; 6205 uint32_t tmp; 6206 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6207 6208 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6209 adev->gfx.ce_fw->data; 6210 6211 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6212 6213 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6214 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6215 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6216 6217 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6218 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6219 &adev->gfx.ce.ce_fw_obj, 6220 &adev->gfx.ce.ce_fw_gpu_addr, 6221 (void **)&adev->gfx.ce.ce_fw_ptr); 6222 if (r) { 6223 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6224 gfx_v10_0_ce_fini(adev); 6225 return r; 6226 } 6227 6228 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6229 6230 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6231 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6232 6233 /* Trigger an invalidation of the L1 instruction caches */ 6234 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6235 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6236 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6237 6238 /* Wait for invalidation complete */ 6239 for (i = 0; i < usec_timeout; i++) { 6240 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6241 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6242 INVALIDATE_CACHE_COMPLETE)) 6243 break; 6244 udelay(1); 6245 } 6246 6247 if (i >= usec_timeout) { 6248 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6249 return -EINVAL; 6250 } 6251 6252 if (amdgpu_emu_mode == 1) 6253 adev->hdp.funcs->flush_hdp(adev, NULL); 6254 6255 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6256 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6257 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6258 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6259 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6260 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6261 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6262 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6263 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6264 6265 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6266 6267 for (i = 0; i < ce_hdr->jt_size; i++) 6268 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6269 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6270 6271 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6272 6273 return 0; 6274 } 6275 6276 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6277 { 6278 int r; 6279 const struct gfx_firmware_header_v1_0 *me_hdr; 6280 const __le32 *fw_data; 6281 unsigned int i, fw_size; 6282 uint32_t tmp; 6283 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6284 6285 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6286 adev->gfx.me_fw->data; 6287 6288 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6289 6290 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6291 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6292 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6293 6294 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6295 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6296 &adev->gfx.me.me_fw_obj, 6297 &adev->gfx.me.me_fw_gpu_addr, 6298 (void **)&adev->gfx.me.me_fw_ptr); 6299 if (r) { 6300 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6301 gfx_v10_0_me_fini(adev); 6302 return r; 6303 } 6304 6305 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6306 6307 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6308 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6309 6310 /* Trigger an invalidation of the L1 instruction caches */ 6311 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6312 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6313 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6314 6315 /* Wait for invalidation complete */ 6316 for (i = 0; i < usec_timeout; i++) { 6317 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6318 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6319 INVALIDATE_CACHE_COMPLETE)) 6320 break; 6321 udelay(1); 6322 } 6323 6324 if (i >= usec_timeout) { 6325 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6326 return -EINVAL; 6327 } 6328 6329 if (amdgpu_emu_mode == 1) 6330 adev->hdp.funcs->flush_hdp(adev, NULL); 6331 6332 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6333 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6334 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6335 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6336 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6337 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6338 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6339 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6340 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6341 6342 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6343 6344 for (i = 0; i < me_hdr->jt_size; i++) 6345 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6346 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6347 6348 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6349 6350 return 0; 6351 } 6352 6353 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6354 { 6355 int r; 6356 6357 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6358 return -EINVAL; 6359 6360 gfx_v10_0_cp_gfx_enable(adev, false); 6361 6362 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6363 if (r) { 6364 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6365 return r; 6366 } 6367 6368 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6369 if (r) { 6370 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6371 return r; 6372 } 6373 6374 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6375 if (r) { 6376 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6377 return r; 6378 } 6379 6380 return 0; 6381 } 6382 6383 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6384 { 6385 struct amdgpu_ring *ring; 6386 const struct cs_section_def *sect = NULL; 6387 const struct cs_extent_def *ext = NULL; 6388 int r, i; 6389 int ctx_reg_offset; 6390 6391 /* init the CP */ 6392 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6393 adev->gfx.config.max_hw_contexts - 1); 6394 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6395 6396 gfx_v10_0_cp_gfx_enable(adev, true); 6397 6398 ring = &adev->gfx.gfx_ring[0]; 6399 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6400 if (r) { 6401 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6402 return r; 6403 } 6404 6405 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6406 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6407 6408 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6409 amdgpu_ring_write(ring, 0x80000000); 6410 amdgpu_ring_write(ring, 0x80000000); 6411 6412 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6413 for (ext = sect->section; ext->extent != NULL; ++ext) { 6414 if (sect->id == SECT_CONTEXT) { 6415 amdgpu_ring_write(ring, 6416 PACKET3(PACKET3_SET_CONTEXT_REG, 6417 ext->reg_count)); 6418 amdgpu_ring_write(ring, ext->reg_index - 6419 PACKET3_SET_CONTEXT_REG_START); 6420 for (i = 0; i < ext->reg_count; i++) 6421 amdgpu_ring_write(ring, ext->extent[i]); 6422 } 6423 } 6424 } 6425 6426 ctx_reg_offset = 6427 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6428 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6429 amdgpu_ring_write(ring, ctx_reg_offset); 6430 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6431 6432 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6433 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6434 6435 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6436 amdgpu_ring_write(ring, 0); 6437 6438 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6439 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6440 amdgpu_ring_write(ring, 0x8000); 6441 amdgpu_ring_write(ring, 0x8000); 6442 6443 amdgpu_ring_commit(ring); 6444 6445 /* submit cs packet to copy state 0 to next available state */ 6446 if (adev->gfx.num_gfx_rings > 1) { 6447 /* maximum supported gfx ring is 2 */ 6448 ring = &adev->gfx.gfx_ring[1]; 6449 r = amdgpu_ring_alloc(ring, 2); 6450 if (r) { 6451 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6452 return r; 6453 } 6454 6455 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6456 amdgpu_ring_write(ring, 0); 6457 6458 amdgpu_ring_commit(ring); 6459 } 6460 return 0; 6461 } 6462 6463 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6464 CP_PIPE_ID pipe) 6465 { 6466 u32 tmp; 6467 6468 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6469 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6470 6471 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6472 } 6473 6474 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6475 struct amdgpu_ring *ring) 6476 { 6477 u32 tmp; 6478 6479 if (!amdgpu_async_gfx_ring) { 6480 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6481 if (ring->use_doorbell) { 6482 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6483 DOORBELL_OFFSET, ring->doorbell_index); 6484 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6485 DOORBELL_EN, 1); 6486 } else { 6487 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6488 DOORBELL_EN, 0); 6489 } 6490 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6491 } 6492 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6493 case IP_VERSION(10, 3, 0): 6494 case IP_VERSION(10, 3, 2): 6495 case IP_VERSION(10, 3, 1): 6496 case IP_VERSION(10, 3, 4): 6497 case IP_VERSION(10, 3, 5): 6498 case IP_VERSION(10, 3, 6): 6499 case IP_VERSION(10, 3, 3): 6500 case IP_VERSION(10, 3, 7): 6501 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6502 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6503 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6504 6505 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6506 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6507 break; 6508 default: 6509 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6510 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6511 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6512 6513 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6514 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6515 break; 6516 } 6517 } 6518 6519 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6520 { 6521 struct amdgpu_ring *ring; 6522 u32 tmp; 6523 u32 rb_bufsz; 6524 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6525 6526 /* Set the write pointer delay */ 6527 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6528 6529 /* set the RB to use vmid 0 */ 6530 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6531 6532 /* Init gfx ring 0 for pipe 0 */ 6533 mutex_lock(&adev->srbm_mutex); 6534 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6535 6536 /* Set ring buffer size */ 6537 ring = &adev->gfx.gfx_ring[0]; 6538 rb_bufsz = order_base_2(ring->ring_size / 8); 6539 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6540 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6541 #ifdef __BIG_ENDIAN 6542 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6543 #endif 6544 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6545 6546 /* Initialize the ring buffer's write pointers */ 6547 ring->wptr = 0; 6548 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6549 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6550 6551 /* set the wb address whether it's enabled or not */ 6552 rptr_addr = ring->rptr_gpu_addr; 6553 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6554 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6555 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6556 6557 wptr_gpu_addr = ring->wptr_gpu_addr; 6558 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6559 lower_32_bits(wptr_gpu_addr)); 6560 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6561 upper_32_bits(wptr_gpu_addr)); 6562 6563 mdelay(1); 6564 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6565 6566 rb_addr = ring->gpu_addr >> 8; 6567 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6568 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6569 6570 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6571 6572 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6573 mutex_unlock(&adev->srbm_mutex); 6574 6575 /* Init gfx ring 1 for pipe 1 */ 6576 if (adev->gfx.num_gfx_rings > 1) { 6577 mutex_lock(&adev->srbm_mutex); 6578 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6579 /* maximum supported gfx ring is 2 */ 6580 ring = &adev->gfx.gfx_ring[1]; 6581 rb_bufsz = order_base_2(ring->ring_size / 8); 6582 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6583 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6584 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6585 /* Initialize the ring buffer's write pointers */ 6586 ring->wptr = 0; 6587 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6588 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6589 /* Set the wb address whether it's enabled or not */ 6590 rptr_addr = ring->rptr_gpu_addr; 6591 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6592 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6593 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6594 wptr_gpu_addr = ring->wptr_gpu_addr; 6595 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6596 lower_32_bits(wptr_gpu_addr)); 6597 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6598 upper_32_bits(wptr_gpu_addr)); 6599 6600 mdelay(1); 6601 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6602 6603 rb_addr = ring->gpu_addr >> 8; 6604 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6605 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6606 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6607 6608 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6609 mutex_unlock(&adev->srbm_mutex); 6610 } 6611 /* Switch to pipe 0 */ 6612 mutex_lock(&adev->srbm_mutex); 6613 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6614 mutex_unlock(&adev->srbm_mutex); 6615 6616 /* start the ring */ 6617 gfx_v10_0_cp_gfx_start(adev); 6618 6619 return 0; 6620 } 6621 6622 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6623 { 6624 if (enable) { 6625 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6626 case IP_VERSION(10, 3, 0): 6627 case IP_VERSION(10, 3, 2): 6628 case IP_VERSION(10, 3, 1): 6629 case IP_VERSION(10, 3, 4): 6630 case IP_VERSION(10, 3, 5): 6631 case IP_VERSION(10, 3, 6): 6632 case IP_VERSION(10, 3, 3): 6633 case IP_VERSION(10, 3, 7): 6634 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6635 break; 6636 default: 6637 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6638 break; 6639 } 6640 } else { 6641 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6642 case IP_VERSION(10, 3, 0): 6643 case IP_VERSION(10, 3, 2): 6644 case IP_VERSION(10, 3, 1): 6645 case IP_VERSION(10, 3, 4): 6646 case IP_VERSION(10, 3, 5): 6647 case IP_VERSION(10, 3, 6): 6648 case IP_VERSION(10, 3, 3): 6649 case IP_VERSION(10, 3, 7): 6650 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6651 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6652 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6653 break; 6654 default: 6655 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6656 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6657 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6658 break; 6659 } 6660 adev->gfx.kiq[0].ring.sched.ready = false; 6661 } 6662 udelay(50); 6663 } 6664 6665 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6666 { 6667 const struct gfx_firmware_header_v1_0 *mec_hdr; 6668 const __le32 *fw_data; 6669 unsigned int i; 6670 u32 tmp; 6671 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6672 6673 if (!adev->gfx.mec_fw) 6674 return -EINVAL; 6675 6676 gfx_v10_0_cp_compute_enable(adev, false); 6677 6678 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6679 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6680 6681 fw_data = (const __le32 *) 6682 (adev->gfx.mec_fw->data + 6683 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6684 6685 /* Trigger an invalidation of the L1 instruction caches */ 6686 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6687 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6688 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6689 6690 /* Wait for invalidation complete */ 6691 for (i = 0; i < usec_timeout; i++) { 6692 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6693 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6694 INVALIDATE_CACHE_COMPLETE)) 6695 break; 6696 udelay(1); 6697 } 6698 6699 if (i >= usec_timeout) { 6700 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6701 return -EINVAL; 6702 } 6703 6704 if (amdgpu_emu_mode == 1) 6705 adev->hdp.funcs->flush_hdp(adev, NULL); 6706 6707 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6708 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6709 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6710 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6711 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6712 6713 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6714 0xFFFFF000); 6715 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6716 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6717 6718 /* MEC1 */ 6719 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6720 6721 for (i = 0; i < mec_hdr->jt_size; i++) 6722 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6723 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6724 6725 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6726 6727 /* 6728 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6729 * different microcode than MEC1. 6730 */ 6731 6732 return 0; 6733 } 6734 6735 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6736 { 6737 uint32_t tmp; 6738 struct amdgpu_device *adev = ring->adev; 6739 6740 /* tell RLC which is KIQ queue */ 6741 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6742 case IP_VERSION(10, 3, 0): 6743 case IP_VERSION(10, 3, 2): 6744 case IP_VERSION(10, 3, 1): 6745 case IP_VERSION(10, 3, 4): 6746 case IP_VERSION(10, 3, 5): 6747 case IP_VERSION(10, 3, 6): 6748 case IP_VERSION(10, 3, 3): 6749 case IP_VERSION(10, 3, 7): 6750 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6751 tmp &= 0xffffff00; 6752 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6753 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80); 6754 break; 6755 default: 6756 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6757 tmp &= 0xffffff00; 6758 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6759 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80); 6760 break; 6761 } 6762 } 6763 6764 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6765 struct v10_gfx_mqd *mqd, 6766 struct amdgpu_mqd_prop *prop) 6767 { 6768 bool priority = 0; 6769 u32 tmp; 6770 6771 /* set up default queue priority level 6772 * 0x0 = low priority, 0x1 = high priority 6773 */ 6774 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6775 priority = 1; 6776 6777 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6778 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6779 mqd->cp_gfx_hqd_queue_priority = tmp; 6780 } 6781 6782 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6783 struct amdgpu_mqd_prop *prop) 6784 { 6785 struct v10_gfx_mqd *mqd = m; 6786 uint64_t hqd_gpu_addr, wb_gpu_addr; 6787 uint32_t tmp; 6788 uint32_t rb_bufsz; 6789 6790 /* set up gfx hqd wptr */ 6791 mqd->cp_gfx_hqd_wptr = 0; 6792 mqd->cp_gfx_hqd_wptr_hi = 0; 6793 6794 /* set the pointer to the MQD */ 6795 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6796 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6797 6798 /* set up mqd control */ 6799 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6800 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6801 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6802 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6803 mqd->cp_gfx_mqd_control = tmp; 6804 6805 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6806 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6807 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6808 mqd->cp_gfx_hqd_vmid = 0; 6809 6810 /* set up gfx queue priority */ 6811 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6812 6813 /* set up time quantum */ 6814 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6815 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6816 mqd->cp_gfx_hqd_quantum = tmp; 6817 6818 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6819 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6820 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6821 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6822 6823 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6824 wb_gpu_addr = prop->rptr_gpu_addr; 6825 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6826 mqd->cp_gfx_hqd_rptr_addr_hi = 6827 upper_32_bits(wb_gpu_addr) & 0xffff; 6828 6829 /* set up rb_wptr_poll addr */ 6830 wb_gpu_addr = prop->wptr_gpu_addr; 6831 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6832 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6833 6834 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6835 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6836 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6837 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6838 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6839 #ifdef __BIG_ENDIAN 6840 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6841 #endif 6842 mqd->cp_gfx_hqd_cntl = tmp; 6843 6844 /* set up cp_doorbell_control */ 6845 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6846 if (prop->use_doorbell) { 6847 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6848 DOORBELL_OFFSET, prop->doorbell_index); 6849 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6850 DOORBELL_EN, 1); 6851 } else 6852 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6853 DOORBELL_EN, 0); 6854 mqd->cp_rb_doorbell_control = tmp; 6855 6856 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6857 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6858 6859 /* active the queue */ 6860 mqd->cp_gfx_hqd_active = 1; 6861 6862 return 0; 6863 } 6864 6865 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 6866 { 6867 struct amdgpu_device *adev = ring->adev; 6868 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6869 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6870 6871 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 6872 memset((void *)mqd, 0, sizeof(*mqd)); 6873 mutex_lock(&adev->srbm_mutex); 6874 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6875 amdgpu_ring_init_mqd(ring); 6876 6877 /* 6878 * if there are 2 gfx rings, set the lower doorbell 6879 * range of the first ring, otherwise the range of 6880 * the second ring will override the first ring 6881 */ 6882 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6883 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6884 6885 nv_grbm_select(adev, 0, 0, 0, 0); 6886 mutex_unlock(&adev->srbm_mutex); 6887 if (adev->gfx.me.mqd_backup[mqd_idx]) 6888 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6889 } else { 6890 mutex_lock(&adev->srbm_mutex); 6891 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6892 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6893 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6894 6895 nv_grbm_select(adev, 0, 0, 0, 0); 6896 mutex_unlock(&adev->srbm_mutex); 6897 /* restore mqd with the backup copy */ 6898 if (adev->gfx.me.mqd_backup[mqd_idx]) 6899 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6900 /* reset the ring */ 6901 ring->wptr = 0; 6902 *ring->wptr_cpu_addr = 0; 6903 amdgpu_ring_clear_ring(ring); 6904 } 6905 6906 return 0; 6907 } 6908 6909 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6910 { 6911 int r, i; 6912 6913 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6914 r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 6915 if (r) 6916 return r; 6917 } 6918 6919 r = amdgpu_gfx_enable_kgq(adev, 0); 6920 if (r) 6921 return r; 6922 6923 return gfx_v10_0_cp_gfx_start(adev); 6924 } 6925 6926 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6927 struct amdgpu_mqd_prop *prop) 6928 { 6929 struct v10_compute_mqd *mqd = m; 6930 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6931 uint32_t tmp; 6932 6933 mqd->header = 0xC0310800; 6934 mqd->compute_pipelinestat_enable = 0x00000001; 6935 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6936 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6937 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6938 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6939 mqd->compute_misc_reserved = 0x00000003; 6940 6941 eop_base_addr = prop->eop_gpu_addr >> 8; 6942 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6943 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6944 6945 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6946 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6947 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6948 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6949 6950 mqd->cp_hqd_eop_control = tmp; 6951 6952 /* enable doorbell? */ 6953 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6954 6955 if (prop->use_doorbell) { 6956 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6957 DOORBELL_OFFSET, prop->doorbell_index); 6958 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6959 DOORBELL_EN, 1); 6960 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6961 DOORBELL_SOURCE, 0); 6962 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6963 DOORBELL_HIT, 0); 6964 } else { 6965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6966 DOORBELL_EN, 0); 6967 } 6968 6969 mqd->cp_hqd_pq_doorbell_control = tmp; 6970 6971 /* disable the queue if it's active */ 6972 mqd->cp_hqd_dequeue_request = 0; 6973 mqd->cp_hqd_pq_rptr = 0; 6974 mqd->cp_hqd_pq_wptr_lo = 0; 6975 mqd->cp_hqd_pq_wptr_hi = 0; 6976 6977 /* set the pointer to the MQD */ 6978 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6979 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6980 6981 /* set MQD vmid to 0 */ 6982 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6983 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6984 mqd->cp_mqd_control = tmp; 6985 6986 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6987 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6988 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6989 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6990 6991 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6992 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6993 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6994 (order_base_2(prop->queue_size / 4) - 1)); 6995 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6996 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6997 #ifdef __BIG_ENDIAN 6998 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6999 #endif 7000 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 7001 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 7002 prop->allow_tunneling); 7003 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 7004 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 7005 mqd->cp_hqd_pq_control = tmp; 7006 7007 /* set the wb address whether it's enabled or not */ 7008 wb_gpu_addr = prop->rptr_gpu_addr; 7009 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 7010 mqd->cp_hqd_pq_rptr_report_addr_hi = 7011 upper_32_bits(wb_gpu_addr) & 0xffff; 7012 7013 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7014 wb_gpu_addr = prop->wptr_gpu_addr; 7015 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 7016 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 7017 7018 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7019 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 7020 7021 /* set the vmid for the queue */ 7022 mqd->cp_hqd_vmid = 0; 7023 7024 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 7025 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 7026 mqd->cp_hqd_persistent_state = tmp; 7027 7028 /* set MIN_IB_AVAIL_SIZE */ 7029 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 7030 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 7031 mqd->cp_hqd_ib_control = tmp; 7032 7033 /* set static priority for a compute queue/ring */ 7034 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 7035 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 7036 7037 mqd->cp_hqd_active = prop->hqd_active; 7038 7039 return 0; 7040 } 7041 7042 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 7043 { 7044 struct amdgpu_device *adev = ring->adev; 7045 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7046 int j; 7047 7048 /* inactivate the queue */ 7049 if (amdgpu_sriov_vf(adev)) 7050 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 7051 7052 /* disable wptr polling */ 7053 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 7054 7055 /* disable the queue if it's active */ 7056 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7057 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7058 for (j = 0; j < adev->usec_timeout; j++) { 7059 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7060 break; 7061 udelay(1); 7062 } 7063 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7064 mqd->cp_hqd_dequeue_request); 7065 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7066 mqd->cp_hqd_pq_rptr); 7067 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7068 mqd->cp_hqd_pq_wptr_lo); 7069 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7070 mqd->cp_hqd_pq_wptr_hi); 7071 } 7072 7073 /* disable doorbells */ 7074 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 7075 7076 /* write the EOP addr */ 7077 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7078 mqd->cp_hqd_eop_base_addr_lo); 7079 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7080 mqd->cp_hqd_eop_base_addr_hi); 7081 7082 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7083 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7084 mqd->cp_hqd_eop_control); 7085 7086 /* set the pointer to the MQD */ 7087 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7088 mqd->cp_mqd_base_addr_lo); 7089 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7090 mqd->cp_mqd_base_addr_hi); 7091 7092 /* set MQD vmid to 0 */ 7093 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7094 mqd->cp_mqd_control); 7095 7096 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7097 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7098 mqd->cp_hqd_pq_base_lo); 7099 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7100 mqd->cp_hqd_pq_base_hi); 7101 7102 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7103 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7104 mqd->cp_hqd_pq_control); 7105 7106 /* set the wb address whether it's enabled or not */ 7107 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7108 mqd->cp_hqd_pq_rptr_report_addr_lo); 7109 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7110 mqd->cp_hqd_pq_rptr_report_addr_hi); 7111 7112 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7113 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7114 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7115 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7116 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7117 7118 /* enable the doorbell if requested */ 7119 if (ring->use_doorbell) { 7120 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7121 (adev->doorbell_index.kiq * 2) << 2); 7122 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7123 (adev->doorbell_index.userqueue_end * 2) << 2); 7124 } 7125 7126 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7127 mqd->cp_hqd_pq_doorbell_control); 7128 7129 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7130 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7131 mqd->cp_hqd_pq_wptr_lo); 7132 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7133 mqd->cp_hqd_pq_wptr_hi); 7134 7135 /* set the vmid for the queue */ 7136 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7137 7138 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7139 mqd->cp_hqd_persistent_state); 7140 7141 /* activate the queue */ 7142 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7143 mqd->cp_hqd_active); 7144 7145 if (ring->use_doorbell) 7146 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7147 7148 return 0; 7149 } 7150 7151 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7152 { 7153 struct amdgpu_device *adev = ring->adev; 7154 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7155 7156 gfx_v10_0_kiq_setting(ring); 7157 7158 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7159 /* reset MQD to a clean status */ 7160 if (adev->gfx.kiq[0].mqd_backup) 7161 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7162 7163 /* reset ring buffer */ 7164 ring->wptr = 0; 7165 amdgpu_ring_clear_ring(ring); 7166 7167 mutex_lock(&adev->srbm_mutex); 7168 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7169 gfx_v10_0_kiq_init_register(ring); 7170 nv_grbm_select(adev, 0, 0, 0, 0); 7171 mutex_unlock(&adev->srbm_mutex); 7172 } else { 7173 memset((void *)mqd, 0, sizeof(*mqd)); 7174 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7175 amdgpu_ring_clear_ring(ring); 7176 mutex_lock(&adev->srbm_mutex); 7177 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7178 amdgpu_ring_init_mqd(ring); 7179 gfx_v10_0_kiq_init_register(ring); 7180 nv_grbm_select(adev, 0, 0, 0, 0); 7181 mutex_unlock(&adev->srbm_mutex); 7182 7183 if (adev->gfx.kiq[0].mqd_backup) 7184 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7185 } 7186 7187 return 0; 7188 } 7189 7190 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) 7191 { 7192 struct amdgpu_device *adev = ring->adev; 7193 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7194 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7195 7196 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { 7197 memset((void *)mqd, 0, sizeof(*mqd)); 7198 mutex_lock(&adev->srbm_mutex); 7199 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7200 amdgpu_ring_init_mqd(ring); 7201 nv_grbm_select(adev, 0, 0, 0, 0); 7202 mutex_unlock(&adev->srbm_mutex); 7203 7204 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7205 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7206 } else { 7207 /* restore MQD to a clean status */ 7208 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7209 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7210 /* reset ring buffer */ 7211 ring->wptr = 0; 7212 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7213 amdgpu_ring_clear_ring(ring); 7214 } 7215 7216 return 0; 7217 } 7218 7219 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7220 { 7221 gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 7222 return 0; 7223 } 7224 7225 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7226 { 7227 int i, r; 7228 7229 gfx_v10_0_cp_compute_enable(adev, true); 7230 7231 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7232 r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i], 7233 false); 7234 if (r) 7235 return r; 7236 } 7237 7238 return amdgpu_gfx_enable_kcq(adev, 0); 7239 } 7240 7241 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7242 { 7243 int r, i; 7244 struct amdgpu_ring *ring; 7245 7246 if (!(adev->flags & AMD_IS_APU)) 7247 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7248 7249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7250 /* legacy firmware loading */ 7251 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7252 if (r) 7253 return r; 7254 7255 r = gfx_v10_0_cp_compute_load_microcode(adev); 7256 if (r) 7257 return r; 7258 } 7259 7260 r = gfx_v10_0_kiq_resume(adev); 7261 if (r) 7262 return r; 7263 7264 r = gfx_v10_0_kcq_resume(adev); 7265 if (r) 7266 return r; 7267 7268 if (!amdgpu_async_gfx_ring) { 7269 r = gfx_v10_0_cp_gfx_resume(adev); 7270 if (r) 7271 return r; 7272 } else { 7273 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7274 if (r) 7275 return r; 7276 } 7277 7278 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7279 ring = &adev->gfx.gfx_ring[i]; 7280 r = amdgpu_ring_test_helper(ring); 7281 if (r) 7282 return r; 7283 } 7284 7285 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7286 ring = &adev->gfx.compute_ring[i]; 7287 r = amdgpu_ring_test_helper(ring); 7288 if (r) 7289 return r; 7290 } 7291 7292 return 0; 7293 } 7294 7295 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7296 { 7297 gfx_v10_0_cp_gfx_enable(adev, enable); 7298 gfx_v10_0_cp_compute_enable(adev, enable); 7299 } 7300 7301 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7302 { 7303 uint32_t data, pattern = 0xDEADBEEF; 7304 7305 /* 7306 * check if mmVGT_ESGS_RING_SIZE_UMD 7307 * has been remapped to mmVGT_ESGS_RING_SIZE 7308 */ 7309 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7310 case IP_VERSION(10, 3, 0): 7311 case IP_VERSION(10, 3, 2): 7312 case IP_VERSION(10, 3, 4): 7313 case IP_VERSION(10, 3, 5): 7314 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7315 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7316 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7317 7318 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7319 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7320 return true; 7321 } 7322 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7323 break; 7324 case IP_VERSION(10, 3, 1): 7325 case IP_VERSION(10, 3, 3): 7326 case IP_VERSION(10, 3, 6): 7327 case IP_VERSION(10, 3, 7): 7328 return true; 7329 default: 7330 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7331 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7332 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7333 7334 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7335 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7336 return true; 7337 } 7338 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7339 break; 7340 } 7341 7342 return false; 7343 } 7344 7345 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7346 { 7347 uint32_t data; 7348 7349 if (amdgpu_sriov_vf(adev)) 7350 return; 7351 7352 /* 7353 * Initialize cam_index to 0 7354 * index will auto-inc after each data writing 7355 */ 7356 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7357 7358 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7359 case IP_VERSION(10, 3, 0): 7360 case IP_VERSION(10, 3, 2): 7361 case IP_VERSION(10, 3, 1): 7362 case IP_VERSION(10, 3, 4): 7363 case IP_VERSION(10, 3, 5): 7364 case IP_VERSION(10, 3, 6): 7365 case IP_VERSION(10, 3, 3): 7366 case IP_VERSION(10, 3, 7): 7367 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7368 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7369 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7370 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7371 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7372 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7373 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7374 7375 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7376 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7377 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7378 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7379 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7380 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7381 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7382 7383 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7384 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7385 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7386 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7387 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7388 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7389 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7390 7391 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7392 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7393 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7394 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7395 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7396 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7397 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7398 7399 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7400 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7401 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7402 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7403 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7404 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7405 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7406 7407 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7408 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7409 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7410 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7411 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7412 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7413 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7414 7415 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7416 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7417 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7418 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7419 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7420 break; 7421 default: 7422 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7423 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7424 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7425 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7426 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7427 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7428 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7429 7430 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7431 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7432 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7433 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7434 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7435 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7436 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7437 7438 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7439 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7440 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7441 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7442 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7443 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7444 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7445 7446 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7447 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7448 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7449 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7450 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7451 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7452 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7453 7454 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7455 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7456 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7457 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7458 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7459 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7460 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7461 7462 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7463 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7464 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7465 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7466 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7467 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7468 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7469 7470 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7471 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7472 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7473 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7474 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7475 break; 7476 } 7477 7478 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7479 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7480 } 7481 7482 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7483 { 7484 uint32_t data; 7485 7486 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7487 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7488 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7489 7490 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7491 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7492 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7493 } 7494 7495 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 7496 { 7497 int r; 7498 struct amdgpu_device *adev = ip_block->adev; 7499 7500 if (!amdgpu_emu_mode) 7501 gfx_v10_0_init_golden_registers(adev); 7502 7503 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 7504 adev->gfx.cleaner_shader_ptr); 7505 7506 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7507 /** 7508 * For gfx 10, rlc firmware loading relies on smu firmware is 7509 * loaded firstly, so in direct type, it has to load smc ucode 7510 * here before rlc. 7511 */ 7512 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7513 if (r) 7514 return r; 7515 gfx_v10_0_disable_gpa_mode(adev); 7516 } 7517 7518 /* if GRBM CAM not remapped, set up the remapping */ 7519 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7520 gfx_v10_0_setup_grbm_cam_remapping(adev); 7521 7522 gfx_v10_0_constants_init(adev); 7523 7524 r = gfx_v10_0_rlc_resume(adev); 7525 if (r) 7526 return r; 7527 7528 /* 7529 * init golden registers and rlc resume may override some registers, 7530 * reconfig them here 7531 */ 7532 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7533 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7534 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7535 gfx_v10_0_tcp_harvest(adev); 7536 7537 r = gfx_v10_0_cp_resume(adev); 7538 if (r) 7539 return r; 7540 7541 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7542 gfx_v10_3_program_pbb_mode(adev); 7543 7544 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7545 gfx_v10_3_set_power_brake_sequence(adev); 7546 7547 return r; 7548 } 7549 7550 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 7551 { 7552 struct amdgpu_device *adev = ip_block->adev; 7553 7554 cancel_delayed_work_sync(&adev->gfx.idle_work); 7555 7556 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7557 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7558 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7559 7560 /* WA added for Vangogh asic fixing the SMU suspend failure 7561 * It needs to set power gating again during gfxoff control 7562 * otherwise the gfxoff disallowing will be failed to set. 7563 */ 7564 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7565 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 7566 7567 if (!adev->no_hw_access) { 7568 if (amdgpu_async_gfx_ring) { 7569 if (amdgpu_gfx_disable_kgq(adev, 0)) 7570 DRM_ERROR("KGQ disable failed\n"); 7571 } 7572 7573 if (amdgpu_gfx_disable_kcq(adev, 0)) 7574 DRM_ERROR("KCQ disable failed\n"); 7575 } 7576 7577 if (amdgpu_sriov_vf(adev)) { 7578 gfx_v10_0_cp_gfx_enable(adev, false); 7579 /* Remove the steps of clearing KIQ position. 7580 * It causes GFX hang when another Win guest is rendering. 7581 */ 7582 return 0; 7583 } 7584 gfx_v10_0_cp_enable(adev, false); 7585 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7586 7587 return 0; 7588 } 7589 7590 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) 7591 { 7592 return gfx_v10_0_hw_fini(ip_block); 7593 } 7594 7595 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) 7596 { 7597 return gfx_v10_0_hw_init(ip_block); 7598 } 7599 7600 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 7601 { 7602 struct amdgpu_device *adev = ip_block->adev; 7603 7604 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7605 GRBM_STATUS, GUI_ACTIVE)) 7606 return false; 7607 else 7608 return true; 7609 } 7610 7611 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 7612 { 7613 unsigned int i; 7614 u32 tmp; 7615 struct amdgpu_device *adev = ip_block->adev; 7616 7617 for (i = 0; i < adev->usec_timeout; i++) { 7618 /* read MC_STATUS */ 7619 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7620 GRBM_STATUS__GUI_ACTIVE_MASK; 7621 7622 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7623 return 0; 7624 udelay(1); 7625 } 7626 return -ETIMEDOUT; 7627 } 7628 7629 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) 7630 { 7631 u32 grbm_soft_reset = 0; 7632 u32 tmp; 7633 struct amdgpu_device *adev = ip_block->adev; 7634 7635 /* GRBM_STATUS */ 7636 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7637 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7638 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7639 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7640 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7641 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7642 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7643 GRBM_SOFT_RESET, SOFT_RESET_CP, 7644 1); 7645 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7646 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7647 1); 7648 } 7649 7650 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7651 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7652 GRBM_SOFT_RESET, SOFT_RESET_CP, 7653 1); 7654 } 7655 7656 /* GRBM_STATUS2 */ 7657 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7658 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7659 case IP_VERSION(10, 3, 0): 7660 case IP_VERSION(10, 3, 2): 7661 case IP_VERSION(10, 3, 1): 7662 case IP_VERSION(10, 3, 4): 7663 case IP_VERSION(10, 3, 5): 7664 case IP_VERSION(10, 3, 6): 7665 case IP_VERSION(10, 3, 3): 7666 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7667 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7668 GRBM_SOFT_RESET, 7669 SOFT_RESET_RLC, 7670 1); 7671 break; 7672 default: 7673 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7674 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7675 GRBM_SOFT_RESET, 7676 SOFT_RESET_RLC, 7677 1); 7678 break; 7679 } 7680 7681 if (grbm_soft_reset) { 7682 /* stop the rlc */ 7683 gfx_v10_0_rlc_stop(adev); 7684 7685 /* Disable GFX parsing/prefetching */ 7686 gfx_v10_0_cp_gfx_enable(adev, false); 7687 7688 /* Disable MEC parsing/prefetching */ 7689 gfx_v10_0_cp_compute_enable(adev, false); 7690 7691 if (grbm_soft_reset) { 7692 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7693 tmp |= grbm_soft_reset; 7694 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7695 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7696 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7697 7698 udelay(50); 7699 7700 tmp &= ~grbm_soft_reset; 7701 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7702 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7703 } 7704 7705 /* Wait a little for things to settle down */ 7706 udelay(50); 7707 } 7708 return 0; 7709 } 7710 7711 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7712 { 7713 uint64_t clock, clock_lo, clock_hi, hi_check; 7714 7715 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7716 case IP_VERSION(10, 1, 3): 7717 case IP_VERSION(10, 1, 4): 7718 preempt_disable(); 7719 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7720 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7721 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7722 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7723 * roughly every 42 seconds. 7724 */ 7725 if (hi_check != clock_hi) { 7726 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7727 clock_hi = hi_check; 7728 } 7729 preempt_enable(); 7730 clock = clock_lo | (clock_hi << 32ULL); 7731 break; 7732 case IP_VERSION(10, 3, 1): 7733 case IP_VERSION(10, 3, 3): 7734 case IP_VERSION(10, 3, 7): 7735 preempt_disable(); 7736 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7737 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7738 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7739 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7740 * roughly every 42 seconds. 7741 */ 7742 if (hi_check != clock_hi) { 7743 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7744 clock_hi = hi_check; 7745 } 7746 preempt_enable(); 7747 clock = clock_lo | (clock_hi << 32ULL); 7748 break; 7749 case IP_VERSION(10, 3, 6): 7750 preempt_disable(); 7751 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7752 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7753 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7754 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7755 * roughly every 42 seconds. 7756 */ 7757 if (hi_check != clock_hi) { 7758 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7759 clock_hi = hi_check; 7760 } 7761 preempt_enable(); 7762 clock = clock_lo | (clock_hi << 32ULL); 7763 break; 7764 default: 7765 preempt_disable(); 7766 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7767 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7768 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7769 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7770 * roughly every 42 seconds. 7771 */ 7772 if (hi_check != clock_hi) { 7773 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7774 clock_hi = hi_check; 7775 } 7776 preempt_enable(); 7777 clock = clock_lo | (clock_hi << 32ULL); 7778 break; 7779 } 7780 return clock; 7781 } 7782 7783 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7784 uint32_t vmid, 7785 uint32_t gds_base, uint32_t gds_size, 7786 uint32_t gws_base, uint32_t gws_size, 7787 uint32_t oa_base, uint32_t oa_size) 7788 { 7789 struct amdgpu_device *adev = ring->adev; 7790 7791 /* GDS Base */ 7792 gfx_v10_0_write_data_to_reg(ring, 0, false, 7793 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7794 gds_base); 7795 7796 /* GDS Size */ 7797 gfx_v10_0_write_data_to_reg(ring, 0, false, 7798 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7799 gds_size); 7800 7801 /* GWS */ 7802 gfx_v10_0_write_data_to_reg(ring, 0, false, 7803 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7804 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7805 7806 /* OA */ 7807 gfx_v10_0_write_data_to_reg(ring, 0, false, 7808 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7809 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7810 } 7811 7812 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) 7813 { 7814 struct amdgpu_device *adev = ip_block->adev; 7815 7816 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7817 7818 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7819 case IP_VERSION(10, 1, 10): 7820 case IP_VERSION(10, 1, 1): 7821 case IP_VERSION(10, 1, 2): 7822 case IP_VERSION(10, 1, 3): 7823 case IP_VERSION(10, 1, 4): 7824 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7825 break; 7826 case IP_VERSION(10, 3, 0): 7827 case IP_VERSION(10, 3, 2): 7828 case IP_VERSION(10, 3, 1): 7829 case IP_VERSION(10, 3, 4): 7830 case IP_VERSION(10, 3, 5): 7831 case IP_VERSION(10, 3, 6): 7832 case IP_VERSION(10, 3, 3): 7833 case IP_VERSION(10, 3, 7): 7834 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7835 break; 7836 default: 7837 break; 7838 } 7839 7840 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7841 AMDGPU_MAX_COMPUTE_RINGS); 7842 7843 gfx_v10_0_set_kiq_pm4_funcs(adev); 7844 gfx_v10_0_set_ring_funcs(adev); 7845 gfx_v10_0_set_irq_funcs(adev); 7846 gfx_v10_0_set_gds_init(adev); 7847 gfx_v10_0_set_rlc_funcs(adev); 7848 gfx_v10_0_set_mqd_funcs(adev); 7849 7850 /* init rlcg reg access ctrl */ 7851 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7852 7853 return gfx_v10_0_init_microcode(adev); 7854 } 7855 7856 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) 7857 { 7858 struct amdgpu_device *adev = ip_block->adev; 7859 int r; 7860 7861 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7862 if (r) 7863 return r; 7864 7865 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7866 if (r) 7867 return r; 7868 7869 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7870 if (r) 7871 return r; 7872 7873 return 0; 7874 } 7875 7876 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7877 { 7878 uint32_t rlc_cntl; 7879 7880 /* if RLC is not enabled, do nothing */ 7881 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7882 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7883 } 7884 7885 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7886 { 7887 uint32_t data; 7888 unsigned int i; 7889 7890 data = RLC_SAFE_MODE__CMD_MASK; 7891 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7892 7893 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7894 case IP_VERSION(10, 3, 0): 7895 case IP_VERSION(10, 3, 2): 7896 case IP_VERSION(10, 3, 1): 7897 case IP_VERSION(10, 3, 4): 7898 case IP_VERSION(10, 3, 5): 7899 case IP_VERSION(10, 3, 6): 7900 case IP_VERSION(10, 3, 3): 7901 case IP_VERSION(10, 3, 7): 7902 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7903 7904 /* wait for RLC_SAFE_MODE */ 7905 for (i = 0; i < adev->usec_timeout; i++) { 7906 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7907 RLC_SAFE_MODE, CMD)) 7908 break; 7909 udelay(1); 7910 } 7911 break; 7912 default: 7913 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7914 7915 /* wait for RLC_SAFE_MODE */ 7916 for (i = 0; i < adev->usec_timeout; i++) { 7917 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7918 RLC_SAFE_MODE, CMD)) 7919 break; 7920 udelay(1); 7921 } 7922 break; 7923 } 7924 } 7925 7926 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7927 { 7928 uint32_t data; 7929 7930 data = RLC_SAFE_MODE__CMD_MASK; 7931 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7932 case IP_VERSION(10, 3, 0): 7933 case IP_VERSION(10, 3, 2): 7934 case IP_VERSION(10, 3, 1): 7935 case IP_VERSION(10, 3, 4): 7936 case IP_VERSION(10, 3, 5): 7937 case IP_VERSION(10, 3, 6): 7938 case IP_VERSION(10, 3, 3): 7939 case IP_VERSION(10, 3, 7): 7940 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7941 break; 7942 default: 7943 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7944 break; 7945 } 7946 } 7947 7948 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7949 bool enable) 7950 { 7951 uint32_t data, def; 7952 7953 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7954 return; 7955 7956 /* It is disabled by HW by default */ 7957 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7958 /* 0 - Disable some blocks' MGCG */ 7959 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7960 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7961 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7962 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7963 7964 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7965 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7966 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7967 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7968 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7969 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7970 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7971 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7972 7973 if (def != data) 7974 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7975 7976 /* MGLS is a global flag to control all MGLS in GFX */ 7977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7978 /* 2 - RLC memory Light sleep */ 7979 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7980 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7981 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7982 if (def != data) 7983 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7984 } 7985 /* 3 - CP memory Light sleep */ 7986 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7987 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7988 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7989 if (def != data) 7990 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7991 } 7992 } 7993 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7994 /* 1 - MGCG_OVERRIDE */ 7995 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7996 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7997 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7998 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7999 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 8000 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 8001 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 8002 if (def != data) 8003 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8004 8005 /* 2 - disable MGLS in CP */ 8006 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 8007 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 8008 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 8009 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 8010 } 8011 8012 /* 3 - disable MGLS in RLC */ 8013 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 8014 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 8015 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 8016 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 8017 } 8018 8019 } 8020 } 8021 8022 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 8023 bool enable) 8024 { 8025 uint32_t data, def; 8026 8027 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 8028 return; 8029 8030 /* Enable 3D CGCG/CGLS */ 8031 if (enable) { 8032 /* write cmd to clear cgcg/cgls ov */ 8033 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8034 8035 /* unset CGCG override */ 8036 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8037 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 8038 8039 /* update CGCG and CGLS override bits */ 8040 if (def != data) 8041 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8042 8043 /* enable 3Dcgcg FSM(0x0000363f) */ 8044 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8045 data = 0; 8046 8047 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8048 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8049 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8050 8051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8052 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8053 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8054 8055 if (def != data) 8056 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8057 8058 /* set IDLE_POLL_COUNT(0x00900100) */ 8059 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8060 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8061 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8062 if (def != data) 8063 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8064 } else { 8065 /* Disable CGCG/CGLS */ 8066 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8067 8068 /* disable cgcg, cgls should be disabled */ 8069 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8070 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8071 8072 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8073 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8074 8075 /* disable cgcg and cgls in FSM */ 8076 if (def != data) 8077 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8078 } 8079 } 8080 8081 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8082 bool enable) 8083 { 8084 uint32_t def, data; 8085 8086 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8087 return; 8088 8089 if (enable) { 8090 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8091 8092 /* unset CGCG override */ 8093 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8094 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8095 8096 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8097 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8098 8099 /* update CGCG and CGLS override bits */ 8100 if (def != data) 8101 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8102 8103 /* enable cgcg FSM(0x0000363F) */ 8104 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8105 data = 0; 8106 8107 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8108 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8109 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8110 8111 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8112 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8113 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8114 8115 if (def != data) 8116 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8117 8118 /* set IDLE_POLL_COUNT(0x00900100) */ 8119 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8120 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8121 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8122 if (def != data) 8123 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8124 } else { 8125 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8126 8127 /* reset CGCG/CGLS bits */ 8128 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8129 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8130 8131 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8132 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8133 8134 /* disable cgcg and cgls in FSM */ 8135 if (def != data) 8136 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8137 } 8138 } 8139 8140 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8141 bool enable) 8142 { 8143 uint32_t def, data; 8144 8145 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8146 return; 8147 8148 if (enable) { 8149 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8150 /* unset FGCG override */ 8151 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8152 /* update FGCG override bits */ 8153 if (def != data) 8154 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8155 8156 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8157 /* unset RLC SRAM CLK GATER override */ 8158 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8159 /* update RLC SRAM CLK GATER override bits */ 8160 if (def != data) 8161 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8162 } else { 8163 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8164 /* reset FGCG bits */ 8165 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8166 /* disable FGCG*/ 8167 if (def != data) 8168 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8169 8170 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8171 /* reset RLC SRAM CLK GATER bits */ 8172 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8173 /* disable RLC SRAM CLK*/ 8174 if (def != data) 8175 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8176 } 8177 } 8178 8179 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8180 { 8181 uint32_t reg_data = 0; 8182 uint32_t reg_idx = 0; 8183 uint32_t i; 8184 8185 const uint32_t tcp_ctrl_regs[] = { 8186 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8187 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8188 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8189 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8190 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8191 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8192 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8193 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8194 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8195 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8196 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8197 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8198 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8199 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8200 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8201 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8202 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8203 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8204 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8205 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8206 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8207 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8208 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8209 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8210 }; 8211 8212 const uint32_t tcp_ctrl_regs_nv12[] = { 8213 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8214 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8215 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8216 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8217 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8218 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8219 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8220 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8221 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8222 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8223 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8224 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8225 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8226 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8227 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8228 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8229 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8230 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8231 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8232 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8233 }; 8234 8235 const uint32_t sm_ctlr_regs[] = { 8236 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8237 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8238 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8239 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8240 }; 8241 8242 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8243 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8244 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8245 tcp_ctrl_regs_nv12[i]; 8246 reg_data = RREG32(reg_idx); 8247 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8248 WREG32(reg_idx, reg_data); 8249 } 8250 } else { 8251 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8252 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8253 tcp_ctrl_regs[i]; 8254 reg_data = RREG32(reg_idx); 8255 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8256 WREG32(reg_idx, reg_data); 8257 } 8258 } 8259 8260 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8261 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8262 sm_ctlr_regs[i]; 8263 reg_data = RREG32(reg_idx); 8264 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8265 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8266 WREG32(reg_idx, reg_data); 8267 } 8268 } 8269 8270 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8271 bool enable) 8272 { 8273 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8274 8275 if (enable) { 8276 /* enable FGCG firstly*/ 8277 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8278 /* CGCG/CGLS should be enabled after MGCG/MGLS 8279 * === MGCG + MGLS === 8280 */ 8281 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8282 /* === CGCG /CGLS for GFX 3D Only === */ 8283 gfx_v10_0_update_3d_clock_gating(adev, enable); 8284 /* === CGCG + CGLS === */ 8285 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8286 8287 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8288 IP_VERSION(10, 1, 10)) || 8289 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8290 IP_VERSION(10, 1, 1)) || 8291 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8292 IP_VERSION(10, 1, 2))) 8293 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8294 } else { 8295 /* CGCG/CGLS should be disabled before MGCG/MGLS 8296 * === CGCG + CGLS === 8297 */ 8298 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8299 /* === CGCG /CGLS for GFX 3D Only === */ 8300 gfx_v10_0_update_3d_clock_gating(adev, enable); 8301 /* === MGCG + MGLS === */ 8302 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8303 /* disable fgcg at last*/ 8304 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8305 } 8306 8307 if (adev->cg_flags & 8308 (AMD_CG_SUPPORT_GFX_MGCG | 8309 AMD_CG_SUPPORT_GFX_CGLS | 8310 AMD_CG_SUPPORT_GFX_CGCG | 8311 AMD_CG_SUPPORT_GFX_3D_CGCG | 8312 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8313 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8314 8315 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8316 8317 return 0; 8318 } 8319 8320 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8321 unsigned int vmid) 8322 { 8323 u32 reg, pre_data, data; 8324 8325 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8326 /* not for *_SOC15 */ 8327 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8328 pre_data = RREG32_NO_KIQ(reg); 8329 else 8330 pre_data = RREG32(reg); 8331 8332 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8333 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8334 8335 if (pre_data != data) { 8336 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8337 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8338 } else 8339 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8340 } 8341 } 8342 8343 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8344 { 8345 amdgpu_gfx_off_ctrl(adev, false); 8346 8347 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8348 8349 amdgpu_gfx_off_ctrl(adev, true); 8350 } 8351 8352 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8353 uint32_t offset, 8354 struct soc15_reg_rlcg *entries, int arr_size) 8355 { 8356 int i; 8357 uint32_t reg; 8358 8359 if (!entries) 8360 return false; 8361 8362 for (i = 0; i < arr_size; i++) { 8363 const struct soc15_reg_rlcg *entry; 8364 8365 entry = &entries[i]; 8366 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8367 if (offset == reg) 8368 return true; 8369 } 8370 8371 return false; 8372 } 8373 8374 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8375 { 8376 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8377 } 8378 8379 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8380 { 8381 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8382 8383 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8384 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8385 else 8386 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8387 8388 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8389 8390 /* 8391 * CGPG enablement required and the register to program the hysteresis value 8392 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8393 * in refclk count. Note that RLC FW is modified to take 16 bits from 8394 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8395 * 8396 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8397 * of CGPG enablement starting point. 8398 * Power/performance team will optimize it and might give a new value later. 8399 */ 8400 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8401 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8402 case IP_VERSION(10, 3, 1): 8403 case IP_VERSION(10, 3, 3): 8404 case IP_VERSION(10, 3, 6): 8405 case IP_VERSION(10, 3, 7): 8406 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8407 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8408 break; 8409 default: 8410 break; 8411 } 8412 } 8413 } 8414 8415 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8416 { 8417 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8418 8419 gfx_v10_cntl_power_gating(adev, enable); 8420 8421 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8422 } 8423 8424 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8425 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8426 .set_safe_mode = gfx_v10_0_set_safe_mode, 8427 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8428 .init = gfx_v10_0_rlc_init, 8429 .get_csb_size = gfx_v10_0_get_csb_size, 8430 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8431 .resume = gfx_v10_0_rlc_resume, 8432 .stop = gfx_v10_0_rlc_stop, 8433 .reset = gfx_v10_0_rlc_reset, 8434 .start = gfx_v10_0_rlc_start, 8435 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8436 }; 8437 8438 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8439 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8440 .set_safe_mode = gfx_v10_0_set_safe_mode, 8441 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8442 .init = gfx_v10_0_rlc_init, 8443 .get_csb_size = gfx_v10_0_get_csb_size, 8444 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8445 .resume = gfx_v10_0_rlc_resume, 8446 .stop = gfx_v10_0_rlc_stop, 8447 .reset = gfx_v10_0_rlc_reset, 8448 .start = gfx_v10_0_rlc_start, 8449 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8450 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8451 }; 8452 8453 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 8454 enum amd_powergating_state state) 8455 { 8456 struct amdgpu_device *adev = ip_block->adev; 8457 bool enable = (state == AMD_PG_STATE_GATE); 8458 8459 if (amdgpu_sriov_vf(adev)) 8460 return 0; 8461 8462 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8463 case IP_VERSION(10, 1, 10): 8464 case IP_VERSION(10, 1, 1): 8465 case IP_VERSION(10, 1, 2): 8466 case IP_VERSION(10, 3, 0): 8467 case IP_VERSION(10, 3, 2): 8468 case IP_VERSION(10, 3, 4): 8469 case IP_VERSION(10, 3, 5): 8470 amdgpu_gfx_off_ctrl(adev, enable); 8471 break; 8472 case IP_VERSION(10, 3, 1): 8473 case IP_VERSION(10, 3, 3): 8474 case IP_VERSION(10, 3, 6): 8475 case IP_VERSION(10, 3, 7): 8476 if (!enable) 8477 amdgpu_gfx_off_ctrl(adev, false); 8478 8479 gfx_v10_cntl_pg(adev, enable); 8480 8481 if (enable) 8482 amdgpu_gfx_off_ctrl(adev, true); 8483 8484 break; 8485 default: 8486 break; 8487 } 8488 return 0; 8489 } 8490 8491 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 8492 enum amd_clockgating_state state) 8493 { 8494 struct amdgpu_device *adev = ip_block->adev; 8495 8496 if (amdgpu_sriov_vf(adev)) 8497 return 0; 8498 8499 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8500 case IP_VERSION(10, 1, 10): 8501 case IP_VERSION(10, 1, 1): 8502 case IP_VERSION(10, 1, 2): 8503 case IP_VERSION(10, 3, 0): 8504 case IP_VERSION(10, 3, 2): 8505 case IP_VERSION(10, 3, 1): 8506 case IP_VERSION(10, 3, 4): 8507 case IP_VERSION(10, 3, 5): 8508 case IP_VERSION(10, 3, 6): 8509 case IP_VERSION(10, 3, 3): 8510 case IP_VERSION(10, 3, 7): 8511 gfx_v10_0_update_gfx_clock_gating(adev, 8512 state == AMD_CG_STATE_GATE); 8513 break; 8514 default: 8515 break; 8516 } 8517 return 0; 8518 } 8519 8520 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 8521 { 8522 struct amdgpu_device *adev = ip_block->adev; 8523 int data; 8524 8525 /* AMD_CG_SUPPORT_GFX_FGCG */ 8526 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8527 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8528 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8529 8530 /* AMD_CG_SUPPORT_GFX_MGCG */ 8531 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8532 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8533 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8534 8535 /* AMD_CG_SUPPORT_GFX_CGCG */ 8536 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8537 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8538 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8539 8540 /* AMD_CG_SUPPORT_GFX_CGLS */ 8541 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8542 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8543 8544 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8545 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8546 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8547 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8548 8549 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8550 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8551 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8552 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8553 8554 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8555 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8556 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8557 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8558 8559 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8560 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8561 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8562 } 8563 8564 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8565 { 8566 /* gfx10 is 32bit rptr*/ 8567 return *(uint32_t *)ring->rptr_cpu_addr; 8568 } 8569 8570 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8571 { 8572 struct amdgpu_device *adev = ring->adev; 8573 u64 wptr; 8574 8575 /* XXX check if swapping is necessary on BE */ 8576 if (ring->use_doorbell) { 8577 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8578 } else { 8579 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8580 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8581 } 8582 8583 return wptr; 8584 } 8585 8586 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8587 { 8588 struct amdgpu_device *adev = ring->adev; 8589 8590 if (ring->use_doorbell) { 8591 /* XXX check if swapping is necessary on BE */ 8592 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8593 ring->wptr); 8594 WDOORBELL64(ring->doorbell_index, ring->wptr); 8595 } else { 8596 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8597 lower_32_bits(ring->wptr)); 8598 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8599 upper_32_bits(ring->wptr)); 8600 } 8601 } 8602 8603 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8604 { 8605 /* gfx10 hardware is 32bit rptr */ 8606 return *(uint32_t *)ring->rptr_cpu_addr; 8607 } 8608 8609 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8610 { 8611 u64 wptr; 8612 8613 /* XXX check if swapping is necessary on BE */ 8614 if (ring->use_doorbell) 8615 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8616 else 8617 BUG(); 8618 return wptr; 8619 } 8620 8621 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8622 { 8623 struct amdgpu_device *adev = ring->adev; 8624 8625 if (ring->use_doorbell) { 8626 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8627 ring->wptr); 8628 WDOORBELL64(ring->doorbell_index, ring->wptr); 8629 } else { 8630 BUG(); /* only DOORBELL method supported on gfx10 now */ 8631 } 8632 } 8633 8634 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8635 { 8636 struct amdgpu_device *adev = ring->adev; 8637 u32 ref_and_mask, reg_mem_engine; 8638 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8639 8640 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8641 switch (ring->me) { 8642 case 1: 8643 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8644 break; 8645 case 2: 8646 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8647 break; 8648 default: 8649 return; 8650 } 8651 reg_mem_engine = 0; 8652 } else { 8653 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8654 reg_mem_engine = 1; /* pfp */ 8655 } 8656 8657 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8658 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8659 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8660 ref_and_mask, ref_and_mask, 0x20); 8661 } 8662 8663 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8664 struct amdgpu_job *job, 8665 struct amdgpu_ib *ib, 8666 uint32_t flags) 8667 { 8668 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8669 u32 header, control = 0; 8670 8671 if (ib->flags & AMDGPU_IB_FLAG_CE) 8672 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8673 else 8674 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8675 8676 control |= ib->length_dw | (vmid << 24); 8677 8678 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8679 control |= INDIRECT_BUFFER_PRE_ENB(1); 8680 8681 if (flags & AMDGPU_IB_PREEMPTED) 8682 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8683 8684 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8685 gfx_v10_0_ring_emit_de_meta(ring, 8686 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8687 } 8688 8689 amdgpu_ring_write(ring, header); 8690 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8691 amdgpu_ring_write(ring, 8692 #ifdef __BIG_ENDIAN 8693 (2 << 0) | 8694 #endif 8695 lower_32_bits(ib->gpu_addr)); 8696 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8697 amdgpu_ring_write(ring, control); 8698 } 8699 8700 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8701 struct amdgpu_job *job, 8702 struct amdgpu_ib *ib, 8703 uint32_t flags) 8704 { 8705 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8706 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8707 8708 /* Currently, there is a high possibility to get wave ID mismatch 8709 * between ME and GDS, leading to a hw deadlock, because ME generates 8710 * different wave IDs than the GDS expects. This situation happens 8711 * randomly when at least 5 compute pipes use GDS ordered append. 8712 * The wave IDs generated by ME are also wrong after suspend/resume. 8713 * Those are probably bugs somewhere else in the kernel driver. 8714 * 8715 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8716 * GDS to 0 for this ring (me/pipe). 8717 */ 8718 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8719 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8720 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8721 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8722 } 8723 8724 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8725 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8726 amdgpu_ring_write(ring, 8727 #ifdef __BIG_ENDIAN 8728 (2 << 0) | 8729 #endif 8730 lower_32_bits(ib->gpu_addr)); 8731 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8732 amdgpu_ring_write(ring, control); 8733 } 8734 8735 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8736 u64 seq, unsigned int flags) 8737 { 8738 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8739 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8740 8741 /* RELEASE_MEM - flush caches, send int */ 8742 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8743 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8744 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8745 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8746 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8747 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8748 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8749 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8750 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8751 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8752 8753 /* 8754 * the address should be Qword aligned if 64bit write, Dword 8755 * aligned if only send 32bit data low (discard data high) 8756 */ 8757 if (write64bit) 8758 BUG_ON(addr & 0x7); 8759 else 8760 BUG_ON(addr & 0x3); 8761 amdgpu_ring_write(ring, lower_32_bits(addr)); 8762 amdgpu_ring_write(ring, upper_32_bits(addr)); 8763 amdgpu_ring_write(ring, lower_32_bits(seq)); 8764 amdgpu_ring_write(ring, upper_32_bits(seq)); 8765 amdgpu_ring_write(ring, 0); 8766 } 8767 8768 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8769 { 8770 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8771 uint32_t seq = ring->fence_drv.sync_seq; 8772 uint64_t addr = ring->fence_drv.gpu_addr; 8773 8774 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8775 upper_32_bits(addr), seq, 0xffffffff, 4); 8776 } 8777 8778 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8779 uint16_t pasid, uint32_t flush_type, 8780 bool all_hub, uint8_t dst_sel) 8781 { 8782 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8783 amdgpu_ring_write(ring, 8784 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8785 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8786 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8787 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8788 } 8789 8790 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8791 unsigned int vmid, uint64_t pd_addr) 8792 { 8793 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8794 8795 /* compute doesn't have PFP */ 8796 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8797 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8798 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8799 amdgpu_ring_write(ring, 0x0); 8800 } 8801 } 8802 8803 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8804 u64 seq, unsigned int flags) 8805 { 8806 struct amdgpu_device *adev = ring->adev; 8807 8808 /* we only allocate 32bit for each seq wb address */ 8809 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8810 8811 /* write fence seq to the "addr" */ 8812 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8813 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8814 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8815 amdgpu_ring_write(ring, lower_32_bits(addr)); 8816 amdgpu_ring_write(ring, upper_32_bits(addr)); 8817 amdgpu_ring_write(ring, lower_32_bits(seq)); 8818 8819 if (flags & AMDGPU_FENCE_FLAG_INT) { 8820 /* set register to trigger INT */ 8821 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8822 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8823 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8824 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8825 amdgpu_ring_write(ring, 0); 8826 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8827 } 8828 } 8829 8830 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8831 { 8832 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8833 amdgpu_ring_write(ring, 0); 8834 } 8835 8836 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8837 uint32_t flags) 8838 { 8839 uint32_t dw2 = 0; 8840 8841 if (ring->adev->gfx.mcbp) 8842 gfx_v10_0_ring_emit_ce_meta(ring, 8843 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8844 8845 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8846 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8847 /* set load_global_config & load_global_uconfig */ 8848 dw2 |= 0x8001; 8849 /* set load_cs_sh_regs */ 8850 dw2 |= 0x01000000; 8851 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8852 dw2 |= 0x10002; 8853 8854 /* set load_ce_ram if preamble presented */ 8855 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8856 dw2 |= 0x10000000; 8857 } else { 8858 /* still load_ce_ram if this is the first time preamble presented 8859 * although there is no context switch happens. 8860 */ 8861 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8862 dw2 |= 0x10000000; 8863 } 8864 8865 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8866 amdgpu_ring_write(ring, dw2); 8867 amdgpu_ring_write(ring, 0); 8868 } 8869 8870 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8871 uint64_t addr) 8872 { 8873 unsigned int ret; 8874 8875 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8876 amdgpu_ring_write(ring, lower_32_bits(addr)); 8877 amdgpu_ring_write(ring, upper_32_bits(addr)); 8878 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8879 amdgpu_ring_write(ring, 0); 8880 ret = ring->wptr & ring->buf_mask; 8881 /* patch dummy value later */ 8882 amdgpu_ring_write(ring, 0); 8883 8884 return ret; 8885 } 8886 8887 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8888 { 8889 int i, r = 0; 8890 struct amdgpu_device *adev = ring->adev; 8891 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8892 struct amdgpu_ring *kiq_ring = &kiq->ring; 8893 unsigned long flags; 8894 8895 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8896 return -EINVAL; 8897 8898 spin_lock_irqsave(&kiq->ring_lock, flags); 8899 8900 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8901 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8902 return -ENOMEM; 8903 } 8904 8905 /* assert preemption condition */ 8906 amdgpu_ring_set_preempt_cond_exec(ring, false); 8907 8908 /* assert IB preemption, emit the trailing fence */ 8909 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8910 ring->trail_fence_gpu_addr, 8911 ++ring->trail_seq); 8912 amdgpu_ring_commit(kiq_ring); 8913 8914 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8915 8916 /* poll the trailing fence */ 8917 for (i = 0; i < adev->usec_timeout; i++) { 8918 if (ring->trail_seq == 8919 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8920 break; 8921 udelay(1); 8922 } 8923 8924 if (i >= adev->usec_timeout) { 8925 r = -EINVAL; 8926 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8927 } 8928 8929 /* deassert preemption condition */ 8930 amdgpu_ring_set_preempt_cond_exec(ring, true); 8931 return r; 8932 } 8933 8934 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8935 { 8936 struct amdgpu_device *adev = ring->adev; 8937 struct v10_ce_ib_state ce_payload = {0}; 8938 uint64_t offset, ce_payload_gpu_addr; 8939 void *ce_payload_cpu_addr; 8940 int cnt; 8941 8942 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8943 8944 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8945 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8946 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8947 8948 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8949 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8950 WRITE_DATA_DST_SEL(8) | 8951 WR_CONFIRM) | 8952 WRITE_DATA_CACHE_POLICY(0)); 8953 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8954 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8955 8956 if (resume) 8957 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8958 sizeof(ce_payload) >> 2); 8959 else 8960 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8961 sizeof(ce_payload) >> 2); 8962 } 8963 8964 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8965 { 8966 struct amdgpu_device *adev = ring->adev; 8967 struct v10_de_ib_state de_payload = {0}; 8968 uint64_t offset, gds_addr, de_payload_gpu_addr; 8969 void *de_payload_cpu_addr; 8970 int cnt; 8971 8972 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8973 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8974 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8975 8976 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8977 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8978 PAGE_SIZE); 8979 8980 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8981 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8982 8983 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8986 WRITE_DATA_DST_SEL(8) | 8987 WR_CONFIRM) | 8988 WRITE_DATA_CACHE_POLICY(0)); 8989 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8990 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8991 8992 if (resume) 8993 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8994 sizeof(de_payload) >> 2); 8995 else 8996 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8997 sizeof(de_payload) >> 2); 8998 } 8999 9000 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 9001 bool secure) 9002 { 9003 uint32_t v = secure ? FRAME_TMZ : 0; 9004 9005 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 9006 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 9007 } 9008 9009 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 9010 uint32_t reg_val_offs) 9011 { 9012 struct amdgpu_device *adev = ring->adev; 9013 9014 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 9015 amdgpu_ring_write(ring, 0 | /* src: register*/ 9016 (5 << 8) | /* dst: memory */ 9017 (1 << 20)); /* write confirm */ 9018 amdgpu_ring_write(ring, reg); 9019 amdgpu_ring_write(ring, 0); 9020 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 9021 reg_val_offs * 4)); 9022 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 9023 reg_val_offs * 4)); 9024 } 9025 9026 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 9027 uint32_t val) 9028 { 9029 uint32_t cmd = 0; 9030 9031 switch (ring->funcs->type) { 9032 case AMDGPU_RING_TYPE_GFX: 9033 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 9034 break; 9035 case AMDGPU_RING_TYPE_KIQ: 9036 cmd = (1 << 16); /* no inc addr */ 9037 break; 9038 default: 9039 cmd = WR_CONFIRM; 9040 break; 9041 } 9042 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 9043 amdgpu_ring_write(ring, cmd); 9044 amdgpu_ring_write(ring, reg); 9045 amdgpu_ring_write(ring, 0); 9046 amdgpu_ring_write(ring, val); 9047 } 9048 9049 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 9050 uint32_t val, uint32_t mask) 9051 { 9052 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 9053 } 9054 9055 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 9056 uint32_t reg0, uint32_t reg1, 9057 uint32_t ref, uint32_t mask) 9058 { 9059 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 9060 struct amdgpu_device *adev = ring->adev; 9061 bool fw_version_ok = false; 9062 9063 fw_version_ok = adev->gfx.cp_fw_write_wait; 9064 9065 if (fw_version_ok) 9066 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 9067 ref, mask, 0x20); 9068 else 9069 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 9070 ref, mask); 9071 } 9072 9073 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 9074 unsigned int vmid) 9075 { 9076 struct amdgpu_device *adev = ring->adev; 9077 uint32_t value = 0; 9078 9079 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 9080 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 9081 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 9082 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 9083 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9084 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 9085 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9086 } 9087 9088 static void 9089 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9090 uint32_t me, uint32_t pipe, 9091 enum amdgpu_interrupt_state state) 9092 { 9093 uint32_t cp_int_cntl, cp_int_cntl_reg; 9094 9095 if (!me) { 9096 switch (pipe) { 9097 case 0: 9098 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9099 break; 9100 case 1: 9101 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9102 break; 9103 default: 9104 DRM_DEBUG("invalid pipe %d\n", pipe); 9105 return; 9106 } 9107 } else { 9108 DRM_DEBUG("invalid me %d\n", me); 9109 return; 9110 } 9111 9112 switch (state) { 9113 case AMDGPU_IRQ_STATE_DISABLE: 9114 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9115 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9116 TIME_STAMP_INT_ENABLE, 0); 9117 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9118 break; 9119 case AMDGPU_IRQ_STATE_ENABLE: 9120 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9121 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9122 TIME_STAMP_INT_ENABLE, 1); 9123 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9124 break; 9125 default: 9126 break; 9127 } 9128 } 9129 9130 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9131 int me, int pipe, 9132 enum amdgpu_interrupt_state state) 9133 { 9134 u32 mec_int_cntl, mec_int_cntl_reg; 9135 9136 /* 9137 * amdgpu controls only the first MEC. That's why this function only 9138 * handles the setting of interrupts for this specific MEC. All other 9139 * pipes' interrupts are set by amdkfd. 9140 */ 9141 9142 if (me == 1) { 9143 switch (pipe) { 9144 case 0: 9145 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9146 break; 9147 case 1: 9148 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9149 break; 9150 case 2: 9151 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9152 break; 9153 case 3: 9154 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9155 break; 9156 default: 9157 DRM_DEBUG("invalid pipe %d\n", pipe); 9158 return; 9159 } 9160 } else { 9161 DRM_DEBUG("invalid me %d\n", me); 9162 return; 9163 } 9164 9165 switch (state) { 9166 case AMDGPU_IRQ_STATE_DISABLE: 9167 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9168 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9169 TIME_STAMP_INT_ENABLE, 0); 9170 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9171 break; 9172 case AMDGPU_IRQ_STATE_ENABLE: 9173 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9174 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9175 TIME_STAMP_INT_ENABLE, 1); 9176 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9177 break; 9178 default: 9179 break; 9180 } 9181 } 9182 9183 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9184 struct amdgpu_irq_src *src, 9185 unsigned int type, 9186 enum amdgpu_interrupt_state state) 9187 { 9188 switch (type) { 9189 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9190 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9191 break; 9192 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9193 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9194 break; 9195 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9196 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9197 break; 9198 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9199 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9200 break; 9201 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9202 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9203 break; 9204 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9205 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9206 break; 9207 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9208 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9209 break; 9210 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9211 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9212 break; 9213 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9214 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9215 break; 9216 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9217 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9218 break; 9219 default: 9220 break; 9221 } 9222 return 0; 9223 } 9224 9225 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9226 struct amdgpu_irq_src *source, 9227 struct amdgpu_iv_entry *entry) 9228 { 9229 int i; 9230 u8 me_id, pipe_id, queue_id; 9231 struct amdgpu_ring *ring; 9232 9233 DRM_DEBUG("IH: CP EOP\n"); 9234 9235 me_id = (entry->ring_id & 0x0c) >> 2; 9236 pipe_id = (entry->ring_id & 0x03) >> 0; 9237 queue_id = (entry->ring_id & 0x70) >> 4; 9238 9239 switch (me_id) { 9240 case 0: 9241 if (pipe_id == 0) 9242 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9243 else 9244 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9245 break; 9246 case 1: 9247 case 2: 9248 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9249 ring = &adev->gfx.compute_ring[i]; 9250 /* Per-queue interrupt is supported for MEC starting from VI. 9251 * The interrupt can only be enabled/disabled per pipe instead 9252 * of per queue. 9253 */ 9254 if ((ring->me == me_id) && 9255 (ring->pipe == pipe_id) && 9256 (ring->queue == queue_id)) 9257 amdgpu_fence_process(ring); 9258 } 9259 break; 9260 } 9261 9262 return 0; 9263 } 9264 9265 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9266 struct amdgpu_irq_src *source, 9267 unsigned int type, 9268 enum amdgpu_interrupt_state state) 9269 { 9270 u32 cp_int_cntl_reg, cp_int_cntl; 9271 int i, j; 9272 9273 switch (state) { 9274 case AMDGPU_IRQ_STATE_DISABLE: 9275 case AMDGPU_IRQ_STATE_ENABLE: 9276 for (i = 0; i < adev->gfx.me.num_me; i++) { 9277 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9278 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9279 9280 if (cp_int_cntl_reg) { 9281 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9282 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9283 PRIV_REG_INT_ENABLE, 9284 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9285 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9286 } 9287 } 9288 } 9289 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9290 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9291 /* MECs start at 1 */ 9292 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9293 9294 if (cp_int_cntl_reg) { 9295 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9296 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9297 PRIV_REG_INT_ENABLE, 9298 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9299 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9300 } 9301 } 9302 } 9303 break; 9304 default: 9305 break; 9306 } 9307 9308 return 0; 9309 } 9310 9311 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9312 struct amdgpu_irq_src *source, 9313 unsigned type, 9314 enum amdgpu_interrupt_state state) 9315 { 9316 u32 cp_int_cntl_reg, cp_int_cntl; 9317 int i, j; 9318 9319 switch (state) { 9320 case AMDGPU_IRQ_STATE_DISABLE: 9321 case AMDGPU_IRQ_STATE_ENABLE: 9322 for (i = 0; i < adev->gfx.me.num_me; i++) { 9323 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9324 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9325 9326 if (cp_int_cntl_reg) { 9327 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9328 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9329 OPCODE_ERROR_INT_ENABLE, 9330 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9331 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9332 } 9333 } 9334 } 9335 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9336 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9337 /* MECs start at 1 */ 9338 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9339 9340 if (cp_int_cntl_reg) { 9341 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9342 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9343 OPCODE_ERROR_INT_ENABLE, 9344 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9345 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9346 } 9347 } 9348 } 9349 break; 9350 default: 9351 break; 9352 } 9353 return 0; 9354 } 9355 9356 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9357 struct amdgpu_irq_src *source, 9358 unsigned int type, 9359 enum amdgpu_interrupt_state state) 9360 { 9361 u32 cp_int_cntl_reg, cp_int_cntl; 9362 int i, j; 9363 9364 switch (state) { 9365 case AMDGPU_IRQ_STATE_DISABLE: 9366 case AMDGPU_IRQ_STATE_ENABLE: 9367 for (i = 0; i < adev->gfx.me.num_me; i++) { 9368 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9369 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9370 9371 if (cp_int_cntl_reg) { 9372 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9373 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9374 PRIV_INSTR_INT_ENABLE, 9375 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9376 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9377 } 9378 } 9379 } 9380 break; 9381 default: 9382 break; 9383 } 9384 9385 return 0; 9386 } 9387 9388 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9389 struct amdgpu_iv_entry *entry) 9390 { 9391 u8 me_id, pipe_id, queue_id; 9392 struct amdgpu_ring *ring; 9393 int i; 9394 9395 me_id = (entry->ring_id & 0x0c) >> 2; 9396 pipe_id = (entry->ring_id & 0x03) >> 0; 9397 queue_id = (entry->ring_id & 0x70) >> 4; 9398 9399 switch (me_id) { 9400 case 0: 9401 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9402 ring = &adev->gfx.gfx_ring[i]; 9403 if (ring->me == me_id && ring->pipe == pipe_id && 9404 ring->queue == queue_id) 9405 drm_sched_fault(&ring->sched); 9406 } 9407 break; 9408 case 1: 9409 case 2: 9410 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9411 ring = &adev->gfx.compute_ring[i]; 9412 if (ring->me == me_id && ring->pipe == pipe_id && 9413 ring->queue == queue_id) 9414 drm_sched_fault(&ring->sched); 9415 } 9416 break; 9417 default: 9418 BUG(); 9419 } 9420 } 9421 9422 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9423 struct amdgpu_irq_src *source, 9424 struct amdgpu_iv_entry *entry) 9425 { 9426 DRM_ERROR("Illegal register access in command stream\n"); 9427 gfx_v10_0_handle_priv_fault(adev, entry); 9428 return 0; 9429 } 9430 9431 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9432 struct amdgpu_irq_src *source, 9433 struct amdgpu_iv_entry *entry) 9434 { 9435 DRM_ERROR("Illegal opcode in command stream \n"); 9436 gfx_v10_0_handle_priv_fault(adev, entry); 9437 return 0; 9438 } 9439 9440 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9441 struct amdgpu_irq_src *source, 9442 struct amdgpu_iv_entry *entry) 9443 { 9444 DRM_ERROR("Illegal instruction in command stream\n"); 9445 gfx_v10_0_handle_priv_fault(adev, entry); 9446 return 0; 9447 } 9448 9449 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9450 struct amdgpu_irq_src *src, 9451 unsigned int type, 9452 enum amdgpu_interrupt_state state) 9453 { 9454 uint32_t tmp, target; 9455 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9456 9457 if (ring->me == 1) 9458 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9459 else 9460 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9461 target += ring->pipe; 9462 9463 switch (type) { 9464 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9465 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9466 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9467 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9468 GENERIC2_INT_ENABLE, 0); 9469 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9470 9471 tmp = RREG32_SOC15_IP(GC, target); 9472 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9473 GENERIC2_INT_ENABLE, 0); 9474 WREG32_SOC15_IP(GC, target, tmp); 9475 } else { 9476 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9477 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9478 GENERIC2_INT_ENABLE, 1); 9479 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9480 9481 tmp = RREG32_SOC15_IP(GC, target); 9482 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9483 GENERIC2_INT_ENABLE, 1); 9484 WREG32_SOC15_IP(GC, target, tmp); 9485 } 9486 break; 9487 default: 9488 BUG(); /* kiq only support GENERIC2_INT now */ 9489 break; 9490 } 9491 return 0; 9492 } 9493 9494 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9495 struct amdgpu_irq_src *source, 9496 struct amdgpu_iv_entry *entry) 9497 { 9498 u8 me_id, pipe_id, queue_id; 9499 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9500 9501 me_id = (entry->ring_id & 0x0c) >> 2; 9502 pipe_id = (entry->ring_id & 0x03) >> 0; 9503 queue_id = (entry->ring_id & 0x70) >> 4; 9504 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9505 me_id, pipe_id, queue_id); 9506 9507 amdgpu_fence_process(ring); 9508 return 0; 9509 } 9510 9511 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9512 { 9513 const unsigned int gcr_cntl = 9514 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9515 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9516 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9517 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9518 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9519 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9520 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9521 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9522 9523 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9524 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9525 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9526 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9527 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9528 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9529 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9530 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9531 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9532 } 9533 9534 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9535 { 9536 /* Header itself is a NOP packet */ 9537 if (num_nop == 1) { 9538 amdgpu_ring_write(ring, ring->funcs->nop); 9539 return; 9540 } 9541 9542 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9543 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9544 9545 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9546 amdgpu_ring_insert_nop(ring, num_nop - 1); 9547 } 9548 9549 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 9550 { 9551 struct amdgpu_device *adev = ring->adev; 9552 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9553 struct amdgpu_ring *kiq_ring = &kiq->ring; 9554 unsigned long flags; 9555 u32 tmp; 9556 u64 addr; 9557 int r; 9558 9559 if (amdgpu_sriov_vf(adev)) 9560 return -EINVAL; 9561 9562 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9563 return -EINVAL; 9564 9565 spin_lock_irqsave(&kiq->ring_lock, flags); 9566 9567 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) { 9568 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9569 return -ENOMEM; 9570 } 9571 9572 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + 9573 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); 9574 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 9575 if (ring->pipe == 0) 9576 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); 9577 else 9578 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); 9579 9580 gfx_v10_0_ring_emit_wreg(kiq_ring, 9581 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); 9582 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, 9583 lower_32_bits(addr), upper_32_bits(addr), 9584 0, 1, 0x20); 9585 gfx_v10_0_ring_emit_reg_wait(kiq_ring, 9586 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); 9587 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9588 amdgpu_ring_commit(kiq_ring); 9589 9590 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9591 9592 r = amdgpu_ring_test_ring(kiq_ring); 9593 if (r) 9594 return r; 9595 9596 r = gfx_v10_0_kgq_init_queue(ring, true); 9597 if (r) { 9598 DRM_ERROR("fail to init kgq\n"); 9599 return r; 9600 } 9601 9602 return amdgpu_ring_test_ring(ring); 9603 } 9604 9605 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, 9606 unsigned int vmid) 9607 { 9608 struct amdgpu_device *adev = ring->adev; 9609 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9610 struct amdgpu_ring *kiq_ring = &kiq->ring; 9611 unsigned long flags; 9612 int i, r; 9613 9614 if (amdgpu_sriov_vf(adev)) 9615 return -EINVAL; 9616 9617 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9618 return -EINVAL; 9619 9620 spin_lock_irqsave(&kiq->ring_lock, flags); 9621 9622 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 9623 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9624 return -ENOMEM; 9625 } 9626 9627 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 9628 0, 0); 9629 amdgpu_ring_commit(kiq_ring); 9630 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9631 9632 r = amdgpu_ring_test_ring(kiq_ring); 9633 if (r) 9634 return r; 9635 9636 /* make sure dequeue is complete*/ 9637 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9638 mutex_lock(&adev->srbm_mutex); 9639 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 9640 for (i = 0; i < adev->usec_timeout; i++) { 9641 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 9642 break; 9643 udelay(1); 9644 } 9645 if (i >= adev->usec_timeout) 9646 r = -ETIMEDOUT; 9647 nv_grbm_select(adev, 0, 0, 0, 0); 9648 mutex_unlock(&adev->srbm_mutex); 9649 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9650 if (r) { 9651 dev_err(adev->dev, "fail to wait on hqd deactivate\n"); 9652 return r; 9653 } 9654 9655 r = gfx_v10_0_kcq_init_queue(ring, true); 9656 if (r) { 9657 dev_err(adev->dev, "fail to init kcq\n"); 9658 return r; 9659 } 9660 9661 spin_lock_irqsave(&kiq->ring_lock, flags); 9662 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9663 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9664 return -ENOMEM; 9665 } 9666 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9667 amdgpu_ring_commit(kiq_ring); 9668 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9669 9670 r = amdgpu_ring_test_ring(kiq_ring); 9671 if (r) 9672 return r; 9673 9674 return amdgpu_ring_test_ring(ring); 9675 } 9676 9677 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 9678 { 9679 struct amdgpu_device *adev = ip_block->adev; 9680 uint32_t i, j, k, reg, index = 0; 9681 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9682 9683 if (!adev->gfx.ip_dump_core) 9684 return; 9685 9686 for (i = 0; i < reg_count; i++) 9687 drm_printf(p, "%-50s \t 0x%08x\n", 9688 gc_reg_list_10_1[i].reg_name, 9689 adev->gfx.ip_dump_core[i]); 9690 9691 /* print compute queue registers for all instances */ 9692 if (!adev->gfx.ip_dump_compute_queues) 9693 return; 9694 9695 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9696 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9697 adev->gfx.mec.num_mec, 9698 adev->gfx.mec.num_pipe_per_mec, 9699 adev->gfx.mec.num_queue_per_pipe); 9700 9701 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9702 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9703 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9704 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9705 for (reg = 0; reg < reg_count; reg++) { 9706 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9707 drm_printf(p, "%-50s \t 0x%08x\n", 9708 "mmCP_MEC_ME2_HEADER_DUMP", 9709 adev->gfx.ip_dump_compute_queues[index + reg]); 9710 else 9711 drm_printf(p, "%-50s \t 0x%08x\n", 9712 gc_cp_reg_list_10[reg].reg_name, 9713 adev->gfx.ip_dump_compute_queues[index + reg]); 9714 } 9715 index += reg_count; 9716 } 9717 } 9718 } 9719 9720 /* print gfx queue registers for all instances */ 9721 if (!adev->gfx.ip_dump_gfx_queues) 9722 return; 9723 9724 index = 0; 9725 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9726 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9727 adev->gfx.me.num_me, 9728 adev->gfx.me.num_pipe_per_me, 9729 adev->gfx.me.num_queue_per_pipe); 9730 9731 for (i = 0; i < adev->gfx.me.num_me; i++) { 9732 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9733 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9734 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9735 for (reg = 0; reg < reg_count; reg++) { 9736 drm_printf(p, "%-50s \t 0x%08x\n", 9737 gc_gfx_queue_reg_list_10[reg].reg_name, 9738 adev->gfx.ip_dump_gfx_queues[index + reg]); 9739 } 9740 index += reg_count; 9741 } 9742 } 9743 } 9744 } 9745 9746 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) 9747 { 9748 struct amdgpu_device *adev = ip_block->adev; 9749 uint32_t i, j, k, reg, index = 0; 9750 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9751 9752 if (!adev->gfx.ip_dump_core) 9753 return; 9754 9755 amdgpu_gfx_off_ctrl(adev, false); 9756 for (i = 0; i < reg_count; i++) 9757 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9758 amdgpu_gfx_off_ctrl(adev, true); 9759 9760 /* dump compute queue registers for all instances */ 9761 if (!adev->gfx.ip_dump_compute_queues) 9762 return; 9763 9764 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9765 amdgpu_gfx_off_ctrl(adev, false); 9766 mutex_lock(&adev->srbm_mutex); 9767 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9768 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9769 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9770 /* ME0 is for GFX so start from 1 for CP */ 9771 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9772 9773 for (reg = 0; reg < reg_count; reg++) { 9774 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9775 adev->gfx.ip_dump_compute_queues[index + reg] = 9776 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP)); 9777 else 9778 adev->gfx.ip_dump_compute_queues[index + reg] = 9779 RREG32(SOC15_REG_ENTRY_OFFSET( 9780 gc_cp_reg_list_10[reg])); 9781 } 9782 index += reg_count; 9783 } 9784 } 9785 } 9786 nv_grbm_select(adev, 0, 0, 0, 0); 9787 mutex_unlock(&adev->srbm_mutex); 9788 amdgpu_gfx_off_ctrl(adev, true); 9789 9790 /* dump gfx queue registers for all instances */ 9791 if (!adev->gfx.ip_dump_gfx_queues) 9792 return; 9793 9794 index = 0; 9795 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9796 amdgpu_gfx_off_ctrl(adev, false); 9797 mutex_lock(&adev->srbm_mutex); 9798 for (i = 0; i < adev->gfx.me.num_me; i++) { 9799 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9800 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9801 nv_grbm_select(adev, i, j, k, 0); 9802 9803 for (reg = 0; reg < reg_count; reg++) { 9804 adev->gfx.ip_dump_gfx_queues[index + reg] = 9805 RREG32(SOC15_REG_ENTRY_OFFSET( 9806 gc_gfx_queue_reg_list_10[reg])); 9807 } 9808 index += reg_count; 9809 } 9810 } 9811 } 9812 nv_grbm_select(adev, 0, 0, 0, 0); 9813 mutex_unlock(&adev->srbm_mutex); 9814 amdgpu_gfx_off_ctrl(adev, true); 9815 } 9816 9817 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 9818 { 9819 /* Emit the cleaner shader */ 9820 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 9821 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 9822 } 9823 9824 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring) 9825 { 9826 amdgpu_gfx_profile_ring_begin_use(ring); 9827 9828 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 9829 } 9830 9831 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) 9832 { 9833 amdgpu_gfx_profile_ring_end_use(ring); 9834 9835 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 9836 } 9837 9838 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9839 .name = "gfx_v10_0", 9840 .early_init = gfx_v10_0_early_init, 9841 .late_init = gfx_v10_0_late_init, 9842 .sw_init = gfx_v10_0_sw_init, 9843 .sw_fini = gfx_v10_0_sw_fini, 9844 .hw_init = gfx_v10_0_hw_init, 9845 .hw_fini = gfx_v10_0_hw_fini, 9846 .suspend = gfx_v10_0_suspend, 9847 .resume = gfx_v10_0_resume, 9848 .is_idle = gfx_v10_0_is_idle, 9849 .wait_for_idle = gfx_v10_0_wait_for_idle, 9850 .soft_reset = gfx_v10_0_soft_reset, 9851 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9852 .set_powergating_state = gfx_v10_0_set_powergating_state, 9853 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9854 .dump_ip_state = gfx_v10_ip_dump, 9855 .print_ip_state = gfx_v10_ip_print, 9856 }; 9857 9858 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9859 .type = AMDGPU_RING_TYPE_GFX, 9860 .align_mask = 0xff, 9861 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9862 .support_64bit_ptrs = true, 9863 .secure_submission_supported = true, 9864 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9865 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9866 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9867 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9868 5 + /* COND_EXEC */ 9869 7 + /* PIPELINE_SYNC */ 9870 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9871 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9872 4 + /* VM_FLUSH */ 9873 8 + /* FENCE for VM_FLUSH */ 9874 20 + /* GDS switch */ 9875 4 + /* double SWITCH_BUFFER, 9876 * the first COND_EXEC jump to the place 9877 * just prior to this double SWITCH_BUFFER 9878 */ 9879 5 + /* COND_EXEC */ 9880 7 + /* HDP_flush */ 9881 4 + /* VGT_flush */ 9882 14 + /* CE_META */ 9883 31 + /* DE_META */ 9884 3 + /* CNTX_CTRL */ 9885 5 + /* HDP_INVL */ 9886 8 + 8 + /* FENCE x2 */ 9887 2 + /* SWITCH_BUFFER */ 9888 8 + /* gfx_v10_0_emit_mem_sync */ 9889 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9890 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9891 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9892 .emit_fence = gfx_v10_0_ring_emit_fence, 9893 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9894 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9895 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9896 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9897 .test_ring = gfx_v10_0_ring_test_ring, 9898 .test_ib = gfx_v10_0_ring_test_ib, 9899 .insert_nop = gfx_v10_ring_insert_nop, 9900 .pad_ib = amdgpu_ring_generic_pad_ib, 9901 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9902 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9903 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9904 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9905 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9906 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9907 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9908 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9909 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9910 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9911 .reset = gfx_v10_0_reset_kgq, 9912 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9913 .begin_use = gfx_v10_0_ring_begin_use, 9914 .end_use = gfx_v10_0_ring_end_use, 9915 }; 9916 9917 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9918 .type = AMDGPU_RING_TYPE_COMPUTE, 9919 .align_mask = 0xff, 9920 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9921 .support_64bit_ptrs = true, 9922 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9923 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9924 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9925 .emit_frame_size = 9926 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9927 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9928 5 + /* hdp invalidate */ 9929 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9930 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9931 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9932 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9933 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9934 8 + /* gfx_v10_0_emit_mem_sync */ 9935 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9936 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9937 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9938 .emit_fence = gfx_v10_0_ring_emit_fence, 9939 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9940 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9941 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9942 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9943 .test_ring = gfx_v10_0_ring_test_ring, 9944 .test_ib = gfx_v10_0_ring_test_ib, 9945 .insert_nop = gfx_v10_ring_insert_nop, 9946 .pad_ib = amdgpu_ring_generic_pad_ib, 9947 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9948 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9949 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9950 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9951 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9952 .reset = gfx_v10_0_reset_kcq, 9953 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9954 .begin_use = gfx_v10_0_ring_begin_use, 9955 .end_use = gfx_v10_0_ring_end_use, 9956 }; 9957 9958 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9959 .type = AMDGPU_RING_TYPE_KIQ, 9960 .align_mask = 0xff, 9961 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9962 .support_64bit_ptrs = true, 9963 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9964 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9965 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9966 .emit_frame_size = 9967 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9968 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9969 5 + /*hdp invalidate */ 9970 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9971 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9972 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9973 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9974 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9975 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9976 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9977 .test_ring = gfx_v10_0_ring_test_ring, 9978 .test_ib = gfx_v10_0_ring_test_ib, 9979 .insert_nop = amdgpu_ring_insert_nop, 9980 .pad_ib = amdgpu_ring_generic_pad_ib, 9981 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9982 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9983 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9984 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9985 }; 9986 9987 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9988 { 9989 int i; 9990 9991 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9992 9993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9994 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9995 9996 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9997 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9998 } 9999 10000 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 10001 .set = gfx_v10_0_set_eop_interrupt_state, 10002 .process = gfx_v10_0_eop_irq, 10003 }; 10004 10005 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 10006 .set = gfx_v10_0_set_priv_reg_fault_state, 10007 .process = gfx_v10_0_priv_reg_irq, 10008 }; 10009 10010 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 10011 .set = gfx_v10_0_set_bad_op_fault_state, 10012 .process = gfx_v10_0_bad_op_irq, 10013 }; 10014 10015 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 10016 .set = gfx_v10_0_set_priv_inst_fault_state, 10017 .process = gfx_v10_0_priv_inst_irq, 10018 }; 10019 10020 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 10021 .set = gfx_v10_0_kiq_set_interrupt_state, 10022 .process = gfx_v10_0_kiq_irq, 10023 }; 10024 10025 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 10026 { 10027 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 10028 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 10029 10030 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 10031 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 10032 10033 adev->gfx.priv_reg_irq.num_types = 1; 10034 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 10035 10036 adev->gfx.bad_op_irq.num_types = 1; 10037 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 10038 10039 adev->gfx.priv_inst_irq.num_types = 1; 10040 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 10041 } 10042 10043 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 10044 { 10045 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 10046 case IP_VERSION(10, 1, 10): 10047 case IP_VERSION(10, 1, 1): 10048 case IP_VERSION(10, 1, 3): 10049 case IP_VERSION(10, 1, 4): 10050 case IP_VERSION(10, 3, 2): 10051 case IP_VERSION(10, 3, 1): 10052 case IP_VERSION(10, 3, 4): 10053 case IP_VERSION(10, 3, 5): 10054 case IP_VERSION(10, 3, 6): 10055 case IP_VERSION(10, 3, 3): 10056 case IP_VERSION(10, 3, 7): 10057 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 10058 break; 10059 case IP_VERSION(10, 1, 2): 10060 case IP_VERSION(10, 3, 0): 10061 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 10062 break; 10063 default: 10064 break; 10065 } 10066 } 10067 10068 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 10069 { 10070 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 10071 adev->gfx.config.max_sh_per_se * 10072 adev->gfx.config.max_shader_engines; 10073 10074 adev->gds.gds_size = 0x10000; 10075 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 10076 adev->gds.gws_size = 64; 10077 adev->gds.oa_size = 16; 10078 } 10079 10080 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 10081 { 10082 /* set gfx eng mqd */ 10083 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 10084 sizeof(struct v10_gfx_mqd); 10085 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 10086 gfx_v10_0_gfx_mqd_init; 10087 /* set compute eng mqd */ 10088 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 10089 sizeof(struct v10_compute_mqd); 10090 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 10091 gfx_v10_0_compute_mqd_init; 10092 } 10093 10094 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 10095 u32 bitmap) 10096 { 10097 u32 data; 10098 10099 if (!bitmap) 10100 return; 10101 10102 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10103 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10104 10105 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 10106 } 10107 10108 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 10109 { 10110 u32 disabled_mask = 10111 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 10112 u32 efuse_setting = 0; 10113 u32 vbios_setting = 0; 10114 10115 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 10116 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10117 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10118 10119 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 10120 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10121 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10122 10123 disabled_mask |= efuse_setting | vbios_setting; 10124 10125 return (~disabled_mask); 10126 } 10127 10128 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 10129 { 10130 u32 wgp_idx, wgp_active_bitmap; 10131 u32 cu_bitmap_per_wgp, cu_active_bitmap; 10132 10133 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 10134 cu_active_bitmap = 0; 10135 10136 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 10137 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 10138 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 10139 if (wgp_active_bitmap & (1 << wgp_idx)) 10140 cu_active_bitmap |= cu_bitmap_per_wgp; 10141 } 10142 10143 return cu_active_bitmap; 10144 } 10145 10146 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 10147 struct amdgpu_cu_info *cu_info) 10148 { 10149 int i, j, k, counter, active_cu_number = 0; 10150 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 10151 unsigned int disable_masks[4 * 2]; 10152 10153 if (!adev || !cu_info) 10154 return -EINVAL; 10155 10156 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 10157 10158 mutex_lock(&adev->grbm_idx_mutex); 10159 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 10160 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 10161 bitmap = i * adev->gfx.config.max_sh_per_se + j; 10162 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 10163 IP_VERSION(10, 3, 0)) || 10164 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10165 IP_VERSION(10, 3, 3)) || 10166 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10167 IP_VERSION(10, 3, 6)) || 10168 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10169 IP_VERSION(10, 3, 7))) && 10170 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 10171 continue; 10172 mask = 1; 10173 ao_bitmap = 0; 10174 counter = 0; 10175 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 10176 if (i < 4 && j < 2) 10177 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 10178 adev, disable_masks[i * 2 + j]); 10179 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 10180 cu_info->bitmap[0][i][j] = bitmap; 10181 10182 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 10183 if (bitmap & mask) { 10184 if (counter < adev->gfx.config.max_cu_per_sh) 10185 ao_bitmap |= mask; 10186 counter++; 10187 } 10188 mask <<= 1; 10189 } 10190 active_cu_number += counter; 10191 if (i < 2 && j < 2) 10192 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 10193 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 10194 } 10195 } 10196 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 10197 mutex_unlock(&adev->grbm_idx_mutex); 10198 10199 cu_info->number = active_cu_number; 10200 cu_info->ao_cu_mask = ao_cu_mask; 10201 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 10202 10203 return 0; 10204 } 10205 10206 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 10207 { 10208 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 10209 10210 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 10211 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10212 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10213 10214 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 10215 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10216 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10217 10218 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 10219 adev->gfx.config.max_shader_engines); 10220 disabled_sa = efuse_setting | vbios_setting; 10221 disabled_sa &= max_sa_mask; 10222 10223 return disabled_sa; 10224 } 10225 10226 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 10227 { 10228 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 10229 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 10230 10231 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 10232 10233 max_sa_per_se = adev->gfx.config.max_sh_per_se; 10234 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 10235 max_shader_engines = adev->gfx.config.max_shader_engines; 10236 10237 for (se_index = 0; max_shader_engines > se_index; se_index++) { 10238 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 10239 disabled_sa_per_se &= max_sa_per_se_mask; 10240 if (disabled_sa_per_se == max_sa_per_se_mask) { 10241 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 10242 break; 10243 } 10244 } 10245 } 10246 10247 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 10248 { 10249 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 10250 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 10251 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 10252 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 10253 10254 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 10255 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 10256 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 10257 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 10258 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 10259 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 10260 10261 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 10262 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 10263 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 10264 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 10265 10266 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 10267 10268 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 10269 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 10270 } 10271 10272 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 10273 .type = AMD_IP_BLOCK_TYPE_GFX, 10274 .major = 10, 10275 .minor = 0, 10276 .rev = 0, 10277 .funcs = &gfx_v10_0_ip_funcs, 10278 }; 10279