xref: /linux/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (revision ce801e5d6c1bac228bf10f75e8bede4285c58282) 
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34 
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "gfx_v10_0_cleaner_shader.h"
48 #include "nbio_v2_3.h"
49 
50 /*
51  * Navi10 has two graphic rings to share each graphic pipe.
52  * 1. Primary ring
53  * 2. Async ring
54  */
55 #define GFX10_NUM_GFX_RINGS_NV1X	1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
57 #define GFX10_MEC_HPD_SIZE	2048
58 
59 #define F32_CE_PROGRAM_RAM_SIZE		65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
61 
62 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68 
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
71 
72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
76 
77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
104 
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
109 
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
114 
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
119 
120 #define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
139 
140 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
142 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
144 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
146 #define mmCP_HYP_CE_UCODE_DATA			0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
148 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
150 #define mmCP_HYP_ME_UCODE_DATA			0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
152 
153 #define mmCPG_PSP_DEBUG				0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX		1
155 #define mmCPC_PSP_DEBUG				0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX		1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
159 
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3                       0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
175 
176 #define mmCGTT_SPI_CS_CLK_CTRL			0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
178 
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid		0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
183 
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
186 
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
189 
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196 
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208 
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215 
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222 
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229 
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236 
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243 
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250 
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257 
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264 
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271 
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278 
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 	SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
370 	/* cp header registers */
371 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
372 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
373 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
374 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
375 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
376 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
377 	/* SE status registers */
378 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
379 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
380 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
381 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
382 };
383 
384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
385 	/* compute registers */
386 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
387 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
388 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
389 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
390 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
391 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
392 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
393 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
394 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
395 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
396 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
397 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
398 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
399 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
400 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
401 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
402 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
403 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
404 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
405 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
406 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
407 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
408 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
409 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
410 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
411 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
412 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
413 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
414 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
415 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
416 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
417 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
418 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
419 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
420 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
421 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
422 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
423 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
424 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
425 };
426 
427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
428 	/* gfx queue registers */
429 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
430 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
431 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
432 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
433 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
434 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
435 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
436 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
437 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
438 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
439 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
440 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
441 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
442 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
443 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
444 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
445 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
446 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
447 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
448 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
449 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
450 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
451 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
452 };
453 
454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
495 };
496 
497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
498 	/* Pending on emulation bring up */
499 };
500 
501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1554 };
1555 
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1595 };
1596 
1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1640 };
1641 
1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1643 	/* Pending on emulation bring up */
1644 };
1645 
1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2267 };
2268 
2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2270 	/* Pending on emulation bring up */
2271 };
2272 
2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3326 };
3327 
3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3372 };
3373 
3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3375 	/* Pending on emulation bring up */
3376 };
3377 
3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3420 
3421 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3423 };
3424 
3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3450 
3451 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3453 };
3454 
3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3476 };
3477 
3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3515 };
3516 
3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3550 };
3551 
3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3587 };
3588 
3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3612 };
3613 
3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3637 };
3638 
3639 #define DEFAULT_SH_MEM_CONFIG \
3640 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3641 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3642 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3643 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3644 
3645 /* TODO: pending on golden setting value of gb address config */
3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3647 
3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3654 				 struct amdgpu_cu_info *cu_info);
3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3657 				   u32 sh_num, u32 instance, int xcc_id);
3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3659 
3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3671 					   uint16_t pasid, uint32_t flush_type,
3672 					   bool all_hub, uint8_t dst_sel);
3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3674 					       unsigned int vmid);
3675 
3676 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3677 					  enum amd_powergating_state state);
3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3679 {
3680 	struct amdgpu_device *adev = kiq_ring->adev;
3681 	u64 shader_mc_addr;
3682 
3683 	/* Cleaner shader MC address */
3684 	shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3685 
3686 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3687 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3688 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3689 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3690 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3691 	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3692 	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3693 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3694 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3695 }
3696 
3697 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3698 				 struct amdgpu_ring *ring)
3699 {
3700 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3701 	uint64_t wptr_addr = ring->wptr_gpu_addr;
3702 	uint32_t eng_sel = 0;
3703 
3704 	switch (ring->funcs->type) {
3705 	case AMDGPU_RING_TYPE_COMPUTE:
3706 		eng_sel = 0;
3707 		break;
3708 	case AMDGPU_RING_TYPE_GFX:
3709 		eng_sel = 4;
3710 		break;
3711 	case AMDGPU_RING_TYPE_MES:
3712 		eng_sel = 5;
3713 		break;
3714 	default:
3715 		WARN_ON(1);
3716 	}
3717 
3718 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3719 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3720 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3721 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3722 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3723 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3724 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3725 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3726 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3727 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3728 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3729 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3730 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3731 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3732 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3733 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3734 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3735 }
3736 
3737 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3738 				   struct amdgpu_ring *ring,
3739 				   enum amdgpu_unmap_queues_action action,
3740 				   u64 gpu_addr, u64 seq)
3741 {
3742 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3743 
3744 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3745 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3746 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3747 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3748 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3749 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3750 	amdgpu_ring_write(kiq_ring,
3751 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3752 
3753 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3754 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3755 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3756 		amdgpu_ring_write(kiq_ring, seq);
3757 	} else {
3758 		amdgpu_ring_write(kiq_ring, 0);
3759 		amdgpu_ring_write(kiq_ring, 0);
3760 		amdgpu_ring_write(kiq_ring, 0);
3761 	}
3762 }
3763 
3764 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3765 				   struct amdgpu_ring *ring,
3766 				   u64 addr,
3767 				   u64 seq)
3768 {
3769 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3770 
3771 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3772 	amdgpu_ring_write(kiq_ring,
3773 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3774 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3775 			  PACKET3_QUERY_STATUS_COMMAND(2));
3776 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3777 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3778 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3779 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3780 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3781 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3782 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3783 }
3784 
3785 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3786 				uint16_t pasid, uint32_t flush_type,
3787 				bool all_hub)
3788 {
3789 	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3790 }
3791 
3792 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
3793 					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
3794 					uint32_t xcc_id, uint32_t vmid)
3795 {
3796 	struct amdgpu_device *adev = kiq_ring->adev;
3797 	unsigned i;
3798 	uint32_t tmp;
3799 
3800 	/* enter save mode */
3801 	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
3802 	mutex_lock(&adev->srbm_mutex);
3803 	nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
3804 
3805 	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
3806 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
3807 		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
3808 		/* wait till dequeue take effects */
3809 		for (i = 0; i < adev->usec_timeout; i++) {
3810 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3811 				break;
3812 			udelay(1);
3813 		}
3814 		if (i >= adev->usec_timeout)
3815 			dev_err(adev->dev, "fail to wait on hqd deactive\n");
3816 	} else if (queue_type == AMDGPU_RING_TYPE_GFX) {
3817 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
3818 			     (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
3819 		tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
3820 		if (pipe_id == 0)
3821 			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
3822 		else
3823 			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
3824 		WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
3825 
3826 		/* wait till dequeue take effects */
3827 		for (i = 0; i < adev->usec_timeout; i++) {
3828 			if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))
3829 				break;
3830 			udelay(1);
3831 		}
3832 		if (i >= adev->usec_timeout)
3833 			dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
3834 	} else {
3835 		dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
3836 	}
3837 
3838 	nv_grbm_select(adev, 0, 0, 0, 0);
3839 	mutex_unlock(&adev->srbm_mutex);
3840 	/* exit safe mode */
3841 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
3842 }
3843 
3844 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3845 	.kiq_set_resources = gfx10_kiq_set_resources,
3846 	.kiq_map_queues = gfx10_kiq_map_queues,
3847 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3848 	.kiq_query_status = gfx10_kiq_query_status,
3849 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3850 	.kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
3851 	.set_resources_size = 8,
3852 	.map_queues_size = 7,
3853 	.unmap_queues_size = 6,
3854 	.query_status_size = 7,
3855 	.invalidate_tlbs_size = 2,
3856 };
3857 
3858 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3859 {
3860 	adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3861 }
3862 
3863 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3864 {
3865 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3866 	case IP_VERSION(10, 1, 10):
3867 		soc15_program_register_sequence(adev,
3868 						golden_settings_gc_rlc_spm_10_0_nv10,
3869 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3870 		break;
3871 	case IP_VERSION(10, 1, 1):
3872 		soc15_program_register_sequence(adev,
3873 						golden_settings_gc_rlc_spm_10_1_nv14,
3874 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3875 		break;
3876 	case IP_VERSION(10, 1, 2):
3877 		soc15_program_register_sequence(adev,
3878 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3879 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3880 		break;
3881 	default:
3882 		break;
3883 	}
3884 }
3885 
3886 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3887 {
3888 	if (amdgpu_sriov_vf(adev))
3889 		return;
3890 
3891 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3892 	case IP_VERSION(10, 1, 10):
3893 		soc15_program_register_sequence(adev,
3894 						golden_settings_gc_10_1,
3895 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3896 		soc15_program_register_sequence(adev,
3897 						golden_settings_gc_10_0_nv10,
3898 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3899 		break;
3900 	case IP_VERSION(10, 1, 1):
3901 		soc15_program_register_sequence(adev,
3902 						golden_settings_gc_10_1_1,
3903 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3904 		soc15_program_register_sequence(adev,
3905 						golden_settings_gc_10_1_nv14,
3906 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3907 		break;
3908 	case IP_VERSION(10, 1, 2):
3909 		soc15_program_register_sequence(adev,
3910 						golden_settings_gc_10_1_2,
3911 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3912 		soc15_program_register_sequence(adev,
3913 						golden_settings_gc_10_1_2_nv12,
3914 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3915 		break;
3916 	case IP_VERSION(10, 3, 0):
3917 		soc15_program_register_sequence(adev,
3918 						golden_settings_gc_10_3,
3919 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3920 		soc15_program_register_sequence(adev,
3921 						golden_settings_gc_10_3_sienna_cichlid,
3922 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3923 		break;
3924 	case IP_VERSION(10, 3, 2):
3925 		soc15_program_register_sequence(adev,
3926 						golden_settings_gc_10_3_2,
3927 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3928 		break;
3929 	case IP_VERSION(10, 3, 1):
3930 		soc15_program_register_sequence(adev,
3931 						golden_settings_gc_10_3_vangogh,
3932 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3933 		break;
3934 	case IP_VERSION(10, 3, 3):
3935 		soc15_program_register_sequence(adev,
3936 						golden_settings_gc_10_3_3,
3937 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3938 		break;
3939 	case IP_VERSION(10, 3, 4):
3940 		soc15_program_register_sequence(adev,
3941 						golden_settings_gc_10_3_4,
3942 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3943 		break;
3944 	case IP_VERSION(10, 3, 5):
3945 		soc15_program_register_sequence(adev,
3946 						golden_settings_gc_10_3_5,
3947 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3948 		break;
3949 	case IP_VERSION(10, 1, 3):
3950 	case IP_VERSION(10, 1, 4):
3951 		soc15_program_register_sequence(adev,
3952 						golden_settings_gc_10_0_cyan_skillfish,
3953 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3954 		break;
3955 	case IP_VERSION(10, 3, 6):
3956 		soc15_program_register_sequence(adev,
3957 						golden_settings_gc_10_3_6,
3958 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3959 		break;
3960 	case IP_VERSION(10, 3, 7):
3961 		soc15_program_register_sequence(adev,
3962 						golden_settings_gc_10_3_7,
3963 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3964 		break;
3965 	default:
3966 		break;
3967 	}
3968 	gfx_v10_0_init_spm_golden_registers(adev);
3969 }
3970 
3971 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3972 				       bool wc, uint32_t reg, uint32_t val)
3973 {
3974 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3975 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3976 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3977 	amdgpu_ring_write(ring, reg);
3978 	amdgpu_ring_write(ring, 0);
3979 	amdgpu_ring_write(ring, val);
3980 }
3981 
3982 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3983 				  int mem_space, int opt, uint32_t addr0,
3984 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3985 				  uint32_t inv)
3986 {
3987 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3988 	amdgpu_ring_write(ring,
3989 			  /* memory (1) or register (0) */
3990 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3991 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3992 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3993 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3994 
3995 	if (mem_space)
3996 		BUG_ON(addr0 & 0x3); /* Dword align */
3997 	amdgpu_ring_write(ring, addr0);
3998 	amdgpu_ring_write(ring, addr1);
3999 	amdgpu_ring_write(ring, ref);
4000 	amdgpu_ring_write(ring, mask);
4001 	amdgpu_ring_write(ring, inv); /* poll interval */
4002 }
4003 
4004 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
4005 {
4006 	struct amdgpu_device *adev = ring->adev;
4007 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4008 	uint32_t tmp = 0;
4009 	unsigned int i;
4010 	int r;
4011 
4012 	WREG32(scratch, 0xCAFEDEAD);
4013 	r = amdgpu_ring_alloc(ring, 3);
4014 	if (r) {
4015 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
4016 			  ring->idx, r);
4017 		return r;
4018 	}
4019 
4020 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4021 	amdgpu_ring_write(ring, scratch -
4022 			  PACKET3_SET_UCONFIG_REG_START);
4023 	amdgpu_ring_write(ring, 0xDEADBEEF);
4024 	amdgpu_ring_commit(ring);
4025 
4026 	for (i = 0; i < adev->usec_timeout; i++) {
4027 		tmp = RREG32(scratch);
4028 		if (tmp == 0xDEADBEEF)
4029 			break;
4030 		if (amdgpu_emu_mode == 1)
4031 			msleep(1);
4032 		else
4033 			udelay(1);
4034 	}
4035 
4036 	if (i >= adev->usec_timeout)
4037 		r = -ETIMEDOUT;
4038 
4039 	return r;
4040 }
4041 
4042 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
4043 {
4044 	struct amdgpu_device *adev = ring->adev;
4045 	struct amdgpu_ib ib;
4046 	struct dma_fence *f = NULL;
4047 	unsigned int index;
4048 	uint64_t gpu_addr;
4049 	volatile uint32_t *cpu_ptr;
4050 	long r;
4051 
4052 	memset(&ib, 0, sizeof(ib));
4053 
4054 	r = amdgpu_device_wb_get(adev, &index);
4055 	if (r)
4056 		return r;
4057 
4058 	gpu_addr = adev->wb.gpu_addr + (index * 4);
4059 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4060 	cpu_ptr = &adev->wb.wb[index];
4061 
4062 	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4063 	if (r) {
4064 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4065 		goto err1;
4066 	}
4067 
4068 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4069 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4070 	ib.ptr[2] = lower_32_bits(gpu_addr);
4071 	ib.ptr[3] = upper_32_bits(gpu_addr);
4072 	ib.ptr[4] = 0xDEADBEEF;
4073 	ib.length_dw = 5;
4074 
4075 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4076 	if (r)
4077 		goto err2;
4078 
4079 	r = dma_fence_wait_timeout(f, false, timeout);
4080 	if (r == 0) {
4081 		r = -ETIMEDOUT;
4082 		goto err2;
4083 	} else if (r < 0) {
4084 		goto err2;
4085 	}
4086 
4087 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4088 		r = 0;
4089 	else
4090 		r = -EINVAL;
4091 err2:
4092 	amdgpu_ib_free(&ib, NULL);
4093 	dma_fence_put(f);
4094 err1:
4095 	amdgpu_device_wb_free(adev, index);
4096 	return r;
4097 }
4098 
4099 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4100 {
4101 	amdgpu_ucode_release(&adev->gfx.pfp_fw);
4102 	amdgpu_ucode_release(&adev->gfx.me_fw);
4103 	amdgpu_ucode_release(&adev->gfx.ce_fw);
4104 	amdgpu_ucode_release(&adev->gfx.rlc_fw);
4105 	amdgpu_ucode_release(&adev->gfx.mec_fw);
4106 	amdgpu_ucode_release(&adev->gfx.mec2_fw);
4107 
4108 	kfree(adev->gfx.rlc.register_list_format);
4109 }
4110 
4111 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4112 {
4113 	adev->gfx.cp_fw_write_wait = false;
4114 
4115 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4116 	case IP_VERSION(10, 1, 10):
4117 	case IP_VERSION(10, 1, 2):
4118 	case IP_VERSION(10, 1, 1):
4119 	case IP_VERSION(10, 1, 3):
4120 	case IP_VERSION(10, 1, 4):
4121 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
4122 		    (adev->gfx.me_feature_version >= 27) &&
4123 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
4124 		    (adev->gfx.pfp_feature_version >= 27) &&
4125 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
4126 		    (adev->gfx.mec_feature_version >= 27))
4127 			adev->gfx.cp_fw_write_wait = true;
4128 		break;
4129 	case IP_VERSION(10, 3, 0):
4130 	case IP_VERSION(10, 3, 2):
4131 	case IP_VERSION(10, 3, 1):
4132 	case IP_VERSION(10, 3, 4):
4133 	case IP_VERSION(10, 3, 5):
4134 	case IP_VERSION(10, 3, 6):
4135 	case IP_VERSION(10, 3, 3):
4136 	case IP_VERSION(10, 3, 7):
4137 		adev->gfx.cp_fw_write_wait = true;
4138 		break;
4139 	default:
4140 		break;
4141 	}
4142 
4143 	if (!adev->gfx.cp_fw_write_wait)
4144 		DRM_WARN_ONCE("CP firmware version too old, please update!");
4145 }
4146 
4147 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4148 {
4149 	bool ret = false;
4150 
4151 	switch (adev->pdev->revision) {
4152 	case 0xc2:
4153 	case 0xc3:
4154 		ret = true;
4155 		break;
4156 	default:
4157 		ret = false;
4158 		break;
4159 	}
4160 
4161 	return ret;
4162 }
4163 
4164 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4165 {
4166 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4167 	case IP_VERSION(10, 1, 10):
4168 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4169 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4170 		break;
4171 	default:
4172 		break;
4173 	}
4174 }
4175 
4176 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4177 {
4178 	char fw_name[53];
4179 	char ucode_prefix[30];
4180 	const char *wks = "";
4181 	int err;
4182 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4183 	uint16_t version_major;
4184 	uint16_t version_minor;
4185 
4186 	DRM_DEBUG("\n");
4187 
4188 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4189 	    (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4190 		wks = "_wks";
4191 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4192 
4193 	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4194 				   AMDGPU_UCODE_REQUIRED,
4195 				   "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4196 	if (err)
4197 		goto out;
4198 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4199 
4200 	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4201 				   AMDGPU_UCODE_REQUIRED,
4202 				   "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4203 	if (err)
4204 		goto out;
4205 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4206 
4207 	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4208 				   AMDGPU_UCODE_REQUIRED,
4209 				   "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4210 	if (err)
4211 		goto out;
4212 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4213 
4214 	if (!amdgpu_sriov_vf(adev)) {
4215 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4216 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4217 		if (err)
4218 			goto out;
4219 
4220 		/* don't validate this firmware. There are apparently firmwares
4221 		 * in the wild with incorrect size in the header
4222 		 */
4223 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4224 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4225 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4226 		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4227 		if (err)
4228 			goto out;
4229 	}
4230 
4231 	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4232 				   AMDGPU_UCODE_REQUIRED,
4233 				   "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4234 	if (err)
4235 		goto out;
4236 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4237 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4238 
4239 	err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4240 				   AMDGPU_UCODE_REQUIRED,
4241 				   "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4242 	if (!err) {
4243 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4244 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4245 	} else {
4246 		err = 0;
4247 		adev->gfx.mec2_fw = NULL;
4248 	}
4249 
4250 	gfx_v10_0_check_fw_write_wait(adev);
4251 out:
4252 	if (err) {
4253 		amdgpu_ucode_release(&adev->gfx.pfp_fw);
4254 		amdgpu_ucode_release(&adev->gfx.me_fw);
4255 		amdgpu_ucode_release(&adev->gfx.ce_fw);
4256 		amdgpu_ucode_release(&adev->gfx.rlc_fw);
4257 		amdgpu_ucode_release(&adev->gfx.mec_fw);
4258 		amdgpu_ucode_release(&adev->gfx.mec2_fw);
4259 	}
4260 
4261 	gfx_v10_0_check_gfxoff_flag(adev);
4262 
4263 	return err;
4264 }
4265 
4266 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4267 {
4268 	u32 count = 0;
4269 	const struct cs_section_def *sect = NULL;
4270 	const struct cs_extent_def *ext = NULL;
4271 
4272 	/* begin clear state */
4273 	count += 2;
4274 	/* context control state */
4275 	count += 3;
4276 
4277 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4278 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4279 			if (sect->id == SECT_CONTEXT)
4280 				count += 2 + ext->reg_count;
4281 			else
4282 				return 0;
4283 		}
4284 	}
4285 
4286 	/* set PA_SC_TILE_STEERING_OVERRIDE */
4287 	count += 3;
4288 	/* end clear state */
4289 	count += 2;
4290 	/* clear state */
4291 	count += 2;
4292 
4293 	return count;
4294 }
4295 
4296 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4297 				    volatile u32 *buffer)
4298 {
4299 	u32 count = 0, i;
4300 	const struct cs_section_def *sect = NULL;
4301 	const struct cs_extent_def *ext = NULL;
4302 	int ctx_reg_offset;
4303 
4304 	if (adev->gfx.rlc.cs_data == NULL)
4305 		return;
4306 	if (buffer == NULL)
4307 		return;
4308 
4309 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4310 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4311 
4312 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4313 	buffer[count++] = cpu_to_le32(0x80000000);
4314 	buffer[count++] = cpu_to_le32(0x80000000);
4315 
4316 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4317 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4318 			if (sect->id == SECT_CONTEXT) {
4319 				buffer[count++] =
4320 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4321 				buffer[count++] = cpu_to_le32(ext->reg_index -
4322 						PACKET3_SET_CONTEXT_REG_START);
4323 				for (i = 0; i < ext->reg_count; i++)
4324 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4325 			}
4326 		}
4327 	}
4328 
4329 	ctx_reg_offset =
4330 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4331 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4332 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4333 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4334 
4335 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4336 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4337 
4338 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4339 	buffer[count++] = cpu_to_le32(0);
4340 }
4341 
4342 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4343 {
4344 	/* clear state block */
4345 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4346 			&adev->gfx.rlc.clear_state_gpu_addr,
4347 			(void **)&adev->gfx.rlc.cs_ptr);
4348 
4349 	/* jump table block */
4350 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4351 			&adev->gfx.rlc.cp_table_gpu_addr,
4352 			(void **)&adev->gfx.rlc.cp_table_ptr);
4353 }
4354 
4355 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4356 {
4357 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4358 
4359 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4360 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4361 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4362 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4363 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4364 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4365 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4366 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4367 	case IP_VERSION(10, 3, 0):
4368 		reg_access_ctrl->spare_int =
4369 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4370 		break;
4371 	default:
4372 		reg_access_ctrl->spare_int =
4373 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4374 		break;
4375 	}
4376 	adev->gfx.rlc.rlcg_reg_access_supported = true;
4377 }
4378 
4379 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4380 {
4381 	const struct cs_section_def *cs_data;
4382 	int r;
4383 
4384 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4385 
4386 	cs_data = adev->gfx.rlc.cs_data;
4387 
4388 	if (cs_data) {
4389 		/* init clear state block */
4390 		r = amdgpu_gfx_rlc_init_csb(adev);
4391 		if (r)
4392 			return r;
4393 	}
4394 
4395 	return 0;
4396 }
4397 
4398 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4399 {
4400 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4401 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4402 }
4403 
4404 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4405 {
4406 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4407 
4408 	amdgpu_gfx_graphics_queue_acquire(adev);
4409 }
4410 
4411 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4412 {
4413 	int r;
4414 	u32 *hpd;
4415 	const __le32 *fw_data = NULL;
4416 	unsigned int fw_size;
4417 	u32 *fw = NULL;
4418 	size_t mec_hpd_size;
4419 
4420 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4421 
4422 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4423 
4424 	/* take ownership of the relevant compute queues */
4425 	amdgpu_gfx_compute_queue_acquire(adev);
4426 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4427 
4428 	if (mec_hpd_size) {
4429 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4430 					      AMDGPU_GEM_DOMAIN_GTT,
4431 					      &adev->gfx.mec.hpd_eop_obj,
4432 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4433 					      (void **)&hpd);
4434 		if (r) {
4435 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4436 			gfx_v10_0_mec_fini(adev);
4437 			return r;
4438 		}
4439 
4440 		memset(hpd, 0, mec_hpd_size);
4441 
4442 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4443 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4444 	}
4445 
4446 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4447 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4448 
4449 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4450 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4451 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4452 
4453 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4454 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4455 					      &adev->gfx.mec.mec_fw_obj,
4456 					      &adev->gfx.mec.mec_fw_gpu_addr,
4457 					      (void **)&fw);
4458 		if (r) {
4459 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4460 			gfx_v10_0_mec_fini(adev);
4461 			return r;
4462 		}
4463 
4464 		memcpy(fw, fw_data, fw_size);
4465 
4466 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4467 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4468 	}
4469 
4470 	return 0;
4471 }
4472 
4473 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4474 {
4475 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4476 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4477 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4478 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4479 }
4480 
4481 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4482 			   uint32_t thread, uint32_t regno,
4483 			   uint32_t num, uint32_t *out)
4484 {
4485 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4486 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4487 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4488 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4489 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4490 	while (num--)
4491 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4492 }
4493 
4494 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4495 {
4496 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4497 	 * field when performing a select_se_sh so it should be
4498 	 * zero here
4499 	 */
4500 	WARN_ON(simd != 0);
4501 
4502 	/* type 2 wave data */
4503 	dst[(*no_fields)++] = 2;
4504 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4505 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4506 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4507 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4508 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4509 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4510 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4511 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4512 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4513 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4514 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4515 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4516 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4517 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4518 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4519 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4520 }
4521 
4522 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4523 				     uint32_t wave, uint32_t start,
4524 				     uint32_t size, uint32_t *dst)
4525 {
4526 	WARN_ON(simd != 0);
4527 
4528 	wave_read_regs(
4529 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4530 		dst);
4531 }
4532 
4533 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4534 				      uint32_t wave, uint32_t thread,
4535 				      uint32_t start, uint32_t size,
4536 				      uint32_t *dst)
4537 {
4538 	wave_read_regs(
4539 		adev, wave, thread,
4540 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4541 }
4542 
4543 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4544 				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4545 {
4546 	nv_grbm_select(adev, me, pipe, q, vm);
4547 }
4548 
4549 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4550 					  bool enable)
4551 {
4552 	uint32_t data, def;
4553 
4554 	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4555 
4556 	if (enable)
4557 		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4558 	else
4559 		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4560 
4561 	if (data != def)
4562 		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4563 }
4564 
4565 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4566 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4567 	.select_se_sh = &gfx_v10_0_select_se_sh,
4568 	.read_wave_data = &gfx_v10_0_read_wave_data,
4569 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4570 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4571 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4572 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4573 	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4574 };
4575 
4576 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4577 {
4578 	u32 gb_addr_config;
4579 
4580 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4581 	case IP_VERSION(10, 1, 10):
4582 	case IP_VERSION(10, 1, 1):
4583 	case IP_VERSION(10, 1, 2):
4584 		adev->gfx.config.max_hw_contexts = 8;
4585 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4586 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4587 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4588 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4589 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4590 		break;
4591 	case IP_VERSION(10, 3, 0):
4592 	case IP_VERSION(10, 3, 2):
4593 	case IP_VERSION(10, 3, 1):
4594 	case IP_VERSION(10, 3, 4):
4595 	case IP_VERSION(10, 3, 5):
4596 	case IP_VERSION(10, 3, 6):
4597 	case IP_VERSION(10, 3, 3):
4598 	case IP_VERSION(10, 3, 7):
4599 		adev->gfx.config.max_hw_contexts = 8;
4600 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4601 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4602 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4603 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4604 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4605 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4606 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4607 		break;
4608 	case IP_VERSION(10, 1, 3):
4609 	case IP_VERSION(10, 1, 4):
4610 		adev->gfx.config.max_hw_contexts = 8;
4611 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4612 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4613 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4614 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4615 		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4616 		break;
4617 	default:
4618 		BUG();
4619 		break;
4620 	}
4621 
4622 	adev->gfx.config.gb_addr_config = gb_addr_config;
4623 
4624 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4625 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4626 				      GB_ADDR_CONFIG, NUM_PIPES);
4627 
4628 	adev->gfx.config.max_tile_pipes =
4629 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4630 
4631 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4632 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4633 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4634 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4635 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4636 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4637 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4638 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4639 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4640 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4641 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4642 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4643 }
4644 
4645 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4646 				   int me, int pipe, int queue)
4647 {
4648 	struct amdgpu_ring *ring;
4649 	unsigned int irq_type;
4650 	unsigned int hw_prio;
4651 
4652 	ring = &adev->gfx.gfx_ring[ring_id];
4653 
4654 	ring->me = me;
4655 	ring->pipe = pipe;
4656 	ring->queue = queue;
4657 
4658 	ring->ring_obj = NULL;
4659 	ring->use_doorbell = true;
4660 
4661 	if (!ring_id)
4662 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4663 	else
4664 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4665 	ring->vm_hub = AMDGPU_GFXHUB(0);
4666 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4667 
4668 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4669 	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4670 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4671 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4672 				hw_prio, NULL);
4673 }
4674 
4675 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4676 				       int mec, int pipe, int queue)
4677 {
4678 	unsigned int irq_type;
4679 	struct amdgpu_ring *ring;
4680 	unsigned int hw_prio;
4681 
4682 	ring = &adev->gfx.compute_ring[ring_id];
4683 
4684 	/* mec0 is me1 */
4685 	ring->me = mec + 1;
4686 	ring->pipe = pipe;
4687 	ring->queue = queue;
4688 
4689 	ring->ring_obj = NULL;
4690 	ring->use_doorbell = true;
4691 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4692 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4693 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4694 	ring->vm_hub = AMDGPU_GFXHUB(0);
4695 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4696 
4697 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4698 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4699 		+ ring->pipe;
4700 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4701 			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4702 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4703 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4704 			     hw_prio, NULL);
4705 }
4706 
4707 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4708 {
4709 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4710 	uint32_t *ptr;
4711 	uint32_t inst;
4712 
4713 	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4714 	if (!ptr) {
4715 		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4716 		adev->gfx.ip_dump_core = NULL;
4717 	} else {
4718 		adev->gfx.ip_dump_core = ptr;
4719 	}
4720 
4721 	/* Allocate memory for compute queue registers for all the instances */
4722 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4723 	inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4724 		adev->gfx.mec.num_queue_per_pipe;
4725 
4726 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4727 	if (!ptr) {
4728 		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4729 		adev->gfx.ip_dump_compute_queues = NULL;
4730 	} else {
4731 		adev->gfx.ip_dump_compute_queues = ptr;
4732 	}
4733 
4734 	/* Allocate memory for gfx queue registers for all the instances */
4735 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4736 	inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4737 		adev->gfx.me.num_queue_per_pipe;
4738 
4739 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4740 	if (!ptr) {
4741 		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4742 		adev->gfx.ip_dump_gfx_queues = NULL;
4743 	} else {
4744 		adev->gfx.ip_dump_gfx_queues = ptr;
4745 	}
4746 }
4747 
4748 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4749 {
4750 	int i, j, k, r, ring_id = 0;
4751 	int xcc_id = 0;
4752 	struct amdgpu_device *adev = ip_block->adev;
4753 	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
4754 
4755 	INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
4756 
4757 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4758 	case IP_VERSION(10, 1, 10):
4759 	case IP_VERSION(10, 1, 1):
4760 	case IP_VERSION(10, 1, 2):
4761 	case IP_VERSION(10, 1, 3):
4762 	case IP_VERSION(10, 1, 4):
4763 		adev->gfx.me.num_me = 1;
4764 		adev->gfx.me.num_pipe_per_me = 1;
4765 		adev->gfx.me.num_queue_per_pipe = 8;
4766 		adev->gfx.mec.num_mec = 2;
4767 		adev->gfx.mec.num_pipe_per_mec = 4;
4768 		adev->gfx.mec.num_queue_per_pipe = 8;
4769 		break;
4770 	case IP_VERSION(10, 3, 0):
4771 	case IP_VERSION(10, 3, 2):
4772 	case IP_VERSION(10, 3, 1):
4773 	case IP_VERSION(10, 3, 4):
4774 	case IP_VERSION(10, 3, 5):
4775 	case IP_VERSION(10, 3, 6):
4776 	case IP_VERSION(10, 3, 3):
4777 	case IP_VERSION(10, 3, 7):
4778 		adev->gfx.me.num_me = 1;
4779 		adev->gfx.me.num_pipe_per_me = 2;
4780 		adev->gfx.me.num_queue_per_pipe = 2;
4781 		adev->gfx.mec.num_mec = 2;
4782 		adev->gfx.mec.num_pipe_per_mec = 4;
4783 		adev->gfx.mec.num_queue_per_pipe = 4;
4784 		break;
4785 	default:
4786 		adev->gfx.me.num_me = 1;
4787 		adev->gfx.me.num_pipe_per_me = 1;
4788 		adev->gfx.me.num_queue_per_pipe = 1;
4789 		adev->gfx.mec.num_mec = 1;
4790 		adev->gfx.mec.num_pipe_per_mec = 4;
4791 		adev->gfx.mec.num_queue_per_pipe = 8;
4792 		break;
4793 	}
4794 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4795 	case IP_VERSION(10, 1, 10):
4796 	case IP_VERSION(10, 1, 1):
4797 	case IP_VERSION(10, 1, 2):
4798 		adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;
4799 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);
4800 		if (adev->gfx.me_fw_version >= 101 &&
4801 		    adev->gfx.pfp_fw_version  >= 158 &&
4802 		    adev->gfx.mec_fw_version >= 152) {
4803 			adev->gfx.enable_cleaner_shader = true;
4804 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4805 			if (r) {
4806 				adev->gfx.enable_cleaner_shader = false;
4807 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4808 			}
4809 		}
4810 		break;
4811 	case IP_VERSION(10, 3, 0):
4812 	case IP_VERSION(10, 3, 1):
4813 	case IP_VERSION(10, 3, 2):
4814 	case IP_VERSION(10, 3, 3):
4815 	case IP_VERSION(10, 3, 4):
4816 	case IP_VERSION(10, 3, 5):
4817 		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4818 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4819 		if (adev->gfx.me_fw_version >= 64 &&
4820 		    adev->gfx.pfp_fw_version >= 100 &&
4821 		    adev->gfx.mec_fw_version >= 122) {
4822 			adev->gfx.enable_cleaner_shader = true;
4823 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4824 			if (r) {
4825 				adev->gfx.enable_cleaner_shader = false;
4826 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4827 			}
4828 		}
4829 		break;
4830 	case IP_VERSION(10, 3, 6):
4831 		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4832 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4833 		if (adev->gfx.me_fw_version >= 14 &&
4834 		    adev->gfx.pfp_fw_version >= 17 &&
4835 		    adev->gfx.mec_fw_version >= 24) {
4836 			adev->gfx.enable_cleaner_shader = true;
4837 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4838 			if (r) {
4839 				adev->gfx.enable_cleaner_shader = false;
4840 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4841 			}
4842 		}
4843 		break;
4844 	case IP_VERSION(10, 3, 7):
4845 		adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4846 		adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4847 		if (adev->gfx.me_fw_version >= 4 &&
4848 		    adev->gfx.pfp_fw_version >= 9 &&
4849 		    adev->gfx.mec_fw_version >= 12) {
4850 			adev->gfx.enable_cleaner_shader = true;
4851 			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4852 			if (r) {
4853 				adev->gfx.enable_cleaner_shader = false;
4854 				dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4855 			}
4856 		}
4857 		break;
4858 	default:
4859 		adev->gfx.enable_cleaner_shader = false;
4860 		break;
4861 	}
4862 
4863 	/* KIQ event */
4864 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4865 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4866 			      &adev->gfx.kiq[0].irq);
4867 	if (r)
4868 		return r;
4869 
4870 	/* EOP Event */
4871 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4872 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4873 			      &adev->gfx.eop_irq);
4874 	if (r)
4875 		return r;
4876 
4877 	/* Bad opcode Event */
4878 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4879 			      GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4880 			      &adev->gfx.bad_op_irq);
4881 	if (r)
4882 		return r;
4883 
4884 	/* Privileged reg */
4885 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4886 			      &adev->gfx.priv_reg_irq);
4887 	if (r)
4888 		return r;
4889 
4890 	/* Privileged inst */
4891 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4892 			      &adev->gfx.priv_inst_irq);
4893 	if (r)
4894 		return r;
4895 
4896 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4897 
4898 	gfx_v10_0_me_init(adev);
4899 
4900 	if (adev->gfx.rlc.funcs) {
4901 		if (adev->gfx.rlc.funcs->init) {
4902 			r = adev->gfx.rlc.funcs->init(adev);
4903 			if (r) {
4904 				dev_err(adev->dev, "Failed to init rlc BOs!\n");
4905 				return r;
4906 			}
4907 		}
4908 	}
4909 
4910 	r = gfx_v10_0_mec_init(adev);
4911 	if (r) {
4912 		DRM_ERROR("Failed to init MEC BOs!\n");
4913 		return r;
4914 	}
4915 
4916 	/* set up the gfx ring */
4917 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4918 		for (j = 0; j < num_queue_per_pipe; j++) {
4919 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4920 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4921 					continue;
4922 
4923 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4924 							    i, k, j);
4925 				if (r)
4926 					return r;
4927 				ring_id++;
4928 			}
4929 		}
4930 	}
4931 
4932 	ring_id = 0;
4933 	/* set up the compute queues - allocate horizontally across pipes */
4934 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4935 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4936 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4937 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4938 								     k, j))
4939 					continue;
4940 
4941 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4942 								i, k, j);
4943 				if (r)
4944 					return r;
4945 
4946 				ring_id++;
4947 			}
4948 		}
4949 	}
4950 	/* TODO: Add queue reset mask when FW fully supports it */
4951 	adev->gfx.gfx_supported_reset =
4952 		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4953 	adev->gfx.compute_supported_reset =
4954 		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4955 
4956 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4957 	if (r) {
4958 		DRM_ERROR("Failed to init KIQ BOs!\n");
4959 		return r;
4960 	}
4961 
4962 	r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4963 	if (r)
4964 		return r;
4965 
4966 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4967 	if (r)
4968 		return r;
4969 
4970 	/* allocate visible FB for rlc auto-loading fw */
4971 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4972 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4973 		if (r)
4974 			return r;
4975 	}
4976 
4977 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4978 
4979 	gfx_v10_0_gpu_early_init(adev);
4980 
4981 	gfx_v10_0_alloc_ip_dump(adev);
4982 
4983 	r = amdgpu_gfx_sysfs_init(adev);
4984 	if (r)
4985 		return r;
4986 
4987 	return 0;
4988 }
4989 
4990 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4991 {
4992 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4993 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4994 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4995 }
4996 
4997 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4998 {
4999 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
5000 			      &adev->gfx.ce.ce_fw_gpu_addr,
5001 			      (void **)&adev->gfx.ce.ce_fw_ptr);
5002 }
5003 
5004 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
5005 {
5006 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
5007 			      &adev->gfx.me.me_fw_gpu_addr,
5008 			      (void **)&adev->gfx.me.me_fw_ptr);
5009 }
5010 
5011 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
5012 {
5013 	int i;
5014 	struct amdgpu_device *adev = ip_block->adev;
5015 
5016 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5017 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
5018 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
5019 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
5020 
5021 	amdgpu_gfx_mqd_sw_fini(adev, 0);
5022 
5023 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
5024 	amdgpu_gfx_kiq_fini(adev, 0);
5025 
5026 	amdgpu_gfx_cleaner_shader_sw_fini(adev);
5027 
5028 	gfx_v10_0_pfp_fini(adev);
5029 	gfx_v10_0_ce_fini(adev);
5030 	gfx_v10_0_me_fini(adev);
5031 	gfx_v10_0_rlc_fini(adev);
5032 	gfx_v10_0_mec_fini(adev);
5033 
5034 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5035 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5036 
5037 	gfx_v10_0_free_microcode(adev);
5038 	amdgpu_gfx_sysfs_fini(adev);
5039 
5040 	kfree(adev->gfx.ip_dump_core);
5041 	kfree(adev->gfx.ip_dump_compute_queues);
5042 	kfree(adev->gfx.ip_dump_gfx_queues);
5043 
5044 	return 0;
5045 }
5046 
5047 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5048 				   u32 sh_num, u32 instance, int xcc_id)
5049 {
5050 	u32 data;
5051 
5052 	if (instance == 0xffffffff)
5053 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5054 				     INSTANCE_BROADCAST_WRITES, 1);
5055 	else
5056 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5057 				     instance);
5058 
5059 	if (se_num == 0xffffffff)
5060 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5061 				     1);
5062 	else
5063 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5064 
5065 	if (sh_num == 0xffffffff)
5066 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5067 				     1);
5068 	else
5069 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5070 
5071 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5072 }
5073 
5074 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5075 {
5076 	u32 data, mask;
5077 
5078 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5079 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5080 
5081 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5082 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5083 
5084 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5085 					 adev->gfx.config.max_sh_per_se);
5086 
5087 	return (~data) & mask;
5088 }
5089 
5090 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5091 {
5092 	int i, j;
5093 	u32 data;
5094 	u32 active_rbs = 0;
5095 	u32 bitmap;
5096 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5097 					adev->gfx.config.max_sh_per_se;
5098 
5099 	mutex_lock(&adev->grbm_idx_mutex);
5100 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5101 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5102 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
5103 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
5104 			      IP_VERSION(10, 3, 0)) ||
5105 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5106 			      IP_VERSION(10, 3, 3)) ||
5107 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5108 			      IP_VERSION(10, 3, 6))) &&
5109 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5110 				continue;
5111 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5112 			data = gfx_v10_0_get_rb_active_bitmap(adev);
5113 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5114 					       rb_bitmap_width_per_sh);
5115 		}
5116 	}
5117 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5118 	mutex_unlock(&adev->grbm_idx_mutex);
5119 
5120 	adev->gfx.config.backend_enable_mask = active_rbs;
5121 	adev->gfx.config.num_rbs = hweight32(active_rbs);
5122 }
5123 
5124 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5125 {
5126 	uint32_t num_sc;
5127 	uint32_t enabled_rb_per_sh;
5128 	uint32_t active_rb_bitmap;
5129 	uint32_t num_rb_per_sc;
5130 	uint32_t num_packer_per_sc;
5131 	uint32_t pa_sc_tile_steering_override;
5132 
5133 	/* for ASICs that integrates GFX v10.3
5134 	 * pa_sc_tile_steering_override should be set to 0
5135 	 */
5136 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5137 		return 0;
5138 
5139 	/* init num_sc */
5140 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5141 			adev->gfx.config.num_sc_per_sh;
5142 	/* init num_rb_per_sc */
5143 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5144 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
5145 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5146 	/* init num_packer_per_sc */
5147 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5148 
5149 	pa_sc_tile_steering_override = 0;
5150 	pa_sc_tile_steering_override |=
5151 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5152 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5153 	pa_sc_tile_steering_override |=
5154 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5155 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5156 	pa_sc_tile_steering_override |=
5157 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5158 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5159 
5160 	return pa_sc_tile_steering_override;
5161 }
5162 
5163 #define DEFAULT_SH_MEM_BASES	(0x6000)
5164 
5165 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5166 				uint32_t first_vmid,
5167 				uint32_t last_vmid)
5168 {
5169 	uint32_t data;
5170 	uint32_t trap_config_vmid_mask = 0;
5171 	int i;
5172 
5173 	/* Calculate trap config vmid mask */
5174 	for (i = first_vmid; i < last_vmid; i++)
5175 		trap_config_vmid_mask |= (1 << i);
5176 
5177 	data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5178 			VMID_SEL, trap_config_vmid_mask);
5179 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5180 			TRAP_EN, 1);
5181 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5182 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5183 
5184 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5185 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5186 }
5187 
5188 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5189 {
5190 	int i;
5191 	uint32_t sh_mem_bases;
5192 
5193 	/*
5194 	 * Configure apertures:
5195 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5196 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5197 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5198 	 */
5199 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5200 
5201 	mutex_lock(&adev->srbm_mutex);
5202 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5203 		nv_grbm_select(adev, 0, 0, 0, i);
5204 		/* CP and shaders */
5205 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5206 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5207 	}
5208 	nv_grbm_select(adev, 0, 0, 0, 0);
5209 	mutex_unlock(&adev->srbm_mutex);
5210 
5211 	/*
5212 	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
5213 	 * access. These should be enabled by FW for target VMIDs.
5214 	 */
5215 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5216 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5217 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5218 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5219 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5220 	}
5221 
5222 	gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5223 					AMDGPU_NUM_VMID);
5224 }
5225 
5226 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5227 {
5228 	int vmid;
5229 
5230 	/*
5231 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5232 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5233 	 * the driver can enable them for graphics. VMID0 should maintain
5234 	 * access so that HWS firmware can save/restore entries.
5235 	 */
5236 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5237 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5238 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5239 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5240 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5241 	}
5242 }
5243 
5244 
5245 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5246 {
5247 	int i, j, k;
5248 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5249 	u32 tmp, wgp_active_bitmap = 0;
5250 	u32 gcrd_targets_disable_tcp = 0;
5251 	u32 utcl_invreq_disable = 0;
5252 	/*
5253 	 * GCRD_TARGETS_DISABLE field contains
5254 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5255 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5256 	 */
5257 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5258 		2 * max_wgp_per_sh + /* TCP */
5259 		max_wgp_per_sh + /* SQC */
5260 		4); /* GL1C */
5261 	/*
5262 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5263 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5264 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5265 	 */
5266 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5267 		2 * max_wgp_per_sh + /* TCP */
5268 		2 * max_wgp_per_sh + /* SQC */
5269 		4 + /* RMI */
5270 		1); /* SQG */
5271 
5272 	mutex_lock(&adev->grbm_idx_mutex);
5273 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5274 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5275 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5276 			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5277 			/*
5278 			 * Set corresponding TCP bits for the inactive WGPs in
5279 			 * GCRD_SA_TARGETS_DISABLE
5280 			 */
5281 			gcrd_targets_disable_tcp = 0;
5282 			/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5283 			utcl_invreq_disable = 0;
5284 
5285 			for (k = 0; k < max_wgp_per_sh; k++) {
5286 				if (!(wgp_active_bitmap & (1 << k))) {
5287 					gcrd_targets_disable_tcp |= 3 << (2 * k);
5288 					gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5289 					utcl_invreq_disable |= (3 << (2 * k)) |
5290 						(3 << (2 * (max_wgp_per_sh + k)));
5291 				}
5292 			}
5293 
5294 			tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5295 			/* only override TCP & SQC bits */
5296 			tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5297 			tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5298 			WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5299 
5300 			tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5301 			/* only override TCP & SQC bits */
5302 			tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5303 			tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5304 			WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5305 		}
5306 	}
5307 
5308 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5309 	mutex_unlock(&adev->grbm_idx_mutex);
5310 }
5311 
5312 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5313 {
5314 	/* TCCs are global (not instanced). */
5315 	uint32_t tcc_disable;
5316 
5317 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5318 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5319 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5320 	} else {
5321 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5322 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5323 	}
5324 
5325 	adev->gfx.config.tcc_disabled_mask =
5326 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5327 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5328 }
5329 
5330 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5331 {
5332 	u32 tmp;
5333 	int i;
5334 
5335 	if (!amdgpu_sriov_vf(adev))
5336 		WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5337 
5338 	gfx_v10_0_setup_rb(adev);
5339 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5340 	gfx_v10_0_get_tcc_info(adev);
5341 	adev->gfx.config.pa_sc_tile_steering_override =
5342 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5343 
5344 	/* XXX SH_MEM regs */
5345 	/* where to put LDS, scratch, GPUVM in FSA64 space */
5346 	mutex_lock(&adev->srbm_mutex);
5347 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5348 		nv_grbm_select(adev, 0, 0, 0, i);
5349 		/* CP and shaders */
5350 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5351 		if (i != 0) {
5352 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5353 				(adev->gmc.private_aperture_start >> 48));
5354 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5355 				(adev->gmc.shared_aperture_start >> 48));
5356 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5357 		}
5358 	}
5359 	nv_grbm_select(adev, 0, 0, 0, 0);
5360 
5361 	mutex_unlock(&adev->srbm_mutex);
5362 
5363 	gfx_v10_0_init_compute_vmid(adev);
5364 	gfx_v10_0_init_gds_vmid(adev);
5365 
5366 }
5367 
5368 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5369 				      int me, int pipe)
5370 {
5371 	if (me != 0)
5372 		return 0;
5373 
5374 	switch (pipe) {
5375 	case 0:
5376 		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5377 	case 1:
5378 		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5379 	default:
5380 		return 0;
5381 	}
5382 }
5383 
5384 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5385 				      int me, int pipe)
5386 {
5387 	/*
5388 	 * amdgpu controls only the first MEC. That's why this function only
5389 	 * handles the setting of interrupts for this specific MEC. All other
5390 	 * pipes' interrupts are set by amdkfd.
5391 	 */
5392 	if (me != 1)
5393 		return 0;
5394 
5395 	switch (pipe) {
5396 	case 0:
5397 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5398 	case 1:
5399 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5400 	case 2:
5401 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5402 	case 3:
5403 		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5404 	default:
5405 		return 0;
5406 	}
5407 }
5408 
5409 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5410 					       bool enable)
5411 {
5412 	u32 tmp, cp_int_cntl_reg;
5413 	int i, j;
5414 
5415 	if (amdgpu_sriov_vf(adev))
5416 		return;
5417 
5418 	for (i = 0; i < adev->gfx.me.num_me; i++) {
5419 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5420 			cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5421 
5422 			if (cp_int_cntl_reg) {
5423 				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5424 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5425 						    enable ? 1 : 0);
5426 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5427 						    enable ? 1 : 0);
5428 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5429 						    enable ? 1 : 0);
5430 				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5431 						    enable ? 1 : 0);
5432 				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5433 			}
5434 		}
5435 	}
5436 }
5437 
5438 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5439 {
5440 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5441 
5442 	/* csib */
5443 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5444 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5445 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5446 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5447 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5448 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5449 	} else {
5450 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5451 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5452 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5453 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5454 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5455 	}
5456 	return 0;
5457 }
5458 
5459 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5460 {
5461 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5462 
5463 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5464 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5465 }
5466 
5467 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5468 {
5469 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5470 	udelay(50);
5471 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5472 	udelay(50);
5473 }
5474 
5475 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5476 					     bool enable)
5477 {
5478 	uint32_t rlc_pg_cntl;
5479 
5480 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5481 
5482 	if (!enable) {
5483 		/* RLC_PG_CNTL[23] = 0 (default)
5484 		 * RLC will wait for handshake acks with SMU
5485 		 * GFXOFF will be enabled
5486 		 * RLC_PG_CNTL[23] = 1
5487 		 * RLC will not issue any message to SMU
5488 		 * hence no handshake between SMU & RLC
5489 		 * GFXOFF will be disabled
5490 		 */
5491 		rlc_pg_cntl |= 0x800000;
5492 	} else
5493 		rlc_pg_cntl &= ~0x800000;
5494 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5495 }
5496 
5497 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5498 {
5499 	/*
5500 	 * TODO: enable rlc & smu handshake until smu
5501 	 * and gfxoff feature works as expected
5502 	 */
5503 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5504 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5505 
5506 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5507 	udelay(50);
5508 }
5509 
5510 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5511 {
5512 	uint32_t tmp;
5513 
5514 	/* enable Save Restore Machine */
5515 	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5516 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5517 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5518 	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5519 }
5520 
5521 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5522 {
5523 	const struct rlc_firmware_header_v2_0 *hdr;
5524 	const __le32 *fw_data;
5525 	unsigned int i, fw_size;
5526 
5527 	if (!adev->gfx.rlc_fw)
5528 		return -EINVAL;
5529 
5530 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5531 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
5532 
5533 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5534 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5535 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5536 
5537 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5538 		     RLCG_UCODE_LOADING_START_ADDRESS);
5539 
5540 	for (i = 0; i < fw_size; i++)
5541 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5542 			     le32_to_cpup(fw_data++));
5543 
5544 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5545 
5546 	return 0;
5547 }
5548 
5549 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5550 {
5551 	int r;
5552 
5553 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5554 		adev->psp.autoload_supported) {
5555 
5556 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5557 		if (r)
5558 			return r;
5559 
5560 		gfx_v10_0_init_csb(adev);
5561 
5562 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5563 
5564 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5565 			gfx_v10_0_rlc_enable_srm(adev);
5566 	} else {
5567 		if (amdgpu_sriov_vf(adev)) {
5568 			gfx_v10_0_init_csb(adev);
5569 			return 0;
5570 		}
5571 
5572 		adev->gfx.rlc.funcs->stop(adev);
5573 
5574 		/* disable CG */
5575 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5576 
5577 		/* disable PG */
5578 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5579 
5580 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5581 			/* legacy rlc firmware loading */
5582 			r = gfx_v10_0_rlc_load_microcode(adev);
5583 			if (r)
5584 				return r;
5585 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5586 			/* rlc backdoor autoload firmware */
5587 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5588 			if (r)
5589 				return r;
5590 		}
5591 
5592 		gfx_v10_0_init_csb(adev);
5593 
5594 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5595 
5596 		adev->gfx.rlc.funcs->start(adev);
5597 
5598 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5599 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5600 			if (r)
5601 				return r;
5602 		}
5603 	}
5604 
5605 	return 0;
5606 }
5607 
5608 static struct {
5609 	FIRMWARE_ID	id;
5610 	unsigned int	offset;
5611 	unsigned int	size;
5612 } rlc_autoload_info[FIRMWARE_ID_MAX];
5613 
5614 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5615 {
5616 	int ret;
5617 	RLC_TABLE_OF_CONTENT *rlc_toc;
5618 
5619 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5620 					AMDGPU_GEM_DOMAIN_GTT,
5621 					&adev->gfx.rlc.rlc_toc_bo,
5622 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5623 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5624 	if (ret) {
5625 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5626 		return ret;
5627 	}
5628 
5629 	/* Copy toc from psp sos fw to rlc toc buffer */
5630 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5631 
5632 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5633 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5634 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5635 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5636 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5637 			/* Offset needs 4KB alignment */
5638 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5639 		}
5640 
5641 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5642 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5643 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5644 
5645 		rlc_toc++;
5646 	}
5647 
5648 	return 0;
5649 }
5650 
5651 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5652 {
5653 	uint32_t total_size = 0;
5654 	FIRMWARE_ID id;
5655 	int ret;
5656 
5657 	ret = gfx_v10_0_parse_rlc_toc(adev);
5658 	if (ret) {
5659 		dev_err(adev->dev, "failed to parse rlc toc\n");
5660 		return 0;
5661 	}
5662 
5663 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5664 		total_size += rlc_autoload_info[id].size;
5665 
5666 	/* In case the offset in rlc toc ucode is aligned */
5667 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5668 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5669 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5670 
5671 	return total_size;
5672 }
5673 
5674 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5675 {
5676 	int r;
5677 	uint32_t total_size;
5678 
5679 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5680 
5681 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5682 				      AMDGPU_GEM_DOMAIN_GTT,
5683 				      &adev->gfx.rlc.rlc_autoload_bo,
5684 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5685 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5686 	if (r) {
5687 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5688 		return r;
5689 	}
5690 
5691 	return 0;
5692 }
5693 
5694 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5695 {
5696 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5697 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5698 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5699 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5700 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5701 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5702 }
5703 
5704 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5705 						       FIRMWARE_ID id,
5706 						       const void *fw_data,
5707 						       uint32_t fw_size)
5708 {
5709 	uint32_t toc_offset;
5710 	uint32_t toc_fw_size;
5711 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5712 
5713 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5714 		return;
5715 
5716 	toc_offset = rlc_autoload_info[id].offset;
5717 	toc_fw_size = rlc_autoload_info[id].size;
5718 
5719 	if (fw_size == 0)
5720 		fw_size = toc_fw_size;
5721 
5722 	if (fw_size > toc_fw_size)
5723 		fw_size = toc_fw_size;
5724 
5725 	memcpy(ptr + toc_offset, fw_data, fw_size);
5726 
5727 	if (fw_size < toc_fw_size)
5728 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5729 }
5730 
5731 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5732 {
5733 	void *data;
5734 	uint32_t size;
5735 
5736 	data = adev->gfx.rlc.rlc_toc_buf;
5737 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5738 
5739 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5740 						   FIRMWARE_ID_RLC_TOC,
5741 						   data, size);
5742 }
5743 
5744 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5745 {
5746 	const __le32 *fw_data;
5747 	uint32_t fw_size;
5748 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5749 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5750 
5751 	/* pfp ucode */
5752 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5753 		adev->gfx.pfp_fw->data;
5754 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5755 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5756 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5757 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5758 						   FIRMWARE_ID_CP_PFP,
5759 						   fw_data, fw_size);
5760 
5761 	/* ce ucode */
5762 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5763 		adev->gfx.ce_fw->data;
5764 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5765 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5766 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5767 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5768 						   FIRMWARE_ID_CP_CE,
5769 						   fw_data, fw_size);
5770 
5771 	/* me ucode */
5772 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5773 		adev->gfx.me_fw->data;
5774 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5775 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5776 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5777 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5778 						   FIRMWARE_ID_CP_ME,
5779 						   fw_data, fw_size);
5780 
5781 	/* rlc ucode */
5782 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5783 		adev->gfx.rlc_fw->data;
5784 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5785 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5786 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5787 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5788 						   FIRMWARE_ID_RLC_G_UCODE,
5789 						   fw_data, fw_size);
5790 
5791 	/* mec1 ucode */
5792 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5793 		adev->gfx.mec_fw->data;
5794 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5795 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5796 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5797 		cp_hdr->jt_size * 4;
5798 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5799 						   FIRMWARE_ID_CP_MEC,
5800 						   fw_data, fw_size);
5801 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5802 }
5803 
5804 /* Temporarily put sdma part here */
5805 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5806 {
5807 	const __le32 *fw_data;
5808 	uint32_t fw_size;
5809 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5810 	int i;
5811 
5812 	for (i = 0; i < adev->sdma.num_instances; i++) {
5813 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5814 			adev->sdma.instance[i].fw->data;
5815 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5816 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5817 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5818 
5819 		if (i == 0) {
5820 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5821 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5822 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5823 				FIRMWARE_ID_SDMA0_JT,
5824 				(uint32_t *)fw_data +
5825 				sdma_hdr->jt_offset,
5826 				sdma_hdr->jt_size * 4);
5827 		} else if (i == 1) {
5828 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5829 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5830 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5831 				FIRMWARE_ID_SDMA1_JT,
5832 				(uint32_t *)fw_data +
5833 				sdma_hdr->jt_offset,
5834 				sdma_hdr->jt_size * 4);
5835 		}
5836 	}
5837 }
5838 
5839 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5840 {
5841 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5842 	uint64_t gpu_addr;
5843 
5844 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5845 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5846 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5847 
5848 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5849 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5850 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5851 
5852 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5853 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5854 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5855 
5856 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5857 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5858 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5859 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5860 		return -EINVAL;
5861 	}
5862 
5863 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5864 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5865 		DRM_ERROR("RLC ROM should halt itself\n");
5866 		return -EINVAL;
5867 	}
5868 
5869 	return 0;
5870 }
5871 
5872 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5873 {
5874 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5875 	uint32_t tmp;
5876 	int i;
5877 	uint64_t addr;
5878 
5879 	/* Trigger an invalidation of the L1 instruction caches */
5880 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5881 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5882 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5883 
5884 	/* Wait for invalidation complete */
5885 	for (i = 0; i < usec_timeout; i++) {
5886 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5887 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5888 			INVALIDATE_CACHE_COMPLETE))
5889 			break;
5890 		udelay(1);
5891 	}
5892 
5893 	if (i >= usec_timeout) {
5894 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5895 		return -EINVAL;
5896 	}
5897 
5898 	/* Program me ucode address into intruction cache address register */
5899 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5900 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5901 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5902 			lower_32_bits(addr) & 0xFFFFF000);
5903 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5904 			upper_32_bits(addr));
5905 
5906 	return 0;
5907 }
5908 
5909 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5910 {
5911 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5912 	uint32_t tmp;
5913 	int i;
5914 	uint64_t addr;
5915 
5916 	/* Trigger an invalidation of the L1 instruction caches */
5917 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5918 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5919 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5920 
5921 	/* Wait for invalidation complete */
5922 	for (i = 0; i < usec_timeout; i++) {
5923 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5924 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5925 			INVALIDATE_CACHE_COMPLETE))
5926 			break;
5927 		udelay(1);
5928 	}
5929 
5930 	if (i >= usec_timeout) {
5931 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5932 		return -EINVAL;
5933 	}
5934 
5935 	/* Program ce ucode address into intruction cache address register */
5936 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5937 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5938 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5939 			lower_32_bits(addr) & 0xFFFFF000);
5940 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5941 			upper_32_bits(addr));
5942 
5943 	return 0;
5944 }
5945 
5946 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5947 {
5948 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5949 	uint32_t tmp;
5950 	int i;
5951 	uint64_t addr;
5952 
5953 	/* Trigger an invalidation of the L1 instruction caches */
5954 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5955 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5956 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5957 
5958 	/* Wait for invalidation complete */
5959 	for (i = 0; i < usec_timeout; i++) {
5960 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5961 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5962 			INVALIDATE_CACHE_COMPLETE))
5963 			break;
5964 		udelay(1);
5965 	}
5966 
5967 	if (i >= usec_timeout) {
5968 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5969 		return -EINVAL;
5970 	}
5971 
5972 	/* Program pfp ucode address into intruction cache address register */
5973 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5974 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5975 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5976 			lower_32_bits(addr) & 0xFFFFF000);
5977 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5978 			upper_32_bits(addr));
5979 
5980 	return 0;
5981 }
5982 
5983 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5984 {
5985 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5986 	uint32_t tmp;
5987 	int i;
5988 	uint64_t addr;
5989 
5990 	/* Trigger an invalidation of the L1 instruction caches */
5991 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5992 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5993 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5994 
5995 	/* Wait for invalidation complete */
5996 	for (i = 0; i < usec_timeout; i++) {
5997 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5998 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5999 			INVALIDATE_CACHE_COMPLETE))
6000 			break;
6001 		udelay(1);
6002 	}
6003 
6004 	if (i >= usec_timeout) {
6005 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6006 		return -EINVAL;
6007 	}
6008 
6009 	/* Program mec1 ucode address into intruction cache address register */
6010 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
6011 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
6012 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
6013 			lower_32_bits(addr) & 0xFFFFF000);
6014 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6015 			upper_32_bits(addr));
6016 
6017 	return 0;
6018 }
6019 
6020 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
6021 {
6022 	uint32_t cp_status;
6023 	uint32_t bootload_status;
6024 	int i, r;
6025 
6026 	for (i = 0; i < adev->usec_timeout; i++) {
6027 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
6028 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
6029 		if ((cp_status == 0) &&
6030 		    (REG_GET_FIELD(bootload_status,
6031 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
6032 			break;
6033 		}
6034 		udelay(1);
6035 	}
6036 
6037 	if (i >= adev->usec_timeout) {
6038 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
6039 		return -ETIMEDOUT;
6040 	}
6041 
6042 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
6043 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
6044 		if (r)
6045 			return r;
6046 
6047 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
6048 		if (r)
6049 			return r;
6050 
6051 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
6052 		if (r)
6053 			return r;
6054 
6055 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
6056 		if (r)
6057 			return r;
6058 	}
6059 
6060 	return 0;
6061 }
6062 
6063 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
6064 {
6065 	int i;
6066 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
6067 
6068 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
6069 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
6070 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
6071 
6072 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
6073 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
6074 	else
6075 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
6076 
6077 	if (amdgpu_in_reset(adev) && !enable)
6078 		return 0;
6079 
6080 	for (i = 0; i < adev->usec_timeout; i++) {
6081 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
6082 			break;
6083 		udelay(1);
6084 	}
6085 
6086 	if (i >= adev->usec_timeout)
6087 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
6088 
6089 	return 0;
6090 }
6091 
6092 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
6093 {
6094 	int r;
6095 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
6096 	const __le32 *fw_data;
6097 	unsigned int i, fw_size;
6098 	uint32_t tmp;
6099 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6100 
6101 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6102 		adev->gfx.pfp_fw->data;
6103 
6104 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6105 
6106 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6107 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6108 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6109 
6110 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6111 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6112 				      &adev->gfx.pfp.pfp_fw_obj,
6113 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
6114 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
6115 	if (r) {
6116 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6117 		gfx_v10_0_pfp_fini(adev);
6118 		return r;
6119 	}
6120 
6121 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6122 
6123 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6124 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6125 
6126 	/* Trigger an invalidation of the L1 instruction caches */
6127 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6128 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6129 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6130 
6131 	/* Wait for invalidation complete */
6132 	for (i = 0; i < usec_timeout; i++) {
6133 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6134 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6135 			INVALIDATE_CACHE_COMPLETE))
6136 			break;
6137 		udelay(1);
6138 	}
6139 
6140 	if (i >= usec_timeout) {
6141 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6142 		return -EINVAL;
6143 	}
6144 
6145 	if (amdgpu_emu_mode == 1)
6146 		adev->hdp.funcs->flush_hdp(adev, NULL);
6147 
6148 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6149 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6150 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6151 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6152 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6153 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6154 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6155 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6156 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6157 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6158 
6159 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6160 
6161 	for (i = 0; i < pfp_hdr->jt_size; i++)
6162 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6163 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6164 
6165 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6166 
6167 	return 0;
6168 }
6169 
6170 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6171 {
6172 	int r;
6173 	const struct gfx_firmware_header_v1_0 *ce_hdr;
6174 	const __le32 *fw_data;
6175 	unsigned int i, fw_size;
6176 	uint32_t tmp;
6177 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6178 
6179 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6180 		adev->gfx.ce_fw->data;
6181 
6182 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6183 
6184 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6185 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6186 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6187 
6188 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6189 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6190 				      &adev->gfx.ce.ce_fw_obj,
6191 				      &adev->gfx.ce.ce_fw_gpu_addr,
6192 				      (void **)&adev->gfx.ce.ce_fw_ptr);
6193 	if (r) {
6194 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6195 		gfx_v10_0_ce_fini(adev);
6196 		return r;
6197 	}
6198 
6199 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6200 
6201 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6202 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6203 
6204 	/* Trigger an invalidation of the L1 instruction caches */
6205 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6206 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6207 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6208 
6209 	/* Wait for invalidation complete */
6210 	for (i = 0; i < usec_timeout; i++) {
6211 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6212 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6213 			INVALIDATE_CACHE_COMPLETE))
6214 			break;
6215 		udelay(1);
6216 	}
6217 
6218 	if (i >= usec_timeout) {
6219 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6220 		return -EINVAL;
6221 	}
6222 
6223 	if (amdgpu_emu_mode == 1)
6224 		adev->hdp.funcs->flush_hdp(adev, NULL);
6225 
6226 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6227 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6228 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6229 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6230 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6231 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6232 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6233 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6234 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6235 
6236 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6237 
6238 	for (i = 0; i < ce_hdr->jt_size; i++)
6239 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6240 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6241 
6242 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6243 
6244 	return 0;
6245 }
6246 
6247 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6248 {
6249 	int r;
6250 	const struct gfx_firmware_header_v1_0 *me_hdr;
6251 	const __le32 *fw_data;
6252 	unsigned int i, fw_size;
6253 	uint32_t tmp;
6254 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6255 
6256 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
6257 		adev->gfx.me_fw->data;
6258 
6259 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6260 
6261 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6262 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6263 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6264 
6265 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6266 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6267 				      &adev->gfx.me.me_fw_obj,
6268 				      &adev->gfx.me.me_fw_gpu_addr,
6269 				      (void **)&adev->gfx.me.me_fw_ptr);
6270 	if (r) {
6271 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6272 		gfx_v10_0_me_fini(adev);
6273 		return r;
6274 	}
6275 
6276 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6277 
6278 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6279 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6280 
6281 	/* Trigger an invalidation of the L1 instruction caches */
6282 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6283 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6284 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6285 
6286 	/* Wait for invalidation complete */
6287 	for (i = 0; i < usec_timeout; i++) {
6288 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6289 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6290 			INVALIDATE_CACHE_COMPLETE))
6291 			break;
6292 		udelay(1);
6293 	}
6294 
6295 	if (i >= usec_timeout) {
6296 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6297 		return -EINVAL;
6298 	}
6299 
6300 	if (amdgpu_emu_mode == 1)
6301 		adev->hdp.funcs->flush_hdp(adev, NULL);
6302 
6303 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6304 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6305 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6306 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6307 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6308 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6309 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6310 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6311 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6312 
6313 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6314 
6315 	for (i = 0; i < me_hdr->jt_size; i++)
6316 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6317 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6318 
6319 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6320 
6321 	return 0;
6322 }
6323 
6324 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6325 {
6326 	int r;
6327 
6328 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6329 		return -EINVAL;
6330 
6331 	gfx_v10_0_cp_gfx_enable(adev, false);
6332 
6333 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6334 	if (r) {
6335 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6336 		return r;
6337 	}
6338 
6339 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6340 	if (r) {
6341 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6342 		return r;
6343 	}
6344 
6345 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6346 	if (r) {
6347 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6348 		return r;
6349 	}
6350 
6351 	return 0;
6352 }
6353 
6354 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6355 {
6356 	struct amdgpu_ring *ring;
6357 	const struct cs_section_def *sect = NULL;
6358 	const struct cs_extent_def *ext = NULL;
6359 	int r, i;
6360 	int ctx_reg_offset;
6361 
6362 	/* init the CP */
6363 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6364 		     adev->gfx.config.max_hw_contexts - 1);
6365 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6366 
6367 	gfx_v10_0_cp_gfx_enable(adev, true);
6368 
6369 	ring = &adev->gfx.gfx_ring[0];
6370 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6371 	if (r) {
6372 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6373 		return r;
6374 	}
6375 
6376 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6377 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6378 
6379 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6380 	amdgpu_ring_write(ring, 0x80000000);
6381 	amdgpu_ring_write(ring, 0x80000000);
6382 
6383 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6384 		for (ext = sect->section; ext->extent != NULL; ++ext) {
6385 			if (sect->id == SECT_CONTEXT) {
6386 				amdgpu_ring_write(ring,
6387 						  PACKET3(PACKET3_SET_CONTEXT_REG,
6388 							  ext->reg_count));
6389 				amdgpu_ring_write(ring, ext->reg_index -
6390 						  PACKET3_SET_CONTEXT_REG_START);
6391 				for (i = 0; i < ext->reg_count; i++)
6392 					amdgpu_ring_write(ring, ext->extent[i]);
6393 			}
6394 		}
6395 	}
6396 
6397 	ctx_reg_offset =
6398 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6399 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6400 	amdgpu_ring_write(ring, ctx_reg_offset);
6401 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6402 
6403 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6404 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6405 
6406 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6407 	amdgpu_ring_write(ring, 0);
6408 
6409 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6410 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6411 	amdgpu_ring_write(ring, 0x8000);
6412 	amdgpu_ring_write(ring, 0x8000);
6413 
6414 	amdgpu_ring_commit(ring);
6415 
6416 	/* submit cs packet to copy state 0 to next available state */
6417 	if (adev->gfx.num_gfx_rings > 1) {
6418 		/* maximum supported gfx ring is 2 */
6419 		ring = &adev->gfx.gfx_ring[1];
6420 		r = amdgpu_ring_alloc(ring, 2);
6421 		if (r) {
6422 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6423 			return r;
6424 		}
6425 
6426 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6427 		amdgpu_ring_write(ring, 0);
6428 
6429 		amdgpu_ring_commit(ring);
6430 	}
6431 	return 0;
6432 }
6433 
6434 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6435 					 CP_PIPE_ID pipe)
6436 {
6437 	u32 tmp;
6438 
6439 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6440 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6441 
6442 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6443 }
6444 
6445 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6446 					  struct amdgpu_ring *ring)
6447 {
6448 	u32 tmp;
6449 
6450 	if (!amdgpu_async_gfx_ring) {
6451 		tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6452 		if (ring->use_doorbell) {
6453 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6454 						DOORBELL_OFFSET, ring->doorbell_index);
6455 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6456 						DOORBELL_EN, 1);
6457 		} else {
6458 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6459 						DOORBELL_EN, 0);
6460 		}
6461 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6462 	}
6463 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6464 	case IP_VERSION(10, 3, 0):
6465 	case IP_VERSION(10, 3, 2):
6466 	case IP_VERSION(10, 3, 1):
6467 	case IP_VERSION(10, 3, 4):
6468 	case IP_VERSION(10, 3, 5):
6469 	case IP_VERSION(10, 3, 6):
6470 	case IP_VERSION(10, 3, 3):
6471 	case IP_VERSION(10, 3, 7):
6472 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6473 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6474 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6475 
6476 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6477 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6478 		break;
6479 	default:
6480 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6481 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
6482 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6483 
6484 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6485 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6486 		break;
6487 	}
6488 }
6489 
6490 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6491 {
6492 	struct amdgpu_ring *ring;
6493 	u32 tmp;
6494 	u32 rb_bufsz;
6495 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
6496 
6497 	/* Set the write pointer delay */
6498 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6499 
6500 	/* set the RB to use vmid 0 */
6501 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6502 
6503 	/* Init gfx ring 0 for pipe 0 */
6504 	mutex_lock(&adev->srbm_mutex);
6505 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6506 
6507 	/* Set ring buffer size */
6508 	ring = &adev->gfx.gfx_ring[0];
6509 	rb_bufsz = order_base_2(ring->ring_size / 8);
6510 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6511 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6512 #ifdef __BIG_ENDIAN
6513 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6514 #endif
6515 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6516 
6517 	/* Initialize the ring buffer's write pointers */
6518 	ring->wptr = 0;
6519 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6520 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6521 
6522 	/* set the wb address whether it's enabled or not */
6523 	rptr_addr = ring->rptr_gpu_addr;
6524 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6525 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6526 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6527 
6528 	wptr_gpu_addr = ring->wptr_gpu_addr;
6529 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6530 		     lower_32_bits(wptr_gpu_addr));
6531 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6532 		     upper_32_bits(wptr_gpu_addr));
6533 
6534 	mdelay(1);
6535 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6536 
6537 	rb_addr = ring->gpu_addr >> 8;
6538 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6539 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6540 
6541 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6542 
6543 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6544 	mutex_unlock(&adev->srbm_mutex);
6545 
6546 	/* Init gfx ring 1 for pipe 1 */
6547 	if (adev->gfx.num_gfx_rings > 1) {
6548 		mutex_lock(&adev->srbm_mutex);
6549 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6550 		/* maximum supported gfx ring is 2 */
6551 		ring = &adev->gfx.gfx_ring[1];
6552 		rb_bufsz = order_base_2(ring->ring_size / 8);
6553 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6554 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6555 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6556 		/* Initialize the ring buffer's write pointers */
6557 		ring->wptr = 0;
6558 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6559 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6560 		/* Set the wb address whether it's enabled or not */
6561 		rptr_addr = ring->rptr_gpu_addr;
6562 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6563 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6564 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6565 		wptr_gpu_addr = ring->wptr_gpu_addr;
6566 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6567 			     lower_32_bits(wptr_gpu_addr));
6568 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6569 			     upper_32_bits(wptr_gpu_addr));
6570 
6571 		mdelay(1);
6572 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6573 
6574 		rb_addr = ring->gpu_addr >> 8;
6575 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6576 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6577 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6578 
6579 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6580 		mutex_unlock(&adev->srbm_mutex);
6581 	}
6582 	/* Switch to pipe 0 */
6583 	mutex_lock(&adev->srbm_mutex);
6584 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6585 	mutex_unlock(&adev->srbm_mutex);
6586 
6587 	/* start the ring */
6588 	gfx_v10_0_cp_gfx_start(adev);
6589 
6590 	return 0;
6591 }
6592 
6593 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6594 {
6595 	if (enable) {
6596 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6597 		case IP_VERSION(10, 3, 0):
6598 		case IP_VERSION(10, 3, 2):
6599 		case IP_VERSION(10, 3, 1):
6600 		case IP_VERSION(10, 3, 4):
6601 		case IP_VERSION(10, 3, 5):
6602 		case IP_VERSION(10, 3, 6):
6603 		case IP_VERSION(10, 3, 3):
6604 		case IP_VERSION(10, 3, 7):
6605 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6606 			break;
6607 		default:
6608 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6609 			break;
6610 		}
6611 	} else {
6612 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6613 		case IP_VERSION(10, 3, 0):
6614 		case IP_VERSION(10, 3, 2):
6615 		case IP_VERSION(10, 3, 1):
6616 		case IP_VERSION(10, 3, 4):
6617 		case IP_VERSION(10, 3, 5):
6618 		case IP_VERSION(10, 3, 6):
6619 		case IP_VERSION(10, 3, 3):
6620 		case IP_VERSION(10, 3, 7):
6621 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6622 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6623 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6624 			break;
6625 		default:
6626 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6627 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6628 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6629 			break;
6630 		}
6631 		adev->gfx.kiq[0].ring.sched.ready = false;
6632 	}
6633 	udelay(50);
6634 }
6635 
6636 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6637 {
6638 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6639 	const __le32 *fw_data;
6640 	unsigned int i;
6641 	u32 tmp;
6642 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6643 
6644 	if (!adev->gfx.mec_fw)
6645 		return -EINVAL;
6646 
6647 	gfx_v10_0_cp_compute_enable(adev, false);
6648 
6649 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6650 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6651 
6652 	fw_data = (const __le32 *)
6653 		(adev->gfx.mec_fw->data +
6654 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6655 
6656 	/* Trigger an invalidation of the L1 instruction caches */
6657 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6658 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6659 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6660 
6661 	/* Wait for invalidation complete */
6662 	for (i = 0; i < usec_timeout; i++) {
6663 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6664 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6665 				       INVALIDATE_CACHE_COMPLETE))
6666 			break;
6667 		udelay(1);
6668 	}
6669 
6670 	if (i >= usec_timeout) {
6671 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6672 		return -EINVAL;
6673 	}
6674 
6675 	if (amdgpu_emu_mode == 1)
6676 		adev->hdp.funcs->flush_hdp(adev, NULL);
6677 
6678 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6679 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6680 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6681 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6682 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6683 
6684 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6685 		     0xFFFFF000);
6686 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6687 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6688 
6689 	/* MEC1 */
6690 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6691 
6692 	for (i = 0; i < mec_hdr->jt_size; i++)
6693 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6694 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6695 
6696 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6697 
6698 	/*
6699 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6700 	 * different microcode than MEC1.
6701 	 */
6702 
6703 	return 0;
6704 }
6705 
6706 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6707 {
6708 	uint32_t tmp;
6709 	struct amdgpu_device *adev = ring->adev;
6710 
6711 	/* tell RLC which is KIQ queue */
6712 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6713 	case IP_VERSION(10, 3, 0):
6714 	case IP_VERSION(10, 3, 2):
6715 	case IP_VERSION(10, 3, 1):
6716 	case IP_VERSION(10, 3, 4):
6717 	case IP_VERSION(10, 3, 5):
6718 	case IP_VERSION(10, 3, 6):
6719 	case IP_VERSION(10, 3, 3):
6720 	case IP_VERSION(10, 3, 7):
6721 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6722 		tmp &= 0xffffff00;
6723 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6724 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6725 		break;
6726 	default:
6727 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6728 		tmp &= 0xffffff00;
6729 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6730 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6731 		break;
6732 	}
6733 }
6734 
6735 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6736 					   struct v10_gfx_mqd *mqd,
6737 					   struct amdgpu_mqd_prop *prop)
6738 {
6739 	bool priority = 0;
6740 	u32 tmp;
6741 
6742 	/* set up default queue priority level
6743 	 * 0x0 = low priority, 0x1 = high priority
6744 	 */
6745 	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6746 		priority = 1;
6747 
6748 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6749 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6750 	mqd->cp_gfx_hqd_queue_priority = tmp;
6751 }
6752 
6753 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6754 				  struct amdgpu_mqd_prop *prop)
6755 {
6756 	struct v10_gfx_mqd *mqd = m;
6757 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6758 	uint32_t tmp;
6759 	uint32_t rb_bufsz;
6760 
6761 	/* set up gfx hqd wptr */
6762 	mqd->cp_gfx_hqd_wptr = 0;
6763 	mqd->cp_gfx_hqd_wptr_hi = 0;
6764 
6765 	/* set the pointer to the MQD */
6766 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6767 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6768 
6769 	/* set up mqd control */
6770 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6771 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6772 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6773 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6774 	mqd->cp_gfx_mqd_control = tmp;
6775 
6776 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6777 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6778 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6779 	mqd->cp_gfx_hqd_vmid = 0;
6780 
6781 	/* set up gfx queue priority */
6782 	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6783 
6784 	/* set up time quantum */
6785 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6786 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6787 	mqd->cp_gfx_hqd_quantum = tmp;
6788 
6789 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6790 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6791 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6792 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6793 
6794 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6795 	wb_gpu_addr = prop->rptr_gpu_addr;
6796 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6797 	mqd->cp_gfx_hqd_rptr_addr_hi =
6798 		upper_32_bits(wb_gpu_addr) & 0xffff;
6799 
6800 	/* set up rb_wptr_poll addr */
6801 	wb_gpu_addr = prop->wptr_gpu_addr;
6802 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6803 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6804 
6805 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6806 	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6807 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6808 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6809 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6810 #ifdef __BIG_ENDIAN
6811 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6812 #endif
6813 	mqd->cp_gfx_hqd_cntl = tmp;
6814 
6815 	/* set up cp_doorbell_control */
6816 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6817 	if (prop->use_doorbell) {
6818 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6819 				    DOORBELL_OFFSET, prop->doorbell_index);
6820 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6821 				    DOORBELL_EN, 1);
6822 	} else
6823 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6824 				    DOORBELL_EN, 0);
6825 	mqd->cp_rb_doorbell_control = tmp;
6826 
6827 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6828 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6829 
6830 	/* active the queue */
6831 	mqd->cp_gfx_hqd_active = 1;
6832 
6833 	return 0;
6834 }
6835 
6836 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6837 {
6838 	struct amdgpu_device *adev = ring->adev;
6839 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6840 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6841 
6842 	if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6843 		memset((void *)mqd, 0, sizeof(*mqd));
6844 		mutex_lock(&adev->srbm_mutex);
6845 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6846 		amdgpu_ring_init_mqd(ring);
6847 
6848 		/*
6849 		 * if there are 2 gfx rings, set the lower doorbell
6850 		 * range of the first ring, otherwise the range of
6851 		 * the second ring will override the first ring
6852 		 */
6853 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6854 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6855 
6856 		nv_grbm_select(adev, 0, 0, 0, 0);
6857 		mutex_unlock(&adev->srbm_mutex);
6858 		if (adev->gfx.me.mqd_backup[mqd_idx])
6859 			memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6860 	} else {
6861 		mutex_lock(&adev->srbm_mutex);
6862 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6863 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6864 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6865 
6866 		nv_grbm_select(adev, 0, 0, 0, 0);
6867 		mutex_unlock(&adev->srbm_mutex);
6868 		/* restore mqd with the backup copy */
6869 		if (adev->gfx.me.mqd_backup[mqd_idx])
6870 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6871 		/* reset the ring */
6872 		ring->wptr = 0;
6873 		*ring->wptr_cpu_addr = 0;
6874 		amdgpu_ring_clear_ring(ring);
6875 	}
6876 
6877 	return 0;
6878 }
6879 
6880 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6881 {
6882 	int r, i;
6883 
6884 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6885 		r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
6886 		if (r)
6887 			return r;
6888 	}
6889 
6890 	r = amdgpu_gfx_enable_kgq(adev, 0);
6891 	if (r)
6892 		return r;
6893 
6894 	return gfx_v10_0_cp_gfx_start(adev);
6895 }
6896 
6897 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6898 				      struct amdgpu_mqd_prop *prop)
6899 {
6900 	struct v10_compute_mqd *mqd = m;
6901 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6902 	uint32_t tmp;
6903 
6904 	mqd->header = 0xC0310800;
6905 	mqd->compute_pipelinestat_enable = 0x00000001;
6906 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6907 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6908 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6909 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6910 	mqd->compute_misc_reserved = 0x00000003;
6911 
6912 	eop_base_addr = prop->eop_gpu_addr >> 8;
6913 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6914 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6915 
6916 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6917 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6918 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6919 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6920 
6921 	mqd->cp_hqd_eop_control = tmp;
6922 
6923 	/* enable doorbell? */
6924 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6925 
6926 	if (prop->use_doorbell) {
6927 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6928 				    DOORBELL_OFFSET, prop->doorbell_index);
6929 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6930 				    DOORBELL_EN, 1);
6931 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6932 				    DOORBELL_SOURCE, 0);
6933 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6934 				    DOORBELL_HIT, 0);
6935 	} else {
6936 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6937 				    DOORBELL_EN, 0);
6938 	}
6939 
6940 	mqd->cp_hqd_pq_doorbell_control = tmp;
6941 
6942 	/* disable the queue if it's active */
6943 	mqd->cp_hqd_dequeue_request = 0;
6944 	mqd->cp_hqd_pq_rptr = 0;
6945 	mqd->cp_hqd_pq_wptr_lo = 0;
6946 	mqd->cp_hqd_pq_wptr_hi = 0;
6947 
6948 	/* set the pointer to the MQD */
6949 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6950 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6951 
6952 	/* set MQD vmid to 0 */
6953 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6954 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6955 	mqd->cp_mqd_control = tmp;
6956 
6957 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6958 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6959 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6960 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6961 
6962 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6963 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6964 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6965 			    (order_base_2(prop->queue_size / 4) - 1));
6966 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6967 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6968 #ifdef __BIG_ENDIAN
6969 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6970 #endif
6971 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6972 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6973 			    prop->allow_tunneling);
6974 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6975 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6976 	mqd->cp_hqd_pq_control = tmp;
6977 
6978 	/* set the wb address whether it's enabled or not */
6979 	wb_gpu_addr = prop->rptr_gpu_addr;
6980 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6981 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6982 		upper_32_bits(wb_gpu_addr) & 0xffff;
6983 
6984 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6985 	wb_gpu_addr = prop->wptr_gpu_addr;
6986 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6987 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6988 
6989 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6990 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6991 
6992 	/* set the vmid for the queue */
6993 	mqd->cp_hqd_vmid = 0;
6994 
6995 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6996 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6997 	mqd->cp_hqd_persistent_state = tmp;
6998 
6999 	/* set MIN_IB_AVAIL_SIZE */
7000 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
7001 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
7002 	mqd->cp_hqd_ib_control = tmp;
7003 
7004 	/* set static priority for a compute queue/ring */
7005 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
7006 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
7007 
7008 	mqd->cp_hqd_active = prop->hqd_active;
7009 
7010 	return 0;
7011 }
7012 
7013 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7014 {
7015 	struct amdgpu_device *adev = ring->adev;
7016 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7017 	int j;
7018 
7019 	/* inactivate the queue */
7020 	if (amdgpu_sriov_vf(adev))
7021 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7022 
7023 	/* disable wptr polling */
7024 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7025 
7026 	/* disable the queue if it's active */
7027 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7028 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7029 		for (j = 0; j < adev->usec_timeout; j++) {
7030 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7031 				break;
7032 			udelay(1);
7033 		}
7034 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7035 		       mqd->cp_hqd_dequeue_request);
7036 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7037 		       mqd->cp_hqd_pq_rptr);
7038 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7039 		       mqd->cp_hqd_pq_wptr_lo);
7040 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7041 		       mqd->cp_hqd_pq_wptr_hi);
7042 	}
7043 
7044 	/* disable doorbells */
7045 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7046 
7047 	/* write the EOP addr */
7048 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7049 	       mqd->cp_hqd_eop_base_addr_lo);
7050 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7051 	       mqd->cp_hqd_eop_base_addr_hi);
7052 
7053 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7054 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7055 	       mqd->cp_hqd_eop_control);
7056 
7057 	/* set the pointer to the MQD */
7058 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7059 	       mqd->cp_mqd_base_addr_lo);
7060 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7061 	       mqd->cp_mqd_base_addr_hi);
7062 
7063 	/* set MQD vmid to 0 */
7064 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7065 	       mqd->cp_mqd_control);
7066 
7067 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7068 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7069 	       mqd->cp_hqd_pq_base_lo);
7070 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7071 	       mqd->cp_hqd_pq_base_hi);
7072 
7073 	/* set up the HQD, this is similar to CP_RB0_CNTL */
7074 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7075 	       mqd->cp_hqd_pq_control);
7076 
7077 	/* set the wb address whether it's enabled or not */
7078 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7079 		mqd->cp_hqd_pq_rptr_report_addr_lo);
7080 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7081 		mqd->cp_hqd_pq_rptr_report_addr_hi);
7082 
7083 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7084 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7085 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
7086 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7087 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
7088 
7089 	/* enable the doorbell if requested */
7090 	if (ring->use_doorbell) {
7091 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7092 			(adev->doorbell_index.kiq * 2) << 2);
7093 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7094 			(adev->doorbell_index.userqueue_end * 2) << 2);
7095 	}
7096 
7097 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7098 	       mqd->cp_hqd_pq_doorbell_control);
7099 
7100 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7101 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7102 	       mqd->cp_hqd_pq_wptr_lo);
7103 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7104 	       mqd->cp_hqd_pq_wptr_hi);
7105 
7106 	/* set the vmid for the queue */
7107 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7108 
7109 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7110 	       mqd->cp_hqd_persistent_state);
7111 
7112 	/* activate the queue */
7113 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7114 	       mqd->cp_hqd_active);
7115 
7116 	if (ring->use_doorbell)
7117 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7118 
7119 	return 0;
7120 }
7121 
7122 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7123 {
7124 	struct amdgpu_device *adev = ring->adev;
7125 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7126 
7127 	gfx_v10_0_kiq_setting(ring);
7128 
7129 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7130 		/* reset MQD to a clean status */
7131 		if (adev->gfx.kiq[0].mqd_backup)
7132 			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7133 
7134 		/* reset ring buffer */
7135 		ring->wptr = 0;
7136 		amdgpu_ring_clear_ring(ring);
7137 
7138 		mutex_lock(&adev->srbm_mutex);
7139 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7140 		gfx_v10_0_kiq_init_register(ring);
7141 		nv_grbm_select(adev, 0, 0, 0, 0);
7142 		mutex_unlock(&adev->srbm_mutex);
7143 	} else {
7144 		memset((void *)mqd, 0, sizeof(*mqd));
7145 		if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7146 			amdgpu_ring_clear_ring(ring);
7147 		mutex_lock(&adev->srbm_mutex);
7148 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7149 		amdgpu_ring_init_mqd(ring);
7150 		gfx_v10_0_kiq_init_register(ring);
7151 		nv_grbm_select(adev, 0, 0, 0, 0);
7152 		mutex_unlock(&adev->srbm_mutex);
7153 
7154 		if (adev->gfx.kiq[0].mqd_backup)
7155 			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7156 	}
7157 
7158 	return 0;
7159 }
7160 
7161 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7162 {
7163 	struct amdgpu_device *adev = ring->adev;
7164 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7165 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
7166 
7167 	if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7168 		memset((void *)mqd, 0, sizeof(*mqd));
7169 		mutex_lock(&adev->srbm_mutex);
7170 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7171 		amdgpu_ring_init_mqd(ring);
7172 		nv_grbm_select(adev, 0, 0, 0, 0);
7173 		mutex_unlock(&adev->srbm_mutex);
7174 
7175 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7176 			memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7177 	} else {
7178 		/* restore MQD to a clean status */
7179 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7180 			memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7181 		/* reset ring buffer */
7182 		ring->wptr = 0;
7183 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7184 		amdgpu_ring_clear_ring(ring);
7185 	}
7186 
7187 	return 0;
7188 }
7189 
7190 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7191 {
7192 	gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
7193 	return 0;
7194 }
7195 
7196 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7197 {
7198 	int i, r;
7199 
7200 	gfx_v10_0_cp_compute_enable(adev, true);
7201 
7202 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7203 		r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i],
7204 					     false);
7205 		if (r)
7206 			return r;
7207 	}
7208 
7209 	return amdgpu_gfx_enable_kcq(adev, 0);
7210 }
7211 
7212 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7213 {
7214 	int r, i;
7215 	struct amdgpu_ring *ring;
7216 
7217 	if (!(adev->flags & AMD_IS_APU))
7218 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7219 
7220 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7221 		/* legacy firmware loading */
7222 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
7223 		if (r)
7224 			return r;
7225 
7226 		r = gfx_v10_0_cp_compute_load_microcode(adev);
7227 		if (r)
7228 			return r;
7229 	}
7230 
7231 	r = gfx_v10_0_kiq_resume(adev);
7232 	if (r)
7233 		return r;
7234 
7235 	r = gfx_v10_0_kcq_resume(adev);
7236 	if (r)
7237 		return r;
7238 
7239 	if (!amdgpu_async_gfx_ring) {
7240 		r = gfx_v10_0_cp_gfx_resume(adev);
7241 		if (r)
7242 			return r;
7243 	} else {
7244 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7245 		if (r)
7246 			return r;
7247 	}
7248 
7249 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7250 		ring = &adev->gfx.gfx_ring[i];
7251 		r = amdgpu_ring_test_helper(ring);
7252 		if (r)
7253 			return r;
7254 	}
7255 
7256 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7257 		ring = &adev->gfx.compute_ring[i];
7258 		r = amdgpu_ring_test_helper(ring);
7259 		if (r)
7260 			return r;
7261 	}
7262 
7263 	return 0;
7264 }
7265 
7266 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7267 {
7268 	gfx_v10_0_cp_gfx_enable(adev, enable);
7269 	gfx_v10_0_cp_compute_enable(adev, enable);
7270 }
7271 
7272 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7273 {
7274 	uint32_t data, pattern = 0xDEADBEEF;
7275 
7276 	/*
7277 	 * check if mmVGT_ESGS_RING_SIZE_UMD
7278 	 * has been remapped to mmVGT_ESGS_RING_SIZE
7279 	 */
7280 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7281 	case IP_VERSION(10, 3, 0):
7282 	case IP_VERSION(10, 3, 2):
7283 	case IP_VERSION(10, 3, 4):
7284 	case IP_VERSION(10, 3, 5):
7285 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7286 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7287 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7288 
7289 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7290 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7291 			return true;
7292 		}
7293 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7294 		break;
7295 	case IP_VERSION(10, 3, 1):
7296 	case IP_VERSION(10, 3, 3):
7297 	case IP_VERSION(10, 3, 6):
7298 	case IP_VERSION(10, 3, 7):
7299 		return true;
7300 	default:
7301 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7302 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7303 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7304 
7305 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7306 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7307 			return true;
7308 		}
7309 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7310 		break;
7311 	}
7312 
7313 	return false;
7314 }
7315 
7316 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7317 {
7318 	uint32_t data;
7319 
7320 	if (amdgpu_sriov_vf(adev))
7321 		return;
7322 
7323 	/*
7324 	 * Initialize cam_index to 0
7325 	 * index will auto-inc after each data writing
7326 	 */
7327 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7328 
7329 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7330 	case IP_VERSION(10, 3, 0):
7331 	case IP_VERSION(10, 3, 2):
7332 	case IP_VERSION(10, 3, 1):
7333 	case IP_VERSION(10, 3, 4):
7334 	case IP_VERSION(10, 3, 5):
7335 	case IP_VERSION(10, 3, 6):
7336 	case IP_VERSION(10, 3, 3):
7337 	case IP_VERSION(10, 3, 7):
7338 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7339 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7340 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7341 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7342 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7343 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7344 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7345 
7346 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7347 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7348 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7349 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7350 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7351 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7352 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7353 
7354 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7355 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7356 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7357 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7358 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7359 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7360 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7361 
7362 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7363 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7364 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7365 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7366 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7367 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7368 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7369 
7370 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7371 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7372 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7373 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7374 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7375 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7376 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7377 
7378 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7379 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7380 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7381 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7382 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7383 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7384 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7385 
7386 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7387 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7388 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7389 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7390 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7391 		break;
7392 	default:
7393 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7394 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7395 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7396 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7397 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7398 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7399 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7400 
7401 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7402 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7403 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7404 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7405 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7406 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7407 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7408 
7409 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7410 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7411 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7412 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7413 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7414 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7415 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7416 
7417 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7418 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7419 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7420 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7421 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7422 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7423 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7424 
7425 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7426 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7427 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7428 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7429 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7430 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7431 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7432 
7433 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7434 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7435 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7436 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7437 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7438 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7439 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7440 
7441 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7442 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7443 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7444 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7445 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7446 		break;
7447 	}
7448 
7449 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7450 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7451 }
7452 
7453 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7454 {
7455 	uint32_t data;
7456 
7457 	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7458 	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7459 	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7460 
7461 	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7462 	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7463 	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7464 }
7465 
7466 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7467 {
7468 	int r;
7469 	struct amdgpu_device *adev = ip_block->adev;
7470 
7471 	if (!amdgpu_emu_mode)
7472 		gfx_v10_0_init_golden_registers(adev);
7473 
7474 	amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7475 				       adev->gfx.cleaner_shader_ptr);
7476 
7477 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7478 		/**
7479 		 * For gfx 10, rlc firmware loading relies on smu firmware is
7480 		 * loaded firstly, so in direct type, it has to load smc ucode
7481 		 * here before rlc.
7482 		 */
7483 		r = amdgpu_pm_load_smu_firmware(adev, NULL);
7484 		if (r)
7485 			return r;
7486 		gfx_v10_0_disable_gpa_mode(adev);
7487 	}
7488 
7489 	/* if GRBM CAM not remapped, set up the remapping */
7490 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7491 		gfx_v10_0_setup_grbm_cam_remapping(adev);
7492 
7493 	gfx_v10_0_constants_init(adev);
7494 
7495 	r = gfx_v10_0_rlc_resume(adev);
7496 	if (r)
7497 		return r;
7498 
7499 	/*
7500 	 * init golden registers and rlc resume may override some registers,
7501 	 * reconfig them here
7502 	 */
7503 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7504 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7505 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7506 		gfx_v10_0_tcp_harvest(adev);
7507 
7508 	r = gfx_v10_0_cp_resume(adev);
7509 	if (r)
7510 		return r;
7511 
7512 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7513 		gfx_v10_3_program_pbb_mode(adev);
7514 
7515 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7516 		gfx_v10_3_set_power_brake_sequence(adev);
7517 
7518 	return r;
7519 }
7520 
7521 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7522 {
7523 	struct amdgpu_device *adev = ip_block->adev;
7524 
7525 	cancel_delayed_work_sync(&adev->gfx.idle_work);
7526 
7527 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7528 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7529 	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7530 
7531 	/* WA added for Vangogh asic fixing the SMU suspend failure
7532 	 * It needs to set power gating again during gfxoff control
7533 	 * otherwise the gfxoff disallowing will be failed to set.
7534 	 */
7535 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7536 		gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7537 
7538 	if (!adev->no_hw_access) {
7539 		if (amdgpu_async_gfx_ring) {
7540 			if (amdgpu_gfx_disable_kgq(adev, 0))
7541 				DRM_ERROR("KGQ disable failed\n");
7542 		}
7543 
7544 		if (amdgpu_gfx_disable_kcq(adev, 0))
7545 			DRM_ERROR("KCQ disable failed\n");
7546 	}
7547 
7548 	if (amdgpu_sriov_vf(adev)) {
7549 		gfx_v10_0_cp_gfx_enable(adev, false);
7550 		/* Remove the steps of clearing KIQ position.
7551 		 * It causes GFX hang when another Win guest is rendering.
7552 		 */
7553 		return 0;
7554 	}
7555 	gfx_v10_0_cp_enable(adev, false);
7556 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7557 
7558 	return 0;
7559 }
7560 
7561 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7562 {
7563 	return gfx_v10_0_hw_fini(ip_block);
7564 }
7565 
7566 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7567 {
7568 	return gfx_v10_0_hw_init(ip_block);
7569 }
7570 
7571 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
7572 {
7573 	struct amdgpu_device *adev = ip_block->adev;
7574 
7575 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7576 				GRBM_STATUS, GUI_ACTIVE))
7577 		return false;
7578 	else
7579 		return true;
7580 }
7581 
7582 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7583 {
7584 	unsigned int i;
7585 	u32 tmp;
7586 	struct amdgpu_device *adev = ip_block->adev;
7587 
7588 	for (i = 0; i < adev->usec_timeout; i++) {
7589 		/* read MC_STATUS */
7590 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7591 			GRBM_STATUS__GUI_ACTIVE_MASK;
7592 
7593 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7594 			return 0;
7595 		udelay(1);
7596 	}
7597 	return -ETIMEDOUT;
7598 }
7599 
7600 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7601 {
7602 	u32 grbm_soft_reset = 0;
7603 	u32 tmp;
7604 	struct amdgpu_device *adev = ip_block->adev;
7605 
7606 	/* GRBM_STATUS */
7607 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7608 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7609 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7610 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7611 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7612 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7613 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7614 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7615 						1);
7616 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7617 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7618 						1);
7619 	}
7620 
7621 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7622 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7623 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7624 						1);
7625 	}
7626 
7627 	/* GRBM_STATUS2 */
7628 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7629 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7630 	case IP_VERSION(10, 3, 0):
7631 	case IP_VERSION(10, 3, 2):
7632 	case IP_VERSION(10, 3, 1):
7633 	case IP_VERSION(10, 3, 4):
7634 	case IP_VERSION(10, 3, 5):
7635 	case IP_VERSION(10, 3, 6):
7636 	case IP_VERSION(10, 3, 3):
7637 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7638 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7639 							GRBM_SOFT_RESET,
7640 							SOFT_RESET_RLC,
7641 							1);
7642 		break;
7643 	default:
7644 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7645 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7646 							GRBM_SOFT_RESET,
7647 							SOFT_RESET_RLC,
7648 							1);
7649 		break;
7650 	}
7651 
7652 	if (grbm_soft_reset) {
7653 		/* stop the rlc */
7654 		gfx_v10_0_rlc_stop(adev);
7655 
7656 		/* Disable GFX parsing/prefetching */
7657 		gfx_v10_0_cp_gfx_enable(adev, false);
7658 
7659 		/* Disable MEC parsing/prefetching */
7660 		gfx_v10_0_cp_compute_enable(adev, false);
7661 
7662 		if (grbm_soft_reset) {
7663 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7664 			tmp |= grbm_soft_reset;
7665 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7666 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7667 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7668 
7669 			udelay(50);
7670 
7671 			tmp &= ~grbm_soft_reset;
7672 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7673 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7674 		}
7675 
7676 		/* Wait a little for things to settle down */
7677 		udelay(50);
7678 	}
7679 	return 0;
7680 }
7681 
7682 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7683 {
7684 	uint64_t clock, clock_lo, clock_hi, hi_check;
7685 
7686 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7687 	case IP_VERSION(10, 1, 3):
7688 	case IP_VERSION(10, 1, 4):
7689 		preempt_disable();
7690 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7691 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7692 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7693 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7694 		 * roughly every 42 seconds.
7695 		 */
7696 		if (hi_check != clock_hi) {
7697 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7698 			clock_hi = hi_check;
7699 		}
7700 		preempt_enable();
7701 		clock = clock_lo | (clock_hi << 32ULL);
7702 		break;
7703 	case IP_VERSION(10, 3, 1):
7704 	case IP_VERSION(10, 3, 3):
7705 	case IP_VERSION(10, 3, 7):
7706 		preempt_disable();
7707 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7708 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7709 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7710 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7711 		 * roughly every 42 seconds.
7712 		 */
7713 		if (hi_check != clock_hi) {
7714 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7715 			clock_hi = hi_check;
7716 		}
7717 		preempt_enable();
7718 		clock = clock_lo | (clock_hi << 32ULL);
7719 		break;
7720 	case IP_VERSION(10, 3, 6):
7721 		preempt_disable();
7722 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7723 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7724 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7725 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7726 		 * roughly every 42 seconds.
7727 		 */
7728 		if (hi_check != clock_hi) {
7729 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7730 			clock_hi = hi_check;
7731 		}
7732 		preempt_enable();
7733 		clock = clock_lo | (clock_hi << 32ULL);
7734 		break;
7735 	default:
7736 		preempt_disable();
7737 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7738 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7739 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7740 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7741 		 * roughly every 42 seconds.
7742 		 */
7743 		if (hi_check != clock_hi) {
7744 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7745 			clock_hi = hi_check;
7746 		}
7747 		preempt_enable();
7748 		clock = clock_lo | (clock_hi << 32ULL);
7749 		break;
7750 	}
7751 	return clock;
7752 }
7753 
7754 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7755 					   uint32_t vmid,
7756 					   uint32_t gds_base, uint32_t gds_size,
7757 					   uint32_t gws_base, uint32_t gws_size,
7758 					   uint32_t oa_base, uint32_t oa_size)
7759 {
7760 	struct amdgpu_device *adev = ring->adev;
7761 
7762 	/* GDS Base */
7763 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7764 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7765 				    gds_base);
7766 
7767 	/* GDS Size */
7768 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7769 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7770 				    gds_size);
7771 
7772 	/* GWS */
7773 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7774 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7775 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7776 
7777 	/* OA */
7778 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7779 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7780 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7781 }
7782 
7783 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7784 {
7785 	struct amdgpu_device *adev = ip_block->adev;
7786 
7787 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7788 
7789 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7790 	case IP_VERSION(10, 1, 10):
7791 	case IP_VERSION(10, 1, 1):
7792 	case IP_VERSION(10, 1, 2):
7793 	case IP_VERSION(10, 1, 3):
7794 	case IP_VERSION(10, 1, 4):
7795 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7796 		break;
7797 	case IP_VERSION(10, 3, 0):
7798 	case IP_VERSION(10, 3, 2):
7799 	case IP_VERSION(10, 3, 1):
7800 	case IP_VERSION(10, 3, 4):
7801 	case IP_VERSION(10, 3, 5):
7802 	case IP_VERSION(10, 3, 6):
7803 	case IP_VERSION(10, 3, 3):
7804 	case IP_VERSION(10, 3, 7):
7805 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7806 		break;
7807 	default:
7808 		break;
7809 	}
7810 
7811 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7812 					  AMDGPU_MAX_COMPUTE_RINGS);
7813 
7814 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7815 	gfx_v10_0_set_ring_funcs(adev);
7816 	gfx_v10_0_set_irq_funcs(adev);
7817 	gfx_v10_0_set_gds_init(adev);
7818 	gfx_v10_0_set_rlc_funcs(adev);
7819 	gfx_v10_0_set_mqd_funcs(adev);
7820 
7821 	/* init rlcg reg access ctrl */
7822 	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7823 
7824 	return gfx_v10_0_init_microcode(adev);
7825 }
7826 
7827 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7828 {
7829 	struct amdgpu_device *adev = ip_block->adev;
7830 	int r;
7831 
7832 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7833 	if (r)
7834 		return r;
7835 
7836 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7837 	if (r)
7838 		return r;
7839 
7840 	r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7841 	if (r)
7842 		return r;
7843 
7844 	return 0;
7845 }
7846 
7847 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7848 {
7849 	uint32_t rlc_cntl;
7850 
7851 	/* if RLC is not enabled, do nothing */
7852 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7853 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7854 }
7855 
7856 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7857 {
7858 	uint32_t data;
7859 	unsigned int i;
7860 
7861 	data = RLC_SAFE_MODE__CMD_MASK;
7862 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7863 
7864 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7865 	case IP_VERSION(10, 3, 0):
7866 	case IP_VERSION(10, 3, 2):
7867 	case IP_VERSION(10, 3, 1):
7868 	case IP_VERSION(10, 3, 4):
7869 	case IP_VERSION(10, 3, 5):
7870 	case IP_VERSION(10, 3, 6):
7871 	case IP_VERSION(10, 3, 3):
7872 	case IP_VERSION(10, 3, 7):
7873 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7874 
7875 		/* wait for RLC_SAFE_MODE */
7876 		for (i = 0; i < adev->usec_timeout; i++) {
7877 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7878 					   RLC_SAFE_MODE, CMD))
7879 				break;
7880 			udelay(1);
7881 		}
7882 		break;
7883 	default:
7884 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7885 
7886 		/* wait for RLC_SAFE_MODE */
7887 		for (i = 0; i < adev->usec_timeout; i++) {
7888 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7889 					   RLC_SAFE_MODE, CMD))
7890 				break;
7891 			udelay(1);
7892 		}
7893 		break;
7894 	}
7895 }
7896 
7897 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7898 {
7899 	uint32_t data;
7900 
7901 	data = RLC_SAFE_MODE__CMD_MASK;
7902 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7903 	case IP_VERSION(10, 3, 0):
7904 	case IP_VERSION(10, 3, 2):
7905 	case IP_VERSION(10, 3, 1):
7906 	case IP_VERSION(10, 3, 4):
7907 	case IP_VERSION(10, 3, 5):
7908 	case IP_VERSION(10, 3, 6):
7909 	case IP_VERSION(10, 3, 3):
7910 	case IP_VERSION(10, 3, 7):
7911 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7912 		break;
7913 	default:
7914 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7915 		break;
7916 	}
7917 }
7918 
7919 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7920 						      bool enable)
7921 {
7922 	uint32_t data, def;
7923 
7924 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7925 		return;
7926 
7927 	/* It is disabled by HW by default */
7928 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7929 		/* 0 - Disable some blocks' MGCG */
7930 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7931 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7932 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7933 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7934 
7935 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7936 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7937 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7938 			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7939 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7940 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7941 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7942 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7943 
7944 		if (def != data)
7945 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7946 
7947 		/* MGLS is a global flag to control all MGLS in GFX */
7948 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7949 			/* 2 - RLC memory Light sleep */
7950 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7951 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7952 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7953 				if (def != data)
7954 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7955 			}
7956 			/* 3 - CP memory Light sleep */
7957 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7958 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7959 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7960 				if (def != data)
7961 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7962 			}
7963 		}
7964 	} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7965 		/* 1 - MGCG_OVERRIDE */
7966 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7967 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7968 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7969 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7970 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7971 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7972 			 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7973 		if (def != data)
7974 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7975 
7976 		/* 2 - disable MGLS in CP */
7977 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7978 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7979 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7980 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7981 		}
7982 
7983 		/* 3 - disable MGLS in RLC */
7984 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7985 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7986 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7987 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7988 		}
7989 
7990 	}
7991 }
7992 
7993 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7994 					   bool enable)
7995 {
7996 	uint32_t data, def;
7997 
7998 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7999 		return;
8000 
8001 	/* Enable 3D CGCG/CGLS */
8002 	if (enable) {
8003 		/* write cmd to clear cgcg/cgls ov */
8004 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8005 
8006 		/* unset CGCG override */
8007 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8008 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8009 
8010 		/* update CGCG and CGLS override bits */
8011 		if (def != data)
8012 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8013 
8014 		/* enable 3Dcgcg FSM(0x0000363f) */
8015 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8016 		data = 0;
8017 
8018 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8019 			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8020 				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8021 
8022 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8023 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8024 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8025 
8026 		if (def != data)
8027 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8028 
8029 		/* set IDLE_POLL_COUNT(0x00900100) */
8030 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8031 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8032 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8033 		if (def != data)
8034 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8035 	} else {
8036 		/* Disable CGCG/CGLS */
8037 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8038 
8039 		/* disable cgcg, cgls should be disabled */
8040 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8041 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8042 
8043 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8044 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8045 
8046 		/* disable cgcg and cgls in FSM */
8047 		if (def != data)
8048 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8049 	}
8050 }
8051 
8052 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8053 						      bool enable)
8054 {
8055 	uint32_t def, data;
8056 
8057 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8058 		return;
8059 
8060 	if (enable) {
8061 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8062 
8063 		/* unset CGCG override */
8064 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8065 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8066 
8067 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8068 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8069 
8070 		/* update CGCG and CGLS override bits */
8071 		if (def != data)
8072 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8073 
8074 		/* enable cgcg FSM(0x0000363F) */
8075 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8076 		data = 0;
8077 
8078 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8079 			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8080 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8081 
8082 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8083 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8084 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8085 
8086 		if (def != data)
8087 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8088 
8089 		/* set IDLE_POLL_COUNT(0x00900100) */
8090 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8091 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8092 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8093 		if (def != data)
8094 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8095 	} else {
8096 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8097 
8098 		/* reset CGCG/CGLS bits */
8099 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8100 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8101 
8102 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8103 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8104 
8105 		/* disable cgcg and cgls in FSM */
8106 		if (def != data)
8107 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8108 	}
8109 }
8110 
8111 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8112 						      bool enable)
8113 {
8114 	uint32_t def, data;
8115 
8116 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8117 		return;
8118 
8119 	if (enable) {
8120 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8121 		/* unset FGCG override */
8122 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8123 		/* update FGCG override bits */
8124 		if (def != data)
8125 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8126 
8127 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8128 		/* unset RLC SRAM CLK GATER override */
8129 		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8130 		/* update RLC SRAM CLK GATER override bits */
8131 		if (def != data)
8132 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8133 	} else {
8134 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8135 		/* reset FGCG bits */
8136 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8137 		/* disable FGCG*/
8138 		if (def != data)
8139 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8140 
8141 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8142 		/* reset RLC SRAM CLK GATER bits */
8143 		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8144 		/* disable RLC SRAM CLK*/
8145 		if (def != data)
8146 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8147 	}
8148 }
8149 
8150 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8151 {
8152 	uint32_t reg_data = 0;
8153 	uint32_t reg_idx = 0;
8154 	uint32_t i;
8155 
8156 	const uint32_t tcp_ctrl_regs[] = {
8157 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8158 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8159 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8160 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8161 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8162 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8163 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8164 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8165 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8166 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8167 		mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8168 		mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8169 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8170 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8171 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8172 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8173 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8174 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8175 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8176 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8177 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8178 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8179 		mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8180 		mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8181 	};
8182 
8183 	const uint32_t tcp_ctrl_regs_nv12[] = {
8184 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8185 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8186 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8187 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8188 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8189 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8190 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8191 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8192 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8193 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8194 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8195 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8196 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8197 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8198 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8199 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8200 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8201 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8202 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8203 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8204 	};
8205 
8206 	const uint32_t sm_ctlr_regs[] = {
8207 		mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8208 		mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8209 		mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8210 		mmCGTS_SA1_QUAD1_SM_CTRL_REG
8211 	};
8212 
8213 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8214 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8215 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8216 				  tcp_ctrl_regs_nv12[i];
8217 			reg_data = RREG32(reg_idx);
8218 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8219 			WREG32(reg_idx, reg_data);
8220 		}
8221 	} else {
8222 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8223 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8224 				  tcp_ctrl_regs[i];
8225 			reg_data = RREG32(reg_idx);
8226 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8227 			WREG32(reg_idx, reg_data);
8228 		}
8229 	}
8230 
8231 	for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8232 		reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8233 			  sm_ctlr_regs[i];
8234 		reg_data = RREG32(reg_idx);
8235 		reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8236 		reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8237 		WREG32(reg_idx, reg_data);
8238 	}
8239 }
8240 
8241 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8242 					    bool enable)
8243 {
8244 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8245 
8246 	if (enable) {
8247 		/* enable FGCG firstly*/
8248 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8249 		/* CGCG/CGLS should be enabled after MGCG/MGLS
8250 		 * ===  MGCG + MGLS ===
8251 		 */
8252 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8253 		/* ===  CGCG /CGLS for GFX 3D Only === */
8254 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8255 		/* ===  CGCG + CGLS === */
8256 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8257 
8258 		if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8259 		     IP_VERSION(10, 1, 10)) ||
8260 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8261 		     IP_VERSION(10, 1, 1)) ||
8262 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8263 		     IP_VERSION(10, 1, 2)))
8264 			gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8265 	} else {
8266 		/* CGCG/CGLS should be disabled before MGCG/MGLS
8267 		 * ===  CGCG + CGLS ===
8268 		 */
8269 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8270 		/* ===  CGCG /CGLS for GFX 3D Only === */
8271 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8272 		/* ===  MGCG + MGLS === */
8273 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8274 		/* disable fgcg at last*/
8275 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8276 	}
8277 
8278 	if (adev->cg_flags &
8279 	    (AMD_CG_SUPPORT_GFX_MGCG |
8280 	     AMD_CG_SUPPORT_GFX_CGLS |
8281 	     AMD_CG_SUPPORT_GFX_CGCG |
8282 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
8283 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
8284 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8285 
8286 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8287 
8288 	return 0;
8289 }
8290 
8291 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8292 					       unsigned int vmid)
8293 {
8294 	u32 reg, pre_data, data;
8295 
8296 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8297 	/* not for *_SOC15 */
8298 	if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8299 		pre_data = RREG32_NO_KIQ(reg);
8300 	else
8301 		pre_data = RREG32(reg);
8302 
8303 	data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8304 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8305 
8306 	if (pre_data != data) {
8307 		if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8308 			WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8309 		} else
8310 			WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8311 	}
8312 }
8313 
8314 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8315 {
8316 	amdgpu_gfx_off_ctrl(adev, false);
8317 
8318 	gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8319 
8320 	amdgpu_gfx_off_ctrl(adev, true);
8321 }
8322 
8323 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8324 					uint32_t offset,
8325 					struct soc15_reg_rlcg *entries, int arr_size)
8326 {
8327 	int i;
8328 	uint32_t reg;
8329 
8330 	if (!entries)
8331 		return false;
8332 
8333 	for (i = 0; i < arr_size; i++) {
8334 		const struct soc15_reg_rlcg *entry;
8335 
8336 		entry = &entries[i];
8337 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8338 		if (offset == reg)
8339 			return true;
8340 	}
8341 
8342 	return false;
8343 }
8344 
8345 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8346 {
8347 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8348 }
8349 
8350 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8351 {
8352 	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8353 
8354 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8355 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8356 	else
8357 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8358 
8359 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8360 
8361 	/*
8362 	 * CGPG enablement required and the register to program the hysteresis value
8363 	 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8364 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
8365 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8366 	 *
8367 	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8368 	 * of CGPG enablement starting point.
8369 	 * Power/performance team will optimize it and might give a new value later.
8370 	 */
8371 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8372 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8373 		case IP_VERSION(10, 3, 1):
8374 		case IP_VERSION(10, 3, 3):
8375 		case IP_VERSION(10, 3, 6):
8376 		case IP_VERSION(10, 3, 7):
8377 			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8378 			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8379 			break;
8380 		default:
8381 			break;
8382 		}
8383 	}
8384 }
8385 
8386 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8387 {
8388 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8389 
8390 	gfx_v10_cntl_power_gating(adev, enable);
8391 
8392 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8393 }
8394 
8395 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8396 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8397 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8398 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8399 	.init = gfx_v10_0_rlc_init,
8400 	.get_csb_size = gfx_v10_0_get_csb_size,
8401 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8402 	.resume = gfx_v10_0_rlc_resume,
8403 	.stop = gfx_v10_0_rlc_stop,
8404 	.reset = gfx_v10_0_rlc_reset,
8405 	.start = gfx_v10_0_rlc_start,
8406 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8407 };
8408 
8409 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8410 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8411 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8412 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8413 	.init = gfx_v10_0_rlc_init,
8414 	.get_csb_size = gfx_v10_0_get_csb_size,
8415 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8416 	.resume = gfx_v10_0_rlc_resume,
8417 	.stop = gfx_v10_0_rlc_stop,
8418 	.reset = gfx_v10_0_rlc_reset,
8419 	.start = gfx_v10_0_rlc_start,
8420 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8421 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8422 };
8423 
8424 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8425 					  enum amd_powergating_state state)
8426 {
8427 	struct amdgpu_device *adev = ip_block->adev;
8428 	bool enable = (state == AMD_PG_STATE_GATE);
8429 
8430 	if (amdgpu_sriov_vf(adev))
8431 		return 0;
8432 
8433 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8434 	case IP_VERSION(10, 1, 10):
8435 	case IP_VERSION(10, 1, 1):
8436 	case IP_VERSION(10, 1, 2):
8437 	case IP_VERSION(10, 3, 0):
8438 	case IP_VERSION(10, 3, 2):
8439 	case IP_VERSION(10, 3, 4):
8440 	case IP_VERSION(10, 3, 5):
8441 		amdgpu_gfx_off_ctrl(adev, enable);
8442 		break;
8443 	case IP_VERSION(10, 3, 1):
8444 	case IP_VERSION(10, 3, 3):
8445 	case IP_VERSION(10, 3, 6):
8446 	case IP_VERSION(10, 3, 7):
8447 		if (!enable)
8448 			amdgpu_gfx_off_ctrl(adev, false);
8449 
8450 		gfx_v10_cntl_pg(adev, enable);
8451 
8452 		if (enable)
8453 			amdgpu_gfx_off_ctrl(adev, true);
8454 
8455 		break;
8456 	default:
8457 		break;
8458 	}
8459 	return 0;
8460 }
8461 
8462 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8463 					  enum amd_clockgating_state state)
8464 {
8465 	struct amdgpu_device *adev = ip_block->adev;
8466 
8467 	if (amdgpu_sriov_vf(adev))
8468 		return 0;
8469 
8470 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8471 	case IP_VERSION(10, 1, 10):
8472 	case IP_VERSION(10, 1, 1):
8473 	case IP_VERSION(10, 1, 2):
8474 	case IP_VERSION(10, 3, 0):
8475 	case IP_VERSION(10, 3, 2):
8476 	case IP_VERSION(10, 3, 1):
8477 	case IP_VERSION(10, 3, 4):
8478 	case IP_VERSION(10, 3, 5):
8479 	case IP_VERSION(10, 3, 6):
8480 	case IP_VERSION(10, 3, 3):
8481 	case IP_VERSION(10, 3, 7):
8482 		gfx_v10_0_update_gfx_clock_gating(adev,
8483 						 state == AMD_CG_STATE_GATE);
8484 		break;
8485 	default:
8486 		break;
8487 	}
8488 	return 0;
8489 }
8490 
8491 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
8492 {
8493 	struct amdgpu_device *adev = ip_block->adev;
8494 	int data;
8495 
8496 	/* AMD_CG_SUPPORT_GFX_FGCG */
8497 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8498 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8499 		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
8500 
8501 	/* AMD_CG_SUPPORT_GFX_MGCG */
8502 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8503 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8504 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
8505 
8506 	/* AMD_CG_SUPPORT_GFX_CGCG */
8507 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8508 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8509 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
8510 
8511 	/* AMD_CG_SUPPORT_GFX_CGLS */
8512 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8513 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
8514 
8515 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
8516 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8517 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8518 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8519 
8520 	/* AMD_CG_SUPPORT_GFX_CP_LS */
8521 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8522 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8523 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8524 
8525 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
8526 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8527 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8528 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8529 
8530 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
8531 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8532 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8533 }
8534 
8535 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8536 {
8537 	/* gfx10 is 32bit rptr*/
8538 	return *(uint32_t *)ring->rptr_cpu_addr;
8539 }
8540 
8541 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8542 {
8543 	struct amdgpu_device *adev = ring->adev;
8544 	u64 wptr;
8545 
8546 	/* XXX check if swapping is necessary on BE */
8547 	if (ring->use_doorbell) {
8548 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8549 	} else {
8550 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8551 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8552 	}
8553 
8554 	return wptr;
8555 }
8556 
8557 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8558 {
8559 	struct amdgpu_device *adev = ring->adev;
8560 
8561 	if (ring->use_doorbell) {
8562 		/* XXX check if swapping is necessary on BE */
8563 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8564 			     ring->wptr);
8565 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8566 	} else {
8567 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8568 			     lower_32_bits(ring->wptr));
8569 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8570 			     upper_32_bits(ring->wptr));
8571 	}
8572 }
8573 
8574 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8575 {
8576 	/* gfx10 hardware is 32bit rptr */
8577 	return *(uint32_t *)ring->rptr_cpu_addr;
8578 }
8579 
8580 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8581 {
8582 	u64 wptr;
8583 
8584 	/* XXX check if swapping is necessary on BE */
8585 	if (ring->use_doorbell)
8586 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8587 	else
8588 		BUG();
8589 	return wptr;
8590 }
8591 
8592 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8593 {
8594 	struct amdgpu_device *adev = ring->adev;
8595 
8596 	if (ring->use_doorbell) {
8597 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8598 			     ring->wptr);
8599 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8600 	} else {
8601 		BUG(); /* only DOORBELL method supported on gfx10 now */
8602 	}
8603 }
8604 
8605 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8606 {
8607 	struct amdgpu_device *adev = ring->adev;
8608 	u32 ref_and_mask, reg_mem_engine;
8609 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8610 
8611 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8612 		switch (ring->me) {
8613 		case 1:
8614 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8615 			break;
8616 		case 2:
8617 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8618 			break;
8619 		default:
8620 			return;
8621 		}
8622 		reg_mem_engine = 0;
8623 	} else {
8624 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8625 		reg_mem_engine = 1; /* pfp */
8626 	}
8627 
8628 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8629 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8630 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8631 			       ref_and_mask, ref_and_mask, 0x20);
8632 }
8633 
8634 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8635 				       struct amdgpu_job *job,
8636 				       struct amdgpu_ib *ib,
8637 				       uint32_t flags)
8638 {
8639 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8640 	u32 header, control = 0;
8641 
8642 	if (ib->flags & AMDGPU_IB_FLAG_CE)
8643 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8644 	else
8645 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8646 
8647 	control |= ib->length_dw | (vmid << 24);
8648 
8649 	if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8650 		control |= INDIRECT_BUFFER_PRE_ENB(1);
8651 
8652 		if (flags & AMDGPU_IB_PREEMPTED)
8653 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
8654 
8655 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8656 			gfx_v10_0_ring_emit_de_meta(ring,
8657 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8658 	}
8659 
8660 	amdgpu_ring_write(ring, header);
8661 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8662 	amdgpu_ring_write(ring,
8663 #ifdef __BIG_ENDIAN
8664 		(2 << 0) |
8665 #endif
8666 		lower_32_bits(ib->gpu_addr));
8667 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8668 	amdgpu_ring_write(ring, control);
8669 }
8670 
8671 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8672 					   struct amdgpu_job *job,
8673 					   struct amdgpu_ib *ib,
8674 					   uint32_t flags)
8675 {
8676 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8677 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8678 
8679 	/* Currently, there is a high possibility to get wave ID mismatch
8680 	 * between ME and GDS, leading to a hw deadlock, because ME generates
8681 	 * different wave IDs than the GDS expects. This situation happens
8682 	 * randomly when at least 5 compute pipes use GDS ordered append.
8683 	 * The wave IDs generated by ME are also wrong after suspend/resume.
8684 	 * Those are probably bugs somewhere else in the kernel driver.
8685 	 *
8686 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8687 	 * GDS to 0 for this ring (me/pipe).
8688 	 */
8689 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8690 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8691 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8692 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8693 	}
8694 
8695 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8696 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8697 	amdgpu_ring_write(ring,
8698 #ifdef __BIG_ENDIAN
8699 				(2 << 0) |
8700 #endif
8701 				lower_32_bits(ib->gpu_addr));
8702 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8703 	amdgpu_ring_write(ring, control);
8704 }
8705 
8706 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8707 				     u64 seq, unsigned int flags)
8708 {
8709 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8710 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8711 
8712 	/* RELEASE_MEM - flush caches, send int */
8713 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8714 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8715 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8716 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8717 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8718 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8719 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8720 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8721 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8722 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8723 
8724 	/*
8725 	 * the address should be Qword aligned if 64bit write, Dword
8726 	 * aligned if only send 32bit data low (discard data high)
8727 	 */
8728 	if (write64bit)
8729 		BUG_ON(addr & 0x7);
8730 	else
8731 		BUG_ON(addr & 0x3);
8732 	amdgpu_ring_write(ring, lower_32_bits(addr));
8733 	amdgpu_ring_write(ring, upper_32_bits(addr));
8734 	amdgpu_ring_write(ring, lower_32_bits(seq));
8735 	amdgpu_ring_write(ring, upper_32_bits(seq));
8736 	amdgpu_ring_write(ring, 0);
8737 }
8738 
8739 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8740 {
8741 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8742 	uint32_t seq = ring->fence_drv.sync_seq;
8743 	uint64_t addr = ring->fence_drv.gpu_addr;
8744 
8745 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8746 			       upper_32_bits(addr), seq, 0xffffffff, 4);
8747 }
8748 
8749 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8750 				   uint16_t pasid, uint32_t flush_type,
8751 				   bool all_hub, uint8_t dst_sel)
8752 {
8753 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8754 	amdgpu_ring_write(ring,
8755 			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8756 			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8757 			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8758 			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8759 }
8760 
8761 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8762 					 unsigned int vmid, uint64_t pd_addr)
8763 {
8764 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8765 
8766 	/* compute doesn't have PFP */
8767 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8768 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
8769 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8770 		amdgpu_ring_write(ring, 0x0);
8771 	}
8772 }
8773 
8774 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8775 					  u64 seq, unsigned int flags)
8776 {
8777 	struct amdgpu_device *adev = ring->adev;
8778 
8779 	/* we only allocate 32bit for each seq wb address */
8780 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8781 
8782 	/* write fence seq to the "addr" */
8783 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8784 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8785 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8786 	amdgpu_ring_write(ring, lower_32_bits(addr));
8787 	amdgpu_ring_write(ring, upper_32_bits(addr));
8788 	amdgpu_ring_write(ring, lower_32_bits(seq));
8789 
8790 	if (flags & AMDGPU_FENCE_FLAG_INT) {
8791 		/* set register to trigger INT */
8792 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8793 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8794 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8795 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8796 		amdgpu_ring_write(ring, 0);
8797 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8798 	}
8799 }
8800 
8801 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8802 {
8803 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8804 	amdgpu_ring_write(ring, 0);
8805 }
8806 
8807 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8808 					 uint32_t flags)
8809 {
8810 	uint32_t dw2 = 0;
8811 
8812 	if (ring->adev->gfx.mcbp)
8813 		gfx_v10_0_ring_emit_ce_meta(ring,
8814 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8815 
8816 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8817 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8818 		/* set load_global_config & load_global_uconfig */
8819 		dw2 |= 0x8001;
8820 		/* set load_cs_sh_regs */
8821 		dw2 |= 0x01000000;
8822 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
8823 		dw2 |= 0x10002;
8824 
8825 		/* set load_ce_ram if preamble presented */
8826 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8827 			dw2 |= 0x10000000;
8828 	} else {
8829 		/* still load_ce_ram if this is the first time preamble presented
8830 		 * although there is no context switch happens.
8831 		 */
8832 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8833 			dw2 |= 0x10000000;
8834 	}
8835 
8836 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8837 	amdgpu_ring_write(ring, dw2);
8838 	amdgpu_ring_write(ring, 0);
8839 }
8840 
8841 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8842 						       uint64_t addr)
8843 {
8844 	unsigned int ret;
8845 
8846 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8847 	amdgpu_ring_write(ring, lower_32_bits(addr));
8848 	amdgpu_ring_write(ring, upper_32_bits(addr));
8849 	/* discard following DWs if *cond_exec_gpu_addr==0 */
8850 	amdgpu_ring_write(ring, 0);
8851 	ret = ring->wptr & ring->buf_mask;
8852 	/* patch dummy value later */
8853 	amdgpu_ring_write(ring, 0);
8854 
8855 	return ret;
8856 }
8857 
8858 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8859 {
8860 	int i, r = 0;
8861 	struct amdgpu_device *adev = ring->adev;
8862 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8863 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8864 	unsigned long flags;
8865 
8866 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8867 		return -EINVAL;
8868 
8869 	spin_lock_irqsave(&kiq->ring_lock, flags);
8870 
8871 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8872 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8873 		return -ENOMEM;
8874 	}
8875 
8876 	/* assert preemption condition */
8877 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8878 
8879 	/* assert IB preemption, emit the trailing fence */
8880 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8881 				   ring->trail_fence_gpu_addr,
8882 				   ++ring->trail_seq);
8883 	amdgpu_ring_commit(kiq_ring);
8884 
8885 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8886 
8887 	/* poll the trailing fence */
8888 	for (i = 0; i < adev->usec_timeout; i++) {
8889 		if (ring->trail_seq ==
8890 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8891 			break;
8892 		udelay(1);
8893 	}
8894 
8895 	if (i >= adev->usec_timeout) {
8896 		r = -EINVAL;
8897 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8898 	}
8899 
8900 	/* deassert preemption condition */
8901 	amdgpu_ring_set_preempt_cond_exec(ring, true);
8902 	return r;
8903 }
8904 
8905 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8906 {
8907 	struct amdgpu_device *adev = ring->adev;
8908 	struct v10_ce_ib_state ce_payload = {0};
8909 	uint64_t offset, ce_payload_gpu_addr;
8910 	void *ce_payload_cpu_addr;
8911 	int cnt;
8912 
8913 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8914 
8915 	offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8916 	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8917 	ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8918 
8919 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8920 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8921 				 WRITE_DATA_DST_SEL(8) |
8922 				 WR_CONFIRM) |
8923 				 WRITE_DATA_CACHE_POLICY(0));
8924 	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8925 	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8926 
8927 	if (resume)
8928 		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8929 					   sizeof(ce_payload) >> 2);
8930 	else
8931 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8932 					   sizeof(ce_payload) >> 2);
8933 }
8934 
8935 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8936 {
8937 	struct amdgpu_device *adev = ring->adev;
8938 	struct v10_de_ib_state de_payload = {0};
8939 	uint64_t offset, gds_addr, de_payload_gpu_addr;
8940 	void *de_payload_cpu_addr;
8941 	int cnt;
8942 
8943 	offset = offsetof(struct v10_gfx_meta_data, de_payload);
8944 	de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8945 	de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8946 
8947 	gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8948 			 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8949 			 PAGE_SIZE);
8950 
8951 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8952 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8953 
8954 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8955 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8956 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8957 				 WRITE_DATA_DST_SEL(8) |
8958 				 WR_CONFIRM) |
8959 				 WRITE_DATA_CACHE_POLICY(0));
8960 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8961 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8962 
8963 	if (resume)
8964 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8965 					   sizeof(de_payload) >> 2);
8966 	else
8967 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8968 					   sizeof(de_payload) >> 2);
8969 }
8970 
8971 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8972 				    bool secure)
8973 {
8974 	uint32_t v = secure ? FRAME_TMZ : 0;
8975 
8976 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8977 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8978 }
8979 
8980 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8981 				     uint32_t reg_val_offs)
8982 {
8983 	struct amdgpu_device *adev = ring->adev;
8984 
8985 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8986 	amdgpu_ring_write(ring, 0 |	/* src: register*/
8987 				(5 << 8) |	/* dst: memory */
8988 				(1 << 20));	/* write confirm */
8989 	amdgpu_ring_write(ring, reg);
8990 	amdgpu_ring_write(ring, 0);
8991 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8992 				reg_val_offs * 4));
8993 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8994 				reg_val_offs * 4));
8995 }
8996 
8997 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8998 				   uint32_t val)
8999 {
9000 	uint32_t cmd = 0;
9001 
9002 	switch (ring->funcs->type) {
9003 	case AMDGPU_RING_TYPE_GFX:
9004 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9005 		break;
9006 	case AMDGPU_RING_TYPE_KIQ:
9007 		cmd = (1 << 16); /* no inc addr */
9008 		break;
9009 	default:
9010 		cmd = WR_CONFIRM;
9011 		break;
9012 	}
9013 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9014 	amdgpu_ring_write(ring, cmd);
9015 	amdgpu_ring_write(ring, reg);
9016 	amdgpu_ring_write(ring, 0);
9017 	amdgpu_ring_write(ring, val);
9018 }
9019 
9020 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9021 					uint32_t val, uint32_t mask)
9022 {
9023 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9024 }
9025 
9026 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9027 						   uint32_t reg0, uint32_t reg1,
9028 						   uint32_t ref, uint32_t mask)
9029 {
9030 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9031 	struct amdgpu_device *adev = ring->adev;
9032 	bool fw_version_ok = false;
9033 
9034 	fw_version_ok = adev->gfx.cp_fw_write_wait;
9035 
9036 	if (fw_version_ok)
9037 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9038 				       ref, mask, 0x20);
9039 	else
9040 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9041 							   ref, mask);
9042 }
9043 
9044 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9045 					 unsigned int vmid)
9046 {
9047 	struct amdgpu_device *adev = ring->adev;
9048 	uint32_t value = 0;
9049 
9050 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9051 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9052 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9053 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9054 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9055 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9056 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9057 }
9058 
9059 static void
9060 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9061 				      uint32_t me, uint32_t pipe,
9062 				      enum amdgpu_interrupt_state state)
9063 {
9064 	uint32_t cp_int_cntl, cp_int_cntl_reg;
9065 
9066 	if (!me) {
9067 		switch (pipe) {
9068 		case 0:
9069 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9070 			break;
9071 		case 1:
9072 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9073 			break;
9074 		default:
9075 			DRM_DEBUG("invalid pipe %d\n", pipe);
9076 			return;
9077 		}
9078 	} else {
9079 		DRM_DEBUG("invalid me %d\n", me);
9080 		return;
9081 	}
9082 
9083 	switch (state) {
9084 	case AMDGPU_IRQ_STATE_DISABLE:
9085 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9086 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9087 					    TIME_STAMP_INT_ENABLE, 0);
9088 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9089 		break;
9090 	case AMDGPU_IRQ_STATE_ENABLE:
9091 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9092 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9093 					    TIME_STAMP_INT_ENABLE, 1);
9094 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9095 		break;
9096 	default:
9097 		break;
9098 	}
9099 }
9100 
9101 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9102 						     int me, int pipe,
9103 						     enum amdgpu_interrupt_state state)
9104 {
9105 	u32 mec_int_cntl, mec_int_cntl_reg;
9106 
9107 	/*
9108 	 * amdgpu controls only the first MEC. That's why this function only
9109 	 * handles the setting of interrupts for this specific MEC. All other
9110 	 * pipes' interrupts are set by amdkfd.
9111 	 */
9112 
9113 	if (me == 1) {
9114 		switch (pipe) {
9115 		case 0:
9116 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9117 			break;
9118 		case 1:
9119 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9120 			break;
9121 		case 2:
9122 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9123 			break;
9124 		case 3:
9125 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9126 			break;
9127 		default:
9128 			DRM_DEBUG("invalid pipe %d\n", pipe);
9129 			return;
9130 		}
9131 	} else {
9132 		DRM_DEBUG("invalid me %d\n", me);
9133 		return;
9134 	}
9135 
9136 	switch (state) {
9137 	case AMDGPU_IRQ_STATE_DISABLE:
9138 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9139 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9140 					     TIME_STAMP_INT_ENABLE, 0);
9141 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9142 		break;
9143 	case AMDGPU_IRQ_STATE_ENABLE:
9144 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9145 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9146 					     TIME_STAMP_INT_ENABLE, 1);
9147 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9148 		break;
9149 	default:
9150 		break;
9151 	}
9152 }
9153 
9154 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9155 					    struct amdgpu_irq_src *src,
9156 					    unsigned int type,
9157 					    enum amdgpu_interrupt_state state)
9158 {
9159 	switch (type) {
9160 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9161 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9162 		break;
9163 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9164 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9165 		break;
9166 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9167 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9168 		break;
9169 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9170 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9171 		break;
9172 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9173 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9174 		break;
9175 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9176 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9177 		break;
9178 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9179 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9180 		break;
9181 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9182 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9183 		break;
9184 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9185 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9186 		break;
9187 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9188 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9189 		break;
9190 	default:
9191 		break;
9192 	}
9193 	return 0;
9194 }
9195 
9196 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9197 			     struct amdgpu_irq_src *source,
9198 			     struct amdgpu_iv_entry *entry)
9199 {
9200 	int i;
9201 	u8 me_id, pipe_id, queue_id;
9202 	struct amdgpu_ring *ring;
9203 
9204 	DRM_DEBUG("IH: CP EOP\n");
9205 
9206 	me_id = (entry->ring_id & 0x0c) >> 2;
9207 	pipe_id = (entry->ring_id & 0x03) >> 0;
9208 	queue_id = (entry->ring_id & 0x70) >> 4;
9209 
9210 	switch (me_id) {
9211 	case 0:
9212 		if (pipe_id == 0)
9213 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9214 		else
9215 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9216 		break;
9217 	case 1:
9218 	case 2:
9219 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9220 			ring = &adev->gfx.compute_ring[i];
9221 			/* Per-queue interrupt is supported for MEC starting from VI.
9222 			 * The interrupt can only be enabled/disabled per pipe instead
9223 			 * of per queue.
9224 			 */
9225 			if ((ring->me == me_id) &&
9226 			    (ring->pipe == pipe_id) &&
9227 			    (ring->queue == queue_id))
9228 				amdgpu_fence_process(ring);
9229 		}
9230 		break;
9231 	}
9232 
9233 	return 0;
9234 }
9235 
9236 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9237 					      struct amdgpu_irq_src *source,
9238 					      unsigned int type,
9239 					      enum amdgpu_interrupt_state state)
9240 {
9241 	u32 cp_int_cntl_reg, cp_int_cntl;
9242 	int i, j;
9243 
9244 	switch (state) {
9245 	case AMDGPU_IRQ_STATE_DISABLE:
9246 	case AMDGPU_IRQ_STATE_ENABLE:
9247 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9248 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9249 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9250 
9251 				if (cp_int_cntl_reg) {
9252 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9253 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9254 								    PRIV_REG_INT_ENABLE,
9255 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9256 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9257 				}
9258 			}
9259 		}
9260 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9261 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9262 				/* MECs start at 1 */
9263 				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9264 
9265 				if (cp_int_cntl_reg) {
9266 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9267 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9268 								    PRIV_REG_INT_ENABLE,
9269 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9270 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9271 				}
9272 			}
9273 		}
9274 		break;
9275 	default:
9276 		break;
9277 	}
9278 
9279 	return 0;
9280 }
9281 
9282 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9283 					    struct amdgpu_irq_src *source,
9284 					    unsigned type,
9285 					    enum amdgpu_interrupt_state state)
9286 {
9287 	u32 cp_int_cntl_reg, cp_int_cntl;
9288 	int i, j;
9289 
9290 	switch (state) {
9291 	case AMDGPU_IRQ_STATE_DISABLE:
9292 	case AMDGPU_IRQ_STATE_ENABLE:
9293 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9294 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9295 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9296 
9297 				if (cp_int_cntl_reg) {
9298 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9299 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9300 								    OPCODE_ERROR_INT_ENABLE,
9301 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9302 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9303 				}
9304 			}
9305 		}
9306 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9307 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9308 				/* MECs start at 1 */
9309 				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9310 
9311 				if (cp_int_cntl_reg) {
9312 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9313 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9314 								    OPCODE_ERROR_INT_ENABLE,
9315 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9316 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9317 				}
9318 			}
9319 		}
9320 		break;
9321 	default:
9322 		break;
9323 	}
9324 	return 0;
9325 }
9326 
9327 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9328 					       struct amdgpu_irq_src *source,
9329 					       unsigned int type,
9330 					       enum amdgpu_interrupt_state state)
9331 {
9332 	u32 cp_int_cntl_reg, cp_int_cntl;
9333 	int i, j;
9334 
9335 	switch (state) {
9336 	case AMDGPU_IRQ_STATE_DISABLE:
9337 	case AMDGPU_IRQ_STATE_ENABLE:
9338 		for (i = 0; i < adev->gfx.me.num_me; i++) {
9339 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9340 				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9341 
9342 				if (cp_int_cntl_reg) {
9343 					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9344 					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9345 								    PRIV_INSTR_INT_ENABLE,
9346 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9347 					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9348 				}
9349 			}
9350 		}
9351 		break;
9352 	default:
9353 		break;
9354 	}
9355 
9356 	return 0;
9357 }
9358 
9359 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9360 					struct amdgpu_iv_entry *entry)
9361 {
9362 	u8 me_id, pipe_id, queue_id;
9363 	struct amdgpu_ring *ring;
9364 	int i;
9365 
9366 	me_id = (entry->ring_id & 0x0c) >> 2;
9367 	pipe_id = (entry->ring_id & 0x03) >> 0;
9368 	queue_id = (entry->ring_id & 0x70) >> 4;
9369 
9370 	switch (me_id) {
9371 	case 0:
9372 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9373 			ring = &adev->gfx.gfx_ring[i];
9374 			if (ring->me == me_id && ring->pipe == pipe_id &&
9375 			    ring->queue == queue_id)
9376 				drm_sched_fault(&ring->sched);
9377 		}
9378 		break;
9379 	case 1:
9380 	case 2:
9381 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9382 			ring = &adev->gfx.compute_ring[i];
9383 			if (ring->me == me_id && ring->pipe == pipe_id &&
9384 			    ring->queue == queue_id)
9385 				drm_sched_fault(&ring->sched);
9386 		}
9387 		break;
9388 	default:
9389 		BUG();
9390 	}
9391 }
9392 
9393 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9394 				  struct amdgpu_irq_src *source,
9395 				  struct amdgpu_iv_entry *entry)
9396 {
9397 	DRM_ERROR("Illegal register access in command stream\n");
9398 	gfx_v10_0_handle_priv_fault(adev, entry);
9399 	return 0;
9400 }
9401 
9402 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9403 				struct amdgpu_irq_src *source,
9404 				struct amdgpu_iv_entry *entry)
9405 {
9406 	DRM_ERROR("Illegal opcode in command stream \n");
9407 	gfx_v10_0_handle_priv_fault(adev, entry);
9408 	return 0;
9409 }
9410 
9411 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9412 				   struct amdgpu_irq_src *source,
9413 				   struct amdgpu_iv_entry *entry)
9414 {
9415 	DRM_ERROR("Illegal instruction in command stream\n");
9416 	gfx_v10_0_handle_priv_fault(adev, entry);
9417 	return 0;
9418 }
9419 
9420 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9421 					     struct amdgpu_irq_src *src,
9422 					     unsigned int type,
9423 					     enum amdgpu_interrupt_state state)
9424 {
9425 	uint32_t tmp, target;
9426 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9427 
9428 	if (ring->me == 1)
9429 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9430 	else
9431 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9432 	target += ring->pipe;
9433 
9434 	switch (type) {
9435 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9436 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
9437 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9438 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9439 					    GENERIC2_INT_ENABLE, 0);
9440 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9441 
9442 			tmp = RREG32_SOC15_IP(GC, target);
9443 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9444 					    GENERIC2_INT_ENABLE, 0);
9445 			WREG32_SOC15_IP(GC, target, tmp);
9446 		} else {
9447 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9448 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9449 					    GENERIC2_INT_ENABLE, 1);
9450 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9451 
9452 			tmp = RREG32_SOC15_IP(GC, target);
9453 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9454 					    GENERIC2_INT_ENABLE, 1);
9455 			WREG32_SOC15_IP(GC, target, tmp);
9456 		}
9457 		break;
9458 	default:
9459 		BUG(); /* kiq only support GENERIC2_INT now */
9460 		break;
9461 	}
9462 	return 0;
9463 }
9464 
9465 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9466 			     struct amdgpu_irq_src *source,
9467 			     struct amdgpu_iv_entry *entry)
9468 {
9469 	u8 me_id, pipe_id, queue_id;
9470 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9471 
9472 	me_id = (entry->ring_id & 0x0c) >> 2;
9473 	pipe_id = (entry->ring_id & 0x03) >> 0;
9474 	queue_id = (entry->ring_id & 0x70) >> 4;
9475 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9476 		   me_id, pipe_id, queue_id);
9477 
9478 	amdgpu_fence_process(ring);
9479 	return 0;
9480 }
9481 
9482 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9483 {
9484 	const unsigned int gcr_cntl =
9485 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9486 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9487 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9488 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9489 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9490 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9491 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9492 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9493 
9494 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9495 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9496 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9497 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9498 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9499 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9500 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9501 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9502 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9503 }
9504 
9505 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9506 {
9507 	/* Header itself is a NOP packet */
9508 	if (num_nop == 1) {
9509 		amdgpu_ring_write(ring, ring->funcs->nop);
9510 		return;
9511 	}
9512 
9513 	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9514 	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9515 
9516 	/* Header is at index 0, followed by num_nops - 1 NOP packet's */
9517 	amdgpu_ring_insert_nop(ring, num_nop - 1);
9518 }
9519 
9520 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9521 {
9522 	struct amdgpu_device *adev = ring->adev;
9523 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9524 	struct amdgpu_ring *kiq_ring = &kiq->ring;
9525 	unsigned long flags;
9526 	u32 tmp;
9527 	u64 addr;
9528 	int r;
9529 
9530 	if (amdgpu_sriov_vf(adev))
9531 		return -EINVAL;
9532 
9533 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9534 		return -EINVAL;
9535 
9536 	spin_lock_irqsave(&kiq->ring_lock, flags);
9537 
9538 	if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9539 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9540 		return -ENOMEM;
9541 	}
9542 
9543 	addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9544 		offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9545 	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9546 	if (ring->pipe == 0)
9547 		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9548 	else
9549 		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9550 
9551 	gfx_v10_0_ring_emit_wreg(kiq_ring,
9552 				 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9553 	gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9554 			       lower_32_bits(addr), upper_32_bits(addr),
9555 			       0, 1, 0x20);
9556 	gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9557 				     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9558 	kiq->pmf->kiq_map_queues(kiq_ring, ring);
9559 	amdgpu_ring_commit(kiq_ring);
9560 
9561 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9562 
9563 	r = amdgpu_ring_test_ring(kiq_ring);
9564 	if (r)
9565 		return r;
9566 
9567 	r = gfx_v10_0_kgq_init_queue(ring, true);
9568 	if (r) {
9569 		DRM_ERROR("fail to init kgq\n");
9570 		return r;
9571 	}
9572 
9573 	return amdgpu_ring_test_ring(ring);
9574 }
9575 
9576 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9577 			       unsigned int vmid)
9578 {
9579 	struct amdgpu_device *adev = ring->adev;
9580 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9581 	struct amdgpu_ring *kiq_ring = &kiq->ring;
9582 	unsigned long flags;
9583 	int i, r;
9584 
9585 	if (amdgpu_sriov_vf(adev))
9586 		return -EINVAL;
9587 
9588 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9589 		return -EINVAL;
9590 
9591 	spin_lock_irqsave(&kiq->ring_lock, flags);
9592 
9593 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9594 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9595 		return -ENOMEM;
9596 	}
9597 
9598 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9599 				   0, 0);
9600 	amdgpu_ring_commit(kiq_ring);
9601 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9602 
9603 	r = amdgpu_ring_test_ring(kiq_ring);
9604 	if (r)
9605 		return r;
9606 
9607 	/* make sure dequeue is complete*/
9608 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9609 	mutex_lock(&adev->srbm_mutex);
9610 	nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9611 	for (i = 0; i < adev->usec_timeout; i++) {
9612 		if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9613 			break;
9614 		udelay(1);
9615 	}
9616 	if (i >= adev->usec_timeout)
9617 		r = -ETIMEDOUT;
9618 	nv_grbm_select(adev, 0, 0, 0, 0);
9619 	mutex_unlock(&adev->srbm_mutex);
9620 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9621 	if (r) {
9622 		dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9623 		return r;
9624 	}
9625 
9626 	r = gfx_v10_0_kcq_init_queue(ring, true);
9627 	if (r) {
9628 		dev_err(adev->dev, "fail to init kcq\n");
9629 		return r;
9630 	}
9631 
9632 	spin_lock_irqsave(&kiq->ring_lock, flags);
9633 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9634 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
9635 		return -ENOMEM;
9636 	}
9637 	kiq->pmf->kiq_map_queues(kiq_ring, ring);
9638 	amdgpu_ring_commit(kiq_ring);
9639 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
9640 
9641 	r = amdgpu_ring_test_ring(kiq_ring);
9642 	if (r)
9643 		return r;
9644 
9645 	return amdgpu_ring_test_ring(ring);
9646 }
9647 
9648 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9649 {
9650 	struct amdgpu_device *adev = ip_block->adev;
9651 	uint32_t i, j, k, reg, index = 0;
9652 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9653 
9654 	if (!adev->gfx.ip_dump_core)
9655 		return;
9656 
9657 	for (i = 0; i < reg_count; i++)
9658 		drm_printf(p, "%-50s \t 0x%08x\n",
9659 			   gc_reg_list_10_1[i].reg_name,
9660 			   adev->gfx.ip_dump_core[i]);
9661 
9662 	/* print compute queue registers for all instances */
9663 	if (!adev->gfx.ip_dump_compute_queues)
9664 		return;
9665 
9666 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9667 	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9668 		   adev->gfx.mec.num_mec,
9669 		   adev->gfx.mec.num_pipe_per_mec,
9670 		   adev->gfx.mec.num_queue_per_pipe);
9671 
9672 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9673 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9674 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9675 				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9676 				for (reg = 0; reg < reg_count; reg++) {
9677 					drm_printf(p, "%-50s \t 0x%08x\n",
9678 						   gc_cp_reg_list_10[reg].reg_name,
9679 						   adev->gfx.ip_dump_compute_queues[index + reg]);
9680 				}
9681 				index += reg_count;
9682 			}
9683 		}
9684 	}
9685 
9686 	/* print gfx queue registers for all instances */
9687 	if (!adev->gfx.ip_dump_gfx_queues)
9688 		return;
9689 
9690 	index = 0;
9691 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9692 	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9693 		   adev->gfx.me.num_me,
9694 		   adev->gfx.me.num_pipe_per_me,
9695 		   adev->gfx.me.num_queue_per_pipe);
9696 
9697 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9698 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9699 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9700 				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9701 				for (reg = 0; reg < reg_count; reg++) {
9702 					drm_printf(p, "%-50s \t 0x%08x\n",
9703 						   gc_gfx_queue_reg_list_10[reg].reg_name,
9704 						   adev->gfx.ip_dump_gfx_queues[index + reg]);
9705 				}
9706 				index += reg_count;
9707 			}
9708 		}
9709 	}
9710 }
9711 
9712 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9713 {
9714 	struct amdgpu_device *adev = ip_block->adev;
9715 	uint32_t i, j, k, reg, index = 0;
9716 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9717 
9718 	if (!adev->gfx.ip_dump_core)
9719 		return;
9720 
9721 	amdgpu_gfx_off_ctrl(adev, false);
9722 	for (i = 0; i < reg_count; i++)
9723 		adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9724 	amdgpu_gfx_off_ctrl(adev, true);
9725 
9726 	/* dump compute queue registers for all instances */
9727 	if (!adev->gfx.ip_dump_compute_queues)
9728 		return;
9729 
9730 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9731 	amdgpu_gfx_off_ctrl(adev, false);
9732 	mutex_lock(&adev->srbm_mutex);
9733 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9734 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9735 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9736 				/* ME0 is for GFX so start from 1 for CP */
9737 				nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9738 
9739 				for (reg = 0; reg < reg_count; reg++) {
9740 					adev->gfx.ip_dump_compute_queues[index + reg] =
9741 						RREG32(SOC15_REG_ENTRY_OFFSET(
9742 							gc_cp_reg_list_10[reg]));
9743 				}
9744 				index += reg_count;
9745 			}
9746 		}
9747 	}
9748 	nv_grbm_select(adev, 0, 0, 0, 0);
9749 	mutex_unlock(&adev->srbm_mutex);
9750 	amdgpu_gfx_off_ctrl(adev, true);
9751 
9752 	/* dump gfx queue registers for all instances */
9753 	if (!adev->gfx.ip_dump_gfx_queues)
9754 		return;
9755 
9756 	index = 0;
9757 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9758 	amdgpu_gfx_off_ctrl(adev, false);
9759 	mutex_lock(&adev->srbm_mutex);
9760 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9761 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9762 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9763 				nv_grbm_select(adev, i, j, k, 0);
9764 
9765 				for (reg = 0; reg < reg_count; reg++) {
9766 					adev->gfx.ip_dump_gfx_queues[index + reg] =
9767 						RREG32(SOC15_REG_ENTRY_OFFSET(
9768 							gc_gfx_queue_reg_list_10[reg]));
9769 				}
9770 				index += reg_count;
9771 			}
9772 		}
9773 	}
9774 	nv_grbm_select(adev, 0, 0, 0, 0);
9775 	mutex_unlock(&adev->srbm_mutex);
9776 	amdgpu_gfx_off_ctrl(adev, true);
9777 }
9778 
9779 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9780 {
9781 	/* Emit the cleaner shader */
9782 	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9783 	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
9784 }
9785 
9786 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
9787 {
9788 	amdgpu_gfx_profile_ring_begin_use(ring);
9789 
9790 	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
9791 }
9792 
9793 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
9794 {
9795 	amdgpu_gfx_profile_ring_end_use(ring);
9796 
9797 	amdgpu_gfx_enforce_isolation_ring_end_use(ring);
9798 }
9799 
9800 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9801 	.name = "gfx_v10_0",
9802 	.early_init = gfx_v10_0_early_init,
9803 	.late_init = gfx_v10_0_late_init,
9804 	.sw_init = gfx_v10_0_sw_init,
9805 	.sw_fini = gfx_v10_0_sw_fini,
9806 	.hw_init = gfx_v10_0_hw_init,
9807 	.hw_fini = gfx_v10_0_hw_fini,
9808 	.suspend = gfx_v10_0_suspend,
9809 	.resume = gfx_v10_0_resume,
9810 	.is_idle = gfx_v10_0_is_idle,
9811 	.wait_for_idle = gfx_v10_0_wait_for_idle,
9812 	.soft_reset = gfx_v10_0_soft_reset,
9813 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
9814 	.set_powergating_state = gfx_v10_0_set_powergating_state,
9815 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
9816 	.dump_ip_state = gfx_v10_ip_dump,
9817 	.print_ip_state = gfx_v10_ip_print,
9818 };
9819 
9820 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9821 	.type = AMDGPU_RING_TYPE_GFX,
9822 	.align_mask = 0xff,
9823 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9824 	.support_64bit_ptrs = true,
9825 	.secure_submission_supported = true,
9826 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9827 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9828 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9829 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
9830 		5 + /* COND_EXEC */
9831 		7 + /* PIPELINE_SYNC */
9832 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9833 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9834 		4 + /* VM_FLUSH */
9835 		8 + /* FENCE for VM_FLUSH */
9836 		20 + /* GDS switch */
9837 		4 + /* double SWITCH_BUFFER,
9838 		     * the first COND_EXEC jump to the place
9839 		     * just prior to this double SWITCH_BUFFER
9840 		     */
9841 		5 + /* COND_EXEC */
9842 		7 + /* HDP_flush */
9843 		4 + /* VGT_flush */
9844 		14 + /*	CE_META */
9845 		31 + /*	DE_META */
9846 		3 + /* CNTX_CTRL */
9847 		5 + /* HDP_INVL */
9848 		8 + 8 + /* FENCE x2 */
9849 		2 + /* SWITCH_BUFFER */
9850 		8 + /* gfx_v10_0_emit_mem_sync */
9851 		2, /* gfx_v10_0_ring_emit_cleaner_shader */
9852 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
9853 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9854 	.emit_fence = gfx_v10_0_ring_emit_fence,
9855 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9856 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9857 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9858 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9859 	.test_ring = gfx_v10_0_ring_test_ring,
9860 	.test_ib = gfx_v10_0_ring_test_ib,
9861 	.insert_nop = gfx_v10_ring_insert_nop,
9862 	.pad_ib = amdgpu_ring_generic_pad_ib,
9863 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9864 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9865 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9866 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
9867 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9868 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9869 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9870 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9871 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9872 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9873 	.reset = gfx_v10_0_reset_kgq,
9874 	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9875 	.begin_use = gfx_v10_0_ring_begin_use,
9876 	.end_use = gfx_v10_0_ring_end_use,
9877 };
9878 
9879 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9880 	.type = AMDGPU_RING_TYPE_COMPUTE,
9881 	.align_mask = 0xff,
9882 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9883 	.support_64bit_ptrs = true,
9884 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9885 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9886 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9887 	.emit_frame_size =
9888 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9889 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9890 		5 + /* hdp invalidate */
9891 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9892 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9893 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9894 		2 + /* gfx_v10_0_ring_emit_vm_flush */
9895 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9896 		8 + /* gfx_v10_0_emit_mem_sync */
9897 		2, /* gfx_v10_0_ring_emit_cleaner_shader */
9898 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9899 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9900 	.emit_fence = gfx_v10_0_ring_emit_fence,
9901 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9902 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9903 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9904 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9905 	.test_ring = gfx_v10_0_ring_test_ring,
9906 	.test_ib = gfx_v10_0_ring_test_ib,
9907 	.insert_nop = gfx_v10_ring_insert_nop,
9908 	.pad_ib = amdgpu_ring_generic_pad_ib,
9909 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9910 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9911 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9912 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9913 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9914 	.reset = gfx_v10_0_reset_kcq,
9915 	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9916 	.begin_use = gfx_v10_0_ring_begin_use,
9917 	.end_use = gfx_v10_0_ring_end_use,
9918 };
9919 
9920 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9921 	.type = AMDGPU_RING_TYPE_KIQ,
9922 	.align_mask = 0xff,
9923 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9924 	.support_64bit_ptrs = true,
9925 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9926 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9927 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9928 	.emit_frame_size =
9929 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9930 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9931 		5 + /*hdp invalidate */
9932 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9933 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9934 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9935 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9936 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9937 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9938 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9939 	.test_ring = gfx_v10_0_ring_test_ring,
9940 	.test_ib = gfx_v10_0_ring_test_ib,
9941 	.insert_nop = amdgpu_ring_insert_nop,
9942 	.pad_ib = amdgpu_ring_generic_pad_ib,
9943 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
9944 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9945 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9946 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9947 };
9948 
9949 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9950 {
9951 	int i;
9952 
9953 	adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9954 
9955 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9956 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9957 
9958 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
9959 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9960 }
9961 
9962 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9963 	.set = gfx_v10_0_set_eop_interrupt_state,
9964 	.process = gfx_v10_0_eop_irq,
9965 };
9966 
9967 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9968 	.set = gfx_v10_0_set_priv_reg_fault_state,
9969 	.process = gfx_v10_0_priv_reg_irq,
9970 };
9971 
9972 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
9973 	.set = gfx_v10_0_set_bad_op_fault_state,
9974 	.process = gfx_v10_0_bad_op_irq,
9975 };
9976 
9977 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9978 	.set = gfx_v10_0_set_priv_inst_fault_state,
9979 	.process = gfx_v10_0_priv_inst_irq,
9980 };
9981 
9982 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9983 	.set = gfx_v10_0_kiq_set_interrupt_state,
9984 	.process = gfx_v10_0_kiq_irq,
9985 };
9986 
9987 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9988 {
9989 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9990 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9991 
9992 	adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9993 	adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9994 
9995 	adev->gfx.priv_reg_irq.num_types = 1;
9996 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9997 
9998 	adev->gfx.bad_op_irq.num_types = 1;
9999 	adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
10000 
10001 	adev->gfx.priv_inst_irq.num_types = 1;
10002 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
10003 }
10004 
10005 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
10006 {
10007 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
10008 	case IP_VERSION(10, 1, 10):
10009 	case IP_VERSION(10, 1, 1):
10010 	case IP_VERSION(10, 1, 3):
10011 	case IP_VERSION(10, 1, 4):
10012 	case IP_VERSION(10, 3, 2):
10013 	case IP_VERSION(10, 3, 1):
10014 	case IP_VERSION(10, 3, 4):
10015 	case IP_VERSION(10, 3, 5):
10016 	case IP_VERSION(10, 3, 6):
10017 	case IP_VERSION(10, 3, 3):
10018 	case IP_VERSION(10, 3, 7):
10019 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
10020 		break;
10021 	case IP_VERSION(10, 1, 2):
10022 	case IP_VERSION(10, 3, 0):
10023 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
10024 		break;
10025 	default:
10026 		break;
10027 	}
10028 }
10029 
10030 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
10031 {
10032 	unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
10033 			    adev->gfx.config.max_sh_per_se *
10034 			    adev->gfx.config.max_shader_engines;
10035 
10036 	adev->gds.gds_size = 0x10000;
10037 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
10038 	adev->gds.gws_size = 64;
10039 	adev->gds.oa_size = 16;
10040 }
10041 
10042 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
10043 {
10044 	/* set gfx eng mqd */
10045 	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
10046 		sizeof(struct v10_gfx_mqd);
10047 	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
10048 		gfx_v10_0_gfx_mqd_init;
10049 	/* set compute eng mqd */
10050 	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10051 		sizeof(struct v10_compute_mqd);
10052 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10053 		gfx_v10_0_compute_mqd_init;
10054 }
10055 
10056 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10057 							  u32 bitmap)
10058 {
10059 	u32 data;
10060 
10061 	if (!bitmap)
10062 		return;
10063 
10064 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10065 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10066 
10067 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10068 }
10069 
10070 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10071 {
10072 	u32 disabled_mask =
10073 		~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10074 	u32 efuse_setting = 0;
10075 	u32 vbios_setting = 0;
10076 
10077 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10078 	efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10079 	efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10080 
10081 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10082 	vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10083 	vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10084 
10085 	disabled_mask |= efuse_setting | vbios_setting;
10086 
10087 	return (~disabled_mask);
10088 }
10089 
10090 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10091 {
10092 	u32 wgp_idx, wgp_active_bitmap;
10093 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
10094 
10095 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10096 	cu_active_bitmap = 0;
10097 
10098 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10099 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
10100 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10101 		if (wgp_active_bitmap & (1 << wgp_idx))
10102 			cu_active_bitmap |= cu_bitmap_per_wgp;
10103 	}
10104 
10105 	return cu_active_bitmap;
10106 }
10107 
10108 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10109 				 struct amdgpu_cu_info *cu_info)
10110 {
10111 	int i, j, k, counter, active_cu_number = 0;
10112 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10113 	unsigned int disable_masks[4 * 2];
10114 
10115 	if (!adev || !cu_info)
10116 		return -EINVAL;
10117 
10118 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10119 
10120 	mutex_lock(&adev->grbm_idx_mutex);
10121 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10122 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10123 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
10124 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10125 			      IP_VERSION(10, 3, 0)) ||
10126 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10127 			      IP_VERSION(10, 3, 3)) ||
10128 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10129 			      IP_VERSION(10, 3, 6)) ||
10130 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10131 			      IP_VERSION(10, 3, 7))) &&
10132 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10133 				continue;
10134 			mask = 1;
10135 			ao_bitmap = 0;
10136 			counter = 0;
10137 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10138 			if (i < 4 && j < 2)
10139 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10140 					adev, disable_masks[i * 2 + j]);
10141 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10142 			cu_info->bitmap[0][i][j] = bitmap;
10143 
10144 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10145 				if (bitmap & mask) {
10146 					if (counter < adev->gfx.config.max_cu_per_sh)
10147 						ao_bitmap |= mask;
10148 					counter++;
10149 				}
10150 				mask <<= 1;
10151 			}
10152 			active_cu_number += counter;
10153 			if (i < 2 && j < 2)
10154 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10155 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10156 		}
10157 	}
10158 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10159 	mutex_unlock(&adev->grbm_idx_mutex);
10160 
10161 	cu_info->number = active_cu_number;
10162 	cu_info->ao_cu_mask = ao_cu_mask;
10163 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10164 
10165 	return 0;
10166 }
10167 
10168 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10169 {
10170 	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10171 
10172 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10173 	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10174 	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10175 
10176 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10177 	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10178 	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10179 
10180 	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10181 						adev->gfx.config.max_shader_engines);
10182 	disabled_sa = efuse_setting | vbios_setting;
10183 	disabled_sa &= max_sa_mask;
10184 
10185 	return disabled_sa;
10186 }
10187 
10188 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10189 {
10190 	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10191 	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10192 
10193 	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10194 
10195 	max_sa_per_se = adev->gfx.config.max_sh_per_se;
10196 	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10197 	max_shader_engines = adev->gfx.config.max_shader_engines;
10198 
10199 	for (se_index = 0; max_shader_engines > se_index; se_index++) {
10200 		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10201 		disabled_sa_per_se &= max_sa_per_se_mask;
10202 		if (disabled_sa_per_se == max_sa_per_se_mask) {
10203 			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10204 			break;
10205 		}
10206 	}
10207 }
10208 
10209 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10210 {
10211 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10212 		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10213 		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10214 		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10215 
10216 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10217 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10218 		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10219 		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10220 		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10221 		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10222 
10223 	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10224 		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10225 		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10226 		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10227 
10228 	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10229 
10230 	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10231 		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10232 }
10233 
10234 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10235 	.type = AMD_IP_BLOCK_TYPE_GFX,
10236 	.major = 10,
10237 	.minor = 0,
10238 	.rev = 0,
10239 	.funcs = &gfx_v10_0_ip_funcs,
10240 };
10241