1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 103 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 104 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 105 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 106 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 107 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 108 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 109 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 110 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 111 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 113 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 114 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 115 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 116 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 117 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 118 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 119 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 120 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 121 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 122 123 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 124 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 125 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 126 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 127 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 128 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 129 #define mmCP_HYP_CE_UCODE_DATA 0x5819 130 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 131 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 132 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 133 #define mmCP_HYP_ME_UCODE_DATA 0x5817 134 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 135 136 #define mmCPG_PSP_DEBUG 0x5c10 137 #define mmCPG_PSP_DEBUG_BASE_IDX 1 138 #define mmCPC_PSP_DEBUG 0x5c11 139 #define mmCPC_PSP_DEBUG_BASE_IDX 1 140 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 141 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 142 143 //CC_GC_SA_UNIT_DISABLE 144 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 145 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 146 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 147 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 148 //GC_USER_SA_UNIT_DISABLE 149 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 150 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 151 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 152 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 153 //PA_SC_ENHANCE_3 154 #define mmPA_SC_ENHANCE_3 0x1085 155 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 156 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 157 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 158 159 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 160 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 161 162 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 163 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 164 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 165 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 166 167 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 168 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 169 170 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 171 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 172 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 173 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 174 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 175 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 176 177 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 178 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 179 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 180 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 181 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 182 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 183 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 184 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 185 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 186 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 187 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 188 189 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 190 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 191 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 192 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 193 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 194 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 195 196 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 197 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 198 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 199 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 200 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 201 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 202 203 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 206 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 213 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 216 217 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 218 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 219 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 220 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 221 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 222 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 223 224 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 225 { 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 266 }; 267 268 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 269 { 270 /* Pending on emulation bring up */ 271 }; 272 273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 274 { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1327 }; 1328 1329 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1330 { 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1369 }; 1370 1371 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1372 { 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1413 }; 1414 1415 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1416 { 1417 static void *scratch_reg0; 1418 static void *scratch_reg1; 1419 static void *spare_int; 1420 uint32_t i = 0; 1421 uint32_t retries = 50000; 1422 1423 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1424 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1425 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1426 1427 if (amdgpu_sriov_runtime(adev)) { 1428 pr_err("shouldn't call rlcg write register during runtime\n"); 1429 return; 1430 } 1431 1432 writel(v, scratch_reg0); 1433 writel(offset | 0x80000000, scratch_reg1); 1434 writel(1, spare_int); 1435 for (i = 0; i < retries; i++) { 1436 u32 tmp; 1437 1438 tmp = readl(scratch_reg1); 1439 if (!(tmp & 0x80000000)) 1440 break; 1441 1442 udelay(10); 1443 } 1444 1445 if (i >= retries) 1446 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1447 } 1448 1449 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1450 { 1451 /* Pending on emulation bring up */ 1452 }; 1453 1454 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1455 { 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2076 }; 2077 2078 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2079 { 2080 /* Pending on emulation bring up */ 2081 }; 2082 2083 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2084 { 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3137 }; 3138 3139 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3140 { 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3183 }; 3184 3185 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3186 { 3187 /* Pending on emulation bring up */ 3188 }; 3189 3190 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3191 { 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3233 3234 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3236 }; 3237 3238 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3239 { 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3263 3264 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3266 }; 3267 3268 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3269 { 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3305 }; 3306 3307 #define DEFAULT_SH_MEM_CONFIG \ 3308 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3309 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3310 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3311 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3312 3313 3314 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3315 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3316 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3317 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3318 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3319 struct amdgpu_cu_info *cu_info); 3320 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3321 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3322 u32 sh_num, u32 instance); 3323 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3324 3325 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3326 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3327 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3328 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3329 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3330 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3331 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3332 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3333 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3334 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3335 3336 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3337 { 3338 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3339 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3340 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3341 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3342 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3343 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3344 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3345 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3346 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3347 } 3348 3349 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3350 struct amdgpu_ring *ring) 3351 { 3352 struct amdgpu_device *adev = kiq_ring->adev; 3353 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3354 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3356 3357 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3358 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3359 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3360 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3361 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3362 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3363 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3364 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3365 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3366 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3367 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3368 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3369 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3370 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3371 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3372 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3373 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3374 } 3375 3376 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3377 struct amdgpu_ring *ring, 3378 enum amdgpu_unmap_queues_action action, 3379 u64 gpu_addr, u64 seq) 3380 { 3381 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3382 3383 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3384 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3385 PACKET3_UNMAP_QUEUES_ACTION(action) | 3386 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3387 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3388 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3389 amdgpu_ring_write(kiq_ring, 3390 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3391 3392 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3393 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3394 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3395 amdgpu_ring_write(kiq_ring, seq); 3396 } else { 3397 amdgpu_ring_write(kiq_ring, 0); 3398 amdgpu_ring_write(kiq_ring, 0); 3399 amdgpu_ring_write(kiq_ring, 0); 3400 } 3401 } 3402 3403 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3404 struct amdgpu_ring *ring, 3405 u64 addr, 3406 u64 seq) 3407 { 3408 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3409 3410 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3411 amdgpu_ring_write(kiq_ring, 3412 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3413 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3414 PACKET3_QUERY_STATUS_COMMAND(2)); 3415 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3416 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3417 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3418 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3419 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3420 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3421 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3422 } 3423 3424 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3425 uint16_t pasid, uint32_t flush_type, 3426 bool all_hub) 3427 { 3428 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3429 amdgpu_ring_write(kiq_ring, 3430 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3431 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3432 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3433 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3434 } 3435 3436 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3437 .kiq_set_resources = gfx10_kiq_set_resources, 3438 .kiq_map_queues = gfx10_kiq_map_queues, 3439 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3440 .kiq_query_status = gfx10_kiq_query_status, 3441 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3442 .set_resources_size = 8, 3443 .map_queues_size = 7, 3444 .unmap_queues_size = 6, 3445 .query_status_size = 7, 3446 .invalidate_tlbs_size = 2, 3447 }; 3448 3449 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3450 { 3451 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3452 } 3453 3454 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3455 { 3456 switch (adev->asic_type) { 3457 case CHIP_NAVI10: 3458 soc15_program_register_sequence(adev, 3459 golden_settings_gc_rlc_spm_10_0_nv10, 3460 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3461 break; 3462 case CHIP_NAVI14: 3463 soc15_program_register_sequence(adev, 3464 golden_settings_gc_rlc_spm_10_1_nv14, 3465 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3466 break; 3467 case CHIP_NAVI12: 3468 soc15_program_register_sequence(adev, 3469 golden_settings_gc_rlc_spm_10_1_2_nv12, 3470 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3471 break; 3472 default: 3473 break; 3474 } 3475 } 3476 3477 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3478 { 3479 switch (adev->asic_type) { 3480 case CHIP_NAVI10: 3481 soc15_program_register_sequence(adev, 3482 golden_settings_gc_10_1, 3483 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3484 soc15_program_register_sequence(adev, 3485 golden_settings_gc_10_0_nv10, 3486 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3487 break; 3488 case CHIP_NAVI14: 3489 soc15_program_register_sequence(adev, 3490 golden_settings_gc_10_1_1, 3491 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3492 soc15_program_register_sequence(adev, 3493 golden_settings_gc_10_1_nv14, 3494 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3495 break; 3496 case CHIP_NAVI12: 3497 soc15_program_register_sequence(adev, 3498 golden_settings_gc_10_1_2, 3499 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3500 soc15_program_register_sequence(adev, 3501 golden_settings_gc_10_1_2_nv12, 3502 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3503 break; 3504 case CHIP_SIENNA_CICHLID: 3505 soc15_program_register_sequence(adev, 3506 golden_settings_gc_10_3, 3507 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3508 soc15_program_register_sequence(adev, 3509 golden_settings_gc_10_3_sienna_cichlid, 3510 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3511 break; 3512 case CHIP_NAVY_FLOUNDER: 3513 soc15_program_register_sequence(adev, 3514 golden_settings_gc_10_3_2, 3515 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3516 break; 3517 case CHIP_VANGOGH: 3518 soc15_program_register_sequence(adev, 3519 golden_settings_gc_10_3_vangogh, 3520 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3521 break; 3522 case CHIP_DIMGREY_CAVEFISH: 3523 soc15_program_register_sequence(adev, 3524 golden_settings_gc_10_3_4, 3525 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3526 break; 3527 default: 3528 break; 3529 } 3530 gfx_v10_0_init_spm_golden_registers(adev); 3531 } 3532 3533 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3534 { 3535 adev->gfx.scratch.num_reg = 8; 3536 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3537 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3538 } 3539 3540 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3541 bool wc, uint32_t reg, uint32_t val) 3542 { 3543 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3544 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3545 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3546 amdgpu_ring_write(ring, reg); 3547 amdgpu_ring_write(ring, 0); 3548 amdgpu_ring_write(ring, val); 3549 } 3550 3551 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3552 int mem_space, int opt, uint32_t addr0, 3553 uint32_t addr1, uint32_t ref, uint32_t mask, 3554 uint32_t inv) 3555 { 3556 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3557 amdgpu_ring_write(ring, 3558 /* memory (1) or register (0) */ 3559 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3560 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3561 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3562 WAIT_REG_MEM_ENGINE(eng_sel))); 3563 3564 if (mem_space) 3565 BUG_ON(addr0 & 0x3); /* Dword align */ 3566 amdgpu_ring_write(ring, addr0); 3567 amdgpu_ring_write(ring, addr1); 3568 amdgpu_ring_write(ring, ref); 3569 amdgpu_ring_write(ring, mask); 3570 amdgpu_ring_write(ring, inv); /* poll interval */ 3571 } 3572 3573 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3574 { 3575 struct amdgpu_device *adev = ring->adev; 3576 uint32_t scratch; 3577 uint32_t tmp = 0; 3578 unsigned i; 3579 int r; 3580 3581 r = amdgpu_gfx_scratch_get(adev, &scratch); 3582 if (r) { 3583 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3584 return r; 3585 } 3586 3587 WREG32(scratch, 0xCAFEDEAD); 3588 3589 r = amdgpu_ring_alloc(ring, 3); 3590 if (r) { 3591 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3592 ring->idx, r); 3593 amdgpu_gfx_scratch_free(adev, scratch); 3594 return r; 3595 } 3596 3597 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3598 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3599 amdgpu_ring_write(ring, 0xDEADBEEF); 3600 amdgpu_ring_commit(ring); 3601 3602 for (i = 0; i < adev->usec_timeout; i++) { 3603 tmp = RREG32(scratch); 3604 if (tmp == 0xDEADBEEF) 3605 break; 3606 if (amdgpu_emu_mode == 1) 3607 msleep(1); 3608 else 3609 udelay(1); 3610 } 3611 3612 if (i >= adev->usec_timeout) 3613 r = -ETIMEDOUT; 3614 3615 amdgpu_gfx_scratch_free(adev, scratch); 3616 3617 return r; 3618 } 3619 3620 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3621 { 3622 struct amdgpu_device *adev = ring->adev; 3623 struct amdgpu_ib ib; 3624 struct dma_fence *f = NULL; 3625 unsigned index; 3626 uint64_t gpu_addr; 3627 uint32_t tmp; 3628 long r; 3629 3630 r = amdgpu_device_wb_get(adev, &index); 3631 if (r) 3632 return r; 3633 3634 gpu_addr = adev->wb.gpu_addr + (index * 4); 3635 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3636 memset(&ib, 0, sizeof(ib)); 3637 r = amdgpu_ib_get(adev, NULL, 16, 3638 AMDGPU_IB_POOL_DIRECT, &ib); 3639 if (r) 3640 goto err1; 3641 3642 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3643 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3644 ib.ptr[2] = lower_32_bits(gpu_addr); 3645 ib.ptr[3] = upper_32_bits(gpu_addr); 3646 ib.ptr[4] = 0xDEADBEEF; 3647 ib.length_dw = 5; 3648 3649 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3650 if (r) 3651 goto err2; 3652 3653 r = dma_fence_wait_timeout(f, false, timeout); 3654 if (r == 0) { 3655 r = -ETIMEDOUT; 3656 goto err2; 3657 } else if (r < 0) { 3658 goto err2; 3659 } 3660 3661 tmp = adev->wb.wb[index]; 3662 if (tmp == 0xDEADBEEF) 3663 r = 0; 3664 else 3665 r = -EINVAL; 3666 err2: 3667 amdgpu_ib_free(adev, &ib, NULL); 3668 dma_fence_put(f); 3669 err1: 3670 amdgpu_device_wb_free(adev, index); 3671 return r; 3672 } 3673 3674 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3675 { 3676 release_firmware(adev->gfx.pfp_fw); 3677 adev->gfx.pfp_fw = NULL; 3678 release_firmware(adev->gfx.me_fw); 3679 adev->gfx.me_fw = NULL; 3680 release_firmware(adev->gfx.ce_fw); 3681 adev->gfx.ce_fw = NULL; 3682 release_firmware(adev->gfx.rlc_fw); 3683 adev->gfx.rlc_fw = NULL; 3684 release_firmware(adev->gfx.mec_fw); 3685 adev->gfx.mec_fw = NULL; 3686 release_firmware(adev->gfx.mec2_fw); 3687 adev->gfx.mec2_fw = NULL; 3688 3689 kfree(adev->gfx.rlc.register_list_format); 3690 } 3691 3692 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3693 { 3694 adev->gfx.cp_fw_write_wait = false; 3695 3696 switch (adev->asic_type) { 3697 case CHIP_NAVI10: 3698 case CHIP_NAVI12: 3699 case CHIP_NAVI14: 3700 if ((adev->gfx.me_fw_version >= 0x00000046) && 3701 (adev->gfx.me_feature_version >= 27) && 3702 (adev->gfx.pfp_fw_version >= 0x00000068) && 3703 (adev->gfx.pfp_feature_version >= 27) && 3704 (adev->gfx.mec_fw_version >= 0x0000005b) && 3705 (adev->gfx.mec_feature_version >= 27)) 3706 adev->gfx.cp_fw_write_wait = true; 3707 break; 3708 case CHIP_SIENNA_CICHLID: 3709 case CHIP_NAVY_FLOUNDER: 3710 case CHIP_VANGOGH: 3711 case CHIP_DIMGREY_CAVEFISH: 3712 adev->gfx.cp_fw_write_wait = true; 3713 break; 3714 default: 3715 break; 3716 } 3717 3718 if (!adev->gfx.cp_fw_write_wait) 3719 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3720 } 3721 3722 3723 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3724 { 3725 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3726 3727 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3728 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3729 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3730 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3731 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3732 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3733 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3734 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3735 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3736 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3737 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3738 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3739 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3740 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3741 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3742 } 3743 3744 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3745 { 3746 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3747 3748 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3749 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3750 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3751 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3752 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3753 } 3754 3755 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3756 { 3757 bool ret = false; 3758 3759 switch (adev->pdev->revision) { 3760 case 0xc2: 3761 case 0xc3: 3762 ret = true; 3763 break; 3764 default: 3765 ret = false; 3766 break; 3767 } 3768 3769 return ret ; 3770 } 3771 3772 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3773 { 3774 switch (adev->asic_type) { 3775 case CHIP_NAVI10: 3776 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3777 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3778 break; 3779 case CHIP_VANGOGH: 3780 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3781 break; 3782 default: 3783 break; 3784 } 3785 } 3786 3787 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3788 { 3789 const char *chip_name; 3790 char fw_name[40]; 3791 char wks[10]; 3792 int err; 3793 struct amdgpu_firmware_info *info = NULL; 3794 const struct common_firmware_header *header = NULL; 3795 const struct gfx_firmware_header_v1_0 *cp_hdr; 3796 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3797 unsigned int *tmp = NULL; 3798 unsigned int i = 0; 3799 uint16_t version_major; 3800 uint16_t version_minor; 3801 3802 DRM_DEBUG("\n"); 3803 3804 memset(wks, 0, sizeof(wks)); 3805 switch (adev->asic_type) { 3806 case CHIP_NAVI10: 3807 chip_name = "navi10"; 3808 break; 3809 case CHIP_NAVI14: 3810 chip_name = "navi14"; 3811 if (!(adev->pdev->device == 0x7340 && 3812 adev->pdev->revision != 0x00)) 3813 snprintf(wks, sizeof(wks), "_wks"); 3814 break; 3815 case CHIP_NAVI12: 3816 chip_name = "navi12"; 3817 break; 3818 case CHIP_SIENNA_CICHLID: 3819 chip_name = "sienna_cichlid"; 3820 break; 3821 case CHIP_NAVY_FLOUNDER: 3822 chip_name = "navy_flounder"; 3823 break; 3824 case CHIP_VANGOGH: 3825 chip_name = "vangogh"; 3826 break; 3827 case CHIP_DIMGREY_CAVEFISH: 3828 chip_name = "dimgrey_cavefish"; 3829 break; 3830 default: 3831 BUG(); 3832 } 3833 3834 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3835 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3836 if (err) 3837 goto out; 3838 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3839 if (err) 3840 goto out; 3841 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3842 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3843 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3844 3845 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3846 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3847 if (err) 3848 goto out; 3849 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3850 if (err) 3851 goto out; 3852 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3853 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3854 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3855 3856 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3857 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3858 if (err) 3859 goto out; 3860 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3861 if (err) 3862 goto out; 3863 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3864 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3865 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3866 3867 if (!amdgpu_sriov_vf(adev)) { 3868 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3869 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3870 if (err) 3871 goto out; 3872 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3873 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3874 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3875 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3876 3877 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3878 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3879 adev->gfx.rlc.save_and_restore_offset = 3880 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3881 adev->gfx.rlc.clear_state_descriptor_offset = 3882 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3883 adev->gfx.rlc.avail_scratch_ram_locations = 3884 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3885 adev->gfx.rlc.reg_restore_list_size = 3886 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3887 adev->gfx.rlc.reg_list_format_start = 3888 le32_to_cpu(rlc_hdr->reg_list_format_start); 3889 adev->gfx.rlc.reg_list_format_separate_start = 3890 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3891 adev->gfx.rlc.starting_offsets_start = 3892 le32_to_cpu(rlc_hdr->starting_offsets_start); 3893 adev->gfx.rlc.reg_list_format_size_bytes = 3894 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3895 adev->gfx.rlc.reg_list_size_bytes = 3896 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3897 adev->gfx.rlc.register_list_format = 3898 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3899 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3900 if (!adev->gfx.rlc.register_list_format) { 3901 err = -ENOMEM; 3902 goto out; 3903 } 3904 3905 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3906 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3907 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3908 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3909 3910 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3911 3912 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3913 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3914 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3915 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3916 3917 if (version_major == 2) { 3918 if (version_minor >= 1) 3919 gfx_v10_0_init_rlc_ext_microcode(adev); 3920 if (version_minor == 2) 3921 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3922 } 3923 } 3924 3925 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3926 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3927 if (err) 3928 goto out; 3929 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3930 if (err) 3931 goto out; 3932 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3933 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3934 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3935 3936 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3937 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3938 if (!err) { 3939 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3940 if (err) 3941 goto out; 3942 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3943 adev->gfx.mec2_fw->data; 3944 adev->gfx.mec2_fw_version = 3945 le32_to_cpu(cp_hdr->header.ucode_version); 3946 adev->gfx.mec2_feature_version = 3947 le32_to_cpu(cp_hdr->ucode_feature_version); 3948 } else { 3949 err = 0; 3950 adev->gfx.mec2_fw = NULL; 3951 } 3952 3953 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3954 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3955 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3956 info->fw = adev->gfx.pfp_fw; 3957 header = (const struct common_firmware_header *)info->fw->data; 3958 adev->firmware.fw_size += 3959 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3960 3961 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3962 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3963 info->fw = adev->gfx.me_fw; 3964 header = (const struct common_firmware_header *)info->fw->data; 3965 adev->firmware.fw_size += 3966 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3967 3968 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3969 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3970 info->fw = adev->gfx.ce_fw; 3971 header = (const struct common_firmware_header *)info->fw->data; 3972 adev->firmware.fw_size += 3973 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3974 3975 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3976 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3977 info->fw = adev->gfx.rlc_fw; 3978 if (info->fw) { 3979 header = (const struct common_firmware_header *)info->fw->data; 3980 adev->firmware.fw_size += 3981 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3982 } 3983 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3984 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3985 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3986 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3987 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3988 info->fw = adev->gfx.rlc_fw; 3989 adev->firmware.fw_size += 3990 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3991 3992 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3993 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3994 info->fw = adev->gfx.rlc_fw; 3995 adev->firmware.fw_size += 3996 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3997 3998 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 3999 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4000 info->fw = adev->gfx.rlc_fw; 4001 adev->firmware.fw_size += 4002 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4003 4004 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4005 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4006 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4007 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4008 info->fw = adev->gfx.rlc_fw; 4009 adev->firmware.fw_size += 4010 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4011 4012 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4013 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4014 info->fw = adev->gfx.rlc_fw; 4015 adev->firmware.fw_size += 4016 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4017 } 4018 } 4019 4020 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4021 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4022 info->fw = adev->gfx.mec_fw; 4023 header = (const struct common_firmware_header *)info->fw->data; 4024 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4025 adev->firmware.fw_size += 4026 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4027 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4028 4029 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4030 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4031 info->fw = adev->gfx.mec_fw; 4032 adev->firmware.fw_size += 4033 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4034 4035 if (adev->gfx.mec2_fw) { 4036 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4037 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4038 info->fw = adev->gfx.mec2_fw; 4039 header = (const struct common_firmware_header *)info->fw->data; 4040 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4041 adev->firmware.fw_size += 4042 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4043 le32_to_cpu(cp_hdr->jt_size) * 4, 4044 PAGE_SIZE); 4045 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4046 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4047 info->fw = adev->gfx.mec2_fw; 4048 adev->firmware.fw_size += 4049 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4050 PAGE_SIZE); 4051 } 4052 } 4053 4054 gfx_v10_0_check_fw_write_wait(adev); 4055 out: 4056 if (err) { 4057 dev_err(adev->dev, 4058 "gfx10: Failed to load firmware \"%s\"\n", 4059 fw_name); 4060 release_firmware(adev->gfx.pfp_fw); 4061 adev->gfx.pfp_fw = NULL; 4062 release_firmware(adev->gfx.me_fw); 4063 adev->gfx.me_fw = NULL; 4064 release_firmware(adev->gfx.ce_fw); 4065 adev->gfx.ce_fw = NULL; 4066 release_firmware(adev->gfx.rlc_fw); 4067 adev->gfx.rlc_fw = NULL; 4068 release_firmware(adev->gfx.mec_fw); 4069 adev->gfx.mec_fw = NULL; 4070 release_firmware(adev->gfx.mec2_fw); 4071 adev->gfx.mec2_fw = NULL; 4072 } 4073 4074 gfx_v10_0_check_gfxoff_flag(adev); 4075 4076 return err; 4077 } 4078 4079 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4080 { 4081 u32 count = 0; 4082 const struct cs_section_def *sect = NULL; 4083 const struct cs_extent_def *ext = NULL; 4084 4085 /* begin clear state */ 4086 count += 2; 4087 /* context control state */ 4088 count += 3; 4089 4090 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4091 for (ext = sect->section; ext->extent != NULL; ++ext) { 4092 if (sect->id == SECT_CONTEXT) 4093 count += 2 + ext->reg_count; 4094 else 4095 return 0; 4096 } 4097 } 4098 4099 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4100 count += 3; 4101 /* end clear state */ 4102 count += 2; 4103 /* clear state */ 4104 count += 2; 4105 4106 return count; 4107 } 4108 4109 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4110 volatile u32 *buffer) 4111 { 4112 u32 count = 0, i; 4113 const struct cs_section_def *sect = NULL; 4114 const struct cs_extent_def *ext = NULL; 4115 int ctx_reg_offset; 4116 4117 if (adev->gfx.rlc.cs_data == NULL) 4118 return; 4119 if (buffer == NULL) 4120 return; 4121 4122 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4123 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4124 4125 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4126 buffer[count++] = cpu_to_le32(0x80000000); 4127 buffer[count++] = cpu_to_le32(0x80000000); 4128 4129 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4130 for (ext = sect->section; ext->extent != NULL; ++ext) { 4131 if (sect->id == SECT_CONTEXT) { 4132 buffer[count++] = 4133 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4134 buffer[count++] = cpu_to_le32(ext->reg_index - 4135 PACKET3_SET_CONTEXT_REG_START); 4136 for (i = 0; i < ext->reg_count; i++) 4137 buffer[count++] = cpu_to_le32(ext->extent[i]); 4138 } else { 4139 return; 4140 } 4141 } 4142 } 4143 4144 ctx_reg_offset = 4145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4146 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4147 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4148 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4149 4150 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4151 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4152 4153 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4154 buffer[count++] = cpu_to_le32(0); 4155 } 4156 4157 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4158 { 4159 /* clear state block */ 4160 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4161 &adev->gfx.rlc.clear_state_gpu_addr, 4162 (void **)&adev->gfx.rlc.cs_ptr); 4163 4164 /* jump table block */ 4165 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4166 &adev->gfx.rlc.cp_table_gpu_addr, 4167 (void **)&adev->gfx.rlc.cp_table_ptr); 4168 } 4169 4170 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4171 { 4172 const struct cs_section_def *cs_data; 4173 int r; 4174 4175 adev->gfx.rlc.cs_data = gfx10_cs_data; 4176 4177 cs_data = adev->gfx.rlc.cs_data; 4178 4179 if (cs_data) { 4180 /* init clear state block */ 4181 r = amdgpu_gfx_rlc_init_csb(adev); 4182 if (r) 4183 return r; 4184 } 4185 4186 /* init spm vmid with 0xf */ 4187 if (adev->gfx.rlc.funcs->update_spm_vmid) 4188 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4189 4190 return 0; 4191 } 4192 4193 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4194 { 4195 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4196 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4197 } 4198 4199 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4200 { 4201 int r; 4202 4203 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4204 4205 amdgpu_gfx_graphics_queue_acquire(adev); 4206 4207 r = gfx_v10_0_init_microcode(adev); 4208 if (r) 4209 DRM_ERROR("Failed to load gfx firmware!\n"); 4210 4211 return r; 4212 } 4213 4214 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4215 { 4216 int r; 4217 u32 *hpd; 4218 const __le32 *fw_data = NULL; 4219 unsigned fw_size; 4220 u32 *fw = NULL; 4221 size_t mec_hpd_size; 4222 4223 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4224 4225 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4226 4227 /* take ownership of the relevant compute queues */ 4228 amdgpu_gfx_compute_queue_acquire(adev); 4229 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4230 4231 if (mec_hpd_size) { 4232 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4233 AMDGPU_GEM_DOMAIN_GTT, 4234 &adev->gfx.mec.hpd_eop_obj, 4235 &adev->gfx.mec.hpd_eop_gpu_addr, 4236 (void **)&hpd); 4237 if (r) { 4238 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4239 gfx_v10_0_mec_fini(adev); 4240 return r; 4241 } 4242 4243 memset(hpd, 0, mec_hpd_size); 4244 4245 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4246 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4247 } 4248 4249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4250 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4251 4252 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4253 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4254 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4255 4256 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4257 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4258 &adev->gfx.mec.mec_fw_obj, 4259 &adev->gfx.mec.mec_fw_gpu_addr, 4260 (void **)&fw); 4261 if (r) { 4262 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4263 gfx_v10_0_mec_fini(adev); 4264 return r; 4265 } 4266 4267 memcpy(fw, fw_data, fw_size); 4268 4269 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4270 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4271 } 4272 4273 return 0; 4274 } 4275 4276 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4277 { 4278 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4279 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4280 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4281 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4282 } 4283 4284 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4285 uint32_t thread, uint32_t regno, 4286 uint32_t num, uint32_t *out) 4287 { 4288 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4289 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4290 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4291 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4292 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4293 while (num--) 4294 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4295 } 4296 4297 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4298 { 4299 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4300 * field when performing a select_se_sh so it should be 4301 * zero here */ 4302 WARN_ON(simd != 0); 4303 4304 /* type 2 wave data */ 4305 dst[(*no_fields)++] = 2; 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4319 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4320 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4321 } 4322 4323 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4324 uint32_t wave, uint32_t start, 4325 uint32_t size, uint32_t *dst) 4326 { 4327 WARN_ON(simd != 0); 4328 4329 wave_read_regs( 4330 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4331 dst); 4332 } 4333 4334 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4335 uint32_t wave, uint32_t thread, 4336 uint32_t start, uint32_t size, 4337 uint32_t *dst) 4338 { 4339 wave_read_regs( 4340 adev, wave, thread, 4341 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4342 } 4343 4344 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4345 u32 me, u32 pipe, u32 q, u32 vm) 4346 { 4347 nv_grbm_select(adev, me, pipe, q, vm); 4348 } 4349 4350 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4351 bool enable) 4352 { 4353 uint32_t data, def; 4354 4355 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4356 4357 if (enable) 4358 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4359 else 4360 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4361 4362 if (data != def) 4363 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4364 } 4365 4366 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4367 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4368 .select_se_sh = &gfx_v10_0_select_se_sh, 4369 .read_wave_data = &gfx_v10_0_read_wave_data, 4370 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4371 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4372 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4373 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4374 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4375 }; 4376 4377 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4378 { 4379 u32 gb_addr_config; 4380 4381 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4382 4383 switch (adev->asic_type) { 4384 case CHIP_NAVI10: 4385 case CHIP_NAVI14: 4386 case CHIP_NAVI12: 4387 adev->gfx.config.max_hw_contexts = 8; 4388 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4389 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4390 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4391 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4392 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4393 break; 4394 case CHIP_SIENNA_CICHLID: 4395 case CHIP_NAVY_FLOUNDER: 4396 case CHIP_VANGOGH: 4397 case CHIP_DIMGREY_CAVEFISH: 4398 adev->gfx.config.max_hw_contexts = 8; 4399 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4400 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4401 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4402 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4403 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4404 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4405 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4406 break; 4407 default: 4408 BUG(); 4409 break; 4410 } 4411 4412 adev->gfx.config.gb_addr_config = gb_addr_config; 4413 4414 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4415 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4416 GB_ADDR_CONFIG, NUM_PIPES); 4417 4418 adev->gfx.config.max_tile_pipes = 4419 adev->gfx.config.gb_addr_config_fields.num_pipes; 4420 4421 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4422 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4423 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4424 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4425 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4426 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4427 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4428 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4429 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4430 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4432 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4433 } 4434 4435 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4436 int me, int pipe, int queue) 4437 { 4438 int r; 4439 struct amdgpu_ring *ring; 4440 unsigned int irq_type; 4441 4442 ring = &adev->gfx.gfx_ring[ring_id]; 4443 4444 ring->me = me; 4445 ring->pipe = pipe; 4446 ring->queue = queue; 4447 4448 ring->ring_obj = NULL; 4449 ring->use_doorbell = true; 4450 4451 if (!ring_id) 4452 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4453 else 4454 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4455 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4456 4457 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4458 r = amdgpu_ring_init(adev, ring, 1024, 4459 &adev->gfx.eop_irq, irq_type, 4460 AMDGPU_RING_PRIO_DEFAULT); 4461 if (r) 4462 return r; 4463 return 0; 4464 } 4465 4466 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4467 int mec, int pipe, int queue) 4468 { 4469 int r; 4470 unsigned irq_type; 4471 struct amdgpu_ring *ring; 4472 unsigned int hw_prio; 4473 4474 ring = &adev->gfx.compute_ring[ring_id]; 4475 4476 /* mec0 is me1 */ 4477 ring->me = mec + 1; 4478 ring->pipe = pipe; 4479 ring->queue = queue; 4480 4481 ring->ring_obj = NULL; 4482 ring->use_doorbell = true; 4483 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4484 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4485 + (ring_id * GFX10_MEC_HPD_SIZE); 4486 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4487 4488 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4489 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4490 + ring->pipe; 4491 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4492 ring->queue) ? 4493 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4494 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4495 r = amdgpu_ring_init(adev, ring, 1024, 4496 &adev->gfx.eop_irq, irq_type, hw_prio); 4497 if (r) 4498 return r; 4499 4500 return 0; 4501 } 4502 4503 static int gfx_v10_0_sw_init(void *handle) 4504 { 4505 int i, j, k, r, ring_id = 0; 4506 struct amdgpu_kiq *kiq; 4507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4508 4509 switch (adev->asic_type) { 4510 case CHIP_NAVI10: 4511 case CHIP_NAVI14: 4512 case CHIP_NAVI12: 4513 adev->gfx.me.num_me = 1; 4514 adev->gfx.me.num_pipe_per_me = 1; 4515 adev->gfx.me.num_queue_per_pipe = 1; 4516 adev->gfx.mec.num_mec = 2; 4517 adev->gfx.mec.num_pipe_per_mec = 4; 4518 adev->gfx.mec.num_queue_per_pipe = 8; 4519 break; 4520 case CHIP_SIENNA_CICHLID: 4521 case CHIP_NAVY_FLOUNDER: 4522 case CHIP_VANGOGH: 4523 case CHIP_DIMGREY_CAVEFISH: 4524 adev->gfx.me.num_me = 1; 4525 adev->gfx.me.num_pipe_per_me = 1; 4526 adev->gfx.me.num_queue_per_pipe = 1; 4527 adev->gfx.mec.num_mec = 2; 4528 adev->gfx.mec.num_pipe_per_mec = 4; 4529 adev->gfx.mec.num_queue_per_pipe = 4; 4530 break; 4531 default: 4532 adev->gfx.me.num_me = 1; 4533 adev->gfx.me.num_pipe_per_me = 1; 4534 adev->gfx.me.num_queue_per_pipe = 1; 4535 adev->gfx.mec.num_mec = 1; 4536 adev->gfx.mec.num_pipe_per_mec = 4; 4537 adev->gfx.mec.num_queue_per_pipe = 8; 4538 break; 4539 } 4540 4541 /* KIQ event */ 4542 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4543 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4544 &adev->gfx.kiq.irq); 4545 if (r) 4546 return r; 4547 4548 /* EOP Event */ 4549 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4550 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4551 &adev->gfx.eop_irq); 4552 if (r) 4553 return r; 4554 4555 /* Privileged reg */ 4556 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4557 &adev->gfx.priv_reg_irq); 4558 if (r) 4559 return r; 4560 4561 /* Privileged inst */ 4562 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4563 &adev->gfx.priv_inst_irq); 4564 if (r) 4565 return r; 4566 4567 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4568 4569 gfx_v10_0_scratch_init(adev); 4570 4571 r = gfx_v10_0_me_init(adev); 4572 if (r) 4573 return r; 4574 4575 r = gfx_v10_0_rlc_init(adev); 4576 if (r) { 4577 DRM_ERROR("Failed to init rlc BOs!\n"); 4578 return r; 4579 } 4580 4581 r = gfx_v10_0_mec_init(adev); 4582 if (r) { 4583 DRM_ERROR("Failed to init MEC BOs!\n"); 4584 return r; 4585 } 4586 4587 /* set up the gfx ring */ 4588 for (i = 0; i < adev->gfx.me.num_me; i++) { 4589 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4590 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4591 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4592 continue; 4593 4594 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4595 i, k, j); 4596 if (r) 4597 return r; 4598 ring_id++; 4599 } 4600 } 4601 } 4602 4603 ring_id = 0; 4604 /* set up the compute queues - allocate horizontally across pipes */ 4605 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4606 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4607 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4608 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4609 j)) 4610 continue; 4611 4612 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4613 i, k, j); 4614 if (r) 4615 return r; 4616 4617 ring_id++; 4618 } 4619 } 4620 } 4621 4622 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4623 if (r) { 4624 DRM_ERROR("Failed to init KIQ BOs!\n"); 4625 return r; 4626 } 4627 4628 kiq = &adev->gfx.kiq; 4629 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4630 if (r) 4631 return r; 4632 4633 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4634 if (r) 4635 return r; 4636 4637 /* allocate visible FB for rlc auto-loading fw */ 4638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4639 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4640 if (r) 4641 return r; 4642 } 4643 4644 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4645 4646 gfx_v10_0_gpu_early_init(adev); 4647 4648 return 0; 4649 } 4650 4651 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4652 { 4653 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4654 &adev->gfx.pfp.pfp_fw_gpu_addr, 4655 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4656 } 4657 4658 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4659 { 4660 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4661 &adev->gfx.ce.ce_fw_gpu_addr, 4662 (void **)&adev->gfx.ce.ce_fw_ptr); 4663 } 4664 4665 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4666 { 4667 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4668 &adev->gfx.me.me_fw_gpu_addr, 4669 (void **)&adev->gfx.me.me_fw_ptr); 4670 } 4671 4672 static int gfx_v10_0_sw_fini(void *handle) 4673 { 4674 int i; 4675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4676 4677 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4678 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4679 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4680 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4681 4682 amdgpu_gfx_mqd_sw_fini(adev); 4683 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4684 amdgpu_gfx_kiq_fini(adev); 4685 4686 gfx_v10_0_pfp_fini(adev); 4687 gfx_v10_0_ce_fini(adev); 4688 gfx_v10_0_me_fini(adev); 4689 gfx_v10_0_rlc_fini(adev); 4690 gfx_v10_0_mec_fini(adev); 4691 4692 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4693 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4694 4695 gfx_v10_0_free_microcode(adev); 4696 4697 return 0; 4698 } 4699 4700 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4701 u32 sh_num, u32 instance) 4702 { 4703 u32 data; 4704 4705 if (instance == 0xffffffff) 4706 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4707 INSTANCE_BROADCAST_WRITES, 1); 4708 else 4709 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4710 instance); 4711 4712 if (se_num == 0xffffffff) 4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4714 1); 4715 else 4716 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4717 4718 if (sh_num == 0xffffffff) 4719 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4720 1); 4721 else 4722 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4723 4724 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4725 } 4726 4727 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4728 { 4729 u32 data, mask; 4730 4731 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4732 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4733 4734 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4735 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4736 4737 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4738 adev->gfx.config.max_sh_per_se); 4739 4740 return (~data) & mask; 4741 } 4742 4743 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4744 { 4745 int i, j; 4746 u32 data; 4747 u32 active_rbs = 0; 4748 u32 bitmap; 4749 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4750 adev->gfx.config.max_sh_per_se; 4751 4752 mutex_lock(&adev->grbm_idx_mutex); 4753 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4754 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4755 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4756 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4757 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4758 continue; 4759 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4760 data = gfx_v10_0_get_rb_active_bitmap(adev); 4761 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4762 rb_bitmap_width_per_sh); 4763 } 4764 } 4765 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4766 mutex_unlock(&adev->grbm_idx_mutex); 4767 4768 adev->gfx.config.backend_enable_mask = active_rbs; 4769 adev->gfx.config.num_rbs = hweight32(active_rbs); 4770 } 4771 4772 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4773 { 4774 uint32_t num_sc; 4775 uint32_t enabled_rb_per_sh; 4776 uint32_t active_rb_bitmap; 4777 uint32_t num_rb_per_sc; 4778 uint32_t num_packer_per_sc; 4779 uint32_t pa_sc_tile_steering_override; 4780 4781 /* for ASICs that integrates GFX v10.3 4782 * pa_sc_tile_steering_override should be set to 0 */ 4783 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4784 return 0; 4785 4786 /* init num_sc */ 4787 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4788 adev->gfx.config.num_sc_per_sh; 4789 /* init num_rb_per_sc */ 4790 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4791 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4792 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4793 /* init num_packer_per_sc */ 4794 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4795 4796 pa_sc_tile_steering_override = 0; 4797 pa_sc_tile_steering_override |= 4798 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4799 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4800 pa_sc_tile_steering_override |= 4801 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4802 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4803 pa_sc_tile_steering_override |= 4804 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4805 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4806 4807 return pa_sc_tile_steering_override; 4808 } 4809 4810 #define DEFAULT_SH_MEM_BASES (0x6000) 4811 4812 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4813 { 4814 int i; 4815 uint32_t sh_mem_bases; 4816 4817 /* 4818 * Configure apertures: 4819 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4820 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4821 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4822 */ 4823 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4824 4825 mutex_lock(&adev->srbm_mutex); 4826 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4827 nv_grbm_select(adev, 0, 0, 0, i); 4828 /* CP and shaders */ 4829 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4830 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4831 } 4832 nv_grbm_select(adev, 0, 0, 0, 0); 4833 mutex_unlock(&adev->srbm_mutex); 4834 4835 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4836 acccess. These should be enabled by FW for target VMIDs. */ 4837 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4838 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4839 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4840 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4841 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4842 } 4843 } 4844 4845 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4846 { 4847 int vmid; 4848 4849 /* 4850 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4851 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4852 * the driver can enable them for graphics. VMID0 should maintain 4853 * access so that HWS firmware can save/restore entries. 4854 */ 4855 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4856 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4857 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4858 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4859 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4860 } 4861 } 4862 4863 4864 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4865 { 4866 int i, j, k; 4867 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4868 u32 tmp, wgp_active_bitmap = 0; 4869 u32 gcrd_targets_disable_tcp = 0; 4870 u32 utcl_invreq_disable = 0; 4871 /* 4872 * GCRD_TARGETS_DISABLE field contains 4873 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4874 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4875 */ 4876 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4877 2 * max_wgp_per_sh + /* TCP */ 4878 max_wgp_per_sh + /* SQC */ 4879 4); /* GL1C */ 4880 /* 4881 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4882 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4883 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4884 */ 4885 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4886 2 * max_wgp_per_sh + /* TCP */ 4887 2 * max_wgp_per_sh + /* SQC */ 4888 4 + /* RMI */ 4889 1); /* SQG */ 4890 4891 if (adev->asic_type == CHIP_NAVI10 || 4892 adev->asic_type == CHIP_NAVI14 || 4893 adev->asic_type == CHIP_NAVI12) { 4894 mutex_lock(&adev->grbm_idx_mutex); 4895 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4896 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4897 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4898 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4899 /* 4900 * Set corresponding TCP bits for the inactive WGPs in 4901 * GCRD_SA_TARGETS_DISABLE 4902 */ 4903 gcrd_targets_disable_tcp = 0; 4904 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4905 utcl_invreq_disable = 0; 4906 4907 for (k = 0; k < max_wgp_per_sh; k++) { 4908 if (!(wgp_active_bitmap & (1 << k))) { 4909 gcrd_targets_disable_tcp |= 3 << (2 * k); 4910 utcl_invreq_disable |= (3 << (2 * k)) | 4911 (3 << (2 * (max_wgp_per_sh + k))); 4912 } 4913 } 4914 4915 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4916 /* only override TCP & SQC bits */ 4917 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4918 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4919 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4920 4921 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4922 /* only override TCP bits */ 4923 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4924 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4925 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4926 } 4927 } 4928 4929 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4930 mutex_unlock(&adev->grbm_idx_mutex); 4931 } 4932 } 4933 4934 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4935 { 4936 /* TCCs are global (not instanced). */ 4937 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4938 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4939 4940 adev->gfx.config.tcc_disabled_mask = 4941 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4942 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4943 } 4944 4945 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4946 { 4947 u32 tmp; 4948 int i; 4949 4950 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4951 4952 gfx_v10_0_setup_rb(adev); 4953 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4954 gfx_v10_0_get_tcc_info(adev); 4955 adev->gfx.config.pa_sc_tile_steering_override = 4956 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4957 4958 /* XXX SH_MEM regs */ 4959 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4960 mutex_lock(&adev->srbm_mutex); 4961 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4962 nv_grbm_select(adev, 0, 0, 0, i); 4963 /* CP and shaders */ 4964 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4965 if (i != 0) { 4966 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4967 (adev->gmc.private_aperture_start >> 48)); 4968 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4969 (adev->gmc.shared_aperture_start >> 48)); 4970 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4971 } 4972 } 4973 nv_grbm_select(adev, 0, 0, 0, 0); 4974 4975 mutex_unlock(&adev->srbm_mutex); 4976 4977 gfx_v10_0_init_compute_vmid(adev); 4978 gfx_v10_0_init_gds_vmid(adev); 4979 4980 } 4981 4982 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4983 bool enable) 4984 { 4985 u32 tmp; 4986 4987 if (amdgpu_sriov_vf(adev)) 4988 return; 4989 4990 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4991 4992 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4993 enable ? 1 : 0); 4994 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4995 enable ? 1 : 0); 4996 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4997 enable ? 1 : 0); 4998 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 4999 enable ? 1 : 0); 5000 5001 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5002 } 5003 5004 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5005 { 5006 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5007 5008 /* csib */ 5009 if (adev->asic_type == CHIP_NAVI12) { 5010 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5011 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5012 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5013 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5014 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5015 } else { 5016 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5017 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5018 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5019 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5020 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5021 } 5022 return 0; 5023 } 5024 5025 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5026 { 5027 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5028 5029 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5030 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5031 } 5032 5033 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5034 { 5035 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5036 udelay(50); 5037 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5038 udelay(50); 5039 } 5040 5041 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5042 bool enable) 5043 { 5044 uint32_t rlc_pg_cntl; 5045 5046 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5047 5048 if (!enable) { 5049 /* RLC_PG_CNTL[23] = 0 (default) 5050 * RLC will wait for handshake acks with SMU 5051 * GFXOFF will be enabled 5052 * RLC_PG_CNTL[23] = 1 5053 * RLC will not issue any message to SMU 5054 * hence no handshake between SMU & RLC 5055 * GFXOFF will be disabled 5056 */ 5057 rlc_pg_cntl |= 0x800000; 5058 } else 5059 rlc_pg_cntl &= ~0x800000; 5060 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5061 } 5062 5063 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5064 { 5065 /* TODO: enable rlc & smu handshake until smu 5066 * and gfxoff feature works as expected */ 5067 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5068 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5069 5070 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5071 udelay(50); 5072 } 5073 5074 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5075 { 5076 uint32_t tmp; 5077 5078 /* enable Save Restore Machine */ 5079 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5080 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5081 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5082 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5083 } 5084 5085 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5086 { 5087 const struct rlc_firmware_header_v2_0 *hdr; 5088 const __le32 *fw_data; 5089 unsigned i, fw_size; 5090 5091 if (!adev->gfx.rlc_fw) 5092 return -EINVAL; 5093 5094 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5095 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5096 5097 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5098 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5099 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5100 5101 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5102 RLCG_UCODE_LOADING_START_ADDRESS); 5103 5104 for (i = 0; i < fw_size; i++) 5105 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5106 le32_to_cpup(fw_data++)); 5107 5108 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5109 5110 return 0; 5111 } 5112 5113 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5114 { 5115 int r; 5116 5117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5118 5119 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5120 if (r) 5121 return r; 5122 5123 gfx_v10_0_init_csb(adev); 5124 5125 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5126 gfx_v10_0_rlc_enable_srm(adev); 5127 } else { 5128 if (amdgpu_sriov_vf(adev)) { 5129 gfx_v10_0_init_csb(adev); 5130 return 0; 5131 } 5132 5133 adev->gfx.rlc.funcs->stop(adev); 5134 5135 /* disable CG */ 5136 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5137 5138 /* disable PG */ 5139 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5140 5141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5142 /* legacy rlc firmware loading */ 5143 r = gfx_v10_0_rlc_load_microcode(adev); 5144 if (r) 5145 return r; 5146 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5147 /* rlc backdoor autoload firmware */ 5148 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5149 if (r) 5150 return r; 5151 } 5152 5153 gfx_v10_0_init_csb(adev); 5154 5155 adev->gfx.rlc.funcs->start(adev); 5156 5157 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5158 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5159 if (r) 5160 return r; 5161 } 5162 } 5163 return 0; 5164 } 5165 5166 static struct { 5167 FIRMWARE_ID id; 5168 unsigned int offset; 5169 unsigned int size; 5170 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5171 5172 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5173 { 5174 int ret; 5175 RLC_TABLE_OF_CONTENT *rlc_toc; 5176 5177 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5178 AMDGPU_GEM_DOMAIN_GTT, 5179 &adev->gfx.rlc.rlc_toc_bo, 5180 &adev->gfx.rlc.rlc_toc_gpu_addr, 5181 (void **)&adev->gfx.rlc.rlc_toc_buf); 5182 if (ret) { 5183 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5184 return ret; 5185 } 5186 5187 /* Copy toc from psp sos fw to rlc toc buffer */ 5188 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5189 5190 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5191 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5192 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5193 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5194 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5195 /* Offset needs 4KB alignment */ 5196 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5197 } 5198 5199 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5200 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5201 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5202 5203 rlc_toc++; 5204 } 5205 5206 return 0; 5207 } 5208 5209 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5210 { 5211 uint32_t total_size = 0; 5212 FIRMWARE_ID id; 5213 int ret; 5214 5215 ret = gfx_v10_0_parse_rlc_toc(adev); 5216 if (ret) { 5217 dev_err(adev->dev, "failed to parse rlc toc\n"); 5218 return 0; 5219 } 5220 5221 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5222 total_size += rlc_autoload_info[id].size; 5223 5224 /* In case the offset in rlc toc ucode is aligned */ 5225 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5226 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5227 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5228 5229 return total_size; 5230 } 5231 5232 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5233 { 5234 int r; 5235 uint32_t total_size; 5236 5237 total_size = gfx_v10_0_calc_toc_total_size(adev); 5238 5239 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5240 AMDGPU_GEM_DOMAIN_GTT, 5241 &adev->gfx.rlc.rlc_autoload_bo, 5242 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5243 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5244 if (r) { 5245 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5246 return r; 5247 } 5248 5249 return 0; 5250 } 5251 5252 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5253 { 5254 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5255 &adev->gfx.rlc.rlc_toc_gpu_addr, 5256 (void **)&adev->gfx.rlc.rlc_toc_buf); 5257 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5258 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5259 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5260 } 5261 5262 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5263 FIRMWARE_ID id, 5264 const void *fw_data, 5265 uint32_t fw_size) 5266 { 5267 uint32_t toc_offset; 5268 uint32_t toc_fw_size; 5269 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5270 5271 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5272 return; 5273 5274 toc_offset = rlc_autoload_info[id].offset; 5275 toc_fw_size = rlc_autoload_info[id].size; 5276 5277 if (fw_size == 0) 5278 fw_size = toc_fw_size; 5279 5280 if (fw_size > toc_fw_size) 5281 fw_size = toc_fw_size; 5282 5283 memcpy(ptr + toc_offset, fw_data, fw_size); 5284 5285 if (fw_size < toc_fw_size) 5286 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5287 } 5288 5289 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5290 { 5291 void *data; 5292 uint32_t size; 5293 5294 data = adev->gfx.rlc.rlc_toc_buf; 5295 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5296 5297 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5298 FIRMWARE_ID_RLC_TOC, 5299 data, size); 5300 } 5301 5302 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5303 { 5304 const __le32 *fw_data; 5305 uint32_t fw_size; 5306 const struct gfx_firmware_header_v1_0 *cp_hdr; 5307 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5308 5309 /* pfp ucode */ 5310 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5311 adev->gfx.pfp_fw->data; 5312 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5313 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5314 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5315 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5316 FIRMWARE_ID_CP_PFP, 5317 fw_data, fw_size); 5318 5319 /* ce ucode */ 5320 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5321 adev->gfx.ce_fw->data; 5322 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5323 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5324 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5325 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5326 FIRMWARE_ID_CP_CE, 5327 fw_data, fw_size); 5328 5329 /* me ucode */ 5330 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5331 adev->gfx.me_fw->data; 5332 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5333 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5334 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5335 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5336 FIRMWARE_ID_CP_ME, 5337 fw_data, fw_size); 5338 5339 /* rlc ucode */ 5340 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5341 adev->gfx.rlc_fw->data; 5342 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5343 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5344 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5345 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5346 FIRMWARE_ID_RLC_G_UCODE, 5347 fw_data, fw_size); 5348 5349 /* mec1 ucode */ 5350 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5351 adev->gfx.mec_fw->data; 5352 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5353 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5354 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5355 cp_hdr->jt_size * 4; 5356 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5357 FIRMWARE_ID_CP_MEC, 5358 fw_data, fw_size); 5359 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5360 } 5361 5362 /* Temporarily put sdma part here */ 5363 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5364 { 5365 const __le32 *fw_data; 5366 uint32_t fw_size; 5367 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5368 int i; 5369 5370 for (i = 0; i < adev->sdma.num_instances; i++) { 5371 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5372 adev->sdma.instance[i].fw->data; 5373 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5374 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5375 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5376 5377 if (i == 0) { 5378 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5379 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5380 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5381 FIRMWARE_ID_SDMA0_JT, 5382 (uint32_t *)fw_data + 5383 sdma_hdr->jt_offset, 5384 sdma_hdr->jt_size * 4); 5385 } else if (i == 1) { 5386 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5387 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5388 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5389 FIRMWARE_ID_SDMA1_JT, 5390 (uint32_t *)fw_data + 5391 sdma_hdr->jt_offset, 5392 sdma_hdr->jt_size * 4); 5393 } 5394 } 5395 } 5396 5397 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5398 { 5399 uint32_t rlc_g_offset, rlc_g_size, tmp; 5400 uint64_t gpu_addr; 5401 5402 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5403 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5404 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5405 5406 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5407 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5408 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5409 5410 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5411 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5412 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5413 5414 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5415 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5416 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5417 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5418 return -EINVAL; 5419 } 5420 5421 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5422 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5423 DRM_ERROR("RLC ROM should halt itself\n"); 5424 return -EINVAL; 5425 } 5426 5427 return 0; 5428 } 5429 5430 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5431 { 5432 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5433 uint32_t tmp; 5434 int i; 5435 uint64_t addr; 5436 5437 /* Trigger an invalidation of the L1 instruction caches */ 5438 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5439 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5440 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5441 5442 /* Wait for invalidation complete */ 5443 for (i = 0; i < usec_timeout; i++) { 5444 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5445 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5446 INVALIDATE_CACHE_COMPLETE)) 5447 break; 5448 udelay(1); 5449 } 5450 5451 if (i >= usec_timeout) { 5452 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5453 return -EINVAL; 5454 } 5455 5456 /* Program me ucode address into intruction cache address register */ 5457 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5458 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5459 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5460 lower_32_bits(addr) & 0xFFFFF000); 5461 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5462 upper_32_bits(addr)); 5463 5464 return 0; 5465 } 5466 5467 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5468 { 5469 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5470 uint32_t tmp; 5471 int i; 5472 uint64_t addr; 5473 5474 /* Trigger an invalidation of the L1 instruction caches */ 5475 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5476 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5477 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5478 5479 /* Wait for invalidation complete */ 5480 for (i = 0; i < usec_timeout; i++) { 5481 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5482 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5483 INVALIDATE_CACHE_COMPLETE)) 5484 break; 5485 udelay(1); 5486 } 5487 5488 if (i >= usec_timeout) { 5489 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5490 return -EINVAL; 5491 } 5492 5493 /* Program ce ucode address into intruction cache address register */ 5494 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5495 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5496 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5497 lower_32_bits(addr) & 0xFFFFF000); 5498 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5499 upper_32_bits(addr)); 5500 5501 return 0; 5502 } 5503 5504 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5505 { 5506 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5507 uint32_t tmp; 5508 int i; 5509 uint64_t addr; 5510 5511 /* Trigger an invalidation of the L1 instruction caches */ 5512 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5513 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5514 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5515 5516 /* Wait for invalidation complete */ 5517 for (i = 0; i < usec_timeout; i++) { 5518 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5519 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5520 INVALIDATE_CACHE_COMPLETE)) 5521 break; 5522 udelay(1); 5523 } 5524 5525 if (i >= usec_timeout) { 5526 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5527 return -EINVAL; 5528 } 5529 5530 /* Program pfp ucode address into intruction cache address register */ 5531 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5532 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5533 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5534 lower_32_bits(addr) & 0xFFFFF000); 5535 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5536 upper_32_bits(addr)); 5537 5538 return 0; 5539 } 5540 5541 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5542 { 5543 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5544 uint32_t tmp; 5545 int i; 5546 uint64_t addr; 5547 5548 /* Trigger an invalidation of the L1 instruction caches */ 5549 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5550 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5551 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5552 5553 /* Wait for invalidation complete */ 5554 for (i = 0; i < usec_timeout; i++) { 5555 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5556 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5557 INVALIDATE_CACHE_COMPLETE)) 5558 break; 5559 udelay(1); 5560 } 5561 5562 if (i >= usec_timeout) { 5563 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5564 return -EINVAL; 5565 } 5566 5567 /* Program mec1 ucode address into intruction cache address register */ 5568 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5569 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5570 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5571 lower_32_bits(addr) & 0xFFFFF000); 5572 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5573 upper_32_bits(addr)); 5574 5575 return 0; 5576 } 5577 5578 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5579 { 5580 uint32_t cp_status; 5581 uint32_t bootload_status; 5582 int i, r; 5583 5584 for (i = 0; i < adev->usec_timeout; i++) { 5585 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5586 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5587 if ((cp_status == 0) && 5588 (REG_GET_FIELD(bootload_status, 5589 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5590 break; 5591 } 5592 udelay(1); 5593 } 5594 5595 if (i >= adev->usec_timeout) { 5596 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5597 return -ETIMEDOUT; 5598 } 5599 5600 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5601 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5602 if (r) 5603 return r; 5604 5605 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5606 if (r) 5607 return r; 5608 5609 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5610 if (r) 5611 return r; 5612 5613 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5614 if (r) 5615 return r; 5616 } 5617 5618 return 0; 5619 } 5620 5621 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5622 { 5623 int i; 5624 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5625 5626 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5627 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5628 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5629 5630 if (adev->asic_type == CHIP_NAVI12) { 5631 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5632 } else { 5633 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5634 } 5635 5636 for (i = 0; i < adev->usec_timeout; i++) { 5637 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5638 break; 5639 udelay(1); 5640 } 5641 5642 if (i >= adev->usec_timeout) 5643 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5644 5645 return 0; 5646 } 5647 5648 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5649 { 5650 int r; 5651 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5652 const __le32 *fw_data; 5653 unsigned i, fw_size; 5654 uint32_t tmp; 5655 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5656 5657 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5658 adev->gfx.pfp_fw->data; 5659 5660 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5661 5662 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5663 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5664 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5665 5666 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5667 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5668 &adev->gfx.pfp.pfp_fw_obj, 5669 &adev->gfx.pfp.pfp_fw_gpu_addr, 5670 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5671 if (r) { 5672 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5673 gfx_v10_0_pfp_fini(adev); 5674 return r; 5675 } 5676 5677 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5678 5679 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5680 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5681 5682 /* Trigger an invalidation of the L1 instruction caches */ 5683 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5684 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5685 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5686 5687 /* Wait for invalidation complete */ 5688 for (i = 0; i < usec_timeout; i++) { 5689 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5690 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5691 INVALIDATE_CACHE_COMPLETE)) 5692 break; 5693 udelay(1); 5694 } 5695 5696 if (i >= usec_timeout) { 5697 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5698 return -EINVAL; 5699 } 5700 5701 if (amdgpu_emu_mode == 1) 5702 adev->nbio.funcs->hdp_flush(adev, NULL); 5703 5704 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5705 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5706 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5707 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5708 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5709 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5710 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5711 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5712 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5713 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5714 5715 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5716 5717 for (i = 0; i < pfp_hdr->jt_size; i++) 5718 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5719 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5720 5721 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5722 5723 return 0; 5724 } 5725 5726 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5727 { 5728 int r; 5729 const struct gfx_firmware_header_v1_0 *ce_hdr; 5730 const __le32 *fw_data; 5731 unsigned i, fw_size; 5732 uint32_t tmp; 5733 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5734 5735 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5736 adev->gfx.ce_fw->data; 5737 5738 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5739 5740 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5741 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5742 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5743 5744 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5745 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5746 &adev->gfx.ce.ce_fw_obj, 5747 &adev->gfx.ce.ce_fw_gpu_addr, 5748 (void **)&adev->gfx.ce.ce_fw_ptr); 5749 if (r) { 5750 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5751 gfx_v10_0_ce_fini(adev); 5752 return r; 5753 } 5754 5755 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5756 5757 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5758 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5759 5760 /* Trigger an invalidation of the L1 instruction caches */ 5761 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5762 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5763 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5764 5765 /* Wait for invalidation complete */ 5766 for (i = 0; i < usec_timeout; i++) { 5767 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5768 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5769 INVALIDATE_CACHE_COMPLETE)) 5770 break; 5771 udelay(1); 5772 } 5773 5774 if (i >= usec_timeout) { 5775 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5776 return -EINVAL; 5777 } 5778 5779 if (amdgpu_emu_mode == 1) 5780 adev->nbio.funcs->hdp_flush(adev, NULL); 5781 5782 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5783 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5784 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5785 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5786 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5787 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5788 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5789 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5790 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5791 5792 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5793 5794 for (i = 0; i < ce_hdr->jt_size; i++) 5795 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5796 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5797 5798 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5799 5800 return 0; 5801 } 5802 5803 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5804 { 5805 int r; 5806 const struct gfx_firmware_header_v1_0 *me_hdr; 5807 const __le32 *fw_data; 5808 unsigned i, fw_size; 5809 uint32_t tmp; 5810 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5811 5812 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5813 adev->gfx.me_fw->data; 5814 5815 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5816 5817 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5818 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5819 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5820 5821 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5822 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5823 &adev->gfx.me.me_fw_obj, 5824 &adev->gfx.me.me_fw_gpu_addr, 5825 (void **)&adev->gfx.me.me_fw_ptr); 5826 if (r) { 5827 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5828 gfx_v10_0_me_fini(adev); 5829 return r; 5830 } 5831 5832 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5833 5834 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5835 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5836 5837 /* Trigger an invalidation of the L1 instruction caches */ 5838 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5839 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5840 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5841 5842 /* Wait for invalidation complete */ 5843 for (i = 0; i < usec_timeout; i++) { 5844 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5845 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5846 INVALIDATE_CACHE_COMPLETE)) 5847 break; 5848 udelay(1); 5849 } 5850 5851 if (i >= usec_timeout) { 5852 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5853 return -EINVAL; 5854 } 5855 5856 if (amdgpu_emu_mode == 1) 5857 adev->nbio.funcs->hdp_flush(adev, NULL); 5858 5859 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5860 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5861 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5862 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5863 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5864 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5865 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5866 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5867 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5868 5869 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5870 5871 for (i = 0; i < me_hdr->jt_size; i++) 5872 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5873 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5874 5875 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5876 5877 return 0; 5878 } 5879 5880 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5881 { 5882 int r; 5883 5884 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5885 return -EINVAL; 5886 5887 gfx_v10_0_cp_gfx_enable(adev, false); 5888 5889 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5890 if (r) { 5891 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5892 return r; 5893 } 5894 5895 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5896 if (r) { 5897 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5898 return r; 5899 } 5900 5901 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5902 if (r) { 5903 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5904 return r; 5905 } 5906 5907 return 0; 5908 } 5909 5910 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5911 { 5912 struct amdgpu_ring *ring; 5913 const struct cs_section_def *sect = NULL; 5914 const struct cs_extent_def *ext = NULL; 5915 int r, i; 5916 int ctx_reg_offset; 5917 5918 /* init the CP */ 5919 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5920 adev->gfx.config.max_hw_contexts - 1); 5921 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5922 5923 gfx_v10_0_cp_gfx_enable(adev, true); 5924 5925 ring = &adev->gfx.gfx_ring[0]; 5926 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5927 if (r) { 5928 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5929 return r; 5930 } 5931 5932 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5933 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5934 5935 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5936 amdgpu_ring_write(ring, 0x80000000); 5937 amdgpu_ring_write(ring, 0x80000000); 5938 5939 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5940 for (ext = sect->section; ext->extent != NULL; ++ext) { 5941 if (sect->id == SECT_CONTEXT) { 5942 amdgpu_ring_write(ring, 5943 PACKET3(PACKET3_SET_CONTEXT_REG, 5944 ext->reg_count)); 5945 amdgpu_ring_write(ring, ext->reg_index - 5946 PACKET3_SET_CONTEXT_REG_START); 5947 for (i = 0; i < ext->reg_count; i++) 5948 amdgpu_ring_write(ring, ext->extent[i]); 5949 } 5950 } 5951 } 5952 5953 ctx_reg_offset = 5954 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5955 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5956 amdgpu_ring_write(ring, ctx_reg_offset); 5957 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5958 5959 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5960 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5961 5962 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5963 amdgpu_ring_write(ring, 0); 5964 5965 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5966 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5967 amdgpu_ring_write(ring, 0x8000); 5968 amdgpu_ring_write(ring, 0x8000); 5969 5970 amdgpu_ring_commit(ring); 5971 5972 /* submit cs packet to copy state 0 to next available state */ 5973 if (adev->gfx.num_gfx_rings > 1) { 5974 /* maximum supported gfx ring is 2 */ 5975 ring = &adev->gfx.gfx_ring[1]; 5976 r = amdgpu_ring_alloc(ring, 2); 5977 if (r) { 5978 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5979 return r; 5980 } 5981 5982 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5983 amdgpu_ring_write(ring, 0); 5984 5985 amdgpu_ring_commit(ring); 5986 } 5987 return 0; 5988 } 5989 5990 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5991 CP_PIPE_ID pipe) 5992 { 5993 u32 tmp; 5994 5995 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5996 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5997 5998 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 5999 } 6000 6001 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6002 struct amdgpu_ring *ring) 6003 { 6004 u32 tmp; 6005 6006 if (!amdgpu_async_gfx_ring) { 6007 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6008 if (ring->use_doorbell) { 6009 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6010 DOORBELL_OFFSET, ring->doorbell_index); 6011 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6012 DOORBELL_EN, 1); 6013 } else { 6014 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6015 DOORBELL_EN, 0); 6016 } 6017 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6018 } 6019 switch (adev->asic_type) { 6020 case CHIP_SIENNA_CICHLID: 6021 case CHIP_NAVY_FLOUNDER: 6022 case CHIP_VANGOGH: 6023 case CHIP_DIMGREY_CAVEFISH: 6024 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6025 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6026 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6027 6028 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6029 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6030 break; 6031 default: 6032 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6033 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6034 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6035 6036 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6037 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6038 break; 6039 } 6040 } 6041 6042 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6043 { 6044 struct amdgpu_ring *ring; 6045 u32 tmp; 6046 u32 rb_bufsz; 6047 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6048 u32 i; 6049 6050 /* Set the write pointer delay */ 6051 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6052 6053 /* set the RB to use vmid 0 */ 6054 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6055 6056 /* Init gfx ring 0 for pipe 0 */ 6057 mutex_lock(&adev->srbm_mutex); 6058 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6059 6060 /* Set ring buffer size */ 6061 ring = &adev->gfx.gfx_ring[0]; 6062 rb_bufsz = order_base_2(ring->ring_size / 8); 6063 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6064 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6065 #ifdef __BIG_ENDIAN 6066 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6067 #endif 6068 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6069 6070 /* Initialize the ring buffer's write pointers */ 6071 ring->wptr = 0; 6072 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6073 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6074 6075 /* set the wb address wether it's enabled or not */ 6076 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6077 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6078 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6079 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6080 6081 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6082 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6083 lower_32_bits(wptr_gpu_addr)); 6084 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6085 upper_32_bits(wptr_gpu_addr)); 6086 6087 mdelay(1); 6088 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6089 6090 rb_addr = ring->gpu_addr >> 8; 6091 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6092 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6093 6094 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6095 6096 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6097 mutex_unlock(&adev->srbm_mutex); 6098 6099 /* Init gfx ring 1 for pipe 1 */ 6100 if (adev->gfx.num_gfx_rings > 1) { 6101 mutex_lock(&adev->srbm_mutex); 6102 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6103 /* maximum supported gfx ring is 2 */ 6104 ring = &adev->gfx.gfx_ring[1]; 6105 rb_bufsz = order_base_2(ring->ring_size / 8); 6106 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6107 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6108 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6109 /* Initialize the ring buffer's write pointers */ 6110 ring->wptr = 0; 6111 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6112 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6113 /* Set the wb address wether it's enabled or not */ 6114 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6115 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6116 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6117 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6118 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6119 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6120 lower_32_bits(wptr_gpu_addr)); 6121 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6122 upper_32_bits(wptr_gpu_addr)); 6123 6124 mdelay(1); 6125 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6126 6127 rb_addr = ring->gpu_addr >> 8; 6128 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6129 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6130 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6131 6132 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6133 mutex_unlock(&adev->srbm_mutex); 6134 } 6135 /* Switch to pipe 0 */ 6136 mutex_lock(&adev->srbm_mutex); 6137 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6138 mutex_unlock(&adev->srbm_mutex); 6139 6140 /* start the ring */ 6141 gfx_v10_0_cp_gfx_start(adev); 6142 6143 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6144 ring = &adev->gfx.gfx_ring[i]; 6145 ring->sched.ready = true; 6146 } 6147 6148 return 0; 6149 } 6150 6151 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6152 { 6153 if (enable) { 6154 switch (adev->asic_type) { 6155 case CHIP_SIENNA_CICHLID: 6156 case CHIP_NAVY_FLOUNDER: 6157 case CHIP_VANGOGH: 6158 case CHIP_DIMGREY_CAVEFISH: 6159 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6160 break; 6161 default: 6162 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6163 break; 6164 } 6165 } else { 6166 switch (adev->asic_type) { 6167 case CHIP_SIENNA_CICHLID: 6168 case CHIP_NAVY_FLOUNDER: 6169 case CHIP_VANGOGH: 6170 case CHIP_DIMGREY_CAVEFISH: 6171 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6172 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6173 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6174 break; 6175 default: 6176 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6177 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6178 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6179 break; 6180 } 6181 adev->gfx.kiq.ring.sched.ready = false; 6182 } 6183 udelay(50); 6184 } 6185 6186 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6187 { 6188 const struct gfx_firmware_header_v1_0 *mec_hdr; 6189 const __le32 *fw_data; 6190 unsigned i; 6191 u32 tmp; 6192 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6193 6194 if (!adev->gfx.mec_fw) 6195 return -EINVAL; 6196 6197 gfx_v10_0_cp_compute_enable(adev, false); 6198 6199 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6200 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6201 6202 fw_data = (const __le32 *) 6203 (adev->gfx.mec_fw->data + 6204 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6205 6206 /* Trigger an invalidation of the L1 instruction caches */ 6207 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6208 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6209 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6210 6211 /* Wait for invalidation complete */ 6212 for (i = 0; i < usec_timeout; i++) { 6213 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6214 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6215 INVALIDATE_CACHE_COMPLETE)) 6216 break; 6217 udelay(1); 6218 } 6219 6220 if (i >= usec_timeout) { 6221 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6222 return -EINVAL; 6223 } 6224 6225 if (amdgpu_emu_mode == 1) 6226 adev->nbio.funcs->hdp_flush(adev, NULL); 6227 6228 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6229 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6230 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6231 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6232 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6233 6234 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6235 0xFFFFF000); 6236 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6237 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6238 6239 /* MEC1 */ 6240 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6241 6242 for (i = 0; i < mec_hdr->jt_size; i++) 6243 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6244 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6245 6246 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6247 6248 /* 6249 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6250 * different microcode than MEC1. 6251 */ 6252 6253 return 0; 6254 } 6255 6256 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6257 { 6258 uint32_t tmp; 6259 struct amdgpu_device *adev = ring->adev; 6260 6261 /* tell RLC which is KIQ queue */ 6262 switch (adev->asic_type) { 6263 case CHIP_SIENNA_CICHLID: 6264 case CHIP_NAVY_FLOUNDER: 6265 case CHIP_VANGOGH: 6266 case CHIP_DIMGREY_CAVEFISH: 6267 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6268 tmp &= 0xffffff00; 6269 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6270 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6271 tmp |= 0x80; 6272 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6273 break; 6274 default: 6275 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6276 tmp &= 0xffffff00; 6277 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6278 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6279 tmp |= 0x80; 6280 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6281 break; 6282 } 6283 } 6284 6285 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6286 { 6287 struct amdgpu_device *adev = ring->adev; 6288 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6289 uint64_t hqd_gpu_addr, wb_gpu_addr; 6290 uint32_t tmp; 6291 uint32_t rb_bufsz; 6292 6293 /* set up gfx hqd wptr */ 6294 mqd->cp_gfx_hqd_wptr = 0; 6295 mqd->cp_gfx_hqd_wptr_hi = 0; 6296 6297 /* set the pointer to the MQD */ 6298 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6299 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6300 6301 /* set up mqd control */ 6302 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6303 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6304 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6305 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6306 mqd->cp_gfx_mqd_control = tmp; 6307 6308 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6309 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6310 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6311 mqd->cp_gfx_hqd_vmid = 0; 6312 6313 /* set up default queue priority level 6314 * 0x0 = low priority, 0x1 = high priority */ 6315 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6316 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6317 mqd->cp_gfx_hqd_queue_priority = tmp; 6318 6319 /* set up time quantum */ 6320 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6321 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6322 mqd->cp_gfx_hqd_quantum = tmp; 6323 6324 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6325 hqd_gpu_addr = ring->gpu_addr >> 8; 6326 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6327 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6328 6329 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6330 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6331 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6332 mqd->cp_gfx_hqd_rptr_addr_hi = 6333 upper_32_bits(wb_gpu_addr) & 0xffff; 6334 6335 /* set up rb_wptr_poll addr */ 6336 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6337 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6338 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6339 6340 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6341 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6342 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6343 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6344 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6345 #ifdef __BIG_ENDIAN 6346 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6347 #endif 6348 mqd->cp_gfx_hqd_cntl = tmp; 6349 6350 /* set up cp_doorbell_control */ 6351 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6352 if (ring->use_doorbell) { 6353 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6354 DOORBELL_OFFSET, ring->doorbell_index); 6355 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6356 DOORBELL_EN, 1); 6357 } else 6358 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6359 DOORBELL_EN, 0); 6360 mqd->cp_rb_doorbell_control = tmp; 6361 6362 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6363 *otherwise the range of the second ring will override the first ring */ 6364 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6365 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6366 6367 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6368 ring->wptr = 0; 6369 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6370 6371 /* active the queue */ 6372 mqd->cp_gfx_hqd_active = 1; 6373 6374 return 0; 6375 } 6376 6377 #ifdef BRING_UP_DEBUG 6378 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6379 { 6380 struct amdgpu_device *adev = ring->adev; 6381 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6382 6383 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6384 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6385 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6386 6387 /* set GFX_MQD_BASE */ 6388 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6389 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6390 6391 /* set GFX_MQD_CONTROL */ 6392 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6393 6394 /* set GFX_HQD_VMID to 0 */ 6395 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6396 6397 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6398 mqd->cp_gfx_hqd_queue_priority); 6399 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6400 6401 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6402 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6403 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6404 6405 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6406 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6407 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6408 6409 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6410 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6411 6412 /* set RB_WPTR_POLL_ADDR */ 6413 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6414 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6415 6416 /* set RB_DOORBELL_CONTROL */ 6417 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6418 6419 /* active the queue */ 6420 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6421 6422 return 0; 6423 } 6424 #endif 6425 6426 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6427 { 6428 struct amdgpu_device *adev = ring->adev; 6429 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6430 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6431 6432 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6433 memset((void *)mqd, 0, sizeof(*mqd)); 6434 mutex_lock(&adev->srbm_mutex); 6435 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6436 gfx_v10_0_gfx_mqd_init(ring); 6437 #ifdef BRING_UP_DEBUG 6438 gfx_v10_0_gfx_queue_init_register(ring); 6439 #endif 6440 nv_grbm_select(adev, 0, 0, 0, 0); 6441 mutex_unlock(&adev->srbm_mutex); 6442 if (adev->gfx.me.mqd_backup[mqd_idx]) 6443 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6444 } else if (amdgpu_in_reset(adev)) { 6445 /* reset mqd with the backup copy */ 6446 if (adev->gfx.me.mqd_backup[mqd_idx]) 6447 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6448 /* reset the ring */ 6449 ring->wptr = 0; 6450 adev->wb.wb[ring->wptr_offs] = 0; 6451 amdgpu_ring_clear_ring(ring); 6452 #ifdef BRING_UP_DEBUG 6453 mutex_lock(&adev->srbm_mutex); 6454 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6455 gfx_v10_0_gfx_queue_init_register(ring); 6456 nv_grbm_select(adev, 0, 0, 0, 0); 6457 mutex_unlock(&adev->srbm_mutex); 6458 #endif 6459 } else { 6460 amdgpu_ring_clear_ring(ring); 6461 } 6462 6463 return 0; 6464 } 6465 6466 #ifndef BRING_UP_DEBUG 6467 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6468 { 6469 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6470 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6471 int r, i; 6472 6473 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6474 return -EINVAL; 6475 6476 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6477 adev->gfx.num_gfx_rings); 6478 if (r) { 6479 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6480 return r; 6481 } 6482 6483 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6484 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6485 6486 return amdgpu_ring_test_helper(kiq_ring); 6487 } 6488 #endif 6489 6490 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6491 { 6492 int r, i; 6493 struct amdgpu_ring *ring; 6494 6495 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6496 ring = &adev->gfx.gfx_ring[i]; 6497 6498 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6499 if (unlikely(r != 0)) 6500 goto done; 6501 6502 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6503 if (!r) { 6504 r = gfx_v10_0_gfx_init_queue(ring); 6505 amdgpu_bo_kunmap(ring->mqd_obj); 6506 ring->mqd_ptr = NULL; 6507 } 6508 amdgpu_bo_unreserve(ring->mqd_obj); 6509 if (r) 6510 goto done; 6511 } 6512 #ifndef BRING_UP_DEBUG 6513 r = gfx_v10_0_kiq_enable_kgq(adev); 6514 if (r) 6515 goto done; 6516 #endif 6517 r = gfx_v10_0_cp_gfx_start(adev); 6518 if (r) 6519 goto done; 6520 6521 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6522 ring = &adev->gfx.gfx_ring[i]; 6523 ring->sched.ready = true; 6524 } 6525 done: 6526 return r; 6527 } 6528 6529 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6530 { 6531 struct amdgpu_device *adev = ring->adev; 6532 6533 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6534 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6535 ring->queue)) { 6536 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6537 mqd->cp_hqd_queue_priority = 6538 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6539 } 6540 } 6541 } 6542 6543 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6544 { 6545 struct amdgpu_device *adev = ring->adev; 6546 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6547 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6548 uint32_t tmp; 6549 6550 mqd->header = 0xC0310800; 6551 mqd->compute_pipelinestat_enable = 0x00000001; 6552 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6553 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6554 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6555 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6556 mqd->compute_misc_reserved = 0x00000003; 6557 6558 eop_base_addr = ring->eop_gpu_addr >> 8; 6559 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6560 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6561 6562 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6563 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6564 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6565 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6566 6567 mqd->cp_hqd_eop_control = tmp; 6568 6569 /* enable doorbell? */ 6570 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6571 6572 if (ring->use_doorbell) { 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6574 DOORBELL_OFFSET, ring->doorbell_index); 6575 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6576 DOORBELL_EN, 1); 6577 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6578 DOORBELL_SOURCE, 0); 6579 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6580 DOORBELL_HIT, 0); 6581 } else { 6582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6583 DOORBELL_EN, 0); 6584 } 6585 6586 mqd->cp_hqd_pq_doorbell_control = tmp; 6587 6588 /* disable the queue if it's active */ 6589 ring->wptr = 0; 6590 mqd->cp_hqd_dequeue_request = 0; 6591 mqd->cp_hqd_pq_rptr = 0; 6592 mqd->cp_hqd_pq_wptr_lo = 0; 6593 mqd->cp_hqd_pq_wptr_hi = 0; 6594 6595 /* set the pointer to the MQD */ 6596 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6597 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6598 6599 /* set MQD vmid to 0 */ 6600 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6601 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6602 mqd->cp_mqd_control = tmp; 6603 6604 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6605 hqd_gpu_addr = ring->gpu_addr >> 8; 6606 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6607 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6608 6609 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6610 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6612 (order_base_2(ring->ring_size / 4) - 1)); 6613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6614 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6615 #ifdef __BIG_ENDIAN 6616 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6617 #endif 6618 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6619 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6620 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6621 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6622 mqd->cp_hqd_pq_control = tmp; 6623 6624 /* set the wb address whether it's enabled or not */ 6625 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6626 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6627 mqd->cp_hqd_pq_rptr_report_addr_hi = 6628 upper_32_bits(wb_gpu_addr) & 0xffff; 6629 6630 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6631 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6632 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6633 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6634 6635 tmp = 0; 6636 /* enable the doorbell if requested */ 6637 if (ring->use_doorbell) { 6638 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6639 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6640 DOORBELL_OFFSET, ring->doorbell_index); 6641 6642 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6643 DOORBELL_EN, 1); 6644 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6645 DOORBELL_SOURCE, 0); 6646 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6647 DOORBELL_HIT, 0); 6648 } 6649 6650 mqd->cp_hqd_pq_doorbell_control = tmp; 6651 6652 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6653 ring->wptr = 0; 6654 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6655 6656 /* set the vmid for the queue */ 6657 mqd->cp_hqd_vmid = 0; 6658 6659 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6660 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6661 mqd->cp_hqd_persistent_state = tmp; 6662 6663 /* set MIN_IB_AVAIL_SIZE */ 6664 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6665 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6666 mqd->cp_hqd_ib_control = tmp; 6667 6668 /* set static priority for a compute queue/ring */ 6669 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6670 6671 /* map_queues packet doesn't need activate the queue, 6672 * so only kiq need set this field. 6673 */ 6674 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6675 mqd->cp_hqd_active = 1; 6676 6677 return 0; 6678 } 6679 6680 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6681 { 6682 struct amdgpu_device *adev = ring->adev; 6683 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6684 int j; 6685 6686 /* inactivate the queue */ 6687 if (amdgpu_sriov_vf(adev)) 6688 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6689 6690 /* disable wptr polling */ 6691 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6692 6693 /* write the EOP addr */ 6694 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6695 mqd->cp_hqd_eop_base_addr_lo); 6696 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6697 mqd->cp_hqd_eop_base_addr_hi); 6698 6699 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6700 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6701 mqd->cp_hqd_eop_control); 6702 6703 /* enable doorbell? */ 6704 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6705 mqd->cp_hqd_pq_doorbell_control); 6706 6707 /* disable the queue if it's active */ 6708 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6709 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6710 for (j = 0; j < adev->usec_timeout; j++) { 6711 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6712 break; 6713 udelay(1); 6714 } 6715 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6716 mqd->cp_hqd_dequeue_request); 6717 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6718 mqd->cp_hqd_pq_rptr); 6719 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6720 mqd->cp_hqd_pq_wptr_lo); 6721 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6722 mqd->cp_hqd_pq_wptr_hi); 6723 } 6724 6725 /* set the pointer to the MQD */ 6726 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6727 mqd->cp_mqd_base_addr_lo); 6728 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6729 mqd->cp_mqd_base_addr_hi); 6730 6731 /* set MQD vmid to 0 */ 6732 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6733 mqd->cp_mqd_control); 6734 6735 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6736 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6737 mqd->cp_hqd_pq_base_lo); 6738 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6739 mqd->cp_hqd_pq_base_hi); 6740 6741 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6742 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6743 mqd->cp_hqd_pq_control); 6744 6745 /* set the wb address whether it's enabled or not */ 6746 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6747 mqd->cp_hqd_pq_rptr_report_addr_lo); 6748 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6749 mqd->cp_hqd_pq_rptr_report_addr_hi); 6750 6751 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6752 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6753 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6754 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6755 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6756 6757 /* enable the doorbell if requested */ 6758 if (ring->use_doorbell) { 6759 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6760 (adev->doorbell_index.kiq * 2) << 2); 6761 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6762 (adev->doorbell_index.userqueue_end * 2) << 2); 6763 } 6764 6765 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6766 mqd->cp_hqd_pq_doorbell_control); 6767 6768 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6770 mqd->cp_hqd_pq_wptr_lo); 6771 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6772 mqd->cp_hqd_pq_wptr_hi); 6773 6774 /* set the vmid for the queue */ 6775 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6776 6777 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6778 mqd->cp_hqd_persistent_state); 6779 6780 /* activate the queue */ 6781 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6782 mqd->cp_hqd_active); 6783 6784 if (ring->use_doorbell) 6785 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6786 6787 return 0; 6788 } 6789 6790 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6791 { 6792 struct amdgpu_device *adev = ring->adev; 6793 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6794 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6795 6796 gfx_v10_0_kiq_setting(ring); 6797 6798 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6799 /* reset MQD to a clean status */ 6800 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6801 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6802 6803 /* reset ring buffer */ 6804 ring->wptr = 0; 6805 amdgpu_ring_clear_ring(ring); 6806 6807 mutex_lock(&adev->srbm_mutex); 6808 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6809 gfx_v10_0_kiq_init_register(ring); 6810 nv_grbm_select(adev, 0, 0, 0, 0); 6811 mutex_unlock(&adev->srbm_mutex); 6812 } else { 6813 memset((void *)mqd, 0, sizeof(*mqd)); 6814 mutex_lock(&adev->srbm_mutex); 6815 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6816 gfx_v10_0_compute_mqd_init(ring); 6817 gfx_v10_0_kiq_init_register(ring); 6818 nv_grbm_select(adev, 0, 0, 0, 0); 6819 mutex_unlock(&adev->srbm_mutex); 6820 6821 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6822 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6823 } 6824 6825 return 0; 6826 } 6827 6828 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6829 { 6830 struct amdgpu_device *adev = ring->adev; 6831 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6832 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6833 6834 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6835 memset((void *)mqd, 0, sizeof(*mqd)); 6836 mutex_lock(&adev->srbm_mutex); 6837 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6838 gfx_v10_0_compute_mqd_init(ring); 6839 nv_grbm_select(adev, 0, 0, 0, 0); 6840 mutex_unlock(&adev->srbm_mutex); 6841 6842 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6843 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6844 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6845 /* reset MQD to a clean status */ 6846 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6847 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6848 6849 /* reset ring buffer */ 6850 ring->wptr = 0; 6851 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6852 amdgpu_ring_clear_ring(ring); 6853 } else { 6854 amdgpu_ring_clear_ring(ring); 6855 } 6856 6857 return 0; 6858 } 6859 6860 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6861 { 6862 struct amdgpu_ring *ring; 6863 int r; 6864 6865 ring = &adev->gfx.kiq.ring; 6866 6867 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6868 if (unlikely(r != 0)) 6869 return r; 6870 6871 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6872 if (unlikely(r != 0)) 6873 return r; 6874 6875 gfx_v10_0_kiq_init_queue(ring); 6876 amdgpu_bo_kunmap(ring->mqd_obj); 6877 ring->mqd_ptr = NULL; 6878 amdgpu_bo_unreserve(ring->mqd_obj); 6879 ring->sched.ready = true; 6880 return 0; 6881 } 6882 6883 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6884 { 6885 struct amdgpu_ring *ring = NULL; 6886 int r = 0, i; 6887 6888 gfx_v10_0_cp_compute_enable(adev, true); 6889 6890 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6891 ring = &adev->gfx.compute_ring[i]; 6892 6893 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6894 if (unlikely(r != 0)) 6895 goto done; 6896 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6897 if (!r) { 6898 r = gfx_v10_0_kcq_init_queue(ring); 6899 amdgpu_bo_kunmap(ring->mqd_obj); 6900 ring->mqd_ptr = NULL; 6901 } 6902 amdgpu_bo_unreserve(ring->mqd_obj); 6903 if (r) 6904 goto done; 6905 } 6906 6907 r = amdgpu_gfx_enable_kcq(adev); 6908 done: 6909 return r; 6910 } 6911 6912 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6913 { 6914 int r, i; 6915 struct amdgpu_ring *ring; 6916 6917 if (!(adev->flags & AMD_IS_APU)) 6918 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6919 6920 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6921 /* legacy firmware loading */ 6922 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6923 if (r) 6924 return r; 6925 6926 r = gfx_v10_0_cp_compute_load_microcode(adev); 6927 if (r) 6928 return r; 6929 } 6930 6931 r = gfx_v10_0_kiq_resume(adev); 6932 if (r) 6933 return r; 6934 6935 r = gfx_v10_0_kcq_resume(adev); 6936 if (r) 6937 return r; 6938 6939 if (!amdgpu_async_gfx_ring) { 6940 r = gfx_v10_0_cp_gfx_resume(adev); 6941 if (r) 6942 return r; 6943 } else { 6944 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6945 if (r) 6946 return r; 6947 } 6948 6949 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6950 ring = &adev->gfx.gfx_ring[i]; 6951 r = amdgpu_ring_test_helper(ring); 6952 if (r) 6953 return r; 6954 } 6955 6956 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6957 ring = &adev->gfx.compute_ring[i]; 6958 r = amdgpu_ring_test_helper(ring); 6959 if (r) 6960 return r; 6961 } 6962 6963 return 0; 6964 } 6965 6966 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6967 { 6968 gfx_v10_0_cp_gfx_enable(adev, enable); 6969 gfx_v10_0_cp_compute_enable(adev, enable); 6970 } 6971 6972 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6973 { 6974 uint32_t data, pattern = 0xDEADBEEF; 6975 6976 /* check if mmVGT_ESGS_RING_SIZE_UMD 6977 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6978 switch (adev->asic_type) { 6979 case CHIP_SIENNA_CICHLID: 6980 case CHIP_NAVY_FLOUNDER: 6981 case CHIP_DIMGREY_CAVEFISH: 6982 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6983 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6984 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6985 6986 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6987 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6988 return true; 6989 } else { 6990 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6991 return false; 6992 } 6993 break; 6994 case CHIP_VANGOGH: 6995 return true; 6996 default: 6997 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6998 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6999 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7000 7001 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7002 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7003 return true; 7004 } else { 7005 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7006 return false; 7007 } 7008 break; 7009 } 7010 } 7011 7012 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7013 { 7014 uint32_t data; 7015 7016 /* initialize cam_index to 0 7017 * index will auto-inc after each data writting */ 7018 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7019 7020 switch (adev->asic_type) { 7021 case CHIP_SIENNA_CICHLID: 7022 case CHIP_NAVY_FLOUNDER: 7023 case CHIP_VANGOGH: 7024 case CHIP_DIMGREY_CAVEFISH: 7025 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7026 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7027 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7028 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7029 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7030 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7031 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7032 7033 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7034 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7035 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7036 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7037 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7038 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7039 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7040 7041 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7042 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7043 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7044 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7045 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7047 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7048 7049 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7050 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7051 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7052 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7053 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7055 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7056 7057 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7058 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7059 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7060 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7061 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7063 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7064 7065 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7066 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7067 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7068 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7069 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7070 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7071 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7072 7073 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7074 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7075 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7076 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7077 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7078 break; 7079 default: 7080 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7081 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7082 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7083 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7084 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7085 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7087 7088 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7089 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7090 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7091 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7092 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7093 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7094 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7095 7096 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7097 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7098 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7099 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7100 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7101 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7102 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7103 7104 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7105 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7106 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7107 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7108 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7109 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7110 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7111 7112 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7113 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7114 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7115 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7116 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7117 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7118 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7119 7120 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7121 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7122 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7123 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7124 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7125 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7126 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7127 7128 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7129 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7130 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7131 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7132 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7133 break; 7134 } 7135 7136 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7137 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7138 } 7139 7140 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7141 { 7142 uint32_t data; 7143 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7144 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7145 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7146 7147 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7148 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7149 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7150 } 7151 7152 static int gfx_v10_0_hw_init(void *handle) 7153 { 7154 int r; 7155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7156 7157 if (!amdgpu_emu_mode) 7158 gfx_v10_0_init_golden_registers(adev); 7159 7160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7161 /** 7162 * For gfx 10, rlc firmware loading relies on smu firmware is 7163 * loaded firstly, so in direct type, it has to load smc ucode 7164 * here before rlc. 7165 */ 7166 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7167 r = smu_load_microcode(&adev->smu); 7168 if (r) 7169 return r; 7170 7171 r = smu_check_fw_status(&adev->smu); 7172 if (r) { 7173 pr_err("SMC firmware status is not correct\n"); 7174 return r; 7175 } 7176 } 7177 gfx_v10_0_disable_gpa_mode(adev); 7178 } 7179 7180 /* if GRBM CAM not remapped, set up the remapping */ 7181 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7182 gfx_v10_0_setup_grbm_cam_remapping(adev); 7183 7184 gfx_v10_0_constants_init(adev); 7185 7186 r = gfx_v10_0_rlc_resume(adev); 7187 if (r) 7188 return r; 7189 7190 /* 7191 * init golden registers and rlc resume may override some registers, 7192 * reconfig them here 7193 */ 7194 gfx_v10_0_tcp_harvest(adev); 7195 7196 r = gfx_v10_0_cp_resume(adev); 7197 if (r) 7198 return r; 7199 7200 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7201 gfx_v10_3_program_pbb_mode(adev); 7202 7203 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7204 gfx_v10_3_set_power_brake_sequence(adev); 7205 7206 return r; 7207 } 7208 7209 #ifndef BRING_UP_DEBUG 7210 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7211 { 7212 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7213 struct amdgpu_ring *kiq_ring = &kiq->ring; 7214 int i; 7215 7216 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7217 return -EINVAL; 7218 7219 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7220 adev->gfx.num_gfx_rings)) 7221 return -ENOMEM; 7222 7223 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7224 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7225 PREEMPT_QUEUES, 0, 0); 7226 7227 return amdgpu_ring_test_helper(kiq_ring); 7228 } 7229 #endif 7230 7231 static int gfx_v10_0_hw_fini(void *handle) 7232 { 7233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7234 int r; 7235 uint32_t tmp; 7236 7237 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7238 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7239 7240 if (!adev->in_pci_err_recovery) { 7241 #ifndef BRING_UP_DEBUG 7242 if (amdgpu_async_gfx_ring) { 7243 r = gfx_v10_0_kiq_disable_kgq(adev); 7244 if (r) 7245 DRM_ERROR("KGQ disable failed\n"); 7246 } 7247 #endif 7248 if (amdgpu_gfx_disable_kcq(adev)) 7249 DRM_ERROR("KCQ disable failed\n"); 7250 } 7251 7252 if (amdgpu_sriov_vf(adev)) { 7253 gfx_v10_0_cp_gfx_enable(adev, false); 7254 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7255 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7256 tmp &= 0xffffff00; 7257 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7258 7259 return 0; 7260 } 7261 gfx_v10_0_cp_enable(adev, false); 7262 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7263 7264 return 0; 7265 } 7266 7267 static int gfx_v10_0_suspend(void *handle) 7268 { 7269 return gfx_v10_0_hw_fini(handle); 7270 } 7271 7272 static int gfx_v10_0_resume(void *handle) 7273 { 7274 return gfx_v10_0_hw_init(handle); 7275 } 7276 7277 static bool gfx_v10_0_is_idle(void *handle) 7278 { 7279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7280 7281 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7282 GRBM_STATUS, GUI_ACTIVE)) 7283 return false; 7284 else 7285 return true; 7286 } 7287 7288 static int gfx_v10_0_wait_for_idle(void *handle) 7289 { 7290 unsigned i; 7291 u32 tmp; 7292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7293 7294 for (i = 0; i < adev->usec_timeout; i++) { 7295 /* read MC_STATUS */ 7296 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7297 GRBM_STATUS__GUI_ACTIVE_MASK; 7298 7299 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7300 return 0; 7301 udelay(1); 7302 } 7303 return -ETIMEDOUT; 7304 } 7305 7306 static int gfx_v10_0_soft_reset(void *handle) 7307 { 7308 u32 grbm_soft_reset = 0; 7309 u32 tmp; 7310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7311 7312 /* GRBM_STATUS */ 7313 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7314 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7315 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7316 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7317 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7318 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7319 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7320 GRBM_SOFT_RESET, SOFT_RESET_CP, 7321 1); 7322 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7323 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7324 1); 7325 } 7326 7327 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7328 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7329 GRBM_SOFT_RESET, SOFT_RESET_CP, 7330 1); 7331 } 7332 7333 /* GRBM_STATUS2 */ 7334 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7335 switch (adev->asic_type) { 7336 case CHIP_SIENNA_CICHLID: 7337 case CHIP_NAVY_FLOUNDER: 7338 case CHIP_VANGOGH: 7339 case CHIP_DIMGREY_CAVEFISH: 7340 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7341 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7342 GRBM_SOFT_RESET, 7343 SOFT_RESET_RLC, 7344 1); 7345 break; 7346 default: 7347 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7348 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7349 GRBM_SOFT_RESET, 7350 SOFT_RESET_RLC, 7351 1); 7352 break; 7353 } 7354 7355 if (grbm_soft_reset) { 7356 /* stop the rlc */ 7357 gfx_v10_0_rlc_stop(adev); 7358 7359 /* Disable GFX parsing/prefetching */ 7360 gfx_v10_0_cp_gfx_enable(adev, false); 7361 7362 /* Disable MEC parsing/prefetching */ 7363 gfx_v10_0_cp_compute_enable(adev, false); 7364 7365 if (grbm_soft_reset) { 7366 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7367 tmp |= grbm_soft_reset; 7368 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7369 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7370 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7371 7372 udelay(50); 7373 7374 tmp &= ~grbm_soft_reset; 7375 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7376 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7377 } 7378 7379 /* Wait a little for things to settle down */ 7380 udelay(50); 7381 } 7382 return 0; 7383 } 7384 7385 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7386 { 7387 uint64_t clock; 7388 7389 amdgpu_gfx_off_ctrl(adev, false); 7390 mutex_lock(&adev->gfx.gpu_clock_mutex); 7391 switch (adev->asic_type) { 7392 case CHIP_VANGOGH: 7393 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | 7394 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); 7395 break; 7396 default: 7397 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7398 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7399 break; 7400 } 7401 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7402 amdgpu_gfx_off_ctrl(adev, true); 7403 return clock; 7404 } 7405 7406 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7407 uint32_t vmid, 7408 uint32_t gds_base, uint32_t gds_size, 7409 uint32_t gws_base, uint32_t gws_size, 7410 uint32_t oa_base, uint32_t oa_size) 7411 { 7412 struct amdgpu_device *adev = ring->adev; 7413 7414 /* GDS Base */ 7415 gfx_v10_0_write_data_to_reg(ring, 0, false, 7416 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7417 gds_base); 7418 7419 /* GDS Size */ 7420 gfx_v10_0_write_data_to_reg(ring, 0, false, 7421 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7422 gds_size); 7423 7424 /* GWS */ 7425 gfx_v10_0_write_data_to_reg(ring, 0, false, 7426 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7427 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7428 7429 /* OA */ 7430 gfx_v10_0_write_data_to_reg(ring, 0, false, 7431 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7432 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7433 } 7434 7435 static int gfx_v10_0_early_init(void *handle) 7436 { 7437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7438 7439 switch (adev->asic_type) { 7440 case CHIP_NAVI10: 7441 case CHIP_NAVI14: 7442 case CHIP_NAVI12: 7443 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7444 break; 7445 case CHIP_SIENNA_CICHLID: 7446 case CHIP_NAVY_FLOUNDER: 7447 case CHIP_VANGOGH: 7448 case CHIP_DIMGREY_CAVEFISH: 7449 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7450 break; 7451 default: 7452 break; 7453 } 7454 7455 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7456 AMDGPU_MAX_COMPUTE_RINGS); 7457 7458 gfx_v10_0_set_kiq_pm4_funcs(adev); 7459 gfx_v10_0_set_ring_funcs(adev); 7460 gfx_v10_0_set_irq_funcs(adev); 7461 gfx_v10_0_set_gds_init(adev); 7462 gfx_v10_0_set_rlc_funcs(adev); 7463 7464 return 0; 7465 } 7466 7467 static int gfx_v10_0_late_init(void *handle) 7468 { 7469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7470 int r; 7471 7472 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7473 if (r) 7474 return r; 7475 7476 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7477 if (r) 7478 return r; 7479 7480 return 0; 7481 } 7482 7483 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7484 { 7485 uint32_t rlc_cntl; 7486 7487 /* if RLC is not enabled, do nothing */ 7488 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7489 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7490 } 7491 7492 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7493 { 7494 uint32_t data; 7495 unsigned i; 7496 7497 data = RLC_SAFE_MODE__CMD_MASK; 7498 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7499 7500 switch (adev->asic_type) { 7501 case CHIP_SIENNA_CICHLID: 7502 case CHIP_NAVY_FLOUNDER: 7503 case CHIP_VANGOGH: 7504 case CHIP_DIMGREY_CAVEFISH: 7505 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7506 7507 /* wait for RLC_SAFE_MODE */ 7508 for (i = 0; i < adev->usec_timeout; i++) { 7509 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7510 RLC_SAFE_MODE, CMD)) 7511 break; 7512 udelay(1); 7513 } 7514 break; 7515 default: 7516 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7517 7518 /* wait for RLC_SAFE_MODE */ 7519 for (i = 0; i < adev->usec_timeout; i++) { 7520 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7521 RLC_SAFE_MODE, CMD)) 7522 break; 7523 udelay(1); 7524 } 7525 break; 7526 } 7527 } 7528 7529 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7530 { 7531 uint32_t data; 7532 7533 data = RLC_SAFE_MODE__CMD_MASK; 7534 switch (adev->asic_type) { 7535 case CHIP_SIENNA_CICHLID: 7536 case CHIP_NAVY_FLOUNDER: 7537 case CHIP_VANGOGH: 7538 case CHIP_DIMGREY_CAVEFISH: 7539 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7540 break; 7541 default: 7542 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7543 break; 7544 } 7545 } 7546 7547 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7548 bool enable) 7549 { 7550 uint32_t data, def; 7551 7552 /* It is disabled by HW by default */ 7553 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7554 /* 0 - Disable some blocks' MGCG */ 7555 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7556 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7557 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7558 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7559 7560 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7561 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7562 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7563 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7564 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7565 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7566 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7567 7568 if (def != data) 7569 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7570 7571 /* MGLS is a global flag to control all MGLS in GFX */ 7572 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7573 /* 2 - RLC memory Light sleep */ 7574 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7575 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7576 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7577 if (def != data) 7578 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7579 } 7580 /* 3 - CP memory Light sleep */ 7581 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7582 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7583 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7584 if (def != data) 7585 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7586 } 7587 } 7588 } else { 7589 /* 1 - MGCG_OVERRIDE */ 7590 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7591 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7592 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7593 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7594 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7595 if (def != data) 7596 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7597 7598 /* 2 - disable MGLS in CP */ 7599 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7600 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7601 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7602 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7603 } 7604 7605 /* 3 - disable MGLS in RLC */ 7606 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7607 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7608 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7609 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7610 } 7611 7612 } 7613 } 7614 7615 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7616 bool enable) 7617 { 7618 uint32_t data, def; 7619 7620 /* Enable 3D CGCG/CGLS */ 7621 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7622 /* write cmd to clear cgcg/cgls ov */ 7623 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7624 /* unset CGCG override */ 7625 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7626 /* update CGCG and CGLS override bits */ 7627 if (def != data) 7628 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7629 /* enable 3Dcgcg FSM(0x0000363f) */ 7630 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7631 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7632 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7634 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7635 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7636 if (def != data) 7637 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7638 7639 /* set IDLE_POLL_COUNT(0x00900100) */ 7640 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7641 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7642 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7643 if (def != data) 7644 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7645 } else { 7646 /* Disable CGCG/CGLS */ 7647 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7648 /* disable cgcg, cgls should be disabled */ 7649 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7650 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7651 /* disable cgcg and cgls in FSM */ 7652 if (def != data) 7653 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7654 } 7655 } 7656 7657 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7658 bool enable) 7659 { 7660 uint32_t def, data; 7661 7662 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7663 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7664 /* unset CGCG override */ 7665 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7666 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7667 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7668 else 7669 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7670 /* update CGCG and CGLS override bits */ 7671 if (def != data) 7672 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7673 7674 /* enable cgcg FSM(0x0000363F) */ 7675 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7676 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7677 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7678 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7679 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7680 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7681 if (def != data) 7682 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7683 7684 /* set IDLE_POLL_COUNT(0x00900100) */ 7685 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7686 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7687 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7688 if (def != data) 7689 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7690 } else { 7691 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7692 /* reset CGCG/CGLS bits */ 7693 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7694 /* disable cgcg and cgls in FSM */ 7695 if (def != data) 7696 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7697 } 7698 } 7699 7700 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7701 bool enable) 7702 { 7703 uint32_t def, data; 7704 7705 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7706 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7707 /* unset FGCG override */ 7708 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7709 /* update FGCG override bits */ 7710 if (def != data) 7711 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7712 7713 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7714 /* unset RLC SRAM CLK GATER override */ 7715 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7716 /* update RLC SRAM CLK GATER override bits */ 7717 if (def != data) 7718 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7719 } else { 7720 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7721 /* reset FGCG bits */ 7722 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7723 /* disable FGCG*/ 7724 if (def != data) 7725 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7726 7727 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7728 /* reset RLC SRAM CLK GATER bits */ 7729 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7730 /* disable RLC SRAM CLK*/ 7731 if (def != data) 7732 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7733 } 7734 } 7735 7736 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7737 bool enable) 7738 { 7739 amdgpu_gfx_rlc_enter_safe_mode(adev); 7740 7741 if (enable) { 7742 /* enable FGCG firstly*/ 7743 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7744 /* CGCG/CGLS should be enabled after MGCG/MGLS 7745 * === MGCG + MGLS === 7746 */ 7747 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7748 /* === CGCG /CGLS for GFX 3D Only === */ 7749 gfx_v10_0_update_3d_clock_gating(adev, enable); 7750 /* === CGCG + CGLS === */ 7751 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7752 } else { 7753 /* CGCG/CGLS should be disabled before MGCG/MGLS 7754 * === CGCG + CGLS === 7755 */ 7756 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7757 /* === CGCG /CGLS for GFX 3D Only === */ 7758 gfx_v10_0_update_3d_clock_gating(adev, enable); 7759 /* === MGCG + MGLS === */ 7760 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7761 /* disable fgcg at last*/ 7762 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7763 } 7764 7765 if (adev->cg_flags & 7766 (AMD_CG_SUPPORT_GFX_MGCG | 7767 AMD_CG_SUPPORT_GFX_CGLS | 7768 AMD_CG_SUPPORT_GFX_CGCG | 7769 AMD_CG_SUPPORT_GFX_3D_CGCG | 7770 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7771 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7772 7773 amdgpu_gfx_rlc_exit_safe_mode(adev); 7774 7775 return 0; 7776 } 7777 7778 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7779 { 7780 u32 reg, data; 7781 7782 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7783 if (amdgpu_sriov_is_pp_one_vf(adev)) 7784 data = RREG32_NO_KIQ(reg); 7785 else 7786 data = RREG32(reg); 7787 7788 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7789 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7790 7791 if (amdgpu_sriov_is_pp_one_vf(adev)) 7792 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7793 else 7794 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7795 } 7796 7797 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7798 uint32_t offset, 7799 struct soc15_reg_rlcg *entries, int arr_size) 7800 { 7801 int i; 7802 uint32_t reg; 7803 7804 if (!entries) 7805 return false; 7806 7807 for (i = 0; i < arr_size; i++) { 7808 const struct soc15_reg_rlcg *entry; 7809 7810 entry = &entries[i]; 7811 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7812 if (offset == reg) 7813 return true; 7814 } 7815 7816 return false; 7817 } 7818 7819 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7820 { 7821 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7822 } 7823 7824 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7825 { 7826 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7827 7828 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7829 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7830 else 7831 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7832 7833 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7834 } 7835 7836 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7837 { 7838 amdgpu_gfx_rlc_enter_safe_mode(adev); 7839 7840 gfx_v10_cntl_power_gating(adev, enable); 7841 7842 amdgpu_gfx_rlc_exit_safe_mode(adev); 7843 } 7844 7845 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7846 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7847 .set_safe_mode = gfx_v10_0_set_safe_mode, 7848 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7849 .init = gfx_v10_0_rlc_init, 7850 .get_csb_size = gfx_v10_0_get_csb_size, 7851 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7852 .resume = gfx_v10_0_rlc_resume, 7853 .stop = gfx_v10_0_rlc_stop, 7854 .reset = gfx_v10_0_rlc_reset, 7855 .start = gfx_v10_0_rlc_start, 7856 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7857 }; 7858 7859 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7860 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7861 .set_safe_mode = gfx_v10_0_set_safe_mode, 7862 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7863 .init = gfx_v10_0_rlc_init, 7864 .get_csb_size = gfx_v10_0_get_csb_size, 7865 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7866 .resume = gfx_v10_0_rlc_resume, 7867 .stop = gfx_v10_0_rlc_stop, 7868 .reset = gfx_v10_0_rlc_reset, 7869 .start = gfx_v10_0_rlc_start, 7870 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7871 .rlcg_wreg = gfx_v10_rlcg_wreg, 7872 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7873 }; 7874 7875 static int gfx_v10_0_set_powergating_state(void *handle, 7876 enum amd_powergating_state state) 7877 { 7878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7879 bool enable = (state == AMD_PG_STATE_GATE); 7880 7881 if (amdgpu_sriov_vf(adev)) 7882 return 0; 7883 7884 switch (adev->asic_type) { 7885 case CHIP_NAVI10: 7886 case CHIP_NAVI14: 7887 case CHIP_NAVI12: 7888 case CHIP_SIENNA_CICHLID: 7889 case CHIP_NAVY_FLOUNDER: 7890 case CHIP_DIMGREY_CAVEFISH: 7891 amdgpu_gfx_off_ctrl(adev, enable); 7892 break; 7893 case CHIP_VANGOGH: 7894 gfx_v10_cntl_pg(adev, enable); 7895 break; 7896 default: 7897 break; 7898 } 7899 return 0; 7900 } 7901 7902 static int gfx_v10_0_set_clockgating_state(void *handle, 7903 enum amd_clockgating_state state) 7904 { 7905 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7906 7907 if (amdgpu_sriov_vf(adev)) 7908 return 0; 7909 7910 switch (adev->asic_type) { 7911 case CHIP_NAVI10: 7912 case CHIP_NAVI14: 7913 case CHIP_NAVI12: 7914 case CHIP_SIENNA_CICHLID: 7915 case CHIP_NAVY_FLOUNDER: 7916 case CHIP_VANGOGH: 7917 case CHIP_DIMGREY_CAVEFISH: 7918 gfx_v10_0_update_gfx_clock_gating(adev, 7919 state == AMD_CG_STATE_GATE); 7920 break; 7921 default: 7922 break; 7923 } 7924 return 0; 7925 } 7926 7927 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7928 { 7929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7930 int data; 7931 7932 /* AMD_CG_SUPPORT_GFX_FGCG */ 7933 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7934 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7935 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7936 7937 /* AMD_CG_SUPPORT_GFX_MGCG */ 7938 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7939 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7940 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7941 7942 /* AMD_CG_SUPPORT_GFX_CGCG */ 7943 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7944 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7945 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7946 7947 /* AMD_CG_SUPPORT_GFX_CGLS */ 7948 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7949 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7950 7951 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7952 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7953 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7954 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7955 7956 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7957 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7958 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7959 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7960 7961 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7962 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7963 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7964 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7965 7966 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7967 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7968 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7969 } 7970 7971 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7972 { 7973 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7974 } 7975 7976 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7977 { 7978 struct amdgpu_device *adev = ring->adev; 7979 u64 wptr; 7980 7981 /* XXX check if swapping is necessary on BE */ 7982 if (ring->use_doorbell) { 7983 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7984 } else { 7985 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7986 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7987 } 7988 7989 return wptr; 7990 } 7991 7992 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7993 { 7994 struct amdgpu_device *adev = ring->adev; 7995 7996 if (ring->use_doorbell) { 7997 /* XXX check if swapping is necessary on BE */ 7998 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7999 WDOORBELL64(ring->doorbell_index, ring->wptr); 8000 } else { 8001 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8002 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8003 } 8004 } 8005 8006 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8007 { 8008 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8009 } 8010 8011 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8012 { 8013 u64 wptr; 8014 8015 /* XXX check if swapping is necessary on BE */ 8016 if (ring->use_doorbell) 8017 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8018 else 8019 BUG(); 8020 return wptr; 8021 } 8022 8023 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8024 { 8025 struct amdgpu_device *adev = ring->adev; 8026 8027 /* XXX check if swapping is necessary on BE */ 8028 if (ring->use_doorbell) { 8029 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8030 WDOORBELL64(ring->doorbell_index, ring->wptr); 8031 } else { 8032 BUG(); /* only DOORBELL method supported on gfx10 now */ 8033 } 8034 } 8035 8036 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8037 { 8038 struct amdgpu_device *adev = ring->adev; 8039 u32 ref_and_mask, reg_mem_engine; 8040 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8041 8042 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8043 switch (ring->me) { 8044 case 1: 8045 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8046 break; 8047 case 2: 8048 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8049 break; 8050 default: 8051 return; 8052 } 8053 reg_mem_engine = 0; 8054 } else { 8055 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8056 reg_mem_engine = 1; /* pfp */ 8057 } 8058 8059 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8060 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8061 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8062 ref_and_mask, ref_and_mask, 0x20); 8063 } 8064 8065 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8066 struct amdgpu_job *job, 8067 struct amdgpu_ib *ib, 8068 uint32_t flags) 8069 { 8070 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8071 u32 header, control = 0; 8072 8073 if (ib->flags & AMDGPU_IB_FLAG_CE) 8074 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8075 else 8076 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8077 8078 control |= ib->length_dw | (vmid << 24); 8079 8080 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8081 control |= INDIRECT_BUFFER_PRE_ENB(1); 8082 8083 if (flags & AMDGPU_IB_PREEMPTED) 8084 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8085 8086 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8087 gfx_v10_0_ring_emit_de_meta(ring, 8088 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8089 } 8090 8091 amdgpu_ring_write(ring, header); 8092 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8093 amdgpu_ring_write(ring, 8094 #ifdef __BIG_ENDIAN 8095 (2 << 0) | 8096 #endif 8097 lower_32_bits(ib->gpu_addr)); 8098 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8099 amdgpu_ring_write(ring, control); 8100 } 8101 8102 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8103 struct amdgpu_job *job, 8104 struct amdgpu_ib *ib, 8105 uint32_t flags) 8106 { 8107 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8108 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8109 8110 /* Currently, there is a high possibility to get wave ID mismatch 8111 * between ME and GDS, leading to a hw deadlock, because ME generates 8112 * different wave IDs than the GDS expects. This situation happens 8113 * randomly when at least 5 compute pipes use GDS ordered append. 8114 * The wave IDs generated by ME are also wrong after suspend/resume. 8115 * Those are probably bugs somewhere else in the kernel driver. 8116 * 8117 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8118 * GDS to 0 for this ring (me/pipe). 8119 */ 8120 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8121 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8122 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8123 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8124 } 8125 8126 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8127 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8128 amdgpu_ring_write(ring, 8129 #ifdef __BIG_ENDIAN 8130 (2 << 0) | 8131 #endif 8132 lower_32_bits(ib->gpu_addr)); 8133 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8134 amdgpu_ring_write(ring, control); 8135 } 8136 8137 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8138 u64 seq, unsigned flags) 8139 { 8140 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8141 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8142 8143 /* RELEASE_MEM - flush caches, send int */ 8144 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8145 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8146 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8147 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8148 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8149 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8150 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8151 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8152 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8153 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8154 8155 /* 8156 * the address should be Qword aligned if 64bit write, Dword 8157 * aligned if only send 32bit data low (discard data high) 8158 */ 8159 if (write64bit) 8160 BUG_ON(addr & 0x7); 8161 else 8162 BUG_ON(addr & 0x3); 8163 amdgpu_ring_write(ring, lower_32_bits(addr)); 8164 amdgpu_ring_write(ring, upper_32_bits(addr)); 8165 amdgpu_ring_write(ring, lower_32_bits(seq)); 8166 amdgpu_ring_write(ring, upper_32_bits(seq)); 8167 amdgpu_ring_write(ring, 0); 8168 } 8169 8170 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8171 { 8172 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8173 uint32_t seq = ring->fence_drv.sync_seq; 8174 uint64_t addr = ring->fence_drv.gpu_addr; 8175 8176 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8177 upper_32_bits(addr), seq, 0xffffffff, 4); 8178 } 8179 8180 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8181 unsigned vmid, uint64_t pd_addr) 8182 { 8183 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8184 8185 /* compute doesn't have PFP */ 8186 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8187 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8188 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8189 amdgpu_ring_write(ring, 0x0); 8190 } 8191 } 8192 8193 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8194 u64 seq, unsigned int flags) 8195 { 8196 struct amdgpu_device *adev = ring->adev; 8197 8198 /* we only allocate 32bit for each seq wb address */ 8199 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8200 8201 /* write fence seq to the "addr" */ 8202 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8203 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8204 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8205 amdgpu_ring_write(ring, lower_32_bits(addr)); 8206 amdgpu_ring_write(ring, upper_32_bits(addr)); 8207 amdgpu_ring_write(ring, lower_32_bits(seq)); 8208 8209 if (flags & AMDGPU_FENCE_FLAG_INT) { 8210 /* set register to trigger INT */ 8211 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8212 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8213 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8214 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8215 amdgpu_ring_write(ring, 0); 8216 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8217 } 8218 } 8219 8220 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8221 { 8222 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8223 amdgpu_ring_write(ring, 0); 8224 } 8225 8226 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8227 uint32_t flags) 8228 { 8229 uint32_t dw2 = 0; 8230 8231 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8232 gfx_v10_0_ring_emit_ce_meta(ring, 8233 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8234 8235 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8236 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8237 /* set load_global_config & load_global_uconfig */ 8238 dw2 |= 0x8001; 8239 /* set load_cs_sh_regs */ 8240 dw2 |= 0x01000000; 8241 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8242 dw2 |= 0x10002; 8243 8244 /* set load_ce_ram if preamble presented */ 8245 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8246 dw2 |= 0x10000000; 8247 } else { 8248 /* still load_ce_ram if this is the first time preamble presented 8249 * although there is no context switch happens. 8250 */ 8251 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8252 dw2 |= 0x10000000; 8253 } 8254 8255 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8256 amdgpu_ring_write(ring, dw2); 8257 amdgpu_ring_write(ring, 0); 8258 } 8259 8260 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8261 { 8262 unsigned ret; 8263 8264 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8265 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8266 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8267 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8268 ret = ring->wptr & ring->buf_mask; 8269 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8270 8271 return ret; 8272 } 8273 8274 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8275 { 8276 unsigned cur; 8277 BUG_ON(offset > ring->buf_mask); 8278 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8279 8280 cur = (ring->wptr - 1) & ring->buf_mask; 8281 if (likely(cur > offset)) 8282 ring->ring[offset] = cur - offset; 8283 else 8284 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8285 } 8286 8287 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8288 { 8289 int i, r = 0; 8290 struct amdgpu_device *adev = ring->adev; 8291 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8292 struct amdgpu_ring *kiq_ring = &kiq->ring; 8293 unsigned long flags; 8294 8295 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8296 return -EINVAL; 8297 8298 spin_lock_irqsave(&kiq->ring_lock, flags); 8299 8300 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8301 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8302 return -ENOMEM; 8303 } 8304 8305 /* assert preemption condition */ 8306 amdgpu_ring_set_preempt_cond_exec(ring, false); 8307 8308 /* assert IB preemption, emit the trailing fence */ 8309 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8310 ring->trail_fence_gpu_addr, 8311 ++ring->trail_seq); 8312 amdgpu_ring_commit(kiq_ring); 8313 8314 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8315 8316 /* poll the trailing fence */ 8317 for (i = 0; i < adev->usec_timeout; i++) { 8318 if (ring->trail_seq == 8319 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8320 break; 8321 udelay(1); 8322 } 8323 8324 if (i >= adev->usec_timeout) { 8325 r = -EINVAL; 8326 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8327 } 8328 8329 /* deassert preemption condition */ 8330 amdgpu_ring_set_preempt_cond_exec(ring, true); 8331 return r; 8332 } 8333 8334 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8335 { 8336 struct amdgpu_device *adev = ring->adev; 8337 struct v10_ce_ib_state ce_payload = {0}; 8338 uint64_t csa_addr; 8339 int cnt; 8340 8341 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8342 csa_addr = amdgpu_csa_vaddr(ring->adev); 8343 8344 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8345 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8346 WRITE_DATA_DST_SEL(8) | 8347 WR_CONFIRM) | 8348 WRITE_DATA_CACHE_POLICY(0)); 8349 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8350 offsetof(struct v10_gfx_meta_data, ce_payload))); 8351 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8352 offsetof(struct v10_gfx_meta_data, ce_payload))); 8353 8354 if (resume) 8355 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8356 offsetof(struct v10_gfx_meta_data, 8357 ce_payload), 8358 sizeof(ce_payload) >> 2); 8359 else 8360 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8361 sizeof(ce_payload) >> 2); 8362 } 8363 8364 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8365 { 8366 struct amdgpu_device *adev = ring->adev; 8367 struct v10_de_ib_state de_payload = {0}; 8368 uint64_t csa_addr, gds_addr; 8369 int cnt; 8370 8371 csa_addr = amdgpu_csa_vaddr(ring->adev); 8372 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8373 PAGE_SIZE); 8374 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8375 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8376 8377 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8378 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8379 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8380 WRITE_DATA_DST_SEL(8) | 8381 WR_CONFIRM) | 8382 WRITE_DATA_CACHE_POLICY(0)); 8383 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8384 offsetof(struct v10_gfx_meta_data, de_payload))); 8385 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8386 offsetof(struct v10_gfx_meta_data, de_payload))); 8387 8388 if (resume) 8389 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8390 offsetof(struct v10_gfx_meta_data, 8391 de_payload), 8392 sizeof(de_payload) >> 2); 8393 else 8394 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8395 sizeof(de_payload) >> 2); 8396 } 8397 8398 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8399 bool secure) 8400 { 8401 uint32_t v = secure ? FRAME_TMZ : 0; 8402 8403 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8404 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8405 } 8406 8407 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8408 uint32_t reg_val_offs) 8409 { 8410 struct amdgpu_device *adev = ring->adev; 8411 8412 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8413 amdgpu_ring_write(ring, 0 | /* src: register*/ 8414 (5 << 8) | /* dst: memory */ 8415 (1 << 20)); /* write confirm */ 8416 amdgpu_ring_write(ring, reg); 8417 amdgpu_ring_write(ring, 0); 8418 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8419 reg_val_offs * 4)); 8420 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8421 reg_val_offs * 4)); 8422 } 8423 8424 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8425 uint32_t val) 8426 { 8427 uint32_t cmd = 0; 8428 8429 switch (ring->funcs->type) { 8430 case AMDGPU_RING_TYPE_GFX: 8431 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8432 break; 8433 case AMDGPU_RING_TYPE_KIQ: 8434 cmd = (1 << 16); /* no inc addr */ 8435 break; 8436 default: 8437 cmd = WR_CONFIRM; 8438 break; 8439 } 8440 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8441 amdgpu_ring_write(ring, cmd); 8442 amdgpu_ring_write(ring, reg); 8443 amdgpu_ring_write(ring, 0); 8444 amdgpu_ring_write(ring, val); 8445 } 8446 8447 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8448 uint32_t val, uint32_t mask) 8449 { 8450 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8451 } 8452 8453 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8454 uint32_t reg0, uint32_t reg1, 8455 uint32_t ref, uint32_t mask) 8456 { 8457 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8458 struct amdgpu_device *adev = ring->adev; 8459 bool fw_version_ok = false; 8460 8461 fw_version_ok = adev->gfx.cp_fw_write_wait; 8462 8463 if (fw_version_ok) 8464 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8465 ref, mask, 0x20); 8466 else 8467 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8468 ref, mask); 8469 } 8470 8471 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8472 unsigned vmid) 8473 { 8474 struct amdgpu_device *adev = ring->adev; 8475 uint32_t value = 0; 8476 8477 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8478 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8479 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8480 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8481 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8482 } 8483 8484 static void 8485 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8486 uint32_t me, uint32_t pipe, 8487 enum amdgpu_interrupt_state state) 8488 { 8489 uint32_t cp_int_cntl, cp_int_cntl_reg; 8490 8491 if (!me) { 8492 switch (pipe) { 8493 case 0: 8494 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8495 break; 8496 case 1: 8497 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8498 break; 8499 default: 8500 DRM_DEBUG("invalid pipe %d\n", pipe); 8501 return; 8502 } 8503 } else { 8504 DRM_DEBUG("invalid me %d\n", me); 8505 return; 8506 } 8507 8508 switch (state) { 8509 case AMDGPU_IRQ_STATE_DISABLE: 8510 cp_int_cntl = RREG32(cp_int_cntl_reg); 8511 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8512 TIME_STAMP_INT_ENABLE, 0); 8513 WREG32(cp_int_cntl_reg, cp_int_cntl); 8514 break; 8515 case AMDGPU_IRQ_STATE_ENABLE: 8516 cp_int_cntl = RREG32(cp_int_cntl_reg); 8517 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8518 TIME_STAMP_INT_ENABLE, 1); 8519 WREG32(cp_int_cntl_reg, cp_int_cntl); 8520 break; 8521 default: 8522 break; 8523 } 8524 } 8525 8526 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8527 int me, int pipe, 8528 enum amdgpu_interrupt_state state) 8529 { 8530 u32 mec_int_cntl, mec_int_cntl_reg; 8531 8532 /* 8533 * amdgpu controls only the first MEC. That's why this function only 8534 * handles the setting of interrupts for this specific MEC. All other 8535 * pipes' interrupts are set by amdkfd. 8536 */ 8537 8538 if (me == 1) { 8539 switch (pipe) { 8540 case 0: 8541 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8542 break; 8543 case 1: 8544 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8545 break; 8546 case 2: 8547 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8548 break; 8549 case 3: 8550 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8551 break; 8552 default: 8553 DRM_DEBUG("invalid pipe %d\n", pipe); 8554 return; 8555 } 8556 } else { 8557 DRM_DEBUG("invalid me %d\n", me); 8558 return; 8559 } 8560 8561 switch (state) { 8562 case AMDGPU_IRQ_STATE_DISABLE: 8563 mec_int_cntl = RREG32(mec_int_cntl_reg); 8564 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8565 TIME_STAMP_INT_ENABLE, 0); 8566 WREG32(mec_int_cntl_reg, mec_int_cntl); 8567 break; 8568 case AMDGPU_IRQ_STATE_ENABLE: 8569 mec_int_cntl = RREG32(mec_int_cntl_reg); 8570 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8571 TIME_STAMP_INT_ENABLE, 1); 8572 WREG32(mec_int_cntl_reg, mec_int_cntl); 8573 break; 8574 default: 8575 break; 8576 } 8577 } 8578 8579 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8580 struct amdgpu_irq_src *src, 8581 unsigned type, 8582 enum amdgpu_interrupt_state state) 8583 { 8584 switch (type) { 8585 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8586 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8587 break; 8588 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8589 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8590 break; 8591 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8592 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8593 break; 8594 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8595 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8596 break; 8597 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8598 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8599 break; 8600 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8601 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8602 break; 8603 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8604 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8605 break; 8606 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8607 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8608 break; 8609 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8610 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8611 break; 8612 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8613 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8614 break; 8615 default: 8616 break; 8617 } 8618 return 0; 8619 } 8620 8621 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8622 struct amdgpu_irq_src *source, 8623 struct amdgpu_iv_entry *entry) 8624 { 8625 int i; 8626 u8 me_id, pipe_id, queue_id; 8627 struct amdgpu_ring *ring; 8628 8629 DRM_DEBUG("IH: CP EOP\n"); 8630 me_id = (entry->ring_id & 0x0c) >> 2; 8631 pipe_id = (entry->ring_id & 0x03) >> 0; 8632 queue_id = (entry->ring_id & 0x70) >> 4; 8633 8634 switch (me_id) { 8635 case 0: 8636 if (pipe_id == 0) 8637 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8638 else 8639 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8640 break; 8641 case 1: 8642 case 2: 8643 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8644 ring = &adev->gfx.compute_ring[i]; 8645 /* Per-queue interrupt is supported for MEC starting from VI. 8646 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8647 */ 8648 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8649 amdgpu_fence_process(ring); 8650 } 8651 break; 8652 } 8653 return 0; 8654 } 8655 8656 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8657 struct amdgpu_irq_src *source, 8658 unsigned type, 8659 enum amdgpu_interrupt_state state) 8660 { 8661 switch (state) { 8662 case AMDGPU_IRQ_STATE_DISABLE: 8663 case AMDGPU_IRQ_STATE_ENABLE: 8664 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8665 PRIV_REG_INT_ENABLE, 8666 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8667 break; 8668 default: 8669 break; 8670 } 8671 8672 return 0; 8673 } 8674 8675 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8676 struct amdgpu_irq_src *source, 8677 unsigned type, 8678 enum amdgpu_interrupt_state state) 8679 { 8680 switch (state) { 8681 case AMDGPU_IRQ_STATE_DISABLE: 8682 case AMDGPU_IRQ_STATE_ENABLE: 8683 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8684 PRIV_INSTR_INT_ENABLE, 8685 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8686 break; 8687 default: 8688 break; 8689 } 8690 8691 return 0; 8692 } 8693 8694 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8695 struct amdgpu_iv_entry *entry) 8696 { 8697 u8 me_id, pipe_id, queue_id; 8698 struct amdgpu_ring *ring; 8699 int i; 8700 8701 me_id = (entry->ring_id & 0x0c) >> 2; 8702 pipe_id = (entry->ring_id & 0x03) >> 0; 8703 queue_id = (entry->ring_id & 0x70) >> 4; 8704 8705 switch (me_id) { 8706 case 0: 8707 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8708 ring = &adev->gfx.gfx_ring[i]; 8709 /* we only enabled 1 gfx queue per pipe for now */ 8710 if (ring->me == me_id && ring->pipe == pipe_id) 8711 drm_sched_fault(&ring->sched); 8712 } 8713 break; 8714 case 1: 8715 case 2: 8716 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8717 ring = &adev->gfx.compute_ring[i]; 8718 if (ring->me == me_id && ring->pipe == pipe_id && 8719 ring->queue == queue_id) 8720 drm_sched_fault(&ring->sched); 8721 } 8722 break; 8723 default: 8724 BUG(); 8725 } 8726 } 8727 8728 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8729 struct amdgpu_irq_src *source, 8730 struct amdgpu_iv_entry *entry) 8731 { 8732 DRM_ERROR("Illegal register access in command stream\n"); 8733 gfx_v10_0_handle_priv_fault(adev, entry); 8734 return 0; 8735 } 8736 8737 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8738 struct amdgpu_irq_src *source, 8739 struct amdgpu_iv_entry *entry) 8740 { 8741 DRM_ERROR("Illegal instruction in command stream\n"); 8742 gfx_v10_0_handle_priv_fault(adev, entry); 8743 return 0; 8744 } 8745 8746 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8747 struct amdgpu_irq_src *src, 8748 unsigned int type, 8749 enum amdgpu_interrupt_state state) 8750 { 8751 uint32_t tmp, target; 8752 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8753 8754 if (ring->me == 1) 8755 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8756 else 8757 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8758 target += ring->pipe; 8759 8760 switch (type) { 8761 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8762 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8763 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8764 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8765 GENERIC2_INT_ENABLE, 0); 8766 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8767 8768 tmp = RREG32(target); 8769 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8770 GENERIC2_INT_ENABLE, 0); 8771 WREG32(target, tmp); 8772 } else { 8773 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8774 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8775 GENERIC2_INT_ENABLE, 1); 8776 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8777 8778 tmp = RREG32(target); 8779 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8780 GENERIC2_INT_ENABLE, 1); 8781 WREG32(target, tmp); 8782 } 8783 break; 8784 default: 8785 BUG(); /* kiq only support GENERIC2_INT now */ 8786 break; 8787 } 8788 return 0; 8789 } 8790 8791 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8792 struct amdgpu_irq_src *source, 8793 struct amdgpu_iv_entry *entry) 8794 { 8795 u8 me_id, pipe_id, queue_id; 8796 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8797 8798 me_id = (entry->ring_id & 0x0c) >> 2; 8799 pipe_id = (entry->ring_id & 0x03) >> 0; 8800 queue_id = (entry->ring_id & 0x70) >> 4; 8801 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8802 me_id, pipe_id, queue_id); 8803 8804 amdgpu_fence_process(ring); 8805 return 0; 8806 } 8807 8808 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8809 { 8810 const unsigned int gcr_cntl = 8811 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8812 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8813 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8814 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8815 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8816 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8817 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8818 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8819 8820 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8821 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8822 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8823 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8824 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8825 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8826 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8827 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8828 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8829 } 8830 8831 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8832 .name = "gfx_v10_0", 8833 .early_init = gfx_v10_0_early_init, 8834 .late_init = gfx_v10_0_late_init, 8835 .sw_init = gfx_v10_0_sw_init, 8836 .sw_fini = gfx_v10_0_sw_fini, 8837 .hw_init = gfx_v10_0_hw_init, 8838 .hw_fini = gfx_v10_0_hw_fini, 8839 .suspend = gfx_v10_0_suspend, 8840 .resume = gfx_v10_0_resume, 8841 .is_idle = gfx_v10_0_is_idle, 8842 .wait_for_idle = gfx_v10_0_wait_for_idle, 8843 .soft_reset = gfx_v10_0_soft_reset, 8844 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8845 .set_powergating_state = gfx_v10_0_set_powergating_state, 8846 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8847 }; 8848 8849 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8850 .type = AMDGPU_RING_TYPE_GFX, 8851 .align_mask = 0xff, 8852 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8853 .support_64bit_ptrs = true, 8854 .vmhub = AMDGPU_GFXHUB_0, 8855 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8856 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8857 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8858 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8859 5 + /* COND_EXEC */ 8860 7 + /* PIPELINE_SYNC */ 8861 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8862 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8863 2 + /* VM_FLUSH */ 8864 8 + /* FENCE for VM_FLUSH */ 8865 20 + /* GDS switch */ 8866 4 + /* double SWITCH_BUFFER, 8867 * the first COND_EXEC jump to the place 8868 * just prior to this double SWITCH_BUFFER 8869 */ 8870 5 + /* COND_EXEC */ 8871 7 + /* HDP_flush */ 8872 4 + /* VGT_flush */ 8873 14 + /* CE_META */ 8874 31 + /* DE_META */ 8875 3 + /* CNTX_CTRL */ 8876 5 + /* HDP_INVL */ 8877 8 + 8 + /* FENCE x2 */ 8878 2 + /* SWITCH_BUFFER */ 8879 8, /* gfx_v10_0_emit_mem_sync */ 8880 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8881 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8882 .emit_fence = gfx_v10_0_ring_emit_fence, 8883 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8884 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8885 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8886 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8887 .test_ring = gfx_v10_0_ring_test_ring, 8888 .test_ib = gfx_v10_0_ring_test_ib, 8889 .insert_nop = amdgpu_ring_insert_nop, 8890 .pad_ib = amdgpu_ring_generic_pad_ib, 8891 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8892 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8893 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8894 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8895 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8896 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8897 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8898 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8899 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8900 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8901 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8902 }; 8903 8904 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8905 .type = AMDGPU_RING_TYPE_COMPUTE, 8906 .align_mask = 0xff, 8907 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8908 .support_64bit_ptrs = true, 8909 .vmhub = AMDGPU_GFXHUB_0, 8910 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8911 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8912 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8913 .emit_frame_size = 8914 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8915 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8916 5 + /* hdp invalidate */ 8917 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8918 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8919 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8920 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8921 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8922 8, /* gfx_v10_0_emit_mem_sync */ 8923 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8924 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8925 .emit_fence = gfx_v10_0_ring_emit_fence, 8926 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8927 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8928 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8929 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8930 .test_ring = gfx_v10_0_ring_test_ring, 8931 .test_ib = gfx_v10_0_ring_test_ib, 8932 .insert_nop = amdgpu_ring_insert_nop, 8933 .pad_ib = amdgpu_ring_generic_pad_ib, 8934 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8935 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8936 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8937 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8938 }; 8939 8940 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8941 .type = AMDGPU_RING_TYPE_KIQ, 8942 .align_mask = 0xff, 8943 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8944 .support_64bit_ptrs = true, 8945 .vmhub = AMDGPU_GFXHUB_0, 8946 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8947 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8948 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8949 .emit_frame_size = 8950 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8951 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8952 5 + /*hdp invalidate */ 8953 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8954 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8955 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8956 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8957 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8958 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8959 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8960 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8961 .test_ring = gfx_v10_0_ring_test_ring, 8962 .test_ib = gfx_v10_0_ring_test_ib, 8963 .insert_nop = amdgpu_ring_insert_nop, 8964 .pad_ib = amdgpu_ring_generic_pad_ib, 8965 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8966 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8967 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8968 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8969 }; 8970 8971 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8972 { 8973 int i; 8974 8975 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8976 8977 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8978 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8979 8980 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8981 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8982 } 8983 8984 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8985 .set = gfx_v10_0_set_eop_interrupt_state, 8986 .process = gfx_v10_0_eop_irq, 8987 }; 8988 8989 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8990 .set = gfx_v10_0_set_priv_reg_fault_state, 8991 .process = gfx_v10_0_priv_reg_irq, 8992 }; 8993 8994 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8995 .set = gfx_v10_0_set_priv_inst_fault_state, 8996 .process = gfx_v10_0_priv_inst_irq, 8997 }; 8998 8999 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9000 .set = gfx_v10_0_kiq_set_interrupt_state, 9001 .process = gfx_v10_0_kiq_irq, 9002 }; 9003 9004 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9005 { 9006 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9007 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9008 9009 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9010 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9011 9012 adev->gfx.priv_reg_irq.num_types = 1; 9013 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9014 9015 adev->gfx.priv_inst_irq.num_types = 1; 9016 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9017 } 9018 9019 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9020 { 9021 switch (adev->asic_type) { 9022 case CHIP_NAVI10: 9023 case CHIP_NAVI14: 9024 case CHIP_SIENNA_CICHLID: 9025 case CHIP_NAVY_FLOUNDER: 9026 case CHIP_VANGOGH: 9027 case CHIP_DIMGREY_CAVEFISH: 9028 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9029 break; 9030 case CHIP_NAVI12: 9031 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9032 break; 9033 default: 9034 break; 9035 } 9036 } 9037 9038 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9039 { 9040 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9041 adev->gfx.config.max_sh_per_se * 9042 adev->gfx.config.max_shader_engines; 9043 9044 adev->gds.gds_size = 0x10000; 9045 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9046 adev->gds.gws_size = 64; 9047 adev->gds.oa_size = 16; 9048 } 9049 9050 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9051 u32 bitmap) 9052 { 9053 u32 data; 9054 9055 if (!bitmap) 9056 return; 9057 9058 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9059 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9060 9061 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9062 } 9063 9064 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9065 { 9066 u32 data, wgp_bitmask; 9067 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9068 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9069 9070 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9071 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9072 9073 wgp_bitmask = 9074 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9075 9076 return (~data) & wgp_bitmask; 9077 } 9078 9079 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9080 { 9081 u32 wgp_idx, wgp_active_bitmap; 9082 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9083 9084 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9085 cu_active_bitmap = 0; 9086 9087 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9088 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9089 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9090 if (wgp_active_bitmap & (1 << wgp_idx)) 9091 cu_active_bitmap |= cu_bitmap_per_wgp; 9092 } 9093 9094 return cu_active_bitmap; 9095 } 9096 9097 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9098 struct amdgpu_cu_info *cu_info) 9099 { 9100 int i, j, k, counter, active_cu_number = 0; 9101 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9102 unsigned disable_masks[4 * 2]; 9103 9104 if (!adev || !cu_info) 9105 return -EINVAL; 9106 9107 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9108 9109 mutex_lock(&adev->grbm_idx_mutex); 9110 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9111 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9112 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9113 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9114 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9115 continue; 9116 mask = 1; 9117 ao_bitmap = 0; 9118 counter = 0; 9119 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9120 if (i < 4 && j < 2) 9121 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9122 adev, disable_masks[i * 2 + j]); 9123 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9124 cu_info->bitmap[i][j] = bitmap; 9125 9126 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9127 if (bitmap & mask) { 9128 if (counter < adev->gfx.config.max_cu_per_sh) 9129 ao_bitmap |= mask; 9130 counter++; 9131 } 9132 mask <<= 1; 9133 } 9134 active_cu_number += counter; 9135 if (i < 2 && j < 2) 9136 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9137 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9138 } 9139 } 9140 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9141 mutex_unlock(&adev->grbm_idx_mutex); 9142 9143 cu_info->number = active_cu_number; 9144 cu_info->ao_cu_mask = ao_cu_mask; 9145 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9146 9147 return 0; 9148 } 9149 9150 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9151 { 9152 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9153 9154 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9155 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9156 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9157 9158 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9159 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9160 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9161 9162 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9163 adev->gfx.config.max_shader_engines); 9164 disabled_sa = efuse_setting | vbios_setting; 9165 disabled_sa &= max_sa_mask; 9166 9167 return disabled_sa; 9168 } 9169 9170 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9171 { 9172 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9173 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9174 9175 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9176 9177 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9178 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9179 max_shader_engines = adev->gfx.config.max_shader_engines; 9180 9181 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9182 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9183 disabled_sa_per_se &= max_sa_per_se_mask; 9184 if (disabled_sa_per_se == max_sa_per_se_mask) { 9185 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9186 break; 9187 } 9188 } 9189 } 9190 9191 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9192 { 9193 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9194 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9195 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9196 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9197 9198 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9199 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9200 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9201 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9202 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9203 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9204 9205 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9206 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9207 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9208 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9209 9210 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9211 9212 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9213 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9214 } 9215 9216 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9217 { 9218 .type = AMD_IP_BLOCK_TYPE_GFX, 9219 .major = 10, 9220 .minor = 0, 9221 .rev = 0, 9222 .funcs = &gfx_v10_0_ip_funcs, 9223 }; 9224