1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /** 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 115 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 117 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 119 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 121 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 125 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 128 129 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 131 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 133 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 135 #define mmCP_HYP_CE_UCODE_DATA 0x5819 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 137 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 139 #define mmCP_HYP_ME_UCODE_DATA 0x5817 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 141 142 #define mmCPG_PSP_DEBUG 0x5c10 143 #define mmCPG_PSP_DEBUG_BASE_IDX 1 144 #define mmCPC_PSP_DEBUG 0x5c11 145 #define mmCPC_PSP_DEBUG_BASE_IDX 1 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 148 149 //CC_GC_SA_UNIT_DISABLE 150 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 154 //GC_USER_SA_UNIT_DISABLE 155 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 159 //PA_SC_ENHANCE_3 160 #define mmPA_SC_ENHANCE_3 0x1085 161 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 164 165 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 167 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 172 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 175 176 #define GFX_RLCG_GC_WRITE_OLD (0x8 << 28) 177 #define GFX_RLCG_GC_WRITE (0x0 << 28) 178 #define GFX_RLCG_GC_READ (0x1 << 28) 179 #define GFX_RLCG_MMHUB_WRITE (0x2 << 28) 180 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 187 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 199 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 206 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 213 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 220 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 227 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 234 235 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 236 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 237 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 238 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 239 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 241 242 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 243 { 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 284 }; 285 286 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 287 { 288 /* Pending on emulation bring up */ 289 }; 290 291 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 292 { 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1345 }; 1346 1347 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1348 { 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1387 }; 1388 1389 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1390 { 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1433 }; 1434 1435 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write) 1436 { 1437 /* always programed by rlcg, only for gc */ 1438 if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) || 1439 offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) || 1440 offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) || 1441 offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) || 1442 offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) || 1443 offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) { 1444 if (!amdgpu_sriov_reg_indirect_gc(adev)) 1445 *flag = GFX_RLCG_GC_WRITE_OLD; 1446 else 1447 *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; 1448 1449 return true; 1450 } 1451 1452 /* currently support gc read/write, mmhub write */ 1453 if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) && 1454 offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) { 1455 if (amdgpu_sriov_reg_indirect_gc(adev)) 1456 *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; 1457 else 1458 return false; 1459 } else { 1460 if (amdgpu_sriov_reg_indirect_mmhub(adev)) 1461 *flag = GFX_RLCG_MMHUB_WRITE; 1462 else 1463 return false; 1464 } 1465 1466 return true; 1467 } 1468 1469 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag) 1470 { 1471 static void *scratch_reg0; 1472 static void *scratch_reg1; 1473 static void *scratch_reg2; 1474 static void *scratch_reg3; 1475 static void *spare_int; 1476 static uint32_t grbm_cntl; 1477 static uint32_t grbm_idx; 1478 uint32_t i = 0; 1479 uint32_t retries = 50000; 1480 u32 ret = 0; 1481 1482 scratch_reg0 = adev->rmmio + 1483 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; 1484 scratch_reg1 = adev->rmmio + 1485 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; 1486 scratch_reg2 = adev->rmmio + 1487 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; 1488 scratch_reg3 = adev->rmmio + 1489 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; 1490 spare_int = adev->rmmio + 1491 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; 1492 1493 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1494 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1495 1496 if (offset == grbm_cntl || offset == grbm_idx) { 1497 if (offset == grbm_cntl) 1498 writel(v, scratch_reg2); 1499 else if (offset == grbm_idx) 1500 writel(v, scratch_reg3); 1501 1502 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1503 } else { 1504 writel(v, scratch_reg0); 1505 writel(offset | flag, scratch_reg1); 1506 writel(1, spare_int); 1507 for (i = 0; i < retries; i++) { 1508 u32 tmp; 1509 1510 tmp = readl(scratch_reg1); 1511 if (!(tmp & flag)) 1512 break; 1513 1514 udelay(10); 1515 } 1516 1517 if (i >= retries) 1518 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1519 } 1520 1521 ret = readl(scratch_reg0); 1522 1523 return ret; 1524 } 1525 1526 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag) 1527 { 1528 uint32_t rlcg_flag; 1529 1530 if (amdgpu_sriov_fullaccess(adev) && 1531 gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) { 1532 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag); 1533 1534 return; 1535 } 1536 if (flag & AMDGPU_REGS_NO_KIQ) 1537 WREG32_NO_KIQ(offset, value); 1538 else 1539 WREG32(offset, value); 1540 } 1541 1542 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag) 1543 { 1544 uint32_t rlcg_flag; 1545 1546 if (amdgpu_sriov_fullaccess(adev) && 1547 gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0)) 1548 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag); 1549 1550 if (flag & AMDGPU_REGS_NO_KIQ) 1551 return RREG32_NO_KIQ(offset); 1552 else 1553 return RREG32(offset); 1554 1555 return 0; 1556 } 1557 1558 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1559 { 1560 /* Pending on emulation bring up */ 1561 }; 1562 1563 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1564 { 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2185 }; 2186 2187 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2188 { 2189 /* Pending on emulation bring up */ 2190 }; 2191 2192 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2193 { 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3246 }; 3247 3248 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3249 { 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3292 }; 3293 3294 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3295 { 3296 /* Pending on emulation bring up */ 3297 }; 3298 3299 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3300 { 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3342 3343 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3345 }; 3346 3347 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3348 { 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3372 3373 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3375 }; 3376 3377 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3378 { 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3414 }; 3415 3416 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3449 }; 3450 3451 #define DEFAULT_SH_MEM_CONFIG \ 3452 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3453 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3454 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3455 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3456 3457 3458 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3459 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3460 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3461 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3462 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3463 struct amdgpu_cu_info *cu_info); 3464 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3465 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3466 u32 sh_num, u32 instance); 3467 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3468 3469 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3470 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3471 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3472 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3473 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3474 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3475 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3476 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3477 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3478 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3479 3480 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3481 { 3482 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3483 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3484 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3485 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3486 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3487 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3488 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3489 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3490 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3491 } 3492 3493 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3494 struct amdgpu_ring *ring) 3495 { 3496 struct amdgpu_device *adev = kiq_ring->adev; 3497 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3498 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3499 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3500 3501 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3502 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3503 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3504 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3505 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3506 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3507 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3508 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3509 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3510 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3511 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3512 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3513 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3514 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3515 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3516 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3517 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3518 } 3519 3520 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3521 struct amdgpu_ring *ring, 3522 enum amdgpu_unmap_queues_action action, 3523 u64 gpu_addr, u64 seq) 3524 { 3525 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3526 3527 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3528 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3529 PACKET3_UNMAP_QUEUES_ACTION(action) | 3530 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3531 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3532 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3533 amdgpu_ring_write(kiq_ring, 3534 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3535 3536 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3537 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3538 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3539 amdgpu_ring_write(kiq_ring, seq); 3540 } else { 3541 amdgpu_ring_write(kiq_ring, 0); 3542 amdgpu_ring_write(kiq_ring, 0); 3543 amdgpu_ring_write(kiq_ring, 0); 3544 } 3545 } 3546 3547 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3548 struct amdgpu_ring *ring, 3549 u64 addr, 3550 u64 seq) 3551 { 3552 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3553 3554 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3555 amdgpu_ring_write(kiq_ring, 3556 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3557 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3558 PACKET3_QUERY_STATUS_COMMAND(2)); 3559 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3560 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3561 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3562 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3563 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3564 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3565 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3566 } 3567 3568 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3569 uint16_t pasid, uint32_t flush_type, 3570 bool all_hub) 3571 { 3572 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3573 amdgpu_ring_write(kiq_ring, 3574 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3575 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3576 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3577 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3578 } 3579 3580 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3581 .kiq_set_resources = gfx10_kiq_set_resources, 3582 .kiq_map_queues = gfx10_kiq_map_queues, 3583 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3584 .kiq_query_status = gfx10_kiq_query_status, 3585 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3586 .set_resources_size = 8, 3587 .map_queues_size = 7, 3588 .unmap_queues_size = 6, 3589 .query_status_size = 7, 3590 .invalidate_tlbs_size = 2, 3591 }; 3592 3593 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3594 { 3595 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3596 } 3597 3598 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3599 { 3600 switch (adev->asic_type) { 3601 case CHIP_NAVI10: 3602 soc15_program_register_sequence(adev, 3603 golden_settings_gc_rlc_spm_10_0_nv10, 3604 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3605 break; 3606 case CHIP_NAVI14: 3607 soc15_program_register_sequence(adev, 3608 golden_settings_gc_rlc_spm_10_1_nv14, 3609 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3610 break; 3611 case CHIP_NAVI12: 3612 soc15_program_register_sequence(adev, 3613 golden_settings_gc_rlc_spm_10_1_2_nv12, 3614 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3615 break; 3616 default: 3617 break; 3618 } 3619 } 3620 3621 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3622 { 3623 switch (adev->asic_type) { 3624 case CHIP_NAVI10: 3625 soc15_program_register_sequence(adev, 3626 golden_settings_gc_10_1, 3627 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3628 soc15_program_register_sequence(adev, 3629 golden_settings_gc_10_0_nv10, 3630 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3631 break; 3632 case CHIP_NAVI14: 3633 soc15_program_register_sequence(adev, 3634 golden_settings_gc_10_1_1, 3635 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3636 soc15_program_register_sequence(adev, 3637 golden_settings_gc_10_1_nv14, 3638 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3639 break; 3640 case CHIP_NAVI12: 3641 soc15_program_register_sequence(adev, 3642 golden_settings_gc_10_1_2, 3643 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3644 soc15_program_register_sequence(adev, 3645 golden_settings_gc_10_1_2_nv12, 3646 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3647 break; 3648 case CHIP_SIENNA_CICHLID: 3649 soc15_program_register_sequence(adev, 3650 golden_settings_gc_10_3, 3651 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3652 soc15_program_register_sequence(adev, 3653 golden_settings_gc_10_3_sienna_cichlid, 3654 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3655 break; 3656 case CHIP_NAVY_FLOUNDER: 3657 soc15_program_register_sequence(adev, 3658 golden_settings_gc_10_3_2, 3659 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3660 break; 3661 case CHIP_VANGOGH: 3662 soc15_program_register_sequence(adev, 3663 golden_settings_gc_10_3_vangogh, 3664 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3665 break; 3666 case CHIP_DIMGREY_CAVEFISH: 3667 soc15_program_register_sequence(adev, 3668 golden_settings_gc_10_3_4, 3669 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3670 break; 3671 case CHIP_BEIGE_GOBY: 3672 soc15_program_register_sequence(adev, 3673 golden_settings_gc_10_3_5, 3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3675 break; 3676 default: 3677 break; 3678 } 3679 gfx_v10_0_init_spm_golden_registers(adev); 3680 } 3681 3682 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3683 { 3684 adev->gfx.scratch.num_reg = 8; 3685 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3686 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3687 } 3688 3689 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3690 bool wc, uint32_t reg, uint32_t val) 3691 { 3692 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3693 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3694 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3695 amdgpu_ring_write(ring, reg); 3696 amdgpu_ring_write(ring, 0); 3697 amdgpu_ring_write(ring, val); 3698 } 3699 3700 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3701 int mem_space, int opt, uint32_t addr0, 3702 uint32_t addr1, uint32_t ref, uint32_t mask, 3703 uint32_t inv) 3704 { 3705 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3706 amdgpu_ring_write(ring, 3707 /* memory (1) or register (0) */ 3708 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3709 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3710 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3711 WAIT_REG_MEM_ENGINE(eng_sel))); 3712 3713 if (mem_space) 3714 BUG_ON(addr0 & 0x3); /* Dword align */ 3715 amdgpu_ring_write(ring, addr0); 3716 amdgpu_ring_write(ring, addr1); 3717 amdgpu_ring_write(ring, ref); 3718 amdgpu_ring_write(ring, mask); 3719 amdgpu_ring_write(ring, inv); /* poll interval */ 3720 } 3721 3722 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3723 { 3724 struct amdgpu_device *adev = ring->adev; 3725 uint32_t scratch; 3726 uint32_t tmp = 0; 3727 unsigned i; 3728 int r; 3729 3730 r = amdgpu_gfx_scratch_get(adev, &scratch); 3731 if (r) { 3732 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3733 return r; 3734 } 3735 3736 WREG32(scratch, 0xCAFEDEAD); 3737 3738 r = amdgpu_ring_alloc(ring, 3); 3739 if (r) { 3740 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3741 ring->idx, r); 3742 amdgpu_gfx_scratch_free(adev, scratch); 3743 return r; 3744 } 3745 3746 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3747 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3748 amdgpu_ring_write(ring, 0xDEADBEEF); 3749 amdgpu_ring_commit(ring); 3750 3751 for (i = 0; i < adev->usec_timeout; i++) { 3752 tmp = RREG32(scratch); 3753 if (tmp == 0xDEADBEEF) 3754 break; 3755 if (amdgpu_emu_mode == 1) 3756 msleep(1); 3757 else 3758 udelay(1); 3759 } 3760 3761 if (i >= adev->usec_timeout) 3762 r = -ETIMEDOUT; 3763 3764 amdgpu_gfx_scratch_free(adev, scratch); 3765 3766 return r; 3767 } 3768 3769 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3770 { 3771 struct amdgpu_device *adev = ring->adev; 3772 struct amdgpu_ib ib; 3773 struct dma_fence *f = NULL; 3774 unsigned index; 3775 uint64_t gpu_addr; 3776 uint32_t tmp; 3777 long r; 3778 3779 r = amdgpu_device_wb_get(adev, &index); 3780 if (r) 3781 return r; 3782 3783 gpu_addr = adev->wb.gpu_addr + (index * 4); 3784 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3785 memset(&ib, 0, sizeof(ib)); 3786 r = amdgpu_ib_get(adev, NULL, 16, 3787 AMDGPU_IB_POOL_DIRECT, &ib); 3788 if (r) 3789 goto err1; 3790 3791 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3792 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3793 ib.ptr[2] = lower_32_bits(gpu_addr); 3794 ib.ptr[3] = upper_32_bits(gpu_addr); 3795 ib.ptr[4] = 0xDEADBEEF; 3796 ib.length_dw = 5; 3797 3798 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3799 if (r) 3800 goto err2; 3801 3802 r = dma_fence_wait_timeout(f, false, timeout); 3803 if (r == 0) { 3804 r = -ETIMEDOUT; 3805 goto err2; 3806 } else if (r < 0) { 3807 goto err2; 3808 } 3809 3810 tmp = adev->wb.wb[index]; 3811 if (tmp == 0xDEADBEEF) 3812 r = 0; 3813 else 3814 r = -EINVAL; 3815 err2: 3816 amdgpu_ib_free(adev, &ib, NULL); 3817 dma_fence_put(f); 3818 err1: 3819 amdgpu_device_wb_free(adev, index); 3820 return r; 3821 } 3822 3823 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3824 { 3825 release_firmware(adev->gfx.pfp_fw); 3826 adev->gfx.pfp_fw = NULL; 3827 release_firmware(adev->gfx.me_fw); 3828 adev->gfx.me_fw = NULL; 3829 release_firmware(adev->gfx.ce_fw); 3830 adev->gfx.ce_fw = NULL; 3831 release_firmware(adev->gfx.rlc_fw); 3832 adev->gfx.rlc_fw = NULL; 3833 release_firmware(adev->gfx.mec_fw); 3834 adev->gfx.mec_fw = NULL; 3835 release_firmware(adev->gfx.mec2_fw); 3836 adev->gfx.mec2_fw = NULL; 3837 3838 kfree(adev->gfx.rlc.register_list_format); 3839 } 3840 3841 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3842 { 3843 adev->gfx.cp_fw_write_wait = false; 3844 3845 switch (adev->asic_type) { 3846 case CHIP_NAVI10: 3847 case CHIP_NAVI12: 3848 case CHIP_NAVI14: 3849 if ((adev->gfx.me_fw_version >= 0x00000046) && 3850 (adev->gfx.me_feature_version >= 27) && 3851 (adev->gfx.pfp_fw_version >= 0x00000068) && 3852 (adev->gfx.pfp_feature_version >= 27) && 3853 (adev->gfx.mec_fw_version >= 0x0000005b) && 3854 (adev->gfx.mec_feature_version >= 27)) 3855 adev->gfx.cp_fw_write_wait = true; 3856 break; 3857 case CHIP_SIENNA_CICHLID: 3858 case CHIP_NAVY_FLOUNDER: 3859 case CHIP_VANGOGH: 3860 case CHIP_DIMGREY_CAVEFISH: 3861 case CHIP_BEIGE_GOBY: 3862 adev->gfx.cp_fw_write_wait = true; 3863 break; 3864 default: 3865 break; 3866 } 3867 3868 if (!adev->gfx.cp_fw_write_wait) 3869 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3870 } 3871 3872 3873 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3874 { 3875 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3876 3877 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3878 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3879 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3880 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3881 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3882 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3883 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3884 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3885 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3886 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3887 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3888 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3889 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3890 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3891 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3892 } 3893 3894 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3895 { 3896 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3897 3898 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3899 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3900 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3901 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3902 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3903 } 3904 3905 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3906 { 3907 bool ret = false; 3908 3909 switch (adev->pdev->revision) { 3910 case 0xc2: 3911 case 0xc3: 3912 ret = true; 3913 break; 3914 default: 3915 ret = false; 3916 break; 3917 } 3918 3919 return ret ; 3920 } 3921 3922 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3923 { 3924 switch (adev->asic_type) { 3925 case CHIP_NAVI10: 3926 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3927 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3928 break; 3929 default: 3930 break; 3931 } 3932 } 3933 3934 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3935 { 3936 const char *chip_name; 3937 char fw_name[40]; 3938 char wks[10]; 3939 int err; 3940 struct amdgpu_firmware_info *info = NULL; 3941 const struct common_firmware_header *header = NULL; 3942 const struct gfx_firmware_header_v1_0 *cp_hdr; 3943 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3944 unsigned int *tmp = NULL; 3945 unsigned int i = 0; 3946 uint16_t version_major; 3947 uint16_t version_minor; 3948 3949 DRM_DEBUG("\n"); 3950 3951 memset(wks, 0, sizeof(wks)); 3952 switch (adev->asic_type) { 3953 case CHIP_NAVI10: 3954 chip_name = "navi10"; 3955 break; 3956 case CHIP_NAVI14: 3957 chip_name = "navi14"; 3958 if (!(adev->pdev->device == 0x7340 && 3959 adev->pdev->revision != 0x00)) 3960 snprintf(wks, sizeof(wks), "_wks"); 3961 break; 3962 case CHIP_NAVI12: 3963 chip_name = "navi12"; 3964 break; 3965 case CHIP_SIENNA_CICHLID: 3966 chip_name = "sienna_cichlid"; 3967 break; 3968 case CHIP_NAVY_FLOUNDER: 3969 chip_name = "navy_flounder"; 3970 break; 3971 case CHIP_VANGOGH: 3972 chip_name = "vangogh"; 3973 break; 3974 case CHIP_DIMGREY_CAVEFISH: 3975 chip_name = "dimgrey_cavefish"; 3976 break; 3977 case CHIP_BEIGE_GOBY: 3978 chip_name = "beige_goby"; 3979 break; 3980 default: 3981 BUG(); 3982 } 3983 3984 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3985 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3986 if (err) 3987 goto out; 3988 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3989 if (err) 3990 goto out; 3991 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3992 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3993 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3994 3995 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3996 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3997 if (err) 3998 goto out; 3999 err = amdgpu_ucode_validate(adev->gfx.me_fw); 4000 if (err) 4001 goto out; 4002 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 4003 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4004 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4005 4006 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 4007 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 4008 if (err) 4009 goto out; 4010 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 4011 if (err) 4012 goto out; 4013 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 4014 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4015 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4016 4017 if (!amdgpu_sriov_vf(adev)) { 4018 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 4019 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4020 if (err) 4021 goto out; 4022 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 4023 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4024 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4025 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4026 4027 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 4028 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 4029 adev->gfx.rlc.save_and_restore_offset = 4030 le32_to_cpu(rlc_hdr->save_and_restore_offset); 4031 adev->gfx.rlc.clear_state_descriptor_offset = 4032 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 4033 adev->gfx.rlc.avail_scratch_ram_locations = 4034 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 4035 adev->gfx.rlc.reg_restore_list_size = 4036 le32_to_cpu(rlc_hdr->reg_restore_list_size); 4037 adev->gfx.rlc.reg_list_format_start = 4038 le32_to_cpu(rlc_hdr->reg_list_format_start); 4039 adev->gfx.rlc.reg_list_format_separate_start = 4040 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 4041 adev->gfx.rlc.starting_offsets_start = 4042 le32_to_cpu(rlc_hdr->starting_offsets_start); 4043 adev->gfx.rlc.reg_list_format_size_bytes = 4044 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 4045 adev->gfx.rlc.reg_list_size_bytes = 4046 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 4047 adev->gfx.rlc.register_list_format = 4048 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 4049 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 4050 if (!adev->gfx.rlc.register_list_format) { 4051 err = -ENOMEM; 4052 goto out; 4053 } 4054 4055 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4056 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 4057 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 4058 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 4059 4060 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 4061 4062 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4063 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 4064 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 4065 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 4066 4067 if (version_major == 2) { 4068 if (version_minor >= 1) 4069 gfx_v10_0_init_rlc_ext_microcode(adev); 4070 if (version_minor == 2) 4071 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 4072 } 4073 } 4074 4075 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 4076 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 4077 if (err) 4078 goto out; 4079 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 4080 if (err) 4081 goto out; 4082 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4083 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4084 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4085 4086 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 4087 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 4088 if (!err) { 4089 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 4090 if (err) 4091 goto out; 4092 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 4093 adev->gfx.mec2_fw->data; 4094 adev->gfx.mec2_fw_version = 4095 le32_to_cpu(cp_hdr->header.ucode_version); 4096 adev->gfx.mec2_feature_version = 4097 le32_to_cpu(cp_hdr->ucode_feature_version); 4098 } else { 4099 err = 0; 4100 adev->gfx.mec2_fw = NULL; 4101 } 4102 4103 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 4104 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 4105 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 4106 info->fw = adev->gfx.pfp_fw; 4107 header = (const struct common_firmware_header *)info->fw->data; 4108 adev->firmware.fw_size += 4109 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4110 4111 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 4112 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 4113 info->fw = adev->gfx.me_fw; 4114 header = (const struct common_firmware_header *)info->fw->data; 4115 adev->firmware.fw_size += 4116 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4117 4118 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 4119 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 4120 info->fw = adev->gfx.ce_fw; 4121 header = (const struct common_firmware_header *)info->fw->data; 4122 adev->firmware.fw_size += 4123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4124 4125 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 4126 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 4127 info->fw = adev->gfx.rlc_fw; 4128 if (info->fw) { 4129 header = (const struct common_firmware_header *)info->fw->data; 4130 adev->firmware.fw_size += 4131 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4132 } 4133 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 4134 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 4135 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 4136 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 4137 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 4138 info->fw = adev->gfx.rlc_fw; 4139 adev->firmware.fw_size += 4140 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 4141 4142 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 4143 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 4144 info->fw = adev->gfx.rlc_fw; 4145 adev->firmware.fw_size += 4146 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4147 4148 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4149 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4150 info->fw = adev->gfx.rlc_fw; 4151 adev->firmware.fw_size += 4152 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4153 4154 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4155 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4156 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4157 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4158 info->fw = adev->gfx.rlc_fw; 4159 adev->firmware.fw_size += 4160 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4161 4162 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4163 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4164 info->fw = adev->gfx.rlc_fw; 4165 adev->firmware.fw_size += 4166 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4167 } 4168 } 4169 4170 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4171 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4172 info->fw = adev->gfx.mec_fw; 4173 header = (const struct common_firmware_header *)info->fw->data; 4174 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4175 adev->firmware.fw_size += 4176 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4177 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4178 4179 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4180 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4181 info->fw = adev->gfx.mec_fw; 4182 adev->firmware.fw_size += 4183 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4184 4185 if (adev->gfx.mec2_fw) { 4186 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4187 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4188 info->fw = adev->gfx.mec2_fw; 4189 header = (const struct common_firmware_header *)info->fw->data; 4190 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4191 adev->firmware.fw_size += 4192 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4193 le32_to_cpu(cp_hdr->jt_size) * 4, 4194 PAGE_SIZE); 4195 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4196 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4197 info->fw = adev->gfx.mec2_fw; 4198 adev->firmware.fw_size += 4199 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4200 PAGE_SIZE); 4201 } 4202 } 4203 4204 gfx_v10_0_check_fw_write_wait(adev); 4205 out: 4206 if (err) { 4207 dev_err(adev->dev, 4208 "gfx10: Failed to load firmware \"%s\"\n", 4209 fw_name); 4210 release_firmware(adev->gfx.pfp_fw); 4211 adev->gfx.pfp_fw = NULL; 4212 release_firmware(adev->gfx.me_fw); 4213 adev->gfx.me_fw = NULL; 4214 release_firmware(adev->gfx.ce_fw); 4215 adev->gfx.ce_fw = NULL; 4216 release_firmware(adev->gfx.rlc_fw); 4217 adev->gfx.rlc_fw = NULL; 4218 release_firmware(adev->gfx.mec_fw); 4219 adev->gfx.mec_fw = NULL; 4220 release_firmware(adev->gfx.mec2_fw); 4221 adev->gfx.mec2_fw = NULL; 4222 } 4223 4224 gfx_v10_0_check_gfxoff_flag(adev); 4225 4226 return err; 4227 } 4228 4229 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4230 { 4231 u32 count = 0; 4232 const struct cs_section_def *sect = NULL; 4233 const struct cs_extent_def *ext = NULL; 4234 4235 /* begin clear state */ 4236 count += 2; 4237 /* context control state */ 4238 count += 3; 4239 4240 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4241 for (ext = sect->section; ext->extent != NULL; ++ext) { 4242 if (sect->id == SECT_CONTEXT) 4243 count += 2 + ext->reg_count; 4244 else 4245 return 0; 4246 } 4247 } 4248 4249 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4250 count += 3; 4251 /* end clear state */ 4252 count += 2; 4253 /* clear state */ 4254 count += 2; 4255 4256 return count; 4257 } 4258 4259 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4260 volatile u32 *buffer) 4261 { 4262 u32 count = 0, i; 4263 const struct cs_section_def *sect = NULL; 4264 const struct cs_extent_def *ext = NULL; 4265 int ctx_reg_offset; 4266 4267 if (adev->gfx.rlc.cs_data == NULL) 4268 return; 4269 if (buffer == NULL) 4270 return; 4271 4272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4273 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4274 4275 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4276 buffer[count++] = cpu_to_le32(0x80000000); 4277 buffer[count++] = cpu_to_le32(0x80000000); 4278 4279 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4280 for (ext = sect->section; ext->extent != NULL; ++ext) { 4281 if (sect->id == SECT_CONTEXT) { 4282 buffer[count++] = 4283 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4284 buffer[count++] = cpu_to_le32(ext->reg_index - 4285 PACKET3_SET_CONTEXT_REG_START); 4286 for (i = 0; i < ext->reg_count; i++) 4287 buffer[count++] = cpu_to_le32(ext->extent[i]); 4288 } else { 4289 return; 4290 } 4291 } 4292 } 4293 4294 ctx_reg_offset = 4295 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4296 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4297 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4298 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4299 4300 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4301 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4302 4303 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4304 buffer[count++] = cpu_to_le32(0); 4305 } 4306 4307 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4308 { 4309 /* clear state block */ 4310 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4311 &adev->gfx.rlc.clear_state_gpu_addr, 4312 (void **)&adev->gfx.rlc.cs_ptr); 4313 4314 /* jump table block */ 4315 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4316 &adev->gfx.rlc.cp_table_gpu_addr, 4317 (void **)&adev->gfx.rlc.cp_table_ptr); 4318 } 4319 4320 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4321 { 4322 const struct cs_section_def *cs_data; 4323 int r; 4324 4325 adev->gfx.rlc.cs_data = gfx10_cs_data; 4326 4327 cs_data = adev->gfx.rlc.cs_data; 4328 4329 if (cs_data) { 4330 /* init clear state block */ 4331 r = amdgpu_gfx_rlc_init_csb(adev); 4332 if (r) 4333 return r; 4334 } 4335 4336 /* init spm vmid with 0xf */ 4337 if (adev->gfx.rlc.funcs->update_spm_vmid) 4338 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4339 4340 return 0; 4341 } 4342 4343 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4344 { 4345 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4346 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4347 } 4348 4349 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4350 { 4351 int r; 4352 4353 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4354 4355 amdgpu_gfx_graphics_queue_acquire(adev); 4356 4357 r = gfx_v10_0_init_microcode(adev); 4358 if (r) 4359 DRM_ERROR("Failed to load gfx firmware!\n"); 4360 4361 return r; 4362 } 4363 4364 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4365 { 4366 int r; 4367 u32 *hpd; 4368 const __le32 *fw_data = NULL; 4369 unsigned fw_size; 4370 u32 *fw = NULL; 4371 size_t mec_hpd_size; 4372 4373 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4374 4375 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4376 4377 /* take ownership of the relevant compute queues */ 4378 amdgpu_gfx_compute_queue_acquire(adev); 4379 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4380 4381 if (mec_hpd_size) { 4382 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4383 AMDGPU_GEM_DOMAIN_GTT, 4384 &adev->gfx.mec.hpd_eop_obj, 4385 &adev->gfx.mec.hpd_eop_gpu_addr, 4386 (void **)&hpd); 4387 if (r) { 4388 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4389 gfx_v10_0_mec_fini(adev); 4390 return r; 4391 } 4392 4393 memset(hpd, 0, mec_hpd_size); 4394 4395 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4396 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4397 } 4398 4399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4400 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4401 4402 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4403 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4404 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4405 4406 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4407 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4408 &adev->gfx.mec.mec_fw_obj, 4409 &adev->gfx.mec.mec_fw_gpu_addr, 4410 (void **)&fw); 4411 if (r) { 4412 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4413 gfx_v10_0_mec_fini(adev); 4414 return r; 4415 } 4416 4417 memcpy(fw, fw_data, fw_size); 4418 4419 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4420 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4421 } 4422 4423 return 0; 4424 } 4425 4426 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4427 { 4428 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4429 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4430 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4431 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4432 } 4433 4434 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4435 uint32_t thread, uint32_t regno, 4436 uint32_t num, uint32_t *out) 4437 { 4438 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4439 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4440 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4441 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4442 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4443 while (num--) 4444 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4445 } 4446 4447 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4448 { 4449 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4450 * field when performing a select_se_sh so it should be 4451 * zero here */ 4452 WARN_ON(simd != 0); 4453 4454 /* type 2 wave data */ 4455 dst[(*no_fields)++] = 2; 4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4457 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4458 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4459 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4460 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4461 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4462 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4463 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4464 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4465 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4466 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4467 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4468 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4469 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4470 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4471 } 4472 4473 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4474 uint32_t wave, uint32_t start, 4475 uint32_t size, uint32_t *dst) 4476 { 4477 WARN_ON(simd != 0); 4478 4479 wave_read_regs( 4480 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4481 dst); 4482 } 4483 4484 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4485 uint32_t wave, uint32_t thread, 4486 uint32_t start, uint32_t size, 4487 uint32_t *dst) 4488 { 4489 wave_read_regs( 4490 adev, wave, thread, 4491 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4492 } 4493 4494 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4495 u32 me, u32 pipe, u32 q, u32 vm) 4496 { 4497 nv_grbm_select(adev, me, pipe, q, vm); 4498 } 4499 4500 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4501 bool enable) 4502 { 4503 uint32_t data, def; 4504 4505 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4506 4507 if (enable) 4508 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4509 else 4510 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4511 4512 if (data != def) 4513 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4514 } 4515 4516 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4517 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4518 .select_se_sh = &gfx_v10_0_select_se_sh, 4519 .read_wave_data = &gfx_v10_0_read_wave_data, 4520 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4521 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4522 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4523 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4524 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4525 }; 4526 4527 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4528 { 4529 u32 gb_addr_config; 4530 4531 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4532 4533 switch (adev->asic_type) { 4534 case CHIP_NAVI10: 4535 case CHIP_NAVI14: 4536 case CHIP_NAVI12: 4537 adev->gfx.config.max_hw_contexts = 8; 4538 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4539 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4540 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4541 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4542 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4543 break; 4544 case CHIP_SIENNA_CICHLID: 4545 case CHIP_NAVY_FLOUNDER: 4546 case CHIP_VANGOGH: 4547 case CHIP_DIMGREY_CAVEFISH: 4548 case CHIP_BEIGE_GOBY: 4549 adev->gfx.config.max_hw_contexts = 8; 4550 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4551 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4552 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4553 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4554 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4555 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4556 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4557 break; 4558 default: 4559 BUG(); 4560 break; 4561 } 4562 4563 adev->gfx.config.gb_addr_config = gb_addr_config; 4564 4565 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4566 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4567 GB_ADDR_CONFIG, NUM_PIPES); 4568 4569 adev->gfx.config.max_tile_pipes = 4570 adev->gfx.config.gb_addr_config_fields.num_pipes; 4571 4572 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4573 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4574 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4575 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4576 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4577 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4578 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4579 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4580 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4581 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4582 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4583 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4584 } 4585 4586 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4587 int me, int pipe, int queue) 4588 { 4589 int r; 4590 struct amdgpu_ring *ring; 4591 unsigned int irq_type; 4592 4593 ring = &adev->gfx.gfx_ring[ring_id]; 4594 4595 ring->me = me; 4596 ring->pipe = pipe; 4597 ring->queue = queue; 4598 4599 ring->ring_obj = NULL; 4600 ring->use_doorbell = true; 4601 4602 if (!ring_id) 4603 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4604 else 4605 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4606 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4607 4608 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4609 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4610 AMDGPU_RING_PRIO_DEFAULT, NULL); 4611 if (r) 4612 return r; 4613 return 0; 4614 } 4615 4616 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4617 int mec, int pipe, int queue) 4618 { 4619 int r; 4620 unsigned irq_type; 4621 struct amdgpu_ring *ring; 4622 unsigned int hw_prio; 4623 4624 ring = &adev->gfx.compute_ring[ring_id]; 4625 4626 /* mec0 is me1 */ 4627 ring->me = mec + 1; 4628 ring->pipe = pipe; 4629 ring->queue = queue; 4630 4631 ring->ring_obj = NULL; 4632 ring->use_doorbell = true; 4633 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4634 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4635 + (ring_id * GFX10_MEC_HPD_SIZE); 4636 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4637 4638 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4639 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4640 + ring->pipe; 4641 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4642 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4643 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4644 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4645 hw_prio, NULL); 4646 if (r) 4647 return r; 4648 4649 return 0; 4650 } 4651 4652 static int gfx_v10_0_sw_init(void *handle) 4653 { 4654 int i, j, k, r, ring_id = 0; 4655 struct amdgpu_kiq *kiq; 4656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4657 4658 switch (adev->asic_type) { 4659 case CHIP_NAVI10: 4660 case CHIP_NAVI14: 4661 case CHIP_NAVI12: 4662 adev->gfx.me.num_me = 1; 4663 adev->gfx.me.num_pipe_per_me = 1; 4664 adev->gfx.me.num_queue_per_pipe = 1; 4665 adev->gfx.mec.num_mec = 2; 4666 adev->gfx.mec.num_pipe_per_mec = 4; 4667 adev->gfx.mec.num_queue_per_pipe = 8; 4668 break; 4669 case CHIP_SIENNA_CICHLID: 4670 case CHIP_NAVY_FLOUNDER: 4671 case CHIP_VANGOGH: 4672 case CHIP_DIMGREY_CAVEFISH: 4673 case CHIP_BEIGE_GOBY: 4674 adev->gfx.me.num_me = 1; 4675 adev->gfx.me.num_pipe_per_me = 1; 4676 adev->gfx.me.num_queue_per_pipe = 1; 4677 adev->gfx.mec.num_mec = 2; 4678 adev->gfx.mec.num_pipe_per_mec = 4; 4679 adev->gfx.mec.num_queue_per_pipe = 4; 4680 break; 4681 default: 4682 adev->gfx.me.num_me = 1; 4683 adev->gfx.me.num_pipe_per_me = 1; 4684 adev->gfx.me.num_queue_per_pipe = 1; 4685 adev->gfx.mec.num_mec = 1; 4686 adev->gfx.mec.num_pipe_per_mec = 4; 4687 adev->gfx.mec.num_queue_per_pipe = 8; 4688 break; 4689 } 4690 4691 /* KIQ event */ 4692 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4693 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4694 &adev->gfx.kiq.irq); 4695 if (r) 4696 return r; 4697 4698 /* EOP Event */ 4699 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4700 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4701 &adev->gfx.eop_irq); 4702 if (r) 4703 return r; 4704 4705 /* Privileged reg */ 4706 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4707 &adev->gfx.priv_reg_irq); 4708 if (r) 4709 return r; 4710 4711 /* Privileged inst */ 4712 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4713 &adev->gfx.priv_inst_irq); 4714 if (r) 4715 return r; 4716 4717 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4718 4719 gfx_v10_0_scratch_init(adev); 4720 4721 r = gfx_v10_0_me_init(adev); 4722 if (r) 4723 return r; 4724 4725 r = gfx_v10_0_rlc_init(adev); 4726 if (r) { 4727 DRM_ERROR("Failed to init rlc BOs!\n"); 4728 return r; 4729 } 4730 4731 r = gfx_v10_0_mec_init(adev); 4732 if (r) { 4733 DRM_ERROR("Failed to init MEC BOs!\n"); 4734 return r; 4735 } 4736 4737 /* set up the gfx ring */ 4738 for (i = 0; i < adev->gfx.me.num_me; i++) { 4739 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4740 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4741 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4742 continue; 4743 4744 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4745 i, k, j); 4746 if (r) 4747 return r; 4748 ring_id++; 4749 } 4750 } 4751 } 4752 4753 ring_id = 0; 4754 /* set up the compute queues - allocate horizontally across pipes */ 4755 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4756 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4757 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4758 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4759 j)) 4760 continue; 4761 4762 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4763 i, k, j); 4764 if (r) 4765 return r; 4766 4767 ring_id++; 4768 } 4769 } 4770 } 4771 4772 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4773 if (r) { 4774 DRM_ERROR("Failed to init KIQ BOs!\n"); 4775 return r; 4776 } 4777 4778 kiq = &adev->gfx.kiq; 4779 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4780 if (r) 4781 return r; 4782 4783 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4784 if (r) 4785 return r; 4786 4787 /* allocate visible FB for rlc auto-loading fw */ 4788 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4789 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4790 if (r) 4791 return r; 4792 } 4793 4794 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4795 4796 gfx_v10_0_gpu_early_init(adev); 4797 4798 return 0; 4799 } 4800 4801 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4802 { 4803 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4804 &adev->gfx.pfp.pfp_fw_gpu_addr, 4805 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4806 } 4807 4808 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4809 { 4810 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4811 &adev->gfx.ce.ce_fw_gpu_addr, 4812 (void **)&adev->gfx.ce.ce_fw_ptr); 4813 } 4814 4815 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4816 { 4817 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4818 &adev->gfx.me.me_fw_gpu_addr, 4819 (void **)&adev->gfx.me.me_fw_ptr); 4820 } 4821 4822 static int gfx_v10_0_sw_fini(void *handle) 4823 { 4824 int i; 4825 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4826 4827 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4828 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4829 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4830 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4831 4832 amdgpu_gfx_mqd_sw_fini(adev); 4833 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4834 amdgpu_gfx_kiq_fini(adev); 4835 4836 gfx_v10_0_pfp_fini(adev); 4837 gfx_v10_0_ce_fini(adev); 4838 gfx_v10_0_me_fini(adev); 4839 gfx_v10_0_rlc_fini(adev); 4840 gfx_v10_0_mec_fini(adev); 4841 4842 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4843 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4844 4845 gfx_v10_0_free_microcode(adev); 4846 4847 return 0; 4848 } 4849 4850 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4851 u32 sh_num, u32 instance) 4852 { 4853 u32 data; 4854 4855 if (instance == 0xffffffff) 4856 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4857 INSTANCE_BROADCAST_WRITES, 1); 4858 else 4859 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4860 instance); 4861 4862 if (se_num == 0xffffffff) 4863 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4864 1); 4865 else 4866 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4867 4868 if (sh_num == 0xffffffff) 4869 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4870 1); 4871 else 4872 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4873 4874 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4875 } 4876 4877 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4878 { 4879 u32 data, mask; 4880 4881 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4882 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4883 4884 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4885 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4886 4887 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4888 adev->gfx.config.max_sh_per_se); 4889 4890 return (~data) & mask; 4891 } 4892 4893 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4894 { 4895 int i, j; 4896 u32 data; 4897 u32 active_rbs = 0; 4898 u32 bitmap; 4899 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4900 adev->gfx.config.max_sh_per_se; 4901 4902 mutex_lock(&adev->grbm_idx_mutex); 4903 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4904 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4905 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4906 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4907 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4908 continue; 4909 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4910 data = gfx_v10_0_get_rb_active_bitmap(adev); 4911 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4912 rb_bitmap_width_per_sh); 4913 } 4914 } 4915 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4916 mutex_unlock(&adev->grbm_idx_mutex); 4917 4918 adev->gfx.config.backend_enable_mask = active_rbs; 4919 adev->gfx.config.num_rbs = hweight32(active_rbs); 4920 } 4921 4922 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4923 { 4924 uint32_t num_sc; 4925 uint32_t enabled_rb_per_sh; 4926 uint32_t active_rb_bitmap; 4927 uint32_t num_rb_per_sc; 4928 uint32_t num_packer_per_sc; 4929 uint32_t pa_sc_tile_steering_override; 4930 4931 /* for ASICs that integrates GFX v10.3 4932 * pa_sc_tile_steering_override should be set to 0 */ 4933 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4934 return 0; 4935 4936 /* init num_sc */ 4937 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4938 adev->gfx.config.num_sc_per_sh; 4939 /* init num_rb_per_sc */ 4940 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4941 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4942 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4943 /* init num_packer_per_sc */ 4944 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4945 4946 pa_sc_tile_steering_override = 0; 4947 pa_sc_tile_steering_override |= 4948 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4949 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4950 pa_sc_tile_steering_override |= 4951 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4952 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4953 pa_sc_tile_steering_override |= 4954 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4955 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4956 4957 return pa_sc_tile_steering_override; 4958 } 4959 4960 #define DEFAULT_SH_MEM_BASES (0x6000) 4961 4962 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4963 { 4964 int i; 4965 uint32_t sh_mem_bases; 4966 4967 /* 4968 * Configure apertures: 4969 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4970 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4971 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4972 */ 4973 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4974 4975 mutex_lock(&adev->srbm_mutex); 4976 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4977 nv_grbm_select(adev, 0, 0, 0, i); 4978 /* CP and shaders */ 4979 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4980 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4981 } 4982 nv_grbm_select(adev, 0, 0, 0, 0); 4983 mutex_unlock(&adev->srbm_mutex); 4984 4985 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4986 acccess. These should be enabled by FW for target VMIDs. */ 4987 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4988 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4989 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4990 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4991 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4992 } 4993 } 4994 4995 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4996 { 4997 int vmid; 4998 4999 /* 5000 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5001 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5002 * the driver can enable them for graphics. VMID0 should maintain 5003 * access so that HWS firmware can save/restore entries. 5004 */ 5005 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5006 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5007 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5008 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5009 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5010 } 5011 } 5012 5013 5014 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5015 { 5016 int i, j, k; 5017 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5018 u32 tmp, wgp_active_bitmap = 0; 5019 u32 gcrd_targets_disable_tcp = 0; 5020 u32 utcl_invreq_disable = 0; 5021 /* 5022 * GCRD_TARGETS_DISABLE field contains 5023 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5024 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5025 */ 5026 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5027 2 * max_wgp_per_sh + /* TCP */ 5028 max_wgp_per_sh + /* SQC */ 5029 4); /* GL1C */ 5030 /* 5031 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5032 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5033 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5034 */ 5035 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5036 2 * max_wgp_per_sh + /* TCP */ 5037 2 * max_wgp_per_sh + /* SQC */ 5038 4 + /* RMI */ 5039 1); /* SQG */ 5040 5041 if (adev->asic_type == CHIP_NAVI10 || 5042 adev->asic_type == CHIP_NAVI14 || 5043 adev->asic_type == CHIP_NAVI12) { 5044 mutex_lock(&adev->grbm_idx_mutex); 5045 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5046 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5047 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5048 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5049 /* 5050 * Set corresponding TCP bits for the inactive WGPs in 5051 * GCRD_SA_TARGETS_DISABLE 5052 */ 5053 gcrd_targets_disable_tcp = 0; 5054 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5055 utcl_invreq_disable = 0; 5056 5057 for (k = 0; k < max_wgp_per_sh; k++) { 5058 if (!(wgp_active_bitmap & (1 << k))) { 5059 gcrd_targets_disable_tcp |= 3 << (2 * k); 5060 utcl_invreq_disable |= (3 << (2 * k)) | 5061 (3 << (2 * (max_wgp_per_sh + k))); 5062 } 5063 } 5064 5065 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5066 /* only override TCP & SQC bits */ 5067 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 5068 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5069 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5070 5071 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5072 /* only override TCP bits */ 5073 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 5074 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5075 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5076 } 5077 } 5078 5079 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5080 mutex_unlock(&adev->grbm_idx_mutex); 5081 } 5082 } 5083 5084 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5085 { 5086 /* TCCs are global (not instanced). */ 5087 uint32_t tcc_disable; 5088 5089 if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 5090 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5091 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5092 } else { 5093 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5094 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5095 } 5096 5097 adev->gfx.config.tcc_disabled_mask = 5098 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5099 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5100 } 5101 5102 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5103 { 5104 u32 tmp; 5105 int i; 5106 5107 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5108 5109 gfx_v10_0_setup_rb(adev); 5110 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5111 gfx_v10_0_get_tcc_info(adev); 5112 adev->gfx.config.pa_sc_tile_steering_override = 5113 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5114 5115 /* XXX SH_MEM regs */ 5116 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5117 mutex_lock(&adev->srbm_mutex); 5118 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 5119 nv_grbm_select(adev, 0, 0, 0, i); 5120 /* CP and shaders */ 5121 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5122 if (i != 0) { 5123 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5124 (adev->gmc.private_aperture_start >> 48)); 5125 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5126 (adev->gmc.shared_aperture_start >> 48)); 5127 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5128 } 5129 } 5130 nv_grbm_select(adev, 0, 0, 0, 0); 5131 5132 mutex_unlock(&adev->srbm_mutex); 5133 5134 gfx_v10_0_init_compute_vmid(adev); 5135 gfx_v10_0_init_gds_vmid(adev); 5136 5137 } 5138 5139 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5140 bool enable) 5141 { 5142 u32 tmp; 5143 5144 if (amdgpu_sriov_vf(adev)) 5145 return; 5146 5147 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5148 5149 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5150 enable ? 1 : 0); 5151 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5152 enable ? 1 : 0); 5153 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5154 enable ? 1 : 0); 5155 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5156 enable ? 1 : 0); 5157 5158 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5159 } 5160 5161 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5162 { 5163 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5164 5165 /* csib */ 5166 if (adev->asic_type == CHIP_NAVI12) { 5167 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5168 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5169 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5170 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5171 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5172 } else { 5173 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5174 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5175 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5176 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5177 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5178 } 5179 return 0; 5180 } 5181 5182 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5183 { 5184 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5185 5186 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5187 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5188 } 5189 5190 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5191 { 5192 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5193 udelay(50); 5194 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5195 udelay(50); 5196 } 5197 5198 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5199 bool enable) 5200 { 5201 uint32_t rlc_pg_cntl; 5202 5203 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5204 5205 if (!enable) { 5206 /* RLC_PG_CNTL[23] = 0 (default) 5207 * RLC will wait for handshake acks with SMU 5208 * GFXOFF will be enabled 5209 * RLC_PG_CNTL[23] = 1 5210 * RLC will not issue any message to SMU 5211 * hence no handshake between SMU & RLC 5212 * GFXOFF will be disabled 5213 */ 5214 rlc_pg_cntl |= 0x800000; 5215 } else 5216 rlc_pg_cntl &= ~0x800000; 5217 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5218 } 5219 5220 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5221 { 5222 /* TODO: enable rlc & smu handshake until smu 5223 * and gfxoff feature works as expected */ 5224 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5225 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5226 5227 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5228 udelay(50); 5229 } 5230 5231 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5232 { 5233 uint32_t tmp; 5234 5235 /* enable Save Restore Machine */ 5236 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5237 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5238 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5239 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5240 } 5241 5242 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5243 { 5244 const struct rlc_firmware_header_v2_0 *hdr; 5245 const __le32 *fw_data; 5246 unsigned i, fw_size; 5247 5248 if (!adev->gfx.rlc_fw) 5249 return -EINVAL; 5250 5251 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5252 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5253 5254 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5255 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5256 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5257 5258 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5259 RLCG_UCODE_LOADING_START_ADDRESS); 5260 5261 for (i = 0; i < fw_size; i++) 5262 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5263 le32_to_cpup(fw_data++)); 5264 5265 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5266 5267 return 0; 5268 } 5269 5270 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5271 { 5272 int r; 5273 5274 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5275 5276 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5277 if (r) 5278 return r; 5279 5280 gfx_v10_0_init_csb(adev); 5281 5282 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5283 gfx_v10_0_rlc_enable_srm(adev); 5284 } else { 5285 if (amdgpu_sriov_vf(adev)) { 5286 gfx_v10_0_init_csb(adev); 5287 return 0; 5288 } 5289 5290 adev->gfx.rlc.funcs->stop(adev); 5291 5292 /* disable CG */ 5293 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5294 5295 /* disable PG */ 5296 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5297 5298 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5299 /* legacy rlc firmware loading */ 5300 r = gfx_v10_0_rlc_load_microcode(adev); 5301 if (r) 5302 return r; 5303 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5304 /* rlc backdoor autoload firmware */ 5305 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5306 if (r) 5307 return r; 5308 } 5309 5310 gfx_v10_0_init_csb(adev); 5311 5312 adev->gfx.rlc.funcs->start(adev); 5313 5314 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5315 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5316 if (r) 5317 return r; 5318 } 5319 } 5320 return 0; 5321 } 5322 5323 static struct { 5324 FIRMWARE_ID id; 5325 unsigned int offset; 5326 unsigned int size; 5327 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5328 5329 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5330 { 5331 int ret; 5332 RLC_TABLE_OF_CONTENT *rlc_toc; 5333 5334 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5335 AMDGPU_GEM_DOMAIN_GTT, 5336 &adev->gfx.rlc.rlc_toc_bo, 5337 &adev->gfx.rlc.rlc_toc_gpu_addr, 5338 (void **)&adev->gfx.rlc.rlc_toc_buf); 5339 if (ret) { 5340 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5341 return ret; 5342 } 5343 5344 /* Copy toc from psp sos fw to rlc toc buffer */ 5345 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5346 5347 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5348 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5349 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5350 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5351 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5352 /* Offset needs 4KB alignment */ 5353 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5354 } 5355 5356 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5357 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5358 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5359 5360 rlc_toc++; 5361 } 5362 5363 return 0; 5364 } 5365 5366 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5367 { 5368 uint32_t total_size = 0; 5369 FIRMWARE_ID id; 5370 int ret; 5371 5372 ret = gfx_v10_0_parse_rlc_toc(adev); 5373 if (ret) { 5374 dev_err(adev->dev, "failed to parse rlc toc\n"); 5375 return 0; 5376 } 5377 5378 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5379 total_size += rlc_autoload_info[id].size; 5380 5381 /* In case the offset in rlc toc ucode is aligned */ 5382 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5383 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5384 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5385 5386 return total_size; 5387 } 5388 5389 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5390 { 5391 int r; 5392 uint32_t total_size; 5393 5394 total_size = gfx_v10_0_calc_toc_total_size(adev); 5395 5396 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5397 AMDGPU_GEM_DOMAIN_GTT, 5398 &adev->gfx.rlc.rlc_autoload_bo, 5399 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5400 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5401 if (r) { 5402 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5403 return r; 5404 } 5405 5406 return 0; 5407 } 5408 5409 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5410 { 5411 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5412 &adev->gfx.rlc.rlc_toc_gpu_addr, 5413 (void **)&adev->gfx.rlc.rlc_toc_buf); 5414 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5415 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5416 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5417 } 5418 5419 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5420 FIRMWARE_ID id, 5421 const void *fw_data, 5422 uint32_t fw_size) 5423 { 5424 uint32_t toc_offset; 5425 uint32_t toc_fw_size; 5426 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5427 5428 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5429 return; 5430 5431 toc_offset = rlc_autoload_info[id].offset; 5432 toc_fw_size = rlc_autoload_info[id].size; 5433 5434 if (fw_size == 0) 5435 fw_size = toc_fw_size; 5436 5437 if (fw_size > toc_fw_size) 5438 fw_size = toc_fw_size; 5439 5440 memcpy(ptr + toc_offset, fw_data, fw_size); 5441 5442 if (fw_size < toc_fw_size) 5443 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5444 } 5445 5446 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5447 { 5448 void *data; 5449 uint32_t size; 5450 5451 data = adev->gfx.rlc.rlc_toc_buf; 5452 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5453 5454 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5455 FIRMWARE_ID_RLC_TOC, 5456 data, size); 5457 } 5458 5459 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5460 { 5461 const __le32 *fw_data; 5462 uint32_t fw_size; 5463 const struct gfx_firmware_header_v1_0 *cp_hdr; 5464 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5465 5466 /* pfp ucode */ 5467 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5468 adev->gfx.pfp_fw->data; 5469 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5470 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5471 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5472 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5473 FIRMWARE_ID_CP_PFP, 5474 fw_data, fw_size); 5475 5476 /* ce ucode */ 5477 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5478 adev->gfx.ce_fw->data; 5479 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5480 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5481 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5482 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5483 FIRMWARE_ID_CP_CE, 5484 fw_data, fw_size); 5485 5486 /* me ucode */ 5487 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5488 adev->gfx.me_fw->data; 5489 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5490 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5491 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5492 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5493 FIRMWARE_ID_CP_ME, 5494 fw_data, fw_size); 5495 5496 /* rlc ucode */ 5497 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5498 adev->gfx.rlc_fw->data; 5499 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5500 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5501 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5502 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5503 FIRMWARE_ID_RLC_G_UCODE, 5504 fw_data, fw_size); 5505 5506 /* mec1 ucode */ 5507 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5508 adev->gfx.mec_fw->data; 5509 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5510 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5511 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5512 cp_hdr->jt_size * 4; 5513 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5514 FIRMWARE_ID_CP_MEC, 5515 fw_data, fw_size); 5516 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5517 } 5518 5519 /* Temporarily put sdma part here */ 5520 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5521 { 5522 const __le32 *fw_data; 5523 uint32_t fw_size; 5524 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5525 int i; 5526 5527 for (i = 0; i < adev->sdma.num_instances; i++) { 5528 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5529 adev->sdma.instance[i].fw->data; 5530 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5531 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5532 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5533 5534 if (i == 0) { 5535 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5536 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5537 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5538 FIRMWARE_ID_SDMA0_JT, 5539 (uint32_t *)fw_data + 5540 sdma_hdr->jt_offset, 5541 sdma_hdr->jt_size * 4); 5542 } else if (i == 1) { 5543 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5544 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5545 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5546 FIRMWARE_ID_SDMA1_JT, 5547 (uint32_t *)fw_data + 5548 sdma_hdr->jt_offset, 5549 sdma_hdr->jt_size * 4); 5550 } 5551 } 5552 } 5553 5554 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5555 { 5556 uint32_t rlc_g_offset, rlc_g_size, tmp; 5557 uint64_t gpu_addr; 5558 5559 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5560 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5561 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5562 5563 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5564 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5565 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5566 5567 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5568 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5569 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5570 5571 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5572 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5573 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5574 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5575 return -EINVAL; 5576 } 5577 5578 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5579 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5580 DRM_ERROR("RLC ROM should halt itself\n"); 5581 return -EINVAL; 5582 } 5583 5584 return 0; 5585 } 5586 5587 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5588 { 5589 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5590 uint32_t tmp; 5591 int i; 5592 uint64_t addr; 5593 5594 /* Trigger an invalidation of the L1 instruction caches */ 5595 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5596 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5597 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5598 5599 /* Wait for invalidation complete */ 5600 for (i = 0; i < usec_timeout; i++) { 5601 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5602 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5603 INVALIDATE_CACHE_COMPLETE)) 5604 break; 5605 udelay(1); 5606 } 5607 5608 if (i >= usec_timeout) { 5609 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5610 return -EINVAL; 5611 } 5612 5613 /* Program me ucode address into intruction cache address register */ 5614 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5615 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5616 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5617 lower_32_bits(addr) & 0xFFFFF000); 5618 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5619 upper_32_bits(addr)); 5620 5621 return 0; 5622 } 5623 5624 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5625 { 5626 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5627 uint32_t tmp; 5628 int i; 5629 uint64_t addr; 5630 5631 /* Trigger an invalidation of the L1 instruction caches */ 5632 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5633 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5634 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5635 5636 /* Wait for invalidation complete */ 5637 for (i = 0; i < usec_timeout; i++) { 5638 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5639 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5640 INVALIDATE_CACHE_COMPLETE)) 5641 break; 5642 udelay(1); 5643 } 5644 5645 if (i >= usec_timeout) { 5646 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5647 return -EINVAL; 5648 } 5649 5650 /* Program ce ucode address into intruction cache address register */ 5651 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5652 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5653 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5654 lower_32_bits(addr) & 0xFFFFF000); 5655 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5656 upper_32_bits(addr)); 5657 5658 return 0; 5659 } 5660 5661 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5662 { 5663 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5664 uint32_t tmp; 5665 int i; 5666 uint64_t addr; 5667 5668 /* Trigger an invalidation of the L1 instruction caches */ 5669 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5670 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5671 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5672 5673 /* Wait for invalidation complete */ 5674 for (i = 0; i < usec_timeout; i++) { 5675 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5676 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5677 INVALIDATE_CACHE_COMPLETE)) 5678 break; 5679 udelay(1); 5680 } 5681 5682 if (i >= usec_timeout) { 5683 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5684 return -EINVAL; 5685 } 5686 5687 /* Program pfp ucode address into intruction cache address register */ 5688 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5689 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5690 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5691 lower_32_bits(addr) & 0xFFFFF000); 5692 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5693 upper_32_bits(addr)); 5694 5695 return 0; 5696 } 5697 5698 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5699 { 5700 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5701 uint32_t tmp; 5702 int i; 5703 uint64_t addr; 5704 5705 /* Trigger an invalidation of the L1 instruction caches */ 5706 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5707 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5708 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5709 5710 /* Wait for invalidation complete */ 5711 for (i = 0; i < usec_timeout; i++) { 5712 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5713 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5714 INVALIDATE_CACHE_COMPLETE)) 5715 break; 5716 udelay(1); 5717 } 5718 5719 if (i >= usec_timeout) { 5720 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5721 return -EINVAL; 5722 } 5723 5724 /* Program mec1 ucode address into intruction cache address register */ 5725 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5726 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5727 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5728 lower_32_bits(addr) & 0xFFFFF000); 5729 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5730 upper_32_bits(addr)); 5731 5732 return 0; 5733 } 5734 5735 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5736 { 5737 uint32_t cp_status; 5738 uint32_t bootload_status; 5739 int i, r; 5740 5741 for (i = 0; i < adev->usec_timeout; i++) { 5742 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5743 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5744 if ((cp_status == 0) && 5745 (REG_GET_FIELD(bootload_status, 5746 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5747 break; 5748 } 5749 udelay(1); 5750 } 5751 5752 if (i >= adev->usec_timeout) { 5753 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5754 return -ETIMEDOUT; 5755 } 5756 5757 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5758 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5759 if (r) 5760 return r; 5761 5762 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5763 if (r) 5764 return r; 5765 5766 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5767 if (r) 5768 return r; 5769 5770 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5771 if (r) 5772 return r; 5773 } 5774 5775 return 0; 5776 } 5777 5778 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5779 { 5780 int i; 5781 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5782 5783 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5784 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5785 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5786 5787 if (adev->asic_type == CHIP_NAVI12) { 5788 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5789 } else { 5790 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5791 } 5792 5793 for (i = 0; i < adev->usec_timeout; i++) { 5794 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5795 break; 5796 udelay(1); 5797 } 5798 5799 if (i >= adev->usec_timeout) 5800 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5801 5802 return 0; 5803 } 5804 5805 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5806 { 5807 int r; 5808 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5809 const __le32 *fw_data; 5810 unsigned i, fw_size; 5811 uint32_t tmp; 5812 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5813 5814 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5815 adev->gfx.pfp_fw->data; 5816 5817 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5818 5819 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5820 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5821 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5822 5823 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5824 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5825 &adev->gfx.pfp.pfp_fw_obj, 5826 &adev->gfx.pfp.pfp_fw_gpu_addr, 5827 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5828 if (r) { 5829 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5830 gfx_v10_0_pfp_fini(adev); 5831 return r; 5832 } 5833 5834 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5835 5836 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5837 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5838 5839 /* Trigger an invalidation of the L1 instruction caches */ 5840 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5841 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5842 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5843 5844 /* Wait for invalidation complete */ 5845 for (i = 0; i < usec_timeout; i++) { 5846 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5847 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5848 INVALIDATE_CACHE_COMPLETE)) 5849 break; 5850 udelay(1); 5851 } 5852 5853 if (i >= usec_timeout) { 5854 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5855 return -EINVAL; 5856 } 5857 5858 if (amdgpu_emu_mode == 1) 5859 adev->hdp.funcs->flush_hdp(adev, NULL); 5860 5861 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5862 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5863 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5864 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5865 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5866 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5867 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5868 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5869 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5870 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5871 5872 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5873 5874 for (i = 0; i < pfp_hdr->jt_size; i++) 5875 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5876 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5877 5878 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5879 5880 return 0; 5881 } 5882 5883 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5884 { 5885 int r; 5886 const struct gfx_firmware_header_v1_0 *ce_hdr; 5887 const __le32 *fw_data; 5888 unsigned i, fw_size; 5889 uint32_t tmp; 5890 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5891 5892 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5893 adev->gfx.ce_fw->data; 5894 5895 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5896 5897 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5898 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5899 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5900 5901 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5902 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5903 &adev->gfx.ce.ce_fw_obj, 5904 &adev->gfx.ce.ce_fw_gpu_addr, 5905 (void **)&adev->gfx.ce.ce_fw_ptr); 5906 if (r) { 5907 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5908 gfx_v10_0_ce_fini(adev); 5909 return r; 5910 } 5911 5912 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5913 5914 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5915 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5916 5917 /* Trigger an invalidation of the L1 instruction caches */ 5918 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5919 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5920 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5921 5922 /* Wait for invalidation complete */ 5923 for (i = 0; i < usec_timeout; i++) { 5924 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5925 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5926 INVALIDATE_CACHE_COMPLETE)) 5927 break; 5928 udelay(1); 5929 } 5930 5931 if (i >= usec_timeout) { 5932 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5933 return -EINVAL; 5934 } 5935 5936 if (amdgpu_emu_mode == 1) 5937 adev->hdp.funcs->flush_hdp(adev, NULL); 5938 5939 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5940 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5941 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5942 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5943 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5944 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5945 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5946 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5947 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5948 5949 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5950 5951 for (i = 0; i < ce_hdr->jt_size; i++) 5952 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5953 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5954 5955 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5956 5957 return 0; 5958 } 5959 5960 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5961 { 5962 int r; 5963 const struct gfx_firmware_header_v1_0 *me_hdr; 5964 const __le32 *fw_data; 5965 unsigned i, fw_size; 5966 uint32_t tmp; 5967 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5968 5969 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5970 adev->gfx.me_fw->data; 5971 5972 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5973 5974 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5975 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5976 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5977 5978 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5979 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5980 &adev->gfx.me.me_fw_obj, 5981 &adev->gfx.me.me_fw_gpu_addr, 5982 (void **)&adev->gfx.me.me_fw_ptr); 5983 if (r) { 5984 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5985 gfx_v10_0_me_fini(adev); 5986 return r; 5987 } 5988 5989 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5990 5991 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5992 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5993 5994 /* Trigger an invalidation of the L1 instruction caches */ 5995 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5996 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5997 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5998 5999 /* Wait for invalidation complete */ 6000 for (i = 0; i < usec_timeout; i++) { 6001 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6002 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6003 INVALIDATE_CACHE_COMPLETE)) 6004 break; 6005 udelay(1); 6006 } 6007 6008 if (i >= usec_timeout) { 6009 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6010 return -EINVAL; 6011 } 6012 6013 if (amdgpu_emu_mode == 1) 6014 adev->hdp.funcs->flush_hdp(adev, NULL); 6015 6016 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6017 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6018 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6019 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6020 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6021 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6022 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6023 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6024 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6025 6026 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6027 6028 for (i = 0; i < me_hdr->jt_size; i++) 6029 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6030 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6031 6032 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6033 6034 return 0; 6035 } 6036 6037 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6038 { 6039 int r; 6040 6041 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6042 return -EINVAL; 6043 6044 gfx_v10_0_cp_gfx_enable(adev, false); 6045 6046 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6047 if (r) { 6048 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6049 return r; 6050 } 6051 6052 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6053 if (r) { 6054 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6055 return r; 6056 } 6057 6058 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6059 if (r) { 6060 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6061 return r; 6062 } 6063 6064 return 0; 6065 } 6066 6067 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6068 { 6069 struct amdgpu_ring *ring; 6070 const struct cs_section_def *sect = NULL; 6071 const struct cs_extent_def *ext = NULL; 6072 int r, i; 6073 int ctx_reg_offset; 6074 6075 /* init the CP */ 6076 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6077 adev->gfx.config.max_hw_contexts - 1); 6078 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6079 6080 gfx_v10_0_cp_gfx_enable(adev, true); 6081 6082 ring = &adev->gfx.gfx_ring[0]; 6083 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6084 if (r) { 6085 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6086 return r; 6087 } 6088 6089 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6090 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6091 6092 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6093 amdgpu_ring_write(ring, 0x80000000); 6094 amdgpu_ring_write(ring, 0x80000000); 6095 6096 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6097 for (ext = sect->section; ext->extent != NULL; ++ext) { 6098 if (sect->id == SECT_CONTEXT) { 6099 amdgpu_ring_write(ring, 6100 PACKET3(PACKET3_SET_CONTEXT_REG, 6101 ext->reg_count)); 6102 amdgpu_ring_write(ring, ext->reg_index - 6103 PACKET3_SET_CONTEXT_REG_START); 6104 for (i = 0; i < ext->reg_count; i++) 6105 amdgpu_ring_write(ring, ext->extent[i]); 6106 } 6107 } 6108 } 6109 6110 ctx_reg_offset = 6111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6112 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6113 amdgpu_ring_write(ring, ctx_reg_offset); 6114 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6115 6116 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6117 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6118 6119 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6120 amdgpu_ring_write(ring, 0); 6121 6122 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6123 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6124 amdgpu_ring_write(ring, 0x8000); 6125 amdgpu_ring_write(ring, 0x8000); 6126 6127 amdgpu_ring_commit(ring); 6128 6129 /* submit cs packet to copy state 0 to next available state */ 6130 if (adev->gfx.num_gfx_rings > 1) { 6131 /* maximum supported gfx ring is 2 */ 6132 ring = &adev->gfx.gfx_ring[1]; 6133 r = amdgpu_ring_alloc(ring, 2); 6134 if (r) { 6135 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6136 return r; 6137 } 6138 6139 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6140 amdgpu_ring_write(ring, 0); 6141 6142 amdgpu_ring_commit(ring); 6143 } 6144 return 0; 6145 } 6146 6147 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6148 CP_PIPE_ID pipe) 6149 { 6150 u32 tmp; 6151 6152 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6153 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6154 6155 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6156 } 6157 6158 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6159 struct amdgpu_ring *ring) 6160 { 6161 u32 tmp; 6162 6163 if (!amdgpu_async_gfx_ring) { 6164 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6165 if (ring->use_doorbell) { 6166 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6167 DOORBELL_OFFSET, ring->doorbell_index); 6168 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6169 DOORBELL_EN, 1); 6170 } else { 6171 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6172 DOORBELL_EN, 0); 6173 } 6174 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6175 } 6176 switch (adev->asic_type) { 6177 case CHIP_SIENNA_CICHLID: 6178 case CHIP_NAVY_FLOUNDER: 6179 case CHIP_VANGOGH: 6180 case CHIP_DIMGREY_CAVEFISH: 6181 case CHIP_BEIGE_GOBY: 6182 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6183 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6184 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6185 6186 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6187 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6188 break; 6189 default: 6190 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6191 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6192 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6193 6194 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6195 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6196 break; 6197 } 6198 } 6199 6200 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6201 { 6202 struct amdgpu_ring *ring; 6203 u32 tmp; 6204 u32 rb_bufsz; 6205 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6206 u32 i; 6207 6208 /* Set the write pointer delay */ 6209 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6210 6211 /* set the RB to use vmid 0 */ 6212 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6213 6214 /* Init gfx ring 0 for pipe 0 */ 6215 mutex_lock(&adev->srbm_mutex); 6216 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6217 6218 /* Set ring buffer size */ 6219 ring = &adev->gfx.gfx_ring[0]; 6220 rb_bufsz = order_base_2(ring->ring_size / 8); 6221 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6222 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6223 #ifdef __BIG_ENDIAN 6224 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6225 #endif 6226 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6227 6228 /* Initialize the ring buffer's write pointers */ 6229 ring->wptr = 0; 6230 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6231 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6232 6233 /* set the wb address wether it's enabled or not */ 6234 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6235 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6236 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6237 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6238 6239 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6240 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6241 lower_32_bits(wptr_gpu_addr)); 6242 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6243 upper_32_bits(wptr_gpu_addr)); 6244 6245 mdelay(1); 6246 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6247 6248 rb_addr = ring->gpu_addr >> 8; 6249 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6250 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6251 6252 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6253 6254 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6255 mutex_unlock(&adev->srbm_mutex); 6256 6257 /* Init gfx ring 1 for pipe 1 */ 6258 if (adev->gfx.num_gfx_rings > 1) { 6259 mutex_lock(&adev->srbm_mutex); 6260 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6261 /* maximum supported gfx ring is 2 */ 6262 ring = &adev->gfx.gfx_ring[1]; 6263 rb_bufsz = order_base_2(ring->ring_size / 8); 6264 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6265 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6266 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6267 /* Initialize the ring buffer's write pointers */ 6268 ring->wptr = 0; 6269 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6270 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6271 /* Set the wb address wether it's enabled or not */ 6272 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6273 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6274 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6275 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6276 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6277 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6278 lower_32_bits(wptr_gpu_addr)); 6279 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6280 upper_32_bits(wptr_gpu_addr)); 6281 6282 mdelay(1); 6283 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6284 6285 rb_addr = ring->gpu_addr >> 8; 6286 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6287 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6288 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6289 6290 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6291 mutex_unlock(&adev->srbm_mutex); 6292 } 6293 /* Switch to pipe 0 */ 6294 mutex_lock(&adev->srbm_mutex); 6295 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6296 mutex_unlock(&adev->srbm_mutex); 6297 6298 /* start the ring */ 6299 gfx_v10_0_cp_gfx_start(adev); 6300 6301 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6302 ring = &adev->gfx.gfx_ring[i]; 6303 ring->sched.ready = true; 6304 } 6305 6306 return 0; 6307 } 6308 6309 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6310 { 6311 if (enable) { 6312 switch (adev->asic_type) { 6313 case CHIP_SIENNA_CICHLID: 6314 case CHIP_NAVY_FLOUNDER: 6315 case CHIP_VANGOGH: 6316 case CHIP_DIMGREY_CAVEFISH: 6317 case CHIP_BEIGE_GOBY: 6318 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6319 break; 6320 default: 6321 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6322 break; 6323 } 6324 } else { 6325 switch (adev->asic_type) { 6326 case CHIP_SIENNA_CICHLID: 6327 case CHIP_NAVY_FLOUNDER: 6328 case CHIP_VANGOGH: 6329 case CHIP_DIMGREY_CAVEFISH: 6330 case CHIP_BEIGE_GOBY: 6331 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6332 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6333 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6334 break; 6335 default: 6336 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6337 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6338 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6339 break; 6340 } 6341 adev->gfx.kiq.ring.sched.ready = false; 6342 } 6343 udelay(50); 6344 } 6345 6346 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6347 { 6348 const struct gfx_firmware_header_v1_0 *mec_hdr; 6349 const __le32 *fw_data; 6350 unsigned i; 6351 u32 tmp; 6352 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6353 6354 if (!adev->gfx.mec_fw) 6355 return -EINVAL; 6356 6357 gfx_v10_0_cp_compute_enable(adev, false); 6358 6359 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6360 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6361 6362 fw_data = (const __le32 *) 6363 (adev->gfx.mec_fw->data + 6364 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6365 6366 /* Trigger an invalidation of the L1 instruction caches */ 6367 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6368 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6369 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6370 6371 /* Wait for invalidation complete */ 6372 for (i = 0; i < usec_timeout; i++) { 6373 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6374 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6375 INVALIDATE_CACHE_COMPLETE)) 6376 break; 6377 udelay(1); 6378 } 6379 6380 if (i >= usec_timeout) { 6381 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6382 return -EINVAL; 6383 } 6384 6385 if (amdgpu_emu_mode == 1) 6386 adev->hdp.funcs->flush_hdp(adev, NULL); 6387 6388 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6389 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6390 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6391 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6392 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6393 6394 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6395 0xFFFFF000); 6396 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6397 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6398 6399 /* MEC1 */ 6400 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6401 6402 for (i = 0; i < mec_hdr->jt_size; i++) 6403 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6404 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6405 6406 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6407 6408 /* 6409 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6410 * different microcode than MEC1. 6411 */ 6412 6413 return 0; 6414 } 6415 6416 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6417 { 6418 uint32_t tmp; 6419 struct amdgpu_device *adev = ring->adev; 6420 6421 /* tell RLC which is KIQ queue */ 6422 switch (adev->asic_type) { 6423 case CHIP_SIENNA_CICHLID: 6424 case CHIP_NAVY_FLOUNDER: 6425 case CHIP_VANGOGH: 6426 case CHIP_DIMGREY_CAVEFISH: 6427 case CHIP_BEIGE_GOBY: 6428 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6429 tmp &= 0xffffff00; 6430 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6431 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6432 tmp |= 0x80; 6433 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6434 break; 6435 default: 6436 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6437 tmp &= 0xffffff00; 6438 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6439 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6440 tmp |= 0x80; 6441 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6442 break; 6443 } 6444 } 6445 6446 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6447 { 6448 struct amdgpu_device *adev = ring->adev; 6449 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6450 uint64_t hqd_gpu_addr, wb_gpu_addr; 6451 uint32_t tmp; 6452 uint32_t rb_bufsz; 6453 6454 /* set up gfx hqd wptr */ 6455 mqd->cp_gfx_hqd_wptr = 0; 6456 mqd->cp_gfx_hqd_wptr_hi = 0; 6457 6458 /* set the pointer to the MQD */ 6459 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6460 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6461 6462 /* set up mqd control */ 6463 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6464 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6465 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6466 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6467 mqd->cp_gfx_mqd_control = tmp; 6468 6469 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6470 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6471 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6472 mqd->cp_gfx_hqd_vmid = 0; 6473 6474 /* set up default queue priority level 6475 * 0x0 = low priority, 0x1 = high priority */ 6476 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6477 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6478 mqd->cp_gfx_hqd_queue_priority = tmp; 6479 6480 /* set up time quantum */ 6481 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6482 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6483 mqd->cp_gfx_hqd_quantum = tmp; 6484 6485 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6486 hqd_gpu_addr = ring->gpu_addr >> 8; 6487 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6488 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6489 6490 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6491 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6492 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6493 mqd->cp_gfx_hqd_rptr_addr_hi = 6494 upper_32_bits(wb_gpu_addr) & 0xffff; 6495 6496 /* set up rb_wptr_poll addr */ 6497 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6498 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6499 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6500 6501 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6502 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6503 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6504 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6505 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6506 #ifdef __BIG_ENDIAN 6507 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6508 #endif 6509 mqd->cp_gfx_hqd_cntl = tmp; 6510 6511 /* set up cp_doorbell_control */ 6512 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6513 if (ring->use_doorbell) { 6514 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6515 DOORBELL_OFFSET, ring->doorbell_index); 6516 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6517 DOORBELL_EN, 1); 6518 } else 6519 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6520 DOORBELL_EN, 0); 6521 mqd->cp_rb_doorbell_control = tmp; 6522 6523 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6524 *otherwise the range of the second ring will override the first ring */ 6525 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6526 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6527 6528 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6529 ring->wptr = 0; 6530 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6531 6532 /* active the queue */ 6533 mqd->cp_gfx_hqd_active = 1; 6534 6535 return 0; 6536 } 6537 6538 #ifdef BRING_UP_DEBUG 6539 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6540 { 6541 struct amdgpu_device *adev = ring->adev; 6542 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6543 6544 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6545 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6546 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6547 6548 /* set GFX_MQD_BASE */ 6549 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6550 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6551 6552 /* set GFX_MQD_CONTROL */ 6553 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6554 6555 /* set GFX_HQD_VMID to 0 */ 6556 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6557 6558 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6559 mqd->cp_gfx_hqd_queue_priority); 6560 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6561 6562 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6563 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6564 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6565 6566 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6567 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6568 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6569 6570 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6571 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6572 6573 /* set RB_WPTR_POLL_ADDR */ 6574 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6575 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6576 6577 /* set RB_DOORBELL_CONTROL */ 6578 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6579 6580 /* active the queue */ 6581 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6582 6583 return 0; 6584 } 6585 #endif 6586 6587 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6588 { 6589 struct amdgpu_device *adev = ring->adev; 6590 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6591 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6592 6593 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6594 memset((void *)mqd, 0, sizeof(*mqd)); 6595 mutex_lock(&adev->srbm_mutex); 6596 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6597 gfx_v10_0_gfx_mqd_init(ring); 6598 #ifdef BRING_UP_DEBUG 6599 gfx_v10_0_gfx_queue_init_register(ring); 6600 #endif 6601 nv_grbm_select(adev, 0, 0, 0, 0); 6602 mutex_unlock(&adev->srbm_mutex); 6603 if (adev->gfx.me.mqd_backup[mqd_idx]) 6604 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6605 } else if (amdgpu_in_reset(adev)) { 6606 /* reset mqd with the backup copy */ 6607 if (adev->gfx.me.mqd_backup[mqd_idx]) 6608 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6609 /* reset the ring */ 6610 ring->wptr = 0; 6611 adev->wb.wb[ring->wptr_offs] = 0; 6612 amdgpu_ring_clear_ring(ring); 6613 #ifdef BRING_UP_DEBUG 6614 mutex_lock(&adev->srbm_mutex); 6615 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6616 gfx_v10_0_gfx_queue_init_register(ring); 6617 nv_grbm_select(adev, 0, 0, 0, 0); 6618 mutex_unlock(&adev->srbm_mutex); 6619 #endif 6620 } else { 6621 amdgpu_ring_clear_ring(ring); 6622 } 6623 6624 return 0; 6625 } 6626 6627 #ifndef BRING_UP_DEBUG 6628 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6629 { 6630 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6631 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6632 int r, i; 6633 6634 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6635 return -EINVAL; 6636 6637 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6638 adev->gfx.num_gfx_rings); 6639 if (r) { 6640 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6641 return r; 6642 } 6643 6644 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6645 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6646 6647 return amdgpu_ring_test_helper(kiq_ring); 6648 } 6649 #endif 6650 6651 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6652 { 6653 int r, i; 6654 struct amdgpu_ring *ring; 6655 6656 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6657 ring = &adev->gfx.gfx_ring[i]; 6658 6659 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6660 if (unlikely(r != 0)) 6661 goto done; 6662 6663 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6664 if (!r) { 6665 r = gfx_v10_0_gfx_init_queue(ring); 6666 amdgpu_bo_kunmap(ring->mqd_obj); 6667 ring->mqd_ptr = NULL; 6668 } 6669 amdgpu_bo_unreserve(ring->mqd_obj); 6670 if (r) 6671 goto done; 6672 } 6673 #ifndef BRING_UP_DEBUG 6674 r = gfx_v10_0_kiq_enable_kgq(adev); 6675 if (r) 6676 goto done; 6677 #endif 6678 r = gfx_v10_0_cp_gfx_start(adev); 6679 if (r) 6680 goto done; 6681 6682 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6683 ring = &adev->gfx.gfx_ring[i]; 6684 ring->sched.ready = true; 6685 } 6686 done: 6687 return r; 6688 } 6689 6690 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6691 { 6692 struct amdgpu_device *adev = ring->adev; 6693 6694 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6695 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 6696 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6697 mqd->cp_hqd_queue_priority = 6698 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6699 } 6700 } 6701 } 6702 6703 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6704 { 6705 struct amdgpu_device *adev = ring->adev; 6706 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6707 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6708 uint32_t tmp; 6709 6710 mqd->header = 0xC0310800; 6711 mqd->compute_pipelinestat_enable = 0x00000001; 6712 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6713 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6714 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6715 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6716 mqd->compute_misc_reserved = 0x00000003; 6717 6718 eop_base_addr = ring->eop_gpu_addr >> 8; 6719 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6720 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6721 6722 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6723 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6724 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6725 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6726 6727 mqd->cp_hqd_eop_control = tmp; 6728 6729 /* enable doorbell? */ 6730 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6731 6732 if (ring->use_doorbell) { 6733 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6734 DOORBELL_OFFSET, ring->doorbell_index); 6735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6736 DOORBELL_EN, 1); 6737 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6738 DOORBELL_SOURCE, 0); 6739 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6740 DOORBELL_HIT, 0); 6741 } else { 6742 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6743 DOORBELL_EN, 0); 6744 } 6745 6746 mqd->cp_hqd_pq_doorbell_control = tmp; 6747 6748 /* disable the queue if it's active */ 6749 ring->wptr = 0; 6750 mqd->cp_hqd_dequeue_request = 0; 6751 mqd->cp_hqd_pq_rptr = 0; 6752 mqd->cp_hqd_pq_wptr_lo = 0; 6753 mqd->cp_hqd_pq_wptr_hi = 0; 6754 6755 /* set the pointer to the MQD */ 6756 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6757 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6758 6759 /* set MQD vmid to 0 */ 6760 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6761 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6762 mqd->cp_mqd_control = tmp; 6763 6764 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6765 hqd_gpu_addr = ring->gpu_addr >> 8; 6766 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6767 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6768 6769 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6770 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6771 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6772 (order_base_2(ring->ring_size / 4) - 1)); 6773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6774 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6775 #ifdef __BIG_ENDIAN 6776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6777 #endif 6778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6782 mqd->cp_hqd_pq_control = tmp; 6783 6784 /* set the wb address whether it's enabled or not */ 6785 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6786 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6787 mqd->cp_hqd_pq_rptr_report_addr_hi = 6788 upper_32_bits(wb_gpu_addr) & 0xffff; 6789 6790 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6791 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6792 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6793 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6794 6795 tmp = 0; 6796 /* enable the doorbell if requested */ 6797 if (ring->use_doorbell) { 6798 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6800 DOORBELL_OFFSET, ring->doorbell_index); 6801 6802 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6803 DOORBELL_EN, 1); 6804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6805 DOORBELL_SOURCE, 0); 6806 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6807 DOORBELL_HIT, 0); 6808 } 6809 6810 mqd->cp_hqd_pq_doorbell_control = tmp; 6811 6812 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6813 ring->wptr = 0; 6814 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6815 6816 /* set the vmid for the queue */ 6817 mqd->cp_hqd_vmid = 0; 6818 6819 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6820 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6821 mqd->cp_hqd_persistent_state = tmp; 6822 6823 /* set MIN_IB_AVAIL_SIZE */ 6824 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6825 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6826 mqd->cp_hqd_ib_control = tmp; 6827 6828 /* set static priority for a compute queue/ring */ 6829 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6830 6831 /* map_queues packet doesn't need activate the queue, 6832 * so only kiq need set this field. 6833 */ 6834 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6835 mqd->cp_hqd_active = 1; 6836 6837 return 0; 6838 } 6839 6840 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6841 { 6842 struct amdgpu_device *adev = ring->adev; 6843 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6844 int j; 6845 6846 /* inactivate the queue */ 6847 if (amdgpu_sriov_vf(adev)) 6848 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6849 6850 /* disable wptr polling */ 6851 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6852 6853 /* write the EOP addr */ 6854 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6855 mqd->cp_hqd_eop_base_addr_lo); 6856 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6857 mqd->cp_hqd_eop_base_addr_hi); 6858 6859 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6860 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6861 mqd->cp_hqd_eop_control); 6862 6863 /* enable doorbell? */ 6864 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6865 mqd->cp_hqd_pq_doorbell_control); 6866 6867 /* disable the queue if it's active */ 6868 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6869 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6870 for (j = 0; j < adev->usec_timeout; j++) { 6871 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6872 break; 6873 udelay(1); 6874 } 6875 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6876 mqd->cp_hqd_dequeue_request); 6877 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6878 mqd->cp_hqd_pq_rptr); 6879 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6880 mqd->cp_hqd_pq_wptr_lo); 6881 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6882 mqd->cp_hqd_pq_wptr_hi); 6883 } 6884 6885 /* set the pointer to the MQD */ 6886 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6887 mqd->cp_mqd_base_addr_lo); 6888 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6889 mqd->cp_mqd_base_addr_hi); 6890 6891 /* set MQD vmid to 0 */ 6892 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6893 mqd->cp_mqd_control); 6894 6895 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6896 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6897 mqd->cp_hqd_pq_base_lo); 6898 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6899 mqd->cp_hqd_pq_base_hi); 6900 6901 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6902 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6903 mqd->cp_hqd_pq_control); 6904 6905 /* set the wb address whether it's enabled or not */ 6906 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6907 mqd->cp_hqd_pq_rptr_report_addr_lo); 6908 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6909 mqd->cp_hqd_pq_rptr_report_addr_hi); 6910 6911 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6912 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6913 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6914 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6915 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6916 6917 /* enable the doorbell if requested */ 6918 if (ring->use_doorbell) { 6919 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6920 (adev->doorbell_index.kiq * 2) << 2); 6921 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6922 (adev->doorbell_index.userqueue_end * 2) << 2); 6923 } 6924 6925 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6926 mqd->cp_hqd_pq_doorbell_control); 6927 6928 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6929 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6930 mqd->cp_hqd_pq_wptr_lo); 6931 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6932 mqd->cp_hqd_pq_wptr_hi); 6933 6934 /* set the vmid for the queue */ 6935 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6936 6937 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6938 mqd->cp_hqd_persistent_state); 6939 6940 /* activate the queue */ 6941 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6942 mqd->cp_hqd_active); 6943 6944 if (ring->use_doorbell) 6945 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6946 6947 return 0; 6948 } 6949 6950 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6951 { 6952 struct amdgpu_device *adev = ring->adev; 6953 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6954 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6955 6956 gfx_v10_0_kiq_setting(ring); 6957 6958 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6959 /* reset MQD to a clean status */ 6960 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6961 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6962 6963 /* reset ring buffer */ 6964 ring->wptr = 0; 6965 amdgpu_ring_clear_ring(ring); 6966 6967 mutex_lock(&adev->srbm_mutex); 6968 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6969 gfx_v10_0_kiq_init_register(ring); 6970 nv_grbm_select(adev, 0, 0, 0, 0); 6971 mutex_unlock(&adev->srbm_mutex); 6972 } else { 6973 memset((void *)mqd, 0, sizeof(*mqd)); 6974 mutex_lock(&adev->srbm_mutex); 6975 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6976 gfx_v10_0_compute_mqd_init(ring); 6977 gfx_v10_0_kiq_init_register(ring); 6978 nv_grbm_select(adev, 0, 0, 0, 0); 6979 mutex_unlock(&adev->srbm_mutex); 6980 6981 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6982 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6983 } 6984 6985 return 0; 6986 } 6987 6988 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6989 { 6990 struct amdgpu_device *adev = ring->adev; 6991 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6992 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6993 6994 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6995 memset((void *)mqd, 0, sizeof(*mqd)); 6996 mutex_lock(&adev->srbm_mutex); 6997 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6998 gfx_v10_0_compute_mqd_init(ring); 6999 nv_grbm_select(adev, 0, 0, 0, 0); 7000 mutex_unlock(&adev->srbm_mutex); 7001 7002 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7003 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7004 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7005 /* reset MQD to a clean status */ 7006 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7007 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7008 7009 /* reset ring buffer */ 7010 ring->wptr = 0; 7011 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 7012 amdgpu_ring_clear_ring(ring); 7013 } else { 7014 amdgpu_ring_clear_ring(ring); 7015 } 7016 7017 return 0; 7018 } 7019 7020 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7021 { 7022 struct amdgpu_ring *ring; 7023 int r; 7024 7025 ring = &adev->gfx.kiq.ring; 7026 7027 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7028 if (unlikely(r != 0)) 7029 return r; 7030 7031 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7032 if (unlikely(r != 0)) 7033 return r; 7034 7035 gfx_v10_0_kiq_init_queue(ring); 7036 amdgpu_bo_kunmap(ring->mqd_obj); 7037 ring->mqd_ptr = NULL; 7038 amdgpu_bo_unreserve(ring->mqd_obj); 7039 ring->sched.ready = true; 7040 return 0; 7041 } 7042 7043 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7044 { 7045 struct amdgpu_ring *ring = NULL; 7046 int r = 0, i; 7047 7048 gfx_v10_0_cp_compute_enable(adev, true); 7049 7050 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7051 ring = &adev->gfx.compute_ring[i]; 7052 7053 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7054 if (unlikely(r != 0)) 7055 goto done; 7056 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7057 if (!r) { 7058 r = gfx_v10_0_kcq_init_queue(ring); 7059 amdgpu_bo_kunmap(ring->mqd_obj); 7060 ring->mqd_ptr = NULL; 7061 } 7062 amdgpu_bo_unreserve(ring->mqd_obj); 7063 if (r) 7064 goto done; 7065 } 7066 7067 r = amdgpu_gfx_enable_kcq(adev); 7068 done: 7069 return r; 7070 } 7071 7072 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7073 { 7074 int r, i; 7075 struct amdgpu_ring *ring; 7076 7077 if (!(adev->flags & AMD_IS_APU)) 7078 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7079 7080 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7081 /* legacy firmware loading */ 7082 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7083 if (r) 7084 return r; 7085 7086 r = gfx_v10_0_cp_compute_load_microcode(adev); 7087 if (r) 7088 return r; 7089 } 7090 7091 r = gfx_v10_0_kiq_resume(adev); 7092 if (r) 7093 return r; 7094 7095 r = gfx_v10_0_kcq_resume(adev); 7096 if (r) 7097 return r; 7098 7099 if (!amdgpu_async_gfx_ring) { 7100 r = gfx_v10_0_cp_gfx_resume(adev); 7101 if (r) 7102 return r; 7103 } else { 7104 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7105 if (r) 7106 return r; 7107 } 7108 7109 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7110 ring = &adev->gfx.gfx_ring[i]; 7111 r = amdgpu_ring_test_helper(ring); 7112 if (r) 7113 return r; 7114 } 7115 7116 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7117 ring = &adev->gfx.compute_ring[i]; 7118 r = amdgpu_ring_test_helper(ring); 7119 if (r) 7120 return r; 7121 } 7122 7123 return 0; 7124 } 7125 7126 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7127 { 7128 gfx_v10_0_cp_gfx_enable(adev, enable); 7129 gfx_v10_0_cp_compute_enable(adev, enable); 7130 } 7131 7132 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7133 { 7134 uint32_t data, pattern = 0xDEADBEEF; 7135 7136 /* check if mmVGT_ESGS_RING_SIZE_UMD 7137 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7138 switch (adev->asic_type) { 7139 case CHIP_SIENNA_CICHLID: 7140 case CHIP_NAVY_FLOUNDER: 7141 case CHIP_DIMGREY_CAVEFISH: 7142 case CHIP_BEIGE_GOBY: 7143 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7144 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7145 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7146 7147 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7148 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7149 return true; 7150 } else { 7151 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7152 return false; 7153 } 7154 break; 7155 case CHIP_VANGOGH: 7156 return true; 7157 default: 7158 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7159 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7160 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7161 7162 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7163 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7164 return true; 7165 } else { 7166 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7167 return false; 7168 } 7169 break; 7170 } 7171 } 7172 7173 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7174 { 7175 uint32_t data; 7176 7177 if (amdgpu_sriov_vf(adev)) 7178 return; 7179 7180 /* initialize cam_index to 0 7181 * index will auto-inc after each data writting */ 7182 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7183 7184 switch (adev->asic_type) { 7185 case CHIP_SIENNA_CICHLID: 7186 case CHIP_NAVY_FLOUNDER: 7187 case CHIP_VANGOGH: 7188 case CHIP_DIMGREY_CAVEFISH: 7189 case CHIP_BEIGE_GOBY: 7190 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7191 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7192 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7193 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7194 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7195 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7196 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7197 7198 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7199 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7200 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7201 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7202 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7203 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7204 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7205 7206 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7207 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7208 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7209 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7210 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7211 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7212 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7213 7214 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7215 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7216 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7217 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7218 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7219 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7220 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7221 7222 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7223 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7224 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7225 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7226 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7227 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7228 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7229 7230 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7231 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7232 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7233 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7234 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7235 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7236 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7237 7238 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7239 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7240 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7241 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7242 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7243 break; 7244 default: 7245 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7246 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7247 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7248 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7249 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7250 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7251 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7252 7253 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7254 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7255 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7256 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7257 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7258 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7259 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7260 7261 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7262 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7263 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7264 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7265 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7266 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7267 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7268 7269 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7270 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7271 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7272 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7273 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7274 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7275 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7276 7277 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7278 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7279 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7280 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7281 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7282 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7283 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7284 7285 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7286 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7287 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7288 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7289 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7290 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7291 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7292 7293 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7294 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7295 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7296 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7297 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7298 break; 7299 } 7300 7301 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7302 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7303 } 7304 7305 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7306 { 7307 uint32_t data; 7308 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7309 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7310 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7311 7312 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7313 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7314 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7315 } 7316 7317 static int gfx_v10_0_hw_init(void *handle) 7318 { 7319 int r; 7320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7321 7322 if (!amdgpu_emu_mode) 7323 gfx_v10_0_init_golden_registers(adev); 7324 7325 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7326 /** 7327 * For gfx 10, rlc firmware loading relies on smu firmware is 7328 * loaded firstly, so in direct type, it has to load smc ucode 7329 * here before rlc. 7330 */ 7331 if (!(adev->flags & AMD_IS_APU)) { 7332 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7333 if (r) 7334 return r; 7335 } 7336 gfx_v10_0_disable_gpa_mode(adev); 7337 } 7338 7339 /* if GRBM CAM not remapped, set up the remapping */ 7340 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7341 gfx_v10_0_setup_grbm_cam_remapping(adev); 7342 7343 gfx_v10_0_constants_init(adev); 7344 7345 r = gfx_v10_0_rlc_resume(adev); 7346 if (r) 7347 return r; 7348 7349 /* 7350 * init golden registers and rlc resume may override some registers, 7351 * reconfig them here 7352 */ 7353 gfx_v10_0_tcp_harvest(adev); 7354 7355 r = gfx_v10_0_cp_resume(adev); 7356 if (r) 7357 return r; 7358 7359 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7360 gfx_v10_3_program_pbb_mode(adev); 7361 7362 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7363 gfx_v10_3_set_power_brake_sequence(adev); 7364 7365 return r; 7366 } 7367 7368 #ifndef BRING_UP_DEBUG 7369 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7370 { 7371 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7372 struct amdgpu_ring *kiq_ring = &kiq->ring; 7373 int i; 7374 7375 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7376 return -EINVAL; 7377 7378 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7379 adev->gfx.num_gfx_rings)) 7380 return -ENOMEM; 7381 7382 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7383 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7384 PREEMPT_QUEUES, 0, 0); 7385 7386 return amdgpu_ring_test_helper(kiq_ring); 7387 } 7388 #endif 7389 7390 static int gfx_v10_0_hw_fini(void *handle) 7391 { 7392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7393 int r; 7394 uint32_t tmp; 7395 7396 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7397 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7398 7399 if (!adev->no_hw_access) { 7400 #ifndef BRING_UP_DEBUG 7401 if (amdgpu_async_gfx_ring) { 7402 r = gfx_v10_0_kiq_disable_kgq(adev); 7403 if (r) 7404 DRM_ERROR("KGQ disable failed\n"); 7405 } 7406 #endif 7407 if (amdgpu_gfx_disable_kcq(adev)) 7408 DRM_ERROR("KCQ disable failed\n"); 7409 } 7410 7411 if (amdgpu_sriov_vf(adev)) { 7412 gfx_v10_0_cp_gfx_enable(adev, false); 7413 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7414 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7415 tmp &= 0xffffff00; 7416 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7417 7418 return 0; 7419 } 7420 gfx_v10_0_cp_enable(adev, false); 7421 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7422 7423 return 0; 7424 } 7425 7426 static int gfx_v10_0_suspend(void *handle) 7427 { 7428 return gfx_v10_0_hw_fini(handle); 7429 } 7430 7431 static int gfx_v10_0_resume(void *handle) 7432 { 7433 return gfx_v10_0_hw_init(handle); 7434 } 7435 7436 static bool gfx_v10_0_is_idle(void *handle) 7437 { 7438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7439 7440 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7441 GRBM_STATUS, GUI_ACTIVE)) 7442 return false; 7443 else 7444 return true; 7445 } 7446 7447 static int gfx_v10_0_wait_for_idle(void *handle) 7448 { 7449 unsigned i; 7450 u32 tmp; 7451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7452 7453 for (i = 0; i < adev->usec_timeout; i++) { 7454 /* read MC_STATUS */ 7455 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7456 GRBM_STATUS__GUI_ACTIVE_MASK; 7457 7458 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7459 return 0; 7460 udelay(1); 7461 } 7462 return -ETIMEDOUT; 7463 } 7464 7465 static int gfx_v10_0_soft_reset(void *handle) 7466 { 7467 u32 grbm_soft_reset = 0; 7468 u32 tmp; 7469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7470 7471 /* GRBM_STATUS */ 7472 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7473 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7474 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7475 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7476 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7477 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7478 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7479 GRBM_SOFT_RESET, SOFT_RESET_CP, 7480 1); 7481 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7482 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7483 1); 7484 } 7485 7486 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7487 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7488 GRBM_SOFT_RESET, SOFT_RESET_CP, 7489 1); 7490 } 7491 7492 /* GRBM_STATUS2 */ 7493 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7494 switch (adev->asic_type) { 7495 case CHIP_SIENNA_CICHLID: 7496 case CHIP_NAVY_FLOUNDER: 7497 case CHIP_VANGOGH: 7498 case CHIP_DIMGREY_CAVEFISH: 7499 case CHIP_BEIGE_GOBY: 7500 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7501 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7502 GRBM_SOFT_RESET, 7503 SOFT_RESET_RLC, 7504 1); 7505 break; 7506 default: 7507 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7508 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7509 GRBM_SOFT_RESET, 7510 SOFT_RESET_RLC, 7511 1); 7512 break; 7513 } 7514 7515 if (grbm_soft_reset) { 7516 /* stop the rlc */ 7517 gfx_v10_0_rlc_stop(adev); 7518 7519 /* Disable GFX parsing/prefetching */ 7520 gfx_v10_0_cp_gfx_enable(adev, false); 7521 7522 /* Disable MEC parsing/prefetching */ 7523 gfx_v10_0_cp_compute_enable(adev, false); 7524 7525 if (grbm_soft_reset) { 7526 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7527 tmp |= grbm_soft_reset; 7528 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7529 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7530 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7531 7532 udelay(50); 7533 7534 tmp &= ~grbm_soft_reset; 7535 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7536 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7537 } 7538 7539 /* Wait a little for things to settle down */ 7540 udelay(50); 7541 } 7542 return 0; 7543 } 7544 7545 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7546 { 7547 uint64_t clock; 7548 7549 amdgpu_gfx_off_ctrl(adev, false); 7550 mutex_lock(&adev->gfx.gpu_clock_mutex); 7551 switch (adev->asic_type) { 7552 case CHIP_VANGOGH: 7553 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | 7554 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); 7555 break; 7556 default: 7557 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7558 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7559 break; 7560 } 7561 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7562 amdgpu_gfx_off_ctrl(adev, true); 7563 return clock; 7564 } 7565 7566 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7567 uint32_t vmid, 7568 uint32_t gds_base, uint32_t gds_size, 7569 uint32_t gws_base, uint32_t gws_size, 7570 uint32_t oa_base, uint32_t oa_size) 7571 { 7572 struct amdgpu_device *adev = ring->adev; 7573 7574 /* GDS Base */ 7575 gfx_v10_0_write_data_to_reg(ring, 0, false, 7576 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7577 gds_base); 7578 7579 /* GDS Size */ 7580 gfx_v10_0_write_data_to_reg(ring, 0, false, 7581 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7582 gds_size); 7583 7584 /* GWS */ 7585 gfx_v10_0_write_data_to_reg(ring, 0, false, 7586 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7587 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7588 7589 /* OA */ 7590 gfx_v10_0_write_data_to_reg(ring, 0, false, 7591 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7592 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7593 } 7594 7595 static int gfx_v10_0_early_init(void *handle) 7596 { 7597 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7598 7599 switch (adev->asic_type) { 7600 case CHIP_NAVI10: 7601 case CHIP_NAVI14: 7602 case CHIP_NAVI12: 7603 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7604 break; 7605 case CHIP_SIENNA_CICHLID: 7606 case CHIP_NAVY_FLOUNDER: 7607 case CHIP_VANGOGH: 7608 case CHIP_DIMGREY_CAVEFISH: 7609 case CHIP_BEIGE_GOBY: 7610 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7611 break; 7612 default: 7613 break; 7614 } 7615 7616 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7617 AMDGPU_MAX_COMPUTE_RINGS); 7618 7619 gfx_v10_0_set_kiq_pm4_funcs(adev); 7620 gfx_v10_0_set_ring_funcs(adev); 7621 gfx_v10_0_set_irq_funcs(adev); 7622 gfx_v10_0_set_gds_init(adev); 7623 gfx_v10_0_set_rlc_funcs(adev); 7624 7625 return 0; 7626 } 7627 7628 static int gfx_v10_0_late_init(void *handle) 7629 { 7630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7631 int r; 7632 7633 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7634 if (r) 7635 return r; 7636 7637 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7638 if (r) 7639 return r; 7640 7641 return 0; 7642 } 7643 7644 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7645 { 7646 uint32_t rlc_cntl; 7647 7648 /* if RLC is not enabled, do nothing */ 7649 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7650 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7651 } 7652 7653 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7654 { 7655 uint32_t data; 7656 unsigned i; 7657 7658 data = RLC_SAFE_MODE__CMD_MASK; 7659 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7660 7661 switch (adev->asic_type) { 7662 case CHIP_SIENNA_CICHLID: 7663 case CHIP_NAVY_FLOUNDER: 7664 case CHIP_VANGOGH: 7665 case CHIP_DIMGREY_CAVEFISH: 7666 case CHIP_BEIGE_GOBY: 7667 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7668 7669 /* wait for RLC_SAFE_MODE */ 7670 for (i = 0; i < adev->usec_timeout; i++) { 7671 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7672 RLC_SAFE_MODE, CMD)) 7673 break; 7674 udelay(1); 7675 } 7676 break; 7677 default: 7678 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7679 7680 /* wait for RLC_SAFE_MODE */ 7681 for (i = 0; i < adev->usec_timeout; i++) { 7682 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7683 RLC_SAFE_MODE, CMD)) 7684 break; 7685 udelay(1); 7686 } 7687 break; 7688 } 7689 } 7690 7691 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7692 { 7693 uint32_t data; 7694 7695 data = RLC_SAFE_MODE__CMD_MASK; 7696 switch (adev->asic_type) { 7697 case CHIP_SIENNA_CICHLID: 7698 case CHIP_NAVY_FLOUNDER: 7699 case CHIP_VANGOGH: 7700 case CHIP_DIMGREY_CAVEFISH: 7701 case CHIP_BEIGE_GOBY: 7702 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7703 break; 7704 default: 7705 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7706 break; 7707 } 7708 } 7709 7710 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7711 bool enable) 7712 { 7713 uint32_t data, def; 7714 7715 /* It is disabled by HW by default */ 7716 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7717 /* 0 - Disable some blocks' MGCG */ 7718 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7719 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7720 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7721 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7722 7723 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7724 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7725 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7726 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7727 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7728 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7729 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7730 7731 if (def != data) 7732 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7733 7734 /* MGLS is a global flag to control all MGLS in GFX */ 7735 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7736 /* 2 - RLC memory Light sleep */ 7737 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7738 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7739 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7740 if (def != data) 7741 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7742 } 7743 /* 3 - CP memory Light sleep */ 7744 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7745 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7746 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7747 if (def != data) 7748 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7749 } 7750 } 7751 } else { 7752 /* 1 - MGCG_OVERRIDE */ 7753 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7754 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7755 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7756 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7757 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7758 if (def != data) 7759 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7760 7761 /* 2 - disable MGLS in CP */ 7762 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7763 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7764 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7765 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7766 } 7767 7768 /* 3 - disable MGLS in RLC */ 7769 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7770 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7771 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7772 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7773 } 7774 7775 } 7776 } 7777 7778 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7779 bool enable) 7780 { 7781 uint32_t data, def; 7782 7783 /* Enable 3D CGCG/CGLS */ 7784 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7785 /* write cmd to clear cgcg/cgls ov */ 7786 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7787 /* unset CGCG override */ 7788 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7789 /* update CGCG and CGLS override bits */ 7790 if (def != data) 7791 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7792 /* enable 3Dcgcg FSM(0x0000363f) */ 7793 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7794 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7795 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7796 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7797 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7798 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7799 if (def != data) 7800 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7801 7802 /* set IDLE_POLL_COUNT(0x00900100) */ 7803 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7804 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7805 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7806 if (def != data) 7807 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7808 } else { 7809 /* Disable CGCG/CGLS */ 7810 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7811 /* disable cgcg, cgls should be disabled */ 7812 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7813 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7814 /* disable cgcg and cgls in FSM */ 7815 if (def != data) 7816 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7817 } 7818 } 7819 7820 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7821 bool enable) 7822 { 7823 uint32_t def, data; 7824 7825 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7826 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7827 /* unset CGCG override */ 7828 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7829 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7830 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7831 else 7832 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7833 /* update CGCG and CGLS override bits */ 7834 if (def != data) 7835 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7836 7837 /* enable cgcg FSM(0x0000363F) */ 7838 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7839 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7840 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7841 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7842 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7843 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7844 if (def != data) 7845 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7846 7847 /* set IDLE_POLL_COUNT(0x00900100) */ 7848 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7849 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7850 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7851 if (def != data) 7852 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7853 } else { 7854 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7855 /* reset CGCG/CGLS bits */ 7856 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7857 /* disable cgcg and cgls in FSM */ 7858 if (def != data) 7859 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7860 } 7861 } 7862 7863 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7864 bool enable) 7865 { 7866 uint32_t def, data; 7867 7868 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7869 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7870 /* unset FGCG override */ 7871 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7872 /* update FGCG override bits */ 7873 if (def != data) 7874 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7875 7876 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7877 /* unset RLC SRAM CLK GATER override */ 7878 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7879 /* update RLC SRAM CLK GATER override bits */ 7880 if (def != data) 7881 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7882 } else { 7883 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7884 /* reset FGCG bits */ 7885 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7886 /* disable FGCG*/ 7887 if (def != data) 7888 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7889 7890 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7891 /* reset RLC SRAM CLK GATER bits */ 7892 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7893 /* disable RLC SRAM CLK*/ 7894 if (def != data) 7895 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7896 } 7897 } 7898 7899 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7900 bool enable) 7901 { 7902 amdgpu_gfx_rlc_enter_safe_mode(adev); 7903 7904 if (enable) { 7905 /* enable FGCG firstly*/ 7906 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7907 /* CGCG/CGLS should be enabled after MGCG/MGLS 7908 * === MGCG + MGLS === 7909 */ 7910 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7911 /* === CGCG /CGLS for GFX 3D Only === */ 7912 gfx_v10_0_update_3d_clock_gating(adev, enable); 7913 /* === CGCG + CGLS === */ 7914 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7915 } else { 7916 /* CGCG/CGLS should be disabled before MGCG/MGLS 7917 * === CGCG + CGLS === 7918 */ 7919 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7920 /* === CGCG /CGLS for GFX 3D Only === */ 7921 gfx_v10_0_update_3d_clock_gating(adev, enable); 7922 /* === MGCG + MGLS === */ 7923 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7924 /* disable fgcg at last*/ 7925 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7926 } 7927 7928 if (adev->cg_flags & 7929 (AMD_CG_SUPPORT_GFX_MGCG | 7930 AMD_CG_SUPPORT_GFX_CGLS | 7931 AMD_CG_SUPPORT_GFX_CGCG | 7932 AMD_CG_SUPPORT_GFX_3D_CGCG | 7933 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7934 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7935 7936 amdgpu_gfx_rlc_exit_safe_mode(adev); 7937 7938 return 0; 7939 } 7940 7941 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7942 { 7943 u32 reg, data; 7944 7945 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7946 if (amdgpu_sriov_is_pp_one_vf(adev)) 7947 data = RREG32_NO_KIQ(reg); 7948 else 7949 data = RREG32(reg); 7950 7951 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7952 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7953 7954 if (amdgpu_sriov_is_pp_one_vf(adev)) 7955 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7956 else 7957 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7958 } 7959 7960 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7961 uint32_t offset, 7962 struct soc15_reg_rlcg *entries, int arr_size) 7963 { 7964 int i; 7965 uint32_t reg; 7966 7967 if (!entries) 7968 return false; 7969 7970 for (i = 0; i < arr_size; i++) { 7971 const struct soc15_reg_rlcg *entry; 7972 7973 entry = &entries[i]; 7974 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7975 if (offset == reg) 7976 return true; 7977 } 7978 7979 return false; 7980 } 7981 7982 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7983 { 7984 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7985 } 7986 7987 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7988 { 7989 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7990 7991 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7992 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7993 else 7994 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7995 7996 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7997 7998 /* 7999 * CGPG enablement required and the register to program the hysteresis value 8000 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8001 * in refclk count. Note that RLC FW is modified to take 16 bits from 8002 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8003 * 8004 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20) 8005 * as part of CGPG enablement starting point. 8006 */ 8007 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) { 8008 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8009 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8010 } 8011 } 8012 8013 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8014 { 8015 amdgpu_gfx_rlc_enter_safe_mode(adev); 8016 8017 gfx_v10_cntl_power_gating(adev, enable); 8018 8019 amdgpu_gfx_rlc_exit_safe_mode(adev); 8020 } 8021 8022 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8023 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8024 .set_safe_mode = gfx_v10_0_set_safe_mode, 8025 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8026 .init = gfx_v10_0_rlc_init, 8027 .get_csb_size = gfx_v10_0_get_csb_size, 8028 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8029 .resume = gfx_v10_0_rlc_resume, 8030 .stop = gfx_v10_0_rlc_stop, 8031 .reset = gfx_v10_0_rlc_reset, 8032 .start = gfx_v10_0_rlc_start, 8033 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8034 }; 8035 8036 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8037 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8038 .set_safe_mode = gfx_v10_0_set_safe_mode, 8039 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8040 .init = gfx_v10_0_rlc_init, 8041 .get_csb_size = gfx_v10_0_get_csb_size, 8042 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8043 .resume = gfx_v10_0_rlc_resume, 8044 .stop = gfx_v10_0_rlc_stop, 8045 .reset = gfx_v10_0_rlc_reset, 8046 .start = gfx_v10_0_rlc_start, 8047 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8048 .rlcg_wreg = gfx_v10_rlcg_wreg, 8049 .rlcg_rreg = gfx_v10_rlcg_rreg, 8050 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8051 }; 8052 8053 static int gfx_v10_0_set_powergating_state(void *handle, 8054 enum amd_powergating_state state) 8055 { 8056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8057 bool enable = (state == AMD_PG_STATE_GATE); 8058 8059 if (amdgpu_sriov_vf(adev)) 8060 return 0; 8061 8062 switch (adev->asic_type) { 8063 case CHIP_NAVI10: 8064 case CHIP_NAVI14: 8065 case CHIP_NAVI12: 8066 case CHIP_SIENNA_CICHLID: 8067 case CHIP_NAVY_FLOUNDER: 8068 case CHIP_DIMGREY_CAVEFISH: 8069 case CHIP_BEIGE_GOBY: 8070 amdgpu_gfx_off_ctrl(adev, enable); 8071 break; 8072 case CHIP_VANGOGH: 8073 gfx_v10_cntl_pg(adev, enable); 8074 amdgpu_gfx_off_ctrl(adev, enable); 8075 break; 8076 default: 8077 break; 8078 } 8079 return 0; 8080 } 8081 8082 static int gfx_v10_0_set_clockgating_state(void *handle, 8083 enum amd_clockgating_state state) 8084 { 8085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8086 8087 if (amdgpu_sriov_vf(adev)) 8088 return 0; 8089 8090 switch (adev->asic_type) { 8091 case CHIP_NAVI10: 8092 case CHIP_NAVI14: 8093 case CHIP_NAVI12: 8094 case CHIP_SIENNA_CICHLID: 8095 case CHIP_NAVY_FLOUNDER: 8096 case CHIP_VANGOGH: 8097 case CHIP_DIMGREY_CAVEFISH: 8098 case CHIP_BEIGE_GOBY: 8099 gfx_v10_0_update_gfx_clock_gating(adev, 8100 state == AMD_CG_STATE_GATE); 8101 break; 8102 default: 8103 break; 8104 } 8105 return 0; 8106 } 8107 8108 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 8109 { 8110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8111 int data; 8112 8113 /* AMD_CG_SUPPORT_GFX_FGCG */ 8114 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8115 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8116 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8117 8118 /* AMD_CG_SUPPORT_GFX_MGCG */ 8119 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8120 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8121 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8122 8123 /* AMD_CG_SUPPORT_GFX_CGCG */ 8124 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8125 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8126 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8127 8128 /* AMD_CG_SUPPORT_GFX_CGLS */ 8129 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8130 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8131 8132 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8133 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8134 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8135 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8136 8137 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8138 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8139 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8140 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8141 8142 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8143 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8144 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8145 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8146 8147 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8148 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8149 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8150 } 8151 8152 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8153 { 8154 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 8155 } 8156 8157 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8158 { 8159 struct amdgpu_device *adev = ring->adev; 8160 u64 wptr; 8161 8162 /* XXX check if swapping is necessary on BE */ 8163 if (ring->use_doorbell) { 8164 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8165 } else { 8166 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8167 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8168 } 8169 8170 return wptr; 8171 } 8172 8173 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8174 { 8175 struct amdgpu_device *adev = ring->adev; 8176 8177 if (ring->use_doorbell) { 8178 /* XXX check if swapping is necessary on BE */ 8179 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8180 WDOORBELL64(ring->doorbell_index, ring->wptr); 8181 } else { 8182 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8183 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8184 } 8185 } 8186 8187 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8188 { 8189 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8190 } 8191 8192 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8193 { 8194 u64 wptr; 8195 8196 /* XXX check if swapping is necessary on BE */ 8197 if (ring->use_doorbell) 8198 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8199 else 8200 BUG(); 8201 return wptr; 8202 } 8203 8204 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8205 { 8206 struct amdgpu_device *adev = ring->adev; 8207 8208 /* XXX check if swapping is necessary on BE */ 8209 if (ring->use_doorbell) { 8210 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8211 WDOORBELL64(ring->doorbell_index, ring->wptr); 8212 } else { 8213 BUG(); /* only DOORBELL method supported on gfx10 now */ 8214 } 8215 } 8216 8217 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8218 { 8219 struct amdgpu_device *adev = ring->adev; 8220 u32 ref_and_mask, reg_mem_engine; 8221 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8222 8223 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8224 switch (ring->me) { 8225 case 1: 8226 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8227 break; 8228 case 2: 8229 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8230 break; 8231 default: 8232 return; 8233 } 8234 reg_mem_engine = 0; 8235 } else { 8236 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8237 reg_mem_engine = 1; /* pfp */ 8238 } 8239 8240 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8241 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8242 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8243 ref_and_mask, ref_and_mask, 0x20); 8244 } 8245 8246 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8247 struct amdgpu_job *job, 8248 struct amdgpu_ib *ib, 8249 uint32_t flags) 8250 { 8251 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8252 u32 header, control = 0; 8253 8254 if (ib->flags & AMDGPU_IB_FLAG_CE) 8255 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8256 else 8257 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8258 8259 control |= ib->length_dw | (vmid << 24); 8260 8261 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8262 control |= INDIRECT_BUFFER_PRE_ENB(1); 8263 8264 if (flags & AMDGPU_IB_PREEMPTED) 8265 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8266 8267 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8268 gfx_v10_0_ring_emit_de_meta(ring, 8269 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8270 } 8271 8272 amdgpu_ring_write(ring, header); 8273 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8274 amdgpu_ring_write(ring, 8275 #ifdef __BIG_ENDIAN 8276 (2 << 0) | 8277 #endif 8278 lower_32_bits(ib->gpu_addr)); 8279 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8280 amdgpu_ring_write(ring, control); 8281 } 8282 8283 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8284 struct amdgpu_job *job, 8285 struct amdgpu_ib *ib, 8286 uint32_t flags) 8287 { 8288 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8289 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8290 8291 /* Currently, there is a high possibility to get wave ID mismatch 8292 * between ME and GDS, leading to a hw deadlock, because ME generates 8293 * different wave IDs than the GDS expects. This situation happens 8294 * randomly when at least 5 compute pipes use GDS ordered append. 8295 * The wave IDs generated by ME are also wrong after suspend/resume. 8296 * Those are probably bugs somewhere else in the kernel driver. 8297 * 8298 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8299 * GDS to 0 for this ring (me/pipe). 8300 */ 8301 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8302 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8303 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8304 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8305 } 8306 8307 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8308 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8309 amdgpu_ring_write(ring, 8310 #ifdef __BIG_ENDIAN 8311 (2 << 0) | 8312 #endif 8313 lower_32_bits(ib->gpu_addr)); 8314 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8315 amdgpu_ring_write(ring, control); 8316 } 8317 8318 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8319 u64 seq, unsigned flags) 8320 { 8321 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8322 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8323 8324 /* RELEASE_MEM - flush caches, send int */ 8325 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8326 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8327 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8328 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8329 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8330 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8331 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8332 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8333 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8334 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8335 8336 /* 8337 * the address should be Qword aligned if 64bit write, Dword 8338 * aligned if only send 32bit data low (discard data high) 8339 */ 8340 if (write64bit) 8341 BUG_ON(addr & 0x7); 8342 else 8343 BUG_ON(addr & 0x3); 8344 amdgpu_ring_write(ring, lower_32_bits(addr)); 8345 amdgpu_ring_write(ring, upper_32_bits(addr)); 8346 amdgpu_ring_write(ring, lower_32_bits(seq)); 8347 amdgpu_ring_write(ring, upper_32_bits(seq)); 8348 amdgpu_ring_write(ring, 0); 8349 } 8350 8351 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8352 { 8353 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8354 uint32_t seq = ring->fence_drv.sync_seq; 8355 uint64_t addr = ring->fence_drv.gpu_addr; 8356 8357 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8358 upper_32_bits(addr), seq, 0xffffffff, 4); 8359 } 8360 8361 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8362 unsigned vmid, uint64_t pd_addr) 8363 { 8364 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8365 8366 /* compute doesn't have PFP */ 8367 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8368 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8369 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8370 amdgpu_ring_write(ring, 0x0); 8371 } 8372 } 8373 8374 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8375 u64 seq, unsigned int flags) 8376 { 8377 struct amdgpu_device *adev = ring->adev; 8378 8379 /* we only allocate 32bit for each seq wb address */ 8380 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8381 8382 /* write fence seq to the "addr" */ 8383 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8384 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8385 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8386 amdgpu_ring_write(ring, lower_32_bits(addr)); 8387 amdgpu_ring_write(ring, upper_32_bits(addr)); 8388 amdgpu_ring_write(ring, lower_32_bits(seq)); 8389 8390 if (flags & AMDGPU_FENCE_FLAG_INT) { 8391 /* set register to trigger INT */ 8392 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8393 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8394 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8395 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8396 amdgpu_ring_write(ring, 0); 8397 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8398 } 8399 } 8400 8401 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8402 { 8403 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8404 amdgpu_ring_write(ring, 0); 8405 } 8406 8407 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8408 uint32_t flags) 8409 { 8410 uint32_t dw2 = 0; 8411 8412 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8413 gfx_v10_0_ring_emit_ce_meta(ring, 8414 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8415 8416 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8417 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8418 /* set load_global_config & load_global_uconfig */ 8419 dw2 |= 0x8001; 8420 /* set load_cs_sh_regs */ 8421 dw2 |= 0x01000000; 8422 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8423 dw2 |= 0x10002; 8424 8425 /* set load_ce_ram if preamble presented */ 8426 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8427 dw2 |= 0x10000000; 8428 } else { 8429 /* still load_ce_ram if this is the first time preamble presented 8430 * although there is no context switch happens. 8431 */ 8432 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8433 dw2 |= 0x10000000; 8434 } 8435 8436 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8437 amdgpu_ring_write(ring, dw2); 8438 amdgpu_ring_write(ring, 0); 8439 } 8440 8441 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8442 { 8443 unsigned ret; 8444 8445 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8446 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8447 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8448 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8449 ret = ring->wptr & ring->buf_mask; 8450 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8451 8452 return ret; 8453 } 8454 8455 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8456 { 8457 unsigned cur; 8458 BUG_ON(offset > ring->buf_mask); 8459 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8460 8461 cur = (ring->wptr - 1) & ring->buf_mask; 8462 if (likely(cur > offset)) 8463 ring->ring[offset] = cur - offset; 8464 else 8465 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8466 } 8467 8468 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8469 { 8470 int i, r = 0; 8471 struct amdgpu_device *adev = ring->adev; 8472 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8473 struct amdgpu_ring *kiq_ring = &kiq->ring; 8474 unsigned long flags; 8475 8476 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8477 return -EINVAL; 8478 8479 spin_lock_irqsave(&kiq->ring_lock, flags); 8480 8481 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8482 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8483 return -ENOMEM; 8484 } 8485 8486 /* assert preemption condition */ 8487 amdgpu_ring_set_preempt_cond_exec(ring, false); 8488 8489 /* assert IB preemption, emit the trailing fence */ 8490 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8491 ring->trail_fence_gpu_addr, 8492 ++ring->trail_seq); 8493 amdgpu_ring_commit(kiq_ring); 8494 8495 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8496 8497 /* poll the trailing fence */ 8498 for (i = 0; i < adev->usec_timeout; i++) { 8499 if (ring->trail_seq == 8500 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8501 break; 8502 udelay(1); 8503 } 8504 8505 if (i >= adev->usec_timeout) { 8506 r = -EINVAL; 8507 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8508 } 8509 8510 /* deassert preemption condition */ 8511 amdgpu_ring_set_preempt_cond_exec(ring, true); 8512 return r; 8513 } 8514 8515 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8516 { 8517 struct amdgpu_device *adev = ring->adev; 8518 struct v10_ce_ib_state ce_payload = {0}; 8519 uint64_t csa_addr; 8520 int cnt; 8521 8522 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8523 csa_addr = amdgpu_csa_vaddr(ring->adev); 8524 8525 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8526 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8527 WRITE_DATA_DST_SEL(8) | 8528 WR_CONFIRM) | 8529 WRITE_DATA_CACHE_POLICY(0)); 8530 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8531 offsetof(struct v10_gfx_meta_data, ce_payload))); 8532 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8533 offsetof(struct v10_gfx_meta_data, ce_payload))); 8534 8535 if (resume) 8536 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8537 offsetof(struct v10_gfx_meta_data, 8538 ce_payload), 8539 sizeof(ce_payload) >> 2); 8540 else 8541 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8542 sizeof(ce_payload) >> 2); 8543 } 8544 8545 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8546 { 8547 struct amdgpu_device *adev = ring->adev; 8548 struct v10_de_ib_state de_payload = {0}; 8549 uint64_t csa_addr, gds_addr; 8550 int cnt; 8551 8552 csa_addr = amdgpu_csa_vaddr(ring->adev); 8553 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8554 PAGE_SIZE); 8555 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8556 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8557 8558 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8559 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8560 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8561 WRITE_DATA_DST_SEL(8) | 8562 WR_CONFIRM) | 8563 WRITE_DATA_CACHE_POLICY(0)); 8564 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8565 offsetof(struct v10_gfx_meta_data, de_payload))); 8566 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8567 offsetof(struct v10_gfx_meta_data, de_payload))); 8568 8569 if (resume) 8570 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8571 offsetof(struct v10_gfx_meta_data, 8572 de_payload), 8573 sizeof(de_payload) >> 2); 8574 else 8575 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8576 sizeof(de_payload) >> 2); 8577 } 8578 8579 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8580 bool secure) 8581 { 8582 uint32_t v = secure ? FRAME_TMZ : 0; 8583 8584 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8585 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8586 } 8587 8588 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8589 uint32_t reg_val_offs) 8590 { 8591 struct amdgpu_device *adev = ring->adev; 8592 8593 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8594 amdgpu_ring_write(ring, 0 | /* src: register*/ 8595 (5 << 8) | /* dst: memory */ 8596 (1 << 20)); /* write confirm */ 8597 amdgpu_ring_write(ring, reg); 8598 amdgpu_ring_write(ring, 0); 8599 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8600 reg_val_offs * 4)); 8601 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8602 reg_val_offs * 4)); 8603 } 8604 8605 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8606 uint32_t val) 8607 { 8608 uint32_t cmd = 0; 8609 8610 switch (ring->funcs->type) { 8611 case AMDGPU_RING_TYPE_GFX: 8612 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8613 break; 8614 case AMDGPU_RING_TYPE_KIQ: 8615 cmd = (1 << 16); /* no inc addr */ 8616 break; 8617 default: 8618 cmd = WR_CONFIRM; 8619 break; 8620 } 8621 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8622 amdgpu_ring_write(ring, cmd); 8623 amdgpu_ring_write(ring, reg); 8624 amdgpu_ring_write(ring, 0); 8625 amdgpu_ring_write(ring, val); 8626 } 8627 8628 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8629 uint32_t val, uint32_t mask) 8630 { 8631 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8632 } 8633 8634 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8635 uint32_t reg0, uint32_t reg1, 8636 uint32_t ref, uint32_t mask) 8637 { 8638 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8639 struct amdgpu_device *adev = ring->adev; 8640 bool fw_version_ok = false; 8641 8642 fw_version_ok = adev->gfx.cp_fw_write_wait; 8643 8644 if (fw_version_ok) 8645 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8646 ref, mask, 0x20); 8647 else 8648 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8649 ref, mask); 8650 } 8651 8652 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8653 unsigned vmid) 8654 { 8655 struct amdgpu_device *adev = ring->adev; 8656 uint32_t value = 0; 8657 8658 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8659 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8660 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8661 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8662 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8663 } 8664 8665 static void 8666 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8667 uint32_t me, uint32_t pipe, 8668 enum amdgpu_interrupt_state state) 8669 { 8670 uint32_t cp_int_cntl, cp_int_cntl_reg; 8671 8672 if (!me) { 8673 switch (pipe) { 8674 case 0: 8675 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8676 break; 8677 case 1: 8678 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8679 break; 8680 default: 8681 DRM_DEBUG("invalid pipe %d\n", pipe); 8682 return; 8683 } 8684 } else { 8685 DRM_DEBUG("invalid me %d\n", me); 8686 return; 8687 } 8688 8689 switch (state) { 8690 case AMDGPU_IRQ_STATE_DISABLE: 8691 cp_int_cntl = RREG32(cp_int_cntl_reg); 8692 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8693 TIME_STAMP_INT_ENABLE, 0); 8694 WREG32(cp_int_cntl_reg, cp_int_cntl); 8695 break; 8696 case AMDGPU_IRQ_STATE_ENABLE: 8697 cp_int_cntl = RREG32(cp_int_cntl_reg); 8698 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8699 TIME_STAMP_INT_ENABLE, 1); 8700 WREG32(cp_int_cntl_reg, cp_int_cntl); 8701 break; 8702 default: 8703 break; 8704 } 8705 } 8706 8707 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8708 int me, int pipe, 8709 enum amdgpu_interrupt_state state) 8710 { 8711 u32 mec_int_cntl, mec_int_cntl_reg; 8712 8713 /* 8714 * amdgpu controls only the first MEC. That's why this function only 8715 * handles the setting of interrupts for this specific MEC. All other 8716 * pipes' interrupts are set by amdkfd. 8717 */ 8718 8719 if (me == 1) { 8720 switch (pipe) { 8721 case 0: 8722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8723 break; 8724 case 1: 8725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8726 break; 8727 case 2: 8728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8729 break; 8730 case 3: 8731 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8732 break; 8733 default: 8734 DRM_DEBUG("invalid pipe %d\n", pipe); 8735 return; 8736 } 8737 } else { 8738 DRM_DEBUG("invalid me %d\n", me); 8739 return; 8740 } 8741 8742 switch (state) { 8743 case AMDGPU_IRQ_STATE_DISABLE: 8744 mec_int_cntl = RREG32(mec_int_cntl_reg); 8745 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8746 TIME_STAMP_INT_ENABLE, 0); 8747 WREG32(mec_int_cntl_reg, mec_int_cntl); 8748 break; 8749 case AMDGPU_IRQ_STATE_ENABLE: 8750 mec_int_cntl = RREG32(mec_int_cntl_reg); 8751 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8752 TIME_STAMP_INT_ENABLE, 1); 8753 WREG32(mec_int_cntl_reg, mec_int_cntl); 8754 break; 8755 default: 8756 break; 8757 } 8758 } 8759 8760 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8761 struct amdgpu_irq_src *src, 8762 unsigned type, 8763 enum amdgpu_interrupt_state state) 8764 { 8765 switch (type) { 8766 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8767 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8768 break; 8769 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8770 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8771 break; 8772 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8773 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8774 break; 8775 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8776 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8777 break; 8778 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8779 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8780 break; 8781 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8782 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8783 break; 8784 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8785 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8786 break; 8787 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8788 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8789 break; 8790 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8791 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8792 break; 8793 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8794 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8795 break; 8796 default: 8797 break; 8798 } 8799 return 0; 8800 } 8801 8802 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8803 struct amdgpu_irq_src *source, 8804 struct amdgpu_iv_entry *entry) 8805 { 8806 int i; 8807 u8 me_id, pipe_id, queue_id; 8808 struct amdgpu_ring *ring; 8809 8810 DRM_DEBUG("IH: CP EOP\n"); 8811 me_id = (entry->ring_id & 0x0c) >> 2; 8812 pipe_id = (entry->ring_id & 0x03) >> 0; 8813 queue_id = (entry->ring_id & 0x70) >> 4; 8814 8815 switch (me_id) { 8816 case 0: 8817 if (pipe_id == 0) 8818 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8819 else 8820 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8821 break; 8822 case 1: 8823 case 2: 8824 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8825 ring = &adev->gfx.compute_ring[i]; 8826 /* Per-queue interrupt is supported for MEC starting from VI. 8827 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8828 */ 8829 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8830 amdgpu_fence_process(ring); 8831 } 8832 break; 8833 } 8834 return 0; 8835 } 8836 8837 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8838 struct amdgpu_irq_src *source, 8839 unsigned type, 8840 enum amdgpu_interrupt_state state) 8841 { 8842 switch (state) { 8843 case AMDGPU_IRQ_STATE_DISABLE: 8844 case AMDGPU_IRQ_STATE_ENABLE: 8845 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8846 PRIV_REG_INT_ENABLE, 8847 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8848 break; 8849 default: 8850 break; 8851 } 8852 8853 return 0; 8854 } 8855 8856 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8857 struct amdgpu_irq_src *source, 8858 unsigned type, 8859 enum amdgpu_interrupt_state state) 8860 { 8861 switch (state) { 8862 case AMDGPU_IRQ_STATE_DISABLE: 8863 case AMDGPU_IRQ_STATE_ENABLE: 8864 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8865 PRIV_INSTR_INT_ENABLE, 8866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8867 break; 8868 default: 8869 break; 8870 } 8871 8872 return 0; 8873 } 8874 8875 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8876 struct amdgpu_iv_entry *entry) 8877 { 8878 u8 me_id, pipe_id, queue_id; 8879 struct amdgpu_ring *ring; 8880 int i; 8881 8882 me_id = (entry->ring_id & 0x0c) >> 2; 8883 pipe_id = (entry->ring_id & 0x03) >> 0; 8884 queue_id = (entry->ring_id & 0x70) >> 4; 8885 8886 switch (me_id) { 8887 case 0: 8888 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8889 ring = &adev->gfx.gfx_ring[i]; 8890 /* we only enabled 1 gfx queue per pipe for now */ 8891 if (ring->me == me_id && ring->pipe == pipe_id) 8892 drm_sched_fault(&ring->sched); 8893 } 8894 break; 8895 case 1: 8896 case 2: 8897 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8898 ring = &adev->gfx.compute_ring[i]; 8899 if (ring->me == me_id && ring->pipe == pipe_id && 8900 ring->queue == queue_id) 8901 drm_sched_fault(&ring->sched); 8902 } 8903 break; 8904 default: 8905 BUG(); 8906 } 8907 } 8908 8909 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8910 struct amdgpu_irq_src *source, 8911 struct amdgpu_iv_entry *entry) 8912 { 8913 DRM_ERROR("Illegal register access in command stream\n"); 8914 gfx_v10_0_handle_priv_fault(adev, entry); 8915 return 0; 8916 } 8917 8918 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8919 struct amdgpu_irq_src *source, 8920 struct amdgpu_iv_entry *entry) 8921 { 8922 DRM_ERROR("Illegal instruction in command stream\n"); 8923 gfx_v10_0_handle_priv_fault(adev, entry); 8924 return 0; 8925 } 8926 8927 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8928 struct amdgpu_irq_src *src, 8929 unsigned int type, 8930 enum amdgpu_interrupt_state state) 8931 { 8932 uint32_t tmp, target; 8933 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8934 8935 if (ring->me == 1) 8936 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8937 else 8938 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8939 target += ring->pipe; 8940 8941 switch (type) { 8942 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8943 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8944 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8945 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8946 GENERIC2_INT_ENABLE, 0); 8947 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8948 8949 tmp = RREG32(target); 8950 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8951 GENERIC2_INT_ENABLE, 0); 8952 WREG32(target, tmp); 8953 } else { 8954 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8955 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8956 GENERIC2_INT_ENABLE, 1); 8957 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8958 8959 tmp = RREG32(target); 8960 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8961 GENERIC2_INT_ENABLE, 1); 8962 WREG32(target, tmp); 8963 } 8964 break; 8965 default: 8966 BUG(); /* kiq only support GENERIC2_INT now */ 8967 break; 8968 } 8969 return 0; 8970 } 8971 8972 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8973 struct amdgpu_irq_src *source, 8974 struct amdgpu_iv_entry *entry) 8975 { 8976 u8 me_id, pipe_id, queue_id; 8977 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8978 8979 me_id = (entry->ring_id & 0x0c) >> 2; 8980 pipe_id = (entry->ring_id & 0x03) >> 0; 8981 queue_id = (entry->ring_id & 0x70) >> 4; 8982 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8983 me_id, pipe_id, queue_id); 8984 8985 amdgpu_fence_process(ring); 8986 return 0; 8987 } 8988 8989 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8990 { 8991 const unsigned int gcr_cntl = 8992 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8993 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8994 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8995 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8996 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8997 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8998 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8999 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9000 9001 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9002 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9003 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9004 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9005 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9006 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9007 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9008 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9009 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9010 } 9011 9012 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9013 .name = "gfx_v10_0", 9014 .early_init = gfx_v10_0_early_init, 9015 .late_init = gfx_v10_0_late_init, 9016 .sw_init = gfx_v10_0_sw_init, 9017 .sw_fini = gfx_v10_0_sw_fini, 9018 .hw_init = gfx_v10_0_hw_init, 9019 .hw_fini = gfx_v10_0_hw_fini, 9020 .suspend = gfx_v10_0_suspend, 9021 .resume = gfx_v10_0_resume, 9022 .is_idle = gfx_v10_0_is_idle, 9023 .wait_for_idle = gfx_v10_0_wait_for_idle, 9024 .soft_reset = gfx_v10_0_soft_reset, 9025 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9026 .set_powergating_state = gfx_v10_0_set_powergating_state, 9027 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9028 }; 9029 9030 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9031 .type = AMDGPU_RING_TYPE_GFX, 9032 .align_mask = 0xff, 9033 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9034 .support_64bit_ptrs = true, 9035 .vmhub = AMDGPU_GFXHUB_0, 9036 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9037 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9038 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9039 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9040 5 + /* COND_EXEC */ 9041 7 + /* PIPELINE_SYNC */ 9042 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9043 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9044 2 + /* VM_FLUSH */ 9045 8 + /* FENCE for VM_FLUSH */ 9046 20 + /* GDS switch */ 9047 4 + /* double SWITCH_BUFFER, 9048 * the first COND_EXEC jump to the place 9049 * just prior to this double SWITCH_BUFFER 9050 */ 9051 5 + /* COND_EXEC */ 9052 7 + /* HDP_flush */ 9053 4 + /* VGT_flush */ 9054 14 + /* CE_META */ 9055 31 + /* DE_META */ 9056 3 + /* CNTX_CTRL */ 9057 5 + /* HDP_INVL */ 9058 8 + 8 + /* FENCE x2 */ 9059 2 + /* SWITCH_BUFFER */ 9060 8, /* gfx_v10_0_emit_mem_sync */ 9061 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9062 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9063 .emit_fence = gfx_v10_0_ring_emit_fence, 9064 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9065 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9066 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9067 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9068 .test_ring = gfx_v10_0_ring_test_ring, 9069 .test_ib = gfx_v10_0_ring_test_ib, 9070 .insert_nop = amdgpu_ring_insert_nop, 9071 .pad_ib = amdgpu_ring_generic_pad_ib, 9072 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9073 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9074 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9075 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9076 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9077 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9078 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9079 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9080 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9081 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9082 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9083 }; 9084 9085 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9086 .type = AMDGPU_RING_TYPE_COMPUTE, 9087 .align_mask = 0xff, 9088 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9089 .support_64bit_ptrs = true, 9090 .vmhub = AMDGPU_GFXHUB_0, 9091 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9092 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9093 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9094 .emit_frame_size = 9095 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9096 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9097 5 + /* hdp invalidate */ 9098 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9099 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9100 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9101 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9102 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9103 8, /* gfx_v10_0_emit_mem_sync */ 9104 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9105 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9106 .emit_fence = gfx_v10_0_ring_emit_fence, 9107 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9108 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9109 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9110 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9111 .test_ring = gfx_v10_0_ring_test_ring, 9112 .test_ib = gfx_v10_0_ring_test_ib, 9113 .insert_nop = amdgpu_ring_insert_nop, 9114 .pad_ib = amdgpu_ring_generic_pad_ib, 9115 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9116 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9117 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9118 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9119 }; 9120 9121 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9122 .type = AMDGPU_RING_TYPE_KIQ, 9123 .align_mask = 0xff, 9124 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9125 .support_64bit_ptrs = true, 9126 .vmhub = AMDGPU_GFXHUB_0, 9127 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9128 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9129 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9130 .emit_frame_size = 9131 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9132 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9133 5 + /*hdp invalidate */ 9134 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9135 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9136 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9137 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9138 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9139 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9140 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9141 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9142 .test_ring = gfx_v10_0_ring_test_ring, 9143 .test_ib = gfx_v10_0_ring_test_ib, 9144 .insert_nop = amdgpu_ring_insert_nop, 9145 .pad_ib = amdgpu_ring_generic_pad_ib, 9146 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9147 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9148 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9149 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9150 }; 9151 9152 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9153 { 9154 int i; 9155 9156 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9157 9158 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9159 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9160 9161 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9162 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9163 } 9164 9165 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9166 .set = gfx_v10_0_set_eop_interrupt_state, 9167 .process = gfx_v10_0_eop_irq, 9168 }; 9169 9170 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9171 .set = gfx_v10_0_set_priv_reg_fault_state, 9172 .process = gfx_v10_0_priv_reg_irq, 9173 }; 9174 9175 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9176 .set = gfx_v10_0_set_priv_inst_fault_state, 9177 .process = gfx_v10_0_priv_inst_irq, 9178 }; 9179 9180 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9181 .set = gfx_v10_0_kiq_set_interrupt_state, 9182 .process = gfx_v10_0_kiq_irq, 9183 }; 9184 9185 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9186 { 9187 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9188 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9189 9190 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9191 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9192 9193 adev->gfx.priv_reg_irq.num_types = 1; 9194 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9195 9196 adev->gfx.priv_inst_irq.num_types = 1; 9197 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9198 } 9199 9200 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9201 { 9202 switch (adev->asic_type) { 9203 case CHIP_NAVI10: 9204 case CHIP_NAVI14: 9205 case CHIP_SIENNA_CICHLID: 9206 case CHIP_NAVY_FLOUNDER: 9207 case CHIP_VANGOGH: 9208 case CHIP_DIMGREY_CAVEFISH: 9209 case CHIP_BEIGE_GOBY: 9210 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9211 break; 9212 case CHIP_NAVI12: 9213 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9214 break; 9215 default: 9216 break; 9217 } 9218 } 9219 9220 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9221 { 9222 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9223 adev->gfx.config.max_sh_per_se * 9224 adev->gfx.config.max_shader_engines; 9225 9226 adev->gds.gds_size = 0x10000; 9227 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9228 adev->gds.gws_size = 64; 9229 adev->gds.oa_size = 16; 9230 } 9231 9232 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9233 u32 bitmap) 9234 { 9235 u32 data; 9236 9237 if (!bitmap) 9238 return; 9239 9240 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9241 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9242 9243 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9244 } 9245 9246 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9247 { 9248 u32 data, wgp_bitmask; 9249 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9250 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9251 9252 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9253 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9254 9255 wgp_bitmask = 9256 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9257 9258 return (~data) & wgp_bitmask; 9259 } 9260 9261 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9262 { 9263 u32 wgp_idx, wgp_active_bitmap; 9264 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9265 9266 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9267 cu_active_bitmap = 0; 9268 9269 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9270 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9271 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9272 if (wgp_active_bitmap & (1 << wgp_idx)) 9273 cu_active_bitmap |= cu_bitmap_per_wgp; 9274 } 9275 9276 return cu_active_bitmap; 9277 } 9278 9279 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9280 struct amdgpu_cu_info *cu_info) 9281 { 9282 int i, j, k, counter, active_cu_number = 0; 9283 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9284 unsigned disable_masks[4 * 2]; 9285 9286 if (!adev || !cu_info) 9287 return -EINVAL; 9288 9289 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9290 9291 mutex_lock(&adev->grbm_idx_mutex); 9292 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9293 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9294 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9295 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9296 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9297 continue; 9298 mask = 1; 9299 ao_bitmap = 0; 9300 counter = 0; 9301 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9302 if (i < 4 && j < 2) 9303 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9304 adev, disable_masks[i * 2 + j]); 9305 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9306 cu_info->bitmap[i][j] = bitmap; 9307 9308 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9309 if (bitmap & mask) { 9310 if (counter < adev->gfx.config.max_cu_per_sh) 9311 ao_bitmap |= mask; 9312 counter++; 9313 } 9314 mask <<= 1; 9315 } 9316 active_cu_number += counter; 9317 if (i < 2 && j < 2) 9318 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9319 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9320 } 9321 } 9322 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9323 mutex_unlock(&adev->grbm_idx_mutex); 9324 9325 cu_info->number = active_cu_number; 9326 cu_info->ao_cu_mask = ao_cu_mask; 9327 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9328 9329 return 0; 9330 } 9331 9332 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9333 { 9334 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9335 9336 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9337 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9338 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9339 9340 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9341 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9342 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9343 9344 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9345 adev->gfx.config.max_shader_engines); 9346 disabled_sa = efuse_setting | vbios_setting; 9347 disabled_sa &= max_sa_mask; 9348 9349 return disabled_sa; 9350 } 9351 9352 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9353 { 9354 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9355 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9356 9357 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9358 9359 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9360 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9361 max_shader_engines = adev->gfx.config.max_shader_engines; 9362 9363 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9364 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9365 disabled_sa_per_se &= max_sa_per_se_mask; 9366 if (disabled_sa_per_se == max_sa_per_se_mask) { 9367 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9368 break; 9369 } 9370 } 9371 } 9372 9373 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9374 { 9375 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9376 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9377 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9378 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9379 9380 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9381 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9382 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9383 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9384 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9385 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9386 9387 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9388 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9389 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9390 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9391 9392 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9393 9394 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9395 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9396 } 9397 9398 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9399 { 9400 .type = AMD_IP_BLOCK_TYPE_GFX, 9401 .major = 10, 9402 .minor = 0, 9403 .rev = 0, 9404 .funcs = &gfx_v10_0_ip_funcs, 9405 }; 9406