1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "gfx_v10_0_cleaner_shader.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 372 /* SE status registers */ 373 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 374 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 375 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 376 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 377 }; 378 379 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 380 /* compute registers */ 381 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 382 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 383 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 384 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 385 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS), 420 /* cp header registers */ 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 425 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 426 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 427 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 428 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 429 }; 430 431 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 432 /* gfx queue registers */ 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 452 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 453 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 454 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 455 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), 456 /* gfx header registers */ 457 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 458 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 459 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 460 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 461 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 462 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 463 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 464 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 465 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 466 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 467 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 468 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 469 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 470 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 471 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 472 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 473 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 474 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 475 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 476 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 477 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 478 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 479 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 480 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 481 }; 482 483 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 524 }; 525 526 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 527 /* Pending on emulation bring up */ 528 }; 529 530 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1583 }; 1584 1585 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1624 }; 1625 1626 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1669 }; 1670 1671 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1672 /* Pending on emulation bring up */ 1673 }; 1674 1675 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2296 }; 2297 2298 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2299 /* Pending on emulation bring up */ 2300 }; 2301 2302 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3355 }; 3356 3357 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3401 }; 3402 3403 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3404 /* Pending on emulation bring up */ 3405 }; 3406 3407 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3449 3450 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3452 }; 3453 3454 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3479 3480 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3482 }; 3483 3484 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3505 }; 3506 3507 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3544 }; 3545 3546 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3579 }; 3580 3581 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3616 }; 3617 3618 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3641 }; 3642 3643 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3666 }; 3667 3668 #define DEFAULT_SH_MEM_CONFIG \ 3669 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3670 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3671 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3672 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3673 3674 /* TODO: pending on golden setting value of gb address config */ 3675 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3676 3677 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3678 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3679 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3680 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3681 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3682 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3683 struct amdgpu_cu_info *cu_info); 3684 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3685 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3686 u32 sh_num, u32 instance, int xcc_id); 3687 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3688 3689 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3690 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3691 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3692 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3693 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3694 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3695 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3696 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3697 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3698 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3699 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3700 uint16_t pasid, uint32_t flush_type, 3701 bool all_hub, uint8_t dst_sel); 3702 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3703 unsigned int vmid); 3704 3705 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3706 enum amd_powergating_state state); 3707 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3708 { 3709 struct amdgpu_device *adev = kiq_ring->adev; 3710 u64 shader_mc_addr; 3711 3712 /* Cleaner shader MC address */ 3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 3714 3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3717 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3724 } 3725 3726 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3727 struct amdgpu_ring *ring) 3728 { 3729 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3730 uint64_t wptr_addr = ring->wptr_gpu_addr; 3731 uint32_t eng_sel = 0; 3732 3733 switch (ring->funcs->type) { 3734 case AMDGPU_RING_TYPE_COMPUTE: 3735 eng_sel = 0; 3736 break; 3737 case AMDGPU_RING_TYPE_GFX: 3738 eng_sel = 4; 3739 break; 3740 case AMDGPU_RING_TYPE_MES: 3741 eng_sel = 5; 3742 break; 3743 default: 3744 WARN_ON(1); 3745 } 3746 3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3748 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3750 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3751 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3752 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3753 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3754 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3755 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3756 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3757 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3758 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3759 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3760 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3761 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3762 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3763 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3764 } 3765 3766 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3767 struct amdgpu_ring *ring, 3768 enum amdgpu_unmap_queues_action action, 3769 u64 gpu_addr, u64 seq) 3770 { 3771 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3772 3773 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3774 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3775 PACKET3_UNMAP_QUEUES_ACTION(action) | 3776 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3777 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3778 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3779 amdgpu_ring_write(kiq_ring, 3780 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3781 3782 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3783 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3784 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3785 amdgpu_ring_write(kiq_ring, seq); 3786 } else { 3787 amdgpu_ring_write(kiq_ring, 0); 3788 amdgpu_ring_write(kiq_ring, 0); 3789 amdgpu_ring_write(kiq_ring, 0); 3790 } 3791 } 3792 3793 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3794 struct amdgpu_ring *ring, 3795 u64 addr, 3796 u64 seq) 3797 { 3798 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3799 3800 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3801 amdgpu_ring_write(kiq_ring, 3802 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3803 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3804 PACKET3_QUERY_STATUS_COMMAND(2)); 3805 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3806 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3807 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3808 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3809 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3810 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3811 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3812 } 3813 3814 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3815 uint16_t pasid, uint32_t flush_type, 3816 bool all_hub) 3817 { 3818 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3819 } 3820 3821 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 3822 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 3823 uint32_t xcc_id, uint32_t vmid) 3824 { 3825 struct amdgpu_device *adev = kiq_ring->adev; 3826 unsigned i; 3827 uint32_t tmp; 3828 3829 /* enter save mode */ 3830 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3831 mutex_lock(&adev->srbm_mutex); 3832 nv_grbm_select(adev, me_id, pipe_id, queue_id, 0); 3833 3834 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 3835 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2); 3836 WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1); 3837 /* wait till dequeue take effects */ 3838 for (i = 0; i < adev->usec_timeout; i++) { 3839 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3840 break; 3841 udelay(1); 3842 } 3843 if (i >= adev->usec_timeout) 3844 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 3845 } else if (queue_type == AMDGPU_RING_TYPE_GFX) { 3846 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 3847 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 3848 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 3849 if (pipe_id == 0) 3850 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 3851 else 3852 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 3853 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp); 3854 3855 /* wait till dequeue take effects */ 3856 for (i = 0; i < adev->usec_timeout; i++) { 3857 if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1)) 3858 break; 3859 udelay(1); 3860 } 3861 if (i >= adev->usec_timeout) 3862 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 3863 } else { 3864 dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type); 3865 } 3866 3867 nv_grbm_select(adev, 0, 0, 0, 0); 3868 mutex_unlock(&adev->srbm_mutex); 3869 /* exit safe mode */ 3870 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 3871 } 3872 3873 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3874 .kiq_set_resources = gfx10_kiq_set_resources, 3875 .kiq_map_queues = gfx10_kiq_map_queues, 3876 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3877 .kiq_query_status = gfx10_kiq_query_status, 3878 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3879 .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue, 3880 .set_resources_size = 8, 3881 .map_queues_size = 7, 3882 .unmap_queues_size = 6, 3883 .query_status_size = 7, 3884 .invalidate_tlbs_size = 2, 3885 }; 3886 3887 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3888 { 3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3890 } 3891 3892 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3893 { 3894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3895 case IP_VERSION(10, 1, 10): 3896 soc15_program_register_sequence(adev, 3897 golden_settings_gc_rlc_spm_10_0_nv10, 3898 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3899 break; 3900 case IP_VERSION(10, 1, 1): 3901 soc15_program_register_sequence(adev, 3902 golden_settings_gc_rlc_spm_10_1_nv14, 3903 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3904 break; 3905 case IP_VERSION(10, 1, 2): 3906 soc15_program_register_sequence(adev, 3907 golden_settings_gc_rlc_spm_10_1_2_nv12, 3908 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3909 break; 3910 default: 3911 break; 3912 } 3913 } 3914 3915 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3916 { 3917 if (amdgpu_sriov_vf(adev)) 3918 return; 3919 3920 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3921 case IP_VERSION(10, 1, 10): 3922 soc15_program_register_sequence(adev, 3923 golden_settings_gc_10_1, 3924 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3925 soc15_program_register_sequence(adev, 3926 golden_settings_gc_10_0_nv10, 3927 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3928 break; 3929 case IP_VERSION(10, 1, 1): 3930 soc15_program_register_sequence(adev, 3931 golden_settings_gc_10_1_1, 3932 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3933 soc15_program_register_sequence(adev, 3934 golden_settings_gc_10_1_nv14, 3935 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3936 break; 3937 case IP_VERSION(10, 1, 2): 3938 soc15_program_register_sequence(adev, 3939 golden_settings_gc_10_1_2, 3940 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3941 soc15_program_register_sequence(adev, 3942 golden_settings_gc_10_1_2_nv12, 3943 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3944 break; 3945 case IP_VERSION(10, 3, 0): 3946 soc15_program_register_sequence(adev, 3947 golden_settings_gc_10_3, 3948 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3949 soc15_program_register_sequence(adev, 3950 golden_settings_gc_10_3_sienna_cichlid, 3951 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3952 break; 3953 case IP_VERSION(10, 3, 2): 3954 soc15_program_register_sequence(adev, 3955 golden_settings_gc_10_3_2, 3956 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3957 break; 3958 case IP_VERSION(10, 3, 1): 3959 soc15_program_register_sequence(adev, 3960 golden_settings_gc_10_3_vangogh, 3961 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3962 break; 3963 case IP_VERSION(10, 3, 3): 3964 soc15_program_register_sequence(adev, 3965 golden_settings_gc_10_3_3, 3966 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3967 break; 3968 case IP_VERSION(10, 3, 4): 3969 soc15_program_register_sequence(adev, 3970 golden_settings_gc_10_3_4, 3971 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3972 break; 3973 case IP_VERSION(10, 3, 5): 3974 soc15_program_register_sequence(adev, 3975 golden_settings_gc_10_3_5, 3976 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3977 break; 3978 case IP_VERSION(10, 1, 3): 3979 case IP_VERSION(10, 1, 4): 3980 soc15_program_register_sequence(adev, 3981 golden_settings_gc_10_0_cyan_skillfish, 3982 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3983 break; 3984 case IP_VERSION(10, 3, 6): 3985 soc15_program_register_sequence(adev, 3986 golden_settings_gc_10_3_6, 3987 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3988 break; 3989 case IP_VERSION(10, 3, 7): 3990 soc15_program_register_sequence(adev, 3991 golden_settings_gc_10_3_7, 3992 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3993 break; 3994 default: 3995 break; 3996 } 3997 gfx_v10_0_init_spm_golden_registers(adev); 3998 } 3999 4000 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 4001 bool wc, uint32_t reg, uint32_t val) 4002 { 4003 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4004 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 4006 amdgpu_ring_write(ring, reg); 4007 amdgpu_ring_write(ring, 0); 4008 amdgpu_ring_write(ring, val); 4009 } 4010 4011 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 4012 int mem_space, int opt, uint32_t addr0, 4013 uint32_t addr1, uint32_t ref, uint32_t mask, 4014 uint32_t inv) 4015 { 4016 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4017 amdgpu_ring_write(ring, 4018 /* memory (1) or register (0) */ 4019 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 4020 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 4021 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 4022 WAIT_REG_MEM_ENGINE(eng_sel))); 4023 4024 if (mem_space) 4025 WARN_ON(addr0 & 0x3); /* Dword align */ 4026 amdgpu_ring_write(ring, addr0); 4027 amdgpu_ring_write(ring, addr1); 4028 amdgpu_ring_write(ring, ref); 4029 amdgpu_ring_write(ring, mask); 4030 amdgpu_ring_write(ring, inv); /* poll interval */ 4031 } 4032 4033 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 4034 { 4035 struct amdgpu_device *adev = ring->adev; 4036 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4037 uint32_t tmp = 0; 4038 unsigned int i; 4039 int r; 4040 4041 WREG32(scratch, 0xCAFEDEAD); 4042 r = amdgpu_ring_alloc(ring, 3); 4043 if (r) { 4044 drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", 4045 ring->idx, r); 4046 return r; 4047 } 4048 4049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 4050 amdgpu_ring_write(ring, scratch - 4051 PACKET3_SET_UCONFIG_REG_START); 4052 amdgpu_ring_write(ring, 0xDEADBEEF); 4053 amdgpu_ring_commit(ring); 4054 4055 for (i = 0; i < adev->usec_timeout; i++) { 4056 tmp = RREG32(scratch); 4057 if (tmp == 0xDEADBEEF) 4058 break; 4059 if (amdgpu_emu_mode == 1) 4060 msleep(1); 4061 else 4062 udelay(1); 4063 } 4064 4065 if (i >= adev->usec_timeout) 4066 r = -ETIMEDOUT; 4067 4068 return r; 4069 } 4070 4071 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 4072 { 4073 struct amdgpu_device *adev = ring->adev; 4074 struct amdgpu_ib ib; 4075 struct dma_fence *f = NULL; 4076 unsigned int index; 4077 uint64_t gpu_addr; 4078 uint32_t *cpu_ptr; 4079 long r; 4080 4081 memset(&ib, 0, sizeof(ib)); 4082 4083 r = amdgpu_device_wb_get(adev, &index); 4084 if (r) 4085 return r; 4086 4087 gpu_addr = adev->wb.gpu_addr + (index * 4); 4088 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4089 cpu_ptr = &adev->wb.wb[index]; 4090 4091 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4092 if (r) { 4093 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 4094 goto err1; 4095 } 4096 4097 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4099 ib.ptr[2] = lower_32_bits(gpu_addr); 4100 ib.ptr[3] = upper_32_bits(gpu_addr); 4101 ib.ptr[4] = 0xDEADBEEF; 4102 ib.length_dw = 5; 4103 4104 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4105 if (r) 4106 goto err2; 4107 4108 r = dma_fence_wait_timeout(f, false, timeout); 4109 if (r == 0) { 4110 r = -ETIMEDOUT; 4111 goto err2; 4112 } else if (r < 0) { 4113 goto err2; 4114 } 4115 4116 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4117 r = 0; 4118 else 4119 r = -EINVAL; 4120 err2: 4121 amdgpu_ib_free(&ib, NULL); 4122 dma_fence_put(f); 4123 err1: 4124 amdgpu_device_wb_free(adev, index); 4125 return r; 4126 } 4127 4128 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4129 { 4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4131 amdgpu_ucode_release(&adev->gfx.me_fw); 4132 amdgpu_ucode_release(&adev->gfx.ce_fw); 4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4134 amdgpu_ucode_release(&adev->gfx.mec_fw); 4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4136 4137 kfree(adev->gfx.rlc.register_list_format); 4138 } 4139 4140 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4141 { 4142 adev->gfx.cp_fw_write_wait = false; 4143 4144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4145 case IP_VERSION(10, 1, 10): 4146 case IP_VERSION(10, 1, 2): 4147 case IP_VERSION(10, 1, 1): 4148 case IP_VERSION(10, 1, 3): 4149 case IP_VERSION(10, 1, 4): 4150 if ((adev->gfx.me_fw_version >= 0x00000046) && 4151 (adev->gfx.me_feature_version >= 27) && 4152 (adev->gfx.pfp_fw_version >= 0x00000068) && 4153 (adev->gfx.pfp_feature_version >= 27) && 4154 (adev->gfx.mec_fw_version >= 0x0000005b) && 4155 (adev->gfx.mec_feature_version >= 27)) 4156 adev->gfx.cp_fw_write_wait = true; 4157 break; 4158 case IP_VERSION(10, 3, 0): 4159 case IP_VERSION(10, 3, 2): 4160 case IP_VERSION(10, 3, 1): 4161 case IP_VERSION(10, 3, 4): 4162 case IP_VERSION(10, 3, 5): 4163 case IP_VERSION(10, 3, 6): 4164 case IP_VERSION(10, 3, 3): 4165 case IP_VERSION(10, 3, 7): 4166 adev->gfx.cp_fw_write_wait = true; 4167 break; 4168 default: 4169 break; 4170 } 4171 4172 if (!adev->gfx.cp_fw_write_wait) 4173 drm_warn_once(adev_to_drm(adev), "CP firmware version too old, please update!"); 4174 } 4175 4176 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4177 { 4178 bool ret = false; 4179 4180 switch (adev->pdev->revision) { 4181 case 0xc2: 4182 case 0xc3: 4183 ret = true; 4184 break; 4185 default: 4186 ret = false; 4187 break; 4188 } 4189 4190 return ret; 4191 } 4192 4193 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4194 { 4195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4196 case IP_VERSION(10, 1, 10): 4197 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4198 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4199 break; 4200 default: 4201 break; 4202 } 4203 } 4204 4205 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4206 { 4207 char fw_name[53]; 4208 char ucode_prefix[30]; 4209 const char *wks = ""; 4210 int err; 4211 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4212 uint16_t version_major; 4213 uint16_t version_minor; 4214 4215 DRM_DEBUG("\n"); 4216 4217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4218 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4219 wks = "_wks"; 4220 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4221 4222 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4223 AMDGPU_UCODE_REQUIRED, 4224 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4225 if (err) 4226 goto out; 4227 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4228 4229 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4230 AMDGPU_UCODE_REQUIRED, 4231 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4232 if (err) 4233 goto out; 4234 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4235 4236 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4237 AMDGPU_UCODE_REQUIRED, 4238 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4239 if (err) 4240 goto out; 4241 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4242 4243 if (!amdgpu_sriov_vf(adev)) { 4244 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4245 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4246 if (err) 4247 goto out; 4248 4249 /* don't validate this firmware. There are apparently firmwares 4250 * in the wild with incorrect size in the header 4251 */ 4252 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4253 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4254 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4255 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4256 if (err) 4257 goto out; 4258 } 4259 4260 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4261 AMDGPU_UCODE_REQUIRED, 4262 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4263 if (err) 4264 goto out; 4265 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4266 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4267 4268 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4269 AMDGPU_UCODE_REQUIRED, 4270 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4271 if (!err) { 4272 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4274 } else { 4275 err = 0; 4276 adev->gfx.mec2_fw = NULL; 4277 } 4278 4279 gfx_v10_0_check_fw_write_wait(adev); 4280 out: 4281 if (err) { 4282 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4283 amdgpu_ucode_release(&adev->gfx.me_fw); 4284 amdgpu_ucode_release(&adev->gfx.ce_fw); 4285 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4286 amdgpu_ucode_release(&adev->gfx.mec_fw); 4287 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4288 } 4289 4290 gfx_v10_0_check_gfxoff_flag(adev); 4291 4292 return err; 4293 } 4294 4295 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4296 { 4297 u32 count = 0; 4298 const struct cs_section_def *sect = NULL; 4299 const struct cs_extent_def *ext = NULL; 4300 4301 /* begin clear state */ 4302 count += 2; 4303 /* context control state */ 4304 count += 3; 4305 4306 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4307 for (ext = sect->section; ext->extent != NULL; ++ext) { 4308 if (sect->id == SECT_CONTEXT) 4309 count += 2 + ext->reg_count; 4310 else 4311 return 0; 4312 } 4313 } 4314 4315 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4316 count += 3; 4317 /* end clear state */ 4318 count += 2; 4319 /* clear state */ 4320 count += 2; 4321 4322 return count; 4323 } 4324 4325 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 4326 { 4327 u32 count = 0; 4328 int ctx_reg_offset; 4329 4330 if (adev->gfx.rlc.cs_data == NULL) 4331 return; 4332 if (buffer == NULL) 4333 return; 4334 4335 count = amdgpu_gfx_csb_preamble_start(buffer); 4336 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 4337 4338 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4339 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4340 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4341 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4342 4343 amdgpu_gfx_csb_preamble_end(buffer, count); 4344 } 4345 4346 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4347 { 4348 /* clear state block */ 4349 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4350 &adev->gfx.rlc.clear_state_gpu_addr, 4351 (void **)&adev->gfx.rlc.cs_ptr); 4352 4353 /* jump table block */ 4354 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4355 &adev->gfx.rlc.cp_table_gpu_addr, 4356 (void **)&adev->gfx.rlc.cp_table_ptr); 4357 } 4358 4359 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4360 { 4361 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4362 4363 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4364 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4365 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4366 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4367 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4368 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4369 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4371 case IP_VERSION(10, 3, 0): 4372 reg_access_ctrl->spare_int = 4373 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4374 break; 4375 default: 4376 reg_access_ctrl->spare_int = 4377 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4378 break; 4379 } 4380 adev->gfx.rlc.rlcg_reg_access_supported = true; 4381 } 4382 4383 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4384 { 4385 const struct cs_section_def *cs_data; 4386 int r; 4387 4388 adev->gfx.rlc.cs_data = gfx10_cs_data; 4389 4390 cs_data = adev->gfx.rlc.cs_data; 4391 4392 if (cs_data) { 4393 /* init clear state block */ 4394 r = amdgpu_gfx_rlc_init_csb(adev); 4395 if (r) 4396 return r; 4397 } 4398 4399 return 0; 4400 } 4401 4402 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4403 { 4404 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4405 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4406 } 4407 4408 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4409 { 4410 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4411 4412 amdgpu_gfx_graphics_queue_acquire(adev); 4413 } 4414 4415 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4416 { 4417 int r; 4418 u32 *hpd; 4419 const __le32 *fw_data = NULL; 4420 unsigned int fw_size; 4421 u32 *fw = NULL; 4422 size_t mec_hpd_size; 4423 4424 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4425 4426 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4427 4428 /* take ownership of the relevant compute queues */ 4429 amdgpu_gfx_compute_queue_acquire(adev); 4430 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4431 4432 if (mec_hpd_size) { 4433 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4434 AMDGPU_GEM_DOMAIN_GTT, 4435 &adev->gfx.mec.hpd_eop_obj, 4436 &adev->gfx.mec.hpd_eop_gpu_addr, 4437 (void **)&hpd); 4438 if (r) { 4439 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4440 gfx_v10_0_mec_fini(adev); 4441 return r; 4442 } 4443 4444 memset(hpd, 0, mec_hpd_size); 4445 4446 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4447 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4448 } 4449 4450 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4451 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4452 4453 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4454 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4455 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4456 4457 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4459 &adev->gfx.mec.mec_fw_obj, 4460 &adev->gfx.mec.mec_fw_gpu_addr, 4461 (void **)&fw); 4462 if (r) { 4463 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4464 gfx_v10_0_mec_fini(adev); 4465 return r; 4466 } 4467 4468 memcpy(fw, fw_data, fw_size); 4469 4470 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4472 } 4473 4474 return 0; 4475 } 4476 4477 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4478 { 4479 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4480 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4481 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4482 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4483 } 4484 4485 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4486 uint32_t thread, uint32_t regno, 4487 uint32_t num, uint32_t *out) 4488 { 4489 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4490 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4491 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4492 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4493 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4494 while (num--) 4495 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4496 } 4497 4498 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4499 { 4500 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4501 * field when performing a select_se_sh so it should be 4502 * zero here 4503 */ 4504 WARN_ON(simd != 0); 4505 4506 /* type 2 wave data */ 4507 dst[(*no_fields)++] = 2; 4508 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4513 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4514 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4515 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4516 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4517 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4518 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4519 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4520 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4521 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4522 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4523 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4524 } 4525 4526 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4527 uint32_t wave, uint32_t start, 4528 uint32_t size, uint32_t *dst) 4529 { 4530 WARN_ON(simd != 0); 4531 4532 wave_read_regs( 4533 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4534 dst); 4535 } 4536 4537 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4538 uint32_t wave, uint32_t thread, 4539 uint32_t start, uint32_t size, 4540 uint32_t *dst) 4541 { 4542 wave_read_regs( 4543 adev, wave, thread, 4544 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4545 } 4546 4547 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4548 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4549 { 4550 nv_grbm_select(adev, me, pipe, q, vm); 4551 } 4552 4553 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4554 bool enable) 4555 { 4556 uint32_t data, def; 4557 4558 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4559 4560 if (enable) 4561 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4562 else 4563 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4564 4565 if (data != def) 4566 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4567 } 4568 4569 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4570 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4571 .select_se_sh = &gfx_v10_0_select_se_sh, 4572 .read_wave_data = &gfx_v10_0_read_wave_data, 4573 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4574 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4575 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4576 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4577 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4578 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 4579 }; 4580 4581 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4582 { 4583 u32 gb_addr_config; 4584 4585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4586 case IP_VERSION(10, 1, 10): 4587 case IP_VERSION(10, 1, 1): 4588 case IP_VERSION(10, 1, 2): 4589 adev->gfx.config.max_hw_contexts = 8; 4590 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4591 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4592 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4593 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4594 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4595 break; 4596 case IP_VERSION(10, 3, 0): 4597 case IP_VERSION(10, 3, 2): 4598 case IP_VERSION(10, 3, 1): 4599 case IP_VERSION(10, 3, 4): 4600 case IP_VERSION(10, 3, 5): 4601 case IP_VERSION(10, 3, 6): 4602 case IP_VERSION(10, 3, 3): 4603 case IP_VERSION(10, 3, 7): 4604 adev->gfx.config.max_hw_contexts = 8; 4605 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4606 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4607 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4608 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4609 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4610 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4611 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4612 break; 4613 case IP_VERSION(10, 1, 3): 4614 case IP_VERSION(10, 1, 4): 4615 adev->gfx.config.max_hw_contexts = 8; 4616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4617 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4620 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4621 break; 4622 default: 4623 BUG(); 4624 break; 4625 } 4626 4627 adev->gfx.config.gb_addr_config = gb_addr_config; 4628 4629 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4630 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4631 GB_ADDR_CONFIG, NUM_PIPES); 4632 4633 adev->gfx.config.max_tile_pipes = 4634 adev->gfx.config.gb_addr_config_fields.num_pipes; 4635 4636 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4637 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4638 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4639 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4640 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4641 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4642 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4643 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4644 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4645 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4646 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4647 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4648 } 4649 4650 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4651 int me, int pipe, int queue) 4652 { 4653 struct amdgpu_ring *ring; 4654 unsigned int irq_type; 4655 unsigned int hw_prio; 4656 4657 ring = &adev->gfx.gfx_ring[ring_id]; 4658 4659 ring->me = me; 4660 ring->pipe = pipe; 4661 ring->queue = queue; 4662 4663 ring->ring_obj = NULL; 4664 ring->use_doorbell = true; 4665 4666 if (!ring_id) 4667 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4668 else 4669 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4670 ring->vm_hub = AMDGPU_GFXHUB(0); 4671 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4672 4673 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4674 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4675 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4676 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4677 hw_prio, NULL); 4678 } 4679 4680 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4681 int mec, int pipe, int queue) 4682 { 4683 unsigned int irq_type; 4684 struct amdgpu_ring *ring; 4685 unsigned int hw_prio; 4686 4687 ring = &adev->gfx.compute_ring[ring_id]; 4688 4689 /* mec0 is me1 */ 4690 ring->me = mec + 1; 4691 ring->pipe = pipe; 4692 ring->queue = queue; 4693 4694 ring->ring_obj = NULL; 4695 ring->use_doorbell = true; 4696 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4697 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4698 + (ring_id * GFX10_MEC_HPD_SIZE); 4699 ring->vm_hub = AMDGPU_GFXHUB(0); 4700 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4701 4702 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4703 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4704 + ring->pipe; 4705 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4706 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4707 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4708 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4709 hw_prio, NULL); 4710 } 4711 4712 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4713 { 4714 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4715 uint32_t *ptr; 4716 uint32_t inst; 4717 4718 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4719 if (!ptr) { 4720 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4721 adev->gfx.ip_dump_core = NULL; 4722 } else { 4723 adev->gfx.ip_dump_core = ptr; 4724 } 4725 4726 /* Allocate memory for compute queue registers for all the instances */ 4727 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4728 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4729 adev->gfx.mec.num_queue_per_pipe; 4730 4731 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4732 if (!ptr) { 4733 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4734 adev->gfx.ip_dump_compute_queues = NULL; 4735 } else { 4736 adev->gfx.ip_dump_compute_queues = ptr; 4737 } 4738 4739 /* Allocate memory for gfx queue registers for all the instances */ 4740 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4741 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4742 adev->gfx.me.num_queue_per_pipe; 4743 4744 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4745 if (!ptr) { 4746 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4747 adev->gfx.ip_dump_gfx_queues = NULL; 4748 } else { 4749 adev->gfx.ip_dump_gfx_queues = ptr; 4750 } 4751 } 4752 4753 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 4754 { 4755 int i, j, k, r, ring_id = 0; 4756 int xcc_id = 0; 4757 struct amdgpu_device *adev = ip_block->adev; 4758 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 4759 4760 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 4761 4762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4763 case IP_VERSION(10, 1, 10): 4764 case IP_VERSION(10, 1, 1): 4765 case IP_VERSION(10, 1, 2): 4766 case IP_VERSION(10, 1, 3): 4767 case IP_VERSION(10, 1, 4): 4768 adev->gfx.me.num_me = 1; 4769 adev->gfx.me.num_pipe_per_me = 1; 4770 adev->gfx.me.num_queue_per_pipe = 8; 4771 adev->gfx.mec.num_mec = 2; 4772 adev->gfx.mec.num_pipe_per_mec = 4; 4773 adev->gfx.mec.num_queue_per_pipe = 8; 4774 break; 4775 case IP_VERSION(10, 3, 0): 4776 case IP_VERSION(10, 3, 2): 4777 case IP_VERSION(10, 3, 1): 4778 case IP_VERSION(10, 3, 4): 4779 case IP_VERSION(10, 3, 5): 4780 case IP_VERSION(10, 3, 6): 4781 case IP_VERSION(10, 3, 3): 4782 case IP_VERSION(10, 3, 7): 4783 adev->gfx.me.num_me = 1; 4784 adev->gfx.me.num_pipe_per_me = 2; 4785 adev->gfx.me.num_queue_per_pipe = 2; 4786 adev->gfx.mec.num_mec = 2; 4787 adev->gfx.mec.num_pipe_per_mec = 4; 4788 adev->gfx.mec.num_queue_per_pipe = 4; 4789 break; 4790 default: 4791 adev->gfx.me.num_me = 1; 4792 adev->gfx.me.num_pipe_per_me = 1; 4793 adev->gfx.me.num_queue_per_pipe = 1; 4794 adev->gfx.mec.num_mec = 1; 4795 adev->gfx.mec.num_pipe_per_mec = 4; 4796 adev->gfx.mec.num_queue_per_pipe = 8; 4797 break; 4798 } 4799 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4800 case IP_VERSION(10, 1, 10): 4801 case IP_VERSION(10, 1, 1): 4802 case IP_VERSION(10, 1, 2): 4803 adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex; 4804 adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex); 4805 if (adev->gfx.me_fw_version >= 101 && 4806 adev->gfx.pfp_fw_version >= 158 && 4807 adev->gfx.mec_fw_version >= 151) { 4808 adev->gfx.enable_cleaner_shader = true; 4809 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4810 if (r) { 4811 adev->gfx.enable_cleaner_shader = false; 4812 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4813 } 4814 } 4815 break; 4816 case IP_VERSION(10, 3, 0): 4817 case IP_VERSION(10, 3, 1): 4818 case IP_VERSION(10, 3, 2): 4819 case IP_VERSION(10, 3, 3): 4820 case IP_VERSION(10, 3, 4): 4821 case IP_VERSION(10, 3, 5): 4822 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4823 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4824 if (adev->gfx.me_fw_version >= 64 && 4825 adev->gfx.pfp_fw_version >= 100 && 4826 adev->gfx.mec_fw_version >= 122) { 4827 adev->gfx.enable_cleaner_shader = true; 4828 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4829 if (r) { 4830 adev->gfx.enable_cleaner_shader = false; 4831 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4832 } 4833 } 4834 break; 4835 case IP_VERSION(10, 3, 6): 4836 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4837 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4838 if (adev->gfx.me_fw_version >= 14 && 4839 adev->gfx.pfp_fw_version >= 17 && 4840 adev->gfx.mec_fw_version >= 24) { 4841 adev->gfx.enable_cleaner_shader = true; 4842 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4843 if (r) { 4844 adev->gfx.enable_cleaner_shader = false; 4845 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4846 } 4847 } 4848 break; 4849 case IP_VERSION(10, 3, 7): 4850 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4851 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4852 if (adev->gfx.me_fw_version >= 4 && 4853 adev->gfx.pfp_fw_version >= 9 && 4854 adev->gfx.mec_fw_version >= 12) { 4855 adev->gfx.enable_cleaner_shader = true; 4856 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4857 if (r) { 4858 adev->gfx.enable_cleaner_shader = false; 4859 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4860 } 4861 } 4862 break; 4863 default: 4864 adev->gfx.enable_cleaner_shader = false; 4865 break; 4866 } 4867 4868 /* KIQ event */ 4869 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4870 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4871 &adev->gfx.kiq[0].irq); 4872 if (r) 4873 return r; 4874 4875 /* EOP Event */ 4876 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4877 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4878 &adev->gfx.eop_irq); 4879 if (r) 4880 return r; 4881 4882 /* Bad opcode Event */ 4883 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4884 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4885 &adev->gfx.bad_op_irq); 4886 if (r) 4887 return r; 4888 4889 /* Privileged reg */ 4890 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4891 &adev->gfx.priv_reg_irq); 4892 if (r) 4893 return r; 4894 4895 /* Privileged inst */ 4896 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4897 &adev->gfx.priv_inst_irq); 4898 if (r) 4899 return r; 4900 4901 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4902 4903 gfx_v10_0_me_init(adev); 4904 4905 if (adev->gfx.rlc.funcs) { 4906 if (adev->gfx.rlc.funcs->init) { 4907 r = adev->gfx.rlc.funcs->init(adev); 4908 if (r) { 4909 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4910 return r; 4911 } 4912 } 4913 } 4914 4915 r = gfx_v10_0_mec_init(adev); 4916 if (r) { 4917 DRM_ERROR("Failed to init MEC BOs!\n"); 4918 return r; 4919 } 4920 4921 /* set up the gfx ring */ 4922 for (i = 0; i < adev->gfx.me.num_me; i++) { 4923 for (j = 0; j < num_queue_per_pipe; j++) { 4924 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4925 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4926 continue; 4927 4928 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4929 i, k, j); 4930 if (r) 4931 return r; 4932 ring_id++; 4933 } 4934 } 4935 } 4936 4937 ring_id = 0; 4938 /* set up the compute queues - allocate horizontally across pipes */ 4939 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4940 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4941 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4942 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4943 k, j)) 4944 continue; 4945 4946 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4947 i, k, j); 4948 if (r) 4949 return r; 4950 4951 ring_id++; 4952 } 4953 } 4954 } 4955 4956 adev->gfx.gfx_supported_reset = 4957 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4958 adev->gfx.compute_supported_reset = 4959 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4960 if (!amdgpu_sriov_vf(adev) && 4961 !adev->debug_disable_gpu_ring_reset) { 4962 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4963 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4964 } 4965 4966 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4967 if (r) { 4968 DRM_ERROR("Failed to init KIQ BOs!\n"); 4969 return r; 4970 } 4971 4972 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4973 if (r) 4974 return r; 4975 4976 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4977 if (r) 4978 return r; 4979 4980 /* allocate visible FB for rlc auto-loading fw */ 4981 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4982 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4983 if (r) 4984 return r; 4985 } 4986 4987 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4988 4989 gfx_v10_0_gpu_early_init(adev); 4990 4991 gfx_v10_0_alloc_ip_dump(adev); 4992 4993 r = amdgpu_gfx_sysfs_init(adev); 4994 if (r) 4995 return r; 4996 4997 return 0; 4998 } 4999 5000 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 5001 { 5002 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 5003 &adev->gfx.pfp.pfp_fw_gpu_addr, 5004 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5005 } 5006 5007 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 5008 { 5009 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 5010 &adev->gfx.ce.ce_fw_gpu_addr, 5011 (void **)&adev->gfx.ce.ce_fw_ptr); 5012 } 5013 5014 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 5015 { 5016 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 5017 &adev->gfx.me.me_fw_gpu_addr, 5018 (void **)&adev->gfx.me.me_fw_ptr); 5019 } 5020 5021 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 5022 { 5023 int i; 5024 struct amdgpu_device *adev = ip_block->adev; 5025 5026 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5027 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 5028 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5029 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 5030 5031 amdgpu_gfx_mqd_sw_fini(adev, 0); 5032 5033 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 5034 amdgpu_gfx_kiq_fini(adev, 0); 5035 5036 amdgpu_gfx_cleaner_shader_sw_fini(adev); 5037 5038 gfx_v10_0_pfp_fini(adev); 5039 gfx_v10_0_ce_fini(adev); 5040 gfx_v10_0_me_fini(adev); 5041 gfx_v10_0_rlc_fini(adev); 5042 gfx_v10_0_mec_fini(adev); 5043 5044 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 5045 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 5046 5047 gfx_v10_0_free_microcode(adev); 5048 amdgpu_gfx_sysfs_fini(adev); 5049 5050 kfree(adev->gfx.ip_dump_core); 5051 kfree(adev->gfx.ip_dump_compute_queues); 5052 kfree(adev->gfx.ip_dump_gfx_queues); 5053 5054 return 0; 5055 } 5056 5057 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 5058 u32 sh_num, u32 instance, int xcc_id) 5059 { 5060 u32 data; 5061 5062 if (instance == 0xffffffff) 5063 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 5064 INSTANCE_BROADCAST_WRITES, 1); 5065 else 5066 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 5067 instance); 5068 5069 if (se_num == 0xffffffff) 5070 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 5071 1); 5072 else 5073 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 5074 5075 if (sh_num == 0xffffffff) 5076 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 5077 1); 5078 else 5079 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 5080 5081 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 5082 } 5083 5084 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 5085 { 5086 u32 data, mask; 5087 5088 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5089 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5090 5091 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5092 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5093 5094 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5095 adev->gfx.config.max_sh_per_se); 5096 5097 return (~data) & mask; 5098 } 5099 5100 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5101 { 5102 int i, j; 5103 u32 data; 5104 u32 active_rbs = 0; 5105 u32 bitmap; 5106 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5107 adev->gfx.config.max_sh_per_se; 5108 5109 mutex_lock(&adev->grbm_idx_mutex); 5110 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5111 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5112 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5113 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 5114 IP_VERSION(10, 3, 0)) || 5115 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5116 IP_VERSION(10, 3, 3)) || 5117 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5118 IP_VERSION(10, 3, 6))) && 5119 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5120 continue; 5121 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5122 data = gfx_v10_0_get_rb_active_bitmap(adev); 5123 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5124 rb_bitmap_width_per_sh); 5125 } 5126 } 5127 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5128 mutex_unlock(&adev->grbm_idx_mutex); 5129 5130 adev->gfx.config.backend_enable_mask = active_rbs; 5131 adev->gfx.config.num_rbs = hweight32(active_rbs); 5132 } 5133 5134 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5135 { 5136 uint32_t num_sc; 5137 uint32_t enabled_rb_per_sh; 5138 uint32_t active_rb_bitmap; 5139 uint32_t num_rb_per_sc; 5140 uint32_t num_packer_per_sc; 5141 uint32_t pa_sc_tile_steering_override; 5142 5143 /* for ASICs that integrates GFX v10.3 5144 * pa_sc_tile_steering_override should be set to 0 5145 */ 5146 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 5147 return 0; 5148 5149 /* init num_sc */ 5150 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5151 adev->gfx.config.num_sc_per_sh; 5152 /* init num_rb_per_sc */ 5153 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5154 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5155 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5156 /* init num_packer_per_sc */ 5157 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5158 5159 pa_sc_tile_steering_override = 0; 5160 pa_sc_tile_steering_override |= 5161 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5162 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5163 pa_sc_tile_steering_override |= 5164 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5165 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5166 pa_sc_tile_steering_override |= 5167 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5168 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5169 5170 return pa_sc_tile_steering_override; 5171 } 5172 5173 #define DEFAULT_SH_MEM_BASES (0x6000) 5174 5175 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5176 uint32_t first_vmid, 5177 uint32_t last_vmid) 5178 { 5179 uint32_t data; 5180 uint32_t trap_config_vmid_mask = 0; 5181 int i; 5182 5183 /* Calculate trap config vmid mask */ 5184 for (i = first_vmid; i < last_vmid; i++) 5185 trap_config_vmid_mask |= (1 << i); 5186 5187 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5188 VMID_SEL, trap_config_vmid_mask); 5189 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5190 TRAP_EN, 1); 5191 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5192 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5193 5194 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5195 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5196 } 5197 5198 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5199 { 5200 int i; 5201 uint32_t sh_mem_bases; 5202 5203 /* 5204 * Configure apertures: 5205 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5206 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5207 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5208 */ 5209 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5210 5211 mutex_lock(&adev->srbm_mutex); 5212 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5213 nv_grbm_select(adev, 0, 0, 0, i); 5214 /* CP and shaders */ 5215 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5216 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5217 } 5218 nv_grbm_select(adev, 0, 0, 0, 0); 5219 mutex_unlock(&adev->srbm_mutex); 5220 5221 /* 5222 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5223 * access. These should be enabled by FW for target VMIDs. 5224 */ 5225 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5226 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5227 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5228 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5229 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5230 } 5231 5232 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5233 AMDGPU_NUM_VMID); 5234 } 5235 5236 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5237 { 5238 int vmid; 5239 5240 /* 5241 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5242 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5243 * the driver can enable them for graphics. VMID0 should maintain 5244 * access so that HWS firmware can save/restore entries. 5245 */ 5246 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5247 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5248 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5249 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5250 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5251 } 5252 } 5253 5254 5255 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5256 { 5257 int i, j, k; 5258 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5259 u32 tmp, wgp_active_bitmap = 0; 5260 u32 gcrd_targets_disable_tcp = 0; 5261 u32 utcl_invreq_disable = 0; 5262 /* 5263 * GCRD_TARGETS_DISABLE field contains 5264 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5265 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5266 */ 5267 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5268 2 * max_wgp_per_sh + /* TCP */ 5269 max_wgp_per_sh + /* SQC */ 5270 4); /* GL1C */ 5271 /* 5272 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5273 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5274 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5275 */ 5276 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5277 2 * max_wgp_per_sh + /* TCP */ 5278 2 * max_wgp_per_sh + /* SQC */ 5279 4 + /* RMI */ 5280 1); /* SQG */ 5281 5282 mutex_lock(&adev->grbm_idx_mutex); 5283 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5284 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5285 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5286 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5287 /* 5288 * Set corresponding TCP bits for the inactive WGPs in 5289 * GCRD_SA_TARGETS_DISABLE 5290 */ 5291 gcrd_targets_disable_tcp = 0; 5292 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5293 utcl_invreq_disable = 0; 5294 5295 for (k = 0; k < max_wgp_per_sh; k++) { 5296 if (!(wgp_active_bitmap & (1 << k))) { 5297 gcrd_targets_disable_tcp |= 3 << (2 * k); 5298 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5299 utcl_invreq_disable |= (3 << (2 * k)) | 5300 (3 << (2 * (max_wgp_per_sh + k))); 5301 } 5302 } 5303 5304 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5305 /* only override TCP & SQC bits */ 5306 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5307 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5308 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5309 5310 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5311 /* only override TCP & SQC bits */ 5312 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5313 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5314 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5315 } 5316 } 5317 5318 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5319 mutex_unlock(&adev->grbm_idx_mutex); 5320 } 5321 5322 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5323 { 5324 /* TCCs are global (not instanced). */ 5325 uint32_t tcc_disable; 5326 5327 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5328 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5329 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5330 } else { 5331 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5332 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5333 } 5334 5335 adev->gfx.config.tcc_disabled_mask = 5336 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5337 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5338 } 5339 5340 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5341 { 5342 u32 tmp; 5343 int i; 5344 5345 if (!amdgpu_sriov_vf(adev)) 5346 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5347 5348 gfx_v10_0_setup_rb(adev); 5349 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5350 gfx_v10_0_get_tcc_info(adev); 5351 adev->gfx.config.pa_sc_tile_steering_override = 5352 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5353 /* Program DB_RING_CONTROL for multiple GFX pipes 5354 * Default power up value is 1. 5355 * Possible values: 5356 * 0 - split occlusion counters between gfx pipes 5357 * 1 - all occlusion counters to pipe 0 5358 * 2 - all occlusion counters to pipe 1 5359 */ 5360 WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, 5361 (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); 5362 5363 /* XXX SH_MEM regs */ 5364 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5365 mutex_lock(&adev->srbm_mutex); 5366 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5367 nv_grbm_select(adev, 0, 0, 0, i); 5368 /* CP and shaders */ 5369 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5370 if (i != 0) { 5371 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5372 (adev->gmc.private_aperture_start >> 48)); 5373 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5374 (adev->gmc.shared_aperture_start >> 48)); 5375 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5376 } 5377 } 5378 nv_grbm_select(adev, 0, 0, 0, 0); 5379 5380 mutex_unlock(&adev->srbm_mutex); 5381 5382 gfx_v10_0_init_compute_vmid(adev); 5383 gfx_v10_0_init_gds_vmid(adev); 5384 5385 } 5386 5387 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5388 int me, int pipe) 5389 { 5390 if (me != 0) 5391 return 0; 5392 5393 switch (pipe) { 5394 case 0: 5395 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5396 case 1: 5397 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5398 default: 5399 return 0; 5400 } 5401 } 5402 5403 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5404 int me, int pipe) 5405 { 5406 /* 5407 * amdgpu controls only the first MEC. That's why this function only 5408 * handles the setting of interrupts for this specific MEC. All other 5409 * pipes' interrupts are set by amdkfd. 5410 */ 5411 if (me != 1) 5412 return 0; 5413 5414 switch (pipe) { 5415 case 0: 5416 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5417 case 1: 5418 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5419 case 2: 5420 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5421 case 3: 5422 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5423 default: 5424 return 0; 5425 } 5426 } 5427 5428 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5429 bool enable) 5430 { 5431 u32 tmp, cp_int_cntl_reg; 5432 int i, j; 5433 5434 if (amdgpu_sriov_vf(adev)) 5435 return; 5436 5437 for (i = 0; i < adev->gfx.me.num_me; i++) { 5438 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5439 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5440 5441 if (cp_int_cntl_reg) { 5442 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5443 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5444 enable ? 1 : 0); 5445 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5446 enable ? 1 : 0); 5447 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5448 enable ? 1 : 0); 5449 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5450 enable ? 1 : 0); 5451 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5452 } 5453 } 5454 } 5455 } 5456 5457 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5458 { 5459 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5460 5461 /* csib */ 5462 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5463 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5464 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5465 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5466 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5467 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5468 } else { 5469 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5470 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5471 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5472 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5473 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5474 } 5475 return 0; 5476 } 5477 5478 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5479 { 5480 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5481 5482 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5483 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5484 } 5485 5486 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5487 { 5488 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5489 udelay(50); 5490 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5491 udelay(50); 5492 } 5493 5494 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5495 bool enable) 5496 { 5497 uint32_t rlc_pg_cntl; 5498 5499 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5500 5501 if (!enable) { 5502 /* RLC_PG_CNTL[23] = 0 (default) 5503 * RLC will wait for handshake acks with SMU 5504 * GFXOFF will be enabled 5505 * RLC_PG_CNTL[23] = 1 5506 * RLC will not issue any message to SMU 5507 * hence no handshake between SMU & RLC 5508 * GFXOFF will be disabled 5509 */ 5510 rlc_pg_cntl |= 0x800000; 5511 } else 5512 rlc_pg_cntl &= ~0x800000; 5513 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5514 } 5515 5516 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5517 { 5518 /* 5519 * TODO: enable rlc & smu handshake until smu 5520 * and gfxoff feature works as expected 5521 */ 5522 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5523 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5524 5525 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5526 udelay(50); 5527 } 5528 5529 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5530 { 5531 uint32_t tmp; 5532 5533 /* enable Save Restore Machine */ 5534 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5535 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5536 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5537 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5538 } 5539 5540 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5541 { 5542 const struct rlc_firmware_header_v2_0 *hdr; 5543 const __le32 *fw_data; 5544 unsigned int i, fw_size; 5545 5546 if (!adev->gfx.rlc_fw) 5547 return -EINVAL; 5548 5549 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5550 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5551 5552 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5553 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5554 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5555 5556 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5557 RLCG_UCODE_LOADING_START_ADDRESS); 5558 5559 for (i = 0; i < fw_size; i++) 5560 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5561 le32_to_cpup(fw_data++)); 5562 5563 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5564 5565 return 0; 5566 } 5567 5568 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5569 { 5570 int r; 5571 5572 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5573 adev->psp.autoload_supported) { 5574 5575 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5576 if (r) 5577 return r; 5578 5579 gfx_v10_0_init_csb(adev); 5580 5581 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5582 5583 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5584 gfx_v10_0_rlc_enable_srm(adev); 5585 } else { 5586 if (amdgpu_sriov_vf(adev)) { 5587 gfx_v10_0_init_csb(adev); 5588 return 0; 5589 } 5590 5591 adev->gfx.rlc.funcs->stop(adev); 5592 5593 /* disable CG */ 5594 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5595 5596 /* disable PG */ 5597 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5598 5599 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5600 /* legacy rlc firmware loading */ 5601 r = gfx_v10_0_rlc_load_microcode(adev); 5602 if (r) 5603 return r; 5604 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5605 /* rlc backdoor autoload firmware */ 5606 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5607 if (r) 5608 return r; 5609 } 5610 5611 gfx_v10_0_init_csb(adev); 5612 5613 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5614 5615 adev->gfx.rlc.funcs->start(adev); 5616 5617 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5618 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5619 if (r) 5620 return r; 5621 } 5622 } 5623 5624 return 0; 5625 } 5626 5627 static struct { 5628 FIRMWARE_ID id; 5629 unsigned int offset; 5630 unsigned int size; 5631 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5632 5633 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5634 { 5635 int ret; 5636 RLC_TABLE_OF_CONTENT *rlc_toc; 5637 5638 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5639 AMDGPU_GEM_DOMAIN_GTT, 5640 &adev->gfx.rlc.rlc_toc_bo, 5641 &adev->gfx.rlc.rlc_toc_gpu_addr, 5642 (void **)&adev->gfx.rlc.rlc_toc_buf); 5643 if (ret) { 5644 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5645 return ret; 5646 } 5647 5648 /* Copy toc from psp sos fw to rlc toc buffer */ 5649 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5650 5651 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5652 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5653 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5654 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5655 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5656 /* Offset needs 4KB alignment */ 5657 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5658 } 5659 5660 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5661 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5662 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5663 5664 rlc_toc++; 5665 } 5666 5667 return 0; 5668 } 5669 5670 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5671 { 5672 uint32_t total_size = 0; 5673 FIRMWARE_ID id; 5674 int ret; 5675 5676 ret = gfx_v10_0_parse_rlc_toc(adev); 5677 if (ret) { 5678 dev_err(adev->dev, "failed to parse rlc toc\n"); 5679 return 0; 5680 } 5681 5682 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5683 total_size += rlc_autoload_info[id].size; 5684 5685 /* In case the offset in rlc toc ucode is aligned */ 5686 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5687 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5688 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5689 5690 return total_size; 5691 } 5692 5693 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5694 { 5695 int r; 5696 uint32_t total_size; 5697 5698 total_size = gfx_v10_0_calc_toc_total_size(adev); 5699 5700 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5701 AMDGPU_GEM_DOMAIN_GTT, 5702 &adev->gfx.rlc.rlc_autoload_bo, 5703 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5704 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5705 if (r) { 5706 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5707 return r; 5708 } 5709 5710 return 0; 5711 } 5712 5713 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5714 { 5715 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5716 &adev->gfx.rlc.rlc_toc_gpu_addr, 5717 (void **)&adev->gfx.rlc.rlc_toc_buf); 5718 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5719 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5720 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5721 } 5722 5723 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5724 FIRMWARE_ID id, 5725 const void *fw_data, 5726 uint32_t fw_size) 5727 { 5728 uint32_t toc_offset; 5729 uint32_t toc_fw_size; 5730 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5731 5732 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5733 return; 5734 5735 toc_offset = rlc_autoload_info[id].offset; 5736 toc_fw_size = rlc_autoload_info[id].size; 5737 5738 if (fw_size == 0) 5739 fw_size = toc_fw_size; 5740 5741 if (fw_size > toc_fw_size) 5742 fw_size = toc_fw_size; 5743 5744 memcpy(ptr + toc_offset, fw_data, fw_size); 5745 5746 if (fw_size < toc_fw_size) 5747 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5748 } 5749 5750 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5751 { 5752 void *data; 5753 uint32_t size; 5754 5755 data = adev->gfx.rlc.rlc_toc_buf; 5756 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5757 5758 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5759 FIRMWARE_ID_RLC_TOC, 5760 data, size); 5761 } 5762 5763 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5764 { 5765 const __le32 *fw_data; 5766 uint32_t fw_size; 5767 const struct gfx_firmware_header_v1_0 *cp_hdr; 5768 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5769 5770 /* pfp ucode */ 5771 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5772 adev->gfx.pfp_fw->data; 5773 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5774 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5775 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5776 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5777 FIRMWARE_ID_CP_PFP, 5778 fw_data, fw_size); 5779 5780 /* ce ucode */ 5781 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5782 adev->gfx.ce_fw->data; 5783 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5784 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5785 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5786 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5787 FIRMWARE_ID_CP_CE, 5788 fw_data, fw_size); 5789 5790 /* me ucode */ 5791 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5792 adev->gfx.me_fw->data; 5793 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5794 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5795 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5796 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5797 FIRMWARE_ID_CP_ME, 5798 fw_data, fw_size); 5799 5800 /* rlc ucode */ 5801 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5802 adev->gfx.rlc_fw->data; 5803 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5804 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5805 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5806 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5807 FIRMWARE_ID_RLC_G_UCODE, 5808 fw_data, fw_size); 5809 5810 /* mec1 ucode */ 5811 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5812 adev->gfx.mec_fw->data; 5813 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5814 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5815 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5816 cp_hdr->jt_size * 4; 5817 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5818 FIRMWARE_ID_CP_MEC, 5819 fw_data, fw_size); 5820 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5821 } 5822 5823 /* Temporarily put sdma part here */ 5824 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5825 { 5826 const __le32 *fw_data; 5827 uint32_t fw_size; 5828 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5829 int i; 5830 5831 for (i = 0; i < adev->sdma.num_instances; i++) { 5832 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5833 adev->sdma.instance[i].fw->data; 5834 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5835 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5836 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5837 5838 if (i == 0) { 5839 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5840 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5841 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5842 FIRMWARE_ID_SDMA0_JT, 5843 (uint32_t *)fw_data + 5844 sdma_hdr->jt_offset, 5845 sdma_hdr->jt_size * 4); 5846 } else if (i == 1) { 5847 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5848 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5849 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5850 FIRMWARE_ID_SDMA1_JT, 5851 (uint32_t *)fw_data + 5852 sdma_hdr->jt_offset, 5853 sdma_hdr->jt_size * 4); 5854 } 5855 } 5856 } 5857 5858 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5859 { 5860 uint32_t rlc_g_offset, rlc_g_size, tmp; 5861 uint64_t gpu_addr; 5862 5863 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5864 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5865 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5866 5867 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5868 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5869 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5870 5871 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5872 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5873 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5874 5875 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5876 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5877 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5878 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5879 return -EINVAL; 5880 } 5881 5882 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5883 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5884 DRM_ERROR("RLC ROM should halt itself\n"); 5885 return -EINVAL; 5886 } 5887 5888 return 0; 5889 } 5890 5891 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5892 { 5893 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5894 uint32_t tmp; 5895 int i; 5896 uint64_t addr; 5897 5898 /* Trigger an invalidation of the L1 instruction caches */ 5899 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5900 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5901 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5902 5903 /* Wait for invalidation complete */ 5904 for (i = 0; i < usec_timeout; i++) { 5905 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5906 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5907 INVALIDATE_CACHE_COMPLETE)) 5908 break; 5909 udelay(1); 5910 } 5911 5912 if (i >= usec_timeout) { 5913 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5914 return -EINVAL; 5915 } 5916 5917 /* Program me ucode address into intruction cache address register */ 5918 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5919 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5920 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5921 lower_32_bits(addr) & 0xFFFFF000); 5922 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5923 upper_32_bits(addr)); 5924 5925 return 0; 5926 } 5927 5928 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5929 { 5930 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5931 uint32_t tmp; 5932 int i; 5933 uint64_t addr; 5934 5935 /* Trigger an invalidation of the L1 instruction caches */ 5936 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5937 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5938 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5939 5940 /* Wait for invalidation complete */ 5941 for (i = 0; i < usec_timeout; i++) { 5942 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5943 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5944 INVALIDATE_CACHE_COMPLETE)) 5945 break; 5946 udelay(1); 5947 } 5948 5949 if (i >= usec_timeout) { 5950 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5951 return -EINVAL; 5952 } 5953 5954 /* Program ce ucode address into intruction cache address register */ 5955 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5956 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5957 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5958 lower_32_bits(addr) & 0xFFFFF000); 5959 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5960 upper_32_bits(addr)); 5961 5962 return 0; 5963 } 5964 5965 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5966 { 5967 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5968 uint32_t tmp; 5969 int i; 5970 uint64_t addr; 5971 5972 /* Trigger an invalidation of the L1 instruction caches */ 5973 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5974 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5975 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5976 5977 /* Wait for invalidation complete */ 5978 for (i = 0; i < usec_timeout; i++) { 5979 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5980 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5981 INVALIDATE_CACHE_COMPLETE)) 5982 break; 5983 udelay(1); 5984 } 5985 5986 if (i >= usec_timeout) { 5987 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5988 return -EINVAL; 5989 } 5990 5991 /* Program pfp ucode address into intruction cache address register */ 5992 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5993 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5994 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5995 lower_32_bits(addr) & 0xFFFFF000); 5996 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5997 upper_32_bits(addr)); 5998 5999 return 0; 6000 } 6001 6002 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 6003 { 6004 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6005 uint32_t tmp; 6006 int i; 6007 uint64_t addr; 6008 6009 /* Trigger an invalidation of the L1 instruction caches */ 6010 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6011 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6012 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6013 6014 /* Wait for invalidation complete */ 6015 for (i = 0; i < usec_timeout; i++) { 6016 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6017 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6018 INVALIDATE_CACHE_COMPLETE)) 6019 break; 6020 udelay(1); 6021 } 6022 6023 if (i >= usec_timeout) { 6024 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6025 return -EINVAL; 6026 } 6027 6028 /* Program mec1 ucode address into intruction cache address register */ 6029 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 6030 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 6031 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 6032 lower_32_bits(addr) & 0xFFFFF000); 6033 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6034 upper_32_bits(addr)); 6035 6036 return 0; 6037 } 6038 6039 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 6040 { 6041 uint32_t cp_status; 6042 uint32_t bootload_status; 6043 int i, r; 6044 6045 for (i = 0; i < adev->usec_timeout; i++) { 6046 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 6047 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 6048 if ((cp_status == 0) && 6049 (REG_GET_FIELD(bootload_status, 6050 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 6051 break; 6052 } 6053 udelay(1); 6054 } 6055 6056 if (i >= adev->usec_timeout) { 6057 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 6058 return -ETIMEDOUT; 6059 } 6060 6061 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 6062 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 6063 if (r) 6064 return r; 6065 6066 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 6067 if (r) 6068 return r; 6069 6070 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 6071 if (r) 6072 return r; 6073 6074 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 6075 if (r) 6076 return r; 6077 } 6078 6079 return 0; 6080 } 6081 6082 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 6083 { 6084 int i; 6085 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 6086 6087 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 6088 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 6089 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 6090 6091 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 6092 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 6093 else 6094 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 6095 6096 if (amdgpu_in_reset(adev) && !enable) 6097 return 0; 6098 6099 for (i = 0; i < adev->usec_timeout; i++) { 6100 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 6101 break; 6102 udelay(1); 6103 } 6104 6105 if (i >= adev->usec_timeout) 6106 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 6107 6108 return 0; 6109 } 6110 6111 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 6112 { 6113 int r; 6114 const struct gfx_firmware_header_v1_0 *pfp_hdr; 6115 const __le32 *fw_data; 6116 unsigned int i, fw_size; 6117 uint32_t tmp; 6118 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6119 6120 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 6121 adev->gfx.pfp_fw->data; 6122 6123 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 6124 6125 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 6126 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 6127 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 6128 6129 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 6130 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6131 &adev->gfx.pfp.pfp_fw_obj, 6132 &adev->gfx.pfp.pfp_fw_gpu_addr, 6133 (void **)&adev->gfx.pfp.pfp_fw_ptr); 6134 if (r) { 6135 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 6136 gfx_v10_0_pfp_fini(adev); 6137 return r; 6138 } 6139 6140 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6141 6142 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6143 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6144 6145 /* Trigger an invalidation of the L1 instruction caches */ 6146 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6147 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6148 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6149 6150 /* Wait for invalidation complete */ 6151 for (i = 0; i < usec_timeout; i++) { 6152 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6153 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6154 INVALIDATE_CACHE_COMPLETE)) 6155 break; 6156 udelay(1); 6157 } 6158 6159 if (i >= usec_timeout) { 6160 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6161 return -EINVAL; 6162 } 6163 6164 if (amdgpu_emu_mode == 1) 6165 amdgpu_device_flush_hdp(adev, NULL); 6166 6167 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6168 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6169 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6170 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6171 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6172 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6173 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6174 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6175 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6176 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6177 6178 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6179 6180 for (i = 0; i < pfp_hdr->jt_size; i++) 6181 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6182 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6183 6184 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6185 6186 return 0; 6187 } 6188 6189 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6190 { 6191 int r; 6192 const struct gfx_firmware_header_v1_0 *ce_hdr; 6193 const __le32 *fw_data; 6194 unsigned int i, fw_size; 6195 uint32_t tmp; 6196 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6197 6198 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6199 adev->gfx.ce_fw->data; 6200 6201 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6202 6203 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6204 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6205 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6206 6207 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6208 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6209 &adev->gfx.ce.ce_fw_obj, 6210 &adev->gfx.ce.ce_fw_gpu_addr, 6211 (void **)&adev->gfx.ce.ce_fw_ptr); 6212 if (r) { 6213 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6214 gfx_v10_0_ce_fini(adev); 6215 return r; 6216 } 6217 6218 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6219 6220 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6221 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6222 6223 /* Trigger an invalidation of the L1 instruction caches */ 6224 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6225 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6226 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6227 6228 /* Wait for invalidation complete */ 6229 for (i = 0; i < usec_timeout; i++) { 6230 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6231 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6232 INVALIDATE_CACHE_COMPLETE)) 6233 break; 6234 udelay(1); 6235 } 6236 6237 if (i >= usec_timeout) { 6238 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6239 return -EINVAL; 6240 } 6241 6242 if (amdgpu_emu_mode == 1) 6243 amdgpu_device_flush_hdp(adev, NULL); 6244 6245 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6246 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6247 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6248 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6249 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6250 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6251 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6252 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6253 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6254 6255 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6256 6257 for (i = 0; i < ce_hdr->jt_size; i++) 6258 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6259 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6260 6261 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6262 6263 return 0; 6264 } 6265 6266 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6267 { 6268 int r; 6269 const struct gfx_firmware_header_v1_0 *me_hdr; 6270 const __le32 *fw_data; 6271 unsigned int i, fw_size; 6272 uint32_t tmp; 6273 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6274 6275 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6276 adev->gfx.me_fw->data; 6277 6278 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6279 6280 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6281 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6282 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6283 6284 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6285 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6286 &adev->gfx.me.me_fw_obj, 6287 &adev->gfx.me.me_fw_gpu_addr, 6288 (void **)&adev->gfx.me.me_fw_ptr); 6289 if (r) { 6290 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6291 gfx_v10_0_me_fini(adev); 6292 return r; 6293 } 6294 6295 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6296 6297 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6298 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6299 6300 /* Trigger an invalidation of the L1 instruction caches */ 6301 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6302 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6303 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6304 6305 /* Wait for invalidation complete */ 6306 for (i = 0; i < usec_timeout; i++) { 6307 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6308 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6309 INVALIDATE_CACHE_COMPLETE)) 6310 break; 6311 udelay(1); 6312 } 6313 6314 if (i >= usec_timeout) { 6315 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6316 return -EINVAL; 6317 } 6318 6319 if (amdgpu_emu_mode == 1) 6320 amdgpu_device_flush_hdp(adev, NULL); 6321 6322 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6323 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6324 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6325 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6326 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6327 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6328 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6329 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6330 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6331 6332 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6333 6334 for (i = 0; i < me_hdr->jt_size; i++) 6335 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6336 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6337 6338 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6339 6340 return 0; 6341 } 6342 6343 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6344 { 6345 int r; 6346 6347 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6348 return -EINVAL; 6349 6350 gfx_v10_0_cp_gfx_enable(adev, false); 6351 6352 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6353 if (r) { 6354 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6355 return r; 6356 } 6357 6358 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6359 if (r) { 6360 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6361 return r; 6362 } 6363 6364 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6365 if (r) { 6366 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6367 return r; 6368 } 6369 6370 return 0; 6371 } 6372 6373 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6374 { 6375 struct amdgpu_ring *ring; 6376 const struct cs_section_def *sect = NULL; 6377 const struct cs_extent_def *ext = NULL; 6378 int r, i; 6379 int ctx_reg_offset; 6380 6381 /* init the CP */ 6382 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6383 adev->gfx.config.max_hw_contexts - 1); 6384 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6385 6386 gfx_v10_0_cp_gfx_enable(adev, true); 6387 6388 ring = &adev->gfx.gfx_ring[0]; 6389 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6390 if (r) { 6391 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 6392 return r; 6393 } 6394 6395 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6396 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6397 6398 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6399 amdgpu_ring_write(ring, 0x80000000); 6400 amdgpu_ring_write(ring, 0x80000000); 6401 6402 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6403 for (ext = sect->section; ext->extent != NULL; ++ext) { 6404 if (sect->id == SECT_CONTEXT) { 6405 amdgpu_ring_write(ring, 6406 PACKET3(PACKET3_SET_CONTEXT_REG, 6407 ext->reg_count)); 6408 amdgpu_ring_write(ring, ext->reg_index - 6409 PACKET3_SET_CONTEXT_REG_START); 6410 for (i = 0; i < ext->reg_count; i++) 6411 amdgpu_ring_write(ring, ext->extent[i]); 6412 } 6413 } 6414 } 6415 6416 ctx_reg_offset = 6417 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6418 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6419 amdgpu_ring_write(ring, ctx_reg_offset); 6420 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6421 6422 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6423 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6424 6425 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6426 amdgpu_ring_write(ring, 0); 6427 6428 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6429 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6430 amdgpu_ring_write(ring, 0x8000); 6431 amdgpu_ring_write(ring, 0x8000); 6432 6433 amdgpu_ring_commit(ring); 6434 6435 /* submit cs packet to copy state 0 to next available state */ 6436 if (adev->gfx.num_gfx_rings > 1) { 6437 /* maximum supported gfx ring is 2 */ 6438 ring = &adev->gfx.gfx_ring[1]; 6439 r = amdgpu_ring_alloc(ring, 2); 6440 if (r) { 6441 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 6442 return r; 6443 } 6444 6445 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6446 amdgpu_ring_write(ring, 0); 6447 6448 amdgpu_ring_commit(ring); 6449 } 6450 return 0; 6451 } 6452 6453 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6454 CP_PIPE_ID pipe) 6455 { 6456 u32 tmp; 6457 6458 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6459 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6460 6461 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6462 } 6463 6464 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6465 struct amdgpu_ring *ring) 6466 { 6467 u32 tmp; 6468 6469 if (!amdgpu_async_gfx_ring) { 6470 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6471 if (ring->use_doorbell) { 6472 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6473 DOORBELL_OFFSET, ring->doorbell_index); 6474 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6475 DOORBELL_EN, 1); 6476 } else { 6477 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6478 DOORBELL_EN, 0); 6479 } 6480 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6481 } 6482 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6483 case IP_VERSION(10, 3, 0): 6484 case IP_VERSION(10, 3, 2): 6485 case IP_VERSION(10, 3, 1): 6486 case IP_VERSION(10, 3, 4): 6487 case IP_VERSION(10, 3, 5): 6488 case IP_VERSION(10, 3, 6): 6489 case IP_VERSION(10, 3, 3): 6490 case IP_VERSION(10, 3, 7): 6491 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6492 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6493 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6494 6495 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6496 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6497 break; 6498 default: 6499 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6500 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6501 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6502 6503 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6504 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6505 break; 6506 } 6507 } 6508 6509 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6510 { 6511 struct amdgpu_ring *ring; 6512 u32 tmp; 6513 u32 rb_bufsz; 6514 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6515 6516 /* Set the write pointer delay */ 6517 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6518 6519 /* set the RB to use vmid 0 */ 6520 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6521 6522 /* Init gfx ring 0 for pipe 0 */ 6523 mutex_lock(&adev->srbm_mutex); 6524 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6525 6526 /* Set ring buffer size */ 6527 ring = &adev->gfx.gfx_ring[0]; 6528 rb_bufsz = order_base_2(ring->ring_size / 8); 6529 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6530 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6531 #ifdef __BIG_ENDIAN 6532 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6533 #endif 6534 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6535 6536 /* Initialize the ring buffer's write pointers */ 6537 ring->wptr = 0; 6538 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6539 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6540 6541 /* set the wb address whether it's enabled or not */ 6542 rptr_addr = ring->rptr_gpu_addr; 6543 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6544 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6545 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6546 6547 wptr_gpu_addr = ring->wptr_gpu_addr; 6548 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6549 lower_32_bits(wptr_gpu_addr)); 6550 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6551 upper_32_bits(wptr_gpu_addr)); 6552 6553 mdelay(1); 6554 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6555 6556 rb_addr = ring->gpu_addr >> 8; 6557 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6558 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6559 6560 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6561 6562 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6563 mutex_unlock(&adev->srbm_mutex); 6564 6565 /* Init gfx ring 1 for pipe 1 */ 6566 if (adev->gfx.num_gfx_rings > 1) { 6567 mutex_lock(&adev->srbm_mutex); 6568 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6569 /* maximum supported gfx ring is 2 */ 6570 ring = &adev->gfx.gfx_ring[1]; 6571 rb_bufsz = order_base_2(ring->ring_size / 8); 6572 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6573 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6574 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6575 /* Initialize the ring buffer's write pointers */ 6576 ring->wptr = 0; 6577 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6578 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6579 /* Set the wb address whether it's enabled or not */ 6580 rptr_addr = ring->rptr_gpu_addr; 6581 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6582 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6583 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6584 wptr_gpu_addr = ring->wptr_gpu_addr; 6585 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6586 lower_32_bits(wptr_gpu_addr)); 6587 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6588 upper_32_bits(wptr_gpu_addr)); 6589 6590 mdelay(1); 6591 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6592 6593 rb_addr = ring->gpu_addr >> 8; 6594 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6595 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6596 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6597 6598 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6599 mutex_unlock(&adev->srbm_mutex); 6600 } 6601 /* Switch to pipe 0 */ 6602 mutex_lock(&adev->srbm_mutex); 6603 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6604 mutex_unlock(&adev->srbm_mutex); 6605 6606 /* start the ring */ 6607 gfx_v10_0_cp_gfx_start(adev); 6608 6609 return 0; 6610 } 6611 6612 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6613 { 6614 if (enable) { 6615 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6616 case IP_VERSION(10, 3, 0): 6617 case IP_VERSION(10, 3, 2): 6618 case IP_VERSION(10, 3, 1): 6619 case IP_VERSION(10, 3, 4): 6620 case IP_VERSION(10, 3, 5): 6621 case IP_VERSION(10, 3, 6): 6622 case IP_VERSION(10, 3, 3): 6623 case IP_VERSION(10, 3, 7): 6624 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6625 break; 6626 default: 6627 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6628 break; 6629 } 6630 } else { 6631 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6632 case IP_VERSION(10, 3, 0): 6633 case IP_VERSION(10, 3, 2): 6634 case IP_VERSION(10, 3, 1): 6635 case IP_VERSION(10, 3, 4): 6636 case IP_VERSION(10, 3, 5): 6637 case IP_VERSION(10, 3, 6): 6638 case IP_VERSION(10, 3, 3): 6639 case IP_VERSION(10, 3, 7): 6640 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6641 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6642 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6643 break; 6644 default: 6645 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6646 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6647 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6648 break; 6649 } 6650 adev->gfx.kiq[0].ring.sched.ready = false; 6651 } 6652 udelay(50); 6653 } 6654 6655 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6656 { 6657 const struct gfx_firmware_header_v1_0 *mec_hdr; 6658 const __le32 *fw_data; 6659 unsigned int i; 6660 u32 tmp; 6661 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6662 6663 if (!adev->gfx.mec_fw) 6664 return -EINVAL; 6665 6666 gfx_v10_0_cp_compute_enable(adev, false); 6667 6668 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6669 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6670 6671 fw_data = (const __le32 *) 6672 (adev->gfx.mec_fw->data + 6673 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6674 6675 /* Trigger an invalidation of the L1 instruction caches */ 6676 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6677 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6678 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6679 6680 /* Wait for invalidation complete */ 6681 for (i = 0; i < usec_timeout; i++) { 6682 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6683 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6684 INVALIDATE_CACHE_COMPLETE)) 6685 break; 6686 udelay(1); 6687 } 6688 6689 if (i >= usec_timeout) { 6690 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6691 return -EINVAL; 6692 } 6693 6694 if (amdgpu_emu_mode == 1) 6695 amdgpu_device_flush_hdp(adev, NULL); 6696 6697 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6698 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6699 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6700 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6701 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6702 6703 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6704 0xFFFFF000); 6705 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6706 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6707 6708 /* MEC1 */ 6709 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6710 6711 for (i = 0; i < mec_hdr->jt_size; i++) 6712 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6713 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6714 6715 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6716 6717 /* 6718 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6719 * different microcode than MEC1. 6720 */ 6721 6722 return 0; 6723 } 6724 6725 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6726 { 6727 uint32_t tmp; 6728 struct amdgpu_device *adev = ring->adev; 6729 6730 /* tell RLC which is KIQ queue */ 6731 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6732 case IP_VERSION(10, 3, 0): 6733 case IP_VERSION(10, 3, 2): 6734 case IP_VERSION(10, 3, 1): 6735 case IP_VERSION(10, 3, 4): 6736 case IP_VERSION(10, 3, 5): 6737 case IP_VERSION(10, 3, 6): 6738 case IP_VERSION(10, 3, 3): 6739 case IP_VERSION(10, 3, 7): 6740 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6741 tmp &= 0xffffff00; 6742 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6743 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80); 6744 break; 6745 default: 6746 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6747 tmp &= 0xffffff00; 6748 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6749 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80); 6750 break; 6751 } 6752 } 6753 6754 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6755 struct v10_gfx_mqd *mqd, 6756 struct amdgpu_mqd_prop *prop) 6757 { 6758 bool priority = 0; 6759 u32 tmp; 6760 6761 /* set up default queue priority level 6762 * 0x0 = low priority, 0x1 = high priority 6763 */ 6764 if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) 6765 priority = 1; 6766 6767 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6768 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6769 mqd->cp_gfx_hqd_queue_priority = tmp; 6770 } 6771 6772 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6773 struct amdgpu_mqd_prop *prop) 6774 { 6775 struct v10_gfx_mqd *mqd = m; 6776 uint64_t hqd_gpu_addr, wb_gpu_addr; 6777 uint32_t tmp; 6778 uint32_t rb_bufsz; 6779 6780 /* set up gfx hqd wptr */ 6781 mqd->cp_gfx_hqd_wptr = 0; 6782 mqd->cp_gfx_hqd_wptr_hi = 0; 6783 6784 /* set the pointer to the MQD */ 6785 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6786 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6787 6788 /* set up mqd control */ 6789 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6790 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6791 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6792 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6793 mqd->cp_gfx_mqd_control = tmp; 6794 6795 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6796 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6797 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6798 mqd->cp_gfx_hqd_vmid = 0; 6799 6800 /* set up gfx queue priority */ 6801 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6802 6803 /* set up time quantum */ 6804 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6805 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6806 mqd->cp_gfx_hqd_quantum = tmp; 6807 6808 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6809 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6810 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6811 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6812 6813 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6814 wb_gpu_addr = prop->rptr_gpu_addr; 6815 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6816 mqd->cp_gfx_hqd_rptr_addr_hi = 6817 upper_32_bits(wb_gpu_addr) & 0xffff; 6818 6819 /* set up rb_wptr_poll addr */ 6820 wb_gpu_addr = prop->wptr_gpu_addr; 6821 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6822 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6823 6824 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6825 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6826 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6827 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6828 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6829 #ifdef __BIG_ENDIAN 6830 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6831 #endif 6832 mqd->cp_gfx_hqd_cntl = tmp; 6833 6834 /* set up cp_doorbell_control */ 6835 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6836 if (prop->use_doorbell) { 6837 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6838 DOORBELL_OFFSET, prop->doorbell_index); 6839 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6840 DOORBELL_EN, 1); 6841 } else 6842 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6843 DOORBELL_EN, 0); 6844 mqd->cp_rb_doorbell_control = tmp; 6845 6846 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6847 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6848 6849 /* active the queue */ 6850 mqd->cp_gfx_hqd_active = 1; 6851 6852 return 0; 6853 } 6854 6855 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 6856 { 6857 struct amdgpu_device *adev = ring->adev; 6858 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6859 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6860 6861 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 6862 memset((void *)mqd, 0, sizeof(*mqd)); 6863 mutex_lock(&adev->srbm_mutex); 6864 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6865 amdgpu_ring_init_mqd(ring); 6866 6867 /* 6868 * if there are 2 gfx rings, set the lower doorbell 6869 * range of the first ring, otherwise the range of 6870 * the second ring will override the first ring 6871 */ 6872 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6873 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6874 6875 nv_grbm_select(adev, 0, 0, 0, 0); 6876 mutex_unlock(&adev->srbm_mutex); 6877 if (adev->gfx.me.mqd_backup[mqd_idx]) 6878 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6879 } else { 6880 mutex_lock(&adev->srbm_mutex); 6881 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6882 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6883 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6884 6885 nv_grbm_select(adev, 0, 0, 0, 0); 6886 mutex_unlock(&adev->srbm_mutex); 6887 /* restore mqd with the backup copy */ 6888 if (adev->gfx.me.mqd_backup[mqd_idx]) 6889 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6890 /* reset the ring */ 6891 ring->wptr = 0; 6892 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6893 amdgpu_ring_clear_ring(ring); 6894 } 6895 6896 return 0; 6897 } 6898 6899 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6900 { 6901 int r, i; 6902 6903 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6904 r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 6905 if (r) 6906 return r; 6907 } 6908 6909 r = amdgpu_gfx_enable_kgq(adev, 0); 6910 if (r) 6911 return r; 6912 6913 return gfx_v10_0_cp_gfx_start(adev); 6914 } 6915 6916 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6917 struct amdgpu_mqd_prop *prop) 6918 { 6919 struct v10_compute_mqd *mqd = m; 6920 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6921 uint32_t tmp; 6922 6923 mqd->header = 0xC0310800; 6924 mqd->compute_pipelinestat_enable = 0x00000001; 6925 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6926 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6927 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6928 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6929 mqd->compute_misc_reserved = 0x00000003; 6930 6931 eop_base_addr = prop->eop_gpu_addr >> 8; 6932 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6933 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6934 6935 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6936 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6937 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6938 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6939 6940 mqd->cp_hqd_eop_control = tmp; 6941 6942 /* enable doorbell? */ 6943 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6944 6945 if (prop->use_doorbell) { 6946 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6947 DOORBELL_OFFSET, prop->doorbell_index); 6948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6949 DOORBELL_EN, 1); 6950 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6951 DOORBELL_SOURCE, 0); 6952 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6953 DOORBELL_HIT, 0); 6954 } else { 6955 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6956 DOORBELL_EN, 0); 6957 } 6958 6959 mqd->cp_hqd_pq_doorbell_control = tmp; 6960 6961 /* disable the queue if it's active */ 6962 mqd->cp_hqd_dequeue_request = 0; 6963 mqd->cp_hqd_pq_rptr = 0; 6964 mqd->cp_hqd_pq_wptr_lo = 0; 6965 mqd->cp_hqd_pq_wptr_hi = 0; 6966 6967 /* set the pointer to the MQD */ 6968 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6969 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6970 6971 /* set MQD vmid to 0 */ 6972 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6973 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6974 mqd->cp_mqd_control = tmp; 6975 6976 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6977 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6978 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6979 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6980 6981 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6982 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6983 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6984 (order_base_2(prop->queue_size / 4) - 1)); 6985 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6986 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6987 #ifdef __BIG_ENDIAN 6988 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6989 #endif 6990 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6991 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6992 prop->allow_tunneling); 6993 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6994 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6995 mqd->cp_hqd_pq_control = tmp; 6996 6997 /* set the wb address whether it's enabled or not */ 6998 wb_gpu_addr = prop->rptr_gpu_addr; 6999 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 7000 mqd->cp_hqd_pq_rptr_report_addr_hi = 7001 upper_32_bits(wb_gpu_addr) & 0xffff; 7002 7003 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7004 wb_gpu_addr = prop->wptr_gpu_addr; 7005 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 7006 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 7007 7008 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7009 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 7010 7011 /* set the vmid for the queue */ 7012 mqd->cp_hqd_vmid = 0; 7013 7014 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 7015 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 7016 mqd->cp_hqd_persistent_state = tmp; 7017 7018 /* set MIN_IB_AVAIL_SIZE */ 7019 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 7020 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 7021 mqd->cp_hqd_ib_control = tmp; 7022 7023 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 7024 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 7025 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 7026 mqd->cp_hqd_quantum = tmp; 7027 7028 /* set static priority for a compute queue/ring */ 7029 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 7030 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 7031 7032 mqd->cp_hqd_active = prop->hqd_active; 7033 7034 return 0; 7035 } 7036 7037 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 7038 { 7039 struct amdgpu_device *adev = ring->adev; 7040 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7041 int j; 7042 7043 /* inactivate the queue */ 7044 if (amdgpu_sriov_vf(adev)) 7045 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 7046 7047 /* disable wptr polling */ 7048 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 7049 7050 /* disable the queue if it's active */ 7051 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7052 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7053 for (j = 0; j < adev->usec_timeout; j++) { 7054 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7055 break; 7056 udelay(1); 7057 } 7058 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7059 mqd->cp_hqd_dequeue_request); 7060 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7061 mqd->cp_hqd_pq_rptr); 7062 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7063 mqd->cp_hqd_pq_wptr_lo); 7064 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7065 mqd->cp_hqd_pq_wptr_hi); 7066 } 7067 7068 /* disable doorbells */ 7069 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 7070 7071 /* write the EOP addr */ 7072 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7073 mqd->cp_hqd_eop_base_addr_lo); 7074 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7075 mqd->cp_hqd_eop_base_addr_hi); 7076 7077 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7078 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7079 mqd->cp_hqd_eop_control); 7080 7081 /* set the pointer to the MQD */ 7082 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7083 mqd->cp_mqd_base_addr_lo); 7084 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7085 mqd->cp_mqd_base_addr_hi); 7086 7087 /* set MQD vmid to 0 */ 7088 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7089 mqd->cp_mqd_control); 7090 7091 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7092 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7093 mqd->cp_hqd_pq_base_lo); 7094 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7095 mqd->cp_hqd_pq_base_hi); 7096 7097 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7098 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7099 mqd->cp_hqd_pq_control); 7100 7101 /* set the wb address whether it's enabled or not */ 7102 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7103 mqd->cp_hqd_pq_rptr_report_addr_lo); 7104 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7105 mqd->cp_hqd_pq_rptr_report_addr_hi); 7106 7107 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7108 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7109 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7110 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7111 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7112 7113 /* enable the doorbell if requested */ 7114 if (ring->use_doorbell) { 7115 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7116 (adev->doorbell_index.kiq * 2) << 2); 7117 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7118 (adev->doorbell_index.userqueue_end * 2) << 2); 7119 } 7120 7121 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7122 mqd->cp_hqd_pq_doorbell_control); 7123 7124 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7125 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7126 mqd->cp_hqd_pq_wptr_lo); 7127 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7128 mqd->cp_hqd_pq_wptr_hi); 7129 7130 /* set the vmid for the queue */ 7131 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7132 7133 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7134 mqd->cp_hqd_persistent_state); 7135 7136 /* activate the queue */ 7137 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7138 mqd->cp_hqd_active); 7139 7140 if (ring->use_doorbell) 7141 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7142 7143 return 0; 7144 } 7145 7146 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7147 { 7148 struct amdgpu_device *adev = ring->adev; 7149 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7150 7151 gfx_v10_0_kiq_setting(ring); 7152 7153 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7154 /* reset MQD to a clean status */ 7155 if (adev->gfx.kiq[0].mqd_backup) 7156 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7157 7158 /* reset ring buffer */ 7159 ring->wptr = 0; 7160 amdgpu_ring_clear_ring(ring); 7161 7162 mutex_lock(&adev->srbm_mutex); 7163 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7164 gfx_v10_0_kiq_init_register(ring); 7165 nv_grbm_select(adev, 0, 0, 0, 0); 7166 mutex_unlock(&adev->srbm_mutex); 7167 } else { 7168 memset((void *)mqd, 0, sizeof(*mqd)); 7169 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7170 amdgpu_ring_clear_ring(ring); 7171 mutex_lock(&adev->srbm_mutex); 7172 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7173 amdgpu_ring_init_mqd(ring); 7174 gfx_v10_0_kiq_init_register(ring); 7175 nv_grbm_select(adev, 0, 0, 0, 0); 7176 mutex_unlock(&adev->srbm_mutex); 7177 7178 if (adev->gfx.kiq[0].mqd_backup) 7179 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7180 } 7181 7182 return 0; 7183 } 7184 7185 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) 7186 { 7187 struct amdgpu_device *adev = ring->adev; 7188 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7189 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7190 7191 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { 7192 memset((void *)mqd, 0, sizeof(*mqd)); 7193 mutex_lock(&adev->srbm_mutex); 7194 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7195 amdgpu_ring_init_mqd(ring); 7196 nv_grbm_select(adev, 0, 0, 0, 0); 7197 mutex_unlock(&adev->srbm_mutex); 7198 7199 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7200 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7201 } else { 7202 /* restore MQD to a clean status */ 7203 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7204 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7205 /* reset ring buffer */ 7206 ring->wptr = 0; 7207 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7208 amdgpu_ring_clear_ring(ring); 7209 } 7210 7211 return 0; 7212 } 7213 7214 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7215 { 7216 gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 7217 return 0; 7218 } 7219 7220 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7221 { 7222 int i, r; 7223 7224 gfx_v10_0_cp_compute_enable(adev, true); 7225 7226 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7227 r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i], 7228 false); 7229 if (r) 7230 return r; 7231 } 7232 7233 return amdgpu_gfx_enable_kcq(adev, 0); 7234 } 7235 7236 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7237 { 7238 int r, i; 7239 struct amdgpu_ring *ring; 7240 7241 if (!(adev->flags & AMD_IS_APU)) 7242 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7243 7244 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7245 /* legacy firmware loading */ 7246 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7247 if (r) 7248 return r; 7249 7250 r = gfx_v10_0_cp_compute_load_microcode(adev); 7251 if (r) 7252 return r; 7253 } 7254 7255 r = gfx_v10_0_kiq_resume(adev); 7256 if (r) 7257 return r; 7258 7259 r = gfx_v10_0_kcq_resume(adev); 7260 if (r) 7261 return r; 7262 7263 if (!amdgpu_async_gfx_ring) { 7264 r = gfx_v10_0_cp_gfx_resume(adev); 7265 if (r) 7266 return r; 7267 } else { 7268 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7269 if (r) 7270 return r; 7271 } 7272 7273 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7274 ring = &adev->gfx.gfx_ring[i]; 7275 r = amdgpu_ring_test_helper(ring); 7276 if (r) 7277 return r; 7278 } 7279 7280 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7281 ring = &adev->gfx.compute_ring[i]; 7282 r = amdgpu_ring_test_helper(ring); 7283 if (r) 7284 return r; 7285 } 7286 7287 return 0; 7288 } 7289 7290 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7291 { 7292 gfx_v10_0_cp_gfx_enable(adev, enable); 7293 gfx_v10_0_cp_compute_enable(adev, enable); 7294 } 7295 7296 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7297 { 7298 uint32_t data, pattern = 0xDEADBEEF; 7299 7300 /* 7301 * check if mmVGT_ESGS_RING_SIZE_UMD 7302 * has been remapped to mmVGT_ESGS_RING_SIZE 7303 */ 7304 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7305 case IP_VERSION(10, 3, 0): 7306 case IP_VERSION(10, 3, 2): 7307 case IP_VERSION(10, 3, 4): 7308 case IP_VERSION(10, 3, 5): 7309 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7310 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7311 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7312 7313 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7314 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7315 return true; 7316 } 7317 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7318 break; 7319 case IP_VERSION(10, 3, 1): 7320 case IP_VERSION(10, 3, 3): 7321 case IP_VERSION(10, 3, 6): 7322 case IP_VERSION(10, 3, 7): 7323 return true; 7324 default: 7325 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7326 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7327 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7328 7329 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7330 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7331 return true; 7332 } 7333 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7334 break; 7335 } 7336 7337 return false; 7338 } 7339 7340 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7341 { 7342 uint32_t data; 7343 7344 if (amdgpu_sriov_vf(adev)) 7345 return; 7346 7347 /* 7348 * Initialize cam_index to 0 7349 * index will auto-inc after each data writing 7350 */ 7351 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7352 7353 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7354 case IP_VERSION(10, 3, 0): 7355 case IP_VERSION(10, 3, 2): 7356 case IP_VERSION(10, 3, 1): 7357 case IP_VERSION(10, 3, 4): 7358 case IP_VERSION(10, 3, 5): 7359 case IP_VERSION(10, 3, 6): 7360 case IP_VERSION(10, 3, 3): 7361 case IP_VERSION(10, 3, 7): 7362 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7363 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7364 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7365 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7366 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7367 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7368 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7369 7370 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7371 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7372 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7373 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7374 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7375 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7376 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7377 7378 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7379 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7380 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7381 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7382 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7383 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7384 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7385 7386 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7387 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7388 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7389 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7390 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7391 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7392 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7393 7394 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7395 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7396 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7397 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7398 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7399 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7400 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7401 7402 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7403 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7404 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7405 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7406 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7407 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7408 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7409 7410 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7411 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7412 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7413 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7414 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7415 break; 7416 default: 7417 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7418 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7419 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7420 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7421 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7422 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7423 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7424 7425 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7426 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7427 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7428 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7429 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7430 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7431 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7432 7433 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7434 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7435 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7436 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7437 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7438 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7439 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7440 7441 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7442 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7443 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7444 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7445 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7446 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7447 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7448 7449 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7450 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7451 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7452 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7453 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7454 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7455 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7456 7457 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7458 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7459 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7460 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7461 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7462 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7463 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7464 7465 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7466 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7467 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7468 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7469 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7470 break; 7471 } 7472 7473 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7474 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7475 } 7476 7477 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7478 { 7479 uint32_t data; 7480 7481 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7482 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7483 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7484 7485 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7486 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7487 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7488 } 7489 7490 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 7491 { 7492 int r; 7493 struct amdgpu_device *adev = ip_block->adev; 7494 7495 if (!amdgpu_emu_mode) 7496 gfx_v10_0_init_golden_registers(adev); 7497 7498 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 7499 adev->gfx.cleaner_shader_ptr); 7500 7501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7502 /** 7503 * For gfx 10, rlc firmware loading relies on smu firmware is 7504 * loaded firstly, so in direct type, it has to load smc ucode 7505 * here before rlc. 7506 */ 7507 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7508 if (r) 7509 return r; 7510 gfx_v10_0_disable_gpa_mode(adev); 7511 } 7512 7513 /* if GRBM CAM not remapped, set up the remapping */ 7514 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7515 gfx_v10_0_setup_grbm_cam_remapping(adev); 7516 7517 gfx_v10_0_constants_init(adev); 7518 7519 r = gfx_v10_0_rlc_resume(adev); 7520 if (r) 7521 return r; 7522 7523 /* 7524 * init golden registers and rlc resume may override some registers, 7525 * reconfig them here 7526 */ 7527 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7528 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7529 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7530 gfx_v10_0_tcp_harvest(adev); 7531 7532 r = gfx_v10_0_cp_resume(adev); 7533 if (r) 7534 return r; 7535 7536 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7537 gfx_v10_3_program_pbb_mode(adev); 7538 7539 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7540 gfx_v10_3_set_power_brake_sequence(adev); 7541 7542 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7543 if (r) 7544 return r; 7545 7546 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7547 if (r) 7548 goto err_priv_inst; 7549 7550 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7551 if (r) 7552 goto err_bad_op; 7553 7554 return 0; 7555 7556 err_bad_op: 7557 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7558 err_priv_inst: 7559 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7560 return r; 7561 } 7562 7563 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 7564 { 7565 struct amdgpu_device *adev = ip_block->adev; 7566 7567 cancel_delayed_work_sync(&adev->gfx.idle_work); 7568 7569 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7570 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7571 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7572 7573 /* WA added for Vangogh asic fixing the SMU suspend failure 7574 * It needs to set power gating again during gfxoff control 7575 * otherwise the gfxoff disallowing will be failed to set. 7576 */ 7577 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7578 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 7579 7580 if (!adev->no_hw_access) { 7581 if (amdgpu_async_gfx_ring) { 7582 if (amdgpu_gfx_disable_kgq(adev, 0)) 7583 DRM_ERROR("KGQ disable failed\n"); 7584 } 7585 7586 if (amdgpu_gfx_disable_kcq(adev, 0)) 7587 DRM_ERROR("KCQ disable failed\n"); 7588 } 7589 7590 if (amdgpu_sriov_vf(adev)) { 7591 gfx_v10_0_cp_gfx_enable(adev, false); 7592 /* Remove the steps of clearing KIQ position. 7593 * It causes GFX hang when another Win guest is rendering. 7594 */ 7595 return 0; 7596 } 7597 gfx_v10_0_cp_enable(adev, false); 7598 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7599 7600 return 0; 7601 } 7602 7603 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) 7604 { 7605 return gfx_v10_0_hw_fini(ip_block); 7606 } 7607 7608 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) 7609 { 7610 return gfx_v10_0_hw_init(ip_block); 7611 } 7612 7613 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 7614 { 7615 struct amdgpu_device *adev = ip_block->adev; 7616 7617 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7618 GRBM_STATUS, GUI_ACTIVE)) 7619 return false; 7620 else 7621 return true; 7622 } 7623 7624 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 7625 { 7626 unsigned int i; 7627 u32 tmp; 7628 struct amdgpu_device *adev = ip_block->adev; 7629 7630 for (i = 0; i < adev->usec_timeout; i++) { 7631 /* read MC_STATUS */ 7632 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7633 GRBM_STATUS__GUI_ACTIVE_MASK; 7634 7635 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7636 return 0; 7637 udelay(1); 7638 } 7639 return -ETIMEDOUT; 7640 } 7641 7642 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) 7643 { 7644 u32 grbm_soft_reset = 0; 7645 u32 tmp; 7646 struct amdgpu_device *adev = ip_block->adev; 7647 7648 /* GRBM_STATUS */ 7649 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7650 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7651 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7652 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7653 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7654 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7655 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7656 GRBM_SOFT_RESET, SOFT_RESET_CP, 7657 1); 7658 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7659 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7660 1); 7661 } 7662 7663 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7664 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7665 GRBM_SOFT_RESET, SOFT_RESET_CP, 7666 1); 7667 } 7668 7669 /* GRBM_STATUS2 */ 7670 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7671 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7672 case IP_VERSION(10, 3, 0): 7673 case IP_VERSION(10, 3, 2): 7674 case IP_VERSION(10, 3, 1): 7675 case IP_VERSION(10, 3, 4): 7676 case IP_VERSION(10, 3, 5): 7677 case IP_VERSION(10, 3, 6): 7678 case IP_VERSION(10, 3, 3): 7679 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7680 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7681 GRBM_SOFT_RESET, 7682 SOFT_RESET_RLC, 7683 1); 7684 break; 7685 default: 7686 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7687 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7688 GRBM_SOFT_RESET, 7689 SOFT_RESET_RLC, 7690 1); 7691 break; 7692 } 7693 7694 if (grbm_soft_reset) { 7695 /* stop the rlc */ 7696 gfx_v10_0_rlc_stop(adev); 7697 7698 /* Disable GFX parsing/prefetching */ 7699 gfx_v10_0_cp_gfx_enable(adev, false); 7700 7701 /* Disable MEC parsing/prefetching */ 7702 gfx_v10_0_cp_compute_enable(adev, false); 7703 7704 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7705 tmp |= grbm_soft_reset; 7706 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7707 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7708 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7709 7710 udelay(50); 7711 7712 tmp &= ~grbm_soft_reset; 7713 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7714 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7715 7716 /* Wait a little for things to settle down */ 7717 udelay(50); 7718 } 7719 return 0; 7720 } 7721 7722 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7723 { 7724 uint64_t clock, clock_lo, clock_hi, hi_check; 7725 7726 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7727 case IP_VERSION(10, 1, 3): 7728 case IP_VERSION(10, 1, 4): 7729 preempt_disable(); 7730 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7731 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7732 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7733 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7734 * roughly every 42 seconds. 7735 */ 7736 if (hi_check != clock_hi) { 7737 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7738 clock_hi = hi_check; 7739 } 7740 preempt_enable(); 7741 clock = clock_lo | (clock_hi << 32ULL); 7742 break; 7743 case IP_VERSION(10, 3, 1): 7744 case IP_VERSION(10, 3, 3): 7745 case IP_VERSION(10, 3, 7): 7746 preempt_disable(); 7747 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7748 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7749 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7750 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7751 * roughly every 42 seconds. 7752 */ 7753 if (hi_check != clock_hi) { 7754 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7755 clock_hi = hi_check; 7756 } 7757 preempt_enable(); 7758 clock = clock_lo | (clock_hi << 32ULL); 7759 break; 7760 case IP_VERSION(10, 3, 6): 7761 preempt_disable(); 7762 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7763 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7764 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7765 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7766 * roughly every 42 seconds. 7767 */ 7768 if (hi_check != clock_hi) { 7769 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7770 clock_hi = hi_check; 7771 } 7772 preempt_enable(); 7773 clock = clock_lo | (clock_hi << 32ULL); 7774 break; 7775 default: 7776 preempt_disable(); 7777 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7778 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7779 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7780 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7781 * roughly every 42 seconds. 7782 */ 7783 if (hi_check != clock_hi) { 7784 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7785 clock_hi = hi_check; 7786 } 7787 preempt_enable(); 7788 clock = clock_lo | (clock_hi << 32ULL); 7789 break; 7790 } 7791 return clock; 7792 } 7793 7794 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7795 uint32_t vmid, 7796 uint32_t gds_base, uint32_t gds_size, 7797 uint32_t gws_base, uint32_t gws_size, 7798 uint32_t oa_base, uint32_t oa_size) 7799 { 7800 struct amdgpu_device *adev = ring->adev; 7801 7802 /* GDS Base */ 7803 gfx_v10_0_write_data_to_reg(ring, 0, false, 7804 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7805 gds_base); 7806 7807 /* GDS Size */ 7808 gfx_v10_0_write_data_to_reg(ring, 0, false, 7809 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7810 gds_size); 7811 7812 /* GWS */ 7813 gfx_v10_0_write_data_to_reg(ring, 0, false, 7814 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7815 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7816 7817 /* OA */ 7818 gfx_v10_0_write_data_to_reg(ring, 0, false, 7819 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7820 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7821 } 7822 7823 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) 7824 { 7825 struct amdgpu_device *adev = ip_block->adev; 7826 7827 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7828 7829 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7830 case IP_VERSION(10, 1, 10): 7831 case IP_VERSION(10, 1, 1): 7832 case IP_VERSION(10, 1, 2): 7833 case IP_VERSION(10, 1, 3): 7834 case IP_VERSION(10, 1, 4): 7835 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7836 break; 7837 case IP_VERSION(10, 3, 0): 7838 case IP_VERSION(10, 3, 2): 7839 case IP_VERSION(10, 3, 1): 7840 case IP_VERSION(10, 3, 4): 7841 case IP_VERSION(10, 3, 5): 7842 case IP_VERSION(10, 3, 6): 7843 case IP_VERSION(10, 3, 3): 7844 case IP_VERSION(10, 3, 7): 7845 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7846 break; 7847 default: 7848 break; 7849 } 7850 7851 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7852 AMDGPU_MAX_COMPUTE_RINGS); 7853 7854 gfx_v10_0_set_kiq_pm4_funcs(adev); 7855 gfx_v10_0_set_ring_funcs(adev); 7856 gfx_v10_0_set_irq_funcs(adev); 7857 gfx_v10_0_set_gds_init(adev); 7858 gfx_v10_0_set_rlc_funcs(adev); 7859 gfx_v10_0_set_mqd_funcs(adev); 7860 7861 /* init rlcg reg access ctrl */ 7862 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7863 7864 return gfx_v10_0_init_microcode(adev); 7865 } 7866 7867 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7868 { 7869 uint32_t rlc_cntl; 7870 7871 /* if RLC is not enabled, do nothing */ 7872 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7873 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7874 } 7875 7876 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7877 { 7878 uint32_t data; 7879 unsigned int i; 7880 7881 data = RLC_SAFE_MODE__CMD_MASK; 7882 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7883 7884 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7885 case IP_VERSION(10, 3, 0): 7886 case IP_VERSION(10, 3, 2): 7887 case IP_VERSION(10, 3, 1): 7888 case IP_VERSION(10, 3, 4): 7889 case IP_VERSION(10, 3, 5): 7890 case IP_VERSION(10, 3, 6): 7891 case IP_VERSION(10, 3, 3): 7892 case IP_VERSION(10, 3, 7): 7893 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7894 7895 /* wait for RLC_SAFE_MODE */ 7896 for (i = 0; i < adev->usec_timeout; i++) { 7897 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7898 RLC_SAFE_MODE, CMD)) 7899 break; 7900 udelay(1); 7901 } 7902 break; 7903 default: 7904 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7905 7906 /* wait for RLC_SAFE_MODE */ 7907 for (i = 0; i < adev->usec_timeout; i++) { 7908 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7909 RLC_SAFE_MODE, CMD)) 7910 break; 7911 udelay(1); 7912 } 7913 break; 7914 } 7915 } 7916 7917 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7918 { 7919 uint32_t data; 7920 7921 data = RLC_SAFE_MODE__CMD_MASK; 7922 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7923 case IP_VERSION(10, 3, 0): 7924 case IP_VERSION(10, 3, 2): 7925 case IP_VERSION(10, 3, 1): 7926 case IP_VERSION(10, 3, 4): 7927 case IP_VERSION(10, 3, 5): 7928 case IP_VERSION(10, 3, 6): 7929 case IP_VERSION(10, 3, 3): 7930 case IP_VERSION(10, 3, 7): 7931 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7932 break; 7933 default: 7934 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7935 break; 7936 } 7937 } 7938 7939 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7940 bool enable) 7941 { 7942 uint32_t data, def; 7943 7944 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7945 return; 7946 7947 /* It is disabled by HW by default */ 7948 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7949 /* 0 - Disable some blocks' MGCG */ 7950 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7951 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7952 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7953 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7954 7955 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7956 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7957 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7958 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7959 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7960 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7961 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7962 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7963 7964 if (def != data) 7965 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7966 7967 /* MGLS is a global flag to control all MGLS in GFX */ 7968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7969 /* 2 - RLC memory Light sleep */ 7970 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7971 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7972 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7973 if (def != data) 7974 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7975 } 7976 /* 3 - CP memory Light sleep */ 7977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7978 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7979 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7980 if (def != data) 7981 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7982 } 7983 } 7984 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7985 /* 1 - MGCG_OVERRIDE */ 7986 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7987 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7988 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7989 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7990 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7991 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7992 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7993 if (def != data) 7994 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7995 7996 /* 2 - disable MGLS in CP */ 7997 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7998 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7999 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 8000 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 8001 } 8002 8003 /* 3 - disable MGLS in RLC */ 8004 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 8005 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 8006 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 8007 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 8008 } 8009 8010 } 8011 } 8012 8013 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 8014 bool enable) 8015 { 8016 uint32_t data, def; 8017 8018 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 8019 return; 8020 8021 /* Enable 3D CGCG/CGLS */ 8022 if (enable) { 8023 /* write cmd to clear cgcg/cgls ov */ 8024 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8025 8026 /* unset CGCG override */ 8027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8028 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 8029 8030 /* update CGCG and CGLS override bits */ 8031 if (def != data) 8032 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8033 8034 /* enable 3Dcgcg FSM(0x0000363f) */ 8035 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8036 data = 0; 8037 8038 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8039 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8040 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8041 8042 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8043 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8044 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8045 8046 if (def != data) 8047 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8048 8049 /* set IDLE_POLL_COUNT(0x00900100) */ 8050 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8051 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8052 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8053 if (def != data) 8054 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8055 } else { 8056 /* Disable CGCG/CGLS */ 8057 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8058 8059 /* disable cgcg, cgls should be disabled */ 8060 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8061 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8062 8063 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8064 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8065 8066 /* disable cgcg and cgls in FSM */ 8067 if (def != data) 8068 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8069 } 8070 } 8071 8072 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8073 bool enable) 8074 { 8075 uint32_t def, data; 8076 8077 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8078 return; 8079 8080 if (enable) { 8081 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8082 8083 /* unset CGCG override */ 8084 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8085 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8086 8087 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8088 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8089 8090 /* update CGCG and CGLS override bits */ 8091 if (def != data) 8092 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8093 8094 /* enable cgcg FSM(0x0000363F) */ 8095 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8096 data = 0; 8097 8098 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8099 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8100 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8101 8102 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8103 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8104 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8105 8106 if (def != data) 8107 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8108 8109 /* set IDLE_POLL_COUNT(0x00900100) */ 8110 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8111 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8112 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8113 if (def != data) 8114 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8115 } else { 8116 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8117 8118 /* reset CGCG/CGLS bits */ 8119 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8120 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8121 8122 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8123 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8124 8125 /* disable cgcg and cgls in FSM */ 8126 if (def != data) 8127 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8128 } 8129 } 8130 8131 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8132 bool enable) 8133 { 8134 uint32_t def, data; 8135 8136 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8137 return; 8138 8139 if (enable) { 8140 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8141 /* unset FGCG override */ 8142 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8143 /* update FGCG override bits */ 8144 if (def != data) 8145 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8146 8147 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8148 /* unset RLC SRAM CLK GATER override */ 8149 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8150 /* update RLC SRAM CLK GATER override bits */ 8151 if (def != data) 8152 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8153 } else { 8154 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8155 /* reset FGCG bits */ 8156 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8157 /* disable FGCG*/ 8158 if (def != data) 8159 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8160 8161 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8162 /* reset RLC SRAM CLK GATER bits */ 8163 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8164 /* disable RLC SRAM CLK*/ 8165 if (def != data) 8166 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8167 } 8168 } 8169 8170 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8171 { 8172 uint32_t reg_data = 0; 8173 uint32_t reg_idx = 0; 8174 uint32_t i; 8175 8176 const uint32_t tcp_ctrl_regs[] = { 8177 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8178 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8179 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8180 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8181 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8182 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8183 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8184 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8185 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8186 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8187 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8188 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8189 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8190 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8191 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8192 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8193 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8194 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8195 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8196 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8197 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8198 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8199 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8200 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8201 }; 8202 8203 const uint32_t tcp_ctrl_regs_nv12[] = { 8204 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8205 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8206 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8207 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8208 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8209 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8210 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8211 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8212 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8213 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8214 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8215 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8216 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8217 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8218 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8219 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8220 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8221 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8222 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8223 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8224 }; 8225 8226 const uint32_t sm_ctlr_regs[] = { 8227 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8228 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8229 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8230 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8231 }; 8232 8233 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8234 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8235 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8236 tcp_ctrl_regs_nv12[i]; 8237 reg_data = RREG32(reg_idx); 8238 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8239 WREG32(reg_idx, reg_data); 8240 } 8241 } else { 8242 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8243 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8244 tcp_ctrl_regs[i]; 8245 reg_data = RREG32(reg_idx); 8246 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8247 WREG32(reg_idx, reg_data); 8248 } 8249 } 8250 8251 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8252 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8253 sm_ctlr_regs[i]; 8254 reg_data = RREG32(reg_idx); 8255 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8256 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8257 WREG32(reg_idx, reg_data); 8258 } 8259 } 8260 8261 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8262 bool enable) 8263 { 8264 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8265 8266 if (enable) { 8267 /* enable FGCG firstly*/ 8268 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8269 /* CGCG/CGLS should be enabled after MGCG/MGLS 8270 * === MGCG + MGLS === 8271 */ 8272 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8273 /* === CGCG /CGLS for GFX 3D Only === */ 8274 gfx_v10_0_update_3d_clock_gating(adev, enable); 8275 /* === CGCG + CGLS === */ 8276 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8277 8278 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8279 IP_VERSION(10, 1, 10)) || 8280 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8281 IP_VERSION(10, 1, 1)) || 8282 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8283 IP_VERSION(10, 1, 2))) 8284 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8285 } else { 8286 /* CGCG/CGLS should be disabled before MGCG/MGLS 8287 * === CGCG + CGLS === 8288 */ 8289 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8290 /* === CGCG /CGLS for GFX 3D Only === */ 8291 gfx_v10_0_update_3d_clock_gating(adev, enable); 8292 /* === MGCG + MGLS === */ 8293 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8294 /* disable fgcg at last*/ 8295 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8296 } 8297 8298 if (adev->cg_flags & 8299 (AMD_CG_SUPPORT_GFX_MGCG | 8300 AMD_CG_SUPPORT_GFX_CGLS | 8301 AMD_CG_SUPPORT_GFX_CGCG | 8302 AMD_CG_SUPPORT_GFX_3D_CGCG | 8303 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8304 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8305 8306 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8307 8308 return 0; 8309 } 8310 8311 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8312 unsigned int vmid) 8313 { 8314 u32 reg, pre_data, data; 8315 8316 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8317 /* not for *_SOC15 */ 8318 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8319 pre_data = RREG32_NO_KIQ(reg); 8320 else 8321 pre_data = RREG32(reg); 8322 8323 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8324 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8325 8326 if (pre_data != data) { 8327 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8328 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8329 } else 8330 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8331 } 8332 } 8333 8334 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 8335 struct amdgpu_ring *ring, unsigned int vmid) 8336 { 8337 amdgpu_gfx_off_ctrl(adev, false); 8338 8339 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8340 8341 amdgpu_gfx_off_ctrl(adev, true); 8342 } 8343 8344 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8345 uint32_t offset, 8346 struct soc15_reg_rlcg *entries, int arr_size) 8347 { 8348 int i; 8349 uint32_t reg; 8350 8351 if (!entries) 8352 return false; 8353 8354 for (i = 0; i < arr_size; i++) { 8355 const struct soc15_reg_rlcg *entry; 8356 8357 entry = &entries[i]; 8358 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8359 if (offset == reg) 8360 return true; 8361 } 8362 8363 return false; 8364 } 8365 8366 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8367 { 8368 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8369 } 8370 8371 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8372 { 8373 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8374 8375 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8376 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8377 else 8378 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8379 8380 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8381 8382 /* 8383 * CGPG enablement required and the register to program the hysteresis value 8384 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8385 * in refclk count. Note that RLC FW is modified to take 16 bits from 8386 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8387 * 8388 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8389 * of CGPG enablement starting point. 8390 * Power/performance team will optimize it and might give a new value later. 8391 */ 8392 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8393 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8394 case IP_VERSION(10, 3, 1): 8395 case IP_VERSION(10, 3, 3): 8396 case IP_VERSION(10, 3, 6): 8397 case IP_VERSION(10, 3, 7): 8398 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8399 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8400 break; 8401 default: 8402 break; 8403 } 8404 } 8405 } 8406 8407 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8408 { 8409 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8410 8411 gfx_v10_cntl_power_gating(adev, enable); 8412 8413 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8414 } 8415 8416 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8417 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8418 .set_safe_mode = gfx_v10_0_set_safe_mode, 8419 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8420 .init = gfx_v10_0_rlc_init, 8421 .get_csb_size = gfx_v10_0_get_csb_size, 8422 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8423 .resume = gfx_v10_0_rlc_resume, 8424 .stop = gfx_v10_0_rlc_stop, 8425 .reset = gfx_v10_0_rlc_reset, 8426 .start = gfx_v10_0_rlc_start, 8427 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8428 }; 8429 8430 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8431 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8432 .set_safe_mode = gfx_v10_0_set_safe_mode, 8433 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8434 .init = gfx_v10_0_rlc_init, 8435 .get_csb_size = gfx_v10_0_get_csb_size, 8436 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8437 .resume = gfx_v10_0_rlc_resume, 8438 .stop = gfx_v10_0_rlc_stop, 8439 .reset = gfx_v10_0_rlc_reset, 8440 .start = gfx_v10_0_rlc_start, 8441 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8442 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8443 }; 8444 8445 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 8446 enum amd_powergating_state state) 8447 { 8448 struct amdgpu_device *adev = ip_block->adev; 8449 bool enable = (state == AMD_PG_STATE_GATE); 8450 8451 if (amdgpu_sriov_vf(adev)) 8452 return 0; 8453 8454 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8455 case IP_VERSION(10, 1, 10): 8456 case IP_VERSION(10, 1, 1): 8457 case IP_VERSION(10, 1, 2): 8458 case IP_VERSION(10, 3, 0): 8459 case IP_VERSION(10, 3, 2): 8460 case IP_VERSION(10, 3, 4): 8461 case IP_VERSION(10, 3, 5): 8462 amdgpu_gfx_off_ctrl(adev, enable); 8463 break; 8464 case IP_VERSION(10, 3, 1): 8465 case IP_VERSION(10, 3, 3): 8466 case IP_VERSION(10, 3, 6): 8467 case IP_VERSION(10, 3, 7): 8468 if (!enable) 8469 amdgpu_gfx_off_ctrl(adev, false); 8470 8471 gfx_v10_cntl_pg(adev, enable); 8472 8473 if (enable) 8474 amdgpu_gfx_off_ctrl(adev, true); 8475 8476 break; 8477 default: 8478 break; 8479 } 8480 return 0; 8481 } 8482 8483 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 8484 enum amd_clockgating_state state) 8485 { 8486 struct amdgpu_device *adev = ip_block->adev; 8487 8488 if (amdgpu_sriov_vf(adev)) 8489 return 0; 8490 8491 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8492 case IP_VERSION(10, 1, 10): 8493 case IP_VERSION(10, 1, 1): 8494 case IP_VERSION(10, 1, 2): 8495 case IP_VERSION(10, 3, 0): 8496 case IP_VERSION(10, 3, 2): 8497 case IP_VERSION(10, 3, 1): 8498 case IP_VERSION(10, 3, 4): 8499 case IP_VERSION(10, 3, 5): 8500 case IP_VERSION(10, 3, 6): 8501 case IP_VERSION(10, 3, 3): 8502 case IP_VERSION(10, 3, 7): 8503 gfx_v10_0_update_gfx_clock_gating(adev, 8504 state == AMD_CG_STATE_GATE); 8505 break; 8506 default: 8507 break; 8508 } 8509 return 0; 8510 } 8511 8512 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 8513 { 8514 struct amdgpu_device *adev = ip_block->adev; 8515 int data; 8516 8517 /* AMD_CG_SUPPORT_GFX_FGCG */ 8518 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8519 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8520 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8521 8522 /* AMD_CG_SUPPORT_GFX_MGCG */ 8523 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8524 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8525 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8526 8527 /* AMD_CG_SUPPORT_GFX_CGCG */ 8528 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8529 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8530 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8531 8532 /* AMD_CG_SUPPORT_GFX_CGLS */ 8533 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8534 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8535 8536 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8537 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8538 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8539 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8540 8541 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8542 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8543 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8544 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8545 8546 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8547 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8548 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8549 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8550 8551 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8552 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8553 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8554 } 8555 8556 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8557 { 8558 /* gfx10 is 32bit rptr*/ 8559 return *(uint32_t *)ring->rptr_cpu_addr; 8560 } 8561 8562 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8563 { 8564 struct amdgpu_device *adev = ring->adev; 8565 u64 wptr; 8566 8567 /* XXX check if swapping is necessary on BE */ 8568 if (ring->use_doorbell) { 8569 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8570 } else { 8571 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8572 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8573 } 8574 8575 return wptr; 8576 } 8577 8578 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8579 { 8580 struct amdgpu_device *adev = ring->adev; 8581 8582 if (ring->use_doorbell) { 8583 /* XXX check if swapping is necessary on BE */ 8584 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8585 ring->wptr); 8586 WDOORBELL64(ring->doorbell_index, ring->wptr); 8587 } else { 8588 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8589 lower_32_bits(ring->wptr)); 8590 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8591 upper_32_bits(ring->wptr)); 8592 } 8593 } 8594 8595 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8596 { 8597 /* gfx10 hardware is 32bit rptr */ 8598 return *(uint32_t *)ring->rptr_cpu_addr; 8599 } 8600 8601 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8602 { 8603 u64 wptr; 8604 8605 /* XXX check if swapping is necessary on BE */ 8606 if (ring->use_doorbell) 8607 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8608 else 8609 BUG(); 8610 return wptr; 8611 } 8612 8613 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8614 { 8615 struct amdgpu_device *adev = ring->adev; 8616 8617 if (ring->use_doorbell) { 8618 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8619 ring->wptr); 8620 WDOORBELL64(ring->doorbell_index, ring->wptr); 8621 } else { 8622 BUG(); /* only DOORBELL method supported on gfx10 now */ 8623 } 8624 } 8625 8626 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8627 { 8628 struct amdgpu_device *adev = ring->adev; 8629 u32 ref_and_mask, reg_mem_engine; 8630 8631 if (!adev->gfx.funcs->get_hdp_flush_mask) { 8632 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 8633 return; 8634 } 8635 8636 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 8637 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8638 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8639 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8640 ref_and_mask, ref_and_mask, 0x20); 8641 } 8642 8643 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8644 struct amdgpu_job *job, 8645 struct amdgpu_ib *ib, 8646 uint32_t flags) 8647 { 8648 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8649 u32 header, control = 0; 8650 8651 if (ib->flags & AMDGPU_IB_FLAG_CE) 8652 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8653 else 8654 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8655 8656 control |= ib->length_dw | (vmid << 24); 8657 8658 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8659 control |= INDIRECT_BUFFER_PRE_ENB(1); 8660 8661 if (flags & AMDGPU_IB_PREEMPTED) 8662 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8663 8664 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8665 gfx_v10_0_ring_emit_de_meta(ring, 8666 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8667 } 8668 8669 amdgpu_ring_write(ring, header); 8670 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 8671 amdgpu_ring_write(ring, 8672 #ifdef __BIG_ENDIAN 8673 (2 << 0) | 8674 #endif 8675 lower_32_bits(ib->gpu_addr)); 8676 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8677 amdgpu_ring_write(ring, control); 8678 } 8679 8680 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8681 struct amdgpu_job *job, 8682 struct amdgpu_ib *ib, 8683 uint32_t flags) 8684 { 8685 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8686 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8687 8688 /* Currently, there is a high possibility to get wave ID mismatch 8689 * between ME and GDS, leading to a hw deadlock, because ME generates 8690 * different wave IDs than the GDS expects. This situation happens 8691 * randomly when at least 5 compute pipes use GDS ordered append. 8692 * The wave IDs generated by ME are also wrong after suspend/resume. 8693 * Those are probably bugs somewhere else in the kernel driver. 8694 * 8695 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8696 * GDS to 0 for this ring (me/pipe). 8697 */ 8698 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8699 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8700 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8701 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8702 } 8703 8704 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8705 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 8706 amdgpu_ring_write(ring, 8707 #ifdef __BIG_ENDIAN 8708 (2 << 0) | 8709 #endif 8710 lower_32_bits(ib->gpu_addr)); 8711 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8712 amdgpu_ring_write(ring, control); 8713 } 8714 8715 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8716 u64 seq, unsigned int flags) 8717 { 8718 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8719 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8720 8721 /* RELEASE_MEM - flush caches, send int */ 8722 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8723 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8724 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8725 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8726 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8727 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8728 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8729 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8730 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8731 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8732 8733 /* 8734 * the address should be Qword aligned if 64bit write, Dword 8735 * aligned if only send 32bit data low (discard data high) 8736 */ 8737 if (write64bit) 8738 WARN_ON(addr & 0x7); 8739 else 8740 WARN_ON(addr & 0x3); 8741 amdgpu_ring_write(ring, lower_32_bits(addr)); 8742 amdgpu_ring_write(ring, upper_32_bits(addr)); 8743 amdgpu_ring_write(ring, lower_32_bits(seq)); 8744 amdgpu_ring_write(ring, upper_32_bits(seq)); 8745 amdgpu_ring_write(ring, 0); 8746 } 8747 8748 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8749 { 8750 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8751 uint32_t seq = ring->fence_drv.sync_seq; 8752 uint64_t addr = ring->fence_drv.gpu_addr; 8753 8754 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8755 upper_32_bits(addr), seq, 0xffffffff, 4); 8756 } 8757 8758 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8759 uint16_t pasid, uint32_t flush_type, 8760 bool all_hub, uint8_t dst_sel) 8761 { 8762 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8763 amdgpu_ring_write(ring, 8764 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8765 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8766 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8767 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8768 } 8769 8770 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8771 unsigned int vmid, uint64_t pd_addr) 8772 { 8773 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8774 8775 /* compute doesn't have PFP */ 8776 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8777 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8778 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8779 amdgpu_ring_write(ring, 0x0); 8780 } 8781 } 8782 8783 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8784 u64 seq, unsigned int flags) 8785 { 8786 struct amdgpu_device *adev = ring->adev; 8787 8788 /* write fence seq to the "addr" */ 8789 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8790 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8791 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8792 amdgpu_ring_write(ring, lower_32_bits(addr)); 8793 amdgpu_ring_write(ring, upper_32_bits(addr)); 8794 amdgpu_ring_write(ring, lower_32_bits(seq)); 8795 8796 if (flags & AMDGPU_FENCE_FLAG_INT) { 8797 /* set register to trigger INT */ 8798 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8799 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8800 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8801 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8802 amdgpu_ring_write(ring, 0); 8803 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8804 } 8805 } 8806 8807 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8808 { 8809 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8810 amdgpu_ring_write(ring, 0); 8811 } 8812 8813 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8814 uint32_t flags) 8815 { 8816 uint32_t dw2 = 0; 8817 8818 if (ring->adev->gfx.mcbp) 8819 gfx_v10_0_ring_emit_ce_meta(ring, 8820 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8821 8822 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8823 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8824 /* set load_global_config & load_global_uconfig */ 8825 dw2 |= 0x8001; 8826 /* set load_cs_sh_regs */ 8827 dw2 |= 0x01000000; 8828 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8829 dw2 |= 0x10002; 8830 8831 /* set load_ce_ram if preamble presented */ 8832 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8833 dw2 |= 0x10000000; 8834 } else { 8835 /* still load_ce_ram if this is the first time preamble presented 8836 * although there is no context switch happens. 8837 */ 8838 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8839 dw2 |= 0x10000000; 8840 } 8841 8842 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8843 amdgpu_ring_write(ring, dw2); 8844 amdgpu_ring_write(ring, 0); 8845 } 8846 8847 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8848 uint64_t addr) 8849 { 8850 unsigned int ret; 8851 8852 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8853 amdgpu_ring_write(ring, lower_32_bits(addr)); 8854 amdgpu_ring_write(ring, upper_32_bits(addr)); 8855 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8856 amdgpu_ring_write(ring, 0); 8857 ret = ring->wptr & ring->buf_mask; 8858 /* patch dummy value later */ 8859 amdgpu_ring_write(ring, 0); 8860 8861 return ret; 8862 } 8863 8864 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8865 { 8866 int i, r = 0; 8867 struct amdgpu_device *adev = ring->adev; 8868 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8869 struct amdgpu_ring *kiq_ring = &kiq->ring; 8870 unsigned long flags; 8871 8872 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8873 return -EINVAL; 8874 8875 spin_lock_irqsave(&kiq->ring_lock, flags); 8876 8877 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8878 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8879 return -ENOMEM; 8880 } 8881 8882 /* assert preemption condition */ 8883 amdgpu_ring_set_preempt_cond_exec(ring, false); 8884 8885 /* assert IB preemption, emit the trailing fence */ 8886 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8887 ring->trail_fence_gpu_addr, 8888 ++ring->trail_seq); 8889 amdgpu_ring_commit(kiq_ring); 8890 8891 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8892 8893 /* poll the trailing fence */ 8894 for (i = 0; i < adev->usec_timeout; i++) { 8895 if (ring->trail_seq == 8896 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8897 break; 8898 udelay(1); 8899 } 8900 8901 if (i >= adev->usec_timeout) { 8902 r = -EINVAL; 8903 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8904 } 8905 8906 /* deassert preemption condition */ 8907 amdgpu_ring_set_preempt_cond_exec(ring, true); 8908 return r; 8909 } 8910 8911 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8912 { 8913 struct amdgpu_device *adev = ring->adev; 8914 struct v10_ce_ib_state ce_payload = {0}; 8915 uint64_t offset, ce_payload_gpu_addr; 8916 void *ce_payload_cpu_addr; 8917 int cnt; 8918 8919 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8920 8921 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8922 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8923 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8924 8925 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8926 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8927 WRITE_DATA_DST_SEL(8) | 8928 WR_CONFIRM) | 8929 WRITE_DATA_CACHE_POLICY(0)); 8930 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8931 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8932 8933 if (resume) 8934 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8935 sizeof(ce_payload) >> 2); 8936 else 8937 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8938 sizeof(ce_payload) >> 2); 8939 } 8940 8941 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8942 { 8943 struct amdgpu_device *adev = ring->adev; 8944 struct v10_de_ib_state de_payload = {0}; 8945 uint64_t offset, gds_addr, de_payload_gpu_addr; 8946 void *de_payload_cpu_addr; 8947 int cnt; 8948 8949 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8950 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8951 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8952 8953 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8954 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8955 PAGE_SIZE); 8956 8957 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8958 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8959 8960 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8961 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8962 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8963 WRITE_DATA_DST_SEL(8) | 8964 WR_CONFIRM) | 8965 WRITE_DATA_CACHE_POLICY(0)); 8966 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8967 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8968 8969 if (resume) 8970 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8971 sizeof(de_payload) >> 2); 8972 else 8973 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8974 sizeof(de_payload) >> 2); 8975 } 8976 8977 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8978 bool secure) 8979 { 8980 uint32_t v = secure ? FRAME_TMZ : 0; 8981 8982 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8983 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8984 } 8985 8986 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8987 uint32_t reg_val_offs) 8988 { 8989 struct amdgpu_device *adev = ring->adev; 8990 8991 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8992 amdgpu_ring_write(ring, 0 | /* src: register*/ 8993 (5 << 8) | /* dst: memory */ 8994 (1 << 20)); /* write confirm */ 8995 amdgpu_ring_write(ring, reg); 8996 amdgpu_ring_write(ring, 0); 8997 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8998 reg_val_offs * 4)); 8999 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 9000 reg_val_offs * 4)); 9001 } 9002 9003 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 9004 uint32_t val) 9005 { 9006 uint32_t cmd = 0; 9007 9008 switch (ring->funcs->type) { 9009 case AMDGPU_RING_TYPE_GFX: 9010 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 9011 break; 9012 case AMDGPU_RING_TYPE_KIQ: 9013 cmd = (1 << 16); /* no inc addr */ 9014 break; 9015 default: 9016 cmd = WR_CONFIRM; 9017 break; 9018 } 9019 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 9020 amdgpu_ring_write(ring, cmd); 9021 amdgpu_ring_write(ring, reg); 9022 amdgpu_ring_write(ring, 0); 9023 amdgpu_ring_write(ring, val); 9024 } 9025 9026 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 9027 uint32_t val, uint32_t mask) 9028 { 9029 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 9030 } 9031 9032 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 9033 uint32_t reg0, uint32_t reg1, 9034 uint32_t ref, uint32_t mask) 9035 { 9036 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 9037 struct amdgpu_device *adev = ring->adev; 9038 bool fw_version_ok = false; 9039 9040 fw_version_ok = adev->gfx.cp_fw_write_wait; 9041 9042 if (fw_version_ok) 9043 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 9044 ref, mask, 0x20); 9045 else 9046 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 9047 ref, mask); 9048 } 9049 9050 static void 9051 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9052 uint32_t me, uint32_t pipe, 9053 enum amdgpu_interrupt_state state) 9054 { 9055 uint32_t cp_int_cntl, cp_int_cntl_reg; 9056 9057 if (!me) { 9058 switch (pipe) { 9059 case 0: 9060 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9061 break; 9062 case 1: 9063 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9064 break; 9065 default: 9066 DRM_DEBUG("invalid pipe %d\n", pipe); 9067 return; 9068 } 9069 } else { 9070 DRM_DEBUG("invalid me %d\n", me); 9071 return; 9072 } 9073 9074 switch (state) { 9075 case AMDGPU_IRQ_STATE_DISABLE: 9076 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9077 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9078 TIME_STAMP_INT_ENABLE, 0); 9079 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9080 break; 9081 case AMDGPU_IRQ_STATE_ENABLE: 9082 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9083 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9084 TIME_STAMP_INT_ENABLE, 1); 9085 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9086 break; 9087 default: 9088 break; 9089 } 9090 } 9091 9092 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9093 int me, int pipe, 9094 enum amdgpu_interrupt_state state) 9095 { 9096 u32 mec_int_cntl, mec_int_cntl_reg; 9097 9098 /* 9099 * amdgpu controls only the first MEC. That's why this function only 9100 * handles the setting of interrupts for this specific MEC. All other 9101 * pipes' interrupts are set by amdkfd. 9102 */ 9103 9104 if (me == 1) { 9105 switch (pipe) { 9106 case 0: 9107 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9108 break; 9109 case 1: 9110 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9111 break; 9112 case 2: 9113 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9114 break; 9115 case 3: 9116 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9117 break; 9118 default: 9119 DRM_DEBUG("invalid pipe %d\n", pipe); 9120 return; 9121 } 9122 } else { 9123 DRM_DEBUG("invalid me %d\n", me); 9124 return; 9125 } 9126 9127 switch (state) { 9128 case AMDGPU_IRQ_STATE_DISABLE: 9129 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9130 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9131 TIME_STAMP_INT_ENABLE, 0); 9132 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9133 break; 9134 case AMDGPU_IRQ_STATE_ENABLE: 9135 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9136 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9137 TIME_STAMP_INT_ENABLE, 1); 9138 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9139 break; 9140 default: 9141 break; 9142 } 9143 } 9144 9145 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9146 struct amdgpu_irq_src *src, 9147 unsigned int type, 9148 enum amdgpu_interrupt_state state) 9149 { 9150 switch (type) { 9151 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9152 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9153 break; 9154 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9155 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9156 break; 9157 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9158 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9159 break; 9160 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9161 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9162 break; 9163 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9164 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9165 break; 9166 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9167 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9168 break; 9169 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9170 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9171 break; 9172 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9173 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9174 break; 9175 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9176 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9177 break; 9178 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9179 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9180 break; 9181 default: 9182 break; 9183 } 9184 return 0; 9185 } 9186 9187 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9188 struct amdgpu_irq_src *source, 9189 struct amdgpu_iv_entry *entry) 9190 { 9191 int i; 9192 u8 me_id, pipe_id, queue_id; 9193 struct amdgpu_ring *ring; 9194 9195 DRM_DEBUG("IH: CP EOP\n"); 9196 9197 me_id = (entry->ring_id & 0x0c) >> 2; 9198 pipe_id = (entry->ring_id & 0x03) >> 0; 9199 queue_id = (entry->ring_id & 0x70) >> 4; 9200 9201 switch (me_id) { 9202 case 0: 9203 if (pipe_id == 0) 9204 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9205 else 9206 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9207 break; 9208 case 1: 9209 case 2: 9210 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9211 ring = &adev->gfx.compute_ring[i]; 9212 /* Per-queue interrupt is supported for MEC starting from VI. 9213 * The interrupt can only be enabled/disabled per pipe instead 9214 * of per queue. 9215 */ 9216 if ((ring->me == me_id) && 9217 (ring->pipe == pipe_id) && 9218 (ring->queue == queue_id)) 9219 amdgpu_fence_process(ring); 9220 } 9221 break; 9222 } 9223 9224 return 0; 9225 } 9226 9227 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9228 struct amdgpu_irq_src *source, 9229 unsigned int type, 9230 enum amdgpu_interrupt_state state) 9231 { 9232 u32 cp_int_cntl_reg, cp_int_cntl; 9233 int i, j; 9234 9235 switch (state) { 9236 case AMDGPU_IRQ_STATE_DISABLE: 9237 case AMDGPU_IRQ_STATE_ENABLE: 9238 for (i = 0; i < adev->gfx.me.num_me; i++) { 9239 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9240 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9241 9242 if (cp_int_cntl_reg) { 9243 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9244 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9245 PRIV_REG_INT_ENABLE, 9246 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9247 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9248 } 9249 } 9250 } 9251 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9252 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9253 /* MECs start at 1 */ 9254 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9255 9256 if (cp_int_cntl_reg) { 9257 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9258 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9259 PRIV_REG_INT_ENABLE, 9260 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9261 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9262 } 9263 } 9264 } 9265 break; 9266 default: 9267 break; 9268 } 9269 9270 return 0; 9271 } 9272 9273 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9274 struct amdgpu_irq_src *source, 9275 unsigned type, 9276 enum amdgpu_interrupt_state state) 9277 { 9278 u32 cp_int_cntl_reg, cp_int_cntl; 9279 int i, j; 9280 9281 switch (state) { 9282 case AMDGPU_IRQ_STATE_DISABLE: 9283 case AMDGPU_IRQ_STATE_ENABLE: 9284 for (i = 0; i < adev->gfx.me.num_me; i++) { 9285 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9286 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9287 9288 if (cp_int_cntl_reg) { 9289 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9290 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9291 OPCODE_ERROR_INT_ENABLE, 9292 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9293 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9294 } 9295 } 9296 } 9297 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9298 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9299 /* MECs start at 1 */ 9300 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9301 9302 if (cp_int_cntl_reg) { 9303 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9304 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9305 OPCODE_ERROR_INT_ENABLE, 9306 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9307 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9308 } 9309 } 9310 } 9311 break; 9312 default: 9313 break; 9314 } 9315 return 0; 9316 } 9317 9318 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9319 struct amdgpu_irq_src *source, 9320 unsigned int type, 9321 enum amdgpu_interrupt_state state) 9322 { 9323 u32 cp_int_cntl_reg, cp_int_cntl; 9324 int i, j; 9325 9326 switch (state) { 9327 case AMDGPU_IRQ_STATE_DISABLE: 9328 case AMDGPU_IRQ_STATE_ENABLE: 9329 for (i = 0; i < adev->gfx.me.num_me; i++) { 9330 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9331 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9332 9333 if (cp_int_cntl_reg) { 9334 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9335 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9336 PRIV_INSTR_INT_ENABLE, 9337 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9338 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9339 } 9340 } 9341 } 9342 break; 9343 default: 9344 break; 9345 } 9346 9347 return 0; 9348 } 9349 9350 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9351 struct amdgpu_iv_entry *entry) 9352 { 9353 u8 me_id, pipe_id, queue_id; 9354 struct amdgpu_ring *ring; 9355 int i; 9356 9357 me_id = (entry->ring_id & 0x0c) >> 2; 9358 pipe_id = (entry->ring_id & 0x03) >> 0; 9359 queue_id = (entry->ring_id & 0x70) >> 4; 9360 9361 switch (me_id) { 9362 case 0: 9363 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9364 ring = &adev->gfx.gfx_ring[i]; 9365 if (ring->me == me_id && ring->pipe == pipe_id && 9366 ring->queue == queue_id) 9367 drm_sched_fault(&ring->sched); 9368 } 9369 break; 9370 case 1: 9371 case 2: 9372 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9373 ring = &adev->gfx.compute_ring[i]; 9374 if (ring->me == me_id && ring->pipe == pipe_id && 9375 ring->queue == queue_id) 9376 drm_sched_fault(&ring->sched); 9377 } 9378 break; 9379 default: 9380 BUG(); 9381 } 9382 } 9383 9384 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9385 struct amdgpu_irq_src *source, 9386 struct amdgpu_iv_entry *entry) 9387 { 9388 DRM_ERROR("Illegal register access in command stream\n"); 9389 gfx_v10_0_handle_priv_fault(adev, entry); 9390 return 0; 9391 } 9392 9393 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9394 struct amdgpu_irq_src *source, 9395 struct amdgpu_iv_entry *entry) 9396 { 9397 DRM_ERROR("Illegal opcode in command stream\n"); 9398 gfx_v10_0_handle_priv_fault(adev, entry); 9399 return 0; 9400 } 9401 9402 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9403 struct amdgpu_irq_src *source, 9404 struct amdgpu_iv_entry *entry) 9405 { 9406 DRM_ERROR("Illegal instruction in command stream\n"); 9407 gfx_v10_0_handle_priv_fault(adev, entry); 9408 return 0; 9409 } 9410 9411 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9412 struct amdgpu_irq_src *src, 9413 unsigned int type, 9414 enum amdgpu_interrupt_state state) 9415 { 9416 uint32_t tmp, target; 9417 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9418 9419 if (ring->me == 1) 9420 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9421 else 9422 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9423 target += ring->pipe; 9424 9425 switch (type) { 9426 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9427 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9428 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9429 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9430 GENERIC2_INT_ENABLE, 0); 9431 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9432 9433 tmp = RREG32_SOC15_IP(GC, target); 9434 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9435 GENERIC2_INT_ENABLE, 0); 9436 WREG32_SOC15_IP(GC, target, tmp); 9437 } else { 9438 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9439 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9440 GENERIC2_INT_ENABLE, 1); 9441 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9442 9443 tmp = RREG32_SOC15_IP(GC, target); 9444 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9445 GENERIC2_INT_ENABLE, 1); 9446 WREG32_SOC15_IP(GC, target, tmp); 9447 } 9448 break; 9449 default: 9450 BUG(); /* kiq only support GENERIC2_INT now */ 9451 break; 9452 } 9453 return 0; 9454 } 9455 9456 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9457 struct amdgpu_irq_src *source, 9458 struct amdgpu_iv_entry *entry) 9459 { 9460 u8 me_id, pipe_id, queue_id; 9461 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9462 9463 me_id = (entry->ring_id & 0x0c) >> 2; 9464 pipe_id = (entry->ring_id & 0x03) >> 0; 9465 queue_id = (entry->ring_id & 0x70) >> 4; 9466 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9467 me_id, pipe_id, queue_id); 9468 9469 amdgpu_fence_process(ring); 9470 return 0; 9471 } 9472 9473 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9474 { 9475 const unsigned int gcr_cntl = 9476 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9477 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9478 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9479 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9480 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9481 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9482 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9483 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9484 9485 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9486 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9487 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9488 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9489 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9490 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9491 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9492 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9493 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9494 } 9495 9496 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9497 { 9498 /* Header itself is a NOP packet */ 9499 if (num_nop == 1) { 9500 amdgpu_ring_write(ring, ring->funcs->nop); 9501 return; 9502 } 9503 9504 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9505 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9506 9507 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9508 amdgpu_ring_insert_nop(ring, num_nop - 1); 9509 } 9510 9511 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, 9512 unsigned int vmid, 9513 struct amdgpu_fence *timedout_fence) 9514 { 9515 struct amdgpu_device *adev = ring->adev; 9516 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9517 struct amdgpu_ring *kiq_ring = &kiq->ring; 9518 unsigned long flags; 9519 u32 tmp; 9520 u64 addr; 9521 int r; 9522 9523 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9524 return -EINVAL; 9525 9526 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 9527 9528 spin_lock_irqsave(&kiq->ring_lock, flags); 9529 9530 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) { 9531 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9532 return -ENOMEM; 9533 } 9534 9535 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + 9536 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); 9537 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 9538 if (ring->pipe == 0) 9539 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); 9540 else 9541 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); 9542 9543 gfx_v10_0_ring_emit_wreg(kiq_ring, 9544 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); 9545 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, 9546 lower_32_bits(addr), upper_32_bits(addr), 9547 0, 1, 0x20); 9548 gfx_v10_0_ring_emit_reg_wait(kiq_ring, 9549 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); 9550 amdgpu_ring_commit(kiq_ring); 9551 r = amdgpu_ring_test_ring(kiq_ring); 9552 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9553 if (r) 9554 return r; 9555 9556 r = gfx_v10_0_kgq_init_queue(ring, true); 9557 if (r) { 9558 DRM_ERROR("fail to init kgq\n"); 9559 return r; 9560 } 9561 9562 spin_lock_irqsave(&kiq->ring_lock, flags); 9563 9564 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9565 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9566 return -ENOMEM; 9567 } 9568 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9569 amdgpu_ring_commit(kiq_ring); 9570 r = amdgpu_ring_test_ring(kiq_ring); 9571 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9572 if (r) 9573 return r; 9574 9575 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 9576 } 9577 9578 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, 9579 unsigned int vmid, 9580 struct amdgpu_fence *timedout_fence) 9581 { 9582 struct amdgpu_device *adev = ring->adev; 9583 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9584 struct amdgpu_ring *kiq_ring = &kiq->ring; 9585 unsigned long flags; 9586 int i, r; 9587 9588 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9589 return -EINVAL; 9590 9591 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 9592 9593 spin_lock_irqsave(&kiq->ring_lock, flags); 9594 9595 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 9596 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9597 return -ENOMEM; 9598 } 9599 9600 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 9601 0, 0); 9602 amdgpu_ring_commit(kiq_ring); 9603 r = amdgpu_ring_test_ring(kiq_ring); 9604 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9605 if (r) 9606 return r; 9607 9608 /* make sure dequeue is complete*/ 9609 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9610 mutex_lock(&adev->srbm_mutex); 9611 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 9612 for (i = 0; i < adev->usec_timeout; i++) { 9613 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 9614 break; 9615 udelay(1); 9616 } 9617 if (i >= adev->usec_timeout) 9618 r = -ETIMEDOUT; 9619 nv_grbm_select(adev, 0, 0, 0, 0); 9620 mutex_unlock(&adev->srbm_mutex); 9621 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9622 if (r) { 9623 dev_err(adev->dev, "fail to wait on hqd deactivate\n"); 9624 return r; 9625 } 9626 9627 r = gfx_v10_0_kcq_init_queue(ring, true); 9628 if (r) { 9629 dev_err(adev->dev, "fail to init kcq\n"); 9630 return r; 9631 } 9632 9633 spin_lock_irqsave(&kiq->ring_lock, flags); 9634 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9635 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9636 return -ENOMEM; 9637 } 9638 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9639 amdgpu_ring_commit(kiq_ring); 9640 r = amdgpu_ring_test_ring(kiq_ring); 9641 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9642 if (r) 9643 return r; 9644 9645 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 9646 } 9647 9648 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 9649 { 9650 struct amdgpu_device *adev = ip_block->adev; 9651 uint32_t i, j, k, reg, index = 0; 9652 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9653 9654 if (!adev->gfx.ip_dump_core) 9655 return; 9656 9657 for (i = 0; i < reg_count; i++) 9658 drm_printf(p, "%-50s \t 0x%08x\n", 9659 gc_reg_list_10_1[i].reg_name, 9660 adev->gfx.ip_dump_core[i]); 9661 9662 /* print compute queue registers for all instances */ 9663 if (!adev->gfx.ip_dump_compute_queues) 9664 return; 9665 9666 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9667 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9668 adev->gfx.mec.num_mec, 9669 adev->gfx.mec.num_pipe_per_mec, 9670 adev->gfx.mec.num_queue_per_pipe); 9671 9672 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9673 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9674 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9675 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9676 for (reg = 0; reg < reg_count; reg++) { 9677 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9678 drm_printf(p, "%-50s \t 0x%08x\n", 9679 "mmCP_MEC_ME2_HEADER_DUMP", 9680 adev->gfx.ip_dump_compute_queues[index + reg]); 9681 else 9682 drm_printf(p, "%-50s \t 0x%08x\n", 9683 gc_cp_reg_list_10[reg].reg_name, 9684 adev->gfx.ip_dump_compute_queues[index + reg]); 9685 } 9686 index += reg_count; 9687 } 9688 } 9689 } 9690 9691 /* print gfx queue registers for all instances */ 9692 if (!adev->gfx.ip_dump_gfx_queues) 9693 return; 9694 9695 index = 0; 9696 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9697 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9698 adev->gfx.me.num_me, 9699 adev->gfx.me.num_pipe_per_me, 9700 adev->gfx.me.num_queue_per_pipe); 9701 9702 for (i = 0; i < adev->gfx.me.num_me; i++) { 9703 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9704 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9705 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9706 for (reg = 0; reg < reg_count; reg++) { 9707 drm_printf(p, "%-50s \t 0x%08x\n", 9708 gc_gfx_queue_reg_list_10[reg].reg_name, 9709 adev->gfx.ip_dump_gfx_queues[index + reg]); 9710 } 9711 index += reg_count; 9712 } 9713 } 9714 } 9715 } 9716 9717 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) 9718 { 9719 struct amdgpu_device *adev = ip_block->adev; 9720 uint32_t i, j, k, reg, index = 0; 9721 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9722 9723 if (!adev->gfx.ip_dump_core) 9724 return; 9725 9726 amdgpu_gfx_off_ctrl(adev, false); 9727 for (i = 0; i < reg_count; i++) 9728 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9729 amdgpu_gfx_off_ctrl(adev, true); 9730 9731 /* dump compute queue registers for all instances */ 9732 if (!adev->gfx.ip_dump_compute_queues) 9733 return; 9734 9735 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9736 amdgpu_gfx_off_ctrl(adev, false); 9737 mutex_lock(&adev->srbm_mutex); 9738 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9739 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9740 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9741 /* ME0 is for GFX so start from 1 for CP */ 9742 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9743 9744 for (reg = 0; reg < reg_count; reg++) { 9745 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9746 adev->gfx.ip_dump_compute_queues[index + reg] = 9747 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP)); 9748 else 9749 adev->gfx.ip_dump_compute_queues[index + reg] = 9750 RREG32(SOC15_REG_ENTRY_OFFSET( 9751 gc_cp_reg_list_10[reg])); 9752 } 9753 index += reg_count; 9754 } 9755 } 9756 } 9757 nv_grbm_select(adev, 0, 0, 0, 0); 9758 mutex_unlock(&adev->srbm_mutex); 9759 amdgpu_gfx_off_ctrl(adev, true); 9760 9761 /* dump gfx queue registers for all instances */ 9762 if (!adev->gfx.ip_dump_gfx_queues) 9763 return; 9764 9765 index = 0; 9766 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9767 amdgpu_gfx_off_ctrl(adev, false); 9768 mutex_lock(&adev->srbm_mutex); 9769 for (i = 0; i < adev->gfx.me.num_me; i++) { 9770 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9771 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9772 nv_grbm_select(adev, i, j, k, 0); 9773 9774 for (reg = 0; reg < reg_count; reg++) { 9775 adev->gfx.ip_dump_gfx_queues[index + reg] = 9776 RREG32(SOC15_REG_ENTRY_OFFSET( 9777 gc_gfx_queue_reg_list_10[reg])); 9778 } 9779 index += reg_count; 9780 } 9781 } 9782 } 9783 nv_grbm_select(adev, 0, 0, 0, 0); 9784 mutex_unlock(&adev->srbm_mutex); 9785 amdgpu_gfx_off_ctrl(adev, true); 9786 } 9787 9788 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 9789 { 9790 /* Emit the cleaner shader */ 9791 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 9792 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 9793 } 9794 9795 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring) 9796 { 9797 amdgpu_gfx_profile_ring_begin_use(ring); 9798 9799 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 9800 } 9801 9802 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) 9803 { 9804 amdgpu_gfx_profile_ring_end_use(ring); 9805 9806 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 9807 } 9808 9809 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9810 .name = "gfx_v10_0", 9811 .early_init = gfx_v10_0_early_init, 9812 .sw_init = gfx_v10_0_sw_init, 9813 .sw_fini = gfx_v10_0_sw_fini, 9814 .hw_init = gfx_v10_0_hw_init, 9815 .hw_fini = gfx_v10_0_hw_fini, 9816 .suspend = gfx_v10_0_suspend, 9817 .resume = gfx_v10_0_resume, 9818 .is_idle = gfx_v10_0_is_idle, 9819 .wait_for_idle = gfx_v10_0_wait_for_idle, 9820 .soft_reset = gfx_v10_0_soft_reset, 9821 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9822 .set_powergating_state = gfx_v10_0_set_powergating_state, 9823 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9824 .dump_ip_state = gfx_v10_ip_dump, 9825 .print_ip_state = gfx_v10_ip_print, 9826 }; 9827 9828 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9829 .type = AMDGPU_RING_TYPE_GFX, 9830 .align_mask = 0xff, 9831 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9832 .support_64bit_ptrs = true, 9833 .secure_submission_supported = true, 9834 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9835 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9836 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9837 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9838 5 + /* COND_EXEC */ 9839 7 + /* PIPELINE_SYNC */ 9840 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9841 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9842 4 + /* VM_FLUSH */ 9843 8 + /* FENCE for VM_FLUSH */ 9844 20 + /* GDS switch */ 9845 4 + /* double SWITCH_BUFFER, 9846 * the first COND_EXEC jump to the place 9847 * just prior to this double SWITCH_BUFFER 9848 */ 9849 5 + /* COND_EXEC */ 9850 7 + /* HDP_flush */ 9851 4 + /* VGT_flush */ 9852 14 + /* CE_META */ 9853 31 + /* DE_META */ 9854 3 + /* CNTX_CTRL */ 9855 5 + /* HDP_INVL */ 9856 8 + 8 + /* FENCE x2 */ 9857 2 + /* SWITCH_BUFFER */ 9858 8 + /* gfx_v10_0_emit_mem_sync */ 9859 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9860 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9861 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9862 .emit_fence = gfx_v10_0_ring_emit_fence, 9863 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9864 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9865 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9866 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9867 .test_ring = gfx_v10_0_ring_test_ring, 9868 .test_ib = gfx_v10_0_ring_test_ib, 9869 .insert_nop = gfx_v10_ring_insert_nop, 9870 .pad_ib = amdgpu_ring_generic_pad_ib, 9871 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9872 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9873 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9874 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9875 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9876 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9877 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9878 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9879 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9880 .reset = gfx_v10_0_reset_kgq, 9881 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9882 .begin_use = gfx_v10_0_ring_begin_use, 9883 .end_use = gfx_v10_0_ring_end_use, 9884 }; 9885 9886 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9887 .type = AMDGPU_RING_TYPE_COMPUTE, 9888 .align_mask = 0xff, 9889 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9890 .support_64bit_ptrs = true, 9891 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9892 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9893 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9894 .emit_frame_size = 9895 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9896 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9897 5 + /* hdp invalidate */ 9898 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9899 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9900 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9901 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9902 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9903 8 + /* gfx_v10_0_emit_mem_sync */ 9904 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9905 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9906 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9907 .emit_fence = gfx_v10_0_ring_emit_fence, 9908 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9909 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9910 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9911 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9912 .test_ring = gfx_v10_0_ring_test_ring, 9913 .test_ib = gfx_v10_0_ring_test_ib, 9914 .insert_nop = gfx_v10_ring_insert_nop, 9915 .pad_ib = amdgpu_ring_generic_pad_ib, 9916 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9917 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9918 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9919 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9920 .reset = gfx_v10_0_reset_kcq, 9921 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9922 .begin_use = gfx_v10_0_ring_begin_use, 9923 .end_use = gfx_v10_0_ring_end_use, 9924 }; 9925 9926 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9927 .type = AMDGPU_RING_TYPE_KIQ, 9928 .align_mask = 0xff, 9929 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9930 .support_64bit_ptrs = true, 9931 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9932 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9933 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9934 .emit_frame_size = 9935 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9936 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9937 5 + /*hdp invalidate */ 9938 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9939 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9940 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9941 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9942 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9943 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9944 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9945 .test_ring = gfx_v10_0_ring_test_ring, 9946 .test_ib = gfx_v10_0_ring_test_ib, 9947 .insert_nop = amdgpu_ring_insert_nop, 9948 .pad_ib = amdgpu_ring_generic_pad_ib, 9949 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9950 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9951 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9952 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9953 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9954 }; 9955 9956 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9957 { 9958 int i; 9959 9960 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9961 9962 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9963 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9964 9965 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9966 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9967 } 9968 9969 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9970 .set = gfx_v10_0_set_eop_interrupt_state, 9971 .process = gfx_v10_0_eop_irq, 9972 }; 9973 9974 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9975 .set = gfx_v10_0_set_priv_reg_fault_state, 9976 .process = gfx_v10_0_priv_reg_irq, 9977 }; 9978 9979 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 9980 .set = gfx_v10_0_set_bad_op_fault_state, 9981 .process = gfx_v10_0_bad_op_irq, 9982 }; 9983 9984 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9985 .set = gfx_v10_0_set_priv_inst_fault_state, 9986 .process = gfx_v10_0_priv_inst_irq, 9987 }; 9988 9989 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9990 .set = gfx_v10_0_kiq_set_interrupt_state, 9991 .process = gfx_v10_0_kiq_irq, 9992 }; 9993 9994 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9995 { 9996 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9997 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9998 9999 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 10000 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 10001 10002 adev->gfx.priv_reg_irq.num_types = 1; 10003 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 10004 10005 adev->gfx.bad_op_irq.num_types = 1; 10006 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 10007 10008 adev->gfx.priv_inst_irq.num_types = 1; 10009 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 10010 } 10011 10012 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 10013 { 10014 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 10015 case IP_VERSION(10, 1, 10): 10016 case IP_VERSION(10, 1, 1): 10017 case IP_VERSION(10, 1, 3): 10018 case IP_VERSION(10, 1, 4): 10019 case IP_VERSION(10, 3, 2): 10020 case IP_VERSION(10, 3, 1): 10021 case IP_VERSION(10, 3, 4): 10022 case IP_VERSION(10, 3, 5): 10023 case IP_VERSION(10, 3, 6): 10024 case IP_VERSION(10, 3, 3): 10025 case IP_VERSION(10, 3, 7): 10026 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 10027 break; 10028 case IP_VERSION(10, 1, 2): 10029 case IP_VERSION(10, 3, 0): 10030 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 10031 break; 10032 default: 10033 break; 10034 } 10035 } 10036 10037 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 10038 { 10039 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 10040 adev->gfx.config.max_sh_per_se * 10041 adev->gfx.config.max_shader_engines; 10042 10043 adev->gds.gds_size = 0x10000; 10044 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 10045 adev->gds.gws_size = 64; 10046 adev->gds.oa_size = 16; 10047 } 10048 10049 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 10050 { 10051 /* set gfx eng mqd */ 10052 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 10053 sizeof(struct v10_gfx_mqd); 10054 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 10055 gfx_v10_0_gfx_mqd_init; 10056 /* set compute eng mqd */ 10057 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 10058 sizeof(struct v10_compute_mqd); 10059 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 10060 gfx_v10_0_compute_mqd_init; 10061 } 10062 10063 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 10064 u32 bitmap) 10065 { 10066 u32 data; 10067 10068 if (!bitmap) 10069 return; 10070 10071 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10072 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10073 10074 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 10075 } 10076 10077 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 10078 { 10079 u32 disabled_mask = 10080 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 10081 u32 efuse_setting = 0; 10082 u32 vbios_setting = 0; 10083 10084 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 10085 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10086 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10087 10088 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 10089 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10090 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10091 10092 disabled_mask |= efuse_setting | vbios_setting; 10093 10094 return (~disabled_mask); 10095 } 10096 10097 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 10098 { 10099 u32 wgp_idx, wgp_active_bitmap; 10100 u32 cu_bitmap_per_wgp, cu_active_bitmap; 10101 10102 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 10103 cu_active_bitmap = 0; 10104 10105 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 10106 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 10107 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 10108 if (wgp_active_bitmap & (1 << wgp_idx)) 10109 cu_active_bitmap |= cu_bitmap_per_wgp; 10110 } 10111 10112 return cu_active_bitmap; 10113 } 10114 10115 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 10116 struct amdgpu_cu_info *cu_info) 10117 { 10118 int i, j, k, counter, active_cu_number = 0; 10119 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 10120 unsigned int disable_masks[4 * 2]; 10121 10122 if (!adev || !cu_info) 10123 return -EINVAL; 10124 10125 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 10126 10127 mutex_lock(&adev->grbm_idx_mutex); 10128 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 10129 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 10130 bitmap = i * adev->gfx.config.max_sh_per_se + j; 10131 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 10132 IP_VERSION(10, 3, 0)) || 10133 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10134 IP_VERSION(10, 3, 3)) || 10135 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10136 IP_VERSION(10, 3, 6)) || 10137 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10138 IP_VERSION(10, 3, 7))) && 10139 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 10140 continue; 10141 mask = 1; 10142 ao_bitmap = 0; 10143 counter = 0; 10144 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 10145 if (i < 4 && j < 2) 10146 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 10147 adev, disable_masks[i * 2 + j]); 10148 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 10149 cu_info->bitmap[0][i][j] = bitmap; 10150 10151 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 10152 if (bitmap & mask) { 10153 if (counter < adev->gfx.config.max_cu_per_sh) 10154 ao_bitmap |= mask; 10155 counter++; 10156 } 10157 mask <<= 1; 10158 } 10159 active_cu_number += counter; 10160 if (i < 2 && j < 2) 10161 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 10162 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 10163 } 10164 } 10165 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 10166 mutex_unlock(&adev->grbm_idx_mutex); 10167 10168 cu_info->number = active_cu_number; 10169 cu_info->ao_cu_mask = ao_cu_mask; 10170 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 10171 10172 return 0; 10173 } 10174 10175 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 10176 { 10177 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 10178 10179 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 10180 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10181 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10182 10183 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 10184 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10185 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10186 10187 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 10188 adev->gfx.config.max_shader_engines); 10189 disabled_sa = efuse_setting | vbios_setting; 10190 disabled_sa &= max_sa_mask; 10191 10192 return disabled_sa; 10193 } 10194 10195 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 10196 { 10197 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 10198 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 10199 10200 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 10201 10202 max_sa_per_se = adev->gfx.config.max_sh_per_se; 10203 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 10204 max_shader_engines = adev->gfx.config.max_shader_engines; 10205 10206 for (se_index = 0; max_shader_engines > se_index; se_index++) { 10207 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 10208 disabled_sa_per_se &= max_sa_per_se_mask; 10209 if (disabled_sa_per_se == max_sa_per_se_mask) { 10210 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 10211 break; 10212 } 10213 } 10214 } 10215 10216 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 10217 { 10218 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 10219 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 10220 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 10221 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 10222 10223 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 10224 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 10225 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 10226 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 10227 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 10228 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 10229 10230 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 10231 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 10232 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 10233 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 10234 10235 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 10236 10237 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 10238 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 10239 } 10240 10241 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 10242 .type = AMD_IP_BLOCK_TYPE_GFX, 10243 .major = 10, 10244 .minor = 0, 10245 .rev = 0, 10246 .funcs = &gfx_v10_0_ip_funcs, 10247 }; 10248