1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 377 /* SE status registers */ 378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 382 }; 383 384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 385 /* compute registers */ 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) 425 }; 426 427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 428 /* gfx queue registers */ 429 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI) 452 }; 453 454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 495 }; 496 497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 498 /* Pending on emulation bring up */ 499 }; 500 501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1554 }; 1555 1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1595 }; 1596 1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1640 }; 1641 1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1643 /* Pending on emulation bring up */ 1644 }; 1645 1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2267 }; 2268 2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2270 /* Pending on emulation bring up */ 2271 }; 2272 2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3326 }; 3327 3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3372 }; 3373 3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3375 /* Pending on emulation bring up */ 3376 }; 3377 3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3420 3421 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3423 }; 3424 3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3450 3451 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3453 }; 3454 3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3476 }; 3477 3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3515 }; 3516 3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3550 }; 3551 3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3587 }; 3588 3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3612 }; 3613 3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3637 }; 3638 3639 #define DEFAULT_SH_MEM_CONFIG \ 3640 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3641 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3642 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3643 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3644 3645 /* TODO: pending on golden setting value of gb address config */ 3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3647 3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3654 struct amdgpu_cu_info *cu_info); 3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3657 u32 sh_num, u32 instance, int xcc_id); 3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3659 3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3671 uint16_t pasid, uint32_t flush_type, 3672 bool all_hub, uint8_t dst_sel); 3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3674 unsigned int vmid); 3675 3676 static int gfx_v10_0_set_powergating_state(void *handle, 3677 enum amd_powergating_state state); 3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3679 { 3680 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3681 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3682 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3683 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3684 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3685 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3686 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3687 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3688 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3689 } 3690 3691 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3692 struct amdgpu_ring *ring) 3693 { 3694 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3695 uint64_t wptr_addr = ring->wptr_gpu_addr; 3696 uint32_t eng_sel = 0; 3697 3698 switch (ring->funcs->type) { 3699 case AMDGPU_RING_TYPE_COMPUTE: 3700 eng_sel = 0; 3701 break; 3702 case AMDGPU_RING_TYPE_GFX: 3703 eng_sel = 4; 3704 break; 3705 case AMDGPU_RING_TYPE_MES: 3706 eng_sel = 5; 3707 break; 3708 default: 3709 WARN_ON(1); 3710 } 3711 3712 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3713 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3714 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3715 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3716 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3717 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3718 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3719 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3720 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3721 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3722 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3723 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3724 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3725 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3726 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3727 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3728 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3729 } 3730 3731 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3732 struct amdgpu_ring *ring, 3733 enum amdgpu_unmap_queues_action action, 3734 u64 gpu_addr, u64 seq) 3735 { 3736 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3737 3738 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3739 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3740 PACKET3_UNMAP_QUEUES_ACTION(action) | 3741 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3742 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3743 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3744 amdgpu_ring_write(kiq_ring, 3745 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3746 3747 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3748 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3749 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3750 amdgpu_ring_write(kiq_ring, seq); 3751 } else { 3752 amdgpu_ring_write(kiq_ring, 0); 3753 amdgpu_ring_write(kiq_ring, 0); 3754 amdgpu_ring_write(kiq_ring, 0); 3755 } 3756 } 3757 3758 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3759 struct amdgpu_ring *ring, 3760 u64 addr, 3761 u64 seq) 3762 { 3763 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3764 3765 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3766 amdgpu_ring_write(kiq_ring, 3767 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3768 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3769 PACKET3_QUERY_STATUS_COMMAND(2)); 3770 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3771 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3772 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3773 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3774 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3775 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3776 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3777 } 3778 3779 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3780 uint16_t pasid, uint32_t flush_type, 3781 bool all_hub) 3782 { 3783 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3784 } 3785 3786 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3787 .kiq_set_resources = gfx10_kiq_set_resources, 3788 .kiq_map_queues = gfx10_kiq_map_queues, 3789 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3790 .kiq_query_status = gfx10_kiq_query_status, 3791 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3792 .set_resources_size = 8, 3793 .map_queues_size = 7, 3794 .unmap_queues_size = 6, 3795 .query_status_size = 7, 3796 .invalidate_tlbs_size = 2, 3797 }; 3798 3799 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3800 { 3801 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3802 } 3803 3804 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3805 { 3806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3807 case IP_VERSION(10, 1, 10): 3808 soc15_program_register_sequence(adev, 3809 golden_settings_gc_rlc_spm_10_0_nv10, 3810 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3811 break; 3812 case IP_VERSION(10, 1, 1): 3813 soc15_program_register_sequence(adev, 3814 golden_settings_gc_rlc_spm_10_1_nv14, 3815 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3816 break; 3817 case IP_VERSION(10, 1, 2): 3818 soc15_program_register_sequence(adev, 3819 golden_settings_gc_rlc_spm_10_1_2_nv12, 3820 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3821 break; 3822 default: 3823 break; 3824 } 3825 } 3826 3827 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3828 { 3829 if (amdgpu_sriov_vf(adev)) 3830 return; 3831 3832 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3833 case IP_VERSION(10, 1, 10): 3834 soc15_program_register_sequence(adev, 3835 golden_settings_gc_10_1, 3836 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3837 soc15_program_register_sequence(adev, 3838 golden_settings_gc_10_0_nv10, 3839 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3840 break; 3841 case IP_VERSION(10, 1, 1): 3842 soc15_program_register_sequence(adev, 3843 golden_settings_gc_10_1_1, 3844 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3845 soc15_program_register_sequence(adev, 3846 golden_settings_gc_10_1_nv14, 3847 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3848 break; 3849 case IP_VERSION(10, 1, 2): 3850 soc15_program_register_sequence(adev, 3851 golden_settings_gc_10_1_2, 3852 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3853 soc15_program_register_sequence(adev, 3854 golden_settings_gc_10_1_2_nv12, 3855 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3856 break; 3857 case IP_VERSION(10, 3, 0): 3858 soc15_program_register_sequence(adev, 3859 golden_settings_gc_10_3, 3860 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3861 soc15_program_register_sequence(adev, 3862 golden_settings_gc_10_3_sienna_cichlid, 3863 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3864 break; 3865 case IP_VERSION(10, 3, 2): 3866 soc15_program_register_sequence(adev, 3867 golden_settings_gc_10_3_2, 3868 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3869 break; 3870 case IP_VERSION(10, 3, 1): 3871 soc15_program_register_sequence(adev, 3872 golden_settings_gc_10_3_vangogh, 3873 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3874 break; 3875 case IP_VERSION(10, 3, 3): 3876 soc15_program_register_sequence(adev, 3877 golden_settings_gc_10_3_3, 3878 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3879 break; 3880 case IP_VERSION(10, 3, 4): 3881 soc15_program_register_sequence(adev, 3882 golden_settings_gc_10_3_4, 3883 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3884 break; 3885 case IP_VERSION(10, 3, 5): 3886 soc15_program_register_sequence(adev, 3887 golden_settings_gc_10_3_5, 3888 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3889 break; 3890 case IP_VERSION(10, 1, 3): 3891 case IP_VERSION(10, 1, 4): 3892 soc15_program_register_sequence(adev, 3893 golden_settings_gc_10_0_cyan_skillfish, 3894 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3895 break; 3896 case IP_VERSION(10, 3, 6): 3897 soc15_program_register_sequence(adev, 3898 golden_settings_gc_10_3_6, 3899 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3900 break; 3901 case IP_VERSION(10, 3, 7): 3902 soc15_program_register_sequence(adev, 3903 golden_settings_gc_10_3_7, 3904 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3905 break; 3906 default: 3907 break; 3908 } 3909 gfx_v10_0_init_spm_golden_registers(adev); 3910 } 3911 3912 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3913 bool wc, uint32_t reg, uint32_t val) 3914 { 3915 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3916 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3917 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3918 amdgpu_ring_write(ring, reg); 3919 amdgpu_ring_write(ring, 0); 3920 amdgpu_ring_write(ring, val); 3921 } 3922 3923 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3924 int mem_space, int opt, uint32_t addr0, 3925 uint32_t addr1, uint32_t ref, uint32_t mask, 3926 uint32_t inv) 3927 { 3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3929 amdgpu_ring_write(ring, 3930 /* memory (1) or register (0) */ 3931 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3932 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3933 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3934 WAIT_REG_MEM_ENGINE(eng_sel))); 3935 3936 if (mem_space) 3937 BUG_ON(addr0 & 0x3); /* Dword align */ 3938 amdgpu_ring_write(ring, addr0); 3939 amdgpu_ring_write(ring, addr1); 3940 amdgpu_ring_write(ring, ref); 3941 amdgpu_ring_write(ring, mask); 3942 amdgpu_ring_write(ring, inv); /* poll interval */ 3943 } 3944 3945 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3946 { 3947 struct amdgpu_device *adev = ring->adev; 3948 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3949 uint32_t tmp = 0; 3950 unsigned int i; 3951 int r; 3952 3953 WREG32(scratch, 0xCAFEDEAD); 3954 r = amdgpu_ring_alloc(ring, 3); 3955 if (r) { 3956 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3957 ring->idx, r); 3958 return r; 3959 } 3960 3961 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3962 amdgpu_ring_write(ring, scratch - 3963 PACKET3_SET_UCONFIG_REG_START); 3964 amdgpu_ring_write(ring, 0xDEADBEEF); 3965 amdgpu_ring_commit(ring); 3966 3967 for (i = 0; i < adev->usec_timeout; i++) { 3968 tmp = RREG32(scratch); 3969 if (tmp == 0xDEADBEEF) 3970 break; 3971 if (amdgpu_emu_mode == 1) 3972 msleep(1); 3973 else 3974 udelay(1); 3975 } 3976 3977 if (i >= adev->usec_timeout) 3978 r = -ETIMEDOUT; 3979 3980 return r; 3981 } 3982 3983 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3984 { 3985 struct amdgpu_device *adev = ring->adev; 3986 struct amdgpu_ib ib; 3987 struct dma_fence *f = NULL; 3988 unsigned int index; 3989 uint64_t gpu_addr; 3990 volatile uint32_t *cpu_ptr; 3991 long r; 3992 3993 memset(&ib, 0, sizeof(ib)); 3994 3995 r = amdgpu_device_wb_get(adev, &index); 3996 if (r) 3997 return r; 3998 3999 gpu_addr = adev->wb.gpu_addr + (index * 4); 4000 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4001 cpu_ptr = &adev->wb.wb[index]; 4002 4003 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4004 if (r) { 4005 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 4006 goto err1; 4007 } 4008 4009 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4010 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4011 ib.ptr[2] = lower_32_bits(gpu_addr); 4012 ib.ptr[3] = upper_32_bits(gpu_addr); 4013 ib.ptr[4] = 0xDEADBEEF; 4014 ib.length_dw = 5; 4015 4016 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4017 if (r) 4018 goto err2; 4019 4020 r = dma_fence_wait_timeout(f, false, timeout); 4021 if (r == 0) { 4022 r = -ETIMEDOUT; 4023 goto err2; 4024 } else if (r < 0) { 4025 goto err2; 4026 } 4027 4028 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4029 r = 0; 4030 else 4031 r = -EINVAL; 4032 err2: 4033 amdgpu_ib_free(adev, &ib, NULL); 4034 dma_fence_put(f); 4035 err1: 4036 amdgpu_device_wb_free(adev, index); 4037 return r; 4038 } 4039 4040 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4041 { 4042 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4043 amdgpu_ucode_release(&adev->gfx.me_fw); 4044 amdgpu_ucode_release(&adev->gfx.ce_fw); 4045 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4046 amdgpu_ucode_release(&adev->gfx.mec_fw); 4047 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4048 4049 kfree(adev->gfx.rlc.register_list_format); 4050 } 4051 4052 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4053 { 4054 adev->gfx.cp_fw_write_wait = false; 4055 4056 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4057 case IP_VERSION(10, 1, 10): 4058 case IP_VERSION(10, 1, 2): 4059 case IP_VERSION(10, 1, 1): 4060 case IP_VERSION(10, 1, 3): 4061 case IP_VERSION(10, 1, 4): 4062 if ((adev->gfx.me_fw_version >= 0x00000046) && 4063 (adev->gfx.me_feature_version >= 27) && 4064 (adev->gfx.pfp_fw_version >= 0x00000068) && 4065 (adev->gfx.pfp_feature_version >= 27) && 4066 (adev->gfx.mec_fw_version >= 0x0000005b) && 4067 (adev->gfx.mec_feature_version >= 27)) 4068 adev->gfx.cp_fw_write_wait = true; 4069 break; 4070 case IP_VERSION(10, 3, 0): 4071 case IP_VERSION(10, 3, 2): 4072 case IP_VERSION(10, 3, 1): 4073 case IP_VERSION(10, 3, 4): 4074 case IP_VERSION(10, 3, 5): 4075 case IP_VERSION(10, 3, 6): 4076 case IP_VERSION(10, 3, 3): 4077 case IP_VERSION(10, 3, 7): 4078 adev->gfx.cp_fw_write_wait = true; 4079 break; 4080 default: 4081 break; 4082 } 4083 4084 if (!adev->gfx.cp_fw_write_wait) 4085 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4086 } 4087 4088 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4089 { 4090 bool ret = false; 4091 4092 switch (adev->pdev->revision) { 4093 case 0xc2: 4094 case 0xc3: 4095 ret = true; 4096 break; 4097 default: 4098 ret = false; 4099 break; 4100 } 4101 4102 return ret; 4103 } 4104 4105 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4106 { 4107 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4108 case IP_VERSION(10, 1, 10): 4109 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4110 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4111 break; 4112 default: 4113 break; 4114 } 4115 } 4116 4117 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4118 { 4119 char ucode_prefix[30]; 4120 const char *wks = ""; 4121 int err; 4122 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4123 uint16_t version_major; 4124 uint16_t version_minor; 4125 4126 DRM_DEBUG("\n"); 4127 4128 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4129 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4130 wks = "_wks"; 4131 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4132 4133 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4134 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4135 if (err) 4136 goto out; 4137 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4138 4139 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4140 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4141 if (err) 4142 goto out; 4143 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4144 4145 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4146 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4147 if (err) 4148 goto out; 4149 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4150 4151 if (!amdgpu_sriov_vf(adev)) { 4152 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 4153 "amdgpu/%s_rlc.bin", ucode_prefix); 4154 if (err) 4155 goto out; 4156 4157 /* don't validate this firmware. There are apparently firmwares 4158 * in the wild with incorrect size in the header 4159 */ 4160 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4161 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4162 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4163 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4164 if (err) 4165 goto out; 4166 } 4167 4168 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4169 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4170 if (err) 4171 goto out; 4172 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4173 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4174 4175 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4176 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4177 if (!err) { 4178 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4179 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4180 } else { 4181 err = 0; 4182 adev->gfx.mec2_fw = NULL; 4183 } 4184 4185 gfx_v10_0_check_fw_write_wait(adev); 4186 out: 4187 if (err) { 4188 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4189 amdgpu_ucode_release(&adev->gfx.me_fw); 4190 amdgpu_ucode_release(&adev->gfx.ce_fw); 4191 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4192 amdgpu_ucode_release(&adev->gfx.mec_fw); 4193 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4194 } 4195 4196 gfx_v10_0_check_gfxoff_flag(adev); 4197 4198 return err; 4199 } 4200 4201 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4202 { 4203 u32 count = 0; 4204 const struct cs_section_def *sect = NULL; 4205 const struct cs_extent_def *ext = NULL; 4206 4207 /* begin clear state */ 4208 count += 2; 4209 /* context control state */ 4210 count += 3; 4211 4212 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4213 for (ext = sect->section; ext->extent != NULL; ++ext) { 4214 if (sect->id == SECT_CONTEXT) 4215 count += 2 + ext->reg_count; 4216 else 4217 return 0; 4218 } 4219 } 4220 4221 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4222 count += 3; 4223 /* end clear state */ 4224 count += 2; 4225 /* clear state */ 4226 count += 2; 4227 4228 return count; 4229 } 4230 4231 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4232 volatile u32 *buffer) 4233 { 4234 u32 count = 0, i; 4235 const struct cs_section_def *sect = NULL; 4236 const struct cs_extent_def *ext = NULL; 4237 int ctx_reg_offset; 4238 4239 if (adev->gfx.rlc.cs_data == NULL) 4240 return; 4241 if (buffer == NULL) 4242 return; 4243 4244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4245 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4246 4247 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4248 buffer[count++] = cpu_to_le32(0x80000000); 4249 buffer[count++] = cpu_to_le32(0x80000000); 4250 4251 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4252 for (ext = sect->section; ext->extent != NULL; ++ext) { 4253 if (sect->id == SECT_CONTEXT) { 4254 buffer[count++] = 4255 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4256 buffer[count++] = cpu_to_le32(ext->reg_index - 4257 PACKET3_SET_CONTEXT_REG_START); 4258 for (i = 0; i < ext->reg_count; i++) 4259 buffer[count++] = cpu_to_le32(ext->extent[i]); 4260 } else { 4261 return; 4262 } 4263 } 4264 } 4265 4266 ctx_reg_offset = 4267 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4268 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4269 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4270 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4271 4272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4273 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4274 4275 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4276 buffer[count++] = cpu_to_le32(0); 4277 } 4278 4279 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4280 { 4281 /* clear state block */ 4282 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4283 &adev->gfx.rlc.clear_state_gpu_addr, 4284 (void **)&adev->gfx.rlc.cs_ptr); 4285 4286 /* jump table block */ 4287 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4288 &adev->gfx.rlc.cp_table_gpu_addr, 4289 (void **)&adev->gfx.rlc.cp_table_ptr); 4290 } 4291 4292 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4293 { 4294 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4295 4296 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4297 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4298 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4299 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4300 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4301 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4302 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4303 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4304 case IP_VERSION(10, 3, 0): 4305 reg_access_ctrl->spare_int = 4306 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4307 break; 4308 default: 4309 reg_access_ctrl->spare_int = 4310 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4311 break; 4312 } 4313 adev->gfx.rlc.rlcg_reg_access_supported = true; 4314 } 4315 4316 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4317 { 4318 const struct cs_section_def *cs_data; 4319 int r; 4320 4321 adev->gfx.rlc.cs_data = gfx10_cs_data; 4322 4323 cs_data = adev->gfx.rlc.cs_data; 4324 4325 if (cs_data) { 4326 /* init clear state block */ 4327 r = amdgpu_gfx_rlc_init_csb(adev); 4328 if (r) 4329 return r; 4330 } 4331 4332 return 0; 4333 } 4334 4335 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4336 { 4337 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4338 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4339 } 4340 4341 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4342 { 4343 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4344 4345 amdgpu_gfx_graphics_queue_acquire(adev); 4346 } 4347 4348 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4349 { 4350 int r; 4351 u32 *hpd; 4352 const __le32 *fw_data = NULL; 4353 unsigned int fw_size; 4354 u32 *fw = NULL; 4355 size_t mec_hpd_size; 4356 4357 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4358 4359 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4360 4361 /* take ownership of the relevant compute queues */ 4362 amdgpu_gfx_compute_queue_acquire(adev); 4363 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4364 4365 if (mec_hpd_size) { 4366 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4367 AMDGPU_GEM_DOMAIN_GTT, 4368 &adev->gfx.mec.hpd_eop_obj, 4369 &adev->gfx.mec.hpd_eop_gpu_addr, 4370 (void **)&hpd); 4371 if (r) { 4372 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4373 gfx_v10_0_mec_fini(adev); 4374 return r; 4375 } 4376 4377 memset(hpd, 0, mec_hpd_size); 4378 4379 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4380 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4381 } 4382 4383 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4384 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4385 4386 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4387 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4388 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4389 4390 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4391 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4392 &adev->gfx.mec.mec_fw_obj, 4393 &adev->gfx.mec.mec_fw_gpu_addr, 4394 (void **)&fw); 4395 if (r) { 4396 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4397 gfx_v10_0_mec_fini(adev); 4398 return r; 4399 } 4400 4401 memcpy(fw, fw_data, fw_size); 4402 4403 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4404 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4405 } 4406 4407 return 0; 4408 } 4409 4410 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4411 { 4412 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4413 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4414 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4415 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4416 } 4417 4418 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4419 uint32_t thread, uint32_t regno, 4420 uint32_t num, uint32_t *out) 4421 { 4422 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4423 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4424 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4425 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4426 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4427 while (num--) 4428 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4429 } 4430 4431 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4432 { 4433 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4434 * field when performing a select_se_sh so it should be 4435 * zero here 4436 */ 4437 WARN_ON(simd != 0); 4438 4439 /* type 2 wave data */ 4440 dst[(*no_fields)++] = 2; 4441 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4442 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4443 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4444 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4445 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4446 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4447 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4448 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4449 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4450 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4451 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4452 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4453 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4454 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4455 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4457 } 4458 4459 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4460 uint32_t wave, uint32_t start, 4461 uint32_t size, uint32_t *dst) 4462 { 4463 WARN_ON(simd != 0); 4464 4465 wave_read_regs( 4466 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4467 dst); 4468 } 4469 4470 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4471 uint32_t wave, uint32_t thread, 4472 uint32_t start, uint32_t size, 4473 uint32_t *dst) 4474 { 4475 wave_read_regs( 4476 adev, wave, thread, 4477 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4478 } 4479 4480 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4481 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4482 { 4483 nv_grbm_select(adev, me, pipe, q, vm); 4484 } 4485 4486 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4487 bool enable) 4488 { 4489 uint32_t data, def; 4490 4491 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4492 4493 if (enable) 4494 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4495 else 4496 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4497 4498 if (data != def) 4499 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4500 } 4501 4502 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4503 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4504 .select_se_sh = &gfx_v10_0_select_se_sh, 4505 .read_wave_data = &gfx_v10_0_read_wave_data, 4506 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4507 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4508 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4509 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4510 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4511 }; 4512 4513 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4514 { 4515 u32 gb_addr_config; 4516 4517 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4518 case IP_VERSION(10, 1, 10): 4519 case IP_VERSION(10, 1, 1): 4520 case IP_VERSION(10, 1, 2): 4521 adev->gfx.config.max_hw_contexts = 8; 4522 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4523 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4524 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4525 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4526 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4527 break; 4528 case IP_VERSION(10, 3, 0): 4529 case IP_VERSION(10, 3, 2): 4530 case IP_VERSION(10, 3, 1): 4531 case IP_VERSION(10, 3, 4): 4532 case IP_VERSION(10, 3, 5): 4533 case IP_VERSION(10, 3, 6): 4534 case IP_VERSION(10, 3, 3): 4535 case IP_VERSION(10, 3, 7): 4536 adev->gfx.config.max_hw_contexts = 8; 4537 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4538 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4539 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4540 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4541 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4542 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4543 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4544 break; 4545 case IP_VERSION(10, 1, 3): 4546 case IP_VERSION(10, 1, 4): 4547 adev->gfx.config.max_hw_contexts = 8; 4548 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4549 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4550 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4551 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4552 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4553 break; 4554 default: 4555 BUG(); 4556 break; 4557 } 4558 4559 adev->gfx.config.gb_addr_config = gb_addr_config; 4560 4561 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4562 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4563 GB_ADDR_CONFIG, NUM_PIPES); 4564 4565 adev->gfx.config.max_tile_pipes = 4566 adev->gfx.config.gb_addr_config_fields.num_pipes; 4567 4568 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4569 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4570 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4571 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4572 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4573 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4574 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4575 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4576 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4577 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4578 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4579 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4580 } 4581 4582 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4583 int me, int pipe, int queue) 4584 { 4585 struct amdgpu_ring *ring; 4586 unsigned int irq_type; 4587 unsigned int hw_prio; 4588 4589 ring = &adev->gfx.gfx_ring[ring_id]; 4590 4591 ring->me = me; 4592 ring->pipe = pipe; 4593 ring->queue = queue; 4594 4595 ring->ring_obj = NULL; 4596 ring->use_doorbell = true; 4597 4598 if (!ring_id) 4599 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4600 else 4601 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4602 ring->vm_hub = AMDGPU_GFXHUB(0); 4603 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4604 4605 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4606 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4607 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4608 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4609 hw_prio, NULL); 4610 } 4611 4612 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4613 int mec, int pipe, int queue) 4614 { 4615 unsigned int irq_type; 4616 struct amdgpu_ring *ring; 4617 unsigned int hw_prio; 4618 4619 ring = &adev->gfx.compute_ring[ring_id]; 4620 4621 /* mec0 is me1 */ 4622 ring->me = mec + 1; 4623 ring->pipe = pipe; 4624 ring->queue = queue; 4625 4626 ring->ring_obj = NULL; 4627 ring->use_doorbell = true; 4628 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4629 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4630 + (ring_id * GFX10_MEC_HPD_SIZE); 4631 ring->vm_hub = AMDGPU_GFXHUB(0); 4632 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4633 4634 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4635 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4636 + ring->pipe; 4637 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4638 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4639 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4640 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4641 hw_prio, NULL); 4642 } 4643 4644 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4645 { 4646 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4647 uint32_t *ptr; 4648 uint32_t inst; 4649 4650 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4651 if (ptr == NULL) { 4652 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4653 adev->gfx.ip_dump_core = NULL; 4654 } else { 4655 adev->gfx.ip_dump_core = ptr; 4656 } 4657 4658 /* Allocate memory for compute queue registers for all the instances */ 4659 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4660 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4661 adev->gfx.mec.num_queue_per_pipe; 4662 4663 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4664 if (ptr == NULL) { 4665 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4666 adev->gfx.ip_dump_compute_queues = NULL; 4667 } else { 4668 adev->gfx.ip_dump_compute_queues = ptr; 4669 } 4670 4671 /* Allocate memory for gfx queue registers for all the instances */ 4672 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4673 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4674 adev->gfx.me.num_queue_per_pipe; 4675 4676 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4677 if (ptr == NULL) { 4678 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4679 adev->gfx.ip_dump_gfx_queues = NULL; 4680 } else { 4681 adev->gfx.ip_dump_gfx_queues = ptr; 4682 } 4683 } 4684 4685 static int gfx_v10_0_sw_init(void *handle) 4686 { 4687 int i, j, k, r, ring_id = 0; 4688 int xcc_id = 0; 4689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4690 4691 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4692 case IP_VERSION(10, 1, 10): 4693 case IP_VERSION(10, 1, 1): 4694 case IP_VERSION(10, 1, 2): 4695 case IP_VERSION(10, 1, 3): 4696 case IP_VERSION(10, 1, 4): 4697 adev->gfx.me.num_me = 1; 4698 adev->gfx.me.num_pipe_per_me = 1; 4699 adev->gfx.me.num_queue_per_pipe = 1; 4700 adev->gfx.mec.num_mec = 2; 4701 adev->gfx.mec.num_pipe_per_mec = 4; 4702 adev->gfx.mec.num_queue_per_pipe = 8; 4703 break; 4704 case IP_VERSION(10, 3, 0): 4705 case IP_VERSION(10, 3, 2): 4706 case IP_VERSION(10, 3, 1): 4707 case IP_VERSION(10, 3, 4): 4708 case IP_VERSION(10, 3, 5): 4709 case IP_VERSION(10, 3, 6): 4710 case IP_VERSION(10, 3, 3): 4711 case IP_VERSION(10, 3, 7): 4712 adev->gfx.me.num_me = 1; 4713 adev->gfx.me.num_pipe_per_me = 2; 4714 adev->gfx.me.num_queue_per_pipe = 1; 4715 adev->gfx.mec.num_mec = 2; 4716 adev->gfx.mec.num_pipe_per_mec = 4; 4717 adev->gfx.mec.num_queue_per_pipe = 4; 4718 break; 4719 default: 4720 adev->gfx.me.num_me = 1; 4721 adev->gfx.me.num_pipe_per_me = 1; 4722 adev->gfx.me.num_queue_per_pipe = 1; 4723 adev->gfx.mec.num_mec = 1; 4724 adev->gfx.mec.num_pipe_per_mec = 4; 4725 adev->gfx.mec.num_queue_per_pipe = 8; 4726 break; 4727 } 4728 4729 /* KIQ event */ 4730 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4731 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4732 &adev->gfx.kiq[0].irq); 4733 if (r) 4734 return r; 4735 4736 /* EOP Event */ 4737 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4738 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4739 &adev->gfx.eop_irq); 4740 if (r) 4741 return r; 4742 4743 /* Privileged reg */ 4744 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4745 &adev->gfx.priv_reg_irq); 4746 if (r) 4747 return r; 4748 4749 /* Privileged inst */ 4750 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4751 &adev->gfx.priv_inst_irq); 4752 if (r) 4753 return r; 4754 4755 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4756 4757 gfx_v10_0_me_init(adev); 4758 4759 if (adev->gfx.rlc.funcs) { 4760 if (adev->gfx.rlc.funcs->init) { 4761 r = adev->gfx.rlc.funcs->init(adev); 4762 if (r) { 4763 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4764 return r; 4765 } 4766 } 4767 } 4768 4769 r = gfx_v10_0_mec_init(adev); 4770 if (r) { 4771 DRM_ERROR("Failed to init MEC BOs!\n"); 4772 return r; 4773 } 4774 4775 /* set up the gfx ring */ 4776 for (i = 0; i < adev->gfx.me.num_me; i++) { 4777 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4778 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4779 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4780 continue; 4781 4782 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4783 i, k, j); 4784 if (r) 4785 return r; 4786 ring_id++; 4787 } 4788 } 4789 } 4790 4791 ring_id = 0; 4792 /* set up the compute queues - allocate horizontally across pipes */ 4793 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4794 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4795 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4796 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4797 k, j)) 4798 continue; 4799 4800 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4801 i, k, j); 4802 if (r) 4803 return r; 4804 4805 ring_id++; 4806 } 4807 } 4808 } 4809 4810 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4811 if (r) { 4812 DRM_ERROR("Failed to init KIQ BOs!\n"); 4813 return r; 4814 } 4815 4816 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4817 if (r) 4818 return r; 4819 4820 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4821 if (r) 4822 return r; 4823 4824 /* allocate visible FB for rlc auto-loading fw */ 4825 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4826 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4827 if (r) 4828 return r; 4829 } 4830 4831 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4832 4833 gfx_v10_0_gpu_early_init(adev); 4834 4835 gfx_v10_0_alloc_ip_dump(adev); 4836 4837 return 0; 4838 } 4839 4840 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4841 { 4842 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4843 &adev->gfx.pfp.pfp_fw_gpu_addr, 4844 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4845 } 4846 4847 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4848 { 4849 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4850 &adev->gfx.ce.ce_fw_gpu_addr, 4851 (void **)&adev->gfx.ce.ce_fw_ptr); 4852 } 4853 4854 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4855 { 4856 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4857 &adev->gfx.me.me_fw_gpu_addr, 4858 (void **)&adev->gfx.me.me_fw_ptr); 4859 } 4860 4861 static int gfx_v10_0_sw_fini(void *handle) 4862 { 4863 int i; 4864 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4865 4866 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4867 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4868 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4869 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4870 4871 amdgpu_gfx_mqd_sw_fini(adev, 0); 4872 4873 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4874 amdgpu_gfx_kiq_fini(adev, 0); 4875 4876 gfx_v10_0_pfp_fini(adev); 4877 gfx_v10_0_ce_fini(adev); 4878 gfx_v10_0_me_fini(adev); 4879 gfx_v10_0_rlc_fini(adev); 4880 gfx_v10_0_mec_fini(adev); 4881 4882 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4883 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4884 4885 gfx_v10_0_free_microcode(adev); 4886 4887 kfree(adev->gfx.ip_dump_core); 4888 kfree(adev->gfx.ip_dump_compute_queues); 4889 kfree(adev->gfx.ip_dump_gfx_queues); 4890 4891 return 0; 4892 } 4893 4894 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4895 u32 sh_num, u32 instance, int xcc_id) 4896 { 4897 u32 data; 4898 4899 if (instance == 0xffffffff) 4900 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4901 INSTANCE_BROADCAST_WRITES, 1); 4902 else 4903 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4904 instance); 4905 4906 if (se_num == 0xffffffff) 4907 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4908 1); 4909 else 4910 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4911 4912 if (sh_num == 0xffffffff) 4913 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4914 1); 4915 else 4916 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4917 4918 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4919 } 4920 4921 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4922 { 4923 u32 data, mask; 4924 4925 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4926 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4927 4928 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4929 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4930 4931 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4932 adev->gfx.config.max_sh_per_se); 4933 4934 return (~data) & mask; 4935 } 4936 4937 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4938 { 4939 int i, j; 4940 u32 data; 4941 u32 active_rbs = 0; 4942 u32 bitmap; 4943 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4944 adev->gfx.config.max_sh_per_se; 4945 4946 mutex_lock(&adev->grbm_idx_mutex); 4947 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4948 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4949 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4950 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4951 IP_VERSION(10, 3, 0)) || 4952 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4953 IP_VERSION(10, 3, 3)) || 4954 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4955 IP_VERSION(10, 3, 6))) && 4956 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4957 continue; 4958 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4959 data = gfx_v10_0_get_rb_active_bitmap(adev); 4960 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4961 rb_bitmap_width_per_sh); 4962 } 4963 } 4964 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4965 mutex_unlock(&adev->grbm_idx_mutex); 4966 4967 adev->gfx.config.backend_enable_mask = active_rbs; 4968 adev->gfx.config.num_rbs = hweight32(active_rbs); 4969 } 4970 4971 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4972 { 4973 uint32_t num_sc; 4974 uint32_t enabled_rb_per_sh; 4975 uint32_t active_rb_bitmap; 4976 uint32_t num_rb_per_sc; 4977 uint32_t num_packer_per_sc; 4978 uint32_t pa_sc_tile_steering_override; 4979 4980 /* for ASICs that integrates GFX v10.3 4981 * pa_sc_tile_steering_override should be set to 0 4982 */ 4983 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 4984 return 0; 4985 4986 /* init num_sc */ 4987 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4988 adev->gfx.config.num_sc_per_sh; 4989 /* init num_rb_per_sc */ 4990 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4991 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4992 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4993 /* init num_packer_per_sc */ 4994 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4995 4996 pa_sc_tile_steering_override = 0; 4997 pa_sc_tile_steering_override |= 4998 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4999 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5000 pa_sc_tile_steering_override |= 5001 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5002 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5003 pa_sc_tile_steering_override |= 5004 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5005 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5006 5007 return pa_sc_tile_steering_override; 5008 } 5009 5010 #define DEFAULT_SH_MEM_BASES (0x6000) 5011 5012 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5013 uint32_t first_vmid, 5014 uint32_t last_vmid) 5015 { 5016 uint32_t data; 5017 uint32_t trap_config_vmid_mask = 0; 5018 int i; 5019 5020 /* Calculate trap config vmid mask */ 5021 for (i = first_vmid; i < last_vmid; i++) 5022 trap_config_vmid_mask |= (1 << i); 5023 5024 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5025 VMID_SEL, trap_config_vmid_mask); 5026 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5027 TRAP_EN, 1); 5028 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5029 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5030 5031 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5032 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5033 } 5034 5035 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5036 { 5037 int i; 5038 uint32_t sh_mem_bases; 5039 5040 /* 5041 * Configure apertures: 5042 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5043 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5044 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5045 */ 5046 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5047 5048 mutex_lock(&adev->srbm_mutex); 5049 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5050 nv_grbm_select(adev, 0, 0, 0, i); 5051 /* CP and shaders */ 5052 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5053 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5054 } 5055 nv_grbm_select(adev, 0, 0, 0, 0); 5056 mutex_unlock(&adev->srbm_mutex); 5057 5058 /* 5059 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5060 * access. These should be enabled by FW for target VMIDs. 5061 */ 5062 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5063 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5064 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5065 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5066 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5067 } 5068 5069 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5070 AMDGPU_NUM_VMID); 5071 } 5072 5073 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5074 { 5075 int vmid; 5076 5077 /* 5078 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5079 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5080 * the driver can enable them for graphics. VMID0 should maintain 5081 * access so that HWS firmware can save/restore entries. 5082 */ 5083 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5084 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5085 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5086 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5087 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5088 } 5089 } 5090 5091 5092 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5093 { 5094 int i, j, k; 5095 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5096 u32 tmp, wgp_active_bitmap = 0; 5097 u32 gcrd_targets_disable_tcp = 0; 5098 u32 utcl_invreq_disable = 0; 5099 /* 5100 * GCRD_TARGETS_DISABLE field contains 5101 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5102 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5103 */ 5104 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5105 2 * max_wgp_per_sh + /* TCP */ 5106 max_wgp_per_sh + /* SQC */ 5107 4); /* GL1C */ 5108 /* 5109 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5110 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5111 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5112 */ 5113 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5114 2 * max_wgp_per_sh + /* TCP */ 5115 2 * max_wgp_per_sh + /* SQC */ 5116 4 + /* RMI */ 5117 1); /* SQG */ 5118 5119 mutex_lock(&adev->grbm_idx_mutex); 5120 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5121 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5122 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5123 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5124 /* 5125 * Set corresponding TCP bits for the inactive WGPs in 5126 * GCRD_SA_TARGETS_DISABLE 5127 */ 5128 gcrd_targets_disable_tcp = 0; 5129 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5130 utcl_invreq_disable = 0; 5131 5132 for (k = 0; k < max_wgp_per_sh; k++) { 5133 if (!(wgp_active_bitmap & (1 << k))) { 5134 gcrd_targets_disable_tcp |= 3 << (2 * k); 5135 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5136 utcl_invreq_disable |= (3 << (2 * k)) | 5137 (3 << (2 * (max_wgp_per_sh + k))); 5138 } 5139 } 5140 5141 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5142 /* only override TCP & SQC bits */ 5143 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5144 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5145 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5146 5147 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5148 /* only override TCP & SQC bits */ 5149 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5150 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5151 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5152 } 5153 } 5154 5155 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5156 mutex_unlock(&adev->grbm_idx_mutex); 5157 } 5158 5159 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5160 { 5161 /* TCCs are global (not instanced). */ 5162 uint32_t tcc_disable; 5163 5164 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5165 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5166 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5167 } else { 5168 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5169 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5170 } 5171 5172 adev->gfx.config.tcc_disabled_mask = 5173 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5174 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5175 } 5176 5177 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5178 { 5179 u32 tmp; 5180 int i; 5181 5182 if (!amdgpu_sriov_vf(adev)) 5183 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5184 5185 gfx_v10_0_setup_rb(adev); 5186 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5187 gfx_v10_0_get_tcc_info(adev); 5188 adev->gfx.config.pa_sc_tile_steering_override = 5189 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5190 5191 /* XXX SH_MEM regs */ 5192 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5193 mutex_lock(&adev->srbm_mutex); 5194 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5195 nv_grbm_select(adev, 0, 0, 0, i); 5196 /* CP and shaders */ 5197 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5198 if (i != 0) { 5199 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5200 (adev->gmc.private_aperture_start >> 48)); 5201 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5202 (adev->gmc.shared_aperture_start >> 48)); 5203 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5204 } 5205 } 5206 nv_grbm_select(adev, 0, 0, 0, 0); 5207 5208 mutex_unlock(&adev->srbm_mutex); 5209 5210 gfx_v10_0_init_compute_vmid(adev); 5211 gfx_v10_0_init_gds_vmid(adev); 5212 5213 } 5214 5215 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5216 bool enable) 5217 { 5218 u32 tmp; 5219 5220 if (amdgpu_sriov_vf(adev)) 5221 return; 5222 5223 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5224 5225 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5226 enable ? 1 : 0); 5227 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5228 enable ? 1 : 0); 5229 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5230 enable ? 1 : 0); 5231 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5232 enable ? 1 : 0); 5233 5234 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5235 } 5236 5237 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5238 { 5239 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5240 5241 /* csib */ 5242 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5243 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5244 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5245 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5246 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5247 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5248 } else { 5249 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5250 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5251 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5252 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5253 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5254 } 5255 return 0; 5256 } 5257 5258 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5259 { 5260 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5261 5262 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5263 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5264 } 5265 5266 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5267 { 5268 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5269 udelay(50); 5270 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5271 udelay(50); 5272 } 5273 5274 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5275 bool enable) 5276 { 5277 uint32_t rlc_pg_cntl; 5278 5279 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5280 5281 if (!enable) { 5282 /* RLC_PG_CNTL[23] = 0 (default) 5283 * RLC will wait for handshake acks with SMU 5284 * GFXOFF will be enabled 5285 * RLC_PG_CNTL[23] = 1 5286 * RLC will not issue any message to SMU 5287 * hence no handshake between SMU & RLC 5288 * GFXOFF will be disabled 5289 */ 5290 rlc_pg_cntl |= 0x800000; 5291 } else 5292 rlc_pg_cntl &= ~0x800000; 5293 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5294 } 5295 5296 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5297 { 5298 /* 5299 * TODO: enable rlc & smu handshake until smu 5300 * and gfxoff feature works as expected 5301 */ 5302 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5303 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5304 5305 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5306 udelay(50); 5307 } 5308 5309 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5310 { 5311 uint32_t tmp; 5312 5313 /* enable Save Restore Machine */ 5314 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5315 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5316 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5317 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5318 } 5319 5320 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5321 { 5322 const struct rlc_firmware_header_v2_0 *hdr; 5323 const __le32 *fw_data; 5324 unsigned int i, fw_size; 5325 5326 if (!adev->gfx.rlc_fw) 5327 return -EINVAL; 5328 5329 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5330 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5331 5332 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5333 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5334 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5335 5336 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5337 RLCG_UCODE_LOADING_START_ADDRESS); 5338 5339 for (i = 0; i < fw_size; i++) 5340 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5341 le32_to_cpup(fw_data++)); 5342 5343 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5344 5345 return 0; 5346 } 5347 5348 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5349 { 5350 int r; 5351 5352 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5353 adev->psp.autoload_supported) { 5354 5355 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5356 if (r) 5357 return r; 5358 5359 gfx_v10_0_init_csb(adev); 5360 5361 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5362 5363 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5364 gfx_v10_0_rlc_enable_srm(adev); 5365 } else { 5366 if (amdgpu_sriov_vf(adev)) { 5367 gfx_v10_0_init_csb(adev); 5368 return 0; 5369 } 5370 5371 adev->gfx.rlc.funcs->stop(adev); 5372 5373 /* disable CG */ 5374 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5375 5376 /* disable PG */ 5377 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5378 5379 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5380 /* legacy rlc firmware loading */ 5381 r = gfx_v10_0_rlc_load_microcode(adev); 5382 if (r) 5383 return r; 5384 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5385 /* rlc backdoor autoload firmware */ 5386 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5387 if (r) 5388 return r; 5389 } 5390 5391 gfx_v10_0_init_csb(adev); 5392 5393 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5394 5395 adev->gfx.rlc.funcs->start(adev); 5396 5397 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5398 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5399 if (r) 5400 return r; 5401 } 5402 } 5403 5404 return 0; 5405 } 5406 5407 static struct { 5408 FIRMWARE_ID id; 5409 unsigned int offset; 5410 unsigned int size; 5411 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5412 5413 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5414 { 5415 int ret; 5416 RLC_TABLE_OF_CONTENT *rlc_toc; 5417 5418 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5419 AMDGPU_GEM_DOMAIN_GTT, 5420 &adev->gfx.rlc.rlc_toc_bo, 5421 &adev->gfx.rlc.rlc_toc_gpu_addr, 5422 (void **)&adev->gfx.rlc.rlc_toc_buf); 5423 if (ret) { 5424 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5425 return ret; 5426 } 5427 5428 /* Copy toc from psp sos fw to rlc toc buffer */ 5429 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5430 5431 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5432 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5433 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5434 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5435 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5436 /* Offset needs 4KB alignment */ 5437 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5438 } 5439 5440 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5441 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5442 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5443 5444 rlc_toc++; 5445 } 5446 5447 return 0; 5448 } 5449 5450 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5451 { 5452 uint32_t total_size = 0; 5453 FIRMWARE_ID id; 5454 int ret; 5455 5456 ret = gfx_v10_0_parse_rlc_toc(adev); 5457 if (ret) { 5458 dev_err(adev->dev, "failed to parse rlc toc\n"); 5459 return 0; 5460 } 5461 5462 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5463 total_size += rlc_autoload_info[id].size; 5464 5465 /* In case the offset in rlc toc ucode is aligned */ 5466 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5467 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5468 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5469 5470 return total_size; 5471 } 5472 5473 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5474 { 5475 int r; 5476 uint32_t total_size; 5477 5478 total_size = gfx_v10_0_calc_toc_total_size(adev); 5479 5480 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5481 AMDGPU_GEM_DOMAIN_GTT, 5482 &adev->gfx.rlc.rlc_autoload_bo, 5483 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5484 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5485 if (r) { 5486 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5487 return r; 5488 } 5489 5490 return 0; 5491 } 5492 5493 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5494 { 5495 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5496 &adev->gfx.rlc.rlc_toc_gpu_addr, 5497 (void **)&adev->gfx.rlc.rlc_toc_buf); 5498 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5499 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5500 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5501 } 5502 5503 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5504 FIRMWARE_ID id, 5505 const void *fw_data, 5506 uint32_t fw_size) 5507 { 5508 uint32_t toc_offset; 5509 uint32_t toc_fw_size; 5510 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5511 5512 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5513 return; 5514 5515 toc_offset = rlc_autoload_info[id].offset; 5516 toc_fw_size = rlc_autoload_info[id].size; 5517 5518 if (fw_size == 0) 5519 fw_size = toc_fw_size; 5520 5521 if (fw_size > toc_fw_size) 5522 fw_size = toc_fw_size; 5523 5524 memcpy(ptr + toc_offset, fw_data, fw_size); 5525 5526 if (fw_size < toc_fw_size) 5527 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5528 } 5529 5530 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5531 { 5532 void *data; 5533 uint32_t size; 5534 5535 data = adev->gfx.rlc.rlc_toc_buf; 5536 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5537 5538 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5539 FIRMWARE_ID_RLC_TOC, 5540 data, size); 5541 } 5542 5543 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5544 { 5545 const __le32 *fw_data; 5546 uint32_t fw_size; 5547 const struct gfx_firmware_header_v1_0 *cp_hdr; 5548 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5549 5550 /* pfp ucode */ 5551 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5552 adev->gfx.pfp_fw->data; 5553 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5554 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5555 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5556 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5557 FIRMWARE_ID_CP_PFP, 5558 fw_data, fw_size); 5559 5560 /* ce ucode */ 5561 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5562 adev->gfx.ce_fw->data; 5563 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5564 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5565 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5566 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5567 FIRMWARE_ID_CP_CE, 5568 fw_data, fw_size); 5569 5570 /* me ucode */ 5571 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5572 adev->gfx.me_fw->data; 5573 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5574 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5575 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5576 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5577 FIRMWARE_ID_CP_ME, 5578 fw_data, fw_size); 5579 5580 /* rlc ucode */ 5581 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5582 adev->gfx.rlc_fw->data; 5583 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5584 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5585 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5586 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5587 FIRMWARE_ID_RLC_G_UCODE, 5588 fw_data, fw_size); 5589 5590 /* mec1 ucode */ 5591 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5592 adev->gfx.mec_fw->data; 5593 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5594 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5595 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5596 cp_hdr->jt_size * 4; 5597 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5598 FIRMWARE_ID_CP_MEC, 5599 fw_data, fw_size); 5600 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5601 } 5602 5603 /* Temporarily put sdma part here */ 5604 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5605 { 5606 const __le32 *fw_data; 5607 uint32_t fw_size; 5608 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5609 int i; 5610 5611 for (i = 0; i < adev->sdma.num_instances; i++) { 5612 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5613 adev->sdma.instance[i].fw->data; 5614 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5615 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5616 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5617 5618 if (i == 0) { 5619 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5620 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5621 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5622 FIRMWARE_ID_SDMA0_JT, 5623 (uint32_t *)fw_data + 5624 sdma_hdr->jt_offset, 5625 sdma_hdr->jt_size * 4); 5626 } else if (i == 1) { 5627 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5628 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5629 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5630 FIRMWARE_ID_SDMA1_JT, 5631 (uint32_t *)fw_data + 5632 sdma_hdr->jt_offset, 5633 sdma_hdr->jt_size * 4); 5634 } 5635 } 5636 } 5637 5638 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5639 { 5640 uint32_t rlc_g_offset, rlc_g_size, tmp; 5641 uint64_t gpu_addr; 5642 5643 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5644 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5645 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5646 5647 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5648 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5649 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5650 5651 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5652 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5653 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5654 5655 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5656 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5657 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5658 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5659 return -EINVAL; 5660 } 5661 5662 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5663 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5664 DRM_ERROR("RLC ROM should halt itself\n"); 5665 return -EINVAL; 5666 } 5667 5668 return 0; 5669 } 5670 5671 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5672 { 5673 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5674 uint32_t tmp; 5675 int i; 5676 uint64_t addr; 5677 5678 /* Trigger an invalidation of the L1 instruction caches */ 5679 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5680 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5681 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5682 5683 /* Wait for invalidation complete */ 5684 for (i = 0; i < usec_timeout; i++) { 5685 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5686 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5687 INVALIDATE_CACHE_COMPLETE)) 5688 break; 5689 udelay(1); 5690 } 5691 5692 if (i >= usec_timeout) { 5693 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5694 return -EINVAL; 5695 } 5696 5697 /* Program me ucode address into intruction cache address register */ 5698 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5699 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5700 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5701 lower_32_bits(addr) & 0xFFFFF000); 5702 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5703 upper_32_bits(addr)); 5704 5705 return 0; 5706 } 5707 5708 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5709 { 5710 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5711 uint32_t tmp; 5712 int i; 5713 uint64_t addr; 5714 5715 /* Trigger an invalidation of the L1 instruction caches */ 5716 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5717 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5718 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5719 5720 /* Wait for invalidation complete */ 5721 for (i = 0; i < usec_timeout; i++) { 5722 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5723 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5724 INVALIDATE_CACHE_COMPLETE)) 5725 break; 5726 udelay(1); 5727 } 5728 5729 if (i >= usec_timeout) { 5730 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5731 return -EINVAL; 5732 } 5733 5734 /* Program ce ucode address into intruction cache address register */ 5735 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5736 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5737 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5738 lower_32_bits(addr) & 0xFFFFF000); 5739 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5740 upper_32_bits(addr)); 5741 5742 return 0; 5743 } 5744 5745 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5746 { 5747 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5748 uint32_t tmp; 5749 int i; 5750 uint64_t addr; 5751 5752 /* Trigger an invalidation of the L1 instruction caches */ 5753 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5754 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5755 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5756 5757 /* Wait for invalidation complete */ 5758 for (i = 0; i < usec_timeout; i++) { 5759 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5760 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5761 INVALIDATE_CACHE_COMPLETE)) 5762 break; 5763 udelay(1); 5764 } 5765 5766 if (i >= usec_timeout) { 5767 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5768 return -EINVAL; 5769 } 5770 5771 /* Program pfp ucode address into intruction cache address register */ 5772 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5773 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5774 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5775 lower_32_bits(addr) & 0xFFFFF000); 5776 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5777 upper_32_bits(addr)); 5778 5779 return 0; 5780 } 5781 5782 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5783 { 5784 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5785 uint32_t tmp; 5786 int i; 5787 uint64_t addr; 5788 5789 /* Trigger an invalidation of the L1 instruction caches */ 5790 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5791 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5792 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5793 5794 /* Wait for invalidation complete */ 5795 for (i = 0; i < usec_timeout; i++) { 5796 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5797 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5798 INVALIDATE_CACHE_COMPLETE)) 5799 break; 5800 udelay(1); 5801 } 5802 5803 if (i >= usec_timeout) { 5804 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5805 return -EINVAL; 5806 } 5807 5808 /* Program mec1 ucode address into intruction cache address register */ 5809 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5810 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5811 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5812 lower_32_bits(addr) & 0xFFFFF000); 5813 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5814 upper_32_bits(addr)); 5815 5816 return 0; 5817 } 5818 5819 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5820 { 5821 uint32_t cp_status; 5822 uint32_t bootload_status; 5823 int i, r; 5824 5825 for (i = 0; i < adev->usec_timeout; i++) { 5826 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5827 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5828 if ((cp_status == 0) && 5829 (REG_GET_FIELD(bootload_status, 5830 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5831 break; 5832 } 5833 udelay(1); 5834 } 5835 5836 if (i >= adev->usec_timeout) { 5837 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5838 return -ETIMEDOUT; 5839 } 5840 5841 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5842 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5843 if (r) 5844 return r; 5845 5846 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5847 if (r) 5848 return r; 5849 5850 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5851 if (r) 5852 return r; 5853 5854 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5855 if (r) 5856 return r; 5857 } 5858 5859 return 0; 5860 } 5861 5862 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5863 { 5864 int i; 5865 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5866 5867 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5868 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5869 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5870 5871 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5872 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5873 else 5874 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5875 5876 if (adev->job_hang && !enable) 5877 return 0; 5878 5879 for (i = 0; i < adev->usec_timeout; i++) { 5880 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5881 break; 5882 udelay(1); 5883 } 5884 5885 if (i >= adev->usec_timeout) 5886 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5887 5888 return 0; 5889 } 5890 5891 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5892 { 5893 int r; 5894 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5895 const __le32 *fw_data; 5896 unsigned int i, fw_size; 5897 uint32_t tmp; 5898 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5899 5900 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5901 adev->gfx.pfp_fw->data; 5902 5903 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5904 5905 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5906 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5907 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5908 5909 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5910 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5911 &adev->gfx.pfp.pfp_fw_obj, 5912 &adev->gfx.pfp.pfp_fw_gpu_addr, 5913 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5914 if (r) { 5915 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5916 gfx_v10_0_pfp_fini(adev); 5917 return r; 5918 } 5919 5920 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5921 5922 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5923 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5924 5925 /* Trigger an invalidation of the L1 instruction caches */ 5926 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5927 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5928 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5929 5930 /* Wait for invalidation complete */ 5931 for (i = 0; i < usec_timeout; i++) { 5932 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5933 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5934 INVALIDATE_CACHE_COMPLETE)) 5935 break; 5936 udelay(1); 5937 } 5938 5939 if (i >= usec_timeout) { 5940 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5941 return -EINVAL; 5942 } 5943 5944 if (amdgpu_emu_mode == 1) 5945 adev->hdp.funcs->flush_hdp(adev, NULL); 5946 5947 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5948 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5949 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5950 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5951 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5952 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5953 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5954 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5955 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5956 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5957 5958 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5959 5960 for (i = 0; i < pfp_hdr->jt_size; i++) 5961 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5962 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5963 5964 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5965 5966 return 0; 5967 } 5968 5969 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5970 { 5971 int r; 5972 const struct gfx_firmware_header_v1_0 *ce_hdr; 5973 const __le32 *fw_data; 5974 unsigned int i, fw_size; 5975 uint32_t tmp; 5976 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5977 5978 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5979 adev->gfx.ce_fw->data; 5980 5981 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5982 5983 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5984 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5985 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5986 5987 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5988 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5989 &adev->gfx.ce.ce_fw_obj, 5990 &adev->gfx.ce.ce_fw_gpu_addr, 5991 (void **)&adev->gfx.ce.ce_fw_ptr); 5992 if (r) { 5993 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5994 gfx_v10_0_ce_fini(adev); 5995 return r; 5996 } 5997 5998 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5999 6000 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6001 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6002 6003 /* Trigger an invalidation of the L1 instruction caches */ 6004 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6005 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6006 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6007 6008 /* Wait for invalidation complete */ 6009 for (i = 0; i < usec_timeout; i++) { 6010 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6011 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6012 INVALIDATE_CACHE_COMPLETE)) 6013 break; 6014 udelay(1); 6015 } 6016 6017 if (i >= usec_timeout) { 6018 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6019 return -EINVAL; 6020 } 6021 6022 if (amdgpu_emu_mode == 1) 6023 adev->hdp.funcs->flush_hdp(adev, NULL); 6024 6025 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6026 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6027 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6028 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6029 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6030 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6031 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6032 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6033 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6034 6035 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6036 6037 for (i = 0; i < ce_hdr->jt_size; i++) 6038 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6039 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6040 6041 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6042 6043 return 0; 6044 } 6045 6046 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6047 { 6048 int r; 6049 const struct gfx_firmware_header_v1_0 *me_hdr; 6050 const __le32 *fw_data; 6051 unsigned int i, fw_size; 6052 uint32_t tmp; 6053 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6054 6055 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6056 adev->gfx.me_fw->data; 6057 6058 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6059 6060 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6061 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6062 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6063 6064 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6065 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6066 &adev->gfx.me.me_fw_obj, 6067 &adev->gfx.me.me_fw_gpu_addr, 6068 (void **)&adev->gfx.me.me_fw_ptr); 6069 if (r) { 6070 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6071 gfx_v10_0_me_fini(adev); 6072 return r; 6073 } 6074 6075 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6076 6077 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6078 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6079 6080 /* Trigger an invalidation of the L1 instruction caches */ 6081 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6082 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6083 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6084 6085 /* Wait for invalidation complete */ 6086 for (i = 0; i < usec_timeout; i++) { 6087 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6088 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6089 INVALIDATE_CACHE_COMPLETE)) 6090 break; 6091 udelay(1); 6092 } 6093 6094 if (i >= usec_timeout) { 6095 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6096 return -EINVAL; 6097 } 6098 6099 if (amdgpu_emu_mode == 1) 6100 adev->hdp.funcs->flush_hdp(adev, NULL); 6101 6102 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6103 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6104 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6105 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6106 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6107 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6108 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6109 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6110 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6111 6112 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6113 6114 for (i = 0; i < me_hdr->jt_size; i++) 6115 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6116 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6117 6118 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6119 6120 return 0; 6121 } 6122 6123 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6124 { 6125 int r; 6126 6127 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6128 return -EINVAL; 6129 6130 gfx_v10_0_cp_gfx_enable(adev, false); 6131 6132 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6133 if (r) { 6134 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6135 return r; 6136 } 6137 6138 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6139 if (r) { 6140 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6141 return r; 6142 } 6143 6144 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6145 if (r) { 6146 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6147 return r; 6148 } 6149 6150 return 0; 6151 } 6152 6153 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6154 { 6155 struct amdgpu_ring *ring; 6156 const struct cs_section_def *sect = NULL; 6157 const struct cs_extent_def *ext = NULL; 6158 int r, i; 6159 int ctx_reg_offset; 6160 6161 /* init the CP */ 6162 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6163 adev->gfx.config.max_hw_contexts - 1); 6164 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6165 6166 gfx_v10_0_cp_gfx_enable(adev, true); 6167 6168 ring = &adev->gfx.gfx_ring[0]; 6169 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6170 if (r) { 6171 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6172 return r; 6173 } 6174 6175 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6176 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6177 6178 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6179 amdgpu_ring_write(ring, 0x80000000); 6180 amdgpu_ring_write(ring, 0x80000000); 6181 6182 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6183 for (ext = sect->section; ext->extent != NULL; ++ext) { 6184 if (sect->id == SECT_CONTEXT) { 6185 amdgpu_ring_write(ring, 6186 PACKET3(PACKET3_SET_CONTEXT_REG, 6187 ext->reg_count)); 6188 amdgpu_ring_write(ring, ext->reg_index - 6189 PACKET3_SET_CONTEXT_REG_START); 6190 for (i = 0; i < ext->reg_count; i++) 6191 amdgpu_ring_write(ring, ext->extent[i]); 6192 } 6193 } 6194 } 6195 6196 ctx_reg_offset = 6197 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6198 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6199 amdgpu_ring_write(ring, ctx_reg_offset); 6200 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6201 6202 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6203 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6204 6205 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6206 amdgpu_ring_write(ring, 0); 6207 6208 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6209 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6210 amdgpu_ring_write(ring, 0x8000); 6211 amdgpu_ring_write(ring, 0x8000); 6212 6213 amdgpu_ring_commit(ring); 6214 6215 /* submit cs packet to copy state 0 to next available state */ 6216 if (adev->gfx.num_gfx_rings > 1) { 6217 /* maximum supported gfx ring is 2 */ 6218 ring = &adev->gfx.gfx_ring[1]; 6219 r = amdgpu_ring_alloc(ring, 2); 6220 if (r) { 6221 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6222 return r; 6223 } 6224 6225 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6226 amdgpu_ring_write(ring, 0); 6227 6228 amdgpu_ring_commit(ring); 6229 } 6230 return 0; 6231 } 6232 6233 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6234 CP_PIPE_ID pipe) 6235 { 6236 u32 tmp; 6237 6238 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6239 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6240 6241 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6242 } 6243 6244 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6245 struct amdgpu_ring *ring) 6246 { 6247 u32 tmp; 6248 6249 if (!amdgpu_async_gfx_ring) { 6250 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6251 if (ring->use_doorbell) { 6252 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6253 DOORBELL_OFFSET, ring->doorbell_index); 6254 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6255 DOORBELL_EN, 1); 6256 } else { 6257 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6258 DOORBELL_EN, 0); 6259 } 6260 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6261 } 6262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6263 case IP_VERSION(10, 3, 0): 6264 case IP_VERSION(10, 3, 2): 6265 case IP_VERSION(10, 3, 1): 6266 case IP_VERSION(10, 3, 4): 6267 case IP_VERSION(10, 3, 5): 6268 case IP_VERSION(10, 3, 6): 6269 case IP_VERSION(10, 3, 3): 6270 case IP_VERSION(10, 3, 7): 6271 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6272 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6273 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6274 6275 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6276 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6277 break; 6278 default: 6279 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6280 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6281 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6282 6283 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6284 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6285 break; 6286 } 6287 } 6288 6289 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6290 { 6291 struct amdgpu_ring *ring; 6292 u32 tmp; 6293 u32 rb_bufsz; 6294 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6295 6296 /* Set the write pointer delay */ 6297 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6298 6299 /* set the RB to use vmid 0 */ 6300 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6301 6302 /* Init gfx ring 0 for pipe 0 */ 6303 mutex_lock(&adev->srbm_mutex); 6304 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6305 6306 /* Set ring buffer size */ 6307 ring = &adev->gfx.gfx_ring[0]; 6308 rb_bufsz = order_base_2(ring->ring_size / 8); 6309 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6310 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6311 #ifdef __BIG_ENDIAN 6312 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6313 #endif 6314 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6315 6316 /* Initialize the ring buffer's write pointers */ 6317 ring->wptr = 0; 6318 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6319 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6320 6321 /* set the wb address wether it's enabled or not */ 6322 rptr_addr = ring->rptr_gpu_addr; 6323 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6324 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6325 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6326 6327 wptr_gpu_addr = ring->wptr_gpu_addr; 6328 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6329 lower_32_bits(wptr_gpu_addr)); 6330 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6331 upper_32_bits(wptr_gpu_addr)); 6332 6333 mdelay(1); 6334 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6335 6336 rb_addr = ring->gpu_addr >> 8; 6337 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6338 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6339 6340 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6341 6342 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6343 mutex_unlock(&adev->srbm_mutex); 6344 6345 /* Init gfx ring 1 for pipe 1 */ 6346 if (adev->gfx.num_gfx_rings > 1) { 6347 mutex_lock(&adev->srbm_mutex); 6348 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6349 /* maximum supported gfx ring is 2 */ 6350 ring = &adev->gfx.gfx_ring[1]; 6351 rb_bufsz = order_base_2(ring->ring_size / 8); 6352 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6353 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6354 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6355 /* Initialize the ring buffer's write pointers */ 6356 ring->wptr = 0; 6357 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6358 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6359 /* Set the wb address wether it's enabled or not */ 6360 rptr_addr = ring->rptr_gpu_addr; 6361 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6362 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6363 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6364 wptr_gpu_addr = ring->wptr_gpu_addr; 6365 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6366 lower_32_bits(wptr_gpu_addr)); 6367 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6368 upper_32_bits(wptr_gpu_addr)); 6369 6370 mdelay(1); 6371 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6372 6373 rb_addr = ring->gpu_addr >> 8; 6374 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6375 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6376 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6377 6378 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6379 mutex_unlock(&adev->srbm_mutex); 6380 } 6381 /* Switch to pipe 0 */ 6382 mutex_lock(&adev->srbm_mutex); 6383 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6384 mutex_unlock(&adev->srbm_mutex); 6385 6386 /* start the ring */ 6387 gfx_v10_0_cp_gfx_start(adev); 6388 6389 return 0; 6390 } 6391 6392 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6393 { 6394 if (enable) { 6395 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6396 case IP_VERSION(10, 3, 0): 6397 case IP_VERSION(10, 3, 2): 6398 case IP_VERSION(10, 3, 1): 6399 case IP_VERSION(10, 3, 4): 6400 case IP_VERSION(10, 3, 5): 6401 case IP_VERSION(10, 3, 6): 6402 case IP_VERSION(10, 3, 3): 6403 case IP_VERSION(10, 3, 7): 6404 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6405 break; 6406 default: 6407 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6408 break; 6409 } 6410 } else { 6411 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6412 case IP_VERSION(10, 3, 0): 6413 case IP_VERSION(10, 3, 2): 6414 case IP_VERSION(10, 3, 1): 6415 case IP_VERSION(10, 3, 4): 6416 case IP_VERSION(10, 3, 5): 6417 case IP_VERSION(10, 3, 6): 6418 case IP_VERSION(10, 3, 3): 6419 case IP_VERSION(10, 3, 7): 6420 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6421 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6422 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6423 break; 6424 default: 6425 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6426 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6427 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6428 break; 6429 } 6430 adev->gfx.kiq[0].ring.sched.ready = false; 6431 } 6432 udelay(50); 6433 } 6434 6435 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6436 { 6437 const struct gfx_firmware_header_v1_0 *mec_hdr; 6438 const __le32 *fw_data; 6439 unsigned int i; 6440 u32 tmp; 6441 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6442 6443 if (!adev->gfx.mec_fw) 6444 return -EINVAL; 6445 6446 gfx_v10_0_cp_compute_enable(adev, false); 6447 6448 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6449 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6450 6451 fw_data = (const __le32 *) 6452 (adev->gfx.mec_fw->data + 6453 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6454 6455 /* Trigger an invalidation of the L1 instruction caches */ 6456 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6457 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6458 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6459 6460 /* Wait for invalidation complete */ 6461 for (i = 0; i < usec_timeout; i++) { 6462 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6463 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6464 INVALIDATE_CACHE_COMPLETE)) 6465 break; 6466 udelay(1); 6467 } 6468 6469 if (i >= usec_timeout) { 6470 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6471 return -EINVAL; 6472 } 6473 6474 if (amdgpu_emu_mode == 1) 6475 adev->hdp.funcs->flush_hdp(adev, NULL); 6476 6477 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6478 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6479 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6480 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6481 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6482 6483 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6484 0xFFFFF000); 6485 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6486 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6487 6488 /* MEC1 */ 6489 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6490 6491 for (i = 0; i < mec_hdr->jt_size; i++) 6492 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6493 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6494 6495 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6496 6497 /* 6498 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6499 * different microcode than MEC1. 6500 */ 6501 6502 return 0; 6503 } 6504 6505 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6506 { 6507 uint32_t tmp; 6508 struct amdgpu_device *adev = ring->adev; 6509 6510 /* tell RLC which is KIQ queue */ 6511 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6512 case IP_VERSION(10, 3, 0): 6513 case IP_VERSION(10, 3, 2): 6514 case IP_VERSION(10, 3, 1): 6515 case IP_VERSION(10, 3, 4): 6516 case IP_VERSION(10, 3, 5): 6517 case IP_VERSION(10, 3, 6): 6518 case IP_VERSION(10, 3, 3): 6519 case IP_VERSION(10, 3, 7): 6520 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6521 tmp &= 0xffffff00; 6522 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6523 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6524 tmp |= 0x80; 6525 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6526 break; 6527 default: 6528 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6529 tmp &= 0xffffff00; 6530 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6531 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6532 tmp |= 0x80; 6533 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6534 break; 6535 } 6536 } 6537 6538 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6539 struct v10_gfx_mqd *mqd, 6540 struct amdgpu_mqd_prop *prop) 6541 { 6542 bool priority = 0; 6543 u32 tmp; 6544 6545 /* set up default queue priority level 6546 * 0x0 = low priority, 0x1 = high priority 6547 */ 6548 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6549 priority = 1; 6550 6551 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6552 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6553 mqd->cp_gfx_hqd_queue_priority = tmp; 6554 } 6555 6556 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6557 struct amdgpu_mqd_prop *prop) 6558 { 6559 struct v10_gfx_mqd *mqd = m; 6560 uint64_t hqd_gpu_addr, wb_gpu_addr; 6561 uint32_t tmp; 6562 uint32_t rb_bufsz; 6563 6564 /* set up gfx hqd wptr */ 6565 mqd->cp_gfx_hqd_wptr = 0; 6566 mqd->cp_gfx_hqd_wptr_hi = 0; 6567 6568 /* set the pointer to the MQD */ 6569 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6570 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6571 6572 /* set up mqd control */ 6573 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6574 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6575 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6576 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6577 mqd->cp_gfx_mqd_control = tmp; 6578 6579 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6580 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6581 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6582 mqd->cp_gfx_hqd_vmid = 0; 6583 6584 /* set up gfx queue priority */ 6585 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6586 6587 /* set up time quantum */ 6588 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6589 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6590 mqd->cp_gfx_hqd_quantum = tmp; 6591 6592 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6593 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6594 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6595 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6596 6597 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6598 wb_gpu_addr = prop->rptr_gpu_addr; 6599 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6600 mqd->cp_gfx_hqd_rptr_addr_hi = 6601 upper_32_bits(wb_gpu_addr) & 0xffff; 6602 6603 /* set up rb_wptr_poll addr */ 6604 wb_gpu_addr = prop->wptr_gpu_addr; 6605 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6606 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6607 6608 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6609 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6610 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6611 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6612 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6613 #ifdef __BIG_ENDIAN 6614 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6615 #endif 6616 mqd->cp_gfx_hqd_cntl = tmp; 6617 6618 /* set up cp_doorbell_control */ 6619 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6620 if (prop->use_doorbell) { 6621 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6622 DOORBELL_OFFSET, prop->doorbell_index); 6623 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6624 DOORBELL_EN, 1); 6625 } else 6626 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6627 DOORBELL_EN, 0); 6628 mqd->cp_rb_doorbell_control = tmp; 6629 6630 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6631 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6632 6633 /* active the queue */ 6634 mqd->cp_gfx_hqd_active = 1; 6635 6636 return 0; 6637 } 6638 6639 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6640 { 6641 struct amdgpu_device *adev = ring->adev; 6642 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6643 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6644 6645 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6646 memset((void *)mqd, 0, sizeof(*mqd)); 6647 mutex_lock(&adev->srbm_mutex); 6648 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6649 amdgpu_ring_init_mqd(ring); 6650 6651 /* 6652 * if there are 2 gfx rings, set the lower doorbell 6653 * range of the first ring, otherwise the range of 6654 * the second ring will override the first ring 6655 */ 6656 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6657 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6658 6659 nv_grbm_select(adev, 0, 0, 0, 0); 6660 mutex_unlock(&adev->srbm_mutex); 6661 if (adev->gfx.me.mqd_backup[mqd_idx]) 6662 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6663 } else { 6664 mutex_lock(&adev->srbm_mutex); 6665 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6666 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6667 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6668 6669 nv_grbm_select(adev, 0, 0, 0, 0); 6670 mutex_unlock(&adev->srbm_mutex); 6671 /* restore mqd with the backup copy */ 6672 if (adev->gfx.me.mqd_backup[mqd_idx]) 6673 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6674 /* reset the ring */ 6675 ring->wptr = 0; 6676 *ring->wptr_cpu_addr = 0; 6677 amdgpu_ring_clear_ring(ring); 6678 } 6679 6680 return 0; 6681 } 6682 6683 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6684 { 6685 int r, i; 6686 struct amdgpu_ring *ring; 6687 6688 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6689 ring = &adev->gfx.gfx_ring[i]; 6690 6691 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6692 if (unlikely(r != 0)) 6693 return r; 6694 6695 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6696 if (!r) { 6697 r = gfx_v10_0_gfx_init_queue(ring); 6698 amdgpu_bo_kunmap(ring->mqd_obj); 6699 ring->mqd_ptr = NULL; 6700 } 6701 amdgpu_bo_unreserve(ring->mqd_obj); 6702 if (r) 6703 return r; 6704 } 6705 6706 r = amdgpu_gfx_enable_kgq(adev, 0); 6707 if (r) 6708 return r; 6709 6710 return gfx_v10_0_cp_gfx_start(adev); 6711 } 6712 6713 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6714 struct amdgpu_mqd_prop *prop) 6715 { 6716 struct v10_compute_mqd *mqd = m; 6717 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6718 uint32_t tmp; 6719 6720 mqd->header = 0xC0310800; 6721 mqd->compute_pipelinestat_enable = 0x00000001; 6722 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6723 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6724 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6725 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6726 mqd->compute_misc_reserved = 0x00000003; 6727 6728 eop_base_addr = prop->eop_gpu_addr >> 8; 6729 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6730 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6731 6732 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6733 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6734 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6735 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6736 6737 mqd->cp_hqd_eop_control = tmp; 6738 6739 /* enable doorbell? */ 6740 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6741 6742 if (prop->use_doorbell) { 6743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6744 DOORBELL_OFFSET, prop->doorbell_index); 6745 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6746 DOORBELL_EN, 1); 6747 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6748 DOORBELL_SOURCE, 0); 6749 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6750 DOORBELL_HIT, 0); 6751 } else { 6752 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6753 DOORBELL_EN, 0); 6754 } 6755 6756 mqd->cp_hqd_pq_doorbell_control = tmp; 6757 6758 /* disable the queue if it's active */ 6759 mqd->cp_hqd_dequeue_request = 0; 6760 mqd->cp_hqd_pq_rptr = 0; 6761 mqd->cp_hqd_pq_wptr_lo = 0; 6762 mqd->cp_hqd_pq_wptr_hi = 0; 6763 6764 /* set the pointer to the MQD */ 6765 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6766 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6767 6768 /* set MQD vmid to 0 */ 6769 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6770 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6771 mqd->cp_mqd_control = tmp; 6772 6773 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6774 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6775 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6776 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6777 6778 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6779 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6781 (order_base_2(prop->queue_size / 4) - 1)); 6782 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6783 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6784 #ifdef __BIG_ENDIAN 6785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6786 #endif 6787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6788 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6789 prop->allow_tunneling); 6790 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6791 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6792 mqd->cp_hqd_pq_control = tmp; 6793 6794 /* set the wb address whether it's enabled or not */ 6795 wb_gpu_addr = prop->rptr_gpu_addr; 6796 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6797 mqd->cp_hqd_pq_rptr_report_addr_hi = 6798 upper_32_bits(wb_gpu_addr) & 0xffff; 6799 6800 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6801 wb_gpu_addr = prop->wptr_gpu_addr; 6802 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6803 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6804 6805 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6806 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6807 6808 /* set the vmid for the queue */ 6809 mqd->cp_hqd_vmid = 0; 6810 6811 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6812 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6813 mqd->cp_hqd_persistent_state = tmp; 6814 6815 /* set MIN_IB_AVAIL_SIZE */ 6816 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6817 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6818 mqd->cp_hqd_ib_control = tmp; 6819 6820 /* set static priority for a compute queue/ring */ 6821 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6822 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6823 6824 mqd->cp_hqd_active = prop->hqd_active; 6825 6826 return 0; 6827 } 6828 6829 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6830 { 6831 struct amdgpu_device *adev = ring->adev; 6832 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6833 int j; 6834 6835 /* inactivate the queue */ 6836 if (amdgpu_sriov_vf(adev)) 6837 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6838 6839 /* disable wptr polling */ 6840 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6841 6842 /* disable the queue if it's active */ 6843 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6844 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6845 for (j = 0; j < adev->usec_timeout; j++) { 6846 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6847 break; 6848 udelay(1); 6849 } 6850 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6851 mqd->cp_hqd_dequeue_request); 6852 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6853 mqd->cp_hqd_pq_rptr); 6854 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6855 mqd->cp_hqd_pq_wptr_lo); 6856 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6857 mqd->cp_hqd_pq_wptr_hi); 6858 } 6859 6860 /* disable doorbells */ 6861 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6862 6863 /* write the EOP addr */ 6864 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6865 mqd->cp_hqd_eop_base_addr_lo); 6866 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6867 mqd->cp_hqd_eop_base_addr_hi); 6868 6869 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6870 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6871 mqd->cp_hqd_eop_control); 6872 6873 /* set the pointer to the MQD */ 6874 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6875 mqd->cp_mqd_base_addr_lo); 6876 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6877 mqd->cp_mqd_base_addr_hi); 6878 6879 /* set MQD vmid to 0 */ 6880 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6881 mqd->cp_mqd_control); 6882 6883 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6884 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6885 mqd->cp_hqd_pq_base_lo); 6886 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6887 mqd->cp_hqd_pq_base_hi); 6888 6889 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6890 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6891 mqd->cp_hqd_pq_control); 6892 6893 /* set the wb address whether it's enabled or not */ 6894 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6895 mqd->cp_hqd_pq_rptr_report_addr_lo); 6896 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6897 mqd->cp_hqd_pq_rptr_report_addr_hi); 6898 6899 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6900 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6901 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6902 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6903 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6904 6905 /* enable the doorbell if requested */ 6906 if (ring->use_doorbell) { 6907 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6908 (adev->doorbell_index.kiq * 2) << 2); 6909 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6910 (adev->doorbell_index.userqueue_end * 2) << 2); 6911 } 6912 6913 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6914 mqd->cp_hqd_pq_doorbell_control); 6915 6916 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6917 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6918 mqd->cp_hqd_pq_wptr_lo); 6919 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6920 mqd->cp_hqd_pq_wptr_hi); 6921 6922 /* set the vmid for the queue */ 6923 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6924 6925 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6926 mqd->cp_hqd_persistent_state); 6927 6928 /* activate the queue */ 6929 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6930 mqd->cp_hqd_active); 6931 6932 if (ring->use_doorbell) 6933 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6934 6935 return 0; 6936 } 6937 6938 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6939 { 6940 struct amdgpu_device *adev = ring->adev; 6941 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6942 6943 gfx_v10_0_kiq_setting(ring); 6944 6945 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6946 /* reset MQD to a clean status */ 6947 if (adev->gfx.kiq[0].mqd_backup) 6948 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6949 6950 /* reset ring buffer */ 6951 ring->wptr = 0; 6952 amdgpu_ring_clear_ring(ring); 6953 6954 mutex_lock(&adev->srbm_mutex); 6955 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6956 gfx_v10_0_kiq_init_register(ring); 6957 nv_grbm_select(adev, 0, 0, 0, 0); 6958 mutex_unlock(&adev->srbm_mutex); 6959 } else { 6960 memset((void *)mqd, 0, sizeof(*mqd)); 6961 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6962 amdgpu_ring_clear_ring(ring); 6963 mutex_lock(&adev->srbm_mutex); 6964 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6965 amdgpu_ring_init_mqd(ring); 6966 gfx_v10_0_kiq_init_register(ring); 6967 nv_grbm_select(adev, 0, 0, 0, 0); 6968 mutex_unlock(&adev->srbm_mutex); 6969 6970 if (adev->gfx.kiq[0].mqd_backup) 6971 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6972 } 6973 6974 return 0; 6975 } 6976 6977 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6978 { 6979 struct amdgpu_device *adev = ring->adev; 6980 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6981 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6982 6983 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6984 memset((void *)mqd, 0, sizeof(*mqd)); 6985 mutex_lock(&adev->srbm_mutex); 6986 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6987 amdgpu_ring_init_mqd(ring); 6988 nv_grbm_select(adev, 0, 0, 0, 0); 6989 mutex_unlock(&adev->srbm_mutex); 6990 6991 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6992 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6993 } else { 6994 /* restore MQD to a clean status */ 6995 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6996 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6997 /* reset ring buffer */ 6998 ring->wptr = 0; 6999 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7000 amdgpu_ring_clear_ring(ring); 7001 } 7002 7003 return 0; 7004 } 7005 7006 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7007 { 7008 struct amdgpu_ring *ring; 7009 int r; 7010 7011 ring = &adev->gfx.kiq[0].ring; 7012 7013 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7014 if (unlikely(r != 0)) 7015 return r; 7016 7017 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7018 if (unlikely(r != 0)) { 7019 amdgpu_bo_unreserve(ring->mqd_obj); 7020 return r; 7021 } 7022 7023 gfx_v10_0_kiq_init_queue(ring); 7024 amdgpu_bo_kunmap(ring->mqd_obj); 7025 ring->mqd_ptr = NULL; 7026 amdgpu_bo_unreserve(ring->mqd_obj); 7027 return 0; 7028 } 7029 7030 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7031 { 7032 struct amdgpu_ring *ring = NULL; 7033 int r = 0, i; 7034 7035 gfx_v10_0_cp_compute_enable(adev, true); 7036 7037 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7038 ring = &adev->gfx.compute_ring[i]; 7039 7040 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7041 if (unlikely(r != 0)) 7042 goto done; 7043 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7044 if (!r) { 7045 r = gfx_v10_0_kcq_init_queue(ring); 7046 amdgpu_bo_kunmap(ring->mqd_obj); 7047 ring->mqd_ptr = NULL; 7048 } 7049 amdgpu_bo_unreserve(ring->mqd_obj); 7050 if (r) 7051 goto done; 7052 } 7053 7054 r = amdgpu_gfx_enable_kcq(adev, 0); 7055 done: 7056 return r; 7057 } 7058 7059 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7060 { 7061 int r, i; 7062 struct amdgpu_ring *ring; 7063 7064 if (!(adev->flags & AMD_IS_APU)) 7065 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7066 7067 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7068 /* legacy firmware loading */ 7069 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7070 if (r) 7071 return r; 7072 7073 r = gfx_v10_0_cp_compute_load_microcode(adev); 7074 if (r) 7075 return r; 7076 } 7077 7078 r = gfx_v10_0_kiq_resume(adev); 7079 if (r) 7080 return r; 7081 7082 r = gfx_v10_0_kcq_resume(adev); 7083 if (r) 7084 return r; 7085 7086 if (!amdgpu_async_gfx_ring) { 7087 r = gfx_v10_0_cp_gfx_resume(adev); 7088 if (r) 7089 return r; 7090 } else { 7091 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7092 if (r) 7093 return r; 7094 } 7095 7096 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7097 ring = &adev->gfx.gfx_ring[i]; 7098 r = amdgpu_ring_test_helper(ring); 7099 if (r) 7100 return r; 7101 } 7102 7103 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7104 ring = &adev->gfx.compute_ring[i]; 7105 r = amdgpu_ring_test_helper(ring); 7106 if (r) 7107 return r; 7108 } 7109 7110 return 0; 7111 } 7112 7113 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7114 { 7115 gfx_v10_0_cp_gfx_enable(adev, enable); 7116 gfx_v10_0_cp_compute_enable(adev, enable); 7117 } 7118 7119 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7120 { 7121 uint32_t data, pattern = 0xDEADBEEF; 7122 7123 /* 7124 * check if mmVGT_ESGS_RING_SIZE_UMD 7125 * has been remapped to mmVGT_ESGS_RING_SIZE 7126 */ 7127 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7128 case IP_VERSION(10, 3, 0): 7129 case IP_VERSION(10, 3, 2): 7130 case IP_VERSION(10, 3, 4): 7131 case IP_VERSION(10, 3, 5): 7132 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7133 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7134 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7135 7136 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7137 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7138 return true; 7139 } 7140 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7141 break; 7142 case IP_VERSION(10, 3, 1): 7143 case IP_VERSION(10, 3, 3): 7144 case IP_VERSION(10, 3, 6): 7145 case IP_VERSION(10, 3, 7): 7146 return true; 7147 default: 7148 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7149 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7150 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7151 7152 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7153 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7154 return true; 7155 } 7156 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7157 break; 7158 } 7159 7160 return false; 7161 } 7162 7163 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7164 { 7165 uint32_t data; 7166 7167 if (amdgpu_sriov_vf(adev)) 7168 return; 7169 7170 /* 7171 * Initialize cam_index to 0 7172 * index will auto-inc after each data writing 7173 */ 7174 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7175 7176 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7177 case IP_VERSION(10, 3, 0): 7178 case IP_VERSION(10, 3, 2): 7179 case IP_VERSION(10, 3, 1): 7180 case IP_VERSION(10, 3, 4): 7181 case IP_VERSION(10, 3, 5): 7182 case IP_VERSION(10, 3, 6): 7183 case IP_VERSION(10, 3, 3): 7184 case IP_VERSION(10, 3, 7): 7185 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7186 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7187 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7188 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7189 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7190 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7191 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7192 7193 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7194 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7195 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7196 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7197 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7198 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7199 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7200 7201 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7202 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7203 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7204 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7205 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7206 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7207 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7208 7209 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7210 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7211 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7212 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7213 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7214 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7215 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7216 7217 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7218 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7219 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7220 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7221 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7222 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7223 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7224 7225 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7226 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7227 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7228 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7229 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7230 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7231 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7232 7233 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7234 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7235 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7236 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7237 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7238 break; 7239 default: 7240 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7241 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7242 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7243 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7244 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7245 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7246 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7247 7248 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7249 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7250 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7251 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7252 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7253 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7254 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7255 7256 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7257 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7258 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7259 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7260 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7261 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7262 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7263 7264 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7265 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7266 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7267 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7268 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7269 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7270 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7271 7272 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7273 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7274 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7275 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7276 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7277 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7278 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7279 7280 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7281 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7282 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7283 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7284 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7285 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7286 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7287 7288 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7289 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7290 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7291 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7292 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7293 break; 7294 } 7295 7296 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7297 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7298 } 7299 7300 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7301 { 7302 uint32_t data; 7303 7304 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7305 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7306 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7307 7308 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7309 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7310 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7311 } 7312 7313 static int gfx_v10_0_hw_init(void *handle) 7314 { 7315 int r; 7316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7317 7318 if (!amdgpu_emu_mode) 7319 gfx_v10_0_init_golden_registers(adev); 7320 7321 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7322 /** 7323 * For gfx 10, rlc firmware loading relies on smu firmware is 7324 * loaded firstly, so in direct type, it has to load smc ucode 7325 * here before rlc. 7326 */ 7327 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7328 if (r) 7329 return r; 7330 gfx_v10_0_disable_gpa_mode(adev); 7331 } 7332 7333 /* if GRBM CAM not remapped, set up the remapping */ 7334 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7335 gfx_v10_0_setup_grbm_cam_remapping(adev); 7336 7337 gfx_v10_0_constants_init(adev); 7338 7339 r = gfx_v10_0_rlc_resume(adev); 7340 if (r) 7341 return r; 7342 7343 /* 7344 * init golden registers and rlc resume may override some registers, 7345 * reconfig them here 7346 */ 7347 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7348 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7349 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7350 gfx_v10_0_tcp_harvest(adev); 7351 7352 r = gfx_v10_0_cp_resume(adev); 7353 if (r) 7354 return r; 7355 7356 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7357 gfx_v10_3_program_pbb_mode(adev); 7358 7359 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7360 gfx_v10_3_set_power_brake_sequence(adev); 7361 7362 return r; 7363 } 7364 7365 static int gfx_v10_0_hw_fini(void *handle) 7366 { 7367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7368 7369 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7370 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7371 7372 /* WA added for Vangogh asic fixing the SMU suspend failure 7373 * It needs to set power gating again during gfxoff control 7374 * otherwise the gfxoff disallowing will be failed to set. 7375 */ 7376 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7377 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); 7378 7379 if (!adev->no_hw_access) { 7380 if (amdgpu_async_gfx_ring) { 7381 if (amdgpu_gfx_disable_kgq(adev, 0)) 7382 DRM_ERROR("KGQ disable failed\n"); 7383 } 7384 7385 if (amdgpu_gfx_disable_kcq(adev, 0)) 7386 DRM_ERROR("KCQ disable failed\n"); 7387 } 7388 7389 if (amdgpu_sriov_vf(adev)) { 7390 gfx_v10_0_cp_gfx_enable(adev, false); 7391 /* Remove the steps of clearing KIQ position. 7392 * It causes GFX hang when another Win guest is rendering. 7393 */ 7394 return 0; 7395 } 7396 gfx_v10_0_cp_enable(adev, false); 7397 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7398 7399 return 0; 7400 } 7401 7402 static int gfx_v10_0_suspend(void *handle) 7403 { 7404 return gfx_v10_0_hw_fini(handle); 7405 } 7406 7407 static int gfx_v10_0_resume(void *handle) 7408 { 7409 return gfx_v10_0_hw_init(handle); 7410 } 7411 7412 static bool gfx_v10_0_is_idle(void *handle) 7413 { 7414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7415 7416 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7417 GRBM_STATUS, GUI_ACTIVE)) 7418 return false; 7419 else 7420 return true; 7421 } 7422 7423 static int gfx_v10_0_wait_for_idle(void *handle) 7424 { 7425 unsigned int i; 7426 u32 tmp; 7427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7428 7429 for (i = 0; i < adev->usec_timeout; i++) { 7430 /* read MC_STATUS */ 7431 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7432 GRBM_STATUS__GUI_ACTIVE_MASK; 7433 7434 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7435 return 0; 7436 udelay(1); 7437 } 7438 return -ETIMEDOUT; 7439 } 7440 7441 static int gfx_v10_0_soft_reset(void *handle) 7442 { 7443 u32 grbm_soft_reset = 0; 7444 u32 tmp; 7445 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7446 7447 /* GRBM_STATUS */ 7448 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7449 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7450 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7451 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7452 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7453 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7454 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7455 GRBM_SOFT_RESET, SOFT_RESET_CP, 7456 1); 7457 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7458 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7459 1); 7460 } 7461 7462 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7463 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7464 GRBM_SOFT_RESET, SOFT_RESET_CP, 7465 1); 7466 } 7467 7468 /* GRBM_STATUS2 */ 7469 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7470 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7471 case IP_VERSION(10, 3, 0): 7472 case IP_VERSION(10, 3, 2): 7473 case IP_VERSION(10, 3, 1): 7474 case IP_VERSION(10, 3, 4): 7475 case IP_VERSION(10, 3, 5): 7476 case IP_VERSION(10, 3, 6): 7477 case IP_VERSION(10, 3, 3): 7478 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7479 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7480 GRBM_SOFT_RESET, 7481 SOFT_RESET_RLC, 7482 1); 7483 break; 7484 default: 7485 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7486 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7487 GRBM_SOFT_RESET, 7488 SOFT_RESET_RLC, 7489 1); 7490 break; 7491 } 7492 7493 if (grbm_soft_reset) { 7494 /* stop the rlc */ 7495 gfx_v10_0_rlc_stop(adev); 7496 7497 /* Disable GFX parsing/prefetching */ 7498 gfx_v10_0_cp_gfx_enable(adev, false); 7499 7500 /* Disable MEC parsing/prefetching */ 7501 gfx_v10_0_cp_compute_enable(adev, false); 7502 7503 if (grbm_soft_reset) { 7504 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7505 tmp |= grbm_soft_reset; 7506 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7507 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7508 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7509 7510 udelay(50); 7511 7512 tmp &= ~grbm_soft_reset; 7513 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7514 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7515 } 7516 7517 /* Wait a little for things to settle down */ 7518 udelay(50); 7519 } 7520 return 0; 7521 } 7522 7523 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7524 { 7525 uint64_t clock, clock_lo, clock_hi, hi_check; 7526 7527 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7528 case IP_VERSION(10, 1, 3): 7529 case IP_VERSION(10, 1, 4): 7530 preempt_disable(); 7531 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7532 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7533 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7534 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7535 * roughly every 42 seconds. 7536 */ 7537 if (hi_check != clock_hi) { 7538 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7539 clock_hi = hi_check; 7540 } 7541 preempt_enable(); 7542 clock = clock_lo | (clock_hi << 32ULL); 7543 break; 7544 case IP_VERSION(10, 3, 1): 7545 case IP_VERSION(10, 3, 3): 7546 case IP_VERSION(10, 3, 7): 7547 preempt_disable(); 7548 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7549 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7550 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7551 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7552 * roughly every 42 seconds. 7553 */ 7554 if (hi_check != clock_hi) { 7555 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7556 clock_hi = hi_check; 7557 } 7558 preempt_enable(); 7559 clock = clock_lo | (clock_hi << 32ULL); 7560 break; 7561 case IP_VERSION(10, 3, 6): 7562 preempt_disable(); 7563 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7564 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7565 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7566 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7567 * roughly every 42 seconds. 7568 */ 7569 if (hi_check != clock_hi) { 7570 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7571 clock_hi = hi_check; 7572 } 7573 preempt_enable(); 7574 clock = clock_lo | (clock_hi << 32ULL); 7575 break; 7576 default: 7577 preempt_disable(); 7578 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7579 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7580 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7581 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7582 * roughly every 42 seconds. 7583 */ 7584 if (hi_check != clock_hi) { 7585 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7586 clock_hi = hi_check; 7587 } 7588 preempt_enable(); 7589 clock = clock_lo | (clock_hi << 32ULL); 7590 break; 7591 } 7592 return clock; 7593 } 7594 7595 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7596 uint32_t vmid, 7597 uint32_t gds_base, uint32_t gds_size, 7598 uint32_t gws_base, uint32_t gws_size, 7599 uint32_t oa_base, uint32_t oa_size) 7600 { 7601 struct amdgpu_device *adev = ring->adev; 7602 7603 /* GDS Base */ 7604 gfx_v10_0_write_data_to_reg(ring, 0, false, 7605 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7606 gds_base); 7607 7608 /* GDS Size */ 7609 gfx_v10_0_write_data_to_reg(ring, 0, false, 7610 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7611 gds_size); 7612 7613 /* GWS */ 7614 gfx_v10_0_write_data_to_reg(ring, 0, false, 7615 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7616 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7617 7618 /* OA */ 7619 gfx_v10_0_write_data_to_reg(ring, 0, false, 7620 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7621 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7622 } 7623 7624 static int gfx_v10_0_early_init(void *handle) 7625 { 7626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7627 7628 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7629 7630 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7631 case IP_VERSION(10, 1, 10): 7632 case IP_VERSION(10, 1, 1): 7633 case IP_VERSION(10, 1, 2): 7634 case IP_VERSION(10, 1, 3): 7635 case IP_VERSION(10, 1, 4): 7636 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7637 break; 7638 case IP_VERSION(10, 3, 0): 7639 case IP_VERSION(10, 3, 2): 7640 case IP_VERSION(10, 3, 1): 7641 case IP_VERSION(10, 3, 4): 7642 case IP_VERSION(10, 3, 5): 7643 case IP_VERSION(10, 3, 6): 7644 case IP_VERSION(10, 3, 3): 7645 case IP_VERSION(10, 3, 7): 7646 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7647 break; 7648 default: 7649 break; 7650 } 7651 7652 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7653 AMDGPU_MAX_COMPUTE_RINGS); 7654 7655 gfx_v10_0_set_kiq_pm4_funcs(adev); 7656 gfx_v10_0_set_ring_funcs(adev); 7657 gfx_v10_0_set_irq_funcs(adev); 7658 gfx_v10_0_set_gds_init(adev); 7659 gfx_v10_0_set_rlc_funcs(adev); 7660 gfx_v10_0_set_mqd_funcs(adev); 7661 7662 /* init rlcg reg access ctrl */ 7663 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7664 7665 return gfx_v10_0_init_microcode(adev); 7666 } 7667 7668 static int gfx_v10_0_late_init(void *handle) 7669 { 7670 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7671 int r; 7672 7673 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7674 if (r) 7675 return r; 7676 7677 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7678 if (r) 7679 return r; 7680 7681 return 0; 7682 } 7683 7684 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7685 { 7686 uint32_t rlc_cntl; 7687 7688 /* if RLC is not enabled, do nothing */ 7689 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7690 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7691 } 7692 7693 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7694 { 7695 uint32_t data; 7696 unsigned int i; 7697 7698 data = RLC_SAFE_MODE__CMD_MASK; 7699 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7700 7701 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7702 case IP_VERSION(10, 3, 0): 7703 case IP_VERSION(10, 3, 2): 7704 case IP_VERSION(10, 3, 1): 7705 case IP_VERSION(10, 3, 4): 7706 case IP_VERSION(10, 3, 5): 7707 case IP_VERSION(10, 3, 6): 7708 case IP_VERSION(10, 3, 3): 7709 case IP_VERSION(10, 3, 7): 7710 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7711 7712 /* wait for RLC_SAFE_MODE */ 7713 for (i = 0; i < adev->usec_timeout; i++) { 7714 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7715 RLC_SAFE_MODE, CMD)) 7716 break; 7717 udelay(1); 7718 } 7719 break; 7720 default: 7721 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7722 7723 /* wait for RLC_SAFE_MODE */ 7724 for (i = 0; i < adev->usec_timeout; i++) { 7725 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7726 RLC_SAFE_MODE, CMD)) 7727 break; 7728 udelay(1); 7729 } 7730 break; 7731 } 7732 } 7733 7734 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7735 { 7736 uint32_t data; 7737 7738 data = RLC_SAFE_MODE__CMD_MASK; 7739 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7740 case IP_VERSION(10, 3, 0): 7741 case IP_VERSION(10, 3, 2): 7742 case IP_VERSION(10, 3, 1): 7743 case IP_VERSION(10, 3, 4): 7744 case IP_VERSION(10, 3, 5): 7745 case IP_VERSION(10, 3, 6): 7746 case IP_VERSION(10, 3, 3): 7747 case IP_VERSION(10, 3, 7): 7748 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7749 break; 7750 default: 7751 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7752 break; 7753 } 7754 } 7755 7756 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7757 bool enable) 7758 { 7759 uint32_t data, def; 7760 7761 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7762 return; 7763 7764 /* It is disabled by HW by default */ 7765 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7766 /* 0 - Disable some blocks' MGCG */ 7767 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7768 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7769 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7770 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7771 7772 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7773 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7774 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7775 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7776 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7777 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7778 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7779 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7780 7781 if (def != data) 7782 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7783 7784 /* MGLS is a global flag to control all MGLS in GFX */ 7785 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7786 /* 2 - RLC memory Light sleep */ 7787 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7788 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7789 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7790 if (def != data) 7791 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7792 } 7793 /* 3 - CP memory Light sleep */ 7794 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7795 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7796 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7797 if (def != data) 7798 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7799 } 7800 } 7801 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7802 /* 1 - MGCG_OVERRIDE */ 7803 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7804 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7805 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7806 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7807 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7808 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7809 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7810 if (def != data) 7811 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7812 7813 /* 2 - disable MGLS in CP */ 7814 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7815 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7816 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7817 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7818 } 7819 7820 /* 3 - disable MGLS in RLC */ 7821 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7822 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7823 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7824 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7825 } 7826 7827 } 7828 } 7829 7830 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7831 bool enable) 7832 { 7833 uint32_t data, def; 7834 7835 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7836 return; 7837 7838 /* Enable 3D CGCG/CGLS */ 7839 if (enable) { 7840 /* write cmd to clear cgcg/cgls ov */ 7841 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7842 7843 /* unset CGCG override */ 7844 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7845 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7846 7847 /* update CGCG and CGLS override bits */ 7848 if (def != data) 7849 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7850 7851 /* enable 3Dcgcg FSM(0x0000363f) */ 7852 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7853 data = 0; 7854 7855 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7856 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7857 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7858 7859 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7860 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7861 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7862 7863 if (def != data) 7864 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7865 7866 /* set IDLE_POLL_COUNT(0x00900100) */ 7867 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7868 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7869 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7870 if (def != data) 7871 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7872 } else { 7873 /* Disable CGCG/CGLS */ 7874 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7875 7876 /* disable cgcg, cgls should be disabled */ 7877 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7878 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7879 7880 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7881 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7882 7883 /* disable cgcg and cgls in FSM */ 7884 if (def != data) 7885 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7886 } 7887 } 7888 7889 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7890 bool enable) 7891 { 7892 uint32_t def, data; 7893 7894 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7895 return; 7896 7897 if (enable) { 7898 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7899 7900 /* unset CGCG override */ 7901 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7902 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7903 7904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7905 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7906 7907 /* update CGCG and CGLS override bits */ 7908 if (def != data) 7909 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7910 7911 /* enable cgcg FSM(0x0000363F) */ 7912 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7913 data = 0; 7914 7915 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7916 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7917 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7918 7919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7920 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7921 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7922 7923 if (def != data) 7924 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7925 7926 /* set IDLE_POLL_COUNT(0x00900100) */ 7927 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7928 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7929 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7930 if (def != data) 7931 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7932 } else { 7933 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7934 7935 /* reset CGCG/CGLS bits */ 7936 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7937 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7938 7939 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7940 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7941 7942 /* disable cgcg and cgls in FSM */ 7943 if (def != data) 7944 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7945 } 7946 } 7947 7948 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7949 bool enable) 7950 { 7951 uint32_t def, data; 7952 7953 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7954 return; 7955 7956 if (enable) { 7957 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7958 /* unset FGCG override */ 7959 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7960 /* update FGCG override bits */ 7961 if (def != data) 7962 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7963 7964 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7965 /* unset RLC SRAM CLK GATER override */ 7966 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7967 /* update RLC SRAM CLK GATER override bits */ 7968 if (def != data) 7969 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7970 } else { 7971 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7972 /* reset FGCG bits */ 7973 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7974 /* disable FGCG*/ 7975 if (def != data) 7976 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7977 7978 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7979 /* reset RLC SRAM CLK GATER bits */ 7980 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7981 /* disable RLC SRAM CLK*/ 7982 if (def != data) 7983 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7984 } 7985 } 7986 7987 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7988 { 7989 uint32_t reg_data = 0; 7990 uint32_t reg_idx = 0; 7991 uint32_t i; 7992 7993 const uint32_t tcp_ctrl_regs[] = { 7994 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7995 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7996 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7997 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7998 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7999 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8000 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8001 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8002 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8003 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8004 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8005 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8006 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8007 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8008 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8009 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8010 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8011 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8012 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8013 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8014 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8015 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8016 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8017 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8018 }; 8019 8020 const uint32_t tcp_ctrl_regs_nv12[] = { 8021 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8022 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8023 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8024 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8025 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8026 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8027 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8028 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8029 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8030 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8031 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8032 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8033 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8034 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8035 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8036 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8037 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8038 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8039 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8040 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8041 }; 8042 8043 const uint32_t sm_ctlr_regs[] = { 8044 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8045 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8046 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8047 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8048 }; 8049 8050 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8051 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8052 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8053 tcp_ctrl_regs_nv12[i]; 8054 reg_data = RREG32(reg_idx); 8055 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8056 WREG32(reg_idx, reg_data); 8057 } 8058 } else { 8059 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8060 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8061 tcp_ctrl_regs[i]; 8062 reg_data = RREG32(reg_idx); 8063 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8064 WREG32(reg_idx, reg_data); 8065 } 8066 } 8067 8068 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8069 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8070 sm_ctlr_regs[i]; 8071 reg_data = RREG32(reg_idx); 8072 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8073 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8074 WREG32(reg_idx, reg_data); 8075 } 8076 } 8077 8078 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8079 bool enable) 8080 { 8081 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8082 8083 if (enable) { 8084 /* enable FGCG firstly*/ 8085 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8086 /* CGCG/CGLS should be enabled after MGCG/MGLS 8087 * === MGCG + MGLS === 8088 */ 8089 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8090 /* === CGCG /CGLS for GFX 3D Only === */ 8091 gfx_v10_0_update_3d_clock_gating(adev, enable); 8092 /* === CGCG + CGLS === */ 8093 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8094 8095 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8096 IP_VERSION(10, 1, 10)) || 8097 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8098 IP_VERSION(10, 1, 1)) || 8099 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8100 IP_VERSION(10, 1, 2))) 8101 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8102 } else { 8103 /* CGCG/CGLS should be disabled before MGCG/MGLS 8104 * === CGCG + CGLS === 8105 */ 8106 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8107 /* === CGCG /CGLS for GFX 3D Only === */ 8108 gfx_v10_0_update_3d_clock_gating(adev, enable); 8109 /* === MGCG + MGLS === */ 8110 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8111 /* disable fgcg at last*/ 8112 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8113 } 8114 8115 if (adev->cg_flags & 8116 (AMD_CG_SUPPORT_GFX_MGCG | 8117 AMD_CG_SUPPORT_GFX_CGLS | 8118 AMD_CG_SUPPORT_GFX_CGCG | 8119 AMD_CG_SUPPORT_GFX_3D_CGCG | 8120 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8121 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8122 8123 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8124 8125 return 0; 8126 } 8127 8128 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8129 unsigned int vmid) 8130 { 8131 u32 reg, pre_data, data; 8132 8133 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8134 /* not for *_SOC15 */ 8135 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8136 pre_data = RREG32_NO_KIQ(reg); 8137 else 8138 pre_data = RREG32(reg); 8139 8140 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8141 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8142 8143 if (pre_data != data) { 8144 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8145 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8146 } else 8147 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8148 } 8149 } 8150 8151 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8152 { 8153 amdgpu_gfx_off_ctrl(adev, false); 8154 8155 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8156 8157 amdgpu_gfx_off_ctrl(adev, true); 8158 } 8159 8160 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8161 uint32_t offset, 8162 struct soc15_reg_rlcg *entries, int arr_size) 8163 { 8164 int i; 8165 uint32_t reg; 8166 8167 if (!entries) 8168 return false; 8169 8170 for (i = 0; i < arr_size; i++) { 8171 const struct soc15_reg_rlcg *entry; 8172 8173 entry = &entries[i]; 8174 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8175 if (offset == reg) 8176 return true; 8177 } 8178 8179 return false; 8180 } 8181 8182 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8183 { 8184 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8185 } 8186 8187 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8188 { 8189 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8190 8191 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8192 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8193 else 8194 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8195 8196 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8197 8198 /* 8199 * CGPG enablement required and the register to program the hysteresis value 8200 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8201 * in refclk count. Note that RLC FW is modified to take 16 bits from 8202 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8203 * 8204 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8205 * of CGPG enablement starting point. 8206 * Power/performance team will optimize it and might give a new value later. 8207 */ 8208 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8209 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8210 case IP_VERSION(10, 3, 1): 8211 case IP_VERSION(10, 3, 3): 8212 case IP_VERSION(10, 3, 6): 8213 case IP_VERSION(10, 3, 7): 8214 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8215 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8216 break; 8217 default: 8218 break; 8219 } 8220 } 8221 } 8222 8223 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8224 { 8225 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8226 8227 gfx_v10_cntl_power_gating(adev, enable); 8228 8229 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8230 } 8231 8232 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8233 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8234 .set_safe_mode = gfx_v10_0_set_safe_mode, 8235 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8236 .init = gfx_v10_0_rlc_init, 8237 .get_csb_size = gfx_v10_0_get_csb_size, 8238 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8239 .resume = gfx_v10_0_rlc_resume, 8240 .stop = gfx_v10_0_rlc_stop, 8241 .reset = gfx_v10_0_rlc_reset, 8242 .start = gfx_v10_0_rlc_start, 8243 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8244 }; 8245 8246 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8247 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8248 .set_safe_mode = gfx_v10_0_set_safe_mode, 8249 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8250 .init = gfx_v10_0_rlc_init, 8251 .get_csb_size = gfx_v10_0_get_csb_size, 8252 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8253 .resume = gfx_v10_0_rlc_resume, 8254 .stop = gfx_v10_0_rlc_stop, 8255 .reset = gfx_v10_0_rlc_reset, 8256 .start = gfx_v10_0_rlc_start, 8257 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8258 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8259 }; 8260 8261 static int gfx_v10_0_set_powergating_state(void *handle, 8262 enum amd_powergating_state state) 8263 { 8264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8265 bool enable = (state == AMD_PG_STATE_GATE); 8266 8267 if (amdgpu_sriov_vf(adev)) 8268 return 0; 8269 8270 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8271 case IP_VERSION(10, 1, 10): 8272 case IP_VERSION(10, 1, 1): 8273 case IP_VERSION(10, 1, 2): 8274 case IP_VERSION(10, 3, 0): 8275 case IP_VERSION(10, 3, 2): 8276 case IP_VERSION(10, 3, 4): 8277 case IP_VERSION(10, 3, 5): 8278 amdgpu_gfx_off_ctrl(adev, enable); 8279 break; 8280 case IP_VERSION(10, 3, 1): 8281 case IP_VERSION(10, 3, 3): 8282 case IP_VERSION(10, 3, 6): 8283 case IP_VERSION(10, 3, 7): 8284 if (!enable) 8285 amdgpu_gfx_off_ctrl(adev, false); 8286 8287 gfx_v10_cntl_pg(adev, enable); 8288 8289 if (enable) 8290 amdgpu_gfx_off_ctrl(adev, true); 8291 8292 break; 8293 default: 8294 break; 8295 } 8296 return 0; 8297 } 8298 8299 static int gfx_v10_0_set_clockgating_state(void *handle, 8300 enum amd_clockgating_state state) 8301 { 8302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8303 8304 if (amdgpu_sriov_vf(adev)) 8305 return 0; 8306 8307 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8308 case IP_VERSION(10, 1, 10): 8309 case IP_VERSION(10, 1, 1): 8310 case IP_VERSION(10, 1, 2): 8311 case IP_VERSION(10, 3, 0): 8312 case IP_VERSION(10, 3, 2): 8313 case IP_VERSION(10, 3, 1): 8314 case IP_VERSION(10, 3, 4): 8315 case IP_VERSION(10, 3, 5): 8316 case IP_VERSION(10, 3, 6): 8317 case IP_VERSION(10, 3, 3): 8318 case IP_VERSION(10, 3, 7): 8319 gfx_v10_0_update_gfx_clock_gating(adev, 8320 state == AMD_CG_STATE_GATE); 8321 break; 8322 default: 8323 break; 8324 } 8325 return 0; 8326 } 8327 8328 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8329 { 8330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8331 int data; 8332 8333 /* AMD_CG_SUPPORT_GFX_FGCG */ 8334 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8335 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8336 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8337 8338 /* AMD_CG_SUPPORT_GFX_MGCG */ 8339 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8340 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8341 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8342 8343 /* AMD_CG_SUPPORT_GFX_CGCG */ 8344 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8345 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8346 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8347 8348 /* AMD_CG_SUPPORT_GFX_CGLS */ 8349 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8350 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8351 8352 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8353 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8354 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8355 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8356 8357 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8358 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8359 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8360 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8361 8362 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8363 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8364 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8365 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8366 8367 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8368 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8369 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8370 } 8371 8372 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8373 { 8374 /* gfx10 is 32bit rptr*/ 8375 return *(uint32_t *)ring->rptr_cpu_addr; 8376 } 8377 8378 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8379 { 8380 struct amdgpu_device *adev = ring->adev; 8381 u64 wptr; 8382 8383 /* XXX check if swapping is necessary on BE */ 8384 if (ring->use_doorbell) { 8385 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8386 } else { 8387 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8388 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8389 } 8390 8391 return wptr; 8392 } 8393 8394 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8395 { 8396 struct amdgpu_device *adev = ring->adev; 8397 8398 if (ring->use_doorbell) { 8399 /* XXX check if swapping is necessary on BE */ 8400 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8401 ring->wptr); 8402 WDOORBELL64(ring->doorbell_index, ring->wptr); 8403 } else { 8404 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8405 lower_32_bits(ring->wptr)); 8406 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8407 upper_32_bits(ring->wptr)); 8408 } 8409 } 8410 8411 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8412 { 8413 /* gfx10 hardware is 32bit rptr */ 8414 return *(uint32_t *)ring->rptr_cpu_addr; 8415 } 8416 8417 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8418 { 8419 u64 wptr; 8420 8421 /* XXX check if swapping is necessary on BE */ 8422 if (ring->use_doorbell) 8423 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8424 else 8425 BUG(); 8426 return wptr; 8427 } 8428 8429 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8430 { 8431 struct amdgpu_device *adev = ring->adev; 8432 8433 if (ring->use_doorbell) { 8434 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8435 ring->wptr); 8436 WDOORBELL64(ring->doorbell_index, ring->wptr); 8437 } else { 8438 BUG(); /* only DOORBELL method supported on gfx10 now */ 8439 } 8440 } 8441 8442 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8443 { 8444 struct amdgpu_device *adev = ring->adev; 8445 u32 ref_and_mask, reg_mem_engine; 8446 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8447 8448 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8449 switch (ring->me) { 8450 case 1: 8451 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8452 break; 8453 case 2: 8454 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8455 break; 8456 default: 8457 return; 8458 } 8459 reg_mem_engine = 0; 8460 } else { 8461 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8462 reg_mem_engine = 1; /* pfp */ 8463 } 8464 8465 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8466 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8467 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8468 ref_and_mask, ref_and_mask, 0x20); 8469 } 8470 8471 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8472 struct amdgpu_job *job, 8473 struct amdgpu_ib *ib, 8474 uint32_t flags) 8475 { 8476 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8477 u32 header, control = 0; 8478 8479 if (ib->flags & AMDGPU_IB_FLAG_CE) 8480 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8481 else 8482 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8483 8484 control |= ib->length_dw | (vmid << 24); 8485 8486 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8487 control |= INDIRECT_BUFFER_PRE_ENB(1); 8488 8489 if (flags & AMDGPU_IB_PREEMPTED) 8490 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8491 8492 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8493 gfx_v10_0_ring_emit_de_meta(ring, 8494 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8495 } 8496 8497 amdgpu_ring_write(ring, header); 8498 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8499 amdgpu_ring_write(ring, 8500 #ifdef __BIG_ENDIAN 8501 (2 << 0) | 8502 #endif 8503 lower_32_bits(ib->gpu_addr)); 8504 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8505 amdgpu_ring_write(ring, control); 8506 } 8507 8508 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8509 struct amdgpu_job *job, 8510 struct amdgpu_ib *ib, 8511 uint32_t flags) 8512 { 8513 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8514 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8515 8516 /* Currently, there is a high possibility to get wave ID mismatch 8517 * between ME and GDS, leading to a hw deadlock, because ME generates 8518 * different wave IDs than the GDS expects. This situation happens 8519 * randomly when at least 5 compute pipes use GDS ordered append. 8520 * The wave IDs generated by ME are also wrong after suspend/resume. 8521 * Those are probably bugs somewhere else in the kernel driver. 8522 * 8523 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8524 * GDS to 0 for this ring (me/pipe). 8525 */ 8526 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8527 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8528 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8529 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8530 } 8531 8532 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8533 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8534 amdgpu_ring_write(ring, 8535 #ifdef __BIG_ENDIAN 8536 (2 << 0) | 8537 #endif 8538 lower_32_bits(ib->gpu_addr)); 8539 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8540 amdgpu_ring_write(ring, control); 8541 } 8542 8543 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8544 u64 seq, unsigned int flags) 8545 { 8546 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8547 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8548 8549 /* RELEASE_MEM - flush caches, send int */ 8550 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8551 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8552 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8553 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8554 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8555 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8556 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8557 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8558 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8559 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8560 8561 /* 8562 * the address should be Qword aligned if 64bit write, Dword 8563 * aligned if only send 32bit data low (discard data high) 8564 */ 8565 if (write64bit) 8566 BUG_ON(addr & 0x7); 8567 else 8568 BUG_ON(addr & 0x3); 8569 amdgpu_ring_write(ring, lower_32_bits(addr)); 8570 amdgpu_ring_write(ring, upper_32_bits(addr)); 8571 amdgpu_ring_write(ring, lower_32_bits(seq)); 8572 amdgpu_ring_write(ring, upper_32_bits(seq)); 8573 amdgpu_ring_write(ring, 0); 8574 } 8575 8576 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8577 { 8578 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8579 uint32_t seq = ring->fence_drv.sync_seq; 8580 uint64_t addr = ring->fence_drv.gpu_addr; 8581 8582 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8583 upper_32_bits(addr), seq, 0xffffffff, 4); 8584 } 8585 8586 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8587 uint16_t pasid, uint32_t flush_type, 8588 bool all_hub, uint8_t dst_sel) 8589 { 8590 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8591 amdgpu_ring_write(ring, 8592 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8593 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8594 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8595 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8596 } 8597 8598 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8599 unsigned int vmid, uint64_t pd_addr) 8600 { 8601 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8602 8603 /* compute doesn't have PFP */ 8604 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8605 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8606 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8607 amdgpu_ring_write(ring, 0x0); 8608 } 8609 } 8610 8611 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8612 u64 seq, unsigned int flags) 8613 { 8614 struct amdgpu_device *adev = ring->adev; 8615 8616 /* we only allocate 32bit for each seq wb address */ 8617 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8618 8619 /* write fence seq to the "addr" */ 8620 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8621 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8622 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8623 amdgpu_ring_write(ring, lower_32_bits(addr)); 8624 amdgpu_ring_write(ring, upper_32_bits(addr)); 8625 amdgpu_ring_write(ring, lower_32_bits(seq)); 8626 8627 if (flags & AMDGPU_FENCE_FLAG_INT) { 8628 /* set register to trigger INT */ 8629 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8630 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8631 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8632 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8633 amdgpu_ring_write(ring, 0); 8634 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8635 } 8636 } 8637 8638 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8639 { 8640 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8641 amdgpu_ring_write(ring, 0); 8642 } 8643 8644 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8645 uint32_t flags) 8646 { 8647 uint32_t dw2 = 0; 8648 8649 if (ring->adev->gfx.mcbp) 8650 gfx_v10_0_ring_emit_ce_meta(ring, 8651 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8652 8653 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8654 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8655 /* set load_global_config & load_global_uconfig */ 8656 dw2 |= 0x8001; 8657 /* set load_cs_sh_regs */ 8658 dw2 |= 0x01000000; 8659 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8660 dw2 |= 0x10002; 8661 8662 /* set load_ce_ram if preamble presented */ 8663 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8664 dw2 |= 0x10000000; 8665 } else { 8666 /* still load_ce_ram if this is the first time preamble presented 8667 * although there is no context switch happens. 8668 */ 8669 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8670 dw2 |= 0x10000000; 8671 } 8672 8673 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8674 amdgpu_ring_write(ring, dw2); 8675 amdgpu_ring_write(ring, 0); 8676 } 8677 8678 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8679 uint64_t addr) 8680 { 8681 unsigned int ret; 8682 8683 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8684 amdgpu_ring_write(ring, lower_32_bits(addr)); 8685 amdgpu_ring_write(ring, upper_32_bits(addr)); 8686 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8687 amdgpu_ring_write(ring, 0); 8688 ret = ring->wptr & ring->buf_mask; 8689 /* patch dummy value later */ 8690 amdgpu_ring_write(ring, 0); 8691 8692 return ret; 8693 } 8694 8695 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8696 { 8697 int i, r = 0; 8698 struct amdgpu_device *adev = ring->adev; 8699 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8700 struct amdgpu_ring *kiq_ring = &kiq->ring; 8701 unsigned long flags; 8702 8703 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8704 return -EINVAL; 8705 8706 spin_lock_irqsave(&kiq->ring_lock, flags); 8707 8708 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8709 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8710 return -ENOMEM; 8711 } 8712 8713 /* assert preemption condition */ 8714 amdgpu_ring_set_preempt_cond_exec(ring, false); 8715 8716 /* assert IB preemption, emit the trailing fence */ 8717 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8718 ring->trail_fence_gpu_addr, 8719 ++ring->trail_seq); 8720 amdgpu_ring_commit(kiq_ring); 8721 8722 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8723 8724 /* poll the trailing fence */ 8725 for (i = 0; i < adev->usec_timeout; i++) { 8726 if (ring->trail_seq == 8727 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8728 break; 8729 udelay(1); 8730 } 8731 8732 if (i >= adev->usec_timeout) { 8733 r = -EINVAL; 8734 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8735 } 8736 8737 /* deassert preemption condition */ 8738 amdgpu_ring_set_preempt_cond_exec(ring, true); 8739 return r; 8740 } 8741 8742 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8743 { 8744 struct amdgpu_device *adev = ring->adev; 8745 struct v10_ce_ib_state ce_payload = {0}; 8746 uint64_t offset, ce_payload_gpu_addr; 8747 void *ce_payload_cpu_addr; 8748 int cnt; 8749 8750 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8751 8752 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8753 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8754 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8755 8756 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8757 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8758 WRITE_DATA_DST_SEL(8) | 8759 WR_CONFIRM) | 8760 WRITE_DATA_CACHE_POLICY(0)); 8761 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8762 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8763 8764 if (resume) 8765 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8766 sizeof(ce_payload) >> 2); 8767 else 8768 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8769 sizeof(ce_payload) >> 2); 8770 } 8771 8772 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8773 { 8774 struct amdgpu_device *adev = ring->adev; 8775 struct v10_de_ib_state de_payload = {0}; 8776 uint64_t offset, gds_addr, de_payload_gpu_addr; 8777 void *de_payload_cpu_addr; 8778 int cnt; 8779 8780 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8781 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8782 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8783 8784 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8785 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8786 PAGE_SIZE); 8787 8788 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8789 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8790 8791 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8792 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8793 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8794 WRITE_DATA_DST_SEL(8) | 8795 WR_CONFIRM) | 8796 WRITE_DATA_CACHE_POLICY(0)); 8797 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8798 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8799 8800 if (resume) 8801 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8802 sizeof(de_payload) >> 2); 8803 else 8804 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8805 sizeof(de_payload) >> 2); 8806 } 8807 8808 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8809 bool secure) 8810 { 8811 uint32_t v = secure ? FRAME_TMZ : 0; 8812 8813 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8814 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8815 } 8816 8817 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8818 uint32_t reg_val_offs) 8819 { 8820 struct amdgpu_device *adev = ring->adev; 8821 8822 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8823 amdgpu_ring_write(ring, 0 | /* src: register*/ 8824 (5 << 8) | /* dst: memory */ 8825 (1 << 20)); /* write confirm */ 8826 amdgpu_ring_write(ring, reg); 8827 amdgpu_ring_write(ring, 0); 8828 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8829 reg_val_offs * 4)); 8830 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8831 reg_val_offs * 4)); 8832 } 8833 8834 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8835 uint32_t val) 8836 { 8837 uint32_t cmd = 0; 8838 8839 switch (ring->funcs->type) { 8840 case AMDGPU_RING_TYPE_GFX: 8841 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8842 break; 8843 case AMDGPU_RING_TYPE_KIQ: 8844 cmd = (1 << 16); /* no inc addr */ 8845 break; 8846 default: 8847 cmd = WR_CONFIRM; 8848 break; 8849 } 8850 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8851 amdgpu_ring_write(ring, cmd); 8852 amdgpu_ring_write(ring, reg); 8853 amdgpu_ring_write(ring, 0); 8854 amdgpu_ring_write(ring, val); 8855 } 8856 8857 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8858 uint32_t val, uint32_t mask) 8859 { 8860 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8861 } 8862 8863 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8864 uint32_t reg0, uint32_t reg1, 8865 uint32_t ref, uint32_t mask) 8866 { 8867 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8868 struct amdgpu_device *adev = ring->adev; 8869 bool fw_version_ok = false; 8870 8871 fw_version_ok = adev->gfx.cp_fw_write_wait; 8872 8873 if (fw_version_ok) 8874 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8875 ref, mask, 0x20); 8876 else 8877 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8878 ref, mask); 8879 } 8880 8881 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8882 unsigned int vmid) 8883 { 8884 struct amdgpu_device *adev = ring->adev; 8885 uint32_t value = 0; 8886 8887 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8888 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8889 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8890 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8891 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8892 } 8893 8894 static void 8895 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8896 uint32_t me, uint32_t pipe, 8897 enum amdgpu_interrupt_state state) 8898 { 8899 uint32_t cp_int_cntl, cp_int_cntl_reg; 8900 8901 if (!me) { 8902 switch (pipe) { 8903 case 0: 8904 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8905 break; 8906 case 1: 8907 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8908 break; 8909 default: 8910 DRM_DEBUG("invalid pipe %d\n", pipe); 8911 return; 8912 } 8913 } else { 8914 DRM_DEBUG("invalid me %d\n", me); 8915 return; 8916 } 8917 8918 switch (state) { 8919 case AMDGPU_IRQ_STATE_DISABLE: 8920 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8921 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8922 TIME_STAMP_INT_ENABLE, 0); 8923 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8924 break; 8925 case AMDGPU_IRQ_STATE_ENABLE: 8926 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8927 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8928 TIME_STAMP_INT_ENABLE, 1); 8929 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8930 break; 8931 default: 8932 break; 8933 } 8934 } 8935 8936 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8937 int me, int pipe, 8938 enum amdgpu_interrupt_state state) 8939 { 8940 u32 mec_int_cntl, mec_int_cntl_reg; 8941 8942 /* 8943 * amdgpu controls only the first MEC. That's why this function only 8944 * handles the setting of interrupts for this specific MEC. All other 8945 * pipes' interrupts are set by amdkfd. 8946 */ 8947 8948 if (me == 1) { 8949 switch (pipe) { 8950 case 0: 8951 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8952 break; 8953 case 1: 8954 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8955 break; 8956 case 2: 8957 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8958 break; 8959 case 3: 8960 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8961 break; 8962 default: 8963 DRM_DEBUG("invalid pipe %d\n", pipe); 8964 return; 8965 } 8966 } else { 8967 DRM_DEBUG("invalid me %d\n", me); 8968 return; 8969 } 8970 8971 switch (state) { 8972 case AMDGPU_IRQ_STATE_DISABLE: 8973 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8974 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8975 TIME_STAMP_INT_ENABLE, 0); 8976 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8977 break; 8978 case AMDGPU_IRQ_STATE_ENABLE: 8979 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8980 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8981 TIME_STAMP_INT_ENABLE, 1); 8982 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8983 break; 8984 default: 8985 break; 8986 } 8987 } 8988 8989 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8990 struct amdgpu_irq_src *src, 8991 unsigned int type, 8992 enum amdgpu_interrupt_state state) 8993 { 8994 switch (type) { 8995 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8996 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8997 break; 8998 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8999 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9000 break; 9001 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9002 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9003 break; 9004 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9005 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9006 break; 9007 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9008 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9009 break; 9010 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9011 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9012 break; 9013 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9014 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9015 break; 9016 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9017 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9018 break; 9019 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9020 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9021 break; 9022 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9023 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9024 break; 9025 default: 9026 break; 9027 } 9028 return 0; 9029 } 9030 9031 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9032 struct amdgpu_irq_src *source, 9033 struct amdgpu_iv_entry *entry) 9034 { 9035 int i; 9036 u8 me_id, pipe_id, queue_id; 9037 struct amdgpu_ring *ring; 9038 9039 DRM_DEBUG("IH: CP EOP\n"); 9040 9041 me_id = (entry->ring_id & 0x0c) >> 2; 9042 pipe_id = (entry->ring_id & 0x03) >> 0; 9043 queue_id = (entry->ring_id & 0x70) >> 4; 9044 9045 switch (me_id) { 9046 case 0: 9047 if (pipe_id == 0) 9048 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9049 else 9050 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9051 break; 9052 case 1: 9053 case 2: 9054 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9055 ring = &adev->gfx.compute_ring[i]; 9056 /* Per-queue interrupt is supported for MEC starting from VI. 9057 * The interrupt can only be enabled/disabled per pipe instead 9058 * of per queue. 9059 */ 9060 if ((ring->me == me_id) && 9061 (ring->pipe == pipe_id) && 9062 (ring->queue == queue_id)) 9063 amdgpu_fence_process(ring); 9064 } 9065 break; 9066 } 9067 9068 return 0; 9069 } 9070 9071 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9072 struct amdgpu_irq_src *source, 9073 unsigned int type, 9074 enum amdgpu_interrupt_state state) 9075 { 9076 switch (state) { 9077 case AMDGPU_IRQ_STATE_DISABLE: 9078 case AMDGPU_IRQ_STATE_ENABLE: 9079 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9080 PRIV_REG_INT_ENABLE, 9081 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9082 break; 9083 default: 9084 break; 9085 } 9086 9087 return 0; 9088 } 9089 9090 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9091 struct amdgpu_irq_src *source, 9092 unsigned int type, 9093 enum amdgpu_interrupt_state state) 9094 { 9095 switch (state) { 9096 case AMDGPU_IRQ_STATE_DISABLE: 9097 case AMDGPU_IRQ_STATE_ENABLE: 9098 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9099 PRIV_INSTR_INT_ENABLE, 9100 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9101 break; 9102 default: 9103 break; 9104 } 9105 9106 return 0; 9107 } 9108 9109 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9110 struct amdgpu_iv_entry *entry) 9111 { 9112 u8 me_id, pipe_id, queue_id; 9113 struct amdgpu_ring *ring; 9114 int i; 9115 9116 me_id = (entry->ring_id & 0x0c) >> 2; 9117 pipe_id = (entry->ring_id & 0x03) >> 0; 9118 queue_id = (entry->ring_id & 0x70) >> 4; 9119 9120 switch (me_id) { 9121 case 0: 9122 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9123 ring = &adev->gfx.gfx_ring[i]; 9124 /* we only enabled 1 gfx queue per pipe for now */ 9125 if (ring->me == me_id && ring->pipe == pipe_id) 9126 drm_sched_fault(&ring->sched); 9127 } 9128 break; 9129 case 1: 9130 case 2: 9131 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9132 ring = &adev->gfx.compute_ring[i]; 9133 if (ring->me == me_id && ring->pipe == pipe_id && 9134 ring->queue == queue_id) 9135 drm_sched_fault(&ring->sched); 9136 } 9137 break; 9138 default: 9139 BUG(); 9140 } 9141 } 9142 9143 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9144 struct amdgpu_irq_src *source, 9145 struct amdgpu_iv_entry *entry) 9146 { 9147 DRM_ERROR("Illegal register access in command stream\n"); 9148 gfx_v10_0_handle_priv_fault(adev, entry); 9149 return 0; 9150 } 9151 9152 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9153 struct amdgpu_irq_src *source, 9154 struct amdgpu_iv_entry *entry) 9155 { 9156 DRM_ERROR("Illegal instruction in command stream\n"); 9157 gfx_v10_0_handle_priv_fault(adev, entry); 9158 return 0; 9159 } 9160 9161 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9162 struct amdgpu_irq_src *src, 9163 unsigned int type, 9164 enum amdgpu_interrupt_state state) 9165 { 9166 uint32_t tmp, target; 9167 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9168 9169 if (ring->me == 1) 9170 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9171 else 9172 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9173 target += ring->pipe; 9174 9175 switch (type) { 9176 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9177 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9178 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9179 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9180 GENERIC2_INT_ENABLE, 0); 9181 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9182 9183 tmp = RREG32_SOC15_IP(GC, target); 9184 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9185 GENERIC2_INT_ENABLE, 0); 9186 WREG32_SOC15_IP(GC, target, tmp); 9187 } else { 9188 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9189 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9190 GENERIC2_INT_ENABLE, 1); 9191 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9192 9193 tmp = RREG32_SOC15_IP(GC, target); 9194 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9195 GENERIC2_INT_ENABLE, 1); 9196 WREG32_SOC15_IP(GC, target, tmp); 9197 } 9198 break; 9199 default: 9200 BUG(); /* kiq only support GENERIC2_INT now */ 9201 break; 9202 } 9203 return 0; 9204 } 9205 9206 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9207 struct amdgpu_irq_src *source, 9208 struct amdgpu_iv_entry *entry) 9209 { 9210 u8 me_id, pipe_id, queue_id; 9211 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9212 9213 me_id = (entry->ring_id & 0x0c) >> 2; 9214 pipe_id = (entry->ring_id & 0x03) >> 0; 9215 queue_id = (entry->ring_id & 0x70) >> 4; 9216 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9217 me_id, pipe_id, queue_id); 9218 9219 amdgpu_fence_process(ring); 9220 return 0; 9221 } 9222 9223 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9224 { 9225 const unsigned int gcr_cntl = 9226 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9227 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9228 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9229 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9230 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9231 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9232 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9233 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9234 9235 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9236 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9237 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9238 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9239 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9240 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9241 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9242 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9243 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9244 } 9245 9246 static void gfx_v10_ip_print(void *handle, struct drm_printer *p) 9247 { 9248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9249 uint32_t i, j, k, reg, index = 0; 9250 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9251 9252 if (!adev->gfx.ip_dump_core) 9253 return; 9254 9255 for (i = 0; i < reg_count; i++) 9256 drm_printf(p, "%-50s \t 0x%08x\n", 9257 gc_reg_list_10_1[i].reg_name, 9258 adev->gfx.ip_dump_core[i]); 9259 9260 /* print compute queue registers for all instances */ 9261 if (!adev->gfx.ip_dump_compute_queues) 9262 return; 9263 9264 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9265 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9266 adev->gfx.mec.num_mec, 9267 adev->gfx.mec.num_pipe_per_mec, 9268 adev->gfx.mec.num_queue_per_pipe); 9269 9270 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9271 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9272 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9273 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9274 for (reg = 0; reg < reg_count; reg++) { 9275 drm_printf(p, "%-50s \t 0x%08x\n", 9276 gc_cp_reg_list_10[reg].reg_name, 9277 adev->gfx.ip_dump_compute_queues[index + reg]); 9278 } 9279 index += reg_count; 9280 } 9281 } 9282 } 9283 9284 /* print gfx queue registers for all instances */ 9285 if (!adev->gfx.ip_dump_gfx_queues) 9286 return; 9287 9288 index = 0; 9289 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9290 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9291 adev->gfx.me.num_me, 9292 adev->gfx.me.num_pipe_per_me, 9293 adev->gfx.me.num_queue_per_pipe); 9294 9295 for (i = 0; i < adev->gfx.me.num_me; i++) { 9296 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9297 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9298 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9299 for (reg = 0; reg < reg_count; reg++) { 9300 drm_printf(p, "%-50s \t 0x%08x\n", 9301 gc_gfx_queue_reg_list_10[reg].reg_name, 9302 adev->gfx.ip_dump_gfx_queues[index + reg]); 9303 } 9304 index += reg_count; 9305 } 9306 } 9307 } 9308 } 9309 9310 static void gfx_v10_ip_dump(void *handle) 9311 { 9312 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9313 uint32_t i, j, k, reg, index = 0; 9314 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9315 9316 if (!adev->gfx.ip_dump_core) 9317 return; 9318 9319 amdgpu_gfx_off_ctrl(adev, false); 9320 for (i = 0; i < reg_count; i++) 9321 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9322 amdgpu_gfx_off_ctrl(adev, true); 9323 9324 /* dump compute queue registers for all instances */ 9325 if (!adev->gfx.ip_dump_compute_queues) 9326 return; 9327 9328 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9329 amdgpu_gfx_off_ctrl(adev, false); 9330 mutex_lock(&adev->srbm_mutex); 9331 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9332 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9333 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9334 /* ME0 is for GFX so start from 1 for CP */ 9335 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9336 9337 for (reg = 0; reg < reg_count; reg++) { 9338 adev->gfx.ip_dump_compute_queues[index + reg] = 9339 RREG32(SOC15_REG_ENTRY_OFFSET( 9340 gc_cp_reg_list_10[reg])); 9341 } 9342 index += reg_count; 9343 } 9344 } 9345 } 9346 nv_grbm_select(adev, 0, 0, 0, 0); 9347 mutex_unlock(&adev->srbm_mutex); 9348 amdgpu_gfx_off_ctrl(adev, true); 9349 9350 /* dump gfx queue registers for all instances */ 9351 if (!adev->gfx.ip_dump_gfx_queues) 9352 return; 9353 9354 index = 0; 9355 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9356 amdgpu_gfx_off_ctrl(adev, false); 9357 mutex_lock(&adev->srbm_mutex); 9358 for (i = 0; i < adev->gfx.me.num_me; i++) { 9359 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9360 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9361 nv_grbm_select(adev, i, j, k, 0); 9362 9363 for (reg = 0; reg < reg_count; reg++) { 9364 adev->gfx.ip_dump_gfx_queues[index + reg] = 9365 RREG32(SOC15_REG_ENTRY_OFFSET( 9366 gc_gfx_queue_reg_list_10[reg])); 9367 } 9368 index += reg_count; 9369 } 9370 } 9371 } 9372 nv_grbm_select(adev, 0, 0, 0, 0); 9373 mutex_unlock(&adev->srbm_mutex); 9374 amdgpu_gfx_off_ctrl(adev, true); 9375 } 9376 9377 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9378 .name = "gfx_v10_0", 9379 .early_init = gfx_v10_0_early_init, 9380 .late_init = gfx_v10_0_late_init, 9381 .sw_init = gfx_v10_0_sw_init, 9382 .sw_fini = gfx_v10_0_sw_fini, 9383 .hw_init = gfx_v10_0_hw_init, 9384 .hw_fini = gfx_v10_0_hw_fini, 9385 .suspend = gfx_v10_0_suspend, 9386 .resume = gfx_v10_0_resume, 9387 .is_idle = gfx_v10_0_is_idle, 9388 .wait_for_idle = gfx_v10_0_wait_for_idle, 9389 .soft_reset = gfx_v10_0_soft_reset, 9390 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9391 .set_powergating_state = gfx_v10_0_set_powergating_state, 9392 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9393 .dump_ip_state = gfx_v10_ip_dump, 9394 .print_ip_state = gfx_v10_ip_print, 9395 }; 9396 9397 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9398 .type = AMDGPU_RING_TYPE_GFX, 9399 .align_mask = 0xff, 9400 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9401 .support_64bit_ptrs = true, 9402 .secure_submission_supported = true, 9403 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9404 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9405 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9406 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9407 5 + /* COND_EXEC */ 9408 7 + /* PIPELINE_SYNC */ 9409 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9410 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9411 4 + /* VM_FLUSH */ 9412 8 + /* FENCE for VM_FLUSH */ 9413 20 + /* GDS switch */ 9414 4 + /* double SWITCH_BUFFER, 9415 * the first COND_EXEC jump to the place 9416 * just prior to this double SWITCH_BUFFER 9417 */ 9418 5 + /* COND_EXEC */ 9419 7 + /* HDP_flush */ 9420 4 + /* VGT_flush */ 9421 14 + /* CE_META */ 9422 31 + /* DE_META */ 9423 3 + /* CNTX_CTRL */ 9424 5 + /* HDP_INVL */ 9425 8 + 8 + /* FENCE x2 */ 9426 2 + /* SWITCH_BUFFER */ 9427 8, /* gfx_v10_0_emit_mem_sync */ 9428 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9429 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9430 .emit_fence = gfx_v10_0_ring_emit_fence, 9431 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9432 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9433 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9434 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9435 .test_ring = gfx_v10_0_ring_test_ring, 9436 .test_ib = gfx_v10_0_ring_test_ib, 9437 .insert_nop = amdgpu_ring_insert_nop, 9438 .pad_ib = amdgpu_ring_generic_pad_ib, 9439 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9440 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9441 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9442 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9443 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9444 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9445 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9446 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9447 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9448 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9449 }; 9450 9451 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9452 .type = AMDGPU_RING_TYPE_COMPUTE, 9453 .align_mask = 0xff, 9454 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9455 .support_64bit_ptrs = true, 9456 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9457 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9458 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9459 .emit_frame_size = 9460 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9461 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9462 5 + /* hdp invalidate */ 9463 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9464 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9465 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9466 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9467 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9468 8, /* gfx_v10_0_emit_mem_sync */ 9469 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9470 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9471 .emit_fence = gfx_v10_0_ring_emit_fence, 9472 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9473 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9474 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9475 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9476 .test_ring = gfx_v10_0_ring_test_ring, 9477 .test_ib = gfx_v10_0_ring_test_ib, 9478 .insert_nop = amdgpu_ring_insert_nop, 9479 .pad_ib = amdgpu_ring_generic_pad_ib, 9480 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9481 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9482 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9483 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9484 }; 9485 9486 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9487 .type = AMDGPU_RING_TYPE_KIQ, 9488 .align_mask = 0xff, 9489 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9490 .support_64bit_ptrs = true, 9491 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9492 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9493 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9494 .emit_frame_size = 9495 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9496 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9497 5 + /*hdp invalidate */ 9498 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9499 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9500 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9501 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9502 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9503 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9504 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9505 .test_ring = gfx_v10_0_ring_test_ring, 9506 .test_ib = gfx_v10_0_ring_test_ib, 9507 .insert_nop = amdgpu_ring_insert_nop, 9508 .pad_ib = amdgpu_ring_generic_pad_ib, 9509 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9510 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9511 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9512 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9513 }; 9514 9515 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9516 { 9517 int i; 9518 9519 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9520 9521 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9522 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9523 9524 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9525 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9526 } 9527 9528 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9529 .set = gfx_v10_0_set_eop_interrupt_state, 9530 .process = gfx_v10_0_eop_irq, 9531 }; 9532 9533 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9534 .set = gfx_v10_0_set_priv_reg_fault_state, 9535 .process = gfx_v10_0_priv_reg_irq, 9536 }; 9537 9538 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9539 .set = gfx_v10_0_set_priv_inst_fault_state, 9540 .process = gfx_v10_0_priv_inst_irq, 9541 }; 9542 9543 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9544 .set = gfx_v10_0_kiq_set_interrupt_state, 9545 .process = gfx_v10_0_kiq_irq, 9546 }; 9547 9548 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9549 { 9550 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9551 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9552 9553 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9554 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9555 9556 adev->gfx.priv_reg_irq.num_types = 1; 9557 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9558 9559 adev->gfx.priv_inst_irq.num_types = 1; 9560 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9561 } 9562 9563 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9564 { 9565 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9566 case IP_VERSION(10, 1, 10): 9567 case IP_VERSION(10, 1, 1): 9568 case IP_VERSION(10, 1, 3): 9569 case IP_VERSION(10, 1, 4): 9570 case IP_VERSION(10, 3, 2): 9571 case IP_VERSION(10, 3, 1): 9572 case IP_VERSION(10, 3, 4): 9573 case IP_VERSION(10, 3, 5): 9574 case IP_VERSION(10, 3, 6): 9575 case IP_VERSION(10, 3, 3): 9576 case IP_VERSION(10, 3, 7): 9577 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9578 break; 9579 case IP_VERSION(10, 1, 2): 9580 case IP_VERSION(10, 3, 0): 9581 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9582 break; 9583 default: 9584 break; 9585 } 9586 } 9587 9588 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9589 { 9590 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9591 adev->gfx.config.max_sh_per_se * 9592 adev->gfx.config.max_shader_engines; 9593 9594 adev->gds.gds_size = 0x10000; 9595 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9596 adev->gds.gws_size = 64; 9597 adev->gds.oa_size = 16; 9598 } 9599 9600 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9601 { 9602 /* set gfx eng mqd */ 9603 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9604 sizeof(struct v10_gfx_mqd); 9605 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9606 gfx_v10_0_gfx_mqd_init; 9607 /* set compute eng mqd */ 9608 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9609 sizeof(struct v10_compute_mqd); 9610 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9611 gfx_v10_0_compute_mqd_init; 9612 } 9613 9614 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9615 u32 bitmap) 9616 { 9617 u32 data; 9618 9619 if (!bitmap) 9620 return; 9621 9622 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9623 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9624 9625 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9626 } 9627 9628 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9629 { 9630 u32 disabled_mask = 9631 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9632 u32 efuse_setting = 0; 9633 u32 vbios_setting = 0; 9634 9635 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9636 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9637 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9638 9639 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9640 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9641 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9642 9643 disabled_mask |= efuse_setting | vbios_setting; 9644 9645 return (~disabled_mask); 9646 } 9647 9648 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9649 { 9650 u32 wgp_idx, wgp_active_bitmap; 9651 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9652 9653 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9654 cu_active_bitmap = 0; 9655 9656 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9657 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9658 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9659 if (wgp_active_bitmap & (1 << wgp_idx)) 9660 cu_active_bitmap |= cu_bitmap_per_wgp; 9661 } 9662 9663 return cu_active_bitmap; 9664 } 9665 9666 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9667 struct amdgpu_cu_info *cu_info) 9668 { 9669 int i, j, k, counter, active_cu_number = 0; 9670 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9671 unsigned int disable_masks[4 * 2]; 9672 9673 if (!adev || !cu_info) 9674 return -EINVAL; 9675 9676 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9677 9678 mutex_lock(&adev->grbm_idx_mutex); 9679 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9680 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9681 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9682 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 9683 IP_VERSION(10, 3, 0)) || 9684 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9685 IP_VERSION(10, 3, 3)) || 9686 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9687 IP_VERSION(10, 3, 6)) || 9688 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9689 IP_VERSION(10, 3, 7))) && 9690 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9691 continue; 9692 mask = 1; 9693 ao_bitmap = 0; 9694 counter = 0; 9695 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9696 if (i < 4 && j < 2) 9697 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9698 adev, disable_masks[i * 2 + j]); 9699 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9700 cu_info->bitmap[0][i][j] = bitmap; 9701 9702 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9703 if (bitmap & mask) { 9704 if (counter < adev->gfx.config.max_cu_per_sh) 9705 ao_bitmap |= mask; 9706 counter++; 9707 } 9708 mask <<= 1; 9709 } 9710 active_cu_number += counter; 9711 if (i < 2 && j < 2) 9712 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9713 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9714 } 9715 } 9716 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9717 mutex_unlock(&adev->grbm_idx_mutex); 9718 9719 cu_info->number = active_cu_number; 9720 cu_info->ao_cu_mask = ao_cu_mask; 9721 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9722 9723 return 0; 9724 } 9725 9726 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9727 { 9728 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9729 9730 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9731 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9732 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9733 9734 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9735 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9736 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9737 9738 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9739 adev->gfx.config.max_shader_engines); 9740 disabled_sa = efuse_setting | vbios_setting; 9741 disabled_sa &= max_sa_mask; 9742 9743 return disabled_sa; 9744 } 9745 9746 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9747 { 9748 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9749 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9750 9751 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9752 9753 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9754 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9755 max_shader_engines = adev->gfx.config.max_shader_engines; 9756 9757 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9758 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9759 disabled_sa_per_se &= max_sa_per_se_mask; 9760 if (disabled_sa_per_se == max_sa_per_se_mask) { 9761 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9762 break; 9763 } 9764 } 9765 } 9766 9767 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9768 { 9769 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9770 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9771 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9772 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9773 9774 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9775 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9776 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9777 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9778 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9779 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9780 9781 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9782 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9783 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9784 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9785 9786 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9787 9788 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9789 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9790 } 9791 9792 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9793 .type = AMD_IP_BLOCK_TYPE_GFX, 9794 .major = 10, 9795 .minor = 0, 9796 .rev = 0, 9797 .funcs = &gfx_v10_0_ip_funcs, 9798 }; 9799