1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 377 /* SE status registers */ 378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 382 }; 383 384 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 425 }; 426 427 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 428 /* Pending on emulation bring up */ 429 }; 430 431 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1484 }; 1485 1486 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1525 }; 1526 1527 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1570 }; 1571 1572 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1573 /* Pending on emulation bring up */ 1574 }; 1575 1576 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2197 }; 2198 2199 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2200 /* Pending on emulation bring up */ 2201 }; 2202 2203 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3256 }; 3257 3258 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3302 }; 3303 3304 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3305 /* Pending on emulation bring up */ 3306 }; 3307 3308 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3350 3351 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3353 }; 3354 3355 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3380 3381 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3383 }; 3384 3385 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3406 }; 3407 3408 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3445 }; 3446 3447 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3480 }; 3481 3482 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3517 }; 3518 3519 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3542 }; 3543 3544 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3567 }; 3568 3569 #define DEFAULT_SH_MEM_CONFIG \ 3570 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3571 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3572 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3573 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3574 3575 /* TODO: pending on golden setting value of gb address config */ 3576 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3577 3578 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3579 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3580 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3581 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3582 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3583 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3584 struct amdgpu_cu_info *cu_info); 3585 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3586 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3587 u32 sh_num, u32 instance, int xcc_id); 3588 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3589 3590 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3591 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3592 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3593 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3594 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3595 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3596 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3597 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3598 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3599 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3600 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3601 uint16_t pasid, uint32_t flush_type, 3602 bool all_hub, uint8_t dst_sel); 3603 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3604 unsigned int vmid); 3605 3606 static int gfx_v10_0_set_powergating_state(void *handle, 3607 enum amd_powergating_state state); 3608 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3609 { 3610 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3611 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3612 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3613 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3614 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3615 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3616 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3617 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3618 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3619 } 3620 3621 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3622 struct amdgpu_ring *ring) 3623 { 3624 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3625 uint64_t wptr_addr = ring->wptr_gpu_addr; 3626 uint32_t eng_sel = 0; 3627 3628 switch (ring->funcs->type) { 3629 case AMDGPU_RING_TYPE_COMPUTE: 3630 eng_sel = 0; 3631 break; 3632 case AMDGPU_RING_TYPE_GFX: 3633 eng_sel = 4; 3634 break; 3635 case AMDGPU_RING_TYPE_MES: 3636 eng_sel = 5; 3637 break; 3638 default: 3639 WARN_ON(1); 3640 } 3641 3642 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3643 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3644 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3645 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3646 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3647 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3648 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3649 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3650 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3651 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3652 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3653 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3654 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3655 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3656 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3657 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3658 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3659 } 3660 3661 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3662 struct amdgpu_ring *ring, 3663 enum amdgpu_unmap_queues_action action, 3664 u64 gpu_addr, u64 seq) 3665 { 3666 struct amdgpu_device *adev = kiq_ring->adev; 3667 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3668 3669 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3670 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3671 return; 3672 } 3673 3674 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3675 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3676 PACKET3_UNMAP_QUEUES_ACTION(action) | 3677 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3678 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3679 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3680 amdgpu_ring_write(kiq_ring, 3681 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3682 3683 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3684 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3685 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3686 amdgpu_ring_write(kiq_ring, seq); 3687 } else { 3688 amdgpu_ring_write(kiq_ring, 0); 3689 amdgpu_ring_write(kiq_ring, 0); 3690 amdgpu_ring_write(kiq_ring, 0); 3691 } 3692 } 3693 3694 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3695 struct amdgpu_ring *ring, 3696 u64 addr, 3697 u64 seq) 3698 { 3699 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3700 3701 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3702 amdgpu_ring_write(kiq_ring, 3703 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3704 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3705 PACKET3_QUERY_STATUS_COMMAND(2)); 3706 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3707 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3708 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3709 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3710 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3711 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3712 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3713 } 3714 3715 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3716 uint16_t pasid, uint32_t flush_type, 3717 bool all_hub) 3718 { 3719 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3720 } 3721 3722 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3723 .kiq_set_resources = gfx10_kiq_set_resources, 3724 .kiq_map_queues = gfx10_kiq_map_queues, 3725 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3726 .kiq_query_status = gfx10_kiq_query_status, 3727 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3728 .set_resources_size = 8, 3729 .map_queues_size = 7, 3730 .unmap_queues_size = 6, 3731 .query_status_size = 7, 3732 .invalidate_tlbs_size = 2, 3733 }; 3734 3735 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3736 { 3737 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3738 } 3739 3740 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3741 { 3742 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3743 case IP_VERSION(10, 1, 10): 3744 soc15_program_register_sequence(adev, 3745 golden_settings_gc_rlc_spm_10_0_nv10, 3746 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3747 break; 3748 case IP_VERSION(10, 1, 1): 3749 soc15_program_register_sequence(adev, 3750 golden_settings_gc_rlc_spm_10_1_nv14, 3751 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3752 break; 3753 case IP_VERSION(10, 1, 2): 3754 soc15_program_register_sequence(adev, 3755 golden_settings_gc_rlc_spm_10_1_2_nv12, 3756 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3757 break; 3758 default: 3759 break; 3760 } 3761 } 3762 3763 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3764 { 3765 if (amdgpu_sriov_vf(adev)) 3766 return; 3767 3768 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3769 case IP_VERSION(10, 1, 10): 3770 soc15_program_register_sequence(adev, 3771 golden_settings_gc_10_1, 3772 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3773 soc15_program_register_sequence(adev, 3774 golden_settings_gc_10_0_nv10, 3775 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3776 break; 3777 case IP_VERSION(10, 1, 1): 3778 soc15_program_register_sequence(adev, 3779 golden_settings_gc_10_1_1, 3780 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3781 soc15_program_register_sequence(adev, 3782 golden_settings_gc_10_1_nv14, 3783 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3784 break; 3785 case IP_VERSION(10, 1, 2): 3786 soc15_program_register_sequence(adev, 3787 golden_settings_gc_10_1_2, 3788 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3789 soc15_program_register_sequence(adev, 3790 golden_settings_gc_10_1_2_nv12, 3791 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3792 break; 3793 case IP_VERSION(10, 3, 0): 3794 soc15_program_register_sequence(adev, 3795 golden_settings_gc_10_3, 3796 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3797 soc15_program_register_sequence(adev, 3798 golden_settings_gc_10_3_sienna_cichlid, 3799 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3800 break; 3801 case IP_VERSION(10, 3, 2): 3802 soc15_program_register_sequence(adev, 3803 golden_settings_gc_10_3_2, 3804 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3805 break; 3806 case IP_VERSION(10, 3, 1): 3807 soc15_program_register_sequence(adev, 3808 golden_settings_gc_10_3_vangogh, 3809 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3810 break; 3811 case IP_VERSION(10, 3, 3): 3812 soc15_program_register_sequence(adev, 3813 golden_settings_gc_10_3_3, 3814 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3815 break; 3816 case IP_VERSION(10, 3, 4): 3817 soc15_program_register_sequence(adev, 3818 golden_settings_gc_10_3_4, 3819 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3820 break; 3821 case IP_VERSION(10, 3, 5): 3822 soc15_program_register_sequence(adev, 3823 golden_settings_gc_10_3_5, 3824 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3825 break; 3826 case IP_VERSION(10, 1, 3): 3827 case IP_VERSION(10, 1, 4): 3828 soc15_program_register_sequence(adev, 3829 golden_settings_gc_10_0_cyan_skillfish, 3830 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3831 break; 3832 case IP_VERSION(10, 3, 6): 3833 soc15_program_register_sequence(adev, 3834 golden_settings_gc_10_3_6, 3835 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3836 break; 3837 case IP_VERSION(10, 3, 7): 3838 soc15_program_register_sequence(adev, 3839 golden_settings_gc_10_3_7, 3840 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3841 break; 3842 default: 3843 break; 3844 } 3845 gfx_v10_0_init_spm_golden_registers(adev); 3846 } 3847 3848 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3849 bool wc, uint32_t reg, uint32_t val) 3850 { 3851 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3852 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3853 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3854 amdgpu_ring_write(ring, reg); 3855 amdgpu_ring_write(ring, 0); 3856 amdgpu_ring_write(ring, val); 3857 } 3858 3859 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3860 int mem_space, int opt, uint32_t addr0, 3861 uint32_t addr1, uint32_t ref, uint32_t mask, 3862 uint32_t inv) 3863 { 3864 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3865 amdgpu_ring_write(ring, 3866 /* memory (1) or register (0) */ 3867 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3868 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3869 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3870 WAIT_REG_MEM_ENGINE(eng_sel))); 3871 3872 if (mem_space) 3873 BUG_ON(addr0 & 0x3); /* Dword align */ 3874 amdgpu_ring_write(ring, addr0); 3875 amdgpu_ring_write(ring, addr1); 3876 amdgpu_ring_write(ring, ref); 3877 amdgpu_ring_write(ring, mask); 3878 amdgpu_ring_write(ring, inv); /* poll interval */ 3879 } 3880 3881 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3882 { 3883 struct amdgpu_device *adev = ring->adev; 3884 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3885 uint32_t tmp = 0; 3886 unsigned int i; 3887 int r; 3888 3889 WREG32(scratch, 0xCAFEDEAD); 3890 r = amdgpu_ring_alloc(ring, 3); 3891 if (r) { 3892 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3893 ring->idx, r); 3894 return r; 3895 } 3896 3897 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3898 amdgpu_ring_write(ring, scratch - 3899 PACKET3_SET_UCONFIG_REG_START); 3900 amdgpu_ring_write(ring, 0xDEADBEEF); 3901 amdgpu_ring_commit(ring); 3902 3903 for (i = 0; i < adev->usec_timeout; i++) { 3904 tmp = RREG32(scratch); 3905 if (tmp == 0xDEADBEEF) 3906 break; 3907 if (amdgpu_emu_mode == 1) 3908 msleep(1); 3909 else 3910 udelay(1); 3911 } 3912 3913 if (i >= adev->usec_timeout) 3914 r = -ETIMEDOUT; 3915 3916 return r; 3917 } 3918 3919 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3920 { 3921 struct amdgpu_device *adev = ring->adev; 3922 struct amdgpu_ib ib; 3923 struct dma_fence *f = NULL; 3924 unsigned int index; 3925 uint64_t gpu_addr; 3926 volatile uint32_t *cpu_ptr; 3927 long r; 3928 3929 memset(&ib, 0, sizeof(ib)); 3930 3931 if (ring->is_mes_queue) { 3932 uint32_t padding, offset; 3933 3934 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3935 padding = amdgpu_mes_ctx_get_offs(ring, 3936 AMDGPU_MES_CTX_PADDING_OFFS); 3937 3938 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3939 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3940 3941 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3942 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3943 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3944 } else { 3945 r = amdgpu_device_wb_get(adev, &index); 3946 if (r) 3947 return r; 3948 3949 gpu_addr = adev->wb.gpu_addr + (index * 4); 3950 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3951 cpu_ptr = &adev->wb.wb[index]; 3952 3953 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3954 if (r) { 3955 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3956 goto err1; 3957 } 3958 } 3959 3960 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3961 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3962 ib.ptr[2] = lower_32_bits(gpu_addr); 3963 ib.ptr[3] = upper_32_bits(gpu_addr); 3964 ib.ptr[4] = 0xDEADBEEF; 3965 ib.length_dw = 5; 3966 3967 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3968 if (r) 3969 goto err2; 3970 3971 r = dma_fence_wait_timeout(f, false, timeout); 3972 if (r == 0) { 3973 r = -ETIMEDOUT; 3974 goto err2; 3975 } else if (r < 0) { 3976 goto err2; 3977 } 3978 3979 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3980 r = 0; 3981 else 3982 r = -EINVAL; 3983 err2: 3984 if (!ring->is_mes_queue) 3985 amdgpu_ib_free(adev, &ib, NULL); 3986 dma_fence_put(f); 3987 err1: 3988 if (!ring->is_mes_queue) 3989 amdgpu_device_wb_free(adev, index); 3990 return r; 3991 } 3992 3993 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3994 { 3995 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3996 amdgpu_ucode_release(&adev->gfx.me_fw); 3997 amdgpu_ucode_release(&adev->gfx.ce_fw); 3998 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3999 amdgpu_ucode_release(&adev->gfx.mec_fw); 4000 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4001 4002 kfree(adev->gfx.rlc.register_list_format); 4003 } 4004 4005 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4006 { 4007 adev->gfx.cp_fw_write_wait = false; 4008 4009 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4010 case IP_VERSION(10, 1, 10): 4011 case IP_VERSION(10, 1, 2): 4012 case IP_VERSION(10, 1, 1): 4013 case IP_VERSION(10, 1, 3): 4014 case IP_VERSION(10, 1, 4): 4015 if ((adev->gfx.me_fw_version >= 0x00000046) && 4016 (adev->gfx.me_feature_version >= 27) && 4017 (adev->gfx.pfp_fw_version >= 0x00000068) && 4018 (adev->gfx.pfp_feature_version >= 27) && 4019 (adev->gfx.mec_fw_version >= 0x0000005b) && 4020 (adev->gfx.mec_feature_version >= 27)) 4021 adev->gfx.cp_fw_write_wait = true; 4022 break; 4023 case IP_VERSION(10, 3, 0): 4024 case IP_VERSION(10, 3, 2): 4025 case IP_VERSION(10, 3, 1): 4026 case IP_VERSION(10, 3, 4): 4027 case IP_VERSION(10, 3, 5): 4028 case IP_VERSION(10, 3, 6): 4029 case IP_VERSION(10, 3, 3): 4030 case IP_VERSION(10, 3, 7): 4031 adev->gfx.cp_fw_write_wait = true; 4032 break; 4033 default: 4034 break; 4035 } 4036 4037 if (!adev->gfx.cp_fw_write_wait) 4038 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4039 } 4040 4041 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4042 { 4043 bool ret = false; 4044 4045 switch (adev->pdev->revision) { 4046 case 0xc2: 4047 case 0xc3: 4048 ret = true; 4049 break; 4050 default: 4051 ret = false; 4052 break; 4053 } 4054 4055 return ret; 4056 } 4057 4058 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4059 { 4060 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4061 case IP_VERSION(10, 1, 10): 4062 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4063 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4064 break; 4065 default: 4066 break; 4067 } 4068 } 4069 4070 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4071 { 4072 char fw_name[53]; 4073 char ucode_prefix[30]; 4074 const char *wks = ""; 4075 int err; 4076 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4077 uint16_t version_major; 4078 uint16_t version_minor; 4079 4080 DRM_DEBUG("\n"); 4081 4082 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4083 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4084 wks = "_wks"; 4085 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4086 4087 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4088 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 4089 if (err) 4090 goto out; 4091 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4092 4093 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4094 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 4095 if (err) 4096 goto out; 4097 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4098 4099 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4100 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 4101 if (err) 4102 goto out; 4103 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4104 4105 if (!amdgpu_sriov_vf(adev)) { 4106 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4107 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4108 if (err) 4109 goto out; 4110 4111 /* don't validate this firmware. There are apparently firmwares 4112 * in the wild with incorrect size in the header 4113 */ 4114 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4115 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4116 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4117 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4118 if (err) 4119 goto out; 4120 } 4121 4122 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4123 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4124 if (err) 4125 goto out; 4126 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4127 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4128 4129 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4130 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4131 if (!err) { 4132 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4133 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4134 } else { 4135 err = 0; 4136 adev->gfx.mec2_fw = NULL; 4137 } 4138 4139 gfx_v10_0_check_fw_write_wait(adev); 4140 out: 4141 if (err) { 4142 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4143 amdgpu_ucode_release(&adev->gfx.me_fw); 4144 amdgpu_ucode_release(&adev->gfx.ce_fw); 4145 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4146 amdgpu_ucode_release(&adev->gfx.mec_fw); 4147 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4148 } 4149 4150 gfx_v10_0_check_gfxoff_flag(adev); 4151 4152 return err; 4153 } 4154 4155 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4156 { 4157 u32 count = 0; 4158 const struct cs_section_def *sect = NULL; 4159 const struct cs_extent_def *ext = NULL; 4160 4161 /* begin clear state */ 4162 count += 2; 4163 /* context control state */ 4164 count += 3; 4165 4166 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4167 for (ext = sect->section; ext->extent != NULL; ++ext) { 4168 if (sect->id == SECT_CONTEXT) 4169 count += 2 + ext->reg_count; 4170 else 4171 return 0; 4172 } 4173 } 4174 4175 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4176 count += 3; 4177 /* end clear state */ 4178 count += 2; 4179 /* clear state */ 4180 count += 2; 4181 4182 return count; 4183 } 4184 4185 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4186 volatile u32 *buffer) 4187 { 4188 u32 count = 0, i; 4189 const struct cs_section_def *sect = NULL; 4190 const struct cs_extent_def *ext = NULL; 4191 int ctx_reg_offset; 4192 4193 if (adev->gfx.rlc.cs_data == NULL) 4194 return; 4195 if (buffer == NULL) 4196 return; 4197 4198 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4199 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4200 4201 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4202 buffer[count++] = cpu_to_le32(0x80000000); 4203 buffer[count++] = cpu_to_le32(0x80000000); 4204 4205 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4206 for (ext = sect->section; ext->extent != NULL; ++ext) { 4207 if (sect->id == SECT_CONTEXT) { 4208 buffer[count++] = 4209 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4210 buffer[count++] = cpu_to_le32(ext->reg_index - 4211 PACKET3_SET_CONTEXT_REG_START); 4212 for (i = 0; i < ext->reg_count; i++) 4213 buffer[count++] = cpu_to_le32(ext->extent[i]); 4214 } else { 4215 return; 4216 } 4217 } 4218 } 4219 4220 ctx_reg_offset = 4221 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4223 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4224 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4225 4226 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4227 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4228 4229 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4230 buffer[count++] = cpu_to_le32(0); 4231 } 4232 4233 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4234 { 4235 /* clear state block */ 4236 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4237 &adev->gfx.rlc.clear_state_gpu_addr, 4238 (void **)&adev->gfx.rlc.cs_ptr); 4239 4240 /* jump table block */ 4241 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4242 &adev->gfx.rlc.cp_table_gpu_addr, 4243 (void **)&adev->gfx.rlc.cp_table_ptr); 4244 } 4245 4246 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4247 { 4248 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4249 4250 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4251 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4252 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4253 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4254 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4255 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4256 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4257 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4258 case IP_VERSION(10, 3, 0): 4259 reg_access_ctrl->spare_int = 4260 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4261 break; 4262 default: 4263 reg_access_ctrl->spare_int = 4264 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4265 break; 4266 } 4267 adev->gfx.rlc.rlcg_reg_access_supported = true; 4268 } 4269 4270 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4271 { 4272 const struct cs_section_def *cs_data; 4273 int r; 4274 4275 adev->gfx.rlc.cs_data = gfx10_cs_data; 4276 4277 cs_data = adev->gfx.rlc.cs_data; 4278 4279 if (cs_data) { 4280 /* init clear state block */ 4281 r = amdgpu_gfx_rlc_init_csb(adev); 4282 if (r) 4283 return r; 4284 } 4285 4286 return 0; 4287 } 4288 4289 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4290 { 4291 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4292 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4293 } 4294 4295 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4296 { 4297 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4298 4299 amdgpu_gfx_graphics_queue_acquire(adev); 4300 } 4301 4302 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4303 { 4304 int r; 4305 u32 *hpd; 4306 const __le32 *fw_data = NULL; 4307 unsigned int fw_size; 4308 u32 *fw = NULL; 4309 size_t mec_hpd_size; 4310 4311 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4312 4313 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4314 4315 /* take ownership of the relevant compute queues */ 4316 amdgpu_gfx_compute_queue_acquire(adev); 4317 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4318 4319 if (mec_hpd_size) { 4320 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4321 AMDGPU_GEM_DOMAIN_GTT, 4322 &adev->gfx.mec.hpd_eop_obj, 4323 &adev->gfx.mec.hpd_eop_gpu_addr, 4324 (void **)&hpd); 4325 if (r) { 4326 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4327 gfx_v10_0_mec_fini(adev); 4328 return r; 4329 } 4330 4331 memset(hpd, 0, mec_hpd_size); 4332 4333 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4334 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4335 } 4336 4337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4338 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4339 4340 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4341 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4342 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4343 4344 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4345 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4346 &adev->gfx.mec.mec_fw_obj, 4347 &adev->gfx.mec.mec_fw_gpu_addr, 4348 (void **)&fw); 4349 if (r) { 4350 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4351 gfx_v10_0_mec_fini(adev); 4352 return r; 4353 } 4354 4355 memcpy(fw, fw_data, fw_size); 4356 4357 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4358 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4359 } 4360 4361 return 0; 4362 } 4363 4364 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4365 { 4366 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4367 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4368 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4369 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4370 } 4371 4372 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4373 uint32_t thread, uint32_t regno, 4374 uint32_t num, uint32_t *out) 4375 { 4376 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4377 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4378 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4379 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4380 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4381 while (num--) 4382 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4383 } 4384 4385 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4386 { 4387 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4388 * field when performing a select_se_sh so it should be 4389 * zero here 4390 */ 4391 WARN_ON(simd != 0); 4392 4393 /* type 2 wave data */ 4394 dst[(*no_fields)++] = 2; 4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4396 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4397 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4398 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4399 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4400 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4401 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4402 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4403 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4404 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4405 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4406 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4407 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4408 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4409 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4410 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4411 } 4412 4413 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4414 uint32_t wave, uint32_t start, 4415 uint32_t size, uint32_t *dst) 4416 { 4417 WARN_ON(simd != 0); 4418 4419 wave_read_regs( 4420 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4421 dst); 4422 } 4423 4424 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4425 uint32_t wave, uint32_t thread, 4426 uint32_t start, uint32_t size, 4427 uint32_t *dst) 4428 { 4429 wave_read_regs( 4430 adev, wave, thread, 4431 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4432 } 4433 4434 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4435 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4436 { 4437 nv_grbm_select(adev, me, pipe, q, vm); 4438 } 4439 4440 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4441 bool enable) 4442 { 4443 uint32_t data, def; 4444 4445 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4446 4447 if (enable) 4448 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4449 else 4450 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4451 4452 if (data != def) 4453 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4454 } 4455 4456 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4457 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4458 .select_se_sh = &gfx_v10_0_select_se_sh, 4459 .read_wave_data = &gfx_v10_0_read_wave_data, 4460 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4461 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4462 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4463 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4464 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4465 }; 4466 4467 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4468 { 4469 u32 gb_addr_config; 4470 4471 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4472 case IP_VERSION(10, 1, 10): 4473 case IP_VERSION(10, 1, 1): 4474 case IP_VERSION(10, 1, 2): 4475 adev->gfx.config.max_hw_contexts = 8; 4476 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4477 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4478 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4479 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4480 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4481 break; 4482 case IP_VERSION(10, 3, 0): 4483 case IP_VERSION(10, 3, 2): 4484 case IP_VERSION(10, 3, 1): 4485 case IP_VERSION(10, 3, 4): 4486 case IP_VERSION(10, 3, 5): 4487 case IP_VERSION(10, 3, 6): 4488 case IP_VERSION(10, 3, 3): 4489 case IP_VERSION(10, 3, 7): 4490 adev->gfx.config.max_hw_contexts = 8; 4491 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4492 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4493 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4494 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4495 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4496 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4497 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4498 break; 4499 case IP_VERSION(10, 1, 3): 4500 case IP_VERSION(10, 1, 4): 4501 adev->gfx.config.max_hw_contexts = 8; 4502 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4503 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4504 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4505 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4506 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4507 break; 4508 default: 4509 BUG(); 4510 break; 4511 } 4512 4513 adev->gfx.config.gb_addr_config = gb_addr_config; 4514 4515 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4516 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4517 GB_ADDR_CONFIG, NUM_PIPES); 4518 4519 adev->gfx.config.max_tile_pipes = 4520 adev->gfx.config.gb_addr_config_fields.num_pipes; 4521 4522 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4523 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4524 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4525 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4526 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4527 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4528 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4529 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4530 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4531 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4532 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4533 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4534 } 4535 4536 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4537 int me, int pipe, int queue) 4538 { 4539 struct amdgpu_ring *ring; 4540 unsigned int irq_type; 4541 unsigned int hw_prio; 4542 4543 ring = &adev->gfx.gfx_ring[ring_id]; 4544 4545 ring->me = me; 4546 ring->pipe = pipe; 4547 ring->queue = queue; 4548 4549 ring->ring_obj = NULL; 4550 ring->use_doorbell = true; 4551 4552 if (!ring_id) 4553 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4554 else 4555 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4556 ring->vm_hub = AMDGPU_GFXHUB(0); 4557 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4558 4559 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4560 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4561 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4562 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4563 hw_prio, NULL); 4564 } 4565 4566 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4567 int mec, int pipe, int queue) 4568 { 4569 unsigned int irq_type; 4570 struct amdgpu_ring *ring; 4571 unsigned int hw_prio; 4572 4573 ring = &adev->gfx.compute_ring[ring_id]; 4574 4575 /* mec0 is me1 */ 4576 ring->me = mec + 1; 4577 ring->pipe = pipe; 4578 ring->queue = queue; 4579 4580 ring->ring_obj = NULL; 4581 ring->use_doorbell = true; 4582 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4583 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4584 + (ring_id * GFX10_MEC_HPD_SIZE); 4585 ring->vm_hub = AMDGPU_GFXHUB(0); 4586 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4587 4588 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4589 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4590 + ring->pipe; 4591 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4592 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4593 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4594 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4595 hw_prio, NULL); 4596 } 4597 4598 static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) 4599 { 4600 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4601 uint32_t *ptr; 4602 4603 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4604 if (ptr == NULL) { 4605 DRM_ERROR("Failed to allocate memory for IP Dump\n"); 4606 adev->gfx.ip_dump = NULL; 4607 } else { 4608 adev->gfx.ip_dump = ptr; 4609 } 4610 } 4611 4612 static int gfx_v10_0_sw_init(void *handle) 4613 { 4614 int i, j, k, r, ring_id = 0; 4615 int xcc_id = 0; 4616 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4617 4618 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4619 case IP_VERSION(10, 1, 10): 4620 case IP_VERSION(10, 1, 1): 4621 case IP_VERSION(10, 1, 2): 4622 case IP_VERSION(10, 1, 3): 4623 case IP_VERSION(10, 1, 4): 4624 adev->gfx.me.num_me = 1; 4625 adev->gfx.me.num_pipe_per_me = 1; 4626 adev->gfx.me.num_queue_per_pipe = 1; 4627 adev->gfx.mec.num_mec = 2; 4628 adev->gfx.mec.num_pipe_per_mec = 4; 4629 adev->gfx.mec.num_queue_per_pipe = 8; 4630 break; 4631 case IP_VERSION(10, 3, 0): 4632 case IP_VERSION(10, 3, 2): 4633 case IP_VERSION(10, 3, 1): 4634 case IP_VERSION(10, 3, 4): 4635 case IP_VERSION(10, 3, 5): 4636 case IP_VERSION(10, 3, 6): 4637 case IP_VERSION(10, 3, 3): 4638 case IP_VERSION(10, 3, 7): 4639 adev->gfx.me.num_me = 1; 4640 adev->gfx.me.num_pipe_per_me = 2; 4641 adev->gfx.me.num_queue_per_pipe = 1; 4642 adev->gfx.mec.num_mec = 2; 4643 adev->gfx.mec.num_pipe_per_mec = 4; 4644 adev->gfx.mec.num_queue_per_pipe = 4; 4645 break; 4646 default: 4647 adev->gfx.me.num_me = 1; 4648 adev->gfx.me.num_pipe_per_me = 1; 4649 adev->gfx.me.num_queue_per_pipe = 1; 4650 adev->gfx.mec.num_mec = 1; 4651 adev->gfx.mec.num_pipe_per_mec = 4; 4652 adev->gfx.mec.num_queue_per_pipe = 8; 4653 break; 4654 } 4655 4656 /* KIQ event */ 4657 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4658 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4659 &adev->gfx.kiq[0].irq); 4660 if (r) 4661 return r; 4662 4663 /* EOP Event */ 4664 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4665 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4666 &adev->gfx.eop_irq); 4667 if (r) 4668 return r; 4669 4670 /* Privileged reg */ 4671 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4672 &adev->gfx.priv_reg_irq); 4673 if (r) 4674 return r; 4675 4676 /* Privileged inst */ 4677 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4678 &adev->gfx.priv_inst_irq); 4679 if (r) 4680 return r; 4681 4682 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4683 4684 gfx_v10_0_me_init(adev); 4685 4686 if (adev->gfx.rlc.funcs) { 4687 if (adev->gfx.rlc.funcs->init) { 4688 r = adev->gfx.rlc.funcs->init(adev); 4689 if (r) { 4690 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4691 return r; 4692 } 4693 } 4694 } 4695 4696 r = gfx_v10_0_mec_init(adev); 4697 if (r) { 4698 DRM_ERROR("Failed to init MEC BOs!\n"); 4699 return r; 4700 } 4701 4702 /* set up the gfx ring */ 4703 for (i = 0; i < adev->gfx.me.num_me; i++) { 4704 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4705 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4706 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4707 continue; 4708 4709 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4710 i, k, j); 4711 if (r) 4712 return r; 4713 ring_id++; 4714 } 4715 } 4716 } 4717 4718 ring_id = 0; 4719 /* set up the compute queues - allocate horizontally across pipes */ 4720 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4721 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4722 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4723 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4724 k, j)) 4725 continue; 4726 4727 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4728 i, k, j); 4729 if (r) 4730 return r; 4731 4732 ring_id++; 4733 } 4734 } 4735 } 4736 4737 if (!adev->enable_mes_kiq) { 4738 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4739 if (r) { 4740 DRM_ERROR("Failed to init KIQ BOs!\n"); 4741 return r; 4742 } 4743 4744 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4745 if (r) 4746 return r; 4747 } 4748 4749 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4750 if (r) 4751 return r; 4752 4753 /* allocate visible FB for rlc auto-loading fw */ 4754 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4755 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4756 if (r) 4757 return r; 4758 } 4759 4760 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4761 4762 gfx_v10_0_gpu_early_init(adev); 4763 4764 gfx_v10_0_alloc_dump_mem(adev); 4765 4766 return 0; 4767 } 4768 4769 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4770 { 4771 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4772 &adev->gfx.pfp.pfp_fw_gpu_addr, 4773 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4774 } 4775 4776 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4777 { 4778 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4779 &adev->gfx.ce.ce_fw_gpu_addr, 4780 (void **)&adev->gfx.ce.ce_fw_ptr); 4781 } 4782 4783 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4784 { 4785 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4786 &adev->gfx.me.me_fw_gpu_addr, 4787 (void **)&adev->gfx.me.me_fw_ptr); 4788 } 4789 4790 static int gfx_v10_0_sw_fini(void *handle) 4791 { 4792 int i; 4793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4794 4795 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4796 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4797 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4798 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4799 4800 amdgpu_gfx_mqd_sw_fini(adev, 0); 4801 4802 if (!adev->enable_mes_kiq) { 4803 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4804 amdgpu_gfx_kiq_fini(adev, 0); 4805 } 4806 4807 gfx_v10_0_pfp_fini(adev); 4808 gfx_v10_0_ce_fini(adev); 4809 gfx_v10_0_me_fini(adev); 4810 gfx_v10_0_rlc_fini(adev); 4811 gfx_v10_0_mec_fini(adev); 4812 4813 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4814 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4815 4816 gfx_v10_0_free_microcode(adev); 4817 4818 kfree(adev->gfx.ip_dump); 4819 4820 return 0; 4821 } 4822 4823 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4824 u32 sh_num, u32 instance, int xcc_id) 4825 { 4826 u32 data; 4827 4828 if (instance == 0xffffffff) 4829 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4830 INSTANCE_BROADCAST_WRITES, 1); 4831 else 4832 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4833 instance); 4834 4835 if (se_num == 0xffffffff) 4836 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4837 1); 4838 else 4839 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4840 4841 if (sh_num == 0xffffffff) 4842 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4843 1); 4844 else 4845 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4846 4847 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4848 } 4849 4850 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4851 { 4852 u32 data, mask; 4853 4854 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4855 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4856 4857 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4858 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4859 4860 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4861 adev->gfx.config.max_sh_per_se); 4862 4863 return (~data) & mask; 4864 } 4865 4866 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4867 { 4868 int i, j; 4869 u32 data; 4870 u32 active_rbs = 0; 4871 u32 bitmap; 4872 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4873 adev->gfx.config.max_sh_per_se; 4874 4875 mutex_lock(&adev->grbm_idx_mutex); 4876 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4877 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4878 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4879 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4880 IP_VERSION(10, 3, 0)) || 4881 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4882 IP_VERSION(10, 3, 3)) || 4883 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4884 IP_VERSION(10, 3, 6))) && 4885 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4886 continue; 4887 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4888 data = gfx_v10_0_get_rb_active_bitmap(adev); 4889 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4890 rb_bitmap_width_per_sh); 4891 } 4892 } 4893 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4894 mutex_unlock(&adev->grbm_idx_mutex); 4895 4896 adev->gfx.config.backend_enable_mask = active_rbs; 4897 adev->gfx.config.num_rbs = hweight32(active_rbs); 4898 } 4899 4900 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4901 { 4902 uint32_t num_sc; 4903 uint32_t enabled_rb_per_sh; 4904 uint32_t active_rb_bitmap; 4905 uint32_t num_rb_per_sc; 4906 uint32_t num_packer_per_sc; 4907 uint32_t pa_sc_tile_steering_override; 4908 4909 /* for ASICs that integrates GFX v10.3 4910 * pa_sc_tile_steering_override should be set to 0 4911 */ 4912 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 4913 return 0; 4914 4915 /* init num_sc */ 4916 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4917 adev->gfx.config.num_sc_per_sh; 4918 /* init num_rb_per_sc */ 4919 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4920 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4921 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4922 /* init num_packer_per_sc */ 4923 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4924 4925 pa_sc_tile_steering_override = 0; 4926 pa_sc_tile_steering_override |= 4927 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4928 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4929 pa_sc_tile_steering_override |= 4930 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4931 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4932 pa_sc_tile_steering_override |= 4933 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4934 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4935 4936 return pa_sc_tile_steering_override; 4937 } 4938 4939 #define DEFAULT_SH_MEM_BASES (0x6000) 4940 4941 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4942 uint32_t first_vmid, 4943 uint32_t last_vmid) 4944 { 4945 uint32_t data; 4946 uint32_t trap_config_vmid_mask = 0; 4947 int i; 4948 4949 /* Calculate trap config vmid mask */ 4950 for (i = first_vmid; i < last_vmid; i++) 4951 trap_config_vmid_mask |= (1 << i); 4952 4953 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4954 VMID_SEL, trap_config_vmid_mask); 4955 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4956 TRAP_EN, 1); 4957 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4958 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4959 4960 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4961 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4962 } 4963 4964 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4965 { 4966 int i; 4967 uint32_t sh_mem_bases; 4968 4969 /* 4970 * Configure apertures: 4971 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4972 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4973 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4974 */ 4975 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4976 4977 mutex_lock(&adev->srbm_mutex); 4978 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4979 nv_grbm_select(adev, 0, 0, 0, i); 4980 /* CP and shaders */ 4981 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4982 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4983 } 4984 nv_grbm_select(adev, 0, 0, 0, 0); 4985 mutex_unlock(&adev->srbm_mutex); 4986 4987 /* 4988 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4989 * access. These should be enabled by FW for target VMIDs. 4990 */ 4991 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4992 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4993 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4994 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4995 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4996 } 4997 4998 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4999 AMDGPU_NUM_VMID); 5000 } 5001 5002 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5003 { 5004 int vmid; 5005 5006 /* 5007 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5008 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5009 * the driver can enable them for graphics. VMID0 should maintain 5010 * access so that HWS firmware can save/restore entries. 5011 */ 5012 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5013 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5014 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5015 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5016 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5017 } 5018 } 5019 5020 5021 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5022 { 5023 int i, j, k; 5024 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5025 u32 tmp, wgp_active_bitmap = 0; 5026 u32 gcrd_targets_disable_tcp = 0; 5027 u32 utcl_invreq_disable = 0; 5028 /* 5029 * GCRD_TARGETS_DISABLE field contains 5030 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5031 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5032 */ 5033 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5034 2 * max_wgp_per_sh + /* TCP */ 5035 max_wgp_per_sh + /* SQC */ 5036 4); /* GL1C */ 5037 /* 5038 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5039 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5040 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5041 */ 5042 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5043 2 * max_wgp_per_sh + /* TCP */ 5044 2 * max_wgp_per_sh + /* SQC */ 5045 4 + /* RMI */ 5046 1); /* SQG */ 5047 5048 mutex_lock(&adev->grbm_idx_mutex); 5049 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5050 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5051 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5052 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5053 /* 5054 * Set corresponding TCP bits for the inactive WGPs in 5055 * GCRD_SA_TARGETS_DISABLE 5056 */ 5057 gcrd_targets_disable_tcp = 0; 5058 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5059 utcl_invreq_disable = 0; 5060 5061 for (k = 0; k < max_wgp_per_sh; k++) { 5062 if (!(wgp_active_bitmap & (1 << k))) { 5063 gcrd_targets_disable_tcp |= 3 << (2 * k); 5064 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5065 utcl_invreq_disable |= (3 << (2 * k)) | 5066 (3 << (2 * (max_wgp_per_sh + k))); 5067 } 5068 } 5069 5070 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5071 /* only override TCP & SQC bits */ 5072 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5073 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5074 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5075 5076 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5077 /* only override TCP & SQC bits */ 5078 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5079 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5080 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5081 } 5082 } 5083 5084 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5085 mutex_unlock(&adev->grbm_idx_mutex); 5086 } 5087 5088 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5089 { 5090 /* TCCs are global (not instanced). */ 5091 uint32_t tcc_disable; 5092 5093 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5094 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5095 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5096 } else { 5097 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5098 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5099 } 5100 5101 adev->gfx.config.tcc_disabled_mask = 5102 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5103 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5104 } 5105 5106 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5107 { 5108 u32 tmp; 5109 int i; 5110 5111 if (!amdgpu_sriov_vf(adev)) 5112 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5113 5114 gfx_v10_0_setup_rb(adev); 5115 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5116 gfx_v10_0_get_tcc_info(adev); 5117 adev->gfx.config.pa_sc_tile_steering_override = 5118 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5119 5120 /* XXX SH_MEM regs */ 5121 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5122 mutex_lock(&adev->srbm_mutex); 5123 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5124 nv_grbm_select(adev, 0, 0, 0, i); 5125 /* CP and shaders */ 5126 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5127 if (i != 0) { 5128 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5129 (adev->gmc.private_aperture_start >> 48)); 5130 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5131 (adev->gmc.shared_aperture_start >> 48)); 5132 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5133 } 5134 } 5135 nv_grbm_select(adev, 0, 0, 0, 0); 5136 5137 mutex_unlock(&adev->srbm_mutex); 5138 5139 gfx_v10_0_init_compute_vmid(adev); 5140 gfx_v10_0_init_gds_vmid(adev); 5141 5142 } 5143 5144 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5145 bool enable) 5146 { 5147 u32 tmp; 5148 5149 if (amdgpu_sriov_vf(adev)) 5150 return; 5151 5152 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5153 5154 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5155 enable ? 1 : 0); 5156 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5157 enable ? 1 : 0); 5158 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5159 enable ? 1 : 0); 5160 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5161 enable ? 1 : 0); 5162 5163 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5164 } 5165 5166 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5167 { 5168 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5169 5170 /* csib */ 5171 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5172 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5173 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5174 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5175 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5176 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5177 } else { 5178 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5179 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5180 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5181 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5182 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5183 } 5184 return 0; 5185 } 5186 5187 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5188 { 5189 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5190 5191 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5192 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5193 } 5194 5195 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5196 { 5197 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5198 udelay(50); 5199 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5200 udelay(50); 5201 } 5202 5203 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5204 bool enable) 5205 { 5206 uint32_t rlc_pg_cntl; 5207 5208 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5209 5210 if (!enable) { 5211 /* RLC_PG_CNTL[23] = 0 (default) 5212 * RLC will wait for handshake acks with SMU 5213 * GFXOFF will be enabled 5214 * RLC_PG_CNTL[23] = 1 5215 * RLC will not issue any message to SMU 5216 * hence no handshake between SMU & RLC 5217 * GFXOFF will be disabled 5218 */ 5219 rlc_pg_cntl |= 0x800000; 5220 } else 5221 rlc_pg_cntl &= ~0x800000; 5222 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5223 } 5224 5225 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5226 { 5227 /* 5228 * TODO: enable rlc & smu handshake until smu 5229 * and gfxoff feature works as expected 5230 */ 5231 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5232 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5233 5234 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5235 udelay(50); 5236 } 5237 5238 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5239 { 5240 uint32_t tmp; 5241 5242 /* enable Save Restore Machine */ 5243 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5244 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5245 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5246 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5247 } 5248 5249 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5250 { 5251 const struct rlc_firmware_header_v2_0 *hdr; 5252 const __le32 *fw_data; 5253 unsigned int i, fw_size; 5254 5255 if (!adev->gfx.rlc_fw) 5256 return -EINVAL; 5257 5258 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5259 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5260 5261 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5262 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5263 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5264 5265 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5266 RLCG_UCODE_LOADING_START_ADDRESS); 5267 5268 for (i = 0; i < fw_size; i++) 5269 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5270 le32_to_cpup(fw_data++)); 5271 5272 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5273 5274 return 0; 5275 } 5276 5277 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5278 { 5279 int r; 5280 5281 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5282 adev->psp.autoload_supported) { 5283 5284 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5285 if (r) 5286 return r; 5287 5288 gfx_v10_0_init_csb(adev); 5289 5290 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5291 5292 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5293 gfx_v10_0_rlc_enable_srm(adev); 5294 } else { 5295 if (amdgpu_sriov_vf(adev)) { 5296 gfx_v10_0_init_csb(adev); 5297 return 0; 5298 } 5299 5300 adev->gfx.rlc.funcs->stop(adev); 5301 5302 /* disable CG */ 5303 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5304 5305 /* disable PG */ 5306 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5307 5308 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5309 /* legacy rlc firmware loading */ 5310 r = gfx_v10_0_rlc_load_microcode(adev); 5311 if (r) 5312 return r; 5313 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5314 /* rlc backdoor autoload firmware */ 5315 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5316 if (r) 5317 return r; 5318 } 5319 5320 gfx_v10_0_init_csb(adev); 5321 5322 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5323 5324 adev->gfx.rlc.funcs->start(adev); 5325 5326 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5327 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5328 if (r) 5329 return r; 5330 } 5331 } 5332 5333 return 0; 5334 } 5335 5336 static struct { 5337 FIRMWARE_ID id; 5338 unsigned int offset; 5339 unsigned int size; 5340 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5341 5342 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5343 { 5344 int ret; 5345 RLC_TABLE_OF_CONTENT *rlc_toc; 5346 5347 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5348 AMDGPU_GEM_DOMAIN_GTT, 5349 &adev->gfx.rlc.rlc_toc_bo, 5350 &adev->gfx.rlc.rlc_toc_gpu_addr, 5351 (void **)&adev->gfx.rlc.rlc_toc_buf); 5352 if (ret) { 5353 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5354 return ret; 5355 } 5356 5357 /* Copy toc from psp sos fw to rlc toc buffer */ 5358 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5359 5360 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5361 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5362 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5363 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5364 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5365 /* Offset needs 4KB alignment */ 5366 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5367 } 5368 5369 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5370 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5371 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5372 5373 rlc_toc++; 5374 } 5375 5376 return 0; 5377 } 5378 5379 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5380 { 5381 uint32_t total_size = 0; 5382 FIRMWARE_ID id; 5383 int ret; 5384 5385 ret = gfx_v10_0_parse_rlc_toc(adev); 5386 if (ret) { 5387 dev_err(adev->dev, "failed to parse rlc toc\n"); 5388 return 0; 5389 } 5390 5391 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5392 total_size += rlc_autoload_info[id].size; 5393 5394 /* In case the offset in rlc toc ucode is aligned */ 5395 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5396 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5397 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5398 5399 return total_size; 5400 } 5401 5402 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5403 { 5404 int r; 5405 uint32_t total_size; 5406 5407 total_size = gfx_v10_0_calc_toc_total_size(adev); 5408 5409 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5410 AMDGPU_GEM_DOMAIN_GTT, 5411 &adev->gfx.rlc.rlc_autoload_bo, 5412 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5413 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5414 if (r) { 5415 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5416 return r; 5417 } 5418 5419 return 0; 5420 } 5421 5422 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5423 { 5424 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5425 &adev->gfx.rlc.rlc_toc_gpu_addr, 5426 (void **)&adev->gfx.rlc.rlc_toc_buf); 5427 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5428 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5429 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5430 } 5431 5432 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5433 FIRMWARE_ID id, 5434 const void *fw_data, 5435 uint32_t fw_size) 5436 { 5437 uint32_t toc_offset; 5438 uint32_t toc_fw_size; 5439 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5440 5441 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5442 return; 5443 5444 toc_offset = rlc_autoload_info[id].offset; 5445 toc_fw_size = rlc_autoload_info[id].size; 5446 5447 if (fw_size == 0) 5448 fw_size = toc_fw_size; 5449 5450 if (fw_size > toc_fw_size) 5451 fw_size = toc_fw_size; 5452 5453 memcpy(ptr + toc_offset, fw_data, fw_size); 5454 5455 if (fw_size < toc_fw_size) 5456 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5457 } 5458 5459 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5460 { 5461 void *data; 5462 uint32_t size; 5463 5464 data = adev->gfx.rlc.rlc_toc_buf; 5465 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5466 5467 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5468 FIRMWARE_ID_RLC_TOC, 5469 data, size); 5470 } 5471 5472 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5473 { 5474 const __le32 *fw_data; 5475 uint32_t fw_size; 5476 const struct gfx_firmware_header_v1_0 *cp_hdr; 5477 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5478 5479 /* pfp ucode */ 5480 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5481 adev->gfx.pfp_fw->data; 5482 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5483 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5484 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5485 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5486 FIRMWARE_ID_CP_PFP, 5487 fw_data, fw_size); 5488 5489 /* ce ucode */ 5490 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5491 adev->gfx.ce_fw->data; 5492 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5493 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5494 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5495 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5496 FIRMWARE_ID_CP_CE, 5497 fw_data, fw_size); 5498 5499 /* me ucode */ 5500 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5501 adev->gfx.me_fw->data; 5502 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5503 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5504 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5505 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5506 FIRMWARE_ID_CP_ME, 5507 fw_data, fw_size); 5508 5509 /* rlc ucode */ 5510 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5511 adev->gfx.rlc_fw->data; 5512 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5513 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5514 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5515 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5516 FIRMWARE_ID_RLC_G_UCODE, 5517 fw_data, fw_size); 5518 5519 /* mec1 ucode */ 5520 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5521 adev->gfx.mec_fw->data; 5522 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5523 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5524 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5525 cp_hdr->jt_size * 4; 5526 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5527 FIRMWARE_ID_CP_MEC, 5528 fw_data, fw_size); 5529 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5530 } 5531 5532 /* Temporarily put sdma part here */ 5533 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5534 { 5535 const __le32 *fw_data; 5536 uint32_t fw_size; 5537 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5538 int i; 5539 5540 for (i = 0; i < adev->sdma.num_instances; i++) { 5541 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5542 adev->sdma.instance[i].fw->data; 5543 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5544 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5545 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5546 5547 if (i == 0) { 5548 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5549 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5550 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5551 FIRMWARE_ID_SDMA0_JT, 5552 (uint32_t *)fw_data + 5553 sdma_hdr->jt_offset, 5554 sdma_hdr->jt_size * 4); 5555 } else if (i == 1) { 5556 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5557 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5558 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5559 FIRMWARE_ID_SDMA1_JT, 5560 (uint32_t *)fw_data + 5561 sdma_hdr->jt_offset, 5562 sdma_hdr->jt_size * 4); 5563 } 5564 } 5565 } 5566 5567 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5568 { 5569 uint32_t rlc_g_offset, rlc_g_size, tmp; 5570 uint64_t gpu_addr; 5571 5572 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5573 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5574 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5575 5576 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5577 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5578 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5579 5580 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5581 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5582 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5583 5584 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5585 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5586 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5587 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5588 return -EINVAL; 5589 } 5590 5591 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5592 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5593 DRM_ERROR("RLC ROM should halt itself\n"); 5594 return -EINVAL; 5595 } 5596 5597 return 0; 5598 } 5599 5600 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5601 { 5602 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5603 uint32_t tmp; 5604 int i; 5605 uint64_t addr; 5606 5607 /* Trigger an invalidation of the L1 instruction caches */ 5608 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5609 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5610 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5611 5612 /* Wait for invalidation complete */ 5613 for (i = 0; i < usec_timeout; i++) { 5614 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5615 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5616 INVALIDATE_CACHE_COMPLETE)) 5617 break; 5618 udelay(1); 5619 } 5620 5621 if (i >= usec_timeout) { 5622 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5623 return -EINVAL; 5624 } 5625 5626 /* Program me ucode address into intruction cache address register */ 5627 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5628 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5629 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5630 lower_32_bits(addr) & 0xFFFFF000); 5631 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5632 upper_32_bits(addr)); 5633 5634 return 0; 5635 } 5636 5637 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5638 { 5639 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5640 uint32_t tmp; 5641 int i; 5642 uint64_t addr; 5643 5644 /* Trigger an invalidation of the L1 instruction caches */ 5645 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5646 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5647 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5648 5649 /* Wait for invalidation complete */ 5650 for (i = 0; i < usec_timeout; i++) { 5651 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5652 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5653 INVALIDATE_CACHE_COMPLETE)) 5654 break; 5655 udelay(1); 5656 } 5657 5658 if (i >= usec_timeout) { 5659 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5660 return -EINVAL; 5661 } 5662 5663 /* Program ce ucode address into intruction cache address register */ 5664 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5665 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5666 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5667 lower_32_bits(addr) & 0xFFFFF000); 5668 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5669 upper_32_bits(addr)); 5670 5671 return 0; 5672 } 5673 5674 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5675 { 5676 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5677 uint32_t tmp; 5678 int i; 5679 uint64_t addr; 5680 5681 /* Trigger an invalidation of the L1 instruction caches */ 5682 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5683 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5684 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5685 5686 /* Wait for invalidation complete */ 5687 for (i = 0; i < usec_timeout; i++) { 5688 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5689 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5690 INVALIDATE_CACHE_COMPLETE)) 5691 break; 5692 udelay(1); 5693 } 5694 5695 if (i >= usec_timeout) { 5696 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5697 return -EINVAL; 5698 } 5699 5700 /* Program pfp ucode address into intruction cache address register */ 5701 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5702 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5703 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5704 lower_32_bits(addr) & 0xFFFFF000); 5705 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5706 upper_32_bits(addr)); 5707 5708 return 0; 5709 } 5710 5711 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5712 { 5713 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5714 uint32_t tmp; 5715 int i; 5716 uint64_t addr; 5717 5718 /* Trigger an invalidation of the L1 instruction caches */ 5719 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5720 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5721 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5722 5723 /* Wait for invalidation complete */ 5724 for (i = 0; i < usec_timeout; i++) { 5725 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5726 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5727 INVALIDATE_CACHE_COMPLETE)) 5728 break; 5729 udelay(1); 5730 } 5731 5732 if (i >= usec_timeout) { 5733 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5734 return -EINVAL; 5735 } 5736 5737 /* Program mec1 ucode address into intruction cache address register */ 5738 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5739 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5740 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5741 lower_32_bits(addr) & 0xFFFFF000); 5742 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5743 upper_32_bits(addr)); 5744 5745 return 0; 5746 } 5747 5748 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5749 { 5750 uint32_t cp_status; 5751 uint32_t bootload_status; 5752 int i, r; 5753 5754 for (i = 0; i < adev->usec_timeout; i++) { 5755 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5756 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5757 if ((cp_status == 0) && 5758 (REG_GET_FIELD(bootload_status, 5759 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5760 break; 5761 } 5762 udelay(1); 5763 } 5764 5765 if (i >= adev->usec_timeout) { 5766 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5767 return -ETIMEDOUT; 5768 } 5769 5770 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5771 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5772 if (r) 5773 return r; 5774 5775 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5776 if (r) 5777 return r; 5778 5779 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5780 if (r) 5781 return r; 5782 5783 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5784 if (r) 5785 return r; 5786 } 5787 5788 return 0; 5789 } 5790 5791 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5792 { 5793 int i; 5794 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5795 5796 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5797 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5798 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5799 5800 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5801 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5802 else 5803 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5804 5805 if (adev->job_hang && !enable) 5806 return 0; 5807 5808 for (i = 0; i < adev->usec_timeout; i++) { 5809 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5810 break; 5811 udelay(1); 5812 } 5813 5814 if (i >= adev->usec_timeout) 5815 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5816 5817 return 0; 5818 } 5819 5820 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5821 { 5822 int r; 5823 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5824 const __le32 *fw_data; 5825 unsigned int i, fw_size; 5826 uint32_t tmp; 5827 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5828 5829 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5830 adev->gfx.pfp_fw->data; 5831 5832 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5833 5834 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5835 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5836 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5837 5838 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5839 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5840 &adev->gfx.pfp.pfp_fw_obj, 5841 &adev->gfx.pfp.pfp_fw_gpu_addr, 5842 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5843 if (r) { 5844 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5845 gfx_v10_0_pfp_fini(adev); 5846 return r; 5847 } 5848 5849 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5850 5851 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5852 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5853 5854 /* Trigger an invalidation of the L1 instruction caches */ 5855 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5856 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5857 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5858 5859 /* Wait for invalidation complete */ 5860 for (i = 0; i < usec_timeout; i++) { 5861 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5862 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5863 INVALIDATE_CACHE_COMPLETE)) 5864 break; 5865 udelay(1); 5866 } 5867 5868 if (i >= usec_timeout) { 5869 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5870 return -EINVAL; 5871 } 5872 5873 if (amdgpu_emu_mode == 1) 5874 adev->hdp.funcs->flush_hdp(adev, NULL); 5875 5876 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5877 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5878 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5879 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5880 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5881 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5882 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5883 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5884 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5885 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5886 5887 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5888 5889 for (i = 0; i < pfp_hdr->jt_size; i++) 5890 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5891 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5892 5893 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5894 5895 return 0; 5896 } 5897 5898 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5899 { 5900 int r; 5901 const struct gfx_firmware_header_v1_0 *ce_hdr; 5902 const __le32 *fw_data; 5903 unsigned int i, fw_size; 5904 uint32_t tmp; 5905 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5906 5907 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5908 adev->gfx.ce_fw->data; 5909 5910 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5911 5912 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5913 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5914 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5915 5916 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5917 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5918 &adev->gfx.ce.ce_fw_obj, 5919 &adev->gfx.ce.ce_fw_gpu_addr, 5920 (void **)&adev->gfx.ce.ce_fw_ptr); 5921 if (r) { 5922 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5923 gfx_v10_0_ce_fini(adev); 5924 return r; 5925 } 5926 5927 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5928 5929 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5930 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5931 5932 /* Trigger an invalidation of the L1 instruction caches */ 5933 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5934 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5935 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5936 5937 /* Wait for invalidation complete */ 5938 for (i = 0; i < usec_timeout; i++) { 5939 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5940 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5941 INVALIDATE_CACHE_COMPLETE)) 5942 break; 5943 udelay(1); 5944 } 5945 5946 if (i >= usec_timeout) { 5947 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5948 return -EINVAL; 5949 } 5950 5951 if (amdgpu_emu_mode == 1) 5952 adev->hdp.funcs->flush_hdp(adev, NULL); 5953 5954 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5955 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5956 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5957 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5958 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5959 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5960 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5961 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5962 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5963 5964 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5965 5966 for (i = 0; i < ce_hdr->jt_size; i++) 5967 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5968 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5969 5970 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5971 5972 return 0; 5973 } 5974 5975 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5976 { 5977 int r; 5978 const struct gfx_firmware_header_v1_0 *me_hdr; 5979 const __le32 *fw_data; 5980 unsigned int i, fw_size; 5981 uint32_t tmp; 5982 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5983 5984 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5985 adev->gfx.me_fw->data; 5986 5987 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5988 5989 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5990 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5991 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5992 5993 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5994 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5995 &adev->gfx.me.me_fw_obj, 5996 &adev->gfx.me.me_fw_gpu_addr, 5997 (void **)&adev->gfx.me.me_fw_ptr); 5998 if (r) { 5999 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6000 gfx_v10_0_me_fini(adev); 6001 return r; 6002 } 6003 6004 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6005 6006 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6007 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6008 6009 /* Trigger an invalidation of the L1 instruction caches */ 6010 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6011 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6012 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6013 6014 /* Wait for invalidation complete */ 6015 for (i = 0; i < usec_timeout; i++) { 6016 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6017 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6018 INVALIDATE_CACHE_COMPLETE)) 6019 break; 6020 udelay(1); 6021 } 6022 6023 if (i >= usec_timeout) { 6024 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6025 return -EINVAL; 6026 } 6027 6028 if (amdgpu_emu_mode == 1) 6029 adev->hdp.funcs->flush_hdp(adev, NULL); 6030 6031 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6032 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6033 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6034 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6035 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6036 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6037 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6038 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6039 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6040 6041 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6042 6043 for (i = 0; i < me_hdr->jt_size; i++) 6044 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6045 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6046 6047 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6048 6049 return 0; 6050 } 6051 6052 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6053 { 6054 int r; 6055 6056 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6057 return -EINVAL; 6058 6059 gfx_v10_0_cp_gfx_enable(adev, false); 6060 6061 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6062 if (r) { 6063 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6064 return r; 6065 } 6066 6067 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6068 if (r) { 6069 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6070 return r; 6071 } 6072 6073 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6074 if (r) { 6075 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6076 return r; 6077 } 6078 6079 return 0; 6080 } 6081 6082 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6083 { 6084 struct amdgpu_ring *ring; 6085 const struct cs_section_def *sect = NULL; 6086 const struct cs_extent_def *ext = NULL; 6087 int r, i; 6088 int ctx_reg_offset; 6089 6090 /* init the CP */ 6091 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6092 adev->gfx.config.max_hw_contexts - 1); 6093 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6094 6095 gfx_v10_0_cp_gfx_enable(adev, true); 6096 6097 ring = &adev->gfx.gfx_ring[0]; 6098 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6099 if (r) { 6100 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6101 return r; 6102 } 6103 6104 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6105 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6106 6107 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6108 amdgpu_ring_write(ring, 0x80000000); 6109 amdgpu_ring_write(ring, 0x80000000); 6110 6111 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6112 for (ext = sect->section; ext->extent != NULL; ++ext) { 6113 if (sect->id == SECT_CONTEXT) { 6114 amdgpu_ring_write(ring, 6115 PACKET3(PACKET3_SET_CONTEXT_REG, 6116 ext->reg_count)); 6117 amdgpu_ring_write(ring, ext->reg_index - 6118 PACKET3_SET_CONTEXT_REG_START); 6119 for (i = 0; i < ext->reg_count; i++) 6120 amdgpu_ring_write(ring, ext->extent[i]); 6121 } 6122 } 6123 } 6124 6125 ctx_reg_offset = 6126 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6127 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6128 amdgpu_ring_write(ring, ctx_reg_offset); 6129 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6130 6131 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6132 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6133 6134 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6135 amdgpu_ring_write(ring, 0); 6136 6137 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6138 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6139 amdgpu_ring_write(ring, 0x8000); 6140 amdgpu_ring_write(ring, 0x8000); 6141 6142 amdgpu_ring_commit(ring); 6143 6144 /* submit cs packet to copy state 0 to next available state */ 6145 if (adev->gfx.num_gfx_rings > 1) { 6146 /* maximum supported gfx ring is 2 */ 6147 ring = &adev->gfx.gfx_ring[1]; 6148 r = amdgpu_ring_alloc(ring, 2); 6149 if (r) { 6150 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6151 return r; 6152 } 6153 6154 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6155 amdgpu_ring_write(ring, 0); 6156 6157 amdgpu_ring_commit(ring); 6158 } 6159 return 0; 6160 } 6161 6162 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6163 CP_PIPE_ID pipe) 6164 { 6165 u32 tmp; 6166 6167 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6168 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6169 6170 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6171 } 6172 6173 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6174 struct amdgpu_ring *ring) 6175 { 6176 u32 tmp; 6177 6178 if (!amdgpu_async_gfx_ring) { 6179 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6180 if (ring->use_doorbell) { 6181 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6182 DOORBELL_OFFSET, ring->doorbell_index); 6183 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6184 DOORBELL_EN, 1); 6185 } else { 6186 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6187 DOORBELL_EN, 0); 6188 } 6189 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6190 } 6191 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6192 case IP_VERSION(10, 3, 0): 6193 case IP_VERSION(10, 3, 2): 6194 case IP_VERSION(10, 3, 1): 6195 case IP_VERSION(10, 3, 4): 6196 case IP_VERSION(10, 3, 5): 6197 case IP_VERSION(10, 3, 6): 6198 case IP_VERSION(10, 3, 3): 6199 case IP_VERSION(10, 3, 7): 6200 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6201 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6202 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6203 6204 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6205 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6206 break; 6207 default: 6208 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6209 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6210 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6211 6212 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6213 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6214 break; 6215 } 6216 } 6217 6218 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6219 { 6220 struct amdgpu_ring *ring; 6221 u32 tmp; 6222 u32 rb_bufsz; 6223 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6224 6225 /* Set the write pointer delay */ 6226 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6227 6228 /* set the RB to use vmid 0 */ 6229 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6230 6231 /* Init gfx ring 0 for pipe 0 */ 6232 mutex_lock(&adev->srbm_mutex); 6233 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6234 6235 /* Set ring buffer size */ 6236 ring = &adev->gfx.gfx_ring[0]; 6237 rb_bufsz = order_base_2(ring->ring_size / 8); 6238 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6239 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6240 #ifdef __BIG_ENDIAN 6241 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6242 #endif 6243 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6244 6245 /* Initialize the ring buffer's write pointers */ 6246 ring->wptr = 0; 6247 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6248 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6249 6250 /* set the wb address wether it's enabled or not */ 6251 rptr_addr = ring->rptr_gpu_addr; 6252 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6253 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6254 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6255 6256 wptr_gpu_addr = ring->wptr_gpu_addr; 6257 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6258 lower_32_bits(wptr_gpu_addr)); 6259 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6260 upper_32_bits(wptr_gpu_addr)); 6261 6262 mdelay(1); 6263 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6264 6265 rb_addr = ring->gpu_addr >> 8; 6266 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6267 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6268 6269 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6270 6271 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6272 mutex_unlock(&adev->srbm_mutex); 6273 6274 /* Init gfx ring 1 for pipe 1 */ 6275 if (adev->gfx.num_gfx_rings > 1) { 6276 mutex_lock(&adev->srbm_mutex); 6277 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6278 /* maximum supported gfx ring is 2 */ 6279 ring = &adev->gfx.gfx_ring[1]; 6280 rb_bufsz = order_base_2(ring->ring_size / 8); 6281 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6282 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6283 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6284 /* Initialize the ring buffer's write pointers */ 6285 ring->wptr = 0; 6286 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6287 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6288 /* Set the wb address wether it's enabled or not */ 6289 rptr_addr = ring->rptr_gpu_addr; 6290 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6291 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6292 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6293 wptr_gpu_addr = ring->wptr_gpu_addr; 6294 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6295 lower_32_bits(wptr_gpu_addr)); 6296 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6297 upper_32_bits(wptr_gpu_addr)); 6298 6299 mdelay(1); 6300 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6301 6302 rb_addr = ring->gpu_addr >> 8; 6303 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6304 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6305 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6306 6307 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6308 mutex_unlock(&adev->srbm_mutex); 6309 } 6310 /* Switch to pipe 0 */ 6311 mutex_lock(&adev->srbm_mutex); 6312 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6313 mutex_unlock(&adev->srbm_mutex); 6314 6315 /* start the ring */ 6316 gfx_v10_0_cp_gfx_start(adev); 6317 6318 return 0; 6319 } 6320 6321 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6322 { 6323 if (enable) { 6324 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6325 case IP_VERSION(10, 3, 0): 6326 case IP_VERSION(10, 3, 2): 6327 case IP_VERSION(10, 3, 1): 6328 case IP_VERSION(10, 3, 4): 6329 case IP_VERSION(10, 3, 5): 6330 case IP_VERSION(10, 3, 6): 6331 case IP_VERSION(10, 3, 3): 6332 case IP_VERSION(10, 3, 7): 6333 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6334 break; 6335 default: 6336 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6337 break; 6338 } 6339 } else { 6340 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6341 case IP_VERSION(10, 3, 0): 6342 case IP_VERSION(10, 3, 2): 6343 case IP_VERSION(10, 3, 1): 6344 case IP_VERSION(10, 3, 4): 6345 case IP_VERSION(10, 3, 5): 6346 case IP_VERSION(10, 3, 6): 6347 case IP_VERSION(10, 3, 3): 6348 case IP_VERSION(10, 3, 7): 6349 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6350 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6351 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6352 break; 6353 default: 6354 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6355 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6356 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6357 break; 6358 } 6359 adev->gfx.kiq[0].ring.sched.ready = false; 6360 } 6361 udelay(50); 6362 } 6363 6364 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6365 { 6366 const struct gfx_firmware_header_v1_0 *mec_hdr; 6367 const __le32 *fw_data; 6368 unsigned int i; 6369 u32 tmp; 6370 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6371 6372 if (!adev->gfx.mec_fw) 6373 return -EINVAL; 6374 6375 gfx_v10_0_cp_compute_enable(adev, false); 6376 6377 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6378 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6379 6380 fw_data = (const __le32 *) 6381 (adev->gfx.mec_fw->data + 6382 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6383 6384 /* Trigger an invalidation of the L1 instruction caches */ 6385 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6386 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6387 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6388 6389 /* Wait for invalidation complete */ 6390 for (i = 0; i < usec_timeout; i++) { 6391 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6392 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6393 INVALIDATE_CACHE_COMPLETE)) 6394 break; 6395 udelay(1); 6396 } 6397 6398 if (i >= usec_timeout) { 6399 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6400 return -EINVAL; 6401 } 6402 6403 if (amdgpu_emu_mode == 1) 6404 adev->hdp.funcs->flush_hdp(adev, NULL); 6405 6406 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6407 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6408 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6409 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6410 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6411 6412 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6413 0xFFFFF000); 6414 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6415 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6416 6417 /* MEC1 */ 6418 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6419 6420 for (i = 0; i < mec_hdr->jt_size; i++) 6421 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6422 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6423 6424 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6425 6426 /* 6427 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6428 * different microcode than MEC1. 6429 */ 6430 6431 return 0; 6432 } 6433 6434 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6435 { 6436 uint32_t tmp; 6437 struct amdgpu_device *adev = ring->adev; 6438 6439 /* tell RLC which is KIQ queue */ 6440 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6441 case IP_VERSION(10, 3, 0): 6442 case IP_VERSION(10, 3, 2): 6443 case IP_VERSION(10, 3, 1): 6444 case IP_VERSION(10, 3, 4): 6445 case IP_VERSION(10, 3, 5): 6446 case IP_VERSION(10, 3, 6): 6447 case IP_VERSION(10, 3, 3): 6448 case IP_VERSION(10, 3, 7): 6449 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6450 tmp &= 0xffffff00; 6451 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6452 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6453 tmp |= 0x80; 6454 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6455 break; 6456 default: 6457 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6458 tmp &= 0xffffff00; 6459 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6460 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6461 tmp |= 0x80; 6462 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6463 break; 6464 } 6465 } 6466 6467 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6468 struct v10_gfx_mqd *mqd, 6469 struct amdgpu_mqd_prop *prop) 6470 { 6471 bool priority = 0; 6472 u32 tmp; 6473 6474 /* set up default queue priority level 6475 * 0x0 = low priority, 0x1 = high priority 6476 */ 6477 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6478 priority = 1; 6479 6480 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6481 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6482 mqd->cp_gfx_hqd_queue_priority = tmp; 6483 } 6484 6485 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6486 struct amdgpu_mqd_prop *prop) 6487 { 6488 struct v10_gfx_mqd *mqd = m; 6489 uint64_t hqd_gpu_addr, wb_gpu_addr; 6490 uint32_t tmp; 6491 uint32_t rb_bufsz; 6492 6493 /* set up gfx hqd wptr */ 6494 mqd->cp_gfx_hqd_wptr = 0; 6495 mqd->cp_gfx_hqd_wptr_hi = 0; 6496 6497 /* set the pointer to the MQD */ 6498 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6499 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6500 6501 /* set up mqd control */ 6502 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6503 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6504 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6505 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6506 mqd->cp_gfx_mqd_control = tmp; 6507 6508 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6509 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6510 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6511 mqd->cp_gfx_hqd_vmid = 0; 6512 6513 /* set up gfx queue priority */ 6514 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6515 6516 /* set up time quantum */ 6517 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6518 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6519 mqd->cp_gfx_hqd_quantum = tmp; 6520 6521 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6522 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6523 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6524 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6525 6526 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6527 wb_gpu_addr = prop->rptr_gpu_addr; 6528 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6529 mqd->cp_gfx_hqd_rptr_addr_hi = 6530 upper_32_bits(wb_gpu_addr) & 0xffff; 6531 6532 /* set up rb_wptr_poll addr */ 6533 wb_gpu_addr = prop->wptr_gpu_addr; 6534 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6535 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6536 6537 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6538 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6539 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6540 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6541 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6542 #ifdef __BIG_ENDIAN 6543 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6544 #endif 6545 mqd->cp_gfx_hqd_cntl = tmp; 6546 6547 /* set up cp_doorbell_control */ 6548 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6549 if (prop->use_doorbell) { 6550 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6551 DOORBELL_OFFSET, prop->doorbell_index); 6552 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6553 DOORBELL_EN, 1); 6554 } else 6555 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6556 DOORBELL_EN, 0); 6557 mqd->cp_rb_doorbell_control = tmp; 6558 6559 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6560 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6561 6562 /* active the queue */ 6563 mqd->cp_gfx_hqd_active = 1; 6564 6565 return 0; 6566 } 6567 6568 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6569 { 6570 struct amdgpu_device *adev = ring->adev; 6571 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6572 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6573 6574 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6575 memset((void *)mqd, 0, sizeof(*mqd)); 6576 mutex_lock(&adev->srbm_mutex); 6577 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6578 amdgpu_ring_init_mqd(ring); 6579 6580 /* 6581 * if there are 2 gfx rings, set the lower doorbell 6582 * range of the first ring, otherwise the range of 6583 * the second ring will override the first ring 6584 */ 6585 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6586 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6587 6588 nv_grbm_select(adev, 0, 0, 0, 0); 6589 mutex_unlock(&adev->srbm_mutex); 6590 if (adev->gfx.me.mqd_backup[mqd_idx]) 6591 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6592 } else { 6593 mutex_lock(&adev->srbm_mutex); 6594 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6595 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6596 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6597 6598 nv_grbm_select(adev, 0, 0, 0, 0); 6599 mutex_unlock(&adev->srbm_mutex); 6600 /* restore mqd with the backup copy */ 6601 if (adev->gfx.me.mqd_backup[mqd_idx]) 6602 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6603 /* reset the ring */ 6604 ring->wptr = 0; 6605 *ring->wptr_cpu_addr = 0; 6606 amdgpu_ring_clear_ring(ring); 6607 } 6608 6609 return 0; 6610 } 6611 6612 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6613 { 6614 int r, i; 6615 struct amdgpu_ring *ring; 6616 6617 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6618 ring = &adev->gfx.gfx_ring[i]; 6619 6620 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6621 if (unlikely(r != 0)) 6622 return r; 6623 6624 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6625 if (!r) { 6626 r = gfx_v10_0_gfx_init_queue(ring); 6627 amdgpu_bo_kunmap(ring->mqd_obj); 6628 ring->mqd_ptr = NULL; 6629 } 6630 amdgpu_bo_unreserve(ring->mqd_obj); 6631 if (r) 6632 return r; 6633 } 6634 6635 r = amdgpu_gfx_enable_kgq(adev, 0); 6636 if (r) 6637 return r; 6638 6639 return gfx_v10_0_cp_gfx_start(adev); 6640 } 6641 6642 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6643 struct amdgpu_mqd_prop *prop) 6644 { 6645 struct v10_compute_mqd *mqd = m; 6646 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6647 uint32_t tmp; 6648 6649 mqd->header = 0xC0310800; 6650 mqd->compute_pipelinestat_enable = 0x00000001; 6651 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6652 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6653 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6654 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6655 mqd->compute_misc_reserved = 0x00000003; 6656 6657 eop_base_addr = prop->eop_gpu_addr >> 8; 6658 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6659 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6660 6661 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6662 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6663 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6664 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6665 6666 mqd->cp_hqd_eop_control = tmp; 6667 6668 /* enable doorbell? */ 6669 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6670 6671 if (prop->use_doorbell) { 6672 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6673 DOORBELL_OFFSET, prop->doorbell_index); 6674 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6675 DOORBELL_EN, 1); 6676 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6677 DOORBELL_SOURCE, 0); 6678 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6679 DOORBELL_HIT, 0); 6680 } else { 6681 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6682 DOORBELL_EN, 0); 6683 } 6684 6685 mqd->cp_hqd_pq_doorbell_control = tmp; 6686 6687 /* disable the queue if it's active */ 6688 mqd->cp_hqd_dequeue_request = 0; 6689 mqd->cp_hqd_pq_rptr = 0; 6690 mqd->cp_hqd_pq_wptr_lo = 0; 6691 mqd->cp_hqd_pq_wptr_hi = 0; 6692 6693 /* set the pointer to the MQD */ 6694 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6695 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6696 6697 /* set MQD vmid to 0 */ 6698 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6699 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6700 mqd->cp_mqd_control = tmp; 6701 6702 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6703 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6704 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6705 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6706 6707 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6708 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6709 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6710 (order_base_2(prop->queue_size / 4) - 1)); 6711 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6712 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6713 #ifdef __BIG_ENDIAN 6714 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6715 #endif 6716 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6717 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6718 prop->allow_tunneling); 6719 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6720 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6721 mqd->cp_hqd_pq_control = tmp; 6722 6723 /* set the wb address whether it's enabled or not */ 6724 wb_gpu_addr = prop->rptr_gpu_addr; 6725 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6726 mqd->cp_hqd_pq_rptr_report_addr_hi = 6727 upper_32_bits(wb_gpu_addr) & 0xffff; 6728 6729 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6730 wb_gpu_addr = prop->wptr_gpu_addr; 6731 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6732 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6733 6734 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6735 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6736 6737 /* set the vmid for the queue */ 6738 mqd->cp_hqd_vmid = 0; 6739 6740 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6741 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6742 mqd->cp_hqd_persistent_state = tmp; 6743 6744 /* set MIN_IB_AVAIL_SIZE */ 6745 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6746 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6747 mqd->cp_hqd_ib_control = tmp; 6748 6749 /* set static priority for a compute queue/ring */ 6750 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6751 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6752 6753 mqd->cp_hqd_active = prop->hqd_active; 6754 6755 return 0; 6756 } 6757 6758 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6759 { 6760 struct amdgpu_device *adev = ring->adev; 6761 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6762 int j; 6763 6764 /* inactivate the queue */ 6765 if (amdgpu_sriov_vf(adev)) 6766 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6767 6768 /* disable wptr polling */ 6769 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6770 6771 /* disable the queue if it's active */ 6772 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6773 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6774 for (j = 0; j < adev->usec_timeout; j++) { 6775 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6776 break; 6777 udelay(1); 6778 } 6779 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6780 mqd->cp_hqd_dequeue_request); 6781 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6782 mqd->cp_hqd_pq_rptr); 6783 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6784 mqd->cp_hqd_pq_wptr_lo); 6785 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6786 mqd->cp_hqd_pq_wptr_hi); 6787 } 6788 6789 /* disable doorbells */ 6790 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6791 6792 /* write the EOP addr */ 6793 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6794 mqd->cp_hqd_eop_base_addr_lo); 6795 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6796 mqd->cp_hqd_eop_base_addr_hi); 6797 6798 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6799 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6800 mqd->cp_hqd_eop_control); 6801 6802 /* set the pointer to the MQD */ 6803 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6804 mqd->cp_mqd_base_addr_lo); 6805 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6806 mqd->cp_mqd_base_addr_hi); 6807 6808 /* set MQD vmid to 0 */ 6809 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6810 mqd->cp_mqd_control); 6811 6812 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6813 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6814 mqd->cp_hqd_pq_base_lo); 6815 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6816 mqd->cp_hqd_pq_base_hi); 6817 6818 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6819 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6820 mqd->cp_hqd_pq_control); 6821 6822 /* set the wb address whether it's enabled or not */ 6823 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6824 mqd->cp_hqd_pq_rptr_report_addr_lo); 6825 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6826 mqd->cp_hqd_pq_rptr_report_addr_hi); 6827 6828 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6829 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6830 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6831 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6832 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6833 6834 /* enable the doorbell if requested */ 6835 if (ring->use_doorbell) { 6836 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6837 (adev->doorbell_index.kiq * 2) << 2); 6838 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6839 (adev->doorbell_index.userqueue_end * 2) << 2); 6840 } 6841 6842 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6843 mqd->cp_hqd_pq_doorbell_control); 6844 6845 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6846 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6847 mqd->cp_hqd_pq_wptr_lo); 6848 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6849 mqd->cp_hqd_pq_wptr_hi); 6850 6851 /* set the vmid for the queue */ 6852 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6853 6854 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6855 mqd->cp_hqd_persistent_state); 6856 6857 /* activate the queue */ 6858 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6859 mqd->cp_hqd_active); 6860 6861 if (ring->use_doorbell) 6862 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6863 6864 return 0; 6865 } 6866 6867 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6868 { 6869 struct amdgpu_device *adev = ring->adev; 6870 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6871 6872 gfx_v10_0_kiq_setting(ring); 6873 6874 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6875 /* reset MQD to a clean status */ 6876 if (adev->gfx.kiq[0].mqd_backup) 6877 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6878 6879 /* reset ring buffer */ 6880 ring->wptr = 0; 6881 amdgpu_ring_clear_ring(ring); 6882 6883 mutex_lock(&adev->srbm_mutex); 6884 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6885 gfx_v10_0_kiq_init_register(ring); 6886 nv_grbm_select(adev, 0, 0, 0, 0); 6887 mutex_unlock(&adev->srbm_mutex); 6888 } else { 6889 memset((void *)mqd, 0, sizeof(*mqd)); 6890 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6891 amdgpu_ring_clear_ring(ring); 6892 mutex_lock(&adev->srbm_mutex); 6893 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6894 amdgpu_ring_init_mqd(ring); 6895 gfx_v10_0_kiq_init_register(ring); 6896 nv_grbm_select(adev, 0, 0, 0, 0); 6897 mutex_unlock(&adev->srbm_mutex); 6898 6899 if (adev->gfx.kiq[0].mqd_backup) 6900 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6901 } 6902 6903 return 0; 6904 } 6905 6906 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6907 { 6908 struct amdgpu_device *adev = ring->adev; 6909 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6910 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6911 6912 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6913 memset((void *)mqd, 0, sizeof(*mqd)); 6914 mutex_lock(&adev->srbm_mutex); 6915 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6916 amdgpu_ring_init_mqd(ring); 6917 nv_grbm_select(adev, 0, 0, 0, 0); 6918 mutex_unlock(&adev->srbm_mutex); 6919 6920 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6921 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6922 } else { 6923 /* restore MQD to a clean status */ 6924 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6925 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6926 /* reset ring buffer */ 6927 ring->wptr = 0; 6928 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6929 amdgpu_ring_clear_ring(ring); 6930 } 6931 6932 return 0; 6933 } 6934 6935 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6936 { 6937 struct amdgpu_ring *ring; 6938 int r; 6939 6940 ring = &adev->gfx.kiq[0].ring; 6941 6942 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6943 if (unlikely(r != 0)) 6944 return r; 6945 6946 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6947 if (unlikely(r != 0)) { 6948 amdgpu_bo_unreserve(ring->mqd_obj); 6949 return r; 6950 } 6951 6952 gfx_v10_0_kiq_init_queue(ring); 6953 amdgpu_bo_kunmap(ring->mqd_obj); 6954 ring->mqd_ptr = NULL; 6955 amdgpu_bo_unreserve(ring->mqd_obj); 6956 return 0; 6957 } 6958 6959 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6960 { 6961 struct amdgpu_ring *ring = NULL; 6962 int r = 0, i; 6963 6964 gfx_v10_0_cp_compute_enable(adev, true); 6965 6966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6967 ring = &adev->gfx.compute_ring[i]; 6968 6969 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6970 if (unlikely(r != 0)) 6971 goto done; 6972 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6973 if (!r) { 6974 r = gfx_v10_0_kcq_init_queue(ring); 6975 amdgpu_bo_kunmap(ring->mqd_obj); 6976 ring->mqd_ptr = NULL; 6977 } 6978 amdgpu_bo_unreserve(ring->mqd_obj); 6979 if (r) 6980 goto done; 6981 } 6982 6983 r = amdgpu_gfx_enable_kcq(adev, 0); 6984 done: 6985 return r; 6986 } 6987 6988 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6989 { 6990 int r, i; 6991 struct amdgpu_ring *ring; 6992 6993 if (!(adev->flags & AMD_IS_APU)) 6994 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6995 6996 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6997 /* legacy firmware loading */ 6998 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6999 if (r) 7000 return r; 7001 7002 r = gfx_v10_0_cp_compute_load_microcode(adev); 7003 if (r) 7004 return r; 7005 } 7006 7007 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 7008 r = amdgpu_mes_kiq_hw_init(adev); 7009 else 7010 r = gfx_v10_0_kiq_resume(adev); 7011 if (r) 7012 return r; 7013 7014 r = gfx_v10_0_kcq_resume(adev); 7015 if (r) 7016 return r; 7017 7018 if (!amdgpu_async_gfx_ring) { 7019 r = gfx_v10_0_cp_gfx_resume(adev); 7020 if (r) 7021 return r; 7022 } else { 7023 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7024 if (r) 7025 return r; 7026 } 7027 7028 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7029 ring = &adev->gfx.gfx_ring[i]; 7030 r = amdgpu_ring_test_helper(ring); 7031 if (r) 7032 return r; 7033 } 7034 7035 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7036 ring = &adev->gfx.compute_ring[i]; 7037 r = amdgpu_ring_test_helper(ring); 7038 if (r) 7039 return r; 7040 } 7041 7042 return 0; 7043 } 7044 7045 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7046 { 7047 gfx_v10_0_cp_gfx_enable(adev, enable); 7048 gfx_v10_0_cp_compute_enable(adev, enable); 7049 } 7050 7051 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7052 { 7053 uint32_t data, pattern = 0xDEADBEEF; 7054 7055 /* 7056 * check if mmVGT_ESGS_RING_SIZE_UMD 7057 * has been remapped to mmVGT_ESGS_RING_SIZE 7058 */ 7059 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7060 case IP_VERSION(10, 3, 0): 7061 case IP_VERSION(10, 3, 2): 7062 case IP_VERSION(10, 3, 4): 7063 case IP_VERSION(10, 3, 5): 7064 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7065 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7066 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7067 7068 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7069 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7070 return true; 7071 } 7072 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7073 break; 7074 case IP_VERSION(10, 3, 1): 7075 case IP_VERSION(10, 3, 3): 7076 case IP_VERSION(10, 3, 6): 7077 case IP_VERSION(10, 3, 7): 7078 return true; 7079 default: 7080 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7081 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7082 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7083 7084 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7085 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7086 return true; 7087 } 7088 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7089 break; 7090 } 7091 7092 return false; 7093 } 7094 7095 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7096 { 7097 uint32_t data; 7098 7099 if (amdgpu_sriov_vf(adev)) 7100 return; 7101 7102 /* 7103 * Initialize cam_index to 0 7104 * index will auto-inc after each data writing 7105 */ 7106 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7107 7108 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7109 case IP_VERSION(10, 3, 0): 7110 case IP_VERSION(10, 3, 2): 7111 case IP_VERSION(10, 3, 1): 7112 case IP_VERSION(10, 3, 4): 7113 case IP_VERSION(10, 3, 5): 7114 case IP_VERSION(10, 3, 6): 7115 case IP_VERSION(10, 3, 3): 7116 case IP_VERSION(10, 3, 7): 7117 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7118 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7119 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7120 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7121 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7122 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7123 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7124 7125 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7126 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7127 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7128 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7129 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7130 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7131 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7132 7133 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7134 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7135 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7136 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7137 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7138 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7139 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7140 7141 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7142 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7143 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7144 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7145 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7146 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7147 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7148 7149 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7150 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7151 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7152 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7153 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7154 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7155 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7156 7157 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7158 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7159 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7160 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7161 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7162 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7163 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7164 7165 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7166 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7167 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7168 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7169 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7170 break; 7171 default: 7172 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7173 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7174 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7175 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7176 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7177 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7178 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7179 7180 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7181 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7182 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7183 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7184 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7185 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7186 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7187 7188 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7189 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7190 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7191 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7192 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7193 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7194 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7195 7196 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7197 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7198 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7199 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7200 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7201 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7202 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7203 7204 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7205 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7206 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7207 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7208 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7209 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7210 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7211 7212 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7213 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7214 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7215 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7216 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7217 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7218 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7219 7220 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7221 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7222 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7223 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7224 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7225 break; 7226 } 7227 7228 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7229 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7230 } 7231 7232 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7233 { 7234 uint32_t data; 7235 7236 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7237 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7238 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7239 7240 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7241 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7242 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7243 } 7244 7245 static int gfx_v10_0_hw_init(void *handle) 7246 { 7247 int r; 7248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7249 7250 if (!amdgpu_emu_mode) 7251 gfx_v10_0_init_golden_registers(adev); 7252 7253 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7254 /** 7255 * For gfx 10, rlc firmware loading relies on smu firmware is 7256 * loaded firstly, so in direct type, it has to load smc ucode 7257 * here before rlc. 7258 */ 7259 if (!(adev->flags & AMD_IS_APU)) { 7260 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7261 if (r) 7262 return r; 7263 } 7264 gfx_v10_0_disable_gpa_mode(adev); 7265 } 7266 7267 /* if GRBM CAM not remapped, set up the remapping */ 7268 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7269 gfx_v10_0_setup_grbm_cam_remapping(adev); 7270 7271 gfx_v10_0_constants_init(adev); 7272 7273 r = gfx_v10_0_rlc_resume(adev); 7274 if (r) 7275 return r; 7276 7277 /* 7278 * init golden registers and rlc resume may override some registers, 7279 * reconfig them here 7280 */ 7281 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7282 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7283 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7284 gfx_v10_0_tcp_harvest(adev); 7285 7286 r = gfx_v10_0_cp_resume(adev); 7287 if (r) 7288 return r; 7289 7290 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7291 gfx_v10_3_program_pbb_mode(adev); 7292 7293 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7294 gfx_v10_3_set_power_brake_sequence(adev); 7295 7296 return r; 7297 } 7298 7299 static int gfx_v10_0_hw_fini(void *handle) 7300 { 7301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7302 7303 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7304 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7305 7306 /* WA added for Vangogh asic fixing the SMU suspend failure 7307 * It needs to set power gating again during gfxoff control 7308 * otherwise the gfxoff disallowing will be failed to set. 7309 */ 7310 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7311 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); 7312 7313 if (!adev->no_hw_access) { 7314 if (amdgpu_async_gfx_ring) { 7315 if (amdgpu_gfx_disable_kgq(adev, 0)) 7316 DRM_ERROR("KGQ disable failed\n"); 7317 } 7318 7319 if (amdgpu_gfx_disable_kcq(adev, 0)) 7320 DRM_ERROR("KCQ disable failed\n"); 7321 } 7322 7323 if (amdgpu_sriov_vf(adev)) { 7324 gfx_v10_0_cp_gfx_enable(adev, false); 7325 /* Remove the steps of clearing KIQ position. 7326 * It causes GFX hang when another Win guest is rendering. 7327 */ 7328 return 0; 7329 } 7330 gfx_v10_0_cp_enable(adev, false); 7331 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7332 7333 return 0; 7334 } 7335 7336 static int gfx_v10_0_suspend(void *handle) 7337 { 7338 return gfx_v10_0_hw_fini(handle); 7339 } 7340 7341 static int gfx_v10_0_resume(void *handle) 7342 { 7343 return gfx_v10_0_hw_init(handle); 7344 } 7345 7346 static bool gfx_v10_0_is_idle(void *handle) 7347 { 7348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7349 7350 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7351 GRBM_STATUS, GUI_ACTIVE)) 7352 return false; 7353 else 7354 return true; 7355 } 7356 7357 static int gfx_v10_0_wait_for_idle(void *handle) 7358 { 7359 unsigned int i; 7360 u32 tmp; 7361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7362 7363 for (i = 0; i < adev->usec_timeout; i++) { 7364 /* read MC_STATUS */ 7365 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7366 GRBM_STATUS__GUI_ACTIVE_MASK; 7367 7368 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7369 return 0; 7370 udelay(1); 7371 } 7372 return -ETIMEDOUT; 7373 } 7374 7375 static int gfx_v10_0_soft_reset(void *handle) 7376 { 7377 u32 grbm_soft_reset = 0; 7378 u32 tmp; 7379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7380 7381 /* GRBM_STATUS */ 7382 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7383 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7384 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7385 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7386 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7387 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7388 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7389 GRBM_SOFT_RESET, SOFT_RESET_CP, 7390 1); 7391 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7392 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7393 1); 7394 } 7395 7396 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7397 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7398 GRBM_SOFT_RESET, SOFT_RESET_CP, 7399 1); 7400 } 7401 7402 /* GRBM_STATUS2 */ 7403 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7404 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7405 case IP_VERSION(10, 3, 0): 7406 case IP_VERSION(10, 3, 2): 7407 case IP_VERSION(10, 3, 1): 7408 case IP_VERSION(10, 3, 4): 7409 case IP_VERSION(10, 3, 5): 7410 case IP_VERSION(10, 3, 6): 7411 case IP_VERSION(10, 3, 3): 7412 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7413 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7414 GRBM_SOFT_RESET, 7415 SOFT_RESET_RLC, 7416 1); 7417 break; 7418 default: 7419 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7420 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7421 GRBM_SOFT_RESET, 7422 SOFT_RESET_RLC, 7423 1); 7424 break; 7425 } 7426 7427 if (grbm_soft_reset) { 7428 /* stop the rlc */ 7429 gfx_v10_0_rlc_stop(adev); 7430 7431 /* Disable GFX parsing/prefetching */ 7432 gfx_v10_0_cp_gfx_enable(adev, false); 7433 7434 /* Disable MEC parsing/prefetching */ 7435 gfx_v10_0_cp_compute_enable(adev, false); 7436 7437 if (grbm_soft_reset) { 7438 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7439 tmp |= grbm_soft_reset; 7440 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7441 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7442 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7443 7444 udelay(50); 7445 7446 tmp &= ~grbm_soft_reset; 7447 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7448 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7449 } 7450 7451 /* Wait a little for things to settle down */ 7452 udelay(50); 7453 } 7454 return 0; 7455 } 7456 7457 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7458 { 7459 uint64_t clock, clock_lo, clock_hi, hi_check; 7460 7461 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7462 case IP_VERSION(10, 1, 3): 7463 case IP_VERSION(10, 1, 4): 7464 preempt_disable(); 7465 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7466 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7467 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7468 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7469 * roughly every 42 seconds. 7470 */ 7471 if (hi_check != clock_hi) { 7472 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7473 clock_hi = hi_check; 7474 } 7475 preempt_enable(); 7476 clock = clock_lo | (clock_hi << 32ULL); 7477 break; 7478 case IP_VERSION(10, 3, 1): 7479 case IP_VERSION(10, 3, 3): 7480 case IP_VERSION(10, 3, 7): 7481 preempt_disable(); 7482 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7483 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7484 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7485 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7486 * roughly every 42 seconds. 7487 */ 7488 if (hi_check != clock_hi) { 7489 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7490 clock_hi = hi_check; 7491 } 7492 preempt_enable(); 7493 clock = clock_lo | (clock_hi << 32ULL); 7494 break; 7495 case IP_VERSION(10, 3, 6): 7496 preempt_disable(); 7497 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7498 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7499 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7500 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7501 * roughly every 42 seconds. 7502 */ 7503 if (hi_check != clock_hi) { 7504 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7505 clock_hi = hi_check; 7506 } 7507 preempt_enable(); 7508 clock = clock_lo | (clock_hi << 32ULL); 7509 break; 7510 default: 7511 preempt_disable(); 7512 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7513 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7514 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7515 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7516 * roughly every 42 seconds. 7517 */ 7518 if (hi_check != clock_hi) { 7519 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7520 clock_hi = hi_check; 7521 } 7522 preempt_enable(); 7523 clock = clock_lo | (clock_hi << 32ULL); 7524 break; 7525 } 7526 return clock; 7527 } 7528 7529 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7530 uint32_t vmid, 7531 uint32_t gds_base, uint32_t gds_size, 7532 uint32_t gws_base, uint32_t gws_size, 7533 uint32_t oa_base, uint32_t oa_size) 7534 { 7535 struct amdgpu_device *adev = ring->adev; 7536 7537 /* GDS Base */ 7538 gfx_v10_0_write_data_to_reg(ring, 0, false, 7539 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7540 gds_base); 7541 7542 /* GDS Size */ 7543 gfx_v10_0_write_data_to_reg(ring, 0, false, 7544 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7545 gds_size); 7546 7547 /* GWS */ 7548 gfx_v10_0_write_data_to_reg(ring, 0, false, 7549 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7550 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7551 7552 /* OA */ 7553 gfx_v10_0_write_data_to_reg(ring, 0, false, 7554 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7555 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7556 } 7557 7558 static int gfx_v10_0_early_init(void *handle) 7559 { 7560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7561 7562 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7563 7564 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7565 case IP_VERSION(10, 1, 10): 7566 case IP_VERSION(10, 1, 1): 7567 case IP_VERSION(10, 1, 2): 7568 case IP_VERSION(10, 1, 3): 7569 case IP_VERSION(10, 1, 4): 7570 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7571 break; 7572 case IP_VERSION(10, 3, 0): 7573 case IP_VERSION(10, 3, 2): 7574 case IP_VERSION(10, 3, 1): 7575 case IP_VERSION(10, 3, 4): 7576 case IP_VERSION(10, 3, 5): 7577 case IP_VERSION(10, 3, 6): 7578 case IP_VERSION(10, 3, 3): 7579 case IP_VERSION(10, 3, 7): 7580 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7581 break; 7582 default: 7583 break; 7584 } 7585 7586 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7587 AMDGPU_MAX_COMPUTE_RINGS); 7588 7589 gfx_v10_0_set_kiq_pm4_funcs(adev); 7590 gfx_v10_0_set_ring_funcs(adev); 7591 gfx_v10_0_set_irq_funcs(adev); 7592 gfx_v10_0_set_gds_init(adev); 7593 gfx_v10_0_set_rlc_funcs(adev); 7594 gfx_v10_0_set_mqd_funcs(adev); 7595 7596 /* init rlcg reg access ctrl */ 7597 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7598 7599 return gfx_v10_0_init_microcode(adev); 7600 } 7601 7602 static int gfx_v10_0_late_init(void *handle) 7603 { 7604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7605 int r; 7606 7607 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7608 if (r) 7609 return r; 7610 7611 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7612 if (r) 7613 return r; 7614 7615 return 0; 7616 } 7617 7618 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7619 { 7620 uint32_t rlc_cntl; 7621 7622 /* if RLC is not enabled, do nothing */ 7623 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7624 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7625 } 7626 7627 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7628 { 7629 uint32_t data; 7630 unsigned int i; 7631 7632 data = RLC_SAFE_MODE__CMD_MASK; 7633 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7634 7635 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7636 case IP_VERSION(10, 3, 0): 7637 case IP_VERSION(10, 3, 2): 7638 case IP_VERSION(10, 3, 1): 7639 case IP_VERSION(10, 3, 4): 7640 case IP_VERSION(10, 3, 5): 7641 case IP_VERSION(10, 3, 6): 7642 case IP_VERSION(10, 3, 3): 7643 case IP_VERSION(10, 3, 7): 7644 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7645 7646 /* wait for RLC_SAFE_MODE */ 7647 for (i = 0; i < adev->usec_timeout; i++) { 7648 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7649 RLC_SAFE_MODE, CMD)) 7650 break; 7651 udelay(1); 7652 } 7653 break; 7654 default: 7655 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7656 7657 /* wait for RLC_SAFE_MODE */ 7658 for (i = 0; i < adev->usec_timeout; i++) { 7659 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7660 RLC_SAFE_MODE, CMD)) 7661 break; 7662 udelay(1); 7663 } 7664 break; 7665 } 7666 } 7667 7668 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7669 { 7670 uint32_t data; 7671 7672 data = RLC_SAFE_MODE__CMD_MASK; 7673 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7674 case IP_VERSION(10, 3, 0): 7675 case IP_VERSION(10, 3, 2): 7676 case IP_VERSION(10, 3, 1): 7677 case IP_VERSION(10, 3, 4): 7678 case IP_VERSION(10, 3, 5): 7679 case IP_VERSION(10, 3, 6): 7680 case IP_VERSION(10, 3, 3): 7681 case IP_VERSION(10, 3, 7): 7682 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7683 break; 7684 default: 7685 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7686 break; 7687 } 7688 } 7689 7690 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7691 bool enable) 7692 { 7693 uint32_t data, def; 7694 7695 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7696 return; 7697 7698 /* It is disabled by HW by default */ 7699 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7700 /* 0 - Disable some blocks' MGCG */ 7701 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7702 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7703 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7704 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7705 7706 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7707 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7708 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7709 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7710 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7711 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7712 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7713 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7714 7715 if (def != data) 7716 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7717 7718 /* MGLS is a global flag to control all MGLS in GFX */ 7719 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7720 /* 2 - RLC memory Light sleep */ 7721 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7722 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7723 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7724 if (def != data) 7725 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7726 } 7727 /* 3 - CP memory Light sleep */ 7728 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7729 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7730 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7731 if (def != data) 7732 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7733 } 7734 } 7735 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7736 /* 1 - MGCG_OVERRIDE */ 7737 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7738 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7739 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7740 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7741 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7742 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7743 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7744 if (def != data) 7745 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7746 7747 /* 2 - disable MGLS in CP */ 7748 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7749 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7750 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7751 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7752 } 7753 7754 /* 3 - disable MGLS in RLC */ 7755 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7756 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7757 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7758 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7759 } 7760 7761 } 7762 } 7763 7764 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7765 bool enable) 7766 { 7767 uint32_t data, def; 7768 7769 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7770 return; 7771 7772 /* Enable 3D CGCG/CGLS */ 7773 if (enable) { 7774 /* write cmd to clear cgcg/cgls ov */ 7775 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7776 7777 /* unset CGCG override */ 7778 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7779 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7780 7781 /* update CGCG and CGLS override bits */ 7782 if (def != data) 7783 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7784 7785 /* enable 3Dcgcg FSM(0x0000363f) */ 7786 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7787 data = 0; 7788 7789 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7790 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7791 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7792 7793 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7794 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7795 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7796 7797 if (def != data) 7798 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7799 7800 /* set IDLE_POLL_COUNT(0x00900100) */ 7801 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7802 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7803 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7804 if (def != data) 7805 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7806 } else { 7807 /* Disable CGCG/CGLS */ 7808 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7809 7810 /* disable cgcg, cgls should be disabled */ 7811 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7812 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7813 7814 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7815 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7816 7817 /* disable cgcg and cgls in FSM */ 7818 if (def != data) 7819 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7820 } 7821 } 7822 7823 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7824 bool enable) 7825 { 7826 uint32_t def, data; 7827 7828 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7829 return; 7830 7831 if (enable) { 7832 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7833 7834 /* unset CGCG override */ 7835 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7836 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7837 7838 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7839 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7840 7841 /* update CGCG and CGLS override bits */ 7842 if (def != data) 7843 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7844 7845 /* enable cgcg FSM(0x0000363F) */ 7846 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7847 data = 0; 7848 7849 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7850 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7851 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7852 7853 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7854 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7855 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7856 7857 if (def != data) 7858 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7859 7860 /* set IDLE_POLL_COUNT(0x00900100) */ 7861 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7862 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7863 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7864 if (def != data) 7865 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7866 } else { 7867 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7868 7869 /* reset CGCG/CGLS bits */ 7870 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7871 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7872 7873 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7874 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7875 7876 /* disable cgcg and cgls in FSM */ 7877 if (def != data) 7878 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7879 } 7880 } 7881 7882 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7883 bool enable) 7884 { 7885 uint32_t def, data; 7886 7887 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7888 return; 7889 7890 if (enable) { 7891 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7892 /* unset FGCG override */ 7893 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7894 /* update FGCG override bits */ 7895 if (def != data) 7896 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7897 7898 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7899 /* unset RLC SRAM CLK GATER override */ 7900 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7901 /* update RLC SRAM CLK GATER override bits */ 7902 if (def != data) 7903 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7904 } else { 7905 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7906 /* reset FGCG bits */ 7907 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7908 /* disable FGCG*/ 7909 if (def != data) 7910 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7911 7912 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7913 /* reset RLC SRAM CLK GATER bits */ 7914 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7915 /* disable RLC SRAM CLK*/ 7916 if (def != data) 7917 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7918 } 7919 } 7920 7921 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7922 { 7923 uint32_t reg_data = 0; 7924 uint32_t reg_idx = 0; 7925 uint32_t i; 7926 7927 const uint32_t tcp_ctrl_regs[] = { 7928 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7929 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7930 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7931 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7932 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7933 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7934 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7935 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7936 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7937 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7938 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7939 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7940 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7941 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7942 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7943 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7944 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7945 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7946 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7947 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7948 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7949 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7950 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7951 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7952 }; 7953 7954 const uint32_t tcp_ctrl_regs_nv12[] = { 7955 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7956 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7957 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7958 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7959 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7960 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7961 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7962 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7963 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7964 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7965 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7966 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7967 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7968 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7969 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7970 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7971 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7972 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7973 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7974 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7975 }; 7976 7977 const uint32_t sm_ctlr_regs[] = { 7978 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7979 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7980 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7981 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7982 }; 7983 7984 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 7985 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7986 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7987 tcp_ctrl_regs_nv12[i]; 7988 reg_data = RREG32(reg_idx); 7989 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7990 WREG32(reg_idx, reg_data); 7991 } 7992 } else { 7993 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7994 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7995 tcp_ctrl_regs[i]; 7996 reg_data = RREG32(reg_idx); 7997 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7998 WREG32(reg_idx, reg_data); 7999 } 8000 } 8001 8002 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8003 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8004 sm_ctlr_regs[i]; 8005 reg_data = RREG32(reg_idx); 8006 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8007 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8008 WREG32(reg_idx, reg_data); 8009 } 8010 } 8011 8012 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8013 bool enable) 8014 { 8015 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8016 8017 if (enable) { 8018 /* enable FGCG firstly*/ 8019 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8020 /* CGCG/CGLS should be enabled after MGCG/MGLS 8021 * === MGCG + MGLS === 8022 */ 8023 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8024 /* === CGCG /CGLS for GFX 3D Only === */ 8025 gfx_v10_0_update_3d_clock_gating(adev, enable); 8026 /* === CGCG + CGLS === */ 8027 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8028 8029 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8030 IP_VERSION(10, 1, 10)) || 8031 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8032 IP_VERSION(10, 1, 1)) || 8033 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8034 IP_VERSION(10, 1, 2))) 8035 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8036 } else { 8037 /* CGCG/CGLS should be disabled before MGCG/MGLS 8038 * === CGCG + CGLS === 8039 */ 8040 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8041 /* === CGCG /CGLS for GFX 3D Only === */ 8042 gfx_v10_0_update_3d_clock_gating(adev, enable); 8043 /* === MGCG + MGLS === */ 8044 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8045 /* disable fgcg at last*/ 8046 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8047 } 8048 8049 if (adev->cg_flags & 8050 (AMD_CG_SUPPORT_GFX_MGCG | 8051 AMD_CG_SUPPORT_GFX_CGLS | 8052 AMD_CG_SUPPORT_GFX_CGCG | 8053 AMD_CG_SUPPORT_GFX_3D_CGCG | 8054 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8055 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8056 8057 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8058 8059 return 0; 8060 } 8061 8062 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8063 unsigned int vmid) 8064 { 8065 u32 data; 8066 8067 /* not for *_SOC15 */ 8068 data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL); 8069 8070 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8071 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8072 8073 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8074 } 8075 8076 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8077 { 8078 amdgpu_gfx_off_ctrl(adev, false); 8079 8080 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8081 8082 amdgpu_gfx_off_ctrl(adev, true); 8083 } 8084 8085 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8086 uint32_t offset, 8087 struct soc15_reg_rlcg *entries, int arr_size) 8088 { 8089 int i; 8090 uint32_t reg; 8091 8092 if (!entries) 8093 return false; 8094 8095 for (i = 0; i < arr_size; i++) { 8096 const struct soc15_reg_rlcg *entry; 8097 8098 entry = &entries[i]; 8099 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8100 if (offset == reg) 8101 return true; 8102 } 8103 8104 return false; 8105 } 8106 8107 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8108 { 8109 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8110 } 8111 8112 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8113 { 8114 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8115 8116 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8117 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8118 else 8119 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8120 8121 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8122 8123 /* 8124 * CGPG enablement required and the register to program the hysteresis value 8125 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8126 * in refclk count. Note that RLC FW is modified to take 16 bits from 8127 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8128 * 8129 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8130 * of CGPG enablement starting point. 8131 * Power/performance team will optimize it and might give a new value later. 8132 */ 8133 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8134 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8135 case IP_VERSION(10, 3, 1): 8136 case IP_VERSION(10, 3, 3): 8137 case IP_VERSION(10, 3, 6): 8138 case IP_VERSION(10, 3, 7): 8139 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8140 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8141 break; 8142 default: 8143 break; 8144 } 8145 } 8146 } 8147 8148 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8149 { 8150 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8151 8152 gfx_v10_cntl_power_gating(adev, enable); 8153 8154 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8155 } 8156 8157 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8158 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8159 .set_safe_mode = gfx_v10_0_set_safe_mode, 8160 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8161 .init = gfx_v10_0_rlc_init, 8162 .get_csb_size = gfx_v10_0_get_csb_size, 8163 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8164 .resume = gfx_v10_0_rlc_resume, 8165 .stop = gfx_v10_0_rlc_stop, 8166 .reset = gfx_v10_0_rlc_reset, 8167 .start = gfx_v10_0_rlc_start, 8168 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8169 }; 8170 8171 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8172 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8173 .set_safe_mode = gfx_v10_0_set_safe_mode, 8174 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8175 .init = gfx_v10_0_rlc_init, 8176 .get_csb_size = gfx_v10_0_get_csb_size, 8177 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8178 .resume = gfx_v10_0_rlc_resume, 8179 .stop = gfx_v10_0_rlc_stop, 8180 .reset = gfx_v10_0_rlc_reset, 8181 .start = gfx_v10_0_rlc_start, 8182 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8183 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8184 }; 8185 8186 static int gfx_v10_0_set_powergating_state(void *handle, 8187 enum amd_powergating_state state) 8188 { 8189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8190 bool enable = (state == AMD_PG_STATE_GATE); 8191 8192 if (amdgpu_sriov_vf(adev)) 8193 return 0; 8194 8195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8196 case IP_VERSION(10, 1, 10): 8197 case IP_VERSION(10, 1, 1): 8198 case IP_VERSION(10, 1, 2): 8199 case IP_VERSION(10, 3, 0): 8200 case IP_VERSION(10, 3, 2): 8201 case IP_VERSION(10, 3, 4): 8202 case IP_VERSION(10, 3, 5): 8203 amdgpu_gfx_off_ctrl(adev, enable); 8204 break; 8205 case IP_VERSION(10, 3, 1): 8206 case IP_VERSION(10, 3, 3): 8207 case IP_VERSION(10, 3, 6): 8208 case IP_VERSION(10, 3, 7): 8209 if (!enable) 8210 amdgpu_gfx_off_ctrl(adev, false); 8211 8212 gfx_v10_cntl_pg(adev, enable); 8213 8214 if (enable) 8215 amdgpu_gfx_off_ctrl(adev, true); 8216 8217 break; 8218 default: 8219 break; 8220 } 8221 return 0; 8222 } 8223 8224 static int gfx_v10_0_set_clockgating_state(void *handle, 8225 enum amd_clockgating_state state) 8226 { 8227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8228 8229 if (amdgpu_sriov_vf(adev)) 8230 return 0; 8231 8232 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8233 case IP_VERSION(10, 1, 10): 8234 case IP_VERSION(10, 1, 1): 8235 case IP_VERSION(10, 1, 2): 8236 case IP_VERSION(10, 3, 0): 8237 case IP_VERSION(10, 3, 2): 8238 case IP_VERSION(10, 3, 1): 8239 case IP_VERSION(10, 3, 4): 8240 case IP_VERSION(10, 3, 5): 8241 case IP_VERSION(10, 3, 6): 8242 case IP_VERSION(10, 3, 3): 8243 case IP_VERSION(10, 3, 7): 8244 gfx_v10_0_update_gfx_clock_gating(adev, 8245 state == AMD_CG_STATE_GATE); 8246 break; 8247 default: 8248 break; 8249 } 8250 return 0; 8251 } 8252 8253 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8254 { 8255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8256 int data; 8257 8258 /* AMD_CG_SUPPORT_GFX_FGCG */ 8259 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8260 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8261 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8262 8263 /* AMD_CG_SUPPORT_GFX_MGCG */ 8264 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8265 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8266 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8267 8268 /* AMD_CG_SUPPORT_GFX_CGCG */ 8269 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8270 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8271 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8272 8273 /* AMD_CG_SUPPORT_GFX_CGLS */ 8274 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8275 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8276 8277 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8278 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8279 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8280 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8281 8282 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8283 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8284 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8285 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8286 8287 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8288 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8289 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8290 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8291 8292 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8293 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8294 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8295 } 8296 8297 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8298 { 8299 /* gfx10 is 32bit rptr*/ 8300 return *(uint32_t *)ring->rptr_cpu_addr; 8301 } 8302 8303 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8304 { 8305 struct amdgpu_device *adev = ring->adev; 8306 u64 wptr; 8307 8308 /* XXX check if swapping is necessary on BE */ 8309 if (ring->use_doorbell) { 8310 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8311 } else { 8312 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8313 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8314 } 8315 8316 return wptr; 8317 } 8318 8319 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8320 { 8321 struct amdgpu_device *adev = ring->adev; 8322 uint32_t *wptr_saved; 8323 uint32_t *is_queue_unmap; 8324 uint64_t aggregated_db_index; 8325 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8326 uint64_t wptr_tmp; 8327 8328 if (ring->is_mes_queue) { 8329 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8330 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8331 sizeof(uint32_t)); 8332 aggregated_db_index = 8333 amdgpu_mes_get_aggregated_doorbell_index(adev, 8334 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8335 8336 wptr_tmp = ring->wptr & ring->buf_mask; 8337 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8338 *wptr_saved = wptr_tmp; 8339 /* assume doorbell always being used by mes mapped queue */ 8340 if (*is_queue_unmap) { 8341 WDOORBELL64(aggregated_db_index, wptr_tmp); 8342 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8343 } else { 8344 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8345 8346 if (*is_queue_unmap) 8347 WDOORBELL64(aggregated_db_index, wptr_tmp); 8348 } 8349 } else { 8350 if (ring->use_doorbell) { 8351 /* XXX check if swapping is necessary on BE */ 8352 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8353 ring->wptr); 8354 WDOORBELL64(ring->doorbell_index, ring->wptr); 8355 } else { 8356 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8357 lower_32_bits(ring->wptr)); 8358 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8359 upper_32_bits(ring->wptr)); 8360 } 8361 } 8362 } 8363 8364 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8365 { 8366 /* gfx10 hardware is 32bit rptr */ 8367 return *(uint32_t *)ring->rptr_cpu_addr; 8368 } 8369 8370 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8371 { 8372 u64 wptr; 8373 8374 /* XXX check if swapping is necessary on BE */ 8375 if (ring->use_doorbell) 8376 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8377 else 8378 BUG(); 8379 return wptr; 8380 } 8381 8382 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8383 { 8384 struct amdgpu_device *adev = ring->adev; 8385 uint32_t *wptr_saved; 8386 uint32_t *is_queue_unmap; 8387 uint64_t aggregated_db_index; 8388 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8389 uint64_t wptr_tmp; 8390 8391 if (ring->is_mes_queue) { 8392 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8393 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8394 sizeof(uint32_t)); 8395 aggregated_db_index = 8396 amdgpu_mes_get_aggregated_doorbell_index(adev, 8397 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8398 8399 wptr_tmp = ring->wptr & ring->buf_mask; 8400 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8401 *wptr_saved = wptr_tmp; 8402 /* assume doorbell always used by mes mapped queue */ 8403 if (*is_queue_unmap) { 8404 WDOORBELL64(aggregated_db_index, wptr_tmp); 8405 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8406 } else { 8407 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8408 8409 if (*is_queue_unmap) 8410 WDOORBELL64(aggregated_db_index, wptr_tmp); 8411 } 8412 } else { 8413 /* XXX check if swapping is necessary on BE */ 8414 if (ring->use_doorbell) { 8415 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8416 ring->wptr); 8417 WDOORBELL64(ring->doorbell_index, ring->wptr); 8418 } else { 8419 BUG(); /* only DOORBELL method supported on gfx10 now */ 8420 } 8421 } 8422 } 8423 8424 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8425 { 8426 struct amdgpu_device *adev = ring->adev; 8427 u32 ref_and_mask, reg_mem_engine; 8428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8429 8430 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8431 switch (ring->me) { 8432 case 1: 8433 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8434 break; 8435 case 2: 8436 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8437 break; 8438 default: 8439 return; 8440 } 8441 reg_mem_engine = 0; 8442 } else { 8443 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8444 reg_mem_engine = 1; /* pfp */ 8445 } 8446 8447 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8448 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8449 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8450 ref_and_mask, ref_and_mask, 0x20); 8451 } 8452 8453 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8454 struct amdgpu_job *job, 8455 struct amdgpu_ib *ib, 8456 uint32_t flags) 8457 { 8458 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8459 u32 header, control = 0; 8460 8461 if (ib->flags & AMDGPU_IB_FLAG_CE) 8462 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8463 else 8464 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8465 8466 control |= ib->length_dw | (vmid << 24); 8467 8468 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8469 control |= INDIRECT_BUFFER_PRE_ENB(1); 8470 8471 if (flags & AMDGPU_IB_PREEMPTED) 8472 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8473 8474 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8475 gfx_v10_0_ring_emit_de_meta(ring, 8476 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8477 } 8478 8479 if (ring->is_mes_queue) 8480 /* inherit vmid from mqd */ 8481 control |= 0x400000; 8482 8483 amdgpu_ring_write(ring, header); 8484 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8485 amdgpu_ring_write(ring, 8486 #ifdef __BIG_ENDIAN 8487 (2 << 0) | 8488 #endif 8489 lower_32_bits(ib->gpu_addr)); 8490 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8491 amdgpu_ring_write(ring, control); 8492 } 8493 8494 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8495 struct amdgpu_job *job, 8496 struct amdgpu_ib *ib, 8497 uint32_t flags) 8498 { 8499 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8500 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8501 8502 if (ring->is_mes_queue) 8503 /* inherit vmid from mqd */ 8504 control |= 0x40000000; 8505 8506 /* Currently, there is a high possibility to get wave ID mismatch 8507 * between ME and GDS, leading to a hw deadlock, because ME generates 8508 * different wave IDs than the GDS expects. This situation happens 8509 * randomly when at least 5 compute pipes use GDS ordered append. 8510 * The wave IDs generated by ME are also wrong after suspend/resume. 8511 * Those are probably bugs somewhere else in the kernel driver. 8512 * 8513 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8514 * GDS to 0 for this ring (me/pipe). 8515 */ 8516 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8517 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8518 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8519 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8520 } 8521 8522 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8523 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8524 amdgpu_ring_write(ring, 8525 #ifdef __BIG_ENDIAN 8526 (2 << 0) | 8527 #endif 8528 lower_32_bits(ib->gpu_addr)); 8529 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8530 amdgpu_ring_write(ring, control); 8531 } 8532 8533 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8534 u64 seq, unsigned int flags) 8535 { 8536 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8537 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8538 8539 /* RELEASE_MEM - flush caches, send int */ 8540 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8541 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8542 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8543 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8544 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8545 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8546 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8547 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8548 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8549 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8550 8551 /* 8552 * the address should be Qword aligned if 64bit write, Dword 8553 * aligned if only send 32bit data low (discard data high) 8554 */ 8555 if (write64bit) 8556 BUG_ON(addr & 0x7); 8557 else 8558 BUG_ON(addr & 0x3); 8559 amdgpu_ring_write(ring, lower_32_bits(addr)); 8560 amdgpu_ring_write(ring, upper_32_bits(addr)); 8561 amdgpu_ring_write(ring, lower_32_bits(seq)); 8562 amdgpu_ring_write(ring, upper_32_bits(seq)); 8563 amdgpu_ring_write(ring, ring->is_mes_queue ? 8564 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8565 } 8566 8567 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8568 { 8569 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8570 uint32_t seq = ring->fence_drv.sync_seq; 8571 uint64_t addr = ring->fence_drv.gpu_addr; 8572 8573 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8574 upper_32_bits(addr), seq, 0xffffffff, 4); 8575 } 8576 8577 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8578 uint16_t pasid, uint32_t flush_type, 8579 bool all_hub, uint8_t dst_sel) 8580 { 8581 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8582 amdgpu_ring_write(ring, 8583 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8584 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8585 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8586 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8587 } 8588 8589 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8590 unsigned int vmid, uint64_t pd_addr) 8591 { 8592 if (ring->is_mes_queue) 8593 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8594 else 8595 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8596 8597 /* compute doesn't have PFP */ 8598 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8599 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8600 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8601 amdgpu_ring_write(ring, 0x0); 8602 } 8603 } 8604 8605 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8606 u64 seq, unsigned int flags) 8607 { 8608 struct amdgpu_device *adev = ring->adev; 8609 8610 /* we only allocate 32bit for each seq wb address */ 8611 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8612 8613 /* write fence seq to the "addr" */ 8614 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8615 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8616 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8617 amdgpu_ring_write(ring, lower_32_bits(addr)); 8618 amdgpu_ring_write(ring, upper_32_bits(addr)); 8619 amdgpu_ring_write(ring, lower_32_bits(seq)); 8620 8621 if (flags & AMDGPU_FENCE_FLAG_INT) { 8622 /* set register to trigger INT */ 8623 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8624 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8625 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8626 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8627 amdgpu_ring_write(ring, 0); 8628 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8629 } 8630 } 8631 8632 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8633 { 8634 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8635 amdgpu_ring_write(ring, 0); 8636 } 8637 8638 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8639 uint32_t flags) 8640 { 8641 uint32_t dw2 = 0; 8642 8643 if (ring->adev->gfx.mcbp) 8644 gfx_v10_0_ring_emit_ce_meta(ring, 8645 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8646 8647 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8648 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8649 /* set load_global_config & load_global_uconfig */ 8650 dw2 |= 0x8001; 8651 /* set load_cs_sh_regs */ 8652 dw2 |= 0x01000000; 8653 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8654 dw2 |= 0x10002; 8655 8656 /* set load_ce_ram if preamble presented */ 8657 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8658 dw2 |= 0x10000000; 8659 } else { 8660 /* still load_ce_ram if this is the first time preamble presented 8661 * although there is no context switch happens. 8662 */ 8663 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8664 dw2 |= 0x10000000; 8665 } 8666 8667 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8668 amdgpu_ring_write(ring, dw2); 8669 amdgpu_ring_write(ring, 0); 8670 } 8671 8672 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8673 uint64_t addr) 8674 { 8675 unsigned int ret; 8676 8677 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8678 amdgpu_ring_write(ring, lower_32_bits(addr)); 8679 amdgpu_ring_write(ring, upper_32_bits(addr)); 8680 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8681 amdgpu_ring_write(ring, 0); 8682 ret = ring->wptr & ring->buf_mask; 8683 /* patch dummy value later */ 8684 amdgpu_ring_write(ring, 0); 8685 8686 return ret; 8687 } 8688 8689 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8690 { 8691 int i, r = 0; 8692 struct amdgpu_device *adev = ring->adev; 8693 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8694 struct amdgpu_ring *kiq_ring = &kiq->ring; 8695 unsigned long flags; 8696 8697 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8698 return -EINVAL; 8699 8700 spin_lock_irqsave(&kiq->ring_lock, flags); 8701 8702 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8703 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8704 return -ENOMEM; 8705 } 8706 8707 /* assert preemption condition */ 8708 amdgpu_ring_set_preempt_cond_exec(ring, false); 8709 8710 /* assert IB preemption, emit the trailing fence */ 8711 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8712 ring->trail_fence_gpu_addr, 8713 ++ring->trail_seq); 8714 amdgpu_ring_commit(kiq_ring); 8715 8716 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8717 8718 /* poll the trailing fence */ 8719 for (i = 0; i < adev->usec_timeout; i++) { 8720 if (ring->trail_seq == 8721 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8722 break; 8723 udelay(1); 8724 } 8725 8726 if (i >= adev->usec_timeout) { 8727 r = -EINVAL; 8728 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8729 } 8730 8731 /* deassert preemption condition */ 8732 amdgpu_ring_set_preempt_cond_exec(ring, true); 8733 return r; 8734 } 8735 8736 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8737 { 8738 struct amdgpu_device *adev = ring->adev; 8739 struct v10_ce_ib_state ce_payload = {0}; 8740 uint64_t offset, ce_payload_gpu_addr; 8741 void *ce_payload_cpu_addr; 8742 int cnt; 8743 8744 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8745 8746 if (ring->is_mes_queue) { 8747 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8748 gfx[0].gfx_meta_data) + 8749 offsetof(struct v10_gfx_meta_data, ce_payload); 8750 ce_payload_gpu_addr = 8751 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8752 ce_payload_cpu_addr = 8753 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8754 } else { 8755 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8756 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8757 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8758 } 8759 8760 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8761 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8762 WRITE_DATA_DST_SEL(8) | 8763 WR_CONFIRM) | 8764 WRITE_DATA_CACHE_POLICY(0)); 8765 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8766 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8767 8768 if (resume) 8769 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8770 sizeof(ce_payload) >> 2); 8771 else 8772 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8773 sizeof(ce_payload) >> 2); 8774 } 8775 8776 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8777 { 8778 struct amdgpu_device *adev = ring->adev; 8779 struct v10_de_ib_state de_payload = {0}; 8780 uint64_t offset, gds_addr, de_payload_gpu_addr; 8781 void *de_payload_cpu_addr; 8782 int cnt; 8783 8784 if (ring->is_mes_queue) { 8785 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8786 gfx[0].gfx_meta_data) + 8787 offsetof(struct v10_gfx_meta_data, de_payload); 8788 de_payload_gpu_addr = 8789 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8790 de_payload_cpu_addr = 8791 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8792 8793 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8794 gfx[0].gds_backup) + 8795 offsetof(struct v10_gfx_meta_data, de_payload); 8796 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8797 } else { 8798 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8799 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8800 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8801 8802 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8803 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8804 PAGE_SIZE); 8805 } 8806 8807 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8808 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8809 8810 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8811 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8812 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8813 WRITE_DATA_DST_SEL(8) | 8814 WR_CONFIRM) | 8815 WRITE_DATA_CACHE_POLICY(0)); 8816 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8817 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8818 8819 if (resume) 8820 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8821 sizeof(de_payload) >> 2); 8822 else 8823 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8824 sizeof(de_payload) >> 2); 8825 } 8826 8827 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8828 bool secure) 8829 { 8830 uint32_t v = secure ? FRAME_TMZ : 0; 8831 8832 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8833 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8834 } 8835 8836 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8837 uint32_t reg_val_offs) 8838 { 8839 struct amdgpu_device *adev = ring->adev; 8840 8841 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8842 amdgpu_ring_write(ring, 0 | /* src: register*/ 8843 (5 << 8) | /* dst: memory */ 8844 (1 << 20)); /* write confirm */ 8845 amdgpu_ring_write(ring, reg); 8846 amdgpu_ring_write(ring, 0); 8847 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8848 reg_val_offs * 4)); 8849 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8850 reg_val_offs * 4)); 8851 } 8852 8853 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8854 uint32_t val) 8855 { 8856 uint32_t cmd = 0; 8857 8858 switch (ring->funcs->type) { 8859 case AMDGPU_RING_TYPE_GFX: 8860 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8861 break; 8862 case AMDGPU_RING_TYPE_KIQ: 8863 cmd = (1 << 16); /* no inc addr */ 8864 break; 8865 default: 8866 cmd = WR_CONFIRM; 8867 break; 8868 } 8869 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8870 amdgpu_ring_write(ring, cmd); 8871 amdgpu_ring_write(ring, reg); 8872 amdgpu_ring_write(ring, 0); 8873 amdgpu_ring_write(ring, val); 8874 } 8875 8876 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8877 uint32_t val, uint32_t mask) 8878 { 8879 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8880 } 8881 8882 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8883 uint32_t reg0, uint32_t reg1, 8884 uint32_t ref, uint32_t mask) 8885 { 8886 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8887 struct amdgpu_device *adev = ring->adev; 8888 bool fw_version_ok = false; 8889 8890 fw_version_ok = adev->gfx.cp_fw_write_wait; 8891 8892 if (fw_version_ok) 8893 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8894 ref, mask, 0x20); 8895 else 8896 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8897 ref, mask); 8898 } 8899 8900 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8901 unsigned int vmid) 8902 { 8903 struct amdgpu_device *adev = ring->adev; 8904 uint32_t value = 0; 8905 8906 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8907 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8908 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8909 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8910 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8911 } 8912 8913 static void 8914 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8915 uint32_t me, uint32_t pipe, 8916 enum amdgpu_interrupt_state state) 8917 { 8918 uint32_t cp_int_cntl, cp_int_cntl_reg; 8919 8920 if (!me) { 8921 switch (pipe) { 8922 case 0: 8923 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8924 break; 8925 case 1: 8926 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8927 break; 8928 default: 8929 DRM_DEBUG("invalid pipe %d\n", pipe); 8930 return; 8931 } 8932 } else { 8933 DRM_DEBUG("invalid me %d\n", me); 8934 return; 8935 } 8936 8937 switch (state) { 8938 case AMDGPU_IRQ_STATE_DISABLE: 8939 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8940 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8941 TIME_STAMP_INT_ENABLE, 0); 8942 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8943 break; 8944 case AMDGPU_IRQ_STATE_ENABLE: 8945 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8946 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8947 TIME_STAMP_INT_ENABLE, 1); 8948 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8949 break; 8950 default: 8951 break; 8952 } 8953 } 8954 8955 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8956 int me, int pipe, 8957 enum amdgpu_interrupt_state state) 8958 { 8959 u32 mec_int_cntl, mec_int_cntl_reg; 8960 8961 /* 8962 * amdgpu controls only the first MEC. That's why this function only 8963 * handles the setting of interrupts for this specific MEC. All other 8964 * pipes' interrupts are set by amdkfd. 8965 */ 8966 8967 if (me == 1) { 8968 switch (pipe) { 8969 case 0: 8970 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8971 break; 8972 case 1: 8973 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8974 break; 8975 case 2: 8976 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8977 break; 8978 case 3: 8979 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8980 break; 8981 default: 8982 DRM_DEBUG("invalid pipe %d\n", pipe); 8983 return; 8984 } 8985 } else { 8986 DRM_DEBUG("invalid me %d\n", me); 8987 return; 8988 } 8989 8990 switch (state) { 8991 case AMDGPU_IRQ_STATE_DISABLE: 8992 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8993 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8994 TIME_STAMP_INT_ENABLE, 0); 8995 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8996 break; 8997 case AMDGPU_IRQ_STATE_ENABLE: 8998 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8999 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9000 TIME_STAMP_INT_ENABLE, 1); 9001 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9002 break; 9003 default: 9004 break; 9005 } 9006 } 9007 9008 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9009 struct amdgpu_irq_src *src, 9010 unsigned int type, 9011 enum amdgpu_interrupt_state state) 9012 { 9013 switch (type) { 9014 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9015 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9016 break; 9017 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9018 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9019 break; 9020 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9021 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9022 break; 9023 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9024 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9025 break; 9026 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9027 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9028 break; 9029 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9030 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9031 break; 9032 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9033 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9034 break; 9035 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9036 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9037 break; 9038 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9039 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9040 break; 9041 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9042 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9043 break; 9044 default: 9045 break; 9046 } 9047 return 0; 9048 } 9049 9050 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9051 struct amdgpu_irq_src *source, 9052 struct amdgpu_iv_entry *entry) 9053 { 9054 int i; 9055 u8 me_id, pipe_id, queue_id; 9056 struct amdgpu_ring *ring; 9057 uint32_t mes_queue_id = entry->src_data[0]; 9058 9059 DRM_DEBUG("IH: CP EOP\n"); 9060 9061 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 9062 struct amdgpu_mes_queue *queue; 9063 9064 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 9065 9066 spin_lock(&adev->mes.queue_id_lock); 9067 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 9068 if (queue) { 9069 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 9070 amdgpu_fence_process(queue->ring); 9071 } 9072 spin_unlock(&adev->mes.queue_id_lock); 9073 } else { 9074 me_id = (entry->ring_id & 0x0c) >> 2; 9075 pipe_id = (entry->ring_id & 0x03) >> 0; 9076 queue_id = (entry->ring_id & 0x70) >> 4; 9077 9078 switch (me_id) { 9079 case 0: 9080 if (pipe_id == 0) 9081 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9082 else 9083 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9084 break; 9085 case 1: 9086 case 2: 9087 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9088 ring = &adev->gfx.compute_ring[i]; 9089 /* Per-queue interrupt is supported for MEC starting from VI. 9090 * The interrupt can only be enabled/disabled per pipe instead 9091 * of per queue. 9092 */ 9093 if ((ring->me == me_id) && 9094 (ring->pipe == pipe_id) && 9095 (ring->queue == queue_id)) 9096 amdgpu_fence_process(ring); 9097 } 9098 break; 9099 } 9100 } 9101 9102 return 0; 9103 } 9104 9105 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9106 struct amdgpu_irq_src *source, 9107 unsigned int type, 9108 enum amdgpu_interrupt_state state) 9109 { 9110 switch (state) { 9111 case AMDGPU_IRQ_STATE_DISABLE: 9112 case AMDGPU_IRQ_STATE_ENABLE: 9113 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9114 PRIV_REG_INT_ENABLE, 9115 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9116 break; 9117 default: 9118 break; 9119 } 9120 9121 return 0; 9122 } 9123 9124 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9125 struct amdgpu_irq_src *source, 9126 unsigned int type, 9127 enum amdgpu_interrupt_state state) 9128 { 9129 switch (state) { 9130 case AMDGPU_IRQ_STATE_DISABLE: 9131 case AMDGPU_IRQ_STATE_ENABLE: 9132 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9133 PRIV_INSTR_INT_ENABLE, 9134 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9135 break; 9136 default: 9137 break; 9138 } 9139 9140 return 0; 9141 } 9142 9143 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9144 struct amdgpu_iv_entry *entry) 9145 { 9146 u8 me_id, pipe_id, queue_id; 9147 struct amdgpu_ring *ring; 9148 int i; 9149 9150 me_id = (entry->ring_id & 0x0c) >> 2; 9151 pipe_id = (entry->ring_id & 0x03) >> 0; 9152 queue_id = (entry->ring_id & 0x70) >> 4; 9153 9154 switch (me_id) { 9155 case 0: 9156 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9157 ring = &adev->gfx.gfx_ring[i]; 9158 /* we only enabled 1 gfx queue per pipe for now */ 9159 if (ring->me == me_id && ring->pipe == pipe_id) 9160 drm_sched_fault(&ring->sched); 9161 } 9162 break; 9163 case 1: 9164 case 2: 9165 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9166 ring = &adev->gfx.compute_ring[i]; 9167 if (ring->me == me_id && ring->pipe == pipe_id && 9168 ring->queue == queue_id) 9169 drm_sched_fault(&ring->sched); 9170 } 9171 break; 9172 default: 9173 BUG(); 9174 } 9175 } 9176 9177 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9178 struct amdgpu_irq_src *source, 9179 struct amdgpu_iv_entry *entry) 9180 { 9181 DRM_ERROR("Illegal register access in command stream\n"); 9182 gfx_v10_0_handle_priv_fault(adev, entry); 9183 return 0; 9184 } 9185 9186 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9187 struct amdgpu_irq_src *source, 9188 struct amdgpu_iv_entry *entry) 9189 { 9190 DRM_ERROR("Illegal instruction in command stream\n"); 9191 gfx_v10_0_handle_priv_fault(adev, entry); 9192 return 0; 9193 } 9194 9195 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9196 struct amdgpu_irq_src *src, 9197 unsigned int type, 9198 enum amdgpu_interrupt_state state) 9199 { 9200 uint32_t tmp, target; 9201 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9202 9203 if (ring->me == 1) 9204 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9205 else 9206 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9207 target += ring->pipe; 9208 9209 switch (type) { 9210 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9211 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9212 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9213 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9214 GENERIC2_INT_ENABLE, 0); 9215 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9216 9217 tmp = RREG32_SOC15_IP(GC, target); 9218 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9219 GENERIC2_INT_ENABLE, 0); 9220 WREG32_SOC15_IP(GC, target, tmp); 9221 } else { 9222 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9223 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9224 GENERIC2_INT_ENABLE, 1); 9225 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9226 9227 tmp = RREG32_SOC15_IP(GC, target); 9228 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9229 GENERIC2_INT_ENABLE, 1); 9230 WREG32_SOC15_IP(GC, target, tmp); 9231 } 9232 break; 9233 default: 9234 BUG(); /* kiq only support GENERIC2_INT now */ 9235 break; 9236 } 9237 return 0; 9238 } 9239 9240 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9241 struct amdgpu_irq_src *source, 9242 struct amdgpu_iv_entry *entry) 9243 { 9244 u8 me_id, pipe_id, queue_id; 9245 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9246 9247 me_id = (entry->ring_id & 0x0c) >> 2; 9248 pipe_id = (entry->ring_id & 0x03) >> 0; 9249 queue_id = (entry->ring_id & 0x70) >> 4; 9250 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9251 me_id, pipe_id, queue_id); 9252 9253 amdgpu_fence_process(ring); 9254 return 0; 9255 } 9256 9257 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9258 { 9259 const unsigned int gcr_cntl = 9260 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9261 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9262 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9263 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9264 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9265 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9266 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9267 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9268 9269 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9270 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9271 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9272 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9273 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9274 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9275 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9276 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9277 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9278 } 9279 9280 static void gfx_v10_ip_print(void *handle, struct drm_printer *p) 9281 { 9282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9283 uint32_t i; 9284 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9285 9286 if (!adev->gfx.ip_dump) 9287 return; 9288 9289 for (i = 0; i < reg_count; i++) 9290 drm_printf(p, "%-50s \t 0x%08x\n", 9291 gc_reg_list_10_1[i].reg_name, 9292 adev->gfx.ip_dump[i]); 9293 } 9294 9295 static void gfx_v10_ip_dump(void *handle) 9296 { 9297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9298 uint32_t i; 9299 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9300 9301 if (!adev->gfx.ip_dump) 9302 return; 9303 9304 amdgpu_gfx_off_ctrl(adev, false); 9305 for (i = 0; i < reg_count; i++) 9306 adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9307 amdgpu_gfx_off_ctrl(adev, true); 9308 } 9309 9310 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9311 .name = "gfx_v10_0", 9312 .early_init = gfx_v10_0_early_init, 9313 .late_init = gfx_v10_0_late_init, 9314 .sw_init = gfx_v10_0_sw_init, 9315 .sw_fini = gfx_v10_0_sw_fini, 9316 .hw_init = gfx_v10_0_hw_init, 9317 .hw_fini = gfx_v10_0_hw_fini, 9318 .suspend = gfx_v10_0_suspend, 9319 .resume = gfx_v10_0_resume, 9320 .is_idle = gfx_v10_0_is_idle, 9321 .wait_for_idle = gfx_v10_0_wait_for_idle, 9322 .soft_reset = gfx_v10_0_soft_reset, 9323 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9324 .set_powergating_state = gfx_v10_0_set_powergating_state, 9325 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9326 .dump_ip_state = gfx_v10_ip_dump, 9327 .print_ip_state = gfx_v10_ip_print, 9328 }; 9329 9330 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9331 .type = AMDGPU_RING_TYPE_GFX, 9332 .align_mask = 0xff, 9333 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9334 .support_64bit_ptrs = true, 9335 .secure_submission_supported = true, 9336 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9337 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9338 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9339 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9340 5 + /* COND_EXEC */ 9341 7 + /* PIPELINE_SYNC */ 9342 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9343 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9344 4 + /* VM_FLUSH */ 9345 8 + /* FENCE for VM_FLUSH */ 9346 20 + /* GDS switch */ 9347 4 + /* double SWITCH_BUFFER, 9348 * the first COND_EXEC jump to the place 9349 * just prior to this double SWITCH_BUFFER 9350 */ 9351 5 + /* COND_EXEC */ 9352 7 + /* HDP_flush */ 9353 4 + /* VGT_flush */ 9354 14 + /* CE_META */ 9355 31 + /* DE_META */ 9356 3 + /* CNTX_CTRL */ 9357 5 + /* HDP_INVL */ 9358 8 + 8 + /* FENCE x2 */ 9359 2 + /* SWITCH_BUFFER */ 9360 8, /* gfx_v10_0_emit_mem_sync */ 9361 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9362 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9363 .emit_fence = gfx_v10_0_ring_emit_fence, 9364 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9365 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9366 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9367 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9368 .test_ring = gfx_v10_0_ring_test_ring, 9369 .test_ib = gfx_v10_0_ring_test_ib, 9370 .insert_nop = amdgpu_ring_insert_nop, 9371 .pad_ib = amdgpu_ring_generic_pad_ib, 9372 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9373 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9374 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9375 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9376 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9377 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9378 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9379 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9380 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9381 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9382 }; 9383 9384 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9385 .type = AMDGPU_RING_TYPE_COMPUTE, 9386 .align_mask = 0xff, 9387 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9388 .support_64bit_ptrs = true, 9389 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9390 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9391 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9392 .emit_frame_size = 9393 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9394 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9395 5 + /* hdp invalidate */ 9396 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9397 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9398 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9399 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9400 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9401 8, /* gfx_v10_0_emit_mem_sync */ 9402 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9403 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9404 .emit_fence = gfx_v10_0_ring_emit_fence, 9405 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9406 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9407 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9408 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9409 .test_ring = gfx_v10_0_ring_test_ring, 9410 .test_ib = gfx_v10_0_ring_test_ib, 9411 .insert_nop = amdgpu_ring_insert_nop, 9412 .pad_ib = amdgpu_ring_generic_pad_ib, 9413 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9414 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9415 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9416 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9417 }; 9418 9419 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9420 .type = AMDGPU_RING_TYPE_KIQ, 9421 .align_mask = 0xff, 9422 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9423 .support_64bit_ptrs = true, 9424 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9425 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9426 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9427 .emit_frame_size = 9428 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9429 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9430 5 + /*hdp invalidate */ 9431 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9432 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9433 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9434 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9435 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9436 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9437 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9438 .test_ring = gfx_v10_0_ring_test_ring, 9439 .test_ib = gfx_v10_0_ring_test_ib, 9440 .insert_nop = amdgpu_ring_insert_nop, 9441 .pad_ib = amdgpu_ring_generic_pad_ib, 9442 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9443 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9444 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9445 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9446 }; 9447 9448 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9449 { 9450 int i; 9451 9452 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9453 9454 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9455 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9456 9457 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9458 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9459 } 9460 9461 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9462 .set = gfx_v10_0_set_eop_interrupt_state, 9463 .process = gfx_v10_0_eop_irq, 9464 }; 9465 9466 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9467 .set = gfx_v10_0_set_priv_reg_fault_state, 9468 .process = gfx_v10_0_priv_reg_irq, 9469 }; 9470 9471 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9472 .set = gfx_v10_0_set_priv_inst_fault_state, 9473 .process = gfx_v10_0_priv_inst_irq, 9474 }; 9475 9476 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9477 .set = gfx_v10_0_kiq_set_interrupt_state, 9478 .process = gfx_v10_0_kiq_irq, 9479 }; 9480 9481 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9482 { 9483 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9484 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9485 9486 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9487 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9488 9489 adev->gfx.priv_reg_irq.num_types = 1; 9490 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9491 9492 adev->gfx.priv_inst_irq.num_types = 1; 9493 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9494 } 9495 9496 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9497 { 9498 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9499 case IP_VERSION(10, 1, 10): 9500 case IP_VERSION(10, 1, 1): 9501 case IP_VERSION(10, 1, 3): 9502 case IP_VERSION(10, 1, 4): 9503 case IP_VERSION(10, 3, 2): 9504 case IP_VERSION(10, 3, 1): 9505 case IP_VERSION(10, 3, 4): 9506 case IP_VERSION(10, 3, 5): 9507 case IP_VERSION(10, 3, 6): 9508 case IP_VERSION(10, 3, 3): 9509 case IP_VERSION(10, 3, 7): 9510 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9511 break; 9512 case IP_VERSION(10, 1, 2): 9513 case IP_VERSION(10, 3, 0): 9514 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9515 break; 9516 default: 9517 break; 9518 } 9519 } 9520 9521 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9522 { 9523 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9524 adev->gfx.config.max_sh_per_se * 9525 adev->gfx.config.max_shader_engines; 9526 9527 adev->gds.gds_size = 0x10000; 9528 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9529 adev->gds.gws_size = 64; 9530 adev->gds.oa_size = 16; 9531 } 9532 9533 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9534 { 9535 /* set gfx eng mqd */ 9536 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9537 sizeof(struct v10_gfx_mqd); 9538 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9539 gfx_v10_0_gfx_mqd_init; 9540 /* set compute eng mqd */ 9541 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9542 sizeof(struct v10_compute_mqd); 9543 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9544 gfx_v10_0_compute_mqd_init; 9545 } 9546 9547 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9548 u32 bitmap) 9549 { 9550 u32 data; 9551 9552 if (!bitmap) 9553 return; 9554 9555 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9556 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9557 9558 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9559 } 9560 9561 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9562 { 9563 u32 disabled_mask = 9564 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9565 u32 efuse_setting = 0; 9566 u32 vbios_setting = 0; 9567 9568 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9569 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9570 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9571 9572 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9573 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9574 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9575 9576 disabled_mask |= efuse_setting | vbios_setting; 9577 9578 return (~disabled_mask); 9579 } 9580 9581 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9582 { 9583 u32 wgp_idx, wgp_active_bitmap; 9584 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9585 9586 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9587 cu_active_bitmap = 0; 9588 9589 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9590 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9591 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9592 if (wgp_active_bitmap & (1 << wgp_idx)) 9593 cu_active_bitmap |= cu_bitmap_per_wgp; 9594 } 9595 9596 return cu_active_bitmap; 9597 } 9598 9599 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9600 struct amdgpu_cu_info *cu_info) 9601 { 9602 int i, j, k, counter, active_cu_number = 0; 9603 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9604 unsigned int disable_masks[4 * 2]; 9605 9606 if (!adev || !cu_info) 9607 return -EINVAL; 9608 9609 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9610 9611 mutex_lock(&adev->grbm_idx_mutex); 9612 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9613 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9614 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9615 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 9616 IP_VERSION(10, 3, 0)) || 9617 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9618 IP_VERSION(10, 3, 3)) || 9619 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9620 IP_VERSION(10, 3, 6)) || 9621 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9622 IP_VERSION(10, 3, 7))) && 9623 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9624 continue; 9625 mask = 1; 9626 ao_bitmap = 0; 9627 counter = 0; 9628 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9629 if (i < 4 && j < 2) 9630 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9631 adev, disable_masks[i * 2 + j]); 9632 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9633 cu_info->bitmap[0][i][j] = bitmap; 9634 9635 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9636 if (bitmap & mask) { 9637 if (counter < adev->gfx.config.max_cu_per_sh) 9638 ao_bitmap |= mask; 9639 counter++; 9640 } 9641 mask <<= 1; 9642 } 9643 active_cu_number += counter; 9644 if (i < 2 && j < 2) 9645 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9646 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9647 } 9648 } 9649 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9650 mutex_unlock(&adev->grbm_idx_mutex); 9651 9652 cu_info->number = active_cu_number; 9653 cu_info->ao_cu_mask = ao_cu_mask; 9654 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9655 9656 return 0; 9657 } 9658 9659 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9660 { 9661 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9662 9663 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9664 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9665 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9666 9667 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9668 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9669 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9670 9671 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9672 adev->gfx.config.max_shader_engines); 9673 disabled_sa = efuse_setting | vbios_setting; 9674 disabled_sa &= max_sa_mask; 9675 9676 return disabled_sa; 9677 } 9678 9679 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9680 { 9681 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9682 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9683 9684 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9685 9686 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9687 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9688 max_shader_engines = adev->gfx.config.max_shader_engines; 9689 9690 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9691 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9692 disabled_sa_per_se &= max_sa_per_se_mask; 9693 if (disabled_sa_per_se == max_sa_per_se_mask) { 9694 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9695 break; 9696 } 9697 } 9698 } 9699 9700 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9701 { 9702 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9703 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9704 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9705 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9706 9707 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9708 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9709 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9710 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9711 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9712 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9713 9714 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9715 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9716 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9717 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9718 9719 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9720 9721 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9722 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9723 } 9724 9725 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9726 .type = AMD_IP_BLOCK_TYPE_GFX, 9727 .major = 10, 9728 .minor = 0, 9729 .rev = 0, 9730 .funcs = &gfx_v10_0_ip_funcs, 9731 }; 9732