1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 273 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 278 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 279 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 280 281 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 282 { 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 323 }; 324 325 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 326 { 327 /* Pending on emulation bring up */ 328 }; 329 330 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 331 { 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1384 }; 1385 1386 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1387 { 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1426 }; 1427 1428 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1429 { 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1472 }; 1473 1474 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1475 { 1476 /* Pending on emulation bring up */ 1477 }; 1478 1479 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1480 { 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2101 }; 2102 2103 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2104 { 2105 /* Pending on emulation bring up */ 2106 }; 2107 2108 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2109 { 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3162 }; 3163 3164 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3165 { 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3209 }; 3210 3211 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3212 { 3213 /* Pending on emulation bring up */ 3214 }; 3215 3216 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3217 { 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3259 3260 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3262 }; 3263 3264 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3265 { 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3290 3291 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3293 }; 3294 3295 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3296 { 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3317 }; 3318 3319 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3320 { 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3357 }; 3358 3359 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3392 }; 3393 3394 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3429 }; 3430 3431 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = 3432 { 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3455 }; 3456 3457 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3480 }; 3481 3482 #define DEFAULT_SH_MEM_CONFIG \ 3483 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3484 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3485 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3486 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3487 3488 /* TODO: pending on golden setting value of gb address config */ 3489 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3490 3491 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3492 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3493 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3494 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3495 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3496 struct amdgpu_cu_info *cu_info); 3497 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3498 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3499 u32 sh_num, u32 instance); 3500 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3501 3502 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3503 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3504 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3505 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3506 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3507 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3508 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3509 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3510 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3511 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3512 3513 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3514 { 3515 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3516 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3517 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3518 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3519 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3520 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3521 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3522 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3523 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3524 } 3525 3526 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3527 struct amdgpu_ring *ring) 3528 { 3529 struct amdgpu_device *adev = kiq_ring->adev; 3530 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3531 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3532 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3533 3534 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3535 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3536 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3537 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3538 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3539 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3540 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3541 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3542 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3543 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3544 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3545 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3546 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3547 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3548 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3549 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3550 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3551 } 3552 3553 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3554 struct amdgpu_ring *ring, 3555 enum amdgpu_unmap_queues_action action, 3556 u64 gpu_addr, u64 seq) 3557 { 3558 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3559 3560 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3561 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3562 PACKET3_UNMAP_QUEUES_ACTION(action) | 3563 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3564 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3565 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3566 amdgpu_ring_write(kiq_ring, 3567 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3568 3569 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3570 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3571 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3572 amdgpu_ring_write(kiq_ring, seq); 3573 } else { 3574 amdgpu_ring_write(kiq_ring, 0); 3575 amdgpu_ring_write(kiq_ring, 0); 3576 amdgpu_ring_write(kiq_ring, 0); 3577 } 3578 } 3579 3580 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3581 struct amdgpu_ring *ring, 3582 u64 addr, 3583 u64 seq) 3584 { 3585 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3586 3587 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3588 amdgpu_ring_write(kiq_ring, 3589 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3590 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3591 PACKET3_QUERY_STATUS_COMMAND(2)); 3592 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3593 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3594 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3595 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3596 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3597 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3598 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3599 } 3600 3601 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3602 uint16_t pasid, uint32_t flush_type, 3603 bool all_hub) 3604 { 3605 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3606 amdgpu_ring_write(kiq_ring, 3607 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3608 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3609 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3610 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3611 } 3612 3613 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3614 .kiq_set_resources = gfx10_kiq_set_resources, 3615 .kiq_map_queues = gfx10_kiq_map_queues, 3616 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3617 .kiq_query_status = gfx10_kiq_query_status, 3618 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3619 .set_resources_size = 8, 3620 .map_queues_size = 7, 3621 .unmap_queues_size = 6, 3622 .query_status_size = 7, 3623 .invalidate_tlbs_size = 2, 3624 }; 3625 3626 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3627 { 3628 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3629 } 3630 3631 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3632 { 3633 switch (adev->ip_versions[GC_HWIP][0]) { 3634 case IP_VERSION(10, 1, 10): 3635 soc15_program_register_sequence(adev, 3636 golden_settings_gc_rlc_spm_10_0_nv10, 3637 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3638 break; 3639 case IP_VERSION(10, 1, 1): 3640 soc15_program_register_sequence(adev, 3641 golden_settings_gc_rlc_spm_10_1_nv14, 3642 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3643 break; 3644 case IP_VERSION(10, 1, 2): 3645 soc15_program_register_sequence(adev, 3646 golden_settings_gc_rlc_spm_10_1_2_nv12, 3647 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3648 break; 3649 default: 3650 break; 3651 } 3652 } 3653 3654 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3655 { 3656 switch (adev->ip_versions[GC_HWIP][0]) { 3657 case IP_VERSION(10, 1, 10): 3658 soc15_program_register_sequence(adev, 3659 golden_settings_gc_10_1, 3660 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3661 soc15_program_register_sequence(adev, 3662 golden_settings_gc_10_0_nv10, 3663 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3664 break; 3665 case IP_VERSION(10, 1, 1): 3666 soc15_program_register_sequence(adev, 3667 golden_settings_gc_10_1_1, 3668 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3669 soc15_program_register_sequence(adev, 3670 golden_settings_gc_10_1_nv14, 3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3672 break; 3673 case IP_VERSION(10, 1, 2): 3674 soc15_program_register_sequence(adev, 3675 golden_settings_gc_10_1_2, 3676 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3677 soc15_program_register_sequence(adev, 3678 golden_settings_gc_10_1_2_nv12, 3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3680 break; 3681 case IP_VERSION(10, 3, 0): 3682 soc15_program_register_sequence(adev, 3683 golden_settings_gc_10_3, 3684 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3685 soc15_program_register_sequence(adev, 3686 golden_settings_gc_10_3_sienna_cichlid, 3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3688 break; 3689 case IP_VERSION(10, 3, 2): 3690 soc15_program_register_sequence(adev, 3691 golden_settings_gc_10_3_2, 3692 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3693 break; 3694 case IP_VERSION(10, 3, 1): 3695 soc15_program_register_sequence(adev, 3696 golden_settings_gc_10_3_vangogh, 3697 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3698 break; 3699 case IP_VERSION(10, 3, 3): 3700 soc15_program_register_sequence(adev, 3701 golden_settings_gc_10_3_3, 3702 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3703 break; 3704 case IP_VERSION(10, 3, 4): 3705 soc15_program_register_sequence(adev, 3706 golden_settings_gc_10_3_4, 3707 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3708 break; 3709 case IP_VERSION(10, 3, 5): 3710 soc15_program_register_sequence(adev, 3711 golden_settings_gc_10_3_5, 3712 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3713 break; 3714 case IP_VERSION(10, 1, 3): 3715 case IP_VERSION(10, 1, 4): 3716 soc15_program_register_sequence(adev, 3717 golden_settings_gc_10_0_cyan_skillfish, 3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3719 break; 3720 case IP_VERSION(10, 3, 6): 3721 soc15_program_register_sequence(adev, 3722 golden_settings_gc_10_3_6, 3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3724 break; 3725 case IP_VERSION(10, 3, 7): 3726 soc15_program_register_sequence(adev, 3727 golden_settings_gc_10_3_7, 3728 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3729 break; 3730 default: 3731 break; 3732 } 3733 gfx_v10_0_init_spm_golden_registers(adev); 3734 } 3735 3736 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3737 { 3738 adev->gfx.scratch.num_reg = 8; 3739 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3740 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3741 } 3742 3743 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3744 bool wc, uint32_t reg, uint32_t val) 3745 { 3746 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3747 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3748 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3749 amdgpu_ring_write(ring, reg); 3750 amdgpu_ring_write(ring, 0); 3751 amdgpu_ring_write(ring, val); 3752 } 3753 3754 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3755 int mem_space, int opt, uint32_t addr0, 3756 uint32_t addr1, uint32_t ref, uint32_t mask, 3757 uint32_t inv) 3758 { 3759 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3760 amdgpu_ring_write(ring, 3761 /* memory (1) or register (0) */ 3762 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3763 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3764 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3765 WAIT_REG_MEM_ENGINE(eng_sel))); 3766 3767 if (mem_space) 3768 BUG_ON(addr0 & 0x3); /* Dword align */ 3769 amdgpu_ring_write(ring, addr0); 3770 amdgpu_ring_write(ring, addr1); 3771 amdgpu_ring_write(ring, ref); 3772 amdgpu_ring_write(ring, mask); 3773 amdgpu_ring_write(ring, inv); /* poll interval */ 3774 } 3775 3776 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3777 { 3778 struct amdgpu_device *adev = ring->adev; 3779 uint32_t scratch; 3780 uint32_t tmp = 0; 3781 unsigned i; 3782 int r; 3783 3784 r = amdgpu_gfx_scratch_get(adev, &scratch); 3785 if (r) { 3786 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3787 return r; 3788 } 3789 3790 WREG32(scratch, 0xCAFEDEAD); 3791 3792 r = amdgpu_ring_alloc(ring, 3); 3793 if (r) { 3794 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3795 ring->idx, r); 3796 amdgpu_gfx_scratch_free(adev, scratch); 3797 return r; 3798 } 3799 3800 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3801 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3802 amdgpu_ring_write(ring, 0xDEADBEEF); 3803 amdgpu_ring_commit(ring); 3804 3805 for (i = 0; i < adev->usec_timeout; i++) { 3806 tmp = RREG32(scratch); 3807 if (tmp == 0xDEADBEEF) 3808 break; 3809 if (amdgpu_emu_mode == 1) 3810 msleep(1); 3811 else 3812 udelay(1); 3813 } 3814 3815 if (i >= adev->usec_timeout) 3816 r = -ETIMEDOUT; 3817 3818 amdgpu_gfx_scratch_free(adev, scratch); 3819 3820 return r; 3821 } 3822 3823 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3824 { 3825 struct amdgpu_device *adev = ring->adev; 3826 struct amdgpu_ib ib; 3827 struct dma_fence *f = NULL; 3828 unsigned index; 3829 uint64_t gpu_addr; 3830 uint32_t tmp; 3831 long r; 3832 3833 r = amdgpu_device_wb_get(adev, &index); 3834 if (r) 3835 return r; 3836 3837 gpu_addr = adev->wb.gpu_addr + (index * 4); 3838 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3839 memset(&ib, 0, sizeof(ib)); 3840 r = amdgpu_ib_get(adev, NULL, 16, 3841 AMDGPU_IB_POOL_DIRECT, &ib); 3842 if (r) 3843 goto err1; 3844 3845 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3847 ib.ptr[2] = lower_32_bits(gpu_addr); 3848 ib.ptr[3] = upper_32_bits(gpu_addr); 3849 ib.ptr[4] = 0xDEADBEEF; 3850 ib.length_dw = 5; 3851 3852 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3853 if (r) 3854 goto err2; 3855 3856 r = dma_fence_wait_timeout(f, false, timeout); 3857 if (r == 0) { 3858 r = -ETIMEDOUT; 3859 goto err2; 3860 } else if (r < 0) { 3861 goto err2; 3862 } 3863 3864 tmp = adev->wb.wb[index]; 3865 if (tmp == 0xDEADBEEF) 3866 r = 0; 3867 else 3868 r = -EINVAL; 3869 err2: 3870 amdgpu_ib_free(adev, &ib, NULL); 3871 dma_fence_put(f); 3872 err1: 3873 amdgpu_device_wb_free(adev, index); 3874 return r; 3875 } 3876 3877 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3878 { 3879 release_firmware(adev->gfx.pfp_fw); 3880 adev->gfx.pfp_fw = NULL; 3881 release_firmware(adev->gfx.me_fw); 3882 adev->gfx.me_fw = NULL; 3883 release_firmware(adev->gfx.ce_fw); 3884 adev->gfx.ce_fw = NULL; 3885 release_firmware(adev->gfx.rlc_fw); 3886 adev->gfx.rlc_fw = NULL; 3887 release_firmware(adev->gfx.mec_fw); 3888 adev->gfx.mec_fw = NULL; 3889 release_firmware(adev->gfx.mec2_fw); 3890 adev->gfx.mec2_fw = NULL; 3891 3892 kfree(adev->gfx.rlc.register_list_format); 3893 } 3894 3895 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3896 { 3897 adev->gfx.cp_fw_write_wait = false; 3898 3899 switch (adev->ip_versions[GC_HWIP][0]) { 3900 case IP_VERSION(10, 1, 10): 3901 case IP_VERSION(10, 1, 2): 3902 case IP_VERSION(10, 1, 1): 3903 case IP_VERSION(10, 1, 3): 3904 case IP_VERSION(10, 1, 4): 3905 if ((adev->gfx.me_fw_version >= 0x00000046) && 3906 (adev->gfx.me_feature_version >= 27) && 3907 (adev->gfx.pfp_fw_version >= 0x00000068) && 3908 (adev->gfx.pfp_feature_version >= 27) && 3909 (adev->gfx.mec_fw_version >= 0x0000005b) && 3910 (adev->gfx.mec_feature_version >= 27)) 3911 adev->gfx.cp_fw_write_wait = true; 3912 break; 3913 case IP_VERSION(10, 3, 0): 3914 case IP_VERSION(10, 3, 2): 3915 case IP_VERSION(10, 3, 1): 3916 case IP_VERSION(10, 3, 4): 3917 case IP_VERSION(10, 3, 5): 3918 case IP_VERSION(10, 3, 6): 3919 case IP_VERSION(10, 3, 3): 3920 case IP_VERSION(10, 3, 7): 3921 adev->gfx.cp_fw_write_wait = true; 3922 break; 3923 default: 3924 break; 3925 } 3926 3927 if (!adev->gfx.cp_fw_write_wait) 3928 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3929 } 3930 3931 3932 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3933 { 3934 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3935 3936 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3937 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3938 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3939 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3940 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3941 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3942 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3943 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3944 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3945 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3946 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3947 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3948 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3949 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3950 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3951 } 3952 3953 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3954 { 3955 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3956 3957 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3958 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3959 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3960 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3961 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3962 } 3963 3964 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3965 { 3966 bool ret = false; 3967 3968 switch (adev->pdev->revision) { 3969 case 0xc2: 3970 case 0xc3: 3971 ret = true; 3972 break; 3973 default: 3974 ret = false; 3975 break; 3976 } 3977 3978 return ret ; 3979 } 3980 3981 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3982 { 3983 switch (adev->ip_versions[GC_HWIP][0]) { 3984 case IP_VERSION(10, 1, 10): 3985 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3986 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3987 break; 3988 default: 3989 break; 3990 } 3991 } 3992 3993 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3994 { 3995 const char *chip_name; 3996 char fw_name[40]; 3997 char *wks = ""; 3998 int err; 3999 struct amdgpu_firmware_info *info = NULL; 4000 const struct common_firmware_header *header = NULL; 4001 const struct gfx_firmware_header_v1_0 *cp_hdr; 4002 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4003 unsigned int *tmp = NULL; 4004 unsigned int i = 0; 4005 uint16_t version_major; 4006 uint16_t version_minor; 4007 4008 DRM_DEBUG("\n"); 4009 4010 switch (adev->ip_versions[GC_HWIP][0]) { 4011 case IP_VERSION(10, 1, 10): 4012 chip_name = "navi10"; 4013 break; 4014 case IP_VERSION(10, 1, 1): 4015 chip_name = "navi14"; 4016 if (!(adev->pdev->device == 0x7340 && 4017 adev->pdev->revision != 0x00)) 4018 wks = "_wks"; 4019 break; 4020 case IP_VERSION(10, 1, 2): 4021 chip_name = "navi12"; 4022 break; 4023 case IP_VERSION(10, 3, 0): 4024 chip_name = "sienna_cichlid"; 4025 break; 4026 case IP_VERSION(10, 3, 2): 4027 chip_name = "navy_flounder"; 4028 break; 4029 case IP_VERSION(10, 3, 1): 4030 chip_name = "vangogh"; 4031 break; 4032 case IP_VERSION(10, 3, 4): 4033 chip_name = "dimgrey_cavefish"; 4034 break; 4035 case IP_VERSION(10, 3, 5): 4036 chip_name = "beige_goby"; 4037 break; 4038 case IP_VERSION(10, 3, 3): 4039 chip_name = "yellow_carp"; 4040 break; 4041 case IP_VERSION(10, 3, 6): 4042 chip_name = "gc_10_3_6"; 4043 break; 4044 case IP_VERSION(10, 1, 3): 4045 case IP_VERSION(10, 1, 4): 4046 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 4047 chip_name = "cyan_skillfish2"; 4048 else 4049 chip_name = "cyan_skillfish"; 4050 break; 4051 case IP_VERSION(10, 3, 7): 4052 chip_name = "gc_10_3_7"; 4053 break; 4054 default: 4055 BUG(); 4056 } 4057 4058 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 4059 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 4060 if (err) 4061 goto out; 4062 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 4063 if (err) 4064 goto out; 4065 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 4066 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4067 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4068 4069 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 4070 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 4071 if (err) 4072 goto out; 4073 err = amdgpu_ucode_validate(adev->gfx.me_fw); 4074 if (err) 4075 goto out; 4076 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 4077 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4078 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4079 4080 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 4081 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 4082 if (err) 4083 goto out; 4084 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 4085 if (err) 4086 goto out; 4087 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 4088 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4089 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4090 4091 if (!amdgpu_sriov_vf(adev)) { 4092 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 4093 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4094 if (err) 4095 goto out; 4096 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 4097 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4098 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4099 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4100 4101 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 4102 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 4103 adev->gfx.rlc.save_and_restore_offset = 4104 le32_to_cpu(rlc_hdr->save_and_restore_offset); 4105 adev->gfx.rlc.clear_state_descriptor_offset = 4106 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 4107 adev->gfx.rlc.avail_scratch_ram_locations = 4108 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 4109 adev->gfx.rlc.reg_restore_list_size = 4110 le32_to_cpu(rlc_hdr->reg_restore_list_size); 4111 adev->gfx.rlc.reg_list_format_start = 4112 le32_to_cpu(rlc_hdr->reg_list_format_start); 4113 adev->gfx.rlc.reg_list_format_separate_start = 4114 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 4115 adev->gfx.rlc.starting_offsets_start = 4116 le32_to_cpu(rlc_hdr->starting_offsets_start); 4117 adev->gfx.rlc.reg_list_format_size_bytes = 4118 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 4119 adev->gfx.rlc.reg_list_size_bytes = 4120 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 4121 adev->gfx.rlc.register_list_format = 4122 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 4123 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 4124 if (!adev->gfx.rlc.register_list_format) { 4125 err = -ENOMEM; 4126 goto out; 4127 } 4128 4129 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4130 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 4131 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 4132 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 4133 4134 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 4135 4136 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4137 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 4138 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 4139 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 4140 4141 if (version_major == 2) { 4142 if (version_minor >= 1) 4143 gfx_v10_0_init_rlc_ext_microcode(adev); 4144 if (version_minor == 2) 4145 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 4146 } 4147 } 4148 4149 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 4150 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 4151 if (err) 4152 goto out; 4153 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 4154 if (err) 4155 goto out; 4156 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4157 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4158 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4159 4160 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 4161 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 4162 if (!err) { 4163 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 4164 if (err) 4165 goto out; 4166 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 4167 adev->gfx.mec2_fw->data; 4168 adev->gfx.mec2_fw_version = 4169 le32_to_cpu(cp_hdr->header.ucode_version); 4170 adev->gfx.mec2_feature_version = 4171 le32_to_cpu(cp_hdr->ucode_feature_version); 4172 } else { 4173 err = 0; 4174 adev->gfx.mec2_fw = NULL; 4175 } 4176 4177 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 4178 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 4179 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 4180 info->fw = adev->gfx.pfp_fw; 4181 header = (const struct common_firmware_header *)info->fw->data; 4182 adev->firmware.fw_size += 4183 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4184 4185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 4186 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 4187 info->fw = adev->gfx.me_fw; 4188 header = (const struct common_firmware_header *)info->fw->data; 4189 adev->firmware.fw_size += 4190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4191 4192 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 4193 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 4194 info->fw = adev->gfx.ce_fw; 4195 header = (const struct common_firmware_header *)info->fw->data; 4196 adev->firmware.fw_size += 4197 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4198 4199 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 4200 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 4201 info->fw = adev->gfx.rlc_fw; 4202 if (info->fw) { 4203 header = (const struct common_firmware_header *)info->fw->data; 4204 adev->firmware.fw_size += 4205 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4206 } 4207 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 4208 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 4209 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 4210 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 4211 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 4212 info->fw = adev->gfx.rlc_fw; 4213 adev->firmware.fw_size += 4214 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 4215 4216 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 4217 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 4218 info->fw = adev->gfx.rlc_fw; 4219 adev->firmware.fw_size += 4220 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4221 4222 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4223 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4224 info->fw = adev->gfx.rlc_fw; 4225 adev->firmware.fw_size += 4226 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4227 4228 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4229 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4230 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4231 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4232 info->fw = adev->gfx.rlc_fw; 4233 adev->firmware.fw_size += 4234 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4235 4236 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4237 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4238 info->fw = adev->gfx.rlc_fw; 4239 adev->firmware.fw_size += 4240 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4241 } 4242 } 4243 4244 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4245 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4246 info->fw = adev->gfx.mec_fw; 4247 header = (const struct common_firmware_header *)info->fw->data; 4248 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4249 adev->firmware.fw_size += 4250 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4251 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4252 4253 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4254 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4255 info->fw = adev->gfx.mec_fw; 4256 adev->firmware.fw_size += 4257 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4258 4259 if (adev->gfx.mec2_fw) { 4260 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4261 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4262 info->fw = adev->gfx.mec2_fw; 4263 header = (const struct common_firmware_header *)info->fw->data; 4264 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4265 adev->firmware.fw_size += 4266 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4267 le32_to_cpu(cp_hdr->jt_size) * 4, 4268 PAGE_SIZE); 4269 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4270 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4271 info->fw = adev->gfx.mec2_fw; 4272 adev->firmware.fw_size += 4273 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4274 PAGE_SIZE); 4275 } 4276 } 4277 4278 gfx_v10_0_check_fw_write_wait(adev); 4279 out: 4280 if (err) { 4281 dev_err(adev->dev, 4282 "gfx10: Failed to load firmware \"%s\"\n", 4283 fw_name); 4284 release_firmware(adev->gfx.pfp_fw); 4285 adev->gfx.pfp_fw = NULL; 4286 release_firmware(adev->gfx.me_fw); 4287 adev->gfx.me_fw = NULL; 4288 release_firmware(adev->gfx.ce_fw); 4289 adev->gfx.ce_fw = NULL; 4290 release_firmware(adev->gfx.rlc_fw); 4291 adev->gfx.rlc_fw = NULL; 4292 release_firmware(adev->gfx.mec_fw); 4293 adev->gfx.mec_fw = NULL; 4294 release_firmware(adev->gfx.mec2_fw); 4295 adev->gfx.mec2_fw = NULL; 4296 } 4297 4298 gfx_v10_0_check_gfxoff_flag(adev); 4299 4300 return err; 4301 } 4302 4303 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4304 { 4305 u32 count = 0; 4306 const struct cs_section_def *sect = NULL; 4307 const struct cs_extent_def *ext = NULL; 4308 4309 /* begin clear state */ 4310 count += 2; 4311 /* context control state */ 4312 count += 3; 4313 4314 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4315 for (ext = sect->section; ext->extent != NULL; ++ext) { 4316 if (sect->id == SECT_CONTEXT) 4317 count += 2 + ext->reg_count; 4318 else 4319 return 0; 4320 } 4321 } 4322 4323 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4324 count += 3; 4325 /* end clear state */ 4326 count += 2; 4327 /* clear state */ 4328 count += 2; 4329 4330 return count; 4331 } 4332 4333 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4334 volatile u32 *buffer) 4335 { 4336 u32 count = 0, i; 4337 const struct cs_section_def *sect = NULL; 4338 const struct cs_extent_def *ext = NULL; 4339 int ctx_reg_offset; 4340 4341 if (adev->gfx.rlc.cs_data == NULL) 4342 return; 4343 if (buffer == NULL) 4344 return; 4345 4346 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4347 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4348 4349 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4350 buffer[count++] = cpu_to_le32(0x80000000); 4351 buffer[count++] = cpu_to_le32(0x80000000); 4352 4353 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4354 for (ext = sect->section; ext->extent != NULL; ++ext) { 4355 if (sect->id == SECT_CONTEXT) { 4356 buffer[count++] = 4357 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4358 buffer[count++] = cpu_to_le32(ext->reg_index - 4359 PACKET3_SET_CONTEXT_REG_START); 4360 for (i = 0; i < ext->reg_count; i++) 4361 buffer[count++] = cpu_to_le32(ext->extent[i]); 4362 } else { 4363 return; 4364 } 4365 } 4366 } 4367 4368 ctx_reg_offset = 4369 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4370 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4371 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4372 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4373 4374 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4375 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4376 4377 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4378 buffer[count++] = cpu_to_le32(0); 4379 } 4380 4381 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4382 { 4383 /* clear state block */ 4384 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4385 &adev->gfx.rlc.clear_state_gpu_addr, 4386 (void **)&adev->gfx.rlc.cs_ptr); 4387 4388 /* jump table block */ 4389 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4390 &adev->gfx.rlc.cp_table_gpu_addr, 4391 (void **)&adev->gfx.rlc.cp_table_ptr); 4392 } 4393 4394 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4395 { 4396 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4397 4398 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 4399 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4400 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4401 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4402 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4403 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4404 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4405 switch (adev->ip_versions[GC_HWIP][0]) { 4406 case IP_VERSION(10, 3, 0): 4407 reg_access_ctrl->spare_int = 4408 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4409 break; 4410 default: 4411 reg_access_ctrl->spare_int = 4412 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4413 break; 4414 } 4415 adev->gfx.rlc.rlcg_reg_access_supported = true; 4416 } 4417 4418 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4419 { 4420 const struct cs_section_def *cs_data; 4421 int r; 4422 4423 adev->gfx.rlc.cs_data = gfx10_cs_data; 4424 4425 cs_data = adev->gfx.rlc.cs_data; 4426 4427 if (cs_data) { 4428 /* init clear state block */ 4429 r = amdgpu_gfx_rlc_init_csb(adev); 4430 if (r) 4431 return r; 4432 } 4433 4434 /* init spm vmid with 0xf */ 4435 if (adev->gfx.rlc.funcs->update_spm_vmid) 4436 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4437 4438 4439 return 0; 4440 } 4441 4442 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4443 { 4444 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4445 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4446 } 4447 4448 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4449 { 4450 int r; 4451 4452 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4453 4454 amdgpu_gfx_graphics_queue_acquire(adev); 4455 4456 r = gfx_v10_0_init_microcode(adev); 4457 if (r) 4458 DRM_ERROR("Failed to load gfx firmware!\n"); 4459 4460 return r; 4461 } 4462 4463 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4464 { 4465 int r; 4466 u32 *hpd; 4467 const __le32 *fw_data = NULL; 4468 unsigned fw_size; 4469 u32 *fw = NULL; 4470 size_t mec_hpd_size; 4471 4472 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4473 4474 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4475 4476 /* take ownership of the relevant compute queues */ 4477 amdgpu_gfx_compute_queue_acquire(adev); 4478 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4479 4480 if (mec_hpd_size) { 4481 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4482 AMDGPU_GEM_DOMAIN_GTT, 4483 &adev->gfx.mec.hpd_eop_obj, 4484 &adev->gfx.mec.hpd_eop_gpu_addr, 4485 (void **)&hpd); 4486 if (r) { 4487 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4488 gfx_v10_0_mec_fini(adev); 4489 return r; 4490 } 4491 4492 memset(hpd, 0, mec_hpd_size); 4493 4494 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4495 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4496 } 4497 4498 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4499 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4500 4501 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4502 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4503 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4504 4505 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4507 &adev->gfx.mec.mec_fw_obj, 4508 &adev->gfx.mec.mec_fw_gpu_addr, 4509 (void **)&fw); 4510 if (r) { 4511 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4512 gfx_v10_0_mec_fini(adev); 4513 return r; 4514 } 4515 4516 memcpy(fw, fw_data, fw_size); 4517 4518 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4519 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4520 } 4521 4522 return 0; 4523 } 4524 4525 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4526 { 4527 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4528 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4529 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4530 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4531 } 4532 4533 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4534 uint32_t thread, uint32_t regno, 4535 uint32_t num, uint32_t *out) 4536 { 4537 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4538 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4539 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4540 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4541 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4542 while (num--) 4543 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4544 } 4545 4546 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4547 { 4548 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4549 * field when performing a select_se_sh so it should be 4550 * zero here */ 4551 WARN_ON(simd != 0); 4552 4553 /* type 2 wave data */ 4554 dst[(*no_fields)++] = 2; 4555 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4556 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4557 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4558 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4559 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4560 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4561 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4562 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4563 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4564 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4565 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4566 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4567 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4568 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4569 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4570 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4571 } 4572 4573 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4574 uint32_t wave, uint32_t start, 4575 uint32_t size, uint32_t *dst) 4576 { 4577 WARN_ON(simd != 0); 4578 4579 wave_read_regs( 4580 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4581 dst); 4582 } 4583 4584 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4585 uint32_t wave, uint32_t thread, 4586 uint32_t start, uint32_t size, 4587 uint32_t *dst) 4588 { 4589 wave_read_regs( 4590 adev, wave, thread, 4591 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4592 } 4593 4594 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4595 u32 me, u32 pipe, u32 q, u32 vm) 4596 { 4597 nv_grbm_select(adev, me, pipe, q, vm); 4598 } 4599 4600 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4601 bool enable) 4602 { 4603 uint32_t data, def; 4604 4605 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4606 4607 if (enable) 4608 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4609 else 4610 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4611 4612 if (data != def) 4613 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4614 } 4615 4616 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4617 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4618 .select_se_sh = &gfx_v10_0_select_se_sh, 4619 .read_wave_data = &gfx_v10_0_read_wave_data, 4620 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4621 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4622 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4623 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4624 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4625 }; 4626 4627 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4628 { 4629 u32 gb_addr_config; 4630 4631 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4632 4633 switch (adev->ip_versions[GC_HWIP][0]) { 4634 case IP_VERSION(10, 1, 10): 4635 case IP_VERSION(10, 1, 1): 4636 case IP_VERSION(10, 1, 2): 4637 adev->gfx.config.max_hw_contexts = 8; 4638 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4639 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4640 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4641 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4642 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4643 break; 4644 case IP_VERSION(10, 3, 0): 4645 case IP_VERSION(10, 3, 2): 4646 case IP_VERSION(10, 3, 1): 4647 case IP_VERSION(10, 3, 4): 4648 case IP_VERSION(10, 3, 5): 4649 case IP_VERSION(10, 3, 6): 4650 case IP_VERSION(10, 3, 3): 4651 case IP_VERSION(10, 3, 7): 4652 adev->gfx.config.max_hw_contexts = 8; 4653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4654 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4655 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4656 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4657 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4658 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4659 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4660 break; 4661 case IP_VERSION(10, 1, 3): 4662 case IP_VERSION(10, 1, 4): 4663 adev->gfx.config.max_hw_contexts = 8; 4664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4665 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4666 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4667 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4668 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4669 break; 4670 default: 4671 BUG(); 4672 break; 4673 } 4674 4675 adev->gfx.config.gb_addr_config = gb_addr_config; 4676 4677 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4678 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4679 GB_ADDR_CONFIG, NUM_PIPES); 4680 4681 adev->gfx.config.max_tile_pipes = 4682 adev->gfx.config.gb_addr_config_fields.num_pipes; 4683 4684 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4685 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4686 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4687 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4688 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4689 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4690 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4691 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4692 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4693 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4694 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4695 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4696 } 4697 4698 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4699 int me, int pipe, int queue) 4700 { 4701 int r; 4702 struct amdgpu_ring *ring; 4703 unsigned int irq_type; 4704 4705 ring = &adev->gfx.gfx_ring[ring_id]; 4706 4707 ring->me = me; 4708 ring->pipe = pipe; 4709 ring->queue = queue; 4710 4711 ring->ring_obj = NULL; 4712 ring->use_doorbell = true; 4713 4714 if (!ring_id) 4715 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4716 else 4717 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4718 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4719 4720 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4721 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4722 AMDGPU_RING_PRIO_DEFAULT, NULL); 4723 if (r) 4724 return r; 4725 return 0; 4726 } 4727 4728 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4729 int mec, int pipe, int queue) 4730 { 4731 int r; 4732 unsigned irq_type; 4733 struct amdgpu_ring *ring; 4734 unsigned int hw_prio; 4735 4736 ring = &adev->gfx.compute_ring[ring_id]; 4737 4738 /* mec0 is me1 */ 4739 ring->me = mec + 1; 4740 ring->pipe = pipe; 4741 ring->queue = queue; 4742 4743 ring->ring_obj = NULL; 4744 ring->use_doorbell = true; 4745 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4746 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4747 + (ring_id * GFX10_MEC_HPD_SIZE); 4748 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4749 4750 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4751 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4752 + ring->pipe; 4753 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4754 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4755 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4756 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4757 hw_prio, NULL); 4758 if (r) 4759 return r; 4760 4761 return 0; 4762 } 4763 4764 static int gfx_v10_0_sw_init(void *handle) 4765 { 4766 int i, j, k, r, ring_id = 0; 4767 struct amdgpu_kiq *kiq; 4768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4769 4770 switch (adev->ip_versions[GC_HWIP][0]) { 4771 case IP_VERSION(10, 1, 10): 4772 case IP_VERSION(10, 1, 1): 4773 case IP_VERSION(10, 1, 2): 4774 case IP_VERSION(10, 1, 3): 4775 case IP_VERSION(10, 1, 4): 4776 adev->gfx.me.num_me = 1; 4777 adev->gfx.me.num_pipe_per_me = 1; 4778 adev->gfx.me.num_queue_per_pipe = 1; 4779 adev->gfx.mec.num_mec = 2; 4780 adev->gfx.mec.num_pipe_per_mec = 4; 4781 adev->gfx.mec.num_queue_per_pipe = 8; 4782 break; 4783 case IP_VERSION(10, 3, 0): 4784 case IP_VERSION(10, 3, 2): 4785 case IP_VERSION(10, 3, 1): 4786 case IP_VERSION(10, 3, 4): 4787 case IP_VERSION(10, 3, 5): 4788 case IP_VERSION(10, 3, 6): 4789 case IP_VERSION(10, 3, 3): 4790 case IP_VERSION(10, 3, 7): 4791 adev->gfx.me.num_me = 1; 4792 adev->gfx.me.num_pipe_per_me = 1; 4793 adev->gfx.me.num_queue_per_pipe = 1; 4794 adev->gfx.mec.num_mec = 2; 4795 adev->gfx.mec.num_pipe_per_mec = 4; 4796 adev->gfx.mec.num_queue_per_pipe = 4; 4797 break; 4798 default: 4799 adev->gfx.me.num_me = 1; 4800 adev->gfx.me.num_pipe_per_me = 1; 4801 adev->gfx.me.num_queue_per_pipe = 1; 4802 adev->gfx.mec.num_mec = 1; 4803 adev->gfx.mec.num_pipe_per_mec = 4; 4804 adev->gfx.mec.num_queue_per_pipe = 8; 4805 break; 4806 } 4807 4808 /* KIQ event */ 4809 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4810 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4811 &adev->gfx.kiq.irq); 4812 if (r) 4813 return r; 4814 4815 /* EOP Event */ 4816 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4817 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4818 &adev->gfx.eop_irq); 4819 if (r) 4820 return r; 4821 4822 /* Privileged reg */ 4823 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4824 &adev->gfx.priv_reg_irq); 4825 if (r) 4826 return r; 4827 4828 /* Privileged inst */ 4829 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4830 &adev->gfx.priv_inst_irq); 4831 if (r) 4832 return r; 4833 4834 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4835 4836 gfx_v10_0_scratch_init(adev); 4837 4838 r = gfx_v10_0_me_init(adev); 4839 if (r) 4840 return r; 4841 4842 if (adev->gfx.rlc.funcs) { 4843 if (adev->gfx.rlc.funcs->init) { 4844 r = adev->gfx.rlc.funcs->init(adev); 4845 if (r) { 4846 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4847 return r; 4848 } 4849 } 4850 } 4851 4852 r = gfx_v10_0_mec_init(adev); 4853 if (r) { 4854 DRM_ERROR("Failed to init MEC BOs!\n"); 4855 return r; 4856 } 4857 4858 /* set up the gfx ring */ 4859 for (i = 0; i < adev->gfx.me.num_me; i++) { 4860 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4861 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4862 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4863 continue; 4864 4865 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4866 i, k, j); 4867 if (r) 4868 return r; 4869 ring_id++; 4870 } 4871 } 4872 } 4873 4874 ring_id = 0; 4875 /* set up the compute queues - allocate horizontally across pipes */ 4876 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4877 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4878 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4879 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4880 j)) 4881 continue; 4882 4883 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4884 i, k, j); 4885 if (r) 4886 return r; 4887 4888 ring_id++; 4889 } 4890 } 4891 } 4892 4893 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4894 if (r) { 4895 DRM_ERROR("Failed to init KIQ BOs!\n"); 4896 return r; 4897 } 4898 4899 kiq = &adev->gfx.kiq; 4900 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4901 if (r) 4902 return r; 4903 4904 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4905 if (r) 4906 return r; 4907 4908 /* allocate visible FB for rlc auto-loading fw */ 4909 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4910 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4911 if (r) 4912 return r; 4913 } 4914 4915 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4916 4917 gfx_v10_0_gpu_early_init(adev); 4918 4919 return 0; 4920 } 4921 4922 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4923 { 4924 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4925 &adev->gfx.pfp.pfp_fw_gpu_addr, 4926 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4927 } 4928 4929 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4930 { 4931 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4932 &adev->gfx.ce.ce_fw_gpu_addr, 4933 (void **)&adev->gfx.ce.ce_fw_ptr); 4934 } 4935 4936 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4937 { 4938 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4939 &adev->gfx.me.me_fw_gpu_addr, 4940 (void **)&adev->gfx.me.me_fw_ptr); 4941 } 4942 4943 static int gfx_v10_0_sw_fini(void *handle) 4944 { 4945 int i; 4946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4947 4948 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4949 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4950 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4951 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4952 4953 amdgpu_gfx_mqd_sw_fini(adev); 4954 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4955 amdgpu_gfx_kiq_fini(adev); 4956 4957 gfx_v10_0_pfp_fini(adev); 4958 gfx_v10_0_ce_fini(adev); 4959 gfx_v10_0_me_fini(adev); 4960 gfx_v10_0_rlc_fini(adev); 4961 gfx_v10_0_mec_fini(adev); 4962 4963 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4964 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4965 4966 gfx_v10_0_free_microcode(adev); 4967 4968 return 0; 4969 } 4970 4971 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4972 u32 sh_num, u32 instance) 4973 { 4974 u32 data; 4975 4976 if (instance == 0xffffffff) 4977 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4978 INSTANCE_BROADCAST_WRITES, 1); 4979 else 4980 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4981 instance); 4982 4983 if (se_num == 0xffffffff) 4984 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4985 1); 4986 else 4987 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4988 4989 if (sh_num == 0xffffffff) 4990 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4991 1); 4992 else 4993 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4994 4995 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4996 } 4997 4998 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4999 { 5000 u32 data, mask; 5001 5002 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5003 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5004 5005 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5006 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5007 5008 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5009 adev->gfx.config.max_sh_per_se); 5010 5011 return (~data) & mask; 5012 } 5013 5014 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5015 { 5016 int i, j; 5017 u32 data; 5018 u32 active_rbs = 0; 5019 u32 bitmap; 5020 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5021 adev->gfx.config.max_sh_per_se; 5022 5023 mutex_lock(&adev->grbm_idx_mutex); 5024 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5025 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5026 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5027 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 5028 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 5029 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 5030 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5031 continue; 5032 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5033 data = gfx_v10_0_get_rb_active_bitmap(adev); 5034 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5035 rb_bitmap_width_per_sh); 5036 } 5037 } 5038 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5039 mutex_unlock(&adev->grbm_idx_mutex); 5040 5041 adev->gfx.config.backend_enable_mask = active_rbs; 5042 adev->gfx.config.num_rbs = hweight32(active_rbs); 5043 } 5044 5045 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5046 { 5047 uint32_t num_sc; 5048 uint32_t enabled_rb_per_sh; 5049 uint32_t active_rb_bitmap; 5050 uint32_t num_rb_per_sc; 5051 uint32_t num_packer_per_sc; 5052 uint32_t pa_sc_tile_steering_override; 5053 5054 /* for ASICs that integrates GFX v10.3 5055 * pa_sc_tile_steering_override should be set to 0 */ 5056 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 5057 return 0; 5058 5059 /* init num_sc */ 5060 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5061 adev->gfx.config.num_sc_per_sh; 5062 /* init num_rb_per_sc */ 5063 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5064 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5065 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5066 /* init num_packer_per_sc */ 5067 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5068 5069 pa_sc_tile_steering_override = 0; 5070 pa_sc_tile_steering_override |= 5071 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5072 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5073 pa_sc_tile_steering_override |= 5074 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5075 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5076 pa_sc_tile_steering_override |= 5077 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5078 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5079 5080 return pa_sc_tile_steering_override; 5081 } 5082 5083 #define DEFAULT_SH_MEM_BASES (0x6000) 5084 5085 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5086 { 5087 int i; 5088 uint32_t sh_mem_bases; 5089 5090 /* 5091 * Configure apertures: 5092 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5093 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5094 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5095 */ 5096 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5097 5098 mutex_lock(&adev->srbm_mutex); 5099 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5100 nv_grbm_select(adev, 0, 0, 0, i); 5101 /* CP and shaders */ 5102 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5103 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5104 } 5105 nv_grbm_select(adev, 0, 0, 0, 0); 5106 mutex_unlock(&adev->srbm_mutex); 5107 5108 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 5109 acccess. These should be enabled by FW for target VMIDs. */ 5110 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5111 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5112 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5113 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5114 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5115 } 5116 } 5117 5118 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5119 { 5120 int vmid; 5121 5122 /* 5123 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5124 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5125 * the driver can enable them for graphics. VMID0 should maintain 5126 * access so that HWS firmware can save/restore entries. 5127 */ 5128 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5129 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5130 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5131 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5132 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5133 } 5134 } 5135 5136 5137 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5138 { 5139 int i, j, k; 5140 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5141 u32 tmp, wgp_active_bitmap = 0; 5142 u32 gcrd_targets_disable_tcp = 0; 5143 u32 utcl_invreq_disable = 0; 5144 /* 5145 * GCRD_TARGETS_DISABLE field contains 5146 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5147 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5148 */ 5149 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5150 2 * max_wgp_per_sh + /* TCP */ 5151 max_wgp_per_sh + /* SQC */ 5152 4); /* GL1C */ 5153 /* 5154 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5155 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5156 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5157 */ 5158 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5159 2 * max_wgp_per_sh + /* TCP */ 5160 2 * max_wgp_per_sh + /* SQC */ 5161 4 + /* RMI */ 5162 1); /* SQG */ 5163 5164 mutex_lock(&adev->grbm_idx_mutex); 5165 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5166 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5167 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5168 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5169 /* 5170 * Set corresponding TCP bits for the inactive WGPs in 5171 * GCRD_SA_TARGETS_DISABLE 5172 */ 5173 gcrd_targets_disable_tcp = 0; 5174 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5175 utcl_invreq_disable = 0; 5176 5177 for (k = 0; k < max_wgp_per_sh; k++) { 5178 if (!(wgp_active_bitmap & (1 << k))) { 5179 gcrd_targets_disable_tcp |= 3 << (2 * k); 5180 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5181 utcl_invreq_disable |= (3 << (2 * k)) | 5182 (3 << (2 * (max_wgp_per_sh + k))); 5183 } 5184 } 5185 5186 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5187 /* only override TCP & SQC bits */ 5188 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5189 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5190 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5191 5192 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5193 /* only override TCP & SQC bits */ 5194 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5195 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5196 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5197 } 5198 } 5199 5200 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5201 mutex_unlock(&adev->grbm_idx_mutex); 5202 } 5203 5204 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5205 { 5206 /* TCCs are global (not instanced). */ 5207 uint32_t tcc_disable; 5208 5209 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 5210 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5211 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5212 } else { 5213 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5214 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5215 } 5216 5217 adev->gfx.config.tcc_disabled_mask = 5218 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5219 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5220 } 5221 5222 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5223 { 5224 u32 tmp; 5225 int i; 5226 5227 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5228 5229 gfx_v10_0_setup_rb(adev); 5230 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5231 gfx_v10_0_get_tcc_info(adev); 5232 adev->gfx.config.pa_sc_tile_steering_override = 5233 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5234 5235 /* XXX SH_MEM regs */ 5236 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5237 mutex_lock(&adev->srbm_mutex); 5238 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 5239 nv_grbm_select(adev, 0, 0, 0, i); 5240 /* CP and shaders */ 5241 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5242 if (i != 0) { 5243 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5244 (adev->gmc.private_aperture_start >> 48)); 5245 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5246 (adev->gmc.shared_aperture_start >> 48)); 5247 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5248 } 5249 } 5250 nv_grbm_select(adev, 0, 0, 0, 0); 5251 5252 mutex_unlock(&adev->srbm_mutex); 5253 5254 gfx_v10_0_init_compute_vmid(adev); 5255 gfx_v10_0_init_gds_vmid(adev); 5256 5257 } 5258 5259 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5260 bool enable) 5261 { 5262 u32 tmp; 5263 5264 if (amdgpu_sriov_vf(adev)) 5265 return; 5266 5267 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5268 5269 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5270 enable ? 1 : 0); 5271 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5272 enable ? 1 : 0); 5273 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5274 enable ? 1 : 0); 5275 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5276 enable ? 1 : 0); 5277 5278 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5279 } 5280 5281 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5282 { 5283 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5284 5285 /* csib */ 5286 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5287 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5288 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5289 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5290 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5291 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5292 } else { 5293 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5294 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5295 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5296 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5297 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5298 } 5299 return 0; 5300 } 5301 5302 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5303 { 5304 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5305 5306 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5307 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5308 } 5309 5310 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5311 { 5312 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5313 udelay(50); 5314 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5315 udelay(50); 5316 } 5317 5318 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5319 bool enable) 5320 { 5321 uint32_t rlc_pg_cntl; 5322 5323 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5324 5325 if (!enable) { 5326 /* RLC_PG_CNTL[23] = 0 (default) 5327 * RLC will wait for handshake acks with SMU 5328 * GFXOFF will be enabled 5329 * RLC_PG_CNTL[23] = 1 5330 * RLC will not issue any message to SMU 5331 * hence no handshake between SMU & RLC 5332 * GFXOFF will be disabled 5333 */ 5334 rlc_pg_cntl |= 0x800000; 5335 } else 5336 rlc_pg_cntl &= ~0x800000; 5337 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5338 } 5339 5340 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5341 { 5342 /* TODO: enable rlc & smu handshake until smu 5343 * and gfxoff feature works as expected */ 5344 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5345 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5346 5347 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5348 udelay(50); 5349 } 5350 5351 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5352 { 5353 uint32_t tmp; 5354 5355 /* enable Save Restore Machine */ 5356 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5357 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5358 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5359 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5360 } 5361 5362 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5363 { 5364 const struct rlc_firmware_header_v2_0 *hdr; 5365 const __le32 *fw_data; 5366 unsigned i, fw_size; 5367 5368 if (!adev->gfx.rlc_fw) 5369 return -EINVAL; 5370 5371 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5372 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5373 5374 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5375 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5376 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5377 5378 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5379 RLCG_UCODE_LOADING_START_ADDRESS); 5380 5381 for (i = 0; i < fw_size; i++) 5382 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5383 le32_to_cpup(fw_data++)); 5384 5385 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5386 5387 return 0; 5388 } 5389 5390 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5391 { 5392 int r; 5393 5394 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5395 adev->psp.autoload_supported) { 5396 5397 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5398 if (r) 5399 return r; 5400 5401 gfx_v10_0_init_csb(adev); 5402 5403 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5404 gfx_v10_0_rlc_enable_srm(adev); 5405 } else { 5406 if (amdgpu_sriov_vf(adev)) { 5407 gfx_v10_0_init_csb(adev); 5408 return 0; 5409 } 5410 5411 adev->gfx.rlc.funcs->stop(adev); 5412 5413 /* disable CG */ 5414 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5415 5416 /* disable PG */ 5417 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5418 5419 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5420 /* legacy rlc firmware loading */ 5421 r = gfx_v10_0_rlc_load_microcode(adev); 5422 if (r) 5423 return r; 5424 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5425 /* rlc backdoor autoload firmware */ 5426 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5427 if (r) 5428 return r; 5429 } 5430 5431 gfx_v10_0_init_csb(adev); 5432 5433 adev->gfx.rlc.funcs->start(adev); 5434 5435 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5436 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5437 if (r) 5438 return r; 5439 } 5440 } 5441 return 0; 5442 } 5443 5444 static struct { 5445 FIRMWARE_ID id; 5446 unsigned int offset; 5447 unsigned int size; 5448 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5449 5450 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5451 { 5452 int ret; 5453 RLC_TABLE_OF_CONTENT *rlc_toc; 5454 5455 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5456 AMDGPU_GEM_DOMAIN_GTT, 5457 &adev->gfx.rlc.rlc_toc_bo, 5458 &adev->gfx.rlc.rlc_toc_gpu_addr, 5459 (void **)&adev->gfx.rlc.rlc_toc_buf); 5460 if (ret) { 5461 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5462 return ret; 5463 } 5464 5465 /* Copy toc from psp sos fw to rlc toc buffer */ 5466 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5467 5468 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5469 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5470 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5471 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5472 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5473 /* Offset needs 4KB alignment */ 5474 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5475 } 5476 5477 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5478 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5479 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5480 5481 rlc_toc++; 5482 } 5483 5484 return 0; 5485 } 5486 5487 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5488 { 5489 uint32_t total_size = 0; 5490 FIRMWARE_ID id; 5491 int ret; 5492 5493 ret = gfx_v10_0_parse_rlc_toc(adev); 5494 if (ret) { 5495 dev_err(adev->dev, "failed to parse rlc toc\n"); 5496 return 0; 5497 } 5498 5499 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5500 total_size += rlc_autoload_info[id].size; 5501 5502 /* In case the offset in rlc toc ucode is aligned */ 5503 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5504 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5505 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5506 5507 return total_size; 5508 } 5509 5510 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5511 { 5512 int r; 5513 uint32_t total_size; 5514 5515 total_size = gfx_v10_0_calc_toc_total_size(adev); 5516 5517 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5518 AMDGPU_GEM_DOMAIN_GTT, 5519 &adev->gfx.rlc.rlc_autoload_bo, 5520 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5521 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5522 if (r) { 5523 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5524 return r; 5525 } 5526 5527 return 0; 5528 } 5529 5530 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5531 { 5532 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5533 &adev->gfx.rlc.rlc_toc_gpu_addr, 5534 (void **)&adev->gfx.rlc.rlc_toc_buf); 5535 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5536 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5537 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5538 } 5539 5540 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5541 FIRMWARE_ID id, 5542 const void *fw_data, 5543 uint32_t fw_size) 5544 { 5545 uint32_t toc_offset; 5546 uint32_t toc_fw_size; 5547 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5548 5549 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5550 return; 5551 5552 toc_offset = rlc_autoload_info[id].offset; 5553 toc_fw_size = rlc_autoload_info[id].size; 5554 5555 if (fw_size == 0) 5556 fw_size = toc_fw_size; 5557 5558 if (fw_size > toc_fw_size) 5559 fw_size = toc_fw_size; 5560 5561 memcpy(ptr + toc_offset, fw_data, fw_size); 5562 5563 if (fw_size < toc_fw_size) 5564 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5565 } 5566 5567 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5568 { 5569 void *data; 5570 uint32_t size; 5571 5572 data = adev->gfx.rlc.rlc_toc_buf; 5573 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5574 5575 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5576 FIRMWARE_ID_RLC_TOC, 5577 data, size); 5578 } 5579 5580 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5581 { 5582 const __le32 *fw_data; 5583 uint32_t fw_size; 5584 const struct gfx_firmware_header_v1_0 *cp_hdr; 5585 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5586 5587 /* pfp ucode */ 5588 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5589 adev->gfx.pfp_fw->data; 5590 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5591 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5592 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5593 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5594 FIRMWARE_ID_CP_PFP, 5595 fw_data, fw_size); 5596 5597 /* ce ucode */ 5598 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5599 adev->gfx.ce_fw->data; 5600 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5601 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5602 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5603 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5604 FIRMWARE_ID_CP_CE, 5605 fw_data, fw_size); 5606 5607 /* me ucode */ 5608 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5609 adev->gfx.me_fw->data; 5610 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5611 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5612 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5613 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5614 FIRMWARE_ID_CP_ME, 5615 fw_data, fw_size); 5616 5617 /* rlc ucode */ 5618 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5619 adev->gfx.rlc_fw->data; 5620 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5621 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5622 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5623 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5624 FIRMWARE_ID_RLC_G_UCODE, 5625 fw_data, fw_size); 5626 5627 /* mec1 ucode */ 5628 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5629 adev->gfx.mec_fw->data; 5630 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5631 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5632 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5633 cp_hdr->jt_size * 4; 5634 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5635 FIRMWARE_ID_CP_MEC, 5636 fw_data, fw_size); 5637 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5638 } 5639 5640 /* Temporarily put sdma part here */ 5641 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5642 { 5643 const __le32 *fw_data; 5644 uint32_t fw_size; 5645 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5646 int i; 5647 5648 for (i = 0; i < adev->sdma.num_instances; i++) { 5649 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5650 adev->sdma.instance[i].fw->data; 5651 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5652 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5653 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5654 5655 if (i == 0) { 5656 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5657 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5658 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5659 FIRMWARE_ID_SDMA0_JT, 5660 (uint32_t *)fw_data + 5661 sdma_hdr->jt_offset, 5662 sdma_hdr->jt_size * 4); 5663 } else if (i == 1) { 5664 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5665 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5666 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5667 FIRMWARE_ID_SDMA1_JT, 5668 (uint32_t *)fw_data + 5669 sdma_hdr->jt_offset, 5670 sdma_hdr->jt_size * 4); 5671 } 5672 } 5673 } 5674 5675 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5676 { 5677 uint32_t rlc_g_offset, rlc_g_size, tmp; 5678 uint64_t gpu_addr; 5679 5680 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5681 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5682 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5683 5684 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5685 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5686 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5687 5688 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5689 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5690 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5691 5692 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5693 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5694 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5695 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5696 return -EINVAL; 5697 } 5698 5699 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5700 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5701 DRM_ERROR("RLC ROM should halt itself\n"); 5702 return -EINVAL; 5703 } 5704 5705 return 0; 5706 } 5707 5708 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5709 { 5710 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5711 uint32_t tmp; 5712 int i; 5713 uint64_t addr; 5714 5715 /* Trigger an invalidation of the L1 instruction caches */ 5716 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5717 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5718 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5719 5720 /* Wait for invalidation complete */ 5721 for (i = 0; i < usec_timeout; i++) { 5722 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5723 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5724 INVALIDATE_CACHE_COMPLETE)) 5725 break; 5726 udelay(1); 5727 } 5728 5729 if (i >= usec_timeout) { 5730 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5731 return -EINVAL; 5732 } 5733 5734 /* Program me ucode address into intruction cache address register */ 5735 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5736 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5737 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5738 lower_32_bits(addr) & 0xFFFFF000); 5739 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5740 upper_32_bits(addr)); 5741 5742 return 0; 5743 } 5744 5745 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5746 { 5747 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5748 uint32_t tmp; 5749 int i; 5750 uint64_t addr; 5751 5752 /* Trigger an invalidation of the L1 instruction caches */ 5753 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5754 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5755 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5756 5757 /* Wait for invalidation complete */ 5758 for (i = 0; i < usec_timeout; i++) { 5759 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5760 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5761 INVALIDATE_CACHE_COMPLETE)) 5762 break; 5763 udelay(1); 5764 } 5765 5766 if (i >= usec_timeout) { 5767 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5768 return -EINVAL; 5769 } 5770 5771 /* Program ce ucode address into intruction cache address register */ 5772 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5773 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5774 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5775 lower_32_bits(addr) & 0xFFFFF000); 5776 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5777 upper_32_bits(addr)); 5778 5779 return 0; 5780 } 5781 5782 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5783 { 5784 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5785 uint32_t tmp; 5786 int i; 5787 uint64_t addr; 5788 5789 /* Trigger an invalidation of the L1 instruction caches */ 5790 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5791 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5792 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5793 5794 /* Wait for invalidation complete */ 5795 for (i = 0; i < usec_timeout; i++) { 5796 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5797 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5798 INVALIDATE_CACHE_COMPLETE)) 5799 break; 5800 udelay(1); 5801 } 5802 5803 if (i >= usec_timeout) { 5804 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5805 return -EINVAL; 5806 } 5807 5808 /* Program pfp ucode address into intruction cache address register */ 5809 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5810 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5811 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5812 lower_32_bits(addr) & 0xFFFFF000); 5813 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5814 upper_32_bits(addr)); 5815 5816 return 0; 5817 } 5818 5819 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5820 { 5821 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5822 uint32_t tmp; 5823 int i; 5824 uint64_t addr; 5825 5826 /* Trigger an invalidation of the L1 instruction caches */ 5827 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5828 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5829 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5830 5831 /* Wait for invalidation complete */ 5832 for (i = 0; i < usec_timeout; i++) { 5833 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5834 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5835 INVALIDATE_CACHE_COMPLETE)) 5836 break; 5837 udelay(1); 5838 } 5839 5840 if (i >= usec_timeout) { 5841 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5842 return -EINVAL; 5843 } 5844 5845 /* Program mec1 ucode address into intruction cache address register */ 5846 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5847 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5848 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5849 lower_32_bits(addr) & 0xFFFFF000); 5850 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5851 upper_32_bits(addr)); 5852 5853 return 0; 5854 } 5855 5856 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5857 { 5858 uint32_t cp_status; 5859 uint32_t bootload_status; 5860 int i, r; 5861 5862 for (i = 0; i < adev->usec_timeout; i++) { 5863 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5864 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5865 if ((cp_status == 0) && 5866 (REG_GET_FIELD(bootload_status, 5867 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5868 break; 5869 } 5870 udelay(1); 5871 } 5872 5873 if (i >= adev->usec_timeout) { 5874 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5875 return -ETIMEDOUT; 5876 } 5877 5878 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5879 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5880 if (r) 5881 return r; 5882 5883 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5884 if (r) 5885 return r; 5886 5887 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5888 if (r) 5889 return r; 5890 5891 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5892 if (r) 5893 return r; 5894 } 5895 5896 return 0; 5897 } 5898 5899 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5900 { 5901 int i; 5902 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5903 5904 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5905 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5906 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5907 5908 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5909 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5910 } else { 5911 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5912 } 5913 5914 for (i = 0; i < adev->usec_timeout; i++) { 5915 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5916 break; 5917 udelay(1); 5918 } 5919 5920 if (i >= adev->usec_timeout) 5921 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5922 5923 return 0; 5924 } 5925 5926 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5927 { 5928 int r; 5929 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5930 const __le32 *fw_data; 5931 unsigned i, fw_size; 5932 uint32_t tmp; 5933 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5934 5935 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5936 adev->gfx.pfp_fw->data; 5937 5938 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5939 5940 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5941 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5942 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5943 5944 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5945 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5946 &adev->gfx.pfp.pfp_fw_obj, 5947 &adev->gfx.pfp.pfp_fw_gpu_addr, 5948 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5949 if (r) { 5950 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5951 gfx_v10_0_pfp_fini(adev); 5952 return r; 5953 } 5954 5955 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5956 5957 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5958 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5959 5960 /* Trigger an invalidation of the L1 instruction caches */ 5961 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5962 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5963 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5964 5965 /* Wait for invalidation complete */ 5966 for (i = 0; i < usec_timeout; i++) { 5967 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5968 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5969 INVALIDATE_CACHE_COMPLETE)) 5970 break; 5971 udelay(1); 5972 } 5973 5974 if (i >= usec_timeout) { 5975 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5976 return -EINVAL; 5977 } 5978 5979 if (amdgpu_emu_mode == 1) 5980 adev->hdp.funcs->flush_hdp(adev, NULL); 5981 5982 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5983 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5984 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5985 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5986 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5987 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5988 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5989 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5990 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5991 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5992 5993 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5994 5995 for (i = 0; i < pfp_hdr->jt_size; i++) 5996 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5997 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5998 5999 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6000 6001 return 0; 6002 } 6003 6004 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6005 { 6006 int r; 6007 const struct gfx_firmware_header_v1_0 *ce_hdr; 6008 const __le32 *fw_data; 6009 unsigned i, fw_size; 6010 uint32_t tmp; 6011 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6012 6013 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6014 adev->gfx.ce_fw->data; 6015 6016 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6017 6018 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6019 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6020 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6021 6022 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6023 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6024 &adev->gfx.ce.ce_fw_obj, 6025 &adev->gfx.ce.ce_fw_gpu_addr, 6026 (void **)&adev->gfx.ce.ce_fw_ptr); 6027 if (r) { 6028 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6029 gfx_v10_0_ce_fini(adev); 6030 return r; 6031 } 6032 6033 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6034 6035 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6036 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6037 6038 /* Trigger an invalidation of the L1 instruction caches */ 6039 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6040 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6041 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6042 6043 /* Wait for invalidation complete */ 6044 for (i = 0; i < usec_timeout; i++) { 6045 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6046 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6047 INVALIDATE_CACHE_COMPLETE)) 6048 break; 6049 udelay(1); 6050 } 6051 6052 if (i >= usec_timeout) { 6053 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6054 return -EINVAL; 6055 } 6056 6057 if (amdgpu_emu_mode == 1) 6058 adev->hdp.funcs->flush_hdp(adev, NULL); 6059 6060 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6061 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6062 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6063 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6064 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6065 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6066 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6067 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6068 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6069 6070 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6071 6072 for (i = 0; i < ce_hdr->jt_size; i++) 6073 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6074 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6075 6076 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6077 6078 return 0; 6079 } 6080 6081 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6082 { 6083 int r; 6084 const struct gfx_firmware_header_v1_0 *me_hdr; 6085 const __le32 *fw_data; 6086 unsigned i, fw_size; 6087 uint32_t tmp; 6088 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6089 6090 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6091 adev->gfx.me_fw->data; 6092 6093 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6094 6095 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6096 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6097 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6098 6099 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6100 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6101 &adev->gfx.me.me_fw_obj, 6102 &adev->gfx.me.me_fw_gpu_addr, 6103 (void **)&adev->gfx.me.me_fw_ptr); 6104 if (r) { 6105 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6106 gfx_v10_0_me_fini(adev); 6107 return r; 6108 } 6109 6110 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6111 6112 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6113 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6114 6115 /* Trigger an invalidation of the L1 instruction caches */ 6116 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6117 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6118 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6119 6120 /* Wait for invalidation complete */ 6121 for (i = 0; i < usec_timeout; i++) { 6122 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6123 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6124 INVALIDATE_CACHE_COMPLETE)) 6125 break; 6126 udelay(1); 6127 } 6128 6129 if (i >= usec_timeout) { 6130 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6131 return -EINVAL; 6132 } 6133 6134 if (amdgpu_emu_mode == 1) 6135 adev->hdp.funcs->flush_hdp(adev, NULL); 6136 6137 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6138 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6139 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6140 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6141 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6142 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6143 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6144 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6145 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6146 6147 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6148 6149 for (i = 0; i < me_hdr->jt_size; i++) 6150 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6151 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6152 6153 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6154 6155 return 0; 6156 } 6157 6158 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6159 { 6160 int r; 6161 6162 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6163 return -EINVAL; 6164 6165 gfx_v10_0_cp_gfx_enable(adev, false); 6166 6167 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6168 if (r) { 6169 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6170 return r; 6171 } 6172 6173 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6174 if (r) { 6175 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6176 return r; 6177 } 6178 6179 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6180 if (r) { 6181 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6182 return r; 6183 } 6184 6185 return 0; 6186 } 6187 6188 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6189 { 6190 struct amdgpu_ring *ring; 6191 const struct cs_section_def *sect = NULL; 6192 const struct cs_extent_def *ext = NULL; 6193 int r, i; 6194 int ctx_reg_offset; 6195 6196 /* init the CP */ 6197 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6198 adev->gfx.config.max_hw_contexts - 1); 6199 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6200 6201 gfx_v10_0_cp_gfx_enable(adev, true); 6202 6203 ring = &adev->gfx.gfx_ring[0]; 6204 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6205 if (r) { 6206 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6207 return r; 6208 } 6209 6210 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6211 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6212 6213 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6214 amdgpu_ring_write(ring, 0x80000000); 6215 amdgpu_ring_write(ring, 0x80000000); 6216 6217 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6218 for (ext = sect->section; ext->extent != NULL; ++ext) { 6219 if (sect->id == SECT_CONTEXT) { 6220 amdgpu_ring_write(ring, 6221 PACKET3(PACKET3_SET_CONTEXT_REG, 6222 ext->reg_count)); 6223 amdgpu_ring_write(ring, ext->reg_index - 6224 PACKET3_SET_CONTEXT_REG_START); 6225 for (i = 0; i < ext->reg_count; i++) 6226 amdgpu_ring_write(ring, ext->extent[i]); 6227 } 6228 } 6229 } 6230 6231 ctx_reg_offset = 6232 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6233 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6234 amdgpu_ring_write(ring, ctx_reg_offset); 6235 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6236 6237 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6238 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6239 6240 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6241 amdgpu_ring_write(ring, 0); 6242 6243 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6244 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6245 amdgpu_ring_write(ring, 0x8000); 6246 amdgpu_ring_write(ring, 0x8000); 6247 6248 amdgpu_ring_commit(ring); 6249 6250 /* submit cs packet to copy state 0 to next available state */ 6251 if (adev->gfx.num_gfx_rings > 1) { 6252 /* maximum supported gfx ring is 2 */ 6253 ring = &adev->gfx.gfx_ring[1]; 6254 r = amdgpu_ring_alloc(ring, 2); 6255 if (r) { 6256 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6257 return r; 6258 } 6259 6260 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6261 amdgpu_ring_write(ring, 0); 6262 6263 amdgpu_ring_commit(ring); 6264 } 6265 return 0; 6266 } 6267 6268 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6269 CP_PIPE_ID pipe) 6270 { 6271 u32 tmp; 6272 6273 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6274 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6275 6276 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6277 } 6278 6279 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6280 struct amdgpu_ring *ring) 6281 { 6282 u32 tmp; 6283 6284 if (!amdgpu_async_gfx_ring) { 6285 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6286 if (ring->use_doorbell) { 6287 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6288 DOORBELL_OFFSET, ring->doorbell_index); 6289 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6290 DOORBELL_EN, 1); 6291 } else { 6292 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6293 DOORBELL_EN, 0); 6294 } 6295 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6296 } 6297 switch (adev->ip_versions[GC_HWIP][0]) { 6298 case IP_VERSION(10, 3, 0): 6299 case IP_VERSION(10, 3, 2): 6300 case IP_VERSION(10, 3, 1): 6301 case IP_VERSION(10, 3, 4): 6302 case IP_VERSION(10, 3, 5): 6303 case IP_VERSION(10, 3, 6): 6304 case IP_VERSION(10, 3, 3): 6305 case IP_VERSION(10, 3, 7): 6306 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6307 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6308 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6309 6310 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6311 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6312 break; 6313 default: 6314 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6315 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6316 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6317 6318 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6319 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6320 break; 6321 } 6322 } 6323 6324 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6325 { 6326 struct amdgpu_ring *ring; 6327 u32 tmp; 6328 u32 rb_bufsz; 6329 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6330 u32 i; 6331 6332 /* Set the write pointer delay */ 6333 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6334 6335 /* set the RB to use vmid 0 */ 6336 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6337 6338 /* Init gfx ring 0 for pipe 0 */ 6339 mutex_lock(&adev->srbm_mutex); 6340 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6341 6342 /* Set ring buffer size */ 6343 ring = &adev->gfx.gfx_ring[0]; 6344 rb_bufsz = order_base_2(ring->ring_size / 8); 6345 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6346 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6347 #ifdef __BIG_ENDIAN 6348 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6349 #endif 6350 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6351 6352 /* Initialize the ring buffer's write pointers */ 6353 ring->wptr = 0; 6354 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6355 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6356 6357 /* set the wb address wether it's enabled or not */ 6358 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6359 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6360 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6361 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6362 6363 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6364 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6365 lower_32_bits(wptr_gpu_addr)); 6366 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6367 upper_32_bits(wptr_gpu_addr)); 6368 6369 mdelay(1); 6370 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6371 6372 rb_addr = ring->gpu_addr >> 8; 6373 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6374 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6375 6376 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6377 6378 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6379 mutex_unlock(&adev->srbm_mutex); 6380 6381 /* Init gfx ring 1 for pipe 1 */ 6382 if (adev->gfx.num_gfx_rings > 1) { 6383 mutex_lock(&adev->srbm_mutex); 6384 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6385 /* maximum supported gfx ring is 2 */ 6386 ring = &adev->gfx.gfx_ring[1]; 6387 rb_bufsz = order_base_2(ring->ring_size / 8); 6388 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6389 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6390 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6391 /* Initialize the ring buffer's write pointers */ 6392 ring->wptr = 0; 6393 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6394 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6395 /* Set the wb address wether it's enabled or not */ 6396 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6397 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6398 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6399 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6400 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6401 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6402 lower_32_bits(wptr_gpu_addr)); 6403 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6404 upper_32_bits(wptr_gpu_addr)); 6405 6406 mdelay(1); 6407 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6408 6409 rb_addr = ring->gpu_addr >> 8; 6410 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6411 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6412 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6413 6414 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6415 mutex_unlock(&adev->srbm_mutex); 6416 } 6417 /* Switch to pipe 0 */ 6418 mutex_lock(&adev->srbm_mutex); 6419 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6420 mutex_unlock(&adev->srbm_mutex); 6421 6422 /* start the ring */ 6423 gfx_v10_0_cp_gfx_start(adev); 6424 6425 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6426 ring = &adev->gfx.gfx_ring[i]; 6427 ring->sched.ready = true; 6428 } 6429 6430 return 0; 6431 } 6432 6433 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6434 { 6435 if (enable) { 6436 switch (adev->ip_versions[GC_HWIP][0]) { 6437 case IP_VERSION(10, 3, 0): 6438 case IP_VERSION(10, 3, 2): 6439 case IP_VERSION(10, 3, 1): 6440 case IP_VERSION(10, 3, 4): 6441 case IP_VERSION(10, 3, 5): 6442 case IP_VERSION(10, 3, 6): 6443 case IP_VERSION(10, 3, 3): 6444 case IP_VERSION(10, 3, 7): 6445 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6446 break; 6447 default: 6448 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6449 break; 6450 } 6451 } else { 6452 switch (adev->ip_versions[GC_HWIP][0]) { 6453 case IP_VERSION(10, 3, 0): 6454 case IP_VERSION(10, 3, 2): 6455 case IP_VERSION(10, 3, 1): 6456 case IP_VERSION(10, 3, 4): 6457 case IP_VERSION(10, 3, 5): 6458 case IP_VERSION(10, 3, 6): 6459 case IP_VERSION(10, 3, 3): 6460 case IP_VERSION(10, 3, 7): 6461 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6462 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6463 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6464 break; 6465 default: 6466 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6467 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6468 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6469 break; 6470 } 6471 adev->gfx.kiq.ring.sched.ready = false; 6472 } 6473 udelay(50); 6474 } 6475 6476 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6477 { 6478 const struct gfx_firmware_header_v1_0 *mec_hdr; 6479 const __le32 *fw_data; 6480 unsigned i; 6481 u32 tmp; 6482 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6483 6484 if (!adev->gfx.mec_fw) 6485 return -EINVAL; 6486 6487 gfx_v10_0_cp_compute_enable(adev, false); 6488 6489 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6490 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6491 6492 fw_data = (const __le32 *) 6493 (adev->gfx.mec_fw->data + 6494 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6495 6496 /* Trigger an invalidation of the L1 instruction caches */ 6497 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6498 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6499 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6500 6501 /* Wait for invalidation complete */ 6502 for (i = 0; i < usec_timeout; i++) { 6503 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6504 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6505 INVALIDATE_CACHE_COMPLETE)) 6506 break; 6507 udelay(1); 6508 } 6509 6510 if (i >= usec_timeout) { 6511 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6512 return -EINVAL; 6513 } 6514 6515 if (amdgpu_emu_mode == 1) 6516 adev->hdp.funcs->flush_hdp(adev, NULL); 6517 6518 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6519 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6520 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6521 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6522 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6523 6524 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6525 0xFFFFF000); 6526 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6527 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6528 6529 /* MEC1 */ 6530 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6531 6532 for (i = 0; i < mec_hdr->jt_size; i++) 6533 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6534 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6535 6536 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6537 6538 /* 6539 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6540 * different microcode than MEC1. 6541 */ 6542 6543 return 0; 6544 } 6545 6546 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6547 { 6548 uint32_t tmp; 6549 struct amdgpu_device *adev = ring->adev; 6550 6551 /* tell RLC which is KIQ queue */ 6552 switch (adev->ip_versions[GC_HWIP][0]) { 6553 case IP_VERSION(10, 3, 0): 6554 case IP_VERSION(10, 3, 2): 6555 case IP_VERSION(10, 3, 1): 6556 case IP_VERSION(10, 3, 4): 6557 case IP_VERSION(10, 3, 5): 6558 case IP_VERSION(10, 3, 6): 6559 case IP_VERSION(10, 3, 3): 6560 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6561 tmp &= 0xffffff00; 6562 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6563 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6564 tmp |= 0x80; 6565 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6566 break; 6567 default: 6568 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6569 tmp &= 0xffffff00; 6570 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6571 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6572 tmp |= 0x80; 6573 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6574 break; 6575 } 6576 } 6577 6578 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6579 { 6580 struct amdgpu_device *adev = ring->adev; 6581 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6582 uint64_t hqd_gpu_addr, wb_gpu_addr; 6583 uint32_t tmp; 6584 uint32_t rb_bufsz; 6585 6586 /* set up gfx hqd wptr */ 6587 mqd->cp_gfx_hqd_wptr = 0; 6588 mqd->cp_gfx_hqd_wptr_hi = 0; 6589 6590 /* set the pointer to the MQD */ 6591 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6592 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6593 6594 /* set up mqd control */ 6595 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6596 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6597 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6598 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6599 mqd->cp_gfx_mqd_control = tmp; 6600 6601 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6602 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6603 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6604 mqd->cp_gfx_hqd_vmid = 0; 6605 6606 /* set up default queue priority level 6607 * 0x0 = low priority, 0x1 = high priority */ 6608 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6609 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6610 mqd->cp_gfx_hqd_queue_priority = tmp; 6611 6612 /* set up time quantum */ 6613 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6614 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6615 mqd->cp_gfx_hqd_quantum = tmp; 6616 6617 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6618 hqd_gpu_addr = ring->gpu_addr >> 8; 6619 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6620 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6621 6622 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6623 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6624 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6625 mqd->cp_gfx_hqd_rptr_addr_hi = 6626 upper_32_bits(wb_gpu_addr) & 0xffff; 6627 6628 /* set up rb_wptr_poll addr */ 6629 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6630 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6631 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6632 6633 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6634 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6635 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6636 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6637 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6638 #ifdef __BIG_ENDIAN 6639 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6640 #endif 6641 mqd->cp_gfx_hqd_cntl = tmp; 6642 6643 /* set up cp_doorbell_control */ 6644 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6645 if (ring->use_doorbell) { 6646 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6647 DOORBELL_OFFSET, ring->doorbell_index); 6648 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6649 DOORBELL_EN, 1); 6650 } else 6651 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6652 DOORBELL_EN, 0); 6653 mqd->cp_rb_doorbell_control = tmp; 6654 6655 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6656 *otherwise the range of the second ring will override the first ring */ 6657 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6658 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6659 6660 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6661 ring->wptr = 0; 6662 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6663 6664 /* active the queue */ 6665 mqd->cp_gfx_hqd_active = 1; 6666 6667 return 0; 6668 } 6669 6670 #ifdef BRING_UP_DEBUG 6671 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6672 { 6673 struct amdgpu_device *adev = ring->adev; 6674 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6675 6676 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6677 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6678 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6679 6680 /* set GFX_MQD_BASE */ 6681 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6682 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6683 6684 /* set GFX_MQD_CONTROL */ 6685 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6686 6687 /* set GFX_HQD_VMID to 0 */ 6688 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6689 6690 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6691 mqd->cp_gfx_hqd_queue_priority); 6692 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6693 6694 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6695 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6696 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6697 6698 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6699 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6700 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6701 6702 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6703 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6704 6705 /* set RB_WPTR_POLL_ADDR */ 6706 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6707 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6708 6709 /* set RB_DOORBELL_CONTROL */ 6710 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6711 6712 /* active the queue */ 6713 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6714 6715 return 0; 6716 } 6717 #endif 6718 6719 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6720 { 6721 struct amdgpu_device *adev = ring->adev; 6722 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6723 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6724 6725 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6726 memset((void *)mqd, 0, sizeof(*mqd)); 6727 mutex_lock(&adev->srbm_mutex); 6728 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6729 gfx_v10_0_gfx_mqd_init(ring); 6730 #ifdef BRING_UP_DEBUG 6731 gfx_v10_0_gfx_queue_init_register(ring); 6732 #endif 6733 nv_grbm_select(adev, 0, 0, 0, 0); 6734 mutex_unlock(&adev->srbm_mutex); 6735 if (adev->gfx.me.mqd_backup[mqd_idx]) 6736 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6737 } else if (amdgpu_in_reset(adev)) { 6738 /* reset mqd with the backup copy */ 6739 if (adev->gfx.me.mqd_backup[mqd_idx]) 6740 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6741 /* reset the ring */ 6742 ring->wptr = 0; 6743 adev->wb.wb[ring->wptr_offs] = 0; 6744 amdgpu_ring_clear_ring(ring); 6745 #ifdef BRING_UP_DEBUG 6746 mutex_lock(&adev->srbm_mutex); 6747 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6748 gfx_v10_0_gfx_queue_init_register(ring); 6749 nv_grbm_select(adev, 0, 0, 0, 0); 6750 mutex_unlock(&adev->srbm_mutex); 6751 #endif 6752 } else { 6753 amdgpu_ring_clear_ring(ring); 6754 } 6755 6756 return 0; 6757 } 6758 6759 #ifndef BRING_UP_DEBUG 6760 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6761 { 6762 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6763 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6764 int r, i; 6765 6766 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6767 return -EINVAL; 6768 6769 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6770 adev->gfx.num_gfx_rings); 6771 if (r) { 6772 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6773 return r; 6774 } 6775 6776 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6777 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6778 6779 return amdgpu_ring_test_helper(kiq_ring); 6780 } 6781 #endif 6782 6783 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6784 { 6785 int r, i; 6786 struct amdgpu_ring *ring; 6787 6788 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6789 ring = &adev->gfx.gfx_ring[i]; 6790 6791 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6792 if (unlikely(r != 0)) 6793 goto done; 6794 6795 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6796 if (!r) { 6797 r = gfx_v10_0_gfx_init_queue(ring); 6798 amdgpu_bo_kunmap(ring->mqd_obj); 6799 ring->mqd_ptr = NULL; 6800 } 6801 amdgpu_bo_unreserve(ring->mqd_obj); 6802 if (r) 6803 goto done; 6804 } 6805 #ifndef BRING_UP_DEBUG 6806 r = gfx_v10_0_kiq_enable_kgq(adev); 6807 if (r) 6808 goto done; 6809 #endif 6810 r = gfx_v10_0_cp_gfx_start(adev); 6811 if (r) 6812 goto done; 6813 6814 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6815 ring = &adev->gfx.gfx_ring[i]; 6816 ring->sched.ready = true; 6817 } 6818 done: 6819 return r; 6820 } 6821 6822 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6823 { 6824 struct amdgpu_device *adev = ring->adev; 6825 6826 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6827 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 6828 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6829 mqd->cp_hqd_queue_priority = 6830 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6831 } 6832 } 6833 } 6834 6835 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6836 { 6837 struct amdgpu_device *adev = ring->adev; 6838 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6839 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6840 uint32_t tmp; 6841 6842 mqd->header = 0xC0310800; 6843 mqd->compute_pipelinestat_enable = 0x00000001; 6844 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6845 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6846 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6847 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6848 mqd->compute_misc_reserved = 0x00000003; 6849 6850 eop_base_addr = ring->eop_gpu_addr >> 8; 6851 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6852 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6853 6854 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6855 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6856 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6857 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6858 6859 mqd->cp_hqd_eop_control = tmp; 6860 6861 /* enable doorbell? */ 6862 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6863 6864 if (ring->use_doorbell) { 6865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6866 DOORBELL_OFFSET, ring->doorbell_index); 6867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6868 DOORBELL_EN, 1); 6869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6870 DOORBELL_SOURCE, 0); 6871 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6872 DOORBELL_HIT, 0); 6873 } else { 6874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6875 DOORBELL_EN, 0); 6876 } 6877 6878 mqd->cp_hqd_pq_doorbell_control = tmp; 6879 6880 /* disable the queue if it's active */ 6881 ring->wptr = 0; 6882 mqd->cp_hqd_dequeue_request = 0; 6883 mqd->cp_hqd_pq_rptr = 0; 6884 mqd->cp_hqd_pq_wptr_lo = 0; 6885 mqd->cp_hqd_pq_wptr_hi = 0; 6886 6887 /* set the pointer to the MQD */ 6888 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6889 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6890 6891 /* set MQD vmid to 0 */ 6892 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6893 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6894 mqd->cp_mqd_control = tmp; 6895 6896 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6897 hqd_gpu_addr = ring->gpu_addr >> 8; 6898 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6899 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6900 6901 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6902 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6903 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6904 (order_base_2(ring->ring_size / 4) - 1)); 6905 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6906 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6907 #ifdef __BIG_ENDIAN 6908 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6909 #endif 6910 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6914 mqd->cp_hqd_pq_control = tmp; 6915 6916 /* set the wb address whether it's enabled or not */ 6917 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6918 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6919 mqd->cp_hqd_pq_rptr_report_addr_hi = 6920 upper_32_bits(wb_gpu_addr) & 0xffff; 6921 6922 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6923 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6924 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6925 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6926 6927 tmp = 0; 6928 /* enable the doorbell if requested */ 6929 if (ring->use_doorbell) { 6930 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6931 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6932 DOORBELL_OFFSET, ring->doorbell_index); 6933 6934 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6935 DOORBELL_EN, 1); 6936 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6937 DOORBELL_SOURCE, 0); 6938 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6939 DOORBELL_HIT, 0); 6940 } 6941 6942 mqd->cp_hqd_pq_doorbell_control = tmp; 6943 6944 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6945 ring->wptr = 0; 6946 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6947 6948 /* set the vmid for the queue */ 6949 mqd->cp_hqd_vmid = 0; 6950 6951 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6952 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6953 mqd->cp_hqd_persistent_state = tmp; 6954 6955 /* set MIN_IB_AVAIL_SIZE */ 6956 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6957 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6958 mqd->cp_hqd_ib_control = tmp; 6959 6960 /* set static priority for a compute queue/ring */ 6961 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6962 6963 /* map_queues packet doesn't need activate the queue, 6964 * so only kiq need set this field. 6965 */ 6966 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6967 mqd->cp_hqd_active = 1; 6968 6969 return 0; 6970 } 6971 6972 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6973 { 6974 struct amdgpu_device *adev = ring->adev; 6975 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6976 int j; 6977 6978 /* inactivate the queue */ 6979 if (amdgpu_sriov_vf(adev)) 6980 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6981 6982 /* disable wptr polling */ 6983 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6984 6985 /* write the EOP addr */ 6986 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6987 mqd->cp_hqd_eop_base_addr_lo); 6988 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6989 mqd->cp_hqd_eop_base_addr_hi); 6990 6991 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6992 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6993 mqd->cp_hqd_eop_control); 6994 6995 /* enable doorbell? */ 6996 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6997 mqd->cp_hqd_pq_doorbell_control); 6998 6999 /* disable the queue if it's active */ 7000 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7001 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7002 for (j = 0; j < adev->usec_timeout; j++) { 7003 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7004 break; 7005 udelay(1); 7006 } 7007 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7008 mqd->cp_hqd_dequeue_request); 7009 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7010 mqd->cp_hqd_pq_rptr); 7011 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7012 mqd->cp_hqd_pq_wptr_lo); 7013 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7014 mqd->cp_hqd_pq_wptr_hi); 7015 } 7016 7017 /* set the pointer to the MQD */ 7018 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7019 mqd->cp_mqd_base_addr_lo); 7020 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7021 mqd->cp_mqd_base_addr_hi); 7022 7023 /* set MQD vmid to 0 */ 7024 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7025 mqd->cp_mqd_control); 7026 7027 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7028 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7029 mqd->cp_hqd_pq_base_lo); 7030 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7031 mqd->cp_hqd_pq_base_hi); 7032 7033 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7034 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7035 mqd->cp_hqd_pq_control); 7036 7037 /* set the wb address whether it's enabled or not */ 7038 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7039 mqd->cp_hqd_pq_rptr_report_addr_lo); 7040 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7041 mqd->cp_hqd_pq_rptr_report_addr_hi); 7042 7043 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7044 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7045 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7046 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7047 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7048 7049 /* enable the doorbell if requested */ 7050 if (ring->use_doorbell) { 7051 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7052 (adev->doorbell_index.kiq * 2) << 2); 7053 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7054 (adev->doorbell_index.userqueue_end * 2) << 2); 7055 } 7056 7057 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7058 mqd->cp_hqd_pq_doorbell_control); 7059 7060 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7061 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7062 mqd->cp_hqd_pq_wptr_lo); 7063 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7064 mqd->cp_hqd_pq_wptr_hi); 7065 7066 /* set the vmid for the queue */ 7067 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7068 7069 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7070 mqd->cp_hqd_persistent_state); 7071 7072 /* activate the queue */ 7073 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7074 mqd->cp_hqd_active); 7075 7076 if (ring->use_doorbell) 7077 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7078 7079 return 0; 7080 } 7081 7082 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7083 { 7084 struct amdgpu_device *adev = ring->adev; 7085 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7086 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 7087 7088 gfx_v10_0_kiq_setting(ring); 7089 7090 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7091 /* reset MQD to a clean status */ 7092 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7093 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7094 7095 /* reset ring buffer */ 7096 ring->wptr = 0; 7097 amdgpu_ring_clear_ring(ring); 7098 7099 mutex_lock(&adev->srbm_mutex); 7100 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7101 gfx_v10_0_kiq_init_register(ring); 7102 nv_grbm_select(adev, 0, 0, 0, 0); 7103 mutex_unlock(&adev->srbm_mutex); 7104 } else { 7105 memset((void *)mqd, 0, sizeof(*mqd)); 7106 mutex_lock(&adev->srbm_mutex); 7107 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7108 gfx_v10_0_compute_mqd_init(ring); 7109 gfx_v10_0_kiq_init_register(ring); 7110 nv_grbm_select(adev, 0, 0, 0, 0); 7111 mutex_unlock(&adev->srbm_mutex); 7112 7113 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7114 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7115 } 7116 7117 return 0; 7118 } 7119 7120 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 7121 { 7122 struct amdgpu_device *adev = ring->adev; 7123 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7124 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7125 7126 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 7127 memset((void *)mqd, 0, sizeof(*mqd)); 7128 mutex_lock(&adev->srbm_mutex); 7129 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7130 gfx_v10_0_compute_mqd_init(ring); 7131 nv_grbm_select(adev, 0, 0, 0, 0); 7132 mutex_unlock(&adev->srbm_mutex); 7133 7134 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7135 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7136 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7137 /* reset MQD to a clean status */ 7138 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7139 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7140 7141 /* reset ring buffer */ 7142 ring->wptr = 0; 7143 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 7144 amdgpu_ring_clear_ring(ring); 7145 } else { 7146 amdgpu_ring_clear_ring(ring); 7147 } 7148 7149 return 0; 7150 } 7151 7152 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7153 { 7154 struct amdgpu_ring *ring; 7155 int r; 7156 7157 ring = &adev->gfx.kiq.ring; 7158 7159 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7160 if (unlikely(r != 0)) 7161 return r; 7162 7163 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7164 if (unlikely(r != 0)) 7165 return r; 7166 7167 gfx_v10_0_kiq_init_queue(ring); 7168 amdgpu_bo_kunmap(ring->mqd_obj); 7169 ring->mqd_ptr = NULL; 7170 amdgpu_bo_unreserve(ring->mqd_obj); 7171 ring->sched.ready = true; 7172 return 0; 7173 } 7174 7175 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7176 { 7177 struct amdgpu_ring *ring = NULL; 7178 int r = 0, i; 7179 7180 gfx_v10_0_cp_compute_enable(adev, true); 7181 7182 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7183 ring = &adev->gfx.compute_ring[i]; 7184 7185 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7186 if (unlikely(r != 0)) 7187 goto done; 7188 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7189 if (!r) { 7190 r = gfx_v10_0_kcq_init_queue(ring); 7191 amdgpu_bo_kunmap(ring->mqd_obj); 7192 ring->mqd_ptr = NULL; 7193 } 7194 amdgpu_bo_unreserve(ring->mqd_obj); 7195 if (r) 7196 goto done; 7197 } 7198 7199 r = amdgpu_gfx_enable_kcq(adev); 7200 done: 7201 return r; 7202 } 7203 7204 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7205 { 7206 int r, i; 7207 struct amdgpu_ring *ring; 7208 7209 if (!(adev->flags & AMD_IS_APU)) 7210 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7211 7212 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7213 /* legacy firmware loading */ 7214 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7215 if (r) 7216 return r; 7217 7218 r = gfx_v10_0_cp_compute_load_microcode(adev); 7219 if (r) 7220 return r; 7221 } 7222 7223 r = gfx_v10_0_kiq_resume(adev); 7224 if (r) 7225 return r; 7226 7227 r = gfx_v10_0_kcq_resume(adev); 7228 if (r) 7229 return r; 7230 7231 if (!amdgpu_async_gfx_ring) { 7232 r = gfx_v10_0_cp_gfx_resume(adev); 7233 if (r) 7234 return r; 7235 } else { 7236 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7237 if (r) 7238 return r; 7239 } 7240 7241 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7242 ring = &adev->gfx.gfx_ring[i]; 7243 r = amdgpu_ring_test_helper(ring); 7244 if (r) 7245 return r; 7246 } 7247 7248 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7249 ring = &adev->gfx.compute_ring[i]; 7250 r = amdgpu_ring_test_helper(ring); 7251 if (r) 7252 return r; 7253 } 7254 7255 return 0; 7256 } 7257 7258 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7259 { 7260 gfx_v10_0_cp_gfx_enable(adev, enable); 7261 gfx_v10_0_cp_compute_enable(adev, enable); 7262 } 7263 7264 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7265 { 7266 uint32_t data, pattern = 0xDEADBEEF; 7267 7268 /* check if mmVGT_ESGS_RING_SIZE_UMD 7269 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7270 switch (adev->ip_versions[GC_HWIP][0]) { 7271 case IP_VERSION(10, 3, 0): 7272 case IP_VERSION(10, 3, 2): 7273 case IP_VERSION(10, 3, 4): 7274 case IP_VERSION(10, 3, 5): 7275 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7276 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7277 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7278 7279 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7280 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7281 return true; 7282 } else { 7283 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7284 return false; 7285 } 7286 break; 7287 case IP_VERSION(10, 3, 1): 7288 case IP_VERSION(10, 3, 3): 7289 case IP_VERSION(10, 3, 6): 7290 case IP_VERSION(10, 3, 7): 7291 return true; 7292 default: 7293 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7294 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7295 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7296 7297 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7298 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7299 return true; 7300 } else { 7301 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7302 return false; 7303 } 7304 break; 7305 } 7306 } 7307 7308 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7309 { 7310 uint32_t data; 7311 7312 if (amdgpu_sriov_vf(adev)) 7313 return; 7314 7315 /* initialize cam_index to 0 7316 * index will auto-inc after each data writting */ 7317 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7318 7319 switch (adev->ip_versions[GC_HWIP][0]) { 7320 case IP_VERSION(10, 3, 0): 7321 case IP_VERSION(10, 3, 2): 7322 case IP_VERSION(10, 3, 1): 7323 case IP_VERSION(10, 3, 4): 7324 case IP_VERSION(10, 3, 5): 7325 case IP_VERSION(10, 3, 6): 7326 case IP_VERSION(10, 3, 3): 7327 case IP_VERSION(10, 3, 7): 7328 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7329 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7330 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7331 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7332 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7333 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7334 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7335 7336 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7337 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7338 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7339 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7340 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7341 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7342 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7343 7344 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7345 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7346 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7347 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7348 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7349 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7350 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7351 7352 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7353 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7354 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7355 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7356 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7357 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7358 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7359 7360 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7361 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7362 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7363 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7364 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7365 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7366 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7367 7368 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7369 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7370 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7371 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7372 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7373 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7374 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7375 7376 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7377 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7378 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7379 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7380 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7381 break; 7382 default: 7383 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7384 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7385 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7386 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7387 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7388 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7389 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7390 7391 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7392 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7393 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7394 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7395 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7396 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7397 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7398 7399 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7400 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7401 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7402 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7403 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7404 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7405 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7406 7407 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7408 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7409 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7410 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7411 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7412 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7413 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7414 7415 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7416 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7417 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7418 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7419 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7420 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7421 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7422 7423 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7424 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7425 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7426 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7427 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7428 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7429 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7430 7431 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7432 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7433 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7434 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7435 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7436 break; 7437 } 7438 7439 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7440 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7441 } 7442 7443 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7444 { 7445 uint32_t data; 7446 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7447 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7448 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7449 7450 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7451 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7452 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7453 } 7454 7455 static int gfx_v10_0_hw_init(void *handle) 7456 { 7457 int r; 7458 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7459 7460 if (!amdgpu_emu_mode) 7461 gfx_v10_0_init_golden_registers(adev); 7462 7463 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7464 /** 7465 * For gfx 10, rlc firmware loading relies on smu firmware is 7466 * loaded firstly, so in direct type, it has to load smc ucode 7467 * here before rlc. 7468 */ 7469 if (!(adev->flags & AMD_IS_APU)) { 7470 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7471 if (r) 7472 return r; 7473 } 7474 gfx_v10_0_disable_gpa_mode(adev); 7475 } 7476 7477 /* if GRBM CAM not remapped, set up the remapping */ 7478 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7479 gfx_v10_0_setup_grbm_cam_remapping(adev); 7480 7481 gfx_v10_0_constants_init(adev); 7482 7483 r = gfx_v10_0_rlc_resume(adev); 7484 if (r) 7485 return r; 7486 7487 /* 7488 * init golden registers and rlc resume may override some registers, 7489 * reconfig them here 7490 */ 7491 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7492 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7493 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7494 gfx_v10_0_tcp_harvest(adev); 7495 7496 r = gfx_v10_0_cp_resume(adev); 7497 if (r) 7498 return r; 7499 7500 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7501 gfx_v10_3_program_pbb_mode(adev); 7502 7503 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7504 gfx_v10_3_set_power_brake_sequence(adev); 7505 7506 return r; 7507 } 7508 7509 #ifndef BRING_UP_DEBUG 7510 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7511 { 7512 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7513 struct amdgpu_ring *kiq_ring = &kiq->ring; 7514 int i; 7515 7516 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7517 return -EINVAL; 7518 7519 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7520 adev->gfx.num_gfx_rings)) 7521 return -ENOMEM; 7522 7523 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7524 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7525 PREEMPT_QUEUES, 0, 0); 7526 7527 return amdgpu_ring_test_helper(kiq_ring); 7528 } 7529 #endif 7530 7531 static int gfx_v10_0_hw_fini(void *handle) 7532 { 7533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7534 int r; 7535 uint32_t tmp; 7536 7537 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7538 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7539 7540 if (!adev->no_hw_access) { 7541 #ifndef BRING_UP_DEBUG 7542 if (amdgpu_async_gfx_ring) { 7543 r = gfx_v10_0_kiq_disable_kgq(adev); 7544 if (r) 7545 DRM_ERROR("KGQ disable failed\n"); 7546 } 7547 #endif 7548 if (amdgpu_gfx_disable_kcq(adev)) 7549 DRM_ERROR("KCQ disable failed\n"); 7550 } 7551 7552 if (amdgpu_sriov_vf(adev)) { 7553 gfx_v10_0_cp_gfx_enable(adev, false); 7554 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7555 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 7556 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 7557 tmp &= 0xffffff00; 7558 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 7559 } else { 7560 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7561 tmp &= 0xffffff00; 7562 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7563 } 7564 7565 return 0; 7566 } 7567 gfx_v10_0_cp_enable(adev, false); 7568 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7569 7570 return 0; 7571 } 7572 7573 static int gfx_v10_0_suspend(void *handle) 7574 { 7575 return gfx_v10_0_hw_fini(handle); 7576 } 7577 7578 static int gfx_v10_0_resume(void *handle) 7579 { 7580 return gfx_v10_0_hw_init(handle); 7581 } 7582 7583 static bool gfx_v10_0_is_idle(void *handle) 7584 { 7585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7586 7587 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7588 GRBM_STATUS, GUI_ACTIVE)) 7589 return false; 7590 else 7591 return true; 7592 } 7593 7594 static int gfx_v10_0_wait_for_idle(void *handle) 7595 { 7596 unsigned i; 7597 u32 tmp; 7598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7599 7600 for (i = 0; i < adev->usec_timeout; i++) { 7601 /* read MC_STATUS */ 7602 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7603 GRBM_STATUS__GUI_ACTIVE_MASK; 7604 7605 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7606 return 0; 7607 udelay(1); 7608 } 7609 return -ETIMEDOUT; 7610 } 7611 7612 static int gfx_v10_0_soft_reset(void *handle) 7613 { 7614 u32 grbm_soft_reset = 0; 7615 u32 tmp; 7616 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7617 7618 /* GRBM_STATUS */ 7619 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7620 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7621 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7622 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7623 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7624 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7625 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7626 GRBM_SOFT_RESET, SOFT_RESET_CP, 7627 1); 7628 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7629 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7630 1); 7631 } 7632 7633 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7634 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7635 GRBM_SOFT_RESET, SOFT_RESET_CP, 7636 1); 7637 } 7638 7639 /* GRBM_STATUS2 */ 7640 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7641 switch (adev->ip_versions[GC_HWIP][0]) { 7642 case IP_VERSION(10, 3, 0): 7643 case IP_VERSION(10, 3, 2): 7644 case IP_VERSION(10, 3, 1): 7645 case IP_VERSION(10, 3, 4): 7646 case IP_VERSION(10, 3, 5): 7647 case IP_VERSION(10, 3, 6): 7648 case IP_VERSION(10, 3, 3): 7649 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7650 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7651 GRBM_SOFT_RESET, 7652 SOFT_RESET_RLC, 7653 1); 7654 break; 7655 default: 7656 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7657 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7658 GRBM_SOFT_RESET, 7659 SOFT_RESET_RLC, 7660 1); 7661 break; 7662 } 7663 7664 if (grbm_soft_reset) { 7665 /* stop the rlc */ 7666 gfx_v10_0_rlc_stop(adev); 7667 7668 /* Disable GFX parsing/prefetching */ 7669 gfx_v10_0_cp_gfx_enable(adev, false); 7670 7671 /* Disable MEC parsing/prefetching */ 7672 gfx_v10_0_cp_compute_enable(adev, false); 7673 7674 if (grbm_soft_reset) { 7675 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7676 tmp |= grbm_soft_reset; 7677 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7678 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7679 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7680 7681 udelay(50); 7682 7683 tmp &= ~grbm_soft_reset; 7684 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7685 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7686 } 7687 7688 /* Wait a little for things to settle down */ 7689 udelay(50); 7690 } 7691 return 0; 7692 } 7693 7694 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7695 { 7696 uint64_t clock, clock_lo, clock_hi, hi_check; 7697 7698 switch (adev->ip_versions[GC_HWIP][0]) { 7699 case IP_VERSION(10, 3, 1): 7700 case IP_VERSION(10, 3, 3): 7701 preempt_disable(); 7702 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7703 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7704 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7705 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7706 * roughly every 42 seconds. 7707 */ 7708 if (hi_check != clock_hi) { 7709 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7710 clock_hi = hi_check; 7711 } 7712 preempt_enable(); 7713 clock = clock_lo | (clock_hi << 32ULL); 7714 break; 7715 case IP_VERSION(10, 3, 6): 7716 preempt_disable(); 7717 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7718 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7719 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7720 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7721 * roughly every 42 seconds. 7722 */ 7723 if (hi_check != clock_hi) { 7724 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7725 clock_hi = hi_check; 7726 } 7727 preempt_enable(); 7728 clock = clock_lo | (clock_hi << 32ULL); 7729 break; 7730 default: 7731 preempt_disable(); 7732 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7733 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7734 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7735 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7736 * roughly every 42 seconds. 7737 */ 7738 if (hi_check != clock_hi) { 7739 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7740 clock_hi = hi_check; 7741 } 7742 preempt_enable(); 7743 clock = clock_lo | (clock_hi << 32ULL); 7744 break; 7745 } 7746 return clock; 7747 } 7748 7749 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7750 uint32_t vmid, 7751 uint32_t gds_base, uint32_t gds_size, 7752 uint32_t gws_base, uint32_t gws_size, 7753 uint32_t oa_base, uint32_t oa_size) 7754 { 7755 struct amdgpu_device *adev = ring->adev; 7756 7757 /* GDS Base */ 7758 gfx_v10_0_write_data_to_reg(ring, 0, false, 7759 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7760 gds_base); 7761 7762 /* GDS Size */ 7763 gfx_v10_0_write_data_to_reg(ring, 0, false, 7764 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7765 gds_size); 7766 7767 /* GWS */ 7768 gfx_v10_0_write_data_to_reg(ring, 0, false, 7769 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7770 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7771 7772 /* OA */ 7773 gfx_v10_0_write_data_to_reg(ring, 0, false, 7774 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7775 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7776 } 7777 7778 static int gfx_v10_0_early_init(void *handle) 7779 { 7780 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7781 7782 switch (adev->ip_versions[GC_HWIP][0]) { 7783 case IP_VERSION(10, 1, 10): 7784 case IP_VERSION(10, 1, 1): 7785 case IP_VERSION(10, 1, 2): 7786 case IP_VERSION(10, 1, 3): 7787 case IP_VERSION(10, 1, 4): 7788 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7789 break; 7790 case IP_VERSION(10, 3, 0): 7791 case IP_VERSION(10, 3, 2): 7792 case IP_VERSION(10, 3, 1): 7793 case IP_VERSION(10, 3, 4): 7794 case IP_VERSION(10, 3, 5): 7795 case IP_VERSION(10, 3, 6): 7796 case IP_VERSION(10, 3, 3): 7797 case IP_VERSION(10, 3, 7): 7798 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7799 break; 7800 default: 7801 break; 7802 } 7803 7804 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7805 AMDGPU_MAX_COMPUTE_RINGS); 7806 7807 gfx_v10_0_set_kiq_pm4_funcs(adev); 7808 gfx_v10_0_set_ring_funcs(adev); 7809 gfx_v10_0_set_irq_funcs(adev); 7810 gfx_v10_0_set_gds_init(adev); 7811 gfx_v10_0_set_rlc_funcs(adev); 7812 7813 /* init rlcg reg access ctrl */ 7814 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7815 7816 return 0; 7817 } 7818 7819 static int gfx_v10_0_late_init(void *handle) 7820 { 7821 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7822 int r; 7823 7824 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7825 if (r) 7826 return r; 7827 7828 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7829 if (r) 7830 return r; 7831 7832 return 0; 7833 } 7834 7835 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7836 { 7837 uint32_t rlc_cntl; 7838 7839 /* if RLC is not enabled, do nothing */ 7840 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7841 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7842 } 7843 7844 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7845 { 7846 uint32_t data; 7847 unsigned i; 7848 7849 data = RLC_SAFE_MODE__CMD_MASK; 7850 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7851 7852 switch (adev->ip_versions[GC_HWIP][0]) { 7853 case IP_VERSION(10, 3, 0): 7854 case IP_VERSION(10, 3, 2): 7855 case IP_VERSION(10, 3, 1): 7856 case IP_VERSION(10, 3, 4): 7857 case IP_VERSION(10, 3, 5): 7858 case IP_VERSION(10, 3, 6): 7859 case IP_VERSION(10, 3, 3): 7860 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7861 7862 /* wait for RLC_SAFE_MODE */ 7863 for (i = 0; i < adev->usec_timeout; i++) { 7864 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7865 RLC_SAFE_MODE, CMD)) 7866 break; 7867 udelay(1); 7868 } 7869 break; 7870 default: 7871 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7872 7873 /* wait for RLC_SAFE_MODE */ 7874 for (i = 0; i < adev->usec_timeout; i++) { 7875 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7876 RLC_SAFE_MODE, CMD)) 7877 break; 7878 udelay(1); 7879 } 7880 break; 7881 } 7882 } 7883 7884 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7885 { 7886 uint32_t data; 7887 7888 data = RLC_SAFE_MODE__CMD_MASK; 7889 switch (adev->ip_versions[GC_HWIP][0]) { 7890 case IP_VERSION(10, 3, 0): 7891 case IP_VERSION(10, 3, 2): 7892 case IP_VERSION(10, 3, 1): 7893 case IP_VERSION(10, 3, 4): 7894 case IP_VERSION(10, 3, 5): 7895 case IP_VERSION(10, 3, 6): 7896 case IP_VERSION(10, 3, 3): 7897 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7898 break; 7899 default: 7900 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7901 break; 7902 } 7903 } 7904 7905 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7906 bool enable) 7907 { 7908 uint32_t data, def; 7909 7910 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7911 return; 7912 7913 /* It is disabled by HW by default */ 7914 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7915 /* 0 - Disable some blocks' MGCG */ 7916 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7917 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7918 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7919 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7920 7921 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7922 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7923 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7924 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7925 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7926 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7927 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7928 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7929 7930 if (def != data) 7931 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7932 7933 /* MGLS is a global flag to control all MGLS in GFX */ 7934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7935 /* 2 - RLC memory Light sleep */ 7936 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7937 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7938 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7939 if (def != data) 7940 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7941 } 7942 /* 3 - CP memory Light sleep */ 7943 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7944 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7945 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7946 if (def != data) 7947 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7948 } 7949 } 7950 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7951 /* 1 - MGCG_OVERRIDE */ 7952 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7953 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7954 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7955 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7956 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7957 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7958 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7959 if (def != data) 7960 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7961 7962 /* 2 - disable MGLS in CP */ 7963 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7964 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7965 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7966 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7967 } 7968 7969 /* 3 - disable MGLS in RLC */ 7970 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7971 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7972 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7973 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7974 } 7975 7976 } 7977 } 7978 7979 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7980 bool enable) 7981 { 7982 uint32_t data, def; 7983 7984 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7985 return; 7986 7987 /* Enable 3D CGCG/CGLS */ 7988 if (enable) { 7989 /* write cmd to clear cgcg/cgls ov */ 7990 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7991 7992 /* unset CGCG override */ 7993 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7994 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7995 7996 /* update CGCG and CGLS override bits */ 7997 if (def != data) 7998 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7999 8000 /* enable 3Dcgcg FSM(0x0000363f) */ 8001 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8002 data = 0; 8003 8004 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8005 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8006 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8007 8008 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8009 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8010 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8011 8012 if (def != data) 8013 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8014 8015 /* set IDLE_POLL_COUNT(0x00900100) */ 8016 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8017 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8018 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8019 if (def != data) 8020 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8021 } else { 8022 /* Disable CGCG/CGLS */ 8023 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8024 8025 /* disable cgcg, cgls should be disabled */ 8026 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8027 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8028 8029 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8030 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8031 8032 /* disable cgcg and cgls in FSM */ 8033 if (def != data) 8034 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8035 } 8036 } 8037 8038 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8039 bool enable) 8040 { 8041 uint32_t def, data; 8042 8043 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8044 return; 8045 8046 if (enable) { 8047 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8048 8049 /* unset CGCG override */ 8050 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8051 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8052 8053 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8054 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8055 8056 /* update CGCG and CGLS override bits */ 8057 if (def != data) 8058 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8059 8060 /* enable cgcg FSM(0x0000363F) */ 8061 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8062 data = 0; 8063 8064 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8065 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8066 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8067 8068 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8069 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8070 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8071 8072 if (def != data) 8073 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8074 8075 /* set IDLE_POLL_COUNT(0x00900100) */ 8076 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8077 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8078 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8079 if (def != data) 8080 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8081 } else { 8082 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8083 8084 /* reset CGCG/CGLS bits */ 8085 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8086 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8087 8088 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8089 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8090 8091 /* disable cgcg and cgls in FSM */ 8092 if (def != data) 8093 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8094 } 8095 } 8096 8097 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8098 bool enable) 8099 { 8100 uint32_t def, data; 8101 8102 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8103 return; 8104 8105 if (enable) { 8106 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8107 /* unset FGCG override */ 8108 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8109 /* update FGCG override bits */ 8110 if (def != data) 8111 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8112 8113 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8114 /* unset RLC SRAM CLK GATER override */ 8115 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8116 /* update RLC SRAM CLK GATER override bits */ 8117 if (def != data) 8118 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8119 } else { 8120 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8121 /* reset FGCG bits */ 8122 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8123 /* disable FGCG*/ 8124 if (def != data) 8125 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8126 8127 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8128 /* reset RLC SRAM CLK GATER bits */ 8129 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8130 /* disable RLC SRAM CLK*/ 8131 if (def != data) 8132 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8133 } 8134 } 8135 8136 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8137 { 8138 uint32_t reg_data = 0; 8139 uint32_t reg_idx = 0; 8140 uint32_t i; 8141 8142 const uint32_t tcp_ctrl_regs[] = { 8143 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8144 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8145 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8146 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8147 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8148 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8149 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8150 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8151 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8152 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8153 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8154 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8155 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8156 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8157 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8158 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8159 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8160 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8161 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8162 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8163 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8164 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8165 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8166 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8167 }; 8168 8169 const uint32_t tcp_ctrl_regs_nv12[] = { 8170 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8171 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8172 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8173 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8174 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8175 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8176 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8177 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8178 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8179 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8180 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8181 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8182 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8183 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8184 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8185 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8186 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8187 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8188 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8189 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8190 }; 8191 8192 const uint32_t sm_ctlr_regs[] = { 8193 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8194 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8195 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8196 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8197 }; 8198 8199 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 8200 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8201 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8202 tcp_ctrl_regs_nv12[i]; 8203 reg_data = RREG32(reg_idx); 8204 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8205 WREG32(reg_idx, reg_data); 8206 } 8207 } else { 8208 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8209 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8210 tcp_ctrl_regs[i]; 8211 reg_data = RREG32(reg_idx); 8212 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8213 WREG32(reg_idx, reg_data); 8214 } 8215 } 8216 8217 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8218 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8219 sm_ctlr_regs[i]; 8220 reg_data = RREG32(reg_idx); 8221 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8222 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8223 WREG32(reg_idx, reg_data); 8224 } 8225 } 8226 8227 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8228 bool enable) 8229 { 8230 amdgpu_gfx_rlc_enter_safe_mode(adev); 8231 8232 if (enable) { 8233 /* enable FGCG firstly*/ 8234 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8235 /* CGCG/CGLS should be enabled after MGCG/MGLS 8236 * === MGCG + MGLS === 8237 */ 8238 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8239 /* === CGCG /CGLS for GFX 3D Only === */ 8240 gfx_v10_0_update_3d_clock_gating(adev, enable); 8241 /* === CGCG + CGLS === */ 8242 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8243 8244 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 8245 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 8246 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 8247 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8248 } else { 8249 /* CGCG/CGLS should be disabled before MGCG/MGLS 8250 * === CGCG + CGLS === 8251 */ 8252 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8253 /* === CGCG /CGLS for GFX 3D Only === */ 8254 gfx_v10_0_update_3d_clock_gating(adev, enable); 8255 /* === MGCG + MGLS === */ 8256 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8257 /* disable fgcg at last*/ 8258 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8259 } 8260 8261 if (adev->cg_flags & 8262 (AMD_CG_SUPPORT_GFX_MGCG | 8263 AMD_CG_SUPPORT_GFX_CGLS | 8264 AMD_CG_SUPPORT_GFX_CGCG | 8265 AMD_CG_SUPPORT_GFX_3D_CGCG | 8266 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8267 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8268 8269 amdgpu_gfx_rlc_exit_safe_mode(adev); 8270 8271 return 0; 8272 } 8273 8274 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 8275 { 8276 u32 reg, data; 8277 8278 amdgpu_gfx_off_ctrl(adev, false); 8279 8280 /* not for *_SOC15 */ 8281 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8282 if (amdgpu_sriov_is_pp_one_vf(adev)) 8283 data = RREG32_NO_KIQ(reg); 8284 else 8285 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 8286 8287 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8288 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8289 8290 if (amdgpu_sriov_is_pp_one_vf(adev)) 8291 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8292 else 8293 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8294 8295 amdgpu_gfx_off_ctrl(adev, true); 8296 } 8297 8298 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8299 uint32_t offset, 8300 struct soc15_reg_rlcg *entries, int arr_size) 8301 { 8302 int i; 8303 uint32_t reg; 8304 8305 if (!entries) 8306 return false; 8307 8308 for (i = 0; i < arr_size; i++) { 8309 const struct soc15_reg_rlcg *entry; 8310 8311 entry = &entries[i]; 8312 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8313 if (offset == reg) 8314 return true; 8315 } 8316 8317 return false; 8318 } 8319 8320 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8321 { 8322 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8323 } 8324 8325 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8326 { 8327 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8328 8329 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8330 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8331 else 8332 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8333 8334 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8335 8336 /* 8337 * CGPG enablement required and the register to program the hysteresis value 8338 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8339 * in refclk count. Note that RLC FW is modified to take 16 bits from 8340 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8341 * 8342 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8343 * of CGPG enablement starting point. 8344 * Power/performance team will optimize it and might give a new value later. 8345 */ 8346 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8347 switch (adev->ip_versions[GC_HWIP][0]) { 8348 case IP_VERSION(10, 3, 1): 8349 case IP_VERSION(10, 3, 3): 8350 case IP_VERSION(10, 3, 6): 8351 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8352 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8353 break; 8354 default: 8355 break; 8356 } 8357 } 8358 } 8359 8360 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8361 { 8362 amdgpu_gfx_rlc_enter_safe_mode(adev); 8363 8364 gfx_v10_cntl_power_gating(adev, enable); 8365 8366 amdgpu_gfx_rlc_exit_safe_mode(adev); 8367 } 8368 8369 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8370 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8371 .set_safe_mode = gfx_v10_0_set_safe_mode, 8372 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8373 .init = gfx_v10_0_rlc_init, 8374 .get_csb_size = gfx_v10_0_get_csb_size, 8375 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8376 .resume = gfx_v10_0_rlc_resume, 8377 .stop = gfx_v10_0_rlc_stop, 8378 .reset = gfx_v10_0_rlc_reset, 8379 .start = gfx_v10_0_rlc_start, 8380 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8381 }; 8382 8383 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8384 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8385 .set_safe_mode = gfx_v10_0_set_safe_mode, 8386 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8387 .init = gfx_v10_0_rlc_init, 8388 .get_csb_size = gfx_v10_0_get_csb_size, 8389 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8390 .resume = gfx_v10_0_rlc_resume, 8391 .stop = gfx_v10_0_rlc_stop, 8392 .reset = gfx_v10_0_rlc_reset, 8393 .start = gfx_v10_0_rlc_start, 8394 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8395 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8396 }; 8397 8398 static int gfx_v10_0_set_powergating_state(void *handle, 8399 enum amd_powergating_state state) 8400 { 8401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8402 bool enable = (state == AMD_PG_STATE_GATE); 8403 8404 if (amdgpu_sriov_vf(adev)) 8405 return 0; 8406 8407 switch (adev->ip_versions[GC_HWIP][0]) { 8408 case IP_VERSION(10, 1, 10): 8409 case IP_VERSION(10, 1, 1): 8410 case IP_VERSION(10, 1, 2): 8411 case IP_VERSION(10, 3, 0): 8412 case IP_VERSION(10, 3, 2): 8413 case IP_VERSION(10, 3, 4): 8414 case IP_VERSION(10, 3, 5): 8415 amdgpu_gfx_off_ctrl(adev, enable); 8416 break; 8417 case IP_VERSION(10, 3, 1): 8418 case IP_VERSION(10, 3, 3): 8419 case IP_VERSION(10, 3, 6): 8420 gfx_v10_cntl_pg(adev, enable); 8421 amdgpu_gfx_off_ctrl(adev, enable); 8422 break; 8423 default: 8424 break; 8425 } 8426 return 0; 8427 } 8428 8429 static int gfx_v10_0_set_clockgating_state(void *handle, 8430 enum amd_clockgating_state state) 8431 { 8432 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8433 8434 if (amdgpu_sriov_vf(adev)) 8435 return 0; 8436 8437 switch (adev->ip_versions[GC_HWIP][0]) { 8438 case IP_VERSION(10, 1, 10): 8439 case IP_VERSION(10, 1, 1): 8440 case IP_VERSION(10, 1, 2): 8441 case IP_VERSION(10, 3, 0): 8442 case IP_VERSION(10, 3, 2): 8443 case IP_VERSION(10, 3, 1): 8444 case IP_VERSION(10, 3, 4): 8445 case IP_VERSION(10, 3, 5): 8446 case IP_VERSION(10, 3, 6): 8447 case IP_VERSION(10, 3, 3): 8448 gfx_v10_0_update_gfx_clock_gating(adev, 8449 state == AMD_CG_STATE_GATE); 8450 break; 8451 default: 8452 break; 8453 } 8454 return 0; 8455 } 8456 8457 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 8458 { 8459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8460 int data; 8461 8462 /* AMD_CG_SUPPORT_GFX_FGCG */ 8463 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8464 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8465 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8466 8467 /* AMD_CG_SUPPORT_GFX_MGCG */ 8468 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8469 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8470 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8471 8472 /* AMD_CG_SUPPORT_GFX_CGCG */ 8473 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8474 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8475 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8476 8477 /* AMD_CG_SUPPORT_GFX_CGLS */ 8478 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8479 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8480 8481 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8482 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8483 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8484 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8485 8486 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8487 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8488 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8489 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8490 8491 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8492 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8493 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8494 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8495 8496 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8497 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8498 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8499 } 8500 8501 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8502 { 8503 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 8504 } 8505 8506 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8507 { 8508 struct amdgpu_device *adev = ring->adev; 8509 u64 wptr; 8510 8511 /* XXX check if swapping is necessary on BE */ 8512 if (ring->use_doorbell) { 8513 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8514 } else { 8515 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8516 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8517 } 8518 8519 return wptr; 8520 } 8521 8522 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8523 { 8524 struct amdgpu_device *adev = ring->adev; 8525 8526 if (ring->use_doorbell) { 8527 /* XXX check if swapping is necessary on BE */ 8528 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8529 WDOORBELL64(ring->doorbell_index, ring->wptr); 8530 } else { 8531 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8532 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8533 } 8534 } 8535 8536 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8537 { 8538 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8539 } 8540 8541 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8542 { 8543 u64 wptr; 8544 8545 /* XXX check if swapping is necessary on BE */ 8546 if (ring->use_doorbell) 8547 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8548 else 8549 BUG(); 8550 return wptr; 8551 } 8552 8553 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8554 { 8555 struct amdgpu_device *adev = ring->adev; 8556 8557 /* XXX check if swapping is necessary on BE */ 8558 if (ring->use_doorbell) { 8559 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8560 WDOORBELL64(ring->doorbell_index, ring->wptr); 8561 } else { 8562 BUG(); /* only DOORBELL method supported on gfx10 now */ 8563 } 8564 } 8565 8566 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8567 { 8568 struct amdgpu_device *adev = ring->adev; 8569 u32 ref_and_mask, reg_mem_engine; 8570 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8571 8572 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8573 switch (ring->me) { 8574 case 1: 8575 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8576 break; 8577 case 2: 8578 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8579 break; 8580 default: 8581 return; 8582 } 8583 reg_mem_engine = 0; 8584 } else { 8585 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8586 reg_mem_engine = 1; /* pfp */ 8587 } 8588 8589 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8590 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8591 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8592 ref_and_mask, ref_and_mask, 0x20); 8593 } 8594 8595 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8596 struct amdgpu_job *job, 8597 struct amdgpu_ib *ib, 8598 uint32_t flags) 8599 { 8600 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8601 u32 header, control = 0; 8602 8603 if (ib->flags & AMDGPU_IB_FLAG_CE) 8604 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8605 else 8606 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8607 8608 control |= ib->length_dw | (vmid << 24); 8609 8610 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8611 control |= INDIRECT_BUFFER_PRE_ENB(1); 8612 8613 if (flags & AMDGPU_IB_PREEMPTED) 8614 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8615 8616 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8617 gfx_v10_0_ring_emit_de_meta(ring, 8618 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8619 } 8620 8621 amdgpu_ring_write(ring, header); 8622 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8623 amdgpu_ring_write(ring, 8624 #ifdef __BIG_ENDIAN 8625 (2 << 0) | 8626 #endif 8627 lower_32_bits(ib->gpu_addr)); 8628 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8629 amdgpu_ring_write(ring, control); 8630 } 8631 8632 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8633 struct amdgpu_job *job, 8634 struct amdgpu_ib *ib, 8635 uint32_t flags) 8636 { 8637 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8638 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8639 8640 /* Currently, there is a high possibility to get wave ID mismatch 8641 * between ME and GDS, leading to a hw deadlock, because ME generates 8642 * different wave IDs than the GDS expects. This situation happens 8643 * randomly when at least 5 compute pipes use GDS ordered append. 8644 * The wave IDs generated by ME are also wrong after suspend/resume. 8645 * Those are probably bugs somewhere else in the kernel driver. 8646 * 8647 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8648 * GDS to 0 for this ring (me/pipe). 8649 */ 8650 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8651 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8652 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8653 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8654 } 8655 8656 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8657 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8658 amdgpu_ring_write(ring, 8659 #ifdef __BIG_ENDIAN 8660 (2 << 0) | 8661 #endif 8662 lower_32_bits(ib->gpu_addr)); 8663 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8664 amdgpu_ring_write(ring, control); 8665 } 8666 8667 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8668 u64 seq, unsigned flags) 8669 { 8670 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8671 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8672 8673 /* RELEASE_MEM - flush caches, send int */ 8674 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8675 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8676 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8677 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8678 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8679 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8680 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8681 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8682 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8683 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8684 8685 /* 8686 * the address should be Qword aligned if 64bit write, Dword 8687 * aligned if only send 32bit data low (discard data high) 8688 */ 8689 if (write64bit) 8690 BUG_ON(addr & 0x7); 8691 else 8692 BUG_ON(addr & 0x3); 8693 amdgpu_ring_write(ring, lower_32_bits(addr)); 8694 amdgpu_ring_write(ring, upper_32_bits(addr)); 8695 amdgpu_ring_write(ring, lower_32_bits(seq)); 8696 amdgpu_ring_write(ring, upper_32_bits(seq)); 8697 amdgpu_ring_write(ring, 0); 8698 } 8699 8700 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8701 { 8702 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8703 uint32_t seq = ring->fence_drv.sync_seq; 8704 uint64_t addr = ring->fence_drv.gpu_addr; 8705 8706 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8707 upper_32_bits(addr), seq, 0xffffffff, 4); 8708 } 8709 8710 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8711 unsigned vmid, uint64_t pd_addr) 8712 { 8713 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8714 8715 /* compute doesn't have PFP */ 8716 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8717 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8718 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8719 amdgpu_ring_write(ring, 0x0); 8720 } 8721 } 8722 8723 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8724 u64 seq, unsigned int flags) 8725 { 8726 struct amdgpu_device *adev = ring->adev; 8727 8728 /* we only allocate 32bit for each seq wb address */ 8729 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8730 8731 /* write fence seq to the "addr" */ 8732 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8733 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8734 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8735 amdgpu_ring_write(ring, lower_32_bits(addr)); 8736 amdgpu_ring_write(ring, upper_32_bits(addr)); 8737 amdgpu_ring_write(ring, lower_32_bits(seq)); 8738 8739 if (flags & AMDGPU_FENCE_FLAG_INT) { 8740 /* set register to trigger INT */ 8741 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8742 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8743 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8744 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8745 amdgpu_ring_write(ring, 0); 8746 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8747 } 8748 } 8749 8750 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8751 { 8752 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8753 amdgpu_ring_write(ring, 0); 8754 } 8755 8756 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8757 uint32_t flags) 8758 { 8759 uint32_t dw2 = 0; 8760 8761 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8762 gfx_v10_0_ring_emit_ce_meta(ring, 8763 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8764 8765 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8766 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8767 /* set load_global_config & load_global_uconfig */ 8768 dw2 |= 0x8001; 8769 /* set load_cs_sh_regs */ 8770 dw2 |= 0x01000000; 8771 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8772 dw2 |= 0x10002; 8773 8774 /* set load_ce_ram if preamble presented */ 8775 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8776 dw2 |= 0x10000000; 8777 } else { 8778 /* still load_ce_ram if this is the first time preamble presented 8779 * although there is no context switch happens. 8780 */ 8781 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8782 dw2 |= 0x10000000; 8783 } 8784 8785 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8786 amdgpu_ring_write(ring, dw2); 8787 amdgpu_ring_write(ring, 0); 8788 } 8789 8790 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8791 { 8792 unsigned ret; 8793 8794 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8795 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8796 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8797 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8798 ret = ring->wptr & ring->buf_mask; 8799 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8800 8801 return ret; 8802 } 8803 8804 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8805 { 8806 unsigned cur; 8807 BUG_ON(offset > ring->buf_mask); 8808 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8809 8810 cur = (ring->wptr - 1) & ring->buf_mask; 8811 if (likely(cur > offset)) 8812 ring->ring[offset] = cur - offset; 8813 else 8814 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8815 } 8816 8817 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8818 { 8819 int i, r = 0; 8820 struct amdgpu_device *adev = ring->adev; 8821 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8822 struct amdgpu_ring *kiq_ring = &kiq->ring; 8823 unsigned long flags; 8824 8825 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8826 return -EINVAL; 8827 8828 spin_lock_irqsave(&kiq->ring_lock, flags); 8829 8830 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8831 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8832 return -ENOMEM; 8833 } 8834 8835 /* assert preemption condition */ 8836 amdgpu_ring_set_preempt_cond_exec(ring, false); 8837 8838 /* assert IB preemption, emit the trailing fence */ 8839 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8840 ring->trail_fence_gpu_addr, 8841 ++ring->trail_seq); 8842 amdgpu_ring_commit(kiq_ring); 8843 8844 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8845 8846 /* poll the trailing fence */ 8847 for (i = 0; i < adev->usec_timeout; i++) { 8848 if (ring->trail_seq == 8849 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8850 break; 8851 udelay(1); 8852 } 8853 8854 if (i >= adev->usec_timeout) { 8855 r = -EINVAL; 8856 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8857 } 8858 8859 /* deassert preemption condition */ 8860 amdgpu_ring_set_preempt_cond_exec(ring, true); 8861 return r; 8862 } 8863 8864 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8865 { 8866 struct amdgpu_device *adev = ring->adev; 8867 struct v10_ce_ib_state ce_payload = {0}; 8868 uint64_t csa_addr; 8869 int cnt; 8870 8871 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8872 csa_addr = amdgpu_csa_vaddr(ring->adev); 8873 8874 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8875 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8876 WRITE_DATA_DST_SEL(8) | 8877 WR_CONFIRM) | 8878 WRITE_DATA_CACHE_POLICY(0)); 8879 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8880 offsetof(struct v10_gfx_meta_data, ce_payload))); 8881 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8882 offsetof(struct v10_gfx_meta_data, ce_payload))); 8883 8884 if (resume) 8885 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8886 offsetof(struct v10_gfx_meta_data, 8887 ce_payload), 8888 sizeof(ce_payload) >> 2); 8889 else 8890 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8891 sizeof(ce_payload) >> 2); 8892 } 8893 8894 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8895 { 8896 struct amdgpu_device *adev = ring->adev; 8897 struct v10_de_ib_state de_payload = {0}; 8898 uint64_t csa_addr, gds_addr; 8899 int cnt; 8900 8901 csa_addr = amdgpu_csa_vaddr(ring->adev); 8902 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8903 PAGE_SIZE); 8904 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8905 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8906 8907 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8908 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8909 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8910 WRITE_DATA_DST_SEL(8) | 8911 WR_CONFIRM) | 8912 WRITE_DATA_CACHE_POLICY(0)); 8913 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8914 offsetof(struct v10_gfx_meta_data, de_payload))); 8915 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8916 offsetof(struct v10_gfx_meta_data, de_payload))); 8917 8918 if (resume) 8919 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8920 offsetof(struct v10_gfx_meta_data, 8921 de_payload), 8922 sizeof(de_payload) >> 2); 8923 else 8924 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8925 sizeof(de_payload) >> 2); 8926 } 8927 8928 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8929 bool secure) 8930 { 8931 uint32_t v = secure ? FRAME_TMZ : 0; 8932 8933 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8934 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8935 } 8936 8937 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8938 uint32_t reg_val_offs) 8939 { 8940 struct amdgpu_device *adev = ring->adev; 8941 8942 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8943 amdgpu_ring_write(ring, 0 | /* src: register*/ 8944 (5 << 8) | /* dst: memory */ 8945 (1 << 20)); /* write confirm */ 8946 amdgpu_ring_write(ring, reg); 8947 amdgpu_ring_write(ring, 0); 8948 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8949 reg_val_offs * 4)); 8950 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8951 reg_val_offs * 4)); 8952 } 8953 8954 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8955 uint32_t val) 8956 { 8957 uint32_t cmd = 0; 8958 8959 switch (ring->funcs->type) { 8960 case AMDGPU_RING_TYPE_GFX: 8961 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8962 break; 8963 case AMDGPU_RING_TYPE_KIQ: 8964 cmd = (1 << 16); /* no inc addr */ 8965 break; 8966 default: 8967 cmd = WR_CONFIRM; 8968 break; 8969 } 8970 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8971 amdgpu_ring_write(ring, cmd); 8972 amdgpu_ring_write(ring, reg); 8973 amdgpu_ring_write(ring, 0); 8974 amdgpu_ring_write(ring, val); 8975 } 8976 8977 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8978 uint32_t val, uint32_t mask) 8979 { 8980 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8981 } 8982 8983 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8984 uint32_t reg0, uint32_t reg1, 8985 uint32_t ref, uint32_t mask) 8986 { 8987 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8988 struct amdgpu_device *adev = ring->adev; 8989 bool fw_version_ok = false; 8990 8991 fw_version_ok = adev->gfx.cp_fw_write_wait; 8992 8993 if (fw_version_ok) 8994 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8995 ref, mask, 0x20); 8996 else 8997 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8998 ref, mask); 8999 } 9000 9001 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 9002 unsigned vmid) 9003 { 9004 struct amdgpu_device *adev = ring->adev; 9005 uint32_t value = 0; 9006 9007 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 9008 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 9009 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 9010 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 9011 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 9012 } 9013 9014 static void 9015 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9016 uint32_t me, uint32_t pipe, 9017 enum amdgpu_interrupt_state state) 9018 { 9019 uint32_t cp_int_cntl, cp_int_cntl_reg; 9020 9021 if (!me) { 9022 switch (pipe) { 9023 case 0: 9024 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9025 break; 9026 case 1: 9027 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9028 break; 9029 default: 9030 DRM_DEBUG("invalid pipe %d\n", pipe); 9031 return; 9032 } 9033 } else { 9034 DRM_DEBUG("invalid me %d\n", me); 9035 return; 9036 } 9037 9038 switch (state) { 9039 case AMDGPU_IRQ_STATE_DISABLE: 9040 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9041 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9042 TIME_STAMP_INT_ENABLE, 0); 9043 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9044 break; 9045 case AMDGPU_IRQ_STATE_ENABLE: 9046 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9047 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9048 TIME_STAMP_INT_ENABLE, 1); 9049 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9050 break; 9051 default: 9052 break; 9053 } 9054 } 9055 9056 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9057 int me, int pipe, 9058 enum amdgpu_interrupt_state state) 9059 { 9060 u32 mec_int_cntl, mec_int_cntl_reg; 9061 9062 /* 9063 * amdgpu controls only the first MEC. That's why this function only 9064 * handles the setting of interrupts for this specific MEC. All other 9065 * pipes' interrupts are set by amdkfd. 9066 */ 9067 9068 if (me == 1) { 9069 switch (pipe) { 9070 case 0: 9071 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9072 break; 9073 case 1: 9074 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9075 break; 9076 case 2: 9077 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9078 break; 9079 case 3: 9080 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9081 break; 9082 default: 9083 DRM_DEBUG("invalid pipe %d\n", pipe); 9084 return; 9085 } 9086 } else { 9087 DRM_DEBUG("invalid me %d\n", me); 9088 return; 9089 } 9090 9091 switch (state) { 9092 case AMDGPU_IRQ_STATE_DISABLE: 9093 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9094 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9095 TIME_STAMP_INT_ENABLE, 0); 9096 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9097 break; 9098 case AMDGPU_IRQ_STATE_ENABLE: 9099 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9100 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9101 TIME_STAMP_INT_ENABLE, 1); 9102 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9103 break; 9104 default: 9105 break; 9106 } 9107 } 9108 9109 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9110 struct amdgpu_irq_src *src, 9111 unsigned type, 9112 enum amdgpu_interrupt_state state) 9113 { 9114 switch (type) { 9115 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9116 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9117 break; 9118 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9119 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9120 break; 9121 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9122 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9123 break; 9124 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9125 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9126 break; 9127 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9128 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9129 break; 9130 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9131 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9132 break; 9133 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9134 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9135 break; 9136 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9137 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9138 break; 9139 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9140 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9141 break; 9142 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9143 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9144 break; 9145 default: 9146 break; 9147 } 9148 return 0; 9149 } 9150 9151 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9152 struct amdgpu_irq_src *source, 9153 struct amdgpu_iv_entry *entry) 9154 { 9155 int i; 9156 u8 me_id, pipe_id, queue_id; 9157 struct amdgpu_ring *ring; 9158 9159 DRM_DEBUG("IH: CP EOP\n"); 9160 me_id = (entry->ring_id & 0x0c) >> 2; 9161 pipe_id = (entry->ring_id & 0x03) >> 0; 9162 queue_id = (entry->ring_id & 0x70) >> 4; 9163 9164 switch (me_id) { 9165 case 0: 9166 if (pipe_id == 0) 9167 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9168 else 9169 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9170 break; 9171 case 1: 9172 case 2: 9173 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9174 ring = &adev->gfx.compute_ring[i]; 9175 /* Per-queue interrupt is supported for MEC starting from VI. 9176 * The interrupt can only be enabled/disabled per pipe instead of per queue. 9177 */ 9178 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 9179 amdgpu_fence_process(ring); 9180 } 9181 break; 9182 } 9183 return 0; 9184 } 9185 9186 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9187 struct amdgpu_irq_src *source, 9188 unsigned type, 9189 enum amdgpu_interrupt_state state) 9190 { 9191 switch (state) { 9192 case AMDGPU_IRQ_STATE_DISABLE: 9193 case AMDGPU_IRQ_STATE_ENABLE: 9194 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9195 PRIV_REG_INT_ENABLE, 9196 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9197 break; 9198 default: 9199 break; 9200 } 9201 9202 return 0; 9203 } 9204 9205 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9206 struct amdgpu_irq_src *source, 9207 unsigned type, 9208 enum amdgpu_interrupt_state state) 9209 { 9210 switch (state) { 9211 case AMDGPU_IRQ_STATE_DISABLE: 9212 case AMDGPU_IRQ_STATE_ENABLE: 9213 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9214 PRIV_INSTR_INT_ENABLE, 9215 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9216 break; 9217 default: 9218 break; 9219 } 9220 9221 return 0; 9222 } 9223 9224 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9225 struct amdgpu_iv_entry *entry) 9226 { 9227 u8 me_id, pipe_id, queue_id; 9228 struct amdgpu_ring *ring; 9229 int i; 9230 9231 me_id = (entry->ring_id & 0x0c) >> 2; 9232 pipe_id = (entry->ring_id & 0x03) >> 0; 9233 queue_id = (entry->ring_id & 0x70) >> 4; 9234 9235 switch (me_id) { 9236 case 0: 9237 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9238 ring = &adev->gfx.gfx_ring[i]; 9239 /* we only enabled 1 gfx queue per pipe for now */ 9240 if (ring->me == me_id && ring->pipe == pipe_id) 9241 drm_sched_fault(&ring->sched); 9242 } 9243 break; 9244 case 1: 9245 case 2: 9246 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9247 ring = &adev->gfx.compute_ring[i]; 9248 if (ring->me == me_id && ring->pipe == pipe_id && 9249 ring->queue == queue_id) 9250 drm_sched_fault(&ring->sched); 9251 } 9252 break; 9253 default: 9254 BUG(); 9255 } 9256 } 9257 9258 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9259 struct amdgpu_irq_src *source, 9260 struct amdgpu_iv_entry *entry) 9261 { 9262 DRM_ERROR("Illegal register access in command stream\n"); 9263 gfx_v10_0_handle_priv_fault(adev, entry); 9264 return 0; 9265 } 9266 9267 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9268 struct amdgpu_irq_src *source, 9269 struct amdgpu_iv_entry *entry) 9270 { 9271 DRM_ERROR("Illegal instruction in command stream\n"); 9272 gfx_v10_0_handle_priv_fault(adev, entry); 9273 return 0; 9274 } 9275 9276 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9277 struct amdgpu_irq_src *src, 9278 unsigned int type, 9279 enum amdgpu_interrupt_state state) 9280 { 9281 uint32_t tmp, target; 9282 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9283 9284 if (ring->me == 1) 9285 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9286 else 9287 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9288 target += ring->pipe; 9289 9290 switch (type) { 9291 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9292 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9293 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9294 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9295 GENERIC2_INT_ENABLE, 0); 9296 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9297 9298 tmp = RREG32_SOC15_IP(GC, target); 9299 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9300 GENERIC2_INT_ENABLE, 0); 9301 WREG32_SOC15_IP(GC, target, tmp); 9302 } else { 9303 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9304 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9305 GENERIC2_INT_ENABLE, 1); 9306 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9307 9308 tmp = RREG32_SOC15_IP(GC, target); 9309 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9310 GENERIC2_INT_ENABLE, 1); 9311 WREG32_SOC15_IP(GC, target, tmp); 9312 } 9313 break; 9314 default: 9315 BUG(); /* kiq only support GENERIC2_INT now */ 9316 break; 9317 } 9318 return 0; 9319 } 9320 9321 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9322 struct amdgpu_irq_src *source, 9323 struct amdgpu_iv_entry *entry) 9324 { 9325 u8 me_id, pipe_id, queue_id; 9326 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9327 9328 me_id = (entry->ring_id & 0x0c) >> 2; 9329 pipe_id = (entry->ring_id & 0x03) >> 0; 9330 queue_id = (entry->ring_id & 0x70) >> 4; 9331 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9332 me_id, pipe_id, queue_id); 9333 9334 amdgpu_fence_process(ring); 9335 return 0; 9336 } 9337 9338 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9339 { 9340 const unsigned int gcr_cntl = 9341 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9342 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9343 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9344 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9345 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9346 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9347 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9348 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9349 9350 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9351 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9352 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9353 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9354 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9355 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9356 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9357 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9358 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9359 } 9360 9361 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9362 .name = "gfx_v10_0", 9363 .early_init = gfx_v10_0_early_init, 9364 .late_init = gfx_v10_0_late_init, 9365 .sw_init = gfx_v10_0_sw_init, 9366 .sw_fini = gfx_v10_0_sw_fini, 9367 .hw_init = gfx_v10_0_hw_init, 9368 .hw_fini = gfx_v10_0_hw_fini, 9369 .suspend = gfx_v10_0_suspend, 9370 .resume = gfx_v10_0_resume, 9371 .is_idle = gfx_v10_0_is_idle, 9372 .wait_for_idle = gfx_v10_0_wait_for_idle, 9373 .soft_reset = gfx_v10_0_soft_reset, 9374 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9375 .set_powergating_state = gfx_v10_0_set_powergating_state, 9376 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9377 }; 9378 9379 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9380 .type = AMDGPU_RING_TYPE_GFX, 9381 .align_mask = 0xff, 9382 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9383 .support_64bit_ptrs = true, 9384 .vmhub = AMDGPU_GFXHUB_0, 9385 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9386 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9387 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9388 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9389 5 + /* COND_EXEC */ 9390 7 + /* PIPELINE_SYNC */ 9391 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9392 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9393 2 + /* VM_FLUSH */ 9394 8 + /* FENCE for VM_FLUSH */ 9395 20 + /* GDS switch */ 9396 4 + /* double SWITCH_BUFFER, 9397 * the first COND_EXEC jump to the place 9398 * just prior to this double SWITCH_BUFFER 9399 */ 9400 5 + /* COND_EXEC */ 9401 7 + /* HDP_flush */ 9402 4 + /* VGT_flush */ 9403 14 + /* CE_META */ 9404 31 + /* DE_META */ 9405 3 + /* CNTX_CTRL */ 9406 5 + /* HDP_INVL */ 9407 8 + 8 + /* FENCE x2 */ 9408 2 + /* SWITCH_BUFFER */ 9409 8, /* gfx_v10_0_emit_mem_sync */ 9410 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9411 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9412 .emit_fence = gfx_v10_0_ring_emit_fence, 9413 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9414 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9415 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9416 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9417 .test_ring = gfx_v10_0_ring_test_ring, 9418 .test_ib = gfx_v10_0_ring_test_ib, 9419 .insert_nop = amdgpu_ring_insert_nop, 9420 .pad_ib = amdgpu_ring_generic_pad_ib, 9421 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9422 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9423 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9424 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9425 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9426 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9427 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9428 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9429 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9430 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9431 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9432 }; 9433 9434 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9435 .type = AMDGPU_RING_TYPE_COMPUTE, 9436 .align_mask = 0xff, 9437 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9438 .support_64bit_ptrs = true, 9439 .vmhub = AMDGPU_GFXHUB_0, 9440 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9441 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9442 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9443 .emit_frame_size = 9444 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9445 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9446 5 + /* hdp invalidate */ 9447 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9448 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9449 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9450 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9451 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9452 8, /* gfx_v10_0_emit_mem_sync */ 9453 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9454 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9455 .emit_fence = gfx_v10_0_ring_emit_fence, 9456 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9457 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9458 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9459 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9460 .test_ring = gfx_v10_0_ring_test_ring, 9461 .test_ib = gfx_v10_0_ring_test_ib, 9462 .insert_nop = amdgpu_ring_insert_nop, 9463 .pad_ib = amdgpu_ring_generic_pad_ib, 9464 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9465 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9466 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9467 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9468 }; 9469 9470 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9471 .type = AMDGPU_RING_TYPE_KIQ, 9472 .align_mask = 0xff, 9473 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9474 .support_64bit_ptrs = true, 9475 .vmhub = AMDGPU_GFXHUB_0, 9476 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9477 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9478 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9479 .emit_frame_size = 9480 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9481 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9482 5 + /*hdp invalidate */ 9483 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9484 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9485 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9486 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9487 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9488 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9489 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9490 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9491 .test_ring = gfx_v10_0_ring_test_ring, 9492 .test_ib = gfx_v10_0_ring_test_ib, 9493 .insert_nop = amdgpu_ring_insert_nop, 9494 .pad_ib = amdgpu_ring_generic_pad_ib, 9495 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9496 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9497 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9498 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9499 }; 9500 9501 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9502 { 9503 int i; 9504 9505 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9506 9507 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9508 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9509 9510 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9511 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9512 } 9513 9514 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9515 .set = gfx_v10_0_set_eop_interrupt_state, 9516 .process = gfx_v10_0_eop_irq, 9517 }; 9518 9519 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9520 .set = gfx_v10_0_set_priv_reg_fault_state, 9521 .process = gfx_v10_0_priv_reg_irq, 9522 }; 9523 9524 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9525 .set = gfx_v10_0_set_priv_inst_fault_state, 9526 .process = gfx_v10_0_priv_inst_irq, 9527 }; 9528 9529 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9530 .set = gfx_v10_0_kiq_set_interrupt_state, 9531 .process = gfx_v10_0_kiq_irq, 9532 }; 9533 9534 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9535 { 9536 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9537 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9538 9539 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9540 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9541 9542 adev->gfx.priv_reg_irq.num_types = 1; 9543 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9544 9545 adev->gfx.priv_inst_irq.num_types = 1; 9546 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9547 } 9548 9549 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9550 { 9551 switch (adev->ip_versions[GC_HWIP][0]) { 9552 case IP_VERSION(10, 1, 10): 9553 case IP_VERSION(10, 1, 1): 9554 case IP_VERSION(10, 1, 3): 9555 case IP_VERSION(10, 1, 4): 9556 case IP_VERSION(10, 3, 2): 9557 case IP_VERSION(10, 3, 1): 9558 case IP_VERSION(10, 3, 4): 9559 case IP_VERSION(10, 3, 5): 9560 case IP_VERSION(10, 3, 6): 9561 case IP_VERSION(10, 3, 3): 9562 case IP_VERSION(10, 3, 7): 9563 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9564 break; 9565 case IP_VERSION(10, 1, 2): 9566 case IP_VERSION(10, 3, 0): 9567 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9568 break; 9569 default: 9570 break; 9571 } 9572 } 9573 9574 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9575 { 9576 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9577 adev->gfx.config.max_sh_per_se * 9578 adev->gfx.config.max_shader_engines; 9579 9580 adev->gds.gds_size = 0x10000; 9581 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9582 adev->gds.gws_size = 64; 9583 adev->gds.oa_size = 16; 9584 } 9585 9586 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9587 u32 bitmap) 9588 { 9589 u32 data; 9590 9591 if (!bitmap) 9592 return; 9593 9594 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9595 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9596 9597 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9598 } 9599 9600 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9601 { 9602 u32 disabled_mask = 9603 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9604 u32 efuse_setting = 0; 9605 u32 vbios_setting = 0; 9606 9607 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9608 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9609 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9610 9611 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9612 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9613 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9614 9615 disabled_mask |= efuse_setting | vbios_setting; 9616 9617 return (~disabled_mask); 9618 } 9619 9620 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9621 { 9622 u32 wgp_idx, wgp_active_bitmap; 9623 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9624 9625 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9626 cu_active_bitmap = 0; 9627 9628 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9629 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9630 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9631 if (wgp_active_bitmap & (1 << wgp_idx)) 9632 cu_active_bitmap |= cu_bitmap_per_wgp; 9633 } 9634 9635 return cu_active_bitmap; 9636 } 9637 9638 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9639 struct amdgpu_cu_info *cu_info) 9640 { 9641 int i, j, k, counter, active_cu_number = 0; 9642 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9643 unsigned disable_masks[4 * 2]; 9644 9645 if (!adev || !cu_info) 9646 return -EINVAL; 9647 9648 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9649 9650 mutex_lock(&adev->grbm_idx_mutex); 9651 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9652 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9653 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9654 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9655 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9656 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9657 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9658 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9659 continue; 9660 mask = 1; 9661 ao_bitmap = 0; 9662 counter = 0; 9663 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9664 if (i < 4 && j < 2) 9665 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9666 adev, disable_masks[i * 2 + j]); 9667 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9668 cu_info->bitmap[i][j] = bitmap; 9669 9670 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9671 if (bitmap & mask) { 9672 if (counter < adev->gfx.config.max_cu_per_sh) 9673 ao_bitmap |= mask; 9674 counter++; 9675 } 9676 mask <<= 1; 9677 } 9678 active_cu_number += counter; 9679 if (i < 2 && j < 2) 9680 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9681 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9682 } 9683 } 9684 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9685 mutex_unlock(&adev->grbm_idx_mutex); 9686 9687 cu_info->number = active_cu_number; 9688 cu_info->ao_cu_mask = ao_cu_mask; 9689 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9690 9691 return 0; 9692 } 9693 9694 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9695 { 9696 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9697 9698 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9699 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9700 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9701 9702 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9703 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9704 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9705 9706 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9707 adev->gfx.config.max_shader_engines); 9708 disabled_sa = efuse_setting | vbios_setting; 9709 disabled_sa &= max_sa_mask; 9710 9711 return disabled_sa; 9712 } 9713 9714 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9715 { 9716 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9717 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9718 9719 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9720 9721 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9722 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9723 max_shader_engines = adev->gfx.config.max_shader_engines; 9724 9725 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9726 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9727 disabled_sa_per_se &= max_sa_per_se_mask; 9728 if (disabled_sa_per_se == max_sa_per_se_mask) { 9729 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9730 break; 9731 } 9732 } 9733 } 9734 9735 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9736 { 9737 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9738 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9739 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9740 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9741 9742 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9743 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9744 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9745 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9746 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9747 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9748 9749 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9750 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9751 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9752 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9753 9754 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9755 9756 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9757 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9758 } 9759 9760 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9761 { 9762 .type = AMD_IP_BLOCK_TYPE_GFX, 9763 .major = 10, 9764 .minor = 0, 9765 .rev = 0, 9766 .funcs = &gfx_v10_0_ip_funcs, 9767 }; 9768