xref: /linux/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (revision 5a558f369ef89c6fd8170ee1137274fcc08517ae)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34 
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15d.h"
44 #include "soc15_common.h"
45 #include "clearstate_gfx10.h"
46 #include "v10_structs.h"
47 #include "gfx_v10_0.h"
48 #include "nbio_v2_3.h"
49 
50 /*
51  * Navi10 has two graphic rings to share each graphic pipe.
52  * 1. Primary ring
53  * 2. Async ring
54  */
55 #define GFX10_NUM_GFX_RINGS_NV1X	1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
57 #define GFX10_MEC_HPD_SIZE	2048
58 
59 #define F32_CE_PROGRAM_RAM_SIZE		65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
61 
62 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68 
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
71 
72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
76 
77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
104 
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
109 
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
114 
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
119 
120 #define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
139 
140 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
142 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
144 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
146 #define mmCP_HYP_CE_UCODE_DATA			0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
148 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
150 #define mmCP_HYP_ME_UCODE_DATA			0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
152 
153 #define mmCPG_PSP_DEBUG				0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX		1
155 #define mmCPC_PSP_DEBUG				0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX		1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
159 
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3                       0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
175 
176 #define mmCGTT_SPI_CS_CLK_CTRL			0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
178 
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid		0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
183 
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
186 
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
189 
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196 
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208 
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215 
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222 
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229 
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236 
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243 
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250 
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257 
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264 
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271 
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278 
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 	SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
370 	/* cp header registers */
371 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
372 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
373 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
374 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
375 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
376 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
377 	/* SE status registers */
378 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
379 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
380 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
381 	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
382 };
383 
384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
385 	/* compute registers */
386 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
387 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
388 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
389 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
390 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
391 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
392 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
393 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
394 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
395 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
396 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
397 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
398 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
399 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
400 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
401 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
402 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
403 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
404 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
405 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
406 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
407 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
408 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
409 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
410 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
411 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
412 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
413 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
414 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
415 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
416 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
417 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
418 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
419 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
420 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
421 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
422 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
423 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
424 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
425 };
426 
427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
428 	/* gfx queue registers */
429 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
430 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
431 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
432 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
433 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
434 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
435 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
436 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
437 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
438 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
439 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
440 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
441 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
442 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
443 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
444 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
445 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
446 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
447 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
448 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
449 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
450 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
451 	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
452 };
453 
454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
495 };
496 
497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
498 	/* Pending on emulation bring up */
499 };
500 
501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1554 };
1555 
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1595 };
1596 
1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1640 };
1641 
1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1643 	/* Pending on emulation bring up */
1644 };
1645 
1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2267 };
2268 
2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2270 	/* Pending on emulation bring up */
2271 };
2272 
2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3326 };
3327 
3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3372 };
3373 
3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3375 	/* Pending on emulation bring up */
3376 };
3377 
3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3420 
3421 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3423 };
3424 
3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3450 
3451 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3453 };
3454 
3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3476 };
3477 
3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3515 };
3516 
3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3550 };
3551 
3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3587 };
3588 
3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3612 };
3613 
3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3637 };
3638 
3639 #define DEFAULT_SH_MEM_CONFIG \
3640 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3641 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3642 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3643 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3644 
3645 /* TODO: pending on golden setting value of gb address config */
3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3647 
3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3654 				 struct amdgpu_cu_info *cu_info);
3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3657 				   u32 sh_num, u32 instance, int xcc_id);
3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3659 
3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3671 					   uint16_t pasid, uint32_t flush_type,
3672 					   bool all_hub, uint8_t dst_sel);
3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3674 					       unsigned int vmid);
3675 
3676 static int gfx_v10_0_set_powergating_state(void *handle,
3677 					  enum amd_powergating_state state);
3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3679 {
3680 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3681 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3682 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3683 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3684 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3685 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
3686 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
3687 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3688 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3689 }
3690 
3691 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3692 				 struct amdgpu_ring *ring)
3693 {
3694 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3695 	uint64_t wptr_addr = ring->wptr_gpu_addr;
3696 	uint32_t eng_sel = 0;
3697 
3698 	switch (ring->funcs->type) {
3699 	case AMDGPU_RING_TYPE_COMPUTE:
3700 		eng_sel = 0;
3701 		break;
3702 	case AMDGPU_RING_TYPE_GFX:
3703 		eng_sel = 4;
3704 		break;
3705 	case AMDGPU_RING_TYPE_MES:
3706 		eng_sel = 5;
3707 		break;
3708 	default:
3709 		WARN_ON(1);
3710 	}
3711 
3712 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3713 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3714 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3715 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3716 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3717 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3718 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3719 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3720 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3721 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3722 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3723 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3724 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3725 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3726 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3727 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3728 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3729 }
3730 
3731 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3732 				   struct amdgpu_ring *ring,
3733 				   enum amdgpu_unmap_queues_action action,
3734 				   u64 gpu_addr, u64 seq)
3735 {
3736 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3737 
3738 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3739 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3740 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3741 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3742 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3743 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3744 	amdgpu_ring_write(kiq_ring,
3745 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3746 
3747 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3748 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3749 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3750 		amdgpu_ring_write(kiq_ring, seq);
3751 	} else {
3752 		amdgpu_ring_write(kiq_ring, 0);
3753 		amdgpu_ring_write(kiq_ring, 0);
3754 		amdgpu_ring_write(kiq_ring, 0);
3755 	}
3756 }
3757 
3758 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3759 				   struct amdgpu_ring *ring,
3760 				   u64 addr,
3761 				   u64 seq)
3762 {
3763 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3764 
3765 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3766 	amdgpu_ring_write(kiq_ring,
3767 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3768 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3769 			  PACKET3_QUERY_STATUS_COMMAND(2));
3770 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3771 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3772 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3773 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3774 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3775 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3776 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3777 }
3778 
3779 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3780 				uint16_t pasid, uint32_t flush_type,
3781 				bool all_hub)
3782 {
3783 	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3784 }
3785 
3786 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3787 	.kiq_set_resources = gfx10_kiq_set_resources,
3788 	.kiq_map_queues = gfx10_kiq_map_queues,
3789 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3790 	.kiq_query_status = gfx10_kiq_query_status,
3791 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3792 	.set_resources_size = 8,
3793 	.map_queues_size = 7,
3794 	.unmap_queues_size = 6,
3795 	.query_status_size = 7,
3796 	.invalidate_tlbs_size = 2,
3797 };
3798 
3799 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3800 {
3801 	adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3802 }
3803 
3804 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3805 {
3806 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3807 	case IP_VERSION(10, 1, 10):
3808 		soc15_program_register_sequence(adev,
3809 						golden_settings_gc_rlc_spm_10_0_nv10,
3810 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3811 		break;
3812 	case IP_VERSION(10, 1, 1):
3813 		soc15_program_register_sequence(adev,
3814 						golden_settings_gc_rlc_spm_10_1_nv14,
3815 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3816 		break;
3817 	case IP_VERSION(10, 1, 2):
3818 		soc15_program_register_sequence(adev,
3819 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3820 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3821 		break;
3822 	default:
3823 		break;
3824 	}
3825 }
3826 
3827 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3828 {
3829 	if (amdgpu_sriov_vf(adev))
3830 		return;
3831 
3832 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3833 	case IP_VERSION(10, 1, 10):
3834 		soc15_program_register_sequence(adev,
3835 						golden_settings_gc_10_1,
3836 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3837 		soc15_program_register_sequence(adev,
3838 						golden_settings_gc_10_0_nv10,
3839 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3840 		break;
3841 	case IP_VERSION(10, 1, 1):
3842 		soc15_program_register_sequence(adev,
3843 						golden_settings_gc_10_1_1,
3844 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3845 		soc15_program_register_sequence(adev,
3846 						golden_settings_gc_10_1_nv14,
3847 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3848 		break;
3849 	case IP_VERSION(10, 1, 2):
3850 		soc15_program_register_sequence(adev,
3851 						golden_settings_gc_10_1_2,
3852 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3853 		soc15_program_register_sequence(adev,
3854 						golden_settings_gc_10_1_2_nv12,
3855 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3856 		break;
3857 	case IP_VERSION(10, 3, 0):
3858 		soc15_program_register_sequence(adev,
3859 						golden_settings_gc_10_3,
3860 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3861 		soc15_program_register_sequence(adev,
3862 						golden_settings_gc_10_3_sienna_cichlid,
3863 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3864 		break;
3865 	case IP_VERSION(10, 3, 2):
3866 		soc15_program_register_sequence(adev,
3867 						golden_settings_gc_10_3_2,
3868 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3869 		break;
3870 	case IP_VERSION(10, 3, 1):
3871 		soc15_program_register_sequence(adev,
3872 						golden_settings_gc_10_3_vangogh,
3873 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3874 		break;
3875 	case IP_VERSION(10, 3, 3):
3876 		soc15_program_register_sequence(adev,
3877 						golden_settings_gc_10_3_3,
3878 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3879 		break;
3880 	case IP_VERSION(10, 3, 4):
3881 		soc15_program_register_sequence(adev,
3882 						golden_settings_gc_10_3_4,
3883 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3884 		break;
3885 	case IP_VERSION(10, 3, 5):
3886 		soc15_program_register_sequence(adev,
3887 						golden_settings_gc_10_3_5,
3888 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3889 		break;
3890 	case IP_VERSION(10, 1, 3):
3891 	case IP_VERSION(10, 1, 4):
3892 		soc15_program_register_sequence(adev,
3893 						golden_settings_gc_10_0_cyan_skillfish,
3894 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3895 		break;
3896 	case IP_VERSION(10, 3, 6):
3897 		soc15_program_register_sequence(adev,
3898 						golden_settings_gc_10_3_6,
3899 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3900 		break;
3901 	case IP_VERSION(10, 3, 7):
3902 		soc15_program_register_sequence(adev,
3903 						golden_settings_gc_10_3_7,
3904 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3905 		break;
3906 	default:
3907 		break;
3908 	}
3909 	gfx_v10_0_init_spm_golden_registers(adev);
3910 }
3911 
3912 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3913 				       bool wc, uint32_t reg, uint32_t val)
3914 {
3915 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3916 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3917 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3918 	amdgpu_ring_write(ring, reg);
3919 	amdgpu_ring_write(ring, 0);
3920 	amdgpu_ring_write(ring, val);
3921 }
3922 
3923 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3924 				  int mem_space, int opt, uint32_t addr0,
3925 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3926 				  uint32_t inv)
3927 {
3928 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3929 	amdgpu_ring_write(ring,
3930 			  /* memory (1) or register (0) */
3931 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3932 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3933 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3934 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3935 
3936 	if (mem_space)
3937 		BUG_ON(addr0 & 0x3); /* Dword align */
3938 	amdgpu_ring_write(ring, addr0);
3939 	amdgpu_ring_write(ring, addr1);
3940 	amdgpu_ring_write(ring, ref);
3941 	amdgpu_ring_write(ring, mask);
3942 	amdgpu_ring_write(ring, inv); /* poll interval */
3943 }
3944 
3945 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3946 {
3947 	struct amdgpu_device *adev = ring->adev;
3948 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3949 	uint32_t tmp = 0;
3950 	unsigned int i;
3951 	int r;
3952 
3953 	WREG32(scratch, 0xCAFEDEAD);
3954 	r = amdgpu_ring_alloc(ring, 3);
3955 	if (r) {
3956 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3957 			  ring->idx, r);
3958 		return r;
3959 	}
3960 
3961 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3962 	amdgpu_ring_write(ring, scratch -
3963 			  PACKET3_SET_UCONFIG_REG_START);
3964 	amdgpu_ring_write(ring, 0xDEADBEEF);
3965 	amdgpu_ring_commit(ring);
3966 
3967 	for (i = 0; i < adev->usec_timeout; i++) {
3968 		tmp = RREG32(scratch);
3969 		if (tmp == 0xDEADBEEF)
3970 			break;
3971 		if (amdgpu_emu_mode == 1)
3972 			msleep(1);
3973 		else
3974 			udelay(1);
3975 	}
3976 
3977 	if (i >= adev->usec_timeout)
3978 		r = -ETIMEDOUT;
3979 
3980 	return r;
3981 }
3982 
3983 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3984 {
3985 	struct amdgpu_device *adev = ring->adev;
3986 	struct amdgpu_ib ib;
3987 	struct dma_fence *f = NULL;
3988 	unsigned int index;
3989 	uint64_t gpu_addr;
3990 	volatile uint32_t *cpu_ptr;
3991 	long r;
3992 
3993 	memset(&ib, 0, sizeof(ib));
3994 
3995 	r = amdgpu_device_wb_get(adev, &index);
3996 	if (r)
3997 		return r;
3998 
3999 	gpu_addr = adev->wb.gpu_addr + (index * 4);
4000 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4001 	cpu_ptr = &adev->wb.wb[index];
4002 
4003 	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4004 	if (r) {
4005 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4006 		goto err1;
4007 	}
4008 
4009 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4010 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4011 	ib.ptr[2] = lower_32_bits(gpu_addr);
4012 	ib.ptr[3] = upper_32_bits(gpu_addr);
4013 	ib.ptr[4] = 0xDEADBEEF;
4014 	ib.length_dw = 5;
4015 
4016 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4017 	if (r)
4018 		goto err2;
4019 
4020 	r = dma_fence_wait_timeout(f, false, timeout);
4021 	if (r == 0) {
4022 		r = -ETIMEDOUT;
4023 		goto err2;
4024 	} else if (r < 0) {
4025 		goto err2;
4026 	}
4027 
4028 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4029 		r = 0;
4030 	else
4031 		r = -EINVAL;
4032 err2:
4033 	amdgpu_ib_free(adev, &ib, NULL);
4034 	dma_fence_put(f);
4035 err1:
4036 	amdgpu_device_wb_free(adev, index);
4037 	return r;
4038 }
4039 
4040 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4041 {
4042 	amdgpu_ucode_release(&adev->gfx.pfp_fw);
4043 	amdgpu_ucode_release(&adev->gfx.me_fw);
4044 	amdgpu_ucode_release(&adev->gfx.ce_fw);
4045 	amdgpu_ucode_release(&adev->gfx.rlc_fw);
4046 	amdgpu_ucode_release(&adev->gfx.mec_fw);
4047 	amdgpu_ucode_release(&adev->gfx.mec2_fw);
4048 
4049 	kfree(adev->gfx.rlc.register_list_format);
4050 }
4051 
4052 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4053 {
4054 	adev->gfx.cp_fw_write_wait = false;
4055 
4056 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4057 	case IP_VERSION(10, 1, 10):
4058 	case IP_VERSION(10, 1, 2):
4059 	case IP_VERSION(10, 1, 1):
4060 	case IP_VERSION(10, 1, 3):
4061 	case IP_VERSION(10, 1, 4):
4062 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
4063 		    (adev->gfx.me_feature_version >= 27) &&
4064 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
4065 		    (adev->gfx.pfp_feature_version >= 27) &&
4066 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
4067 		    (adev->gfx.mec_feature_version >= 27))
4068 			adev->gfx.cp_fw_write_wait = true;
4069 		break;
4070 	case IP_VERSION(10, 3, 0):
4071 	case IP_VERSION(10, 3, 2):
4072 	case IP_VERSION(10, 3, 1):
4073 	case IP_VERSION(10, 3, 4):
4074 	case IP_VERSION(10, 3, 5):
4075 	case IP_VERSION(10, 3, 6):
4076 	case IP_VERSION(10, 3, 3):
4077 	case IP_VERSION(10, 3, 7):
4078 		adev->gfx.cp_fw_write_wait = true;
4079 		break;
4080 	default:
4081 		break;
4082 	}
4083 
4084 	if (!adev->gfx.cp_fw_write_wait)
4085 		DRM_WARN_ONCE("CP firmware version too old, please update!");
4086 }
4087 
4088 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4089 {
4090 	bool ret = false;
4091 
4092 	switch (adev->pdev->revision) {
4093 	case 0xc2:
4094 	case 0xc3:
4095 		ret = true;
4096 		break;
4097 	default:
4098 		ret = false;
4099 		break;
4100 	}
4101 
4102 	return ret;
4103 }
4104 
4105 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4106 {
4107 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4108 	case IP_VERSION(10, 1, 10):
4109 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4110 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4111 		break;
4112 	default:
4113 		break;
4114 	}
4115 }
4116 
4117 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4118 {
4119 	char fw_name[53];
4120 	char ucode_prefix[30];
4121 	const char *wks = "";
4122 	int err;
4123 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4124 	uint16_t version_major;
4125 	uint16_t version_minor;
4126 
4127 	DRM_DEBUG("\n");
4128 
4129 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4130 	    (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4131 		wks = "_wks";
4132 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4133 
4134 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4135 	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
4136 	if (err)
4137 		goto out;
4138 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4139 
4140 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4141 	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
4142 	if (err)
4143 		goto out;
4144 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4145 
4146 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4147 	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
4148 	if (err)
4149 		goto out;
4150 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4151 
4152 	if (!amdgpu_sriov_vf(adev)) {
4153 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4154 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4155 		if (err)
4156 			goto out;
4157 
4158 		/* don't validate this firmware. There are apparently firmwares
4159 		 * in the wild with incorrect size in the header
4160 		 */
4161 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4162 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4163 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4164 		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4165 		if (err)
4166 			goto out;
4167 	}
4168 
4169 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4170 	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4171 	if (err)
4172 		goto out;
4173 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4174 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4175 
4176 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4177 	err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4178 	if (!err) {
4179 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4180 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4181 	} else {
4182 		err = 0;
4183 		adev->gfx.mec2_fw = NULL;
4184 	}
4185 
4186 	gfx_v10_0_check_fw_write_wait(adev);
4187 out:
4188 	if (err) {
4189 		amdgpu_ucode_release(&adev->gfx.pfp_fw);
4190 		amdgpu_ucode_release(&adev->gfx.me_fw);
4191 		amdgpu_ucode_release(&adev->gfx.ce_fw);
4192 		amdgpu_ucode_release(&adev->gfx.rlc_fw);
4193 		amdgpu_ucode_release(&adev->gfx.mec_fw);
4194 		amdgpu_ucode_release(&adev->gfx.mec2_fw);
4195 	}
4196 
4197 	gfx_v10_0_check_gfxoff_flag(adev);
4198 
4199 	return err;
4200 }
4201 
4202 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4203 {
4204 	u32 count = 0;
4205 	const struct cs_section_def *sect = NULL;
4206 	const struct cs_extent_def *ext = NULL;
4207 
4208 	/* begin clear state */
4209 	count += 2;
4210 	/* context control state */
4211 	count += 3;
4212 
4213 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4214 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4215 			if (sect->id == SECT_CONTEXT)
4216 				count += 2 + ext->reg_count;
4217 			else
4218 				return 0;
4219 		}
4220 	}
4221 
4222 	/* set PA_SC_TILE_STEERING_OVERRIDE */
4223 	count += 3;
4224 	/* end clear state */
4225 	count += 2;
4226 	/* clear state */
4227 	count += 2;
4228 
4229 	return count;
4230 }
4231 
4232 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4233 				    volatile u32 *buffer)
4234 {
4235 	u32 count = 0, i;
4236 	const struct cs_section_def *sect = NULL;
4237 	const struct cs_extent_def *ext = NULL;
4238 	int ctx_reg_offset;
4239 
4240 	if (adev->gfx.rlc.cs_data == NULL)
4241 		return;
4242 	if (buffer == NULL)
4243 		return;
4244 
4245 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4246 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4247 
4248 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4249 	buffer[count++] = cpu_to_le32(0x80000000);
4250 	buffer[count++] = cpu_to_le32(0x80000000);
4251 
4252 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4253 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4254 			if (sect->id == SECT_CONTEXT) {
4255 				buffer[count++] =
4256 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4257 				buffer[count++] = cpu_to_le32(ext->reg_index -
4258 						PACKET3_SET_CONTEXT_REG_START);
4259 				for (i = 0; i < ext->reg_count; i++)
4260 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4261 			} else {
4262 				return;
4263 			}
4264 		}
4265 	}
4266 
4267 	ctx_reg_offset =
4268 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4269 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4270 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4271 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4272 
4273 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4274 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4275 
4276 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4277 	buffer[count++] = cpu_to_le32(0);
4278 }
4279 
4280 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4281 {
4282 	/* clear state block */
4283 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4284 			&adev->gfx.rlc.clear_state_gpu_addr,
4285 			(void **)&adev->gfx.rlc.cs_ptr);
4286 
4287 	/* jump table block */
4288 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4289 			&adev->gfx.rlc.cp_table_gpu_addr,
4290 			(void **)&adev->gfx.rlc.cp_table_ptr);
4291 }
4292 
4293 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4294 {
4295 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4296 
4297 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4298 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4299 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4300 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4301 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4302 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4303 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4304 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4305 	case IP_VERSION(10, 3, 0):
4306 		reg_access_ctrl->spare_int =
4307 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4308 		break;
4309 	default:
4310 		reg_access_ctrl->spare_int =
4311 			SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4312 		break;
4313 	}
4314 	adev->gfx.rlc.rlcg_reg_access_supported = true;
4315 }
4316 
4317 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4318 {
4319 	const struct cs_section_def *cs_data;
4320 	int r;
4321 
4322 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4323 
4324 	cs_data = adev->gfx.rlc.cs_data;
4325 
4326 	if (cs_data) {
4327 		/* init clear state block */
4328 		r = amdgpu_gfx_rlc_init_csb(adev);
4329 		if (r)
4330 			return r;
4331 	}
4332 
4333 	return 0;
4334 }
4335 
4336 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4337 {
4338 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4339 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4340 }
4341 
4342 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4343 {
4344 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4345 
4346 	amdgpu_gfx_graphics_queue_acquire(adev);
4347 }
4348 
4349 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4350 {
4351 	int r;
4352 	u32 *hpd;
4353 	const __le32 *fw_data = NULL;
4354 	unsigned int fw_size;
4355 	u32 *fw = NULL;
4356 	size_t mec_hpd_size;
4357 
4358 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4359 
4360 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4361 
4362 	/* take ownership of the relevant compute queues */
4363 	amdgpu_gfx_compute_queue_acquire(adev);
4364 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4365 
4366 	if (mec_hpd_size) {
4367 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4368 					      AMDGPU_GEM_DOMAIN_GTT,
4369 					      &adev->gfx.mec.hpd_eop_obj,
4370 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4371 					      (void **)&hpd);
4372 		if (r) {
4373 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4374 			gfx_v10_0_mec_fini(adev);
4375 			return r;
4376 		}
4377 
4378 		memset(hpd, 0, mec_hpd_size);
4379 
4380 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4381 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4382 	}
4383 
4384 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4385 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4386 
4387 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4388 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4389 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4390 
4391 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4392 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4393 					      &adev->gfx.mec.mec_fw_obj,
4394 					      &adev->gfx.mec.mec_fw_gpu_addr,
4395 					      (void **)&fw);
4396 		if (r) {
4397 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4398 			gfx_v10_0_mec_fini(adev);
4399 			return r;
4400 		}
4401 
4402 		memcpy(fw, fw_data, fw_size);
4403 
4404 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4405 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4406 	}
4407 
4408 	return 0;
4409 }
4410 
4411 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4412 {
4413 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4414 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4415 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4416 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4417 }
4418 
4419 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4420 			   uint32_t thread, uint32_t regno,
4421 			   uint32_t num, uint32_t *out)
4422 {
4423 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4424 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4425 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4426 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4427 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4428 	while (num--)
4429 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4430 }
4431 
4432 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4433 {
4434 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4435 	 * field when performing a select_se_sh so it should be
4436 	 * zero here
4437 	 */
4438 	WARN_ON(simd != 0);
4439 
4440 	/* type 2 wave data */
4441 	dst[(*no_fields)++] = 2;
4442 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4443 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4444 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4445 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4446 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4447 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4448 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4449 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4450 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4451 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4452 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4453 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4454 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4455 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4456 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4457 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4458 }
4459 
4460 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4461 				     uint32_t wave, uint32_t start,
4462 				     uint32_t size, uint32_t *dst)
4463 {
4464 	WARN_ON(simd != 0);
4465 
4466 	wave_read_regs(
4467 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4468 		dst);
4469 }
4470 
4471 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4472 				      uint32_t wave, uint32_t thread,
4473 				      uint32_t start, uint32_t size,
4474 				      uint32_t *dst)
4475 {
4476 	wave_read_regs(
4477 		adev, wave, thread,
4478 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4479 }
4480 
4481 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4482 				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4483 {
4484 	nv_grbm_select(adev, me, pipe, q, vm);
4485 }
4486 
4487 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4488 					  bool enable)
4489 {
4490 	uint32_t data, def;
4491 
4492 	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4493 
4494 	if (enable)
4495 		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4496 	else
4497 		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4498 
4499 	if (data != def)
4500 		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4501 }
4502 
4503 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4504 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4505 	.select_se_sh = &gfx_v10_0_select_se_sh,
4506 	.read_wave_data = &gfx_v10_0_read_wave_data,
4507 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4508 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4509 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4510 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4511 	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4512 };
4513 
4514 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4515 {
4516 	u32 gb_addr_config;
4517 
4518 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4519 	case IP_VERSION(10, 1, 10):
4520 	case IP_VERSION(10, 1, 1):
4521 	case IP_VERSION(10, 1, 2):
4522 		adev->gfx.config.max_hw_contexts = 8;
4523 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4524 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4525 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4526 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4527 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4528 		break;
4529 	case IP_VERSION(10, 3, 0):
4530 	case IP_VERSION(10, 3, 2):
4531 	case IP_VERSION(10, 3, 1):
4532 	case IP_VERSION(10, 3, 4):
4533 	case IP_VERSION(10, 3, 5):
4534 	case IP_VERSION(10, 3, 6):
4535 	case IP_VERSION(10, 3, 3):
4536 	case IP_VERSION(10, 3, 7):
4537 		adev->gfx.config.max_hw_contexts = 8;
4538 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4539 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4540 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4541 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4542 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4543 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4544 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4545 		break;
4546 	case IP_VERSION(10, 1, 3):
4547 	case IP_VERSION(10, 1, 4):
4548 		adev->gfx.config.max_hw_contexts = 8;
4549 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4550 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4551 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4552 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4553 		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4554 		break;
4555 	default:
4556 		BUG();
4557 		break;
4558 	}
4559 
4560 	adev->gfx.config.gb_addr_config = gb_addr_config;
4561 
4562 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4563 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4564 				      GB_ADDR_CONFIG, NUM_PIPES);
4565 
4566 	adev->gfx.config.max_tile_pipes =
4567 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4568 
4569 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4570 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4571 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4572 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4573 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4574 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4575 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4576 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4577 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4578 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4579 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4580 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4581 }
4582 
4583 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4584 				   int me, int pipe, int queue)
4585 {
4586 	struct amdgpu_ring *ring;
4587 	unsigned int irq_type;
4588 	unsigned int hw_prio;
4589 
4590 	ring = &adev->gfx.gfx_ring[ring_id];
4591 
4592 	ring->me = me;
4593 	ring->pipe = pipe;
4594 	ring->queue = queue;
4595 
4596 	ring->ring_obj = NULL;
4597 	ring->use_doorbell = true;
4598 
4599 	if (!ring_id)
4600 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4601 	else
4602 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4603 	ring->vm_hub = AMDGPU_GFXHUB(0);
4604 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4605 
4606 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4607 	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4608 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4609 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4610 				hw_prio, NULL);
4611 }
4612 
4613 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4614 				       int mec, int pipe, int queue)
4615 {
4616 	unsigned int irq_type;
4617 	struct amdgpu_ring *ring;
4618 	unsigned int hw_prio;
4619 
4620 	ring = &adev->gfx.compute_ring[ring_id];
4621 
4622 	/* mec0 is me1 */
4623 	ring->me = mec + 1;
4624 	ring->pipe = pipe;
4625 	ring->queue = queue;
4626 
4627 	ring->ring_obj = NULL;
4628 	ring->use_doorbell = true;
4629 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4630 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4631 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4632 	ring->vm_hub = AMDGPU_GFXHUB(0);
4633 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4634 
4635 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4636 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4637 		+ ring->pipe;
4638 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4639 			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4640 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4641 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4642 			     hw_prio, NULL);
4643 }
4644 
4645 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4646 {
4647 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4648 	uint32_t *ptr;
4649 	uint32_t inst;
4650 
4651 	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4652 	if (ptr == NULL) {
4653 		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4654 		adev->gfx.ip_dump_core = NULL;
4655 	} else {
4656 		adev->gfx.ip_dump_core = ptr;
4657 	}
4658 
4659 	/* Allocate memory for compute queue registers for all the instances */
4660 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4661 	inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4662 		adev->gfx.mec.num_queue_per_pipe;
4663 
4664 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4665 	if (ptr == NULL) {
4666 		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4667 		adev->gfx.ip_dump_compute_queues = NULL;
4668 	} else {
4669 		adev->gfx.ip_dump_compute_queues = ptr;
4670 	}
4671 
4672 	/* Allocate memory for gfx queue registers for all the instances */
4673 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4674 	inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4675 		adev->gfx.me.num_queue_per_pipe;
4676 
4677 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4678 	if (ptr == NULL) {
4679 		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4680 		adev->gfx.ip_dump_gfx_queues = NULL;
4681 	} else {
4682 		adev->gfx.ip_dump_gfx_queues = ptr;
4683 	}
4684 }
4685 
4686 static int gfx_v10_0_sw_init(void *handle)
4687 {
4688 	int i, j, k, r, ring_id = 0;
4689 	int xcc_id = 0;
4690 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4691 
4692 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4693 	case IP_VERSION(10, 1, 10):
4694 	case IP_VERSION(10, 1, 1):
4695 	case IP_VERSION(10, 1, 2):
4696 	case IP_VERSION(10, 1, 3):
4697 	case IP_VERSION(10, 1, 4):
4698 		adev->gfx.me.num_me = 1;
4699 		adev->gfx.me.num_pipe_per_me = 1;
4700 		adev->gfx.me.num_queue_per_pipe = 1;
4701 		adev->gfx.mec.num_mec = 2;
4702 		adev->gfx.mec.num_pipe_per_mec = 4;
4703 		adev->gfx.mec.num_queue_per_pipe = 8;
4704 		break;
4705 	case IP_VERSION(10, 3, 0):
4706 	case IP_VERSION(10, 3, 2):
4707 	case IP_VERSION(10, 3, 1):
4708 	case IP_VERSION(10, 3, 4):
4709 	case IP_VERSION(10, 3, 5):
4710 	case IP_VERSION(10, 3, 6):
4711 	case IP_VERSION(10, 3, 3):
4712 	case IP_VERSION(10, 3, 7):
4713 		adev->gfx.me.num_me = 1;
4714 		adev->gfx.me.num_pipe_per_me = 2;
4715 		adev->gfx.me.num_queue_per_pipe = 1;
4716 		adev->gfx.mec.num_mec = 2;
4717 		adev->gfx.mec.num_pipe_per_mec = 4;
4718 		adev->gfx.mec.num_queue_per_pipe = 4;
4719 		break;
4720 	default:
4721 		adev->gfx.me.num_me = 1;
4722 		adev->gfx.me.num_pipe_per_me = 1;
4723 		adev->gfx.me.num_queue_per_pipe = 1;
4724 		adev->gfx.mec.num_mec = 1;
4725 		adev->gfx.mec.num_pipe_per_mec = 4;
4726 		adev->gfx.mec.num_queue_per_pipe = 8;
4727 		break;
4728 	}
4729 
4730 	/* KIQ event */
4731 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4732 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4733 			      &adev->gfx.kiq[0].irq);
4734 	if (r)
4735 		return r;
4736 
4737 	/* EOP Event */
4738 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4739 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4740 			      &adev->gfx.eop_irq);
4741 	if (r)
4742 		return r;
4743 
4744 	/* Privileged reg */
4745 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4746 			      &adev->gfx.priv_reg_irq);
4747 	if (r)
4748 		return r;
4749 
4750 	/* Privileged inst */
4751 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4752 			      &adev->gfx.priv_inst_irq);
4753 	if (r)
4754 		return r;
4755 
4756 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4757 
4758 	gfx_v10_0_me_init(adev);
4759 
4760 	if (adev->gfx.rlc.funcs) {
4761 		if (adev->gfx.rlc.funcs->init) {
4762 			r = adev->gfx.rlc.funcs->init(adev);
4763 			if (r) {
4764 				dev_err(adev->dev, "Failed to init rlc BOs!\n");
4765 				return r;
4766 			}
4767 		}
4768 	}
4769 
4770 	r = gfx_v10_0_mec_init(adev);
4771 	if (r) {
4772 		DRM_ERROR("Failed to init MEC BOs!\n");
4773 		return r;
4774 	}
4775 
4776 	/* set up the gfx ring */
4777 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4778 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4779 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4780 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4781 					continue;
4782 
4783 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4784 							    i, k, j);
4785 				if (r)
4786 					return r;
4787 				ring_id++;
4788 			}
4789 		}
4790 	}
4791 
4792 	ring_id = 0;
4793 	/* set up the compute queues - allocate horizontally across pipes */
4794 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4795 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4796 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4797 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4798 								     k, j))
4799 					continue;
4800 
4801 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4802 								i, k, j);
4803 				if (r)
4804 					return r;
4805 
4806 				ring_id++;
4807 			}
4808 		}
4809 	}
4810 
4811 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4812 	if (r) {
4813 		DRM_ERROR("Failed to init KIQ BOs!\n");
4814 		return r;
4815 	}
4816 
4817 	r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4818 	if (r)
4819 		return r;
4820 
4821 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4822 	if (r)
4823 		return r;
4824 
4825 	/* allocate visible FB for rlc auto-loading fw */
4826 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4827 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4828 		if (r)
4829 			return r;
4830 	}
4831 
4832 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4833 
4834 	gfx_v10_0_gpu_early_init(adev);
4835 
4836 	gfx_v10_0_alloc_ip_dump(adev);
4837 
4838 	return 0;
4839 }
4840 
4841 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4842 {
4843 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4844 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4845 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4846 }
4847 
4848 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4849 {
4850 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4851 			      &adev->gfx.ce.ce_fw_gpu_addr,
4852 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4853 }
4854 
4855 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4856 {
4857 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4858 			      &adev->gfx.me.me_fw_gpu_addr,
4859 			      (void **)&adev->gfx.me.me_fw_ptr);
4860 }
4861 
4862 static int gfx_v10_0_sw_fini(void *handle)
4863 {
4864 	int i;
4865 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4866 
4867 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4868 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4869 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4870 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4871 
4872 	amdgpu_gfx_mqd_sw_fini(adev, 0);
4873 
4874 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4875 	amdgpu_gfx_kiq_fini(adev, 0);
4876 
4877 	gfx_v10_0_pfp_fini(adev);
4878 	gfx_v10_0_ce_fini(adev);
4879 	gfx_v10_0_me_fini(adev);
4880 	gfx_v10_0_rlc_fini(adev);
4881 	gfx_v10_0_mec_fini(adev);
4882 
4883 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4884 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4885 
4886 	gfx_v10_0_free_microcode(adev);
4887 
4888 	kfree(adev->gfx.ip_dump_core);
4889 	kfree(adev->gfx.ip_dump_compute_queues);
4890 	kfree(adev->gfx.ip_dump_gfx_queues);
4891 
4892 	return 0;
4893 }
4894 
4895 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4896 				   u32 sh_num, u32 instance, int xcc_id)
4897 {
4898 	u32 data;
4899 
4900 	if (instance == 0xffffffff)
4901 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4902 				     INSTANCE_BROADCAST_WRITES, 1);
4903 	else
4904 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4905 				     instance);
4906 
4907 	if (se_num == 0xffffffff)
4908 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4909 				     1);
4910 	else
4911 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4912 
4913 	if (sh_num == 0xffffffff)
4914 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4915 				     1);
4916 	else
4917 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4918 
4919 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4920 }
4921 
4922 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4923 {
4924 	u32 data, mask;
4925 
4926 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4927 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4928 
4929 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4930 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4931 
4932 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4933 					 adev->gfx.config.max_sh_per_se);
4934 
4935 	return (~data) & mask;
4936 }
4937 
4938 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4939 {
4940 	int i, j;
4941 	u32 data;
4942 	u32 active_rbs = 0;
4943 	u32 bitmap;
4944 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4945 					adev->gfx.config.max_sh_per_se;
4946 
4947 	mutex_lock(&adev->grbm_idx_mutex);
4948 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4949 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4950 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
4951 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4952 			      IP_VERSION(10, 3, 0)) ||
4953 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4954 			      IP_VERSION(10, 3, 3)) ||
4955 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4956 			      IP_VERSION(10, 3, 6))) &&
4957 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4958 				continue;
4959 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4960 			data = gfx_v10_0_get_rb_active_bitmap(adev);
4961 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4962 					       rb_bitmap_width_per_sh);
4963 		}
4964 	}
4965 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4966 	mutex_unlock(&adev->grbm_idx_mutex);
4967 
4968 	adev->gfx.config.backend_enable_mask = active_rbs;
4969 	adev->gfx.config.num_rbs = hweight32(active_rbs);
4970 }
4971 
4972 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4973 {
4974 	uint32_t num_sc;
4975 	uint32_t enabled_rb_per_sh;
4976 	uint32_t active_rb_bitmap;
4977 	uint32_t num_rb_per_sc;
4978 	uint32_t num_packer_per_sc;
4979 	uint32_t pa_sc_tile_steering_override;
4980 
4981 	/* for ASICs that integrates GFX v10.3
4982 	 * pa_sc_tile_steering_override should be set to 0
4983 	 */
4984 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4985 		return 0;
4986 
4987 	/* init num_sc */
4988 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4989 			adev->gfx.config.num_sc_per_sh;
4990 	/* init num_rb_per_sc */
4991 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4992 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
4993 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4994 	/* init num_packer_per_sc */
4995 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4996 
4997 	pa_sc_tile_steering_override = 0;
4998 	pa_sc_tile_steering_override |=
4999 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5000 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5001 	pa_sc_tile_steering_override |=
5002 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5003 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5004 	pa_sc_tile_steering_override |=
5005 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5006 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5007 
5008 	return pa_sc_tile_steering_override;
5009 }
5010 
5011 #define DEFAULT_SH_MEM_BASES	(0x6000)
5012 
5013 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5014 				uint32_t first_vmid,
5015 				uint32_t last_vmid)
5016 {
5017 	uint32_t data;
5018 	uint32_t trap_config_vmid_mask = 0;
5019 	int i;
5020 
5021 	/* Calculate trap config vmid mask */
5022 	for (i = first_vmid; i < last_vmid; i++)
5023 		trap_config_vmid_mask |= (1 << i);
5024 
5025 	data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5026 			VMID_SEL, trap_config_vmid_mask);
5027 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5028 			TRAP_EN, 1);
5029 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5030 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5031 
5032 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5033 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5034 }
5035 
5036 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5037 {
5038 	int i;
5039 	uint32_t sh_mem_bases;
5040 
5041 	/*
5042 	 * Configure apertures:
5043 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5044 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5045 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5046 	 */
5047 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5048 
5049 	mutex_lock(&adev->srbm_mutex);
5050 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5051 		nv_grbm_select(adev, 0, 0, 0, i);
5052 		/* CP and shaders */
5053 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5054 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5055 	}
5056 	nv_grbm_select(adev, 0, 0, 0, 0);
5057 	mutex_unlock(&adev->srbm_mutex);
5058 
5059 	/*
5060 	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
5061 	 * access. These should be enabled by FW for target VMIDs.
5062 	 */
5063 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5064 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5065 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5066 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5067 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5068 	}
5069 
5070 	gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5071 					AMDGPU_NUM_VMID);
5072 }
5073 
5074 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5075 {
5076 	int vmid;
5077 
5078 	/*
5079 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5080 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5081 	 * the driver can enable them for graphics. VMID0 should maintain
5082 	 * access so that HWS firmware can save/restore entries.
5083 	 */
5084 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5085 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5086 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5087 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5088 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5089 	}
5090 }
5091 
5092 
5093 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5094 {
5095 	int i, j, k;
5096 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5097 	u32 tmp, wgp_active_bitmap = 0;
5098 	u32 gcrd_targets_disable_tcp = 0;
5099 	u32 utcl_invreq_disable = 0;
5100 	/*
5101 	 * GCRD_TARGETS_DISABLE field contains
5102 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5103 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5104 	 */
5105 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5106 		2 * max_wgp_per_sh + /* TCP */
5107 		max_wgp_per_sh + /* SQC */
5108 		4); /* GL1C */
5109 	/*
5110 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5111 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5112 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5113 	 */
5114 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5115 		2 * max_wgp_per_sh + /* TCP */
5116 		2 * max_wgp_per_sh + /* SQC */
5117 		4 + /* RMI */
5118 		1); /* SQG */
5119 
5120 	mutex_lock(&adev->grbm_idx_mutex);
5121 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5122 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5123 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5124 			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5125 			/*
5126 			 * Set corresponding TCP bits for the inactive WGPs in
5127 			 * GCRD_SA_TARGETS_DISABLE
5128 			 */
5129 			gcrd_targets_disable_tcp = 0;
5130 			/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5131 			utcl_invreq_disable = 0;
5132 
5133 			for (k = 0; k < max_wgp_per_sh; k++) {
5134 				if (!(wgp_active_bitmap & (1 << k))) {
5135 					gcrd_targets_disable_tcp |= 3 << (2 * k);
5136 					gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5137 					utcl_invreq_disable |= (3 << (2 * k)) |
5138 						(3 << (2 * (max_wgp_per_sh + k)));
5139 				}
5140 			}
5141 
5142 			tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5143 			/* only override TCP & SQC bits */
5144 			tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5145 			tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5146 			WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5147 
5148 			tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5149 			/* only override TCP & SQC bits */
5150 			tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5151 			tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5152 			WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5153 		}
5154 	}
5155 
5156 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5157 	mutex_unlock(&adev->grbm_idx_mutex);
5158 }
5159 
5160 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5161 {
5162 	/* TCCs are global (not instanced). */
5163 	uint32_t tcc_disable;
5164 
5165 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5166 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5167 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5168 	} else {
5169 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5170 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5171 	}
5172 
5173 	adev->gfx.config.tcc_disabled_mask =
5174 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5175 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5176 }
5177 
5178 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5179 {
5180 	u32 tmp;
5181 	int i;
5182 
5183 	if (!amdgpu_sriov_vf(adev))
5184 		WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5185 
5186 	gfx_v10_0_setup_rb(adev);
5187 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5188 	gfx_v10_0_get_tcc_info(adev);
5189 	adev->gfx.config.pa_sc_tile_steering_override =
5190 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5191 
5192 	/* XXX SH_MEM regs */
5193 	/* where to put LDS, scratch, GPUVM in FSA64 space */
5194 	mutex_lock(&adev->srbm_mutex);
5195 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5196 		nv_grbm_select(adev, 0, 0, 0, i);
5197 		/* CP and shaders */
5198 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5199 		if (i != 0) {
5200 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5201 				(adev->gmc.private_aperture_start >> 48));
5202 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5203 				(adev->gmc.shared_aperture_start >> 48));
5204 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5205 		}
5206 	}
5207 	nv_grbm_select(adev, 0, 0, 0, 0);
5208 
5209 	mutex_unlock(&adev->srbm_mutex);
5210 
5211 	gfx_v10_0_init_compute_vmid(adev);
5212 	gfx_v10_0_init_gds_vmid(adev);
5213 
5214 }
5215 
5216 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5217 					       bool enable)
5218 {
5219 	u32 tmp;
5220 
5221 	if (amdgpu_sriov_vf(adev))
5222 		return;
5223 
5224 	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5225 
5226 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5227 			    enable ? 1 : 0);
5228 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5229 			    enable ? 1 : 0);
5230 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5231 			    enable ? 1 : 0);
5232 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5233 			    enable ? 1 : 0);
5234 
5235 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5236 }
5237 
5238 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5239 {
5240 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5241 
5242 	/* csib */
5243 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5244 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5245 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5246 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5247 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5248 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5249 	} else {
5250 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5251 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5252 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5253 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5254 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5255 	}
5256 	return 0;
5257 }
5258 
5259 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5260 {
5261 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5262 
5263 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5264 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5265 }
5266 
5267 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5268 {
5269 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5270 	udelay(50);
5271 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5272 	udelay(50);
5273 }
5274 
5275 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5276 					     bool enable)
5277 {
5278 	uint32_t rlc_pg_cntl;
5279 
5280 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5281 
5282 	if (!enable) {
5283 		/* RLC_PG_CNTL[23] = 0 (default)
5284 		 * RLC will wait for handshake acks with SMU
5285 		 * GFXOFF will be enabled
5286 		 * RLC_PG_CNTL[23] = 1
5287 		 * RLC will not issue any message to SMU
5288 		 * hence no handshake between SMU & RLC
5289 		 * GFXOFF will be disabled
5290 		 */
5291 		rlc_pg_cntl |= 0x800000;
5292 	} else
5293 		rlc_pg_cntl &= ~0x800000;
5294 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5295 }
5296 
5297 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5298 {
5299 	/*
5300 	 * TODO: enable rlc & smu handshake until smu
5301 	 * and gfxoff feature works as expected
5302 	 */
5303 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5304 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5305 
5306 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5307 	udelay(50);
5308 }
5309 
5310 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5311 {
5312 	uint32_t tmp;
5313 
5314 	/* enable Save Restore Machine */
5315 	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5316 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5317 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5318 	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5319 }
5320 
5321 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5322 {
5323 	const struct rlc_firmware_header_v2_0 *hdr;
5324 	const __le32 *fw_data;
5325 	unsigned int i, fw_size;
5326 
5327 	if (!adev->gfx.rlc_fw)
5328 		return -EINVAL;
5329 
5330 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5331 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
5332 
5333 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5334 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5335 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5336 
5337 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5338 		     RLCG_UCODE_LOADING_START_ADDRESS);
5339 
5340 	for (i = 0; i < fw_size; i++)
5341 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5342 			     le32_to_cpup(fw_data++));
5343 
5344 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5345 
5346 	return 0;
5347 }
5348 
5349 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5350 {
5351 	int r;
5352 
5353 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5354 		adev->psp.autoload_supported) {
5355 
5356 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5357 		if (r)
5358 			return r;
5359 
5360 		gfx_v10_0_init_csb(adev);
5361 
5362 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5363 
5364 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5365 			gfx_v10_0_rlc_enable_srm(adev);
5366 	} else {
5367 		if (amdgpu_sriov_vf(adev)) {
5368 			gfx_v10_0_init_csb(adev);
5369 			return 0;
5370 		}
5371 
5372 		adev->gfx.rlc.funcs->stop(adev);
5373 
5374 		/* disable CG */
5375 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5376 
5377 		/* disable PG */
5378 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5379 
5380 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5381 			/* legacy rlc firmware loading */
5382 			r = gfx_v10_0_rlc_load_microcode(adev);
5383 			if (r)
5384 				return r;
5385 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5386 			/* rlc backdoor autoload firmware */
5387 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5388 			if (r)
5389 				return r;
5390 		}
5391 
5392 		gfx_v10_0_init_csb(adev);
5393 
5394 		gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5395 
5396 		adev->gfx.rlc.funcs->start(adev);
5397 
5398 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5399 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5400 			if (r)
5401 				return r;
5402 		}
5403 	}
5404 
5405 	return 0;
5406 }
5407 
5408 static struct {
5409 	FIRMWARE_ID	id;
5410 	unsigned int	offset;
5411 	unsigned int	size;
5412 } rlc_autoload_info[FIRMWARE_ID_MAX];
5413 
5414 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5415 {
5416 	int ret;
5417 	RLC_TABLE_OF_CONTENT *rlc_toc;
5418 
5419 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5420 					AMDGPU_GEM_DOMAIN_GTT,
5421 					&adev->gfx.rlc.rlc_toc_bo,
5422 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5423 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5424 	if (ret) {
5425 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5426 		return ret;
5427 	}
5428 
5429 	/* Copy toc from psp sos fw to rlc toc buffer */
5430 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5431 
5432 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5433 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5434 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5435 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5436 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5437 			/* Offset needs 4KB alignment */
5438 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5439 		}
5440 
5441 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5442 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5443 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5444 
5445 		rlc_toc++;
5446 	}
5447 
5448 	return 0;
5449 }
5450 
5451 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5452 {
5453 	uint32_t total_size = 0;
5454 	FIRMWARE_ID id;
5455 	int ret;
5456 
5457 	ret = gfx_v10_0_parse_rlc_toc(adev);
5458 	if (ret) {
5459 		dev_err(adev->dev, "failed to parse rlc toc\n");
5460 		return 0;
5461 	}
5462 
5463 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5464 		total_size += rlc_autoload_info[id].size;
5465 
5466 	/* In case the offset in rlc toc ucode is aligned */
5467 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5468 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5469 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5470 
5471 	return total_size;
5472 }
5473 
5474 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5475 {
5476 	int r;
5477 	uint32_t total_size;
5478 
5479 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5480 
5481 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5482 				      AMDGPU_GEM_DOMAIN_GTT,
5483 				      &adev->gfx.rlc.rlc_autoload_bo,
5484 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5485 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5486 	if (r) {
5487 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5488 		return r;
5489 	}
5490 
5491 	return 0;
5492 }
5493 
5494 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5495 {
5496 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5497 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5498 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5499 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5500 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5501 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5502 }
5503 
5504 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5505 						       FIRMWARE_ID id,
5506 						       const void *fw_data,
5507 						       uint32_t fw_size)
5508 {
5509 	uint32_t toc_offset;
5510 	uint32_t toc_fw_size;
5511 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5512 
5513 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5514 		return;
5515 
5516 	toc_offset = rlc_autoload_info[id].offset;
5517 	toc_fw_size = rlc_autoload_info[id].size;
5518 
5519 	if (fw_size == 0)
5520 		fw_size = toc_fw_size;
5521 
5522 	if (fw_size > toc_fw_size)
5523 		fw_size = toc_fw_size;
5524 
5525 	memcpy(ptr + toc_offset, fw_data, fw_size);
5526 
5527 	if (fw_size < toc_fw_size)
5528 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5529 }
5530 
5531 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5532 {
5533 	void *data;
5534 	uint32_t size;
5535 
5536 	data = adev->gfx.rlc.rlc_toc_buf;
5537 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5538 
5539 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5540 						   FIRMWARE_ID_RLC_TOC,
5541 						   data, size);
5542 }
5543 
5544 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5545 {
5546 	const __le32 *fw_data;
5547 	uint32_t fw_size;
5548 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5549 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5550 
5551 	/* pfp ucode */
5552 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5553 		adev->gfx.pfp_fw->data;
5554 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5555 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5556 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5557 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5558 						   FIRMWARE_ID_CP_PFP,
5559 						   fw_data, fw_size);
5560 
5561 	/* ce ucode */
5562 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5563 		adev->gfx.ce_fw->data;
5564 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5565 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5566 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5567 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5568 						   FIRMWARE_ID_CP_CE,
5569 						   fw_data, fw_size);
5570 
5571 	/* me ucode */
5572 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5573 		adev->gfx.me_fw->data;
5574 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5575 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5576 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5577 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5578 						   FIRMWARE_ID_CP_ME,
5579 						   fw_data, fw_size);
5580 
5581 	/* rlc ucode */
5582 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5583 		adev->gfx.rlc_fw->data;
5584 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5585 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5586 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5587 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5588 						   FIRMWARE_ID_RLC_G_UCODE,
5589 						   fw_data, fw_size);
5590 
5591 	/* mec1 ucode */
5592 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5593 		adev->gfx.mec_fw->data;
5594 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5595 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5596 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5597 		cp_hdr->jt_size * 4;
5598 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5599 						   FIRMWARE_ID_CP_MEC,
5600 						   fw_data, fw_size);
5601 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5602 }
5603 
5604 /* Temporarily put sdma part here */
5605 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5606 {
5607 	const __le32 *fw_data;
5608 	uint32_t fw_size;
5609 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5610 	int i;
5611 
5612 	for (i = 0; i < adev->sdma.num_instances; i++) {
5613 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5614 			adev->sdma.instance[i].fw->data;
5615 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5616 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5617 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5618 
5619 		if (i == 0) {
5620 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5621 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5622 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5623 				FIRMWARE_ID_SDMA0_JT,
5624 				(uint32_t *)fw_data +
5625 				sdma_hdr->jt_offset,
5626 				sdma_hdr->jt_size * 4);
5627 		} else if (i == 1) {
5628 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5629 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5630 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5631 				FIRMWARE_ID_SDMA1_JT,
5632 				(uint32_t *)fw_data +
5633 				sdma_hdr->jt_offset,
5634 				sdma_hdr->jt_size * 4);
5635 		}
5636 	}
5637 }
5638 
5639 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5640 {
5641 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5642 	uint64_t gpu_addr;
5643 
5644 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5645 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5646 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5647 
5648 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5649 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5650 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5651 
5652 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5653 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5654 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5655 
5656 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5657 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5658 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5659 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5660 		return -EINVAL;
5661 	}
5662 
5663 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5664 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5665 		DRM_ERROR("RLC ROM should halt itself\n");
5666 		return -EINVAL;
5667 	}
5668 
5669 	return 0;
5670 }
5671 
5672 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5673 {
5674 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5675 	uint32_t tmp;
5676 	int i;
5677 	uint64_t addr;
5678 
5679 	/* Trigger an invalidation of the L1 instruction caches */
5680 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5681 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5682 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5683 
5684 	/* Wait for invalidation complete */
5685 	for (i = 0; i < usec_timeout; i++) {
5686 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5687 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5688 			INVALIDATE_CACHE_COMPLETE))
5689 			break;
5690 		udelay(1);
5691 	}
5692 
5693 	if (i >= usec_timeout) {
5694 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5695 		return -EINVAL;
5696 	}
5697 
5698 	/* Program me ucode address into intruction cache address register */
5699 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5700 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5701 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5702 			lower_32_bits(addr) & 0xFFFFF000);
5703 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5704 			upper_32_bits(addr));
5705 
5706 	return 0;
5707 }
5708 
5709 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5710 {
5711 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5712 	uint32_t tmp;
5713 	int i;
5714 	uint64_t addr;
5715 
5716 	/* Trigger an invalidation of the L1 instruction caches */
5717 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5718 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5719 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5720 
5721 	/* Wait for invalidation complete */
5722 	for (i = 0; i < usec_timeout; i++) {
5723 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5724 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5725 			INVALIDATE_CACHE_COMPLETE))
5726 			break;
5727 		udelay(1);
5728 	}
5729 
5730 	if (i >= usec_timeout) {
5731 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5732 		return -EINVAL;
5733 	}
5734 
5735 	/* Program ce ucode address into intruction cache address register */
5736 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5737 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5738 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5739 			lower_32_bits(addr) & 0xFFFFF000);
5740 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5741 			upper_32_bits(addr));
5742 
5743 	return 0;
5744 }
5745 
5746 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5747 {
5748 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5749 	uint32_t tmp;
5750 	int i;
5751 	uint64_t addr;
5752 
5753 	/* Trigger an invalidation of the L1 instruction caches */
5754 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5755 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5756 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5757 
5758 	/* Wait for invalidation complete */
5759 	for (i = 0; i < usec_timeout; i++) {
5760 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5761 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5762 			INVALIDATE_CACHE_COMPLETE))
5763 			break;
5764 		udelay(1);
5765 	}
5766 
5767 	if (i >= usec_timeout) {
5768 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5769 		return -EINVAL;
5770 	}
5771 
5772 	/* Program pfp ucode address into intruction cache address register */
5773 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5774 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5775 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5776 			lower_32_bits(addr) & 0xFFFFF000);
5777 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5778 			upper_32_bits(addr));
5779 
5780 	return 0;
5781 }
5782 
5783 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5784 {
5785 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5786 	uint32_t tmp;
5787 	int i;
5788 	uint64_t addr;
5789 
5790 	/* Trigger an invalidation of the L1 instruction caches */
5791 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5792 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5793 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5794 
5795 	/* Wait for invalidation complete */
5796 	for (i = 0; i < usec_timeout; i++) {
5797 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5798 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5799 			INVALIDATE_CACHE_COMPLETE))
5800 			break;
5801 		udelay(1);
5802 	}
5803 
5804 	if (i >= usec_timeout) {
5805 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5806 		return -EINVAL;
5807 	}
5808 
5809 	/* Program mec1 ucode address into intruction cache address register */
5810 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5811 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5812 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5813 			lower_32_bits(addr) & 0xFFFFF000);
5814 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5815 			upper_32_bits(addr));
5816 
5817 	return 0;
5818 }
5819 
5820 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5821 {
5822 	uint32_t cp_status;
5823 	uint32_t bootload_status;
5824 	int i, r;
5825 
5826 	for (i = 0; i < adev->usec_timeout; i++) {
5827 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5828 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5829 		if ((cp_status == 0) &&
5830 		    (REG_GET_FIELD(bootload_status,
5831 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5832 			break;
5833 		}
5834 		udelay(1);
5835 	}
5836 
5837 	if (i >= adev->usec_timeout) {
5838 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5839 		return -ETIMEDOUT;
5840 	}
5841 
5842 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5843 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5844 		if (r)
5845 			return r;
5846 
5847 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5848 		if (r)
5849 			return r;
5850 
5851 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5852 		if (r)
5853 			return r;
5854 
5855 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5856 		if (r)
5857 			return r;
5858 	}
5859 
5860 	return 0;
5861 }
5862 
5863 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5864 {
5865 	int i;
5866 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5867 
5868 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5869 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5870 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5871 
5872 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5873 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5874 	else
5875 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5876 
5877 	if (adev->job_hang && !enable)
5878 		return 0;
5879 
5880 	for (i = 0; i < adev->usec_timeout; i++) {
5881 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5882 			break;
5883 		udelay(1);
5884 	}
5885 
5886 	if (i >= adev->usec_timeout)
5887 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5888 
5889 	return 0;
5890 }
5891 
5892 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5893 {
5894 	int r;
5895 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
5896 	const __le32 *fw_data;
5897 	unsigned int i, fw_size;
5898 	uint32_t tmp;
5899 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5900 
5901 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5902 		adev->gfx.pfp_fw->data;
5903 
5904 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5905 
5906 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5907 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5908 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5909 
5910 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5911 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5912 				      &adev->gfx.pfp.pfp_fw_obj,
5913 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
5914 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
5915 	if (r) {
5916 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5917 		gfx_v10_0_pfp_fini(adev);
5918 		return r;
5919 	}
5920 
5921 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5922 
5923 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5924 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5925 
5926 	/* Trigger an invalidation of the L1 instruction caches */
5927 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5928 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5929 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5930 
5931 	/* Wait for invalidation complete */
5932 	for (i = 0; i < usec_timeout; i++) {
5933 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5934 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5935 			INVALIDATE_CACHE_COMPLETE))
5936 			break;
5937 		udelay(1);
5938 	}
5939 
5940 	if (i >= usec_timeout) {
5941 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5942 		return -EINVAL;
5943 	}
5944 
5945 	if (amdgpu_emu_mode == 1)
5946 		adev->hdp.funcs->flush_hdp(adev, NULL);
5947 
5948 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5949 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5950 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5951 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5952 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5953 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5954 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5955 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5956 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5957 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5958 
5959 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5960 
5961 	for (i = 0; i < pfp_hdr->jt_size; i++)
5962 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5963 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5964 
5965 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5966 
5967 	return 0;
5968 }
5969 
5970 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5971 {
5972 	int r;
5973 	const struct gfx_firmware_header_v1_0 *ce_hdr;
5974 	const __le32 *fw_data;
5975 	unsigned int i, fw_size;
5976 	uint32_t tmp;
5977 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5978 
5979 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5980 		adev->gfx.ce_fw->data;
5981 
5982 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5983 
5984 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5985 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5986 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5987 
5988 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5989 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5990 				      &adev->gfx.ce.ce_fw_obj,
5991 				      &adev->gfx.ce.ce_fw_gpu_addr,
5992 				      (void **)&adev->gfx.ce.ce_fw_ptr);
5993 	if (r) {
5994 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5995 		gfx_v10_0_ce_fini(adev);
5996 		return r;
5997 	}
5998 
5999 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6000 
6001 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6002 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6003 
6004 	/* Trigger an invalidation of the L1 instruction caches */
6005 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6006 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6007 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6008 
6009 	/* Wait for invalidation complete */
6010 	for (i = 0; i < usec_timeout; i++) {
6011 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6012 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6013 			INVALIDATE_CACHE_COMPLETE))
6014 			break;
6015 		udelay(1);
6016 	}
6017 
6018 	if (i >= usec_timeout) {
6019 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6020 		return -EINVAL;
6021 	}
6022 
6023 	if (amdgpu_emu_mode == 1)
6024 		adev->hdp.funcs->flush_hdp(adev, NULL);
6025 
6026 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6027 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6028 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6029 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6030 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6031 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6032 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6033 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6034 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6035 
6036 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6037 
6038 	for (i = 0; i < ce_hdr->jt_size; i++)
6039 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6040 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6041 
6042 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6043 
6044 	return 0;
6045 }
6046 
6047 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6048 {
6049 	int r;
6050 	const struct gfx_firmware_header_v1_0 *me_hdr;
6051 	const __le32 *fw_data;
6052 	unsigned int i, fw_size;
6053 	uint32_t tmp;
6054 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6055 
6056 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
6057 		adev->gfx.me_fw->data;
6058 
6059 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6060 
6061 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6062 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6063 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6064 
6065 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6066 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6067 				      &adev->gfx.me.me_fw_obj,
6068 				      &adev->gfx.me.me_fw_gpu_addr,
6069 				      (void **)&adev->gfx.me.me_fw_ptr);
6070 	if (r) {
6071 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6072 		gfx_v10_0_me_fini(adev);
6073 		return r;
6074 	}
6075 
6076 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6077 
6078 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6079 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6080 
6081 	/* Trigger an invalidation of the L1 instruction caches */
6082 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6083 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6084 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6085 
6086 	/* Wait for invalidation complete */
6087 	for (i = 0; i < usec_timeout; i++) {
6088 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6089 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6090 			INVALIDATE_CACHE_COMPLETE))
6091 			break;
6092 		udelay(1);
6093 	}
6094 
6095 	if (i >= usec_timeout) {
6096 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6097 		return -EINVAL;
6098 	}
6099 
6100 	if (amdgpu_emu_mode == 1)
6101 		adev->hdp.funcs->flush_hdp(adev, NULL);
6102 
6103 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6104 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6105 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6106 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6107 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6108 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6109 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6110 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6111 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6112 
6113 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6114 
6115 	for (i = 0; i < me_hdr->jt_size; i++)
6116 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6117 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6118 
6119 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6120 
6121 	return 0;
6122 }
6123 
6124 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6125 {
6126 	int r;
6127 
6128 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6129 		return -EINVAL;
6130 
6131 	gfx_v10_0_cp_gfx_enable(adev, false);
6132 
6133 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6134 	if (r) {
6135 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6136 		return r;
6137 	}
6138 
6139 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6140 	if (r) {
6141 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6142 		return r;
6143 	}
6144 
6145 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6146 	if (r) {
6147 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6148 		return r;
6149 	}
6150 
6151 	return 0;
6152 }
6153 
6154 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6155 {
6156 	struct amdgpu_ring *ring;
6157 	const struct cs_section_def *sect = NULL;
6158 	const struct cs_extent_def *ext = NULL;
6159 	int r, i;
6160 	int ctx_reg_offset;
6161 
6162 	/* init the CP */
6163 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6164 		     adev->gfx.config.max_hw_contexts - 1);
6165 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6166 
6167 	gfx_v10_0_cp_gfx_enable(adev, true);
6168 
6169 	ring = &adev->gfx.gfx_ring[0];
6170 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6171 	if (r) {
6172 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6173 		return r;
6174 	}
6175 
6176 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6177 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6178 
6179 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6180 	amdgpu_ring_write(ring, 0x80000000);
6181 	amdgpu_ring_write(ring, 0x80000000);
6182 
6183 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6184 		for (ext = sect->section; ext->extent != NULL; ++ext) {
6185 			if (sect->id == SECT_CONTEXT) {
6186 				amdgpu_ring_write(ring,
6187 						  PACKET3(PACKET3_SET_CONTEXT_REG,
6188 							  ext->reg_count));
6189 				amdgpu_ring_write(ring, ext->reg_index -
6190 						  PACKET3_SET_CONTEXT_REG_START);
6191 				for (i = 0; i < ext->reg_count; i++)
6192 					amdgpu_ring_write(ring, ext->extent[i]);
6193 			}
6194 		}
6195 	}
6196 
6197 	ctx_reg_offset =
6198 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6199 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6200 	amdgpu_ring_write(ring, ctx_reg_offset);
6201 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6202 
6203 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6204 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6205 
6206 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6207 	amdgpu_ring_write(ring, 0);
6208 
6209 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6210 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6211 	amdgpu_ring_write(ring, 0x8000);
6212 	amdgpu_ring_write(ring, 0x8000);
6213 
6214 	amdgpu_ring_commit(ring);
6215 
6216 	/* submit cs packet to copy state 0 to next available state */
6217 	if (adev->gfx.num_gfx_rings > 1) {
6218 		/* maximum supported gfx ring is 2 */
6219 		ring = &adev->gfx.gfx_ring[1];
6220 		r = amdgpu_ring_alloc(ring, 2);
6221 		if (r) {
6222 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6223 			return r;
6224 		}
6225 
6226 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6227 		amdgpu_ring_write(ring, 0);
6228 
6229 		amdgpu_ring_commit(ring);
6230 	}
6231 	return 0;
6232 }
6233 
6234 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6235 					 CP_PIPE_ID pipe)
6236 {
6237 	u32 tmp;
6238 
6239 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6240 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6241 
6242 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6243 }
6244 
6245 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6246 					  struct amdgpu_ring *ring)
6247 {
6248 	u32 tmp;
6249 
6250 	if (!amdgpu_async_gfx_ring) {
6251 		tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6252 		if (ring->use_doorbell) {
6253 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6254 						DOORBELL_OFFSET, ring->doorbell_index);
6255 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6256 						DOORBELL_EN, 1);
6257 		} else {
6258 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6259 						DOORBELL_EN, 0);
6260 		}
6261 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6262 	}
6263 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6264 	case IP_VERSION(10, 3, 0):
6265 	case IP_VERSION(10, 3, 2):
6266 	case IP_VERSION(10, 3, 1):
6267 	case IP_VERSION(10, 3, 4):
6268 	case IP_VERSION(10, 3, 5):
6269 	case IP_VERSION(10, 3, 6):
6270 	case IP_VERSION(10, 3, 3):
6271 	case IP_VERSION(10, 3, 7):
6272 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6273 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6274 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6275 
6276 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6277 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6278 		break;
6279 	default:
6280 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6281 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
6282 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6283 
6284 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6285 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6286 		break;
6287 	}
6288 }
6289 
6290 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6291 {
6292 	struct amdgpu_ring *ring;
6293 	u32 tmp;
6294 	u32 rb_bufsz;
6295 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
6296 
6297 	/* Set the write pointer delay */
6298 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6299 
6300 	/* set the RB to use vmid 0 */
6301 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6302 
6303 	/* Init gfx ring 0 for pipe 0 */
6304 	mutex_lock(&adev->srbm_mutex);
6305 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6306 
6307 	/* Set ring buffer size */
6308 	ring = &adev->gfx.gfx_ring[0];
6309 	rb_bufsz = order_base_2(ring->ring_size / 8);
6310 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6311 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6312 #ifdef __BIG_ENDIAN
6313 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6314 #endif
6315 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6316 
6317 	/* Initialize the ring buffer's write pointers */
6318 	ring->wptr = 0;
6319 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6320 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6321 
6322 	/* set the wb address wether it's enabled or not */
6323 	rptr_addr = ring->rptr_gpu_addr;
6324 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6325 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6326 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6327 
6328 	wptr_gpu_addr = ring->wptr_gpu_addr;
6329 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6330 		     lower_32_bits(wptr_gpu_addr));
6331 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6332 		     upper_32_bits(wptr_gpu_addr));
6333 
6334 	mdelay(1);
6335 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6336 
6337 	rb_addr = ring->gpu_addr >> 8;
6338 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6339 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6340 
6341 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6342 
6343 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6344 	mutex_unlock(&adev->srbm_mutex);
6345 
6346 	/* Init gfx ring 1 for pipe 1 */
6347 	if (adev->gfx.num_gfx_rings > 1) {
6348 		mutex_lock(&adev->srbm_mutex);
6349 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6350 		/* maximum supported gfx ring is 2 */
6351 		ring = &adev->gfx.gfx_ring[1];
6352 		rb_bufsz = order_base_2(ring->ring_size / 8);
6353 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6354 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6355 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6356 		/* Initialize the ring buffer's write pointers */
6357 		ring->wptr = 0;
6358 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6359 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6360 		/* Set the wb address wether it's enabled or not */
6361 		rptr_addr = ring->rptr_gpu_addr;
6362 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6363 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6364 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6365 		wptr_gpu_addr = ring->wptr_gpu_addr;
6366 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6367 			     lower_32_bits(wptr_gpu_addr));
6368 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6369 			     upper_32_bits(wptr_gpu_addr));
6370 
6371 		mdelay(1);
6372 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6373 
6374 		rb_addr = ring->gpu_addr >> 8;
6375 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6376 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6377 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6378 
6379 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6380 		mutex_unlock(&adev->srbm_mutex);
6381 	}
6382 	/* Switch to pipe 0 */
6383 	mutex_lock(&adev->srbm_mutex);
6384 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6385 	mutex_unlock(&adev->srbm_mutex);
6386 
6387 	/* start the ring */
6388 	gfx_v10_0_cp_gfx_start(adev);
6389 
6390 	return 0;
6391 }
6392 
6393 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6394 {
6395 	if (enable) {
6396 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6397 		case IP_VERSION(10, 3, 0):
6398 		case IP_VERSION(10, 3, 2):
6399 		case IP_VERSION(10, 3, 1):
6400 		case IP_VERSION(10, 3, 4):
6401 		case IP_VERSION(10, 3, 5):
6402 		case IP_VERSION(10, 3, 6):
6403 		case IP_VERSION(10, 3, 3):
6404 		case IP_VERSION(10, 3, 7):
6405 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6406 			break;
6407 		default:
6408 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6409 			break;
6410 		}
6411 	} else {
6412 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6413 		case IP_VERSION(10, 3, 0):
6414 		case IP_VERSION(10, 3, 2):
6415 		case IP_VERSION(10, 3, 1):
6416 		case IP_VERSION(10, 3, 4):
6417 		case IP_VERSION(10, 3, 5):
6418 		case IP_VERSION(10, 3, 6):
6419 		case IP_VERSION(10, 3, 3):
6420 		case IP_VERSION(10, 3, 7):
6421 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6422 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6423 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6424 			break;
6425 		default:
6426 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6427 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6428 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6429 			break;
6430 		}
6431 		adev->gfx.kiq[0].ring.sched.ready = false;
6432 	}
6433 	udelay(50);
6434 }
6435 
6436 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6437 {
6438 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6439 	const __le32 *fw_data;
6440 	unsigned int i;
6441 	u32 tmp;
6442 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6443 
6444 	if (!adev->gfx.mec_fw)
6445 		return -EINVAL;
6446 
6447 	gfx_v10_0_cp_compute_enable(adev, false);
6448 
6449 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6450 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6451 
6452 	fw_data = (const __le32 *)
6453 		(adev->gfx.mec_fw->data +
6454 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6455 
6456 	/* Trigger an invalidation of the L1 instruction caches */
6457 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6458 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6459 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6460 
6461 	/* Wait for invalidation complete */
6462 	for (i = 0; i < usec_timeout; i++) {
6463 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6464 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6465 				       INVALIDATE_CACHE_COMPLETE))
6466 			break;
6467 		udelay(1);
6468 	}
6469 
6470 	if (i >= usec_timeout) {
6471 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6472 		return -EINVAL;
6473 	}
6474 
6475 	if (amdgpu_emu_mode == 1)
6476 		adev->hdp.funcs->flush_hdp(adev, NULL);
6477 
6478 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6479 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6480 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6481 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6482 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6483 
6484 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6485 		     0xFFFFF000);
6486 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6487 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6488 
6489 	/* MEC1 */
6490 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6491 
6492 	for (i = 0; i < mec_hdr->jt_size; i++)
6493 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6494 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6495 
6496 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6497 
6498 	/*
6499 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6500 	 * different microcode than MEC1.
6501 	 */
6502 
6503 	return 0;
6504 }
6505 
6506 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6507 {
6508 	uint32_t tmp;
6509 	struct amdgpu_device *adev = ring->adev;
6510 
6511 	/* tell RLC which is KIQ queue */
6512 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6513 	case IP_VERSION(10, 3, 0):
6514 	case IP_VERSION(10, 3, 2):
6515 	case IP_VERSION(10, 3, 1):
6516 	case IP_VERSION(10, 3, 4):
6517 	case IP_VERSION(10, 3, 5):
6518 	case IP_VERSION(10, 3, 6):
6519 	case IP_VERSION(10, 3, 3):
6520 	case IP_VERSION(10, 3, 7):
6521 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6522 		tmp &= 0xffffff00;
6523 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6524 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6525 		tmp |= 0x80;
6526 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6527 		break;
6528 	default:
6529 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6530 		tmp &= 0xffffff00;
6531 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6532 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6533 		tmp |= 0x80;
6534 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6535 		break;
6536 	}
6537 }
6538 
6539 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6540 					   struct v10_gfx_mqd *mqd,
6541 					   struct amdgpu_mqd_prop *prop)
6542 {
6543 	bool priority = 0;
6544 	u32 tmp;
6545 
6546 	/* set up default queue priority level
6547 	 * 0x0 = low priority, 0x1 = high priority
6548 	 */
6549 	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6550 		priority = 1;
6551 
6552 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6553 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6554 	mqd->cp_gfx_hqd_queue_priority = tmp;
6555 }
6556 
6557 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6558 				  struct amdgpu_mqd_prop *prop)
6559 {
6560 	struct v10_gfx_mqd *mqd = m;
6561 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6562 	uint32_t tmp;
6563 	uint32_t rb_bufsz;
6564 
6565 	/* set up gfx hqd wptr */
6566 	mqd->cp_gfx_hqd_wptr = 0;
6567 	mqd->cp_gfx_hqd_wptr_hi = 0;
6568 
6569 	/* set the pointer to the MQD */
6570 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6571 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6572 
6573 	/* set up mqd control */
6574 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6575 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6576 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6577 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6578 	mqd->cp_gfx_mqd_control = tmp;
6579 
6580 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6581 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6582 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6583 	mqd->cp_gfx_hqd_vmid = 0;
6584 
6585 	/* set up gfx queue priority */
6586 	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6587 
6588 	/* set up time quantum */
6589 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6590 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6591 	mqd->cp_gfx_hqd_quantum = tmp;
6592 
6593 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6594 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6595 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6596 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6597 
6598 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6599 	wb_gpu_addr = prop->rptr_gpu_addr;
6600 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6601 	mqd->cp_gfx_hqd_rptr_addr_hi =
6602 		upper_32_bits(wb_gpu_addr) & 0xffff;
6603 
6604 	/* set up rb_wptr_poll addr */
6605 	wb_gpu_addr = prop->wptr_gpu_addr;
6606 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6607 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6608 
6609 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6610 	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6611 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6612 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6613 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6614 #ifdef __BIG_ENDIAN
6615 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6616 #endif
6617 	mqd->cp_gfx_hqd_cntl = tmp;
6618 
6619 	/* set up cp_doorbell_control */
6620 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6621 	if (prop->use_doorbell) {
6622 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6623 				    DOORBELL_OFFSET, prop->doorbell_index);
6624 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6625 				    DOORBELL_EN, 1);
6626 	} else
6627 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6628 				    DOORBELL_EN, 0);
6629 	mqd->cp_rb_doorbell_control = tmp;
6630 
6631 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6632 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6633 
6634 	/* active the queue */
6635 	mqd->cp_gfx_hqd_active = 1;
6636 
6637 	return 0;
6638 }
6639 
6640 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6641 {
6642 	struct amdgpu_device *adev = ring->adev;
6643 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6644 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6645 
6646 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6647 		memset((void *)mqd, 0, sizeof(*mqd));
6648 		mutex_lock(&adev->srbm_mutex);
6649 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6650 		amdgpu_ring_init_mqd(ring);
6651 
6652 		/*
6653 		 * if there are 2 gfx rings, set the lower doorbell
6654 		 * range of the first ring, otherwise the range of
6655 		 * the second ring will override the first ring
6656 		 */
6657 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6658 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6659 
6660 		nv_grbm_select(adev, 0, 0, 0, 0);
6661 		mutex_unlock(&adev->srbm_mutex);
6662 		if (adev->gfx.me.mqd_backup[mqd_idx])
6663 			memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6664 	} else {
6665 		mutex_lock(&adev->srbm_mutex);
6666 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6667 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6668 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6669 
6670 		nv_grbm_select(adev, 0, 0, 0, 0);
6671 		mutex_unlock(&adev->srbm_mutex);
6672 		/* restore mqd with the backup copy */
6673 		if (adev->gfx.me.mqd_backup[mqd_idx])
6674 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6675 		/* reset the ring */
6676 		ring->wptr = 0;
6677 		*ring->wptr_cpu_addr = 0;
6678 		amdgpu_ring_clear_ring(ring);
6679 	}
6680 
6681 	return 0;
6682 }
6683 
6684 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6685 {
6686 	int r, i;
6687 	struct amdgpu_ring *ring;
6688 
6689 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6690 		ring = &adev->gfx.gfx_ring[i];
6691 
6692 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6693 		if (unlikely(r != 0))
6694 			return r;
6695 
6696 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6697 		if (!r) {
6698 			r = gfx_v10_0_gfx_init_queue(ring);
6699 			amdgpu_bo_kunmap(ring->mqd_obj);
6700 			ring->mqd_ptr = NULL;
6701 		}
6702 		amdgpu_bo_unreserve(ring->mqd_obj);
6703 		if (r)
6704 			return r;
6705 	}
6706 
6707 	r = amdgpu_gfx_enable_kgq(adev, 0);
6708 	if (r)
6709 		return r;
6710 
6711 	return gfx_v10_0_cp_gfx_start(adev);
6712 }
6713 
6714 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6715 				      struct amdgpu_mqd_prop *prop)
6716 {
6717 	struct v10_compute_mqd *mqd = m;
6718 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6719 	uint32_t tmp;
6720 
6721 	mqd->header = 0xC0310800;
6722 	mqd->compute_pipelinestat_enable = 0x00000001;
6723 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6724 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6725 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6726 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6727 	mqd->compute_misc_reserved = 0x00000003;
6728 
6729 	eop_base_addr = prop->eop_gpu_addr >> 8;
6730 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6731 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6732 
6733 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6734 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6735 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6736 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6737 
6738 	mqd->cp_hqd_eop_control = tmp;
6739 
6740 	/* enable doorbell? */
6741 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6742 
6743 	if (prop->use_doorbell) {
6744 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6745 				    DOORBELL_OFFSET, prop->doorbell_index);
6746 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6747 				    DOORBELL_EN, 1);
6748 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6749 				    DOORBELL_SOURCE, 0);
6750 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6751 				    DOORBELL_HIT, 0);
6752 	} else {
6753 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6754 				    DOORBELL_EN, 0);
6755 	}
6756 
6757 	mqd->cp_hqd_pq_doorbell_control = tmp;
6758 
6759 	/* disable the queue if it's active */
6760 	mqd->cp_hqd_dequeue_request = 0;
6761 	mqd->cp_hqd_pq_rptr = 0;
6762 	mqd->cp_hqd_pq_wptr_lo = 0;
6763 	mqd->cp_hqd_pq_wptr_hi = 0;
6764 
6765 	/* set the pointer to the MQD */
6766 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6767 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6768 
6769 	/* set MQD vmid to 0 */
6770 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6771 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6772 	mqd->cp_mqd_control = tmp;
6773 
6774 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6775 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6776 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6777 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6778 
6779 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6780 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6781 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6782 			    (order_base_2(prop->queue_size / 4) - 1));
6783 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6784 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6785 #ifdef __BIG_ENDIAN
6786 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6787 #endif
6788 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6789 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6790 			    prop->allow_tunneling);
6791 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6792 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6793 	mqd->cp_hqd_pq_control = tmp;
6794 
6795 	/* set the wb address whether it's enabled or not */
6796 	wb_gpu_addr = prop->rptr_gpu_addr;
6797 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6798 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6799 		upper_32_bits(wb_gpu_addr) & 0xffff;
6800 
6801 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6802 	wb_gpu_addr = prop->wptr_gpu_addr;
6803 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6804 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6805 
6806 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6807 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6808 
6809 	/* set the vmid for the queue */
6810 	mqd->cp_hqd_vmid = 0;
6811 
6812 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6813 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6814 	mqd->cp_hqd_persistent_state = tmp;
6815 
6816 	/* set MIN_IB_AVAIL_SIZE */
6817 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6818 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6819 	mqd->cp_hqd_ib_control = tmp;
6820 
6821 	/* set static priority for a compute queue/ring */
6822 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6823 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6824 
6825 	mqd->cp_hqd_active = prop->hqd_active;
6826 
6827 	return 0;
6828 }
6829 
6830 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6831 {
6832 	struct amdgpu_device *adev = ring->adev;
6833 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6834 	int j;
6835 
6836 	/* inactivate the queue */
6837 	if (amdgpu_sriov_vf(adev))
6838 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6839 
6840 	/* disable wptr polling */
6841 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6842 
6843 	/* disable the queue if it's active */
6844 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6845 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6846 		for (j = 0; j < adev->usec_timeout; j++) {
6847 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6848 				break;
6849 			udelay(1);
6850 		}
6851 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6852 		       mqd->cp_hqd_dequeue_request);
6853 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6854 		       mqd->cp_hqd_pq_rptr);
6855 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6856 		       mqd->cp_hqd_pq_wptr_lo);
6857 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6858 		       mqd->cp_hqd_pq_wptr_hi);
6859 	}
6860 
6861 	/* disable doorbells */
6862 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6863 
6864 	/* write the EOP addr */
6865 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6866 	       mqd->cp_hqd_eop_base_addr_lo);
6867 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6868 	       mqd->cp_hqd_eop_base_addr_hi);
6869 
6870 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6871 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6872 	       mqd->cp_hqd_eop_control);
6873 
6874 	/* set the pointer to the MQD */
6875 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6876 	       mqd->cp_mqd_base_addr_lo);
6877 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6878 	       mqd->cp_mqd_base_addr_hi);
6879 
6880 	/* set MQD vmid to 0 */
6881 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6882 	       mqd->cp_mqd_control);
6883 
6884 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6885 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6886 	       mqd->cp_hqd_pq_base_lo);
6887 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6888 	       mqd->cp_hqd_pq_base_hi);
6889 
6890 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6891 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6892 	       mqd->cp_hqd_pq_control);
6893 
6894 	/* set the wb address whether it's enabled or not */
6895 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6896 		mqd->cp_hqd_pq_rptr_report_addr_lo);
6897 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6898 		mqd->cp_hqd_pq_rptr_report_addr_hi);
6899 
6900 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6901 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6902 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
6903 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6904 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
6905 
6906 	/* enable the doorbell if requested */
6907 	if (ring->use_doorbell) {
6908 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6909 			(adev->doorbell_index.kiq * 2) << 2);
6910 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6911 			(adev->doorbell_index.userqueue_end * 2) << 2);
6912 	}
6913 
6914 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6915 	       mqd->cp_hqd_pq_doorbell_control);
6916 
6917 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6918 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6919 	       mqd->cp_hqd_pq_wptr_lo);
6920 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6921 	       mqd->cp_hqd_pq_wptr_hi);
6922 
6923 	/* set the vmid for the queue */
6924 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6925 
6926 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6927 	       mqd->cp_hqd_persistent_state);
6928 
6929 	/* activate the queue */
6930 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6931 	       mqd->cp_hqd_active);
6932 
6933 	if (ring->use_doorbell)
6934 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6935 
6936 	return 0;
6937 }
6938 
6939 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6940 {
6941 	struct amdgpu_device *adev = ring->adev;
6942 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6943 
6944 	gfx_v10_0_kiq_setting(ring);
6945 
6946 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6947 		/* reset MQD to a clean status */
6948 		if (adev->gfx.kiq[0].mqd_backup)
6949 			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6950 
6951 		/* reset ring buffer */
6952 		ring->wptr = 0;
6953 		amdgpu_ring_clear_ring(ring);
6954 
6955 		mutex_lock(&adev->srbm_mutex);
6956 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6957 		gfx_v10_0_kiq_init_register(ring);
6958 		nv_grbm_select(adev, 0, 0, 0, 0);
6959 		mutex_unlock(&adev->srbm_mutex);
6960 	} else {
6961 		memset((void *)mqd, 0, sizeof(*mqd));
6962 		if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6963 			amdgpu_ring_clear_ring(ring);
6964 		mutex_lock(&adev->srbm_mutex);
6965 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6966 		amdgpu_ring_init_mqd(ring);
6967 		gfx_v10_0_kiq_init_register(ring);
6968 		nv_grbm_select(adev, 0, 0, 0, 0);
6969 		mutex_unlock(&adev->srbm_mutex);
6970 
6971 		if (adev->gfx.kiq[0].mqd_backup)
6972 			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6973 	}
6974 
6975 	return 0;
6976 }
6977 
6978 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6979 {
6980 	struct amdgpu_device *adev = ring->adev;
6981 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6982 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
6983 
6984 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6985 		memset((void *)mqd, 0, sizeof(*mqd));
6986 		mutex_lock(&adev->srbm_mutex);
6987 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6988 		amdgpu_ring_init_mqd(ring);
6989 		nv_grbm_select(adev, 0, 0, 0, 0);
6990 		mutex_unlock(&adev->srbm_mutex);
6991 
6992 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6993 			memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6994 	} else {
6995 		/* restore MQD to a clean status */
6996 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6997 			memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6998 		/* reset ring buffer */
6999 		ring->wptr = 0;
7000 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7001 		amdgpu_ring_clear_ring(ring);
7002 	}
7003 
7004 	return 0;
7005 }
7006 
7007 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7008 {
7009 	struct amdgpu_ring *ring;
7010 	int r;
7011 
7012 	ring = &adev->gfx.kiq[0].ring;
7013 
7014 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
7015 	if (unlikely(r != 0))
7016 		return r;
7017 
7018 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7019 	if (unlikely(r != 0)) {
7020 		amdgpu_bo_unreserve(ring->mqd_obj);
7021 		return r;
7022 	}
7023 
7024 	gfx_v10_0_kiq_init_queue(ring);
7025 	amdgpu_bo_kunmap(ring->mqd_obj);
7026 	ring->mqd_ptr = NULL;
7027 	amdgpu_bo_unreserve(ring->mqd_obj);
7028 	return 0;
7029 }
7030 
7031 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7032 {
7033 	struct amdgpu_ring *ring = NULL;
7034 	int r = 0, i;
7035 
7036 	gfx_v10_0_cp_compute_enable(adev, true);
7037 
7038 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7039 		ring = &adev->gfx.compute_ring[i];
7040 
7041 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
7042 		if (unlikely(r != 0))
7043 			goto done;
7044 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7045 		if (!r) {
7046 			r = gfx_v10_0_kcq_init_queue(ring);
7047 			amdgpu_bo_kunmap(ring->mqd_obj);
7048 			ring->mqd_ptr = NULL;
7049 		}
7050 		amdgpu_bo_unreserve(ring->mqd_obj);
7051 		if (r)
7052 			goto done;
7053 	}
7054 
7055 	r = amdgpu_gfx_enable_kcq(adev, 0);
7056 done:
7057 	return r;
7058 }
7059 
7060 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7061 {
7062 	int r, i;
7063 	struct amdgpu_ring *ring;
7064 
7065 	if (!(adev->flags & AMD_IS_APU))
7066 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7067 
7068 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7069 		/* legacy firmware loading */
7070 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
7071 		if (r)
7072 			return r;
7073 
7074 		r = gfx_v10_0_cp_compute_load_microcode(adev);
7075 		if (r)
7076 			return r;
7077 	}
7078 
7079 	r = gfx_v10_0_kiq_resume(adev);
7080 	if (r)
7081 		return r;
7082 
7083 	r = gfx_v10_0_kcq_resume(adev);
7084 	if (r)
7085 		return r;
7086 
7087 	if (!amdgpu_async_gfx_ring) {
7088 		r = gfx_v10_0_cp_gfx_resume(adev);
7089 		if (r)
7090 			return r;
7091 	} else {
7092 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7093 		if (r)
7094 			return r;
7095 	}
7096 
7097 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7098 		ring = &adev->gfx.gfx_ring[i];
7099 		r = amdgpu_ring_test_helper(ring);
7100 		if (r)
7101 			return r;
7102 	}
7103 
7104 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7105 		ring = &adev->gfx.compute_ring[i];
7106 		r = amdgpu_ring_test_helper(ring);
7107 		if (r)
7108 			return r;
7109 	}
7110 
7111 	return 0;
7112 }
7113 
7114 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7115 {
7116 	gfx_v10_0_cp_gfx_enable(adev, enable);
7117 	gfx_v10_0_cp_compute_enable(adev, enable);
7118 }
7119 
7120 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7121 {
7122 	uint32_t data, pattern = 0xDEADBEEF;
7123 
7124 	/*
7125 	 * check if mmVGT_ESGS_RING_SIZE_UMD
7126 	 * has been remapped to mmVGT_ESGS_RING_SIZE
7127 	 */
7128 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7129 	case IP_VERSION(10, 3, 0):
7130 	case IP_VERSION(10, 3, 2):
7131 	case IP_VERSION(10, 3, 4):
7132 	case IP_VERSION(10, 3, 5):
7133 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7134 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7135 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7136 
7137 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7138 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7139 			return true;
7140 		}
7141 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7142 		break;
7143 	case IP_VERSION(10, 3, 1):
7144 	case IP_VERSION(10, 3, 3):
7145 	case IP_VERSION(10, 3, 6):
7146 	case IP_VERSION(10, 3, 7):
7147 		return true;
7148 	default:
7149 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7150 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7151 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7152 
7153 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7154 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7155 			return true;
7156 		}
7157 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7158 		break;
7159 	}
7160 
7161 	return false;
7162 }
7163 
7164 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7165 {
7166 	uint32_t data;
7167 
7168 	if (amdgpu_sriov_vf(adev))
7169 		return;
7170 
7171 	/*
7172 	 * Initialize cam_index to 0
7173 	 * index will auto-inc after each data writing
7174 	 */
7175 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7176 
7177 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7178 	case IP_VERSION(10, 3, 0):
7179 	case IP_VERSION(10, 3, 2):
7180 	case IP_VERSION(10, 3, 1):
7181 	case IP_VERSION(10, 3, 4):
7182 	case IP_VERSION(10, 3, 5):
7183 	case IP_VERSION(10, 3, 6):
7184 	case IP_VERSION(10, 3, 3):
7185 	case IP_VERSION(10, 3, 7):
7186 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7187 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7188 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7189 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7190 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7191 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7192 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7193 
7194 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7195 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7196 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7197 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7198 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7199 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7200 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7201 
7202 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7203 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7204 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7205 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7206 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7207 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7208 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7209 
7210 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7211 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7212 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7213 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7214 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7215 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7216 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7217 
7218 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7219 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7220 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7221 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7222 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7223 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7224 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7225 
7226 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7227 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7228 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7229 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7230 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7231 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7232 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7233 
7234 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7235 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7236 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7237 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7238 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7239 		break;
7240 	default:
7241 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7242 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7243 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7244 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7245 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7246 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7247 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7248 
7249 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7250 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7251 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7252 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7253 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7254 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7255 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7256 
7257 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7258 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7259 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7260 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7261 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7262 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7263 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7264 
7265 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7266 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7267 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7268 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7269 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7270 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7271 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7272 
7273 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7274 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7275 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7276 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7277 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7278 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7279 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7280 
7281 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7282 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7283 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7284 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7285 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7286 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7287 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7288 
7289 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7290 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7291 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7292 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7293 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7294 		break;
7295 	}
7296 
7297 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7298 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7299 }
7300 
7301 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7302 {
7303 	uint32_t data;
7304 
7305 	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7306 	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7307 	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7308 
7309 	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7310 	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7311 	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7312 }
7313 
7314 static int gfx_v10_0_hw_init(void *handle)
7315 {
7316 	int r;
7317 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7318 
7319 	if (!amdgpu_emu_mode)
7320 		gfx_v10_0_init_golden_registers(adev);
7321 
7322 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7323 		/**
7324 		 * For gfx 10, rlc firmware loading relies on smu firmware is
7325 		 * loaded firstly, so in direct type, it has to load smc ucode
7326 		 * here before rlc.
7327 		 */
7328 		if (!(adev->flags & AMD_IS_APU)) {
7329 			r = amdgpu_pm_load_smu_firmware(adev, NULL);
7330 			if (r)
7331 				return r;
7332 		}
7333 		gfx_v10_0_disable_gpa_mode(adev);
7334 	}
7335 
7336 	/* if GRBM CAM not remapped, set up the remapping */
7337 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7338 		gfx_v10_0_setup_grbm_cam_remapping(adev);
7339 
7340 	gfx_v10_0_constants_init(adev);
7341 
7342 	r = gfx_v10_0_rlc_resume(adev);
7343 	if (r)
7344 		return r;
7345 
7346 	/*
7347 	 * init golden registers and rlc resume may override some registers,
7348 	 * reconfig them here
7349 	 */
7350 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7351 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7352 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7353 		gfx_v10_0_tcp_harvest(adev);
7354 
7355 	r = gfx_v10_0_cp_resume(adev);
7356 	if (r)
7357 		return r;
7358 
7359 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7360 		gfx_v10_3_program_pbb_mode(adev);
7361 
7362 	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7363 		gfx_v10_3_set_power_brake_sequence(adev);
7364 
7365 	return r;
7366 }
7367 
7368 static int gfx_v10_0_hw_fini(void *handle)
7369 {
7370 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7371 
7372 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7373 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7374 
7375 	/* WA added for Vangogh asic fixing the SMU suspend failure
7376 	 * It needs to set power gating again during gfxoff control
7377 	 * otherwise the gfxoff disallowing will be failed to set.
7378 	 */
7379 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7380 		gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
7381 
7382 	if (!adev->no_hw_access) {
7383 		if (amdgpu_async_gfx_ring) {
7384 			if (amdgpu_gfx_disable_kgq(adev, 0))
7385 				DRM_ERROR("KGQ disable failed\n");
7386 		}
7387 
7388 		if (amdgpu_gfx_disable_kcq(adev, 0))
7389 			DRM_ERROR("KCQ disable failed\n");
7390 	}
7391 
7392 	if (amdgpu_sriov_vf(adev)) {
7393 		gfx_v10_0_cp_gfx_enable(adev, false);
7394 		/* Remove the steps of clearing KIQ position.
7395 		 * It causes GFX hang when another Win guest is rendering.
7396 		 */
7397 		return 0;
7398 	}
7399 	gfx_v10_0_cp_enable(adev, false);
7400 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7401 
7402 	return 0;
7403 }
7404 
7405 static int gfx_v10_0_suspend(void *handle)
7406 {
7407 	return gfx_v10_0_hw_fini(handle);
7408 }
7409 
7410 static int gfx_v10_0_resume(void *handle)
7411 {
7412 	return gfx_v10_0_hw_init(handle);
7413 }
7414 
7415 static bool gfx_v10_0_is_idle(void *handle)
7416 {
7417 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7418 
7419 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7420 				GRBM_STATUS, GUI_ACTIVE))
7421 		return false;
7422 	else
7423 		return true;
7424 }
7425 
7426 static int gfx_v10_0_wait_for_idle(void *handle)
7427 {
7428 	unsigned int i;
7429 	u32 tmp;
7430 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7431 
7432 	for (i = 0; i < adev->usec_timeout; i++) {
7433 		/* read MC_STATUS */
7434 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7435 			GRBM_STATUS__GUI_ACTIVE_MASK;
7436 
7437 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7438 			return 0;
7439 		udelay(1);
7440 	}
7441 	return -ETIMEDOUT;
7442 }
7443 
7444 static int gfx_v10_0_soft_reset(void *handle)
7445 {
7446 	u32 grbm_soft_reset = 0;
7447 	u32 tmp;
7448 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7449 
7450 	/* GRBM_STATUS */
7451 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7452 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7453 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7454 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7455 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7456 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7457 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7458 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7459 						1);
7460 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7461 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7462 						1);
7463 	}
7464 
7465 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7466 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7467 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7468 						1);
7469 	}
7470 
7471 	/* GRBM_STATUS2 */
7472 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7473 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7474 	case IP_VERSION(10, 3, 0):
7475 	case IP_VERSION(10, 3, 2):
7476 	case IP_VERSION(10, 3, 1):
7477 	case IP_VERSION(10, 3, 4):
7478 	case IP_VERSION(10, 3, 5):
7479 	case IP_VERSION(10, 3, 6):
7480 	case IP_VERSION(10, 3, 3):
7481 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7482 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7483 							GRBM_SOFT_RESET,
7484 							SOFT_RESET_RLC,
7485 							1);
7486 		break;
7487 	default:
7488 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7489 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7490 							GRBM_SOFT_RESET,
7491 							SOFT_RESET_RLC,
7492 							1);
7493 		break;
7494 	}
7495 
7496 	if (grbm_soft_reset) {
7497 		/* stop the rlc */
7498 		gfx_v10_0_rlc_stop(adev);
7499 
7500 		/* Disable GFX parsing/prefetching */
7501 		gfx_v10_0_cp_gfx_enable(adev, false);
7502 
7503 		/* Disable MEC parsing/prefetching */
7504 		gfx_v10_0_cp_compute_enable(adev, false);
7505 
7506 		if (grbm_soft_reset) {
7507 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7508 			tmp |= grbm_soft_reset;
7509 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7510 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7511 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7512 
7513 			udelay(50);
7514 
7515 			tmp &= ~grbm_soft_reset;
7516 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7517 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7518 		}
7519 
7520 		/* Wait a little for things to settle down */
7521 		udelay(50);
7522 	}
7523 	return 0;
7524 }
7525 
7526 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7527 {
7528 	uint64_t clock, clock_lo, clock_hi, hi_check;
7529 
7530 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7531 	case IP_VERSION(10, 1, 3):
7532 	case IP_VERSION(10, 1, 4):
7533 		preempt_disable();
7534 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7535 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7536 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7537 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7538 		 * roughly every 42 seconds.
7539 		 */
7540 		if (hi_check != clock_hi) {
7541 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7542 			clock_hi = hi_check;
7543 		}
7544 		preempt_enable();
7545 		clock = clock_lo | (clock_hi << 32ULL);
7546 		break;
7547 	case IP_VERSION(10, 3, 1):
7548 	case IP_VERSION(10, 3, 3):
7549 	case IP_VERSION(10, 3, 7):
7550 		preempt_disable();
7551 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7552 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7553 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7554 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7555 		 * roughly every 42 seconds.
7556 		 */
7557 		if (hi_check != clock_hi) {
7558 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7559 			clock_hi = hi_check;
7560 		}
7561 		preempt_enable();
7562 		clock = clock_lo | (clock_hi << 32ULL);
7563 		break;
7564 	case IP_VERSION(10, 3, 6):
7565 		preempt_disable();
7566 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7567 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7568 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7569 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7570 		 * roughly every 42 seconds.
7571 		 */
7572 		if (hi_check != clock_hi) {
7573 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7574 			clock_hi = hi_check;
7575 		}
7576 		preempt_enable();
7577 		clock = clock_lo | (clock_hi << 32ULL);
7578 		break;
7579 	default:
7580 		preempt_disable();
7581 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7582 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7583 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7584 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7585 		 * roughly every 42 seconds.
7586 		 */
7587 		if (hi_check != clock_hi) {
7588 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7589 			clock_hi = hi_check;
7590 		}
7591 		preempt_enable();
7592 		clock = clock_lo | (clock_hi << 32ULL);
7593 		break;
7594 	}
7595 	return clock;
7596 }
7597 
7598 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7599 					   uint32_t vmid,
7600 					   uint32_t gds_base, uint32_t gds_size,
7601 					   uint32_t gws_base, uint32_t gws_size,
7602 					   uint32_t oa_base, uint32_t oa_size)
7603 {
7604 	struct amdgpu_device *adev = ring->adev;
7605 
7606 	/* GDS Base */
7607 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7608 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7609 				    gds_base);
7610 
7611 	/* GDS Size */
7612 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7613 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7614 				    gds_size);
7615 
7616 	/* GWS */
7617 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7618 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7619 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7620 
7621 	/* OA */
7622 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7623 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7624 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7625 }
7626 
7627 static int gfx_v10_0_early_init(void *handle)
7628 {
7629 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7630 
7631 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7632 
7633 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7634 	case IP_VERSION(10, 1, 10):
7635 	case IP_VERSION(10, 1, 1):
7636 	case IP_VERSION(10, 1, 2):
7637 	case IP_VERSION(10, 1, 3):
7638 	case IP_VERSION(10, 1, 4):
7639 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7640 		break;
7641 	case IP_VERSION(10, 3, 0):
7642 	case IP_VERSION(10, 3, 2):
7643 	case IP_VERSION(10, 3, 1):
7644 	case IP_VERSION(10, 3, 4):
7645 	case IP_VERSION(10, 3, 5):
7646 	case IP_VERSION(10, 3, 6):
7647 	case IP_VERSION(10, 3, 3):
7648 	case IP_VERSION(10, 3, 7):
7649 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7650 		break;
7651 	default:
7652 		break;
7653 	}
7654 
7655 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7656 					  AMDGPU_MAX_COMPUTE_RINGS);
7657 
7658 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7659 	gfx_v10_0_set_ring_funcs(adev);
7660 	gfx_v10_0_set_irq_funcs(adev);
7661 	gfx_v10_0_set_gds_init(adev);
7662 	gfx_v10_0_set_rlc_funcs(adev);
7663 	gfx_v10_0_set_mqd_funcs(adev);
7664 
7665 	/* init rlcg reg access ctrl */
7666 	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7667 
7668 	return gfx_v10_0_init_microcode(adev);
7669 }
7670 
7671 static int gfx_v10_0_late_init(void *handle)
7672 {
7673 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7674 	int r;
7675 
7676 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7677 	if (r)
7678 		return r;
7679 
7680 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7681 	if (r)
7682 		return r;
7683 
7684 	return 0;
7685 }
7686 
7687 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7688 {
7689 	uint32_t rlc_cntl;
7690 
7691 	/* if RLC is not enabled, do nothing */
7692 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7693 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7694 }
7695 
7696 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7697 {
7698 	uint32_t data;
7699 	unsigned int i;
7700 
7701 	data = RLC_SAFE_MODE__CMD_MASK;
7702 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7703 
7704 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7705 	case IP_VERSION(10, 3, 0):
7706 	case IP_VERSION(10, 3, 2):
7707 	case IP_VERSION(10, 3, 1):
7708 	case IP_VERSION(10, 3, 4):
7709 	case IP_VERSION(10, 3, 5):
7710 	case IP_VERSION(10, 3, 6):
7711 	case IP_VERSION(10, 3, 3):
7712 	case IP_VERSION(10, 3, 7):
7713 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7714 
7715 		/* wait for RLC_SAFE_MODE */
7716 		for (i = 0; i < adev->usec_timeout; i++) {
7717 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7718 					   RLC_SAFE_MODE, CMD))
7719 				break;
7720 			udelay(1);
7721 		}
7722 		break;
7723 	default:
7724 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7725 
7726 		/* wait for RLC_SAFE_MODE */
7727 		for (i = 0; i < adev->usec_timeout; i++) {
7728 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7729 					   RLC_SAFE_MODE, CMD))
7730 				break;
7731 			udelay(1);
7732 		}
7733 		break;
7734 	}
7735 }
7736 
7737 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7738 {
7739 	uint32_t data;
7740 
7741 	data = RLC_SAFE_MODE__CMD_MASK;
7742 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7743 	case IP_VERSION(10, 3, 0):
7744 	case IP_VERSION(10, 3, 2):
7745 	case IP_VERSION(10, 3, 1):
7746 	case IP_VERSION(10, 3, 4):
7747 	case IP_VERSION(10, 3, 5):
7748 	case IP_VERSION(10, 3, 6):
7749 	case IP_VERSION(10, 3, 3):
7750 	case IP_VERSION(10, 3, 7):
7751 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7752 		break;
7753 	default:
7754 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7755 		break;
7756 	}
7757 }
7758 
7759 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7760 						      bool enable)
7761 {
7762 	uint32_t data, def;
7763 
7764 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7765 		return;
7766 
7767 	/* It is disabled by HW by default */
7768 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7769 		/* 0 - Disable some blocks' MGCG */
7770 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7771 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7772 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7773 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7774 
7775 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7776 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7777 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7778 			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7779 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7780 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7781 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7782 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7783 
7784 		if (def != data)
7785 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7786 
7787 		/* MGLS is a global flag to control all MGLS in GFX */
7788 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7789 			/* 2 - RLC memory Light sleep */
7790 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7791 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7792 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7793 				if (def != data)
7794 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7795 			}
7796 			/* 3 - CP memory Light sleep */
7797 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7798 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7799 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7800 				if (def != data)
7801 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7802 			}
7803 		}
7804 	} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7805 		/* 1 - MGCG_OVERRIDE */
7806 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7807 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7808 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7809 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7810 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7811 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7812 			 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7813 		if (def != data)
7814 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7815 
7816 		/* 2 - disable MGLS in CP */
7817 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7818 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7819 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7820 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7821 		}
7822 
7823 		/* 3 - disable MGLS in RLC */
7824 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7825 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7826 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7827 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7828 		}
7829 
7830 	}
7831 }
7832 
7833 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7834 					   bool enable)
7835 {
7836 	uint32_t data, def;
7837 
7838 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7839 		return;
7840 
7841 	/* Enable 3D CGCG/CGLS */
7842 	if (enable) {
7843 		/* write cmd to clear cgcg/cgls ov */
7844 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7845 
7846 		/* unset CGCG override */
7847 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7848 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7849 
7850 		/* update CGCG and CGLS override bits */
7851 		if (def != data)
7852 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7853 
7854 		/* enable 3Dcgcg FSM(0x0000363f) */
7855 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7856 		data = 0;
7857 
7858 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7859 			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7860 				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7861 
7862 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7863 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7864 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7865 
7866 		if (def != data)
7867 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7868 
7869 		/* set IDLE_POLL_COUNT(0x00900100) */
7870 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7871 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7872 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7873 		if (def != data)
7874 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7875 	} else {
7876 		/* Disable CGCG/CGLS */
7877 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7878 
7879 		/* disable cgcg, cgls should be disabled */
7880 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7881 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7882 
7883 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7884 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7885 
7886 		/* disable cgcg and cgls in FSM */
7887 		if (def != data)
7888 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7889 	}
7890 }
7891 
7892 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7893 						      bool enable)
7894 {
7895 	uint32_t def, data;
7896 
7897 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7898 		return;
7899 
7900 	if (enable) {
7901 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7902 
7903 		/* unset CGCG override */
7904 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7905 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7906 
7907 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7908 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7909 
7910 		/* update CGCG and CGLS override bits */
7911 		if (def != data)
7912 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7913 
7914 		/* enable cgcg FSM(0x0000363F) */
7915 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7916 		data = 0;
7917 
7918 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7919 			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7920 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7921 
7922 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7923 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7924 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7925 
7926 		if (def != data)
7927 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7928 
7929 		/* set IDLE_POLL_COUNT(0x00900100) */
7930 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7931 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7932 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7933 		if (def != data)
7934 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7935 	} else {
7936 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7937 
7938 		/* reset CGCG/CGLS bits */
7939 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7940 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7941 
7942 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7943 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7944 
7945 		/* disable cgcg and cgls in FSM */
7946 		if (def != data)
7947 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7948 	}
7949 }
7950 
7951 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7952 						      bool enable)
7953 {
7954 	uint32_t def, data;
7955 
7956 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7957 		return;
7958 
7959 	if (enable) {
7960 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7961 		/* unset FGCG override */
7962 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7963 		/* update FGCG override bits */
7964 		if (def != data)
7965 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7966 
7967 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7968 		/* unset RLC SRAM CLK GATER override */
7969 		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7970 		/* update RLC SRAM CLK GATER override bits */
7971 		if (def != data)
7972 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7973 	} else {
7974 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7975 		/* reset FGCG bits */
7976 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7977 		/* disable FGCG*/
7978 		if (def != data)
7979 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7980 
7981 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7982 		/* reset RLC SRAM CLK GATER bits */
7983 		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7984 		/* disable RLC SRAM CLK*/
7985 		if (def != data)
7986 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7987 	}
7988 }
7989 
7990 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7991 {
7992 	uint32_t reg_data = 0;
7993 	uint32_t reg_idx = 0;
7994 	uint32_t i;
7995 
7996 	const uint32_t tcp_ctrl_regs[] = {
7997 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7998 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7999 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8000 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8001 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8002 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8003 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8004 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8005 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8006 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8007 		mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8008 		mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8009 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8010 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8011 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8012 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8013 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8014 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8015 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8016 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8017 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8018 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8019 		mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8020 		mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8021 	};
8022 
8023 	const uint32_t tcp_ctrl_regs_nv12[] = {
8024 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8025 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8026 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8027 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8028 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8029 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8030 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8031 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8032 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8033 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8034 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8035 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8036 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8037 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8038 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8039 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8040 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8041 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8042 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8043 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8044 	};
8045 
8046 	const uint32_t sm_ctlr_regs[] = {
8047 		mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8048 		mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8049 		mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8050 		mmCGTS_SA1_QUAD1_SM_CTRL_REG
8051 	};
8052 
8053 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8054 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8055 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8056 				  tcp_ctrl_regs_nv12[i];
8057 			reg_data = RREG32(reg_idx);
8058 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8059 			WREG32(reg_idx, reg_data);
8060 		}
8061 	} else {
8062 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8063 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8064 				  tcp_ctrl_regs[i];
8065 			reg_data = RREG32(reg_idx);
8066 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8067 			WREG32(reg_idx, reg_data);
8068 		}
8069 	}
8070 
8071 	for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8072 		reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8073 			  sm_ctlr_regs[i];
8074 		reg_data = RREG32(reg_idx);
8075 		reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8076 		reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8077 		WREG32(reg_idx, reg_data);
8078 	}
8079 }
8080 
8081 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8082 					    bool enable)
8083 {
8084 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8085 
8086 	if (enable) {
8087 		/* enable FGCG firstly*/
8088 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8089 		/* CGCG/CGLS should be enabled after MGCG/MGLS
8090 		 * ===  MGCG + MGLS ===
8091 		 */
8092 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8093 		/* ===  CGCG /CGLS for GFX 3D Only === */
8094 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8095 		/* ===  CGCG + CGLS === */
8096 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8097 
8098 		if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8099 		     IP_VERSION(10, 1, 10)) ||
8100 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8101 		     IP_VERSION(10, 1, 1)) ||
8102 		    (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8103 		     IP_VERSION(10, 1, 2)))
8104 			gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8105 	} else {
8106 		/* CGCG/CGLS should be disabled before MGCG/MGLS
8107 		 * ===  CGCG + CGLS ===
8108 		 */
8109 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8110 		/* ===  CGCG /CGLS for GFX 3D Only === */
8111 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8112 		/* ===  MGCG + MGLS === */
8113 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8114 		/* disable fgcg at last*/
8115 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8116 	}
8117 
8118 	if (adev->cg_flags &
8119 	    (AMD_CG_SUPPORT_GFX_MGCG |
8120 	     AMD_CG_SUPPORT_GFX_CGLS |
8121 	     AMD_CG_SUPPORT_GFX_CGCG |
8122 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
8123 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
8124 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8125 
8126 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8127 
8128 	return 0;
8129 }
8130 
8131 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8132 					       unsigned int vmid)
8133 {
8134 	u32 reg, pre_data, data;
8135 
8136 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8137 	/* not for *_SOC15 */
8138 	if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8139 		pre_data = RREG32_NO_KIQ(reg);
8140 	else
8141 		pre_data = RREG32(reg);
8142 
8143 	data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8144 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8145 
8146 	if (pre_data != data) {
8147 		if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8148 			WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8149 		} else
8150 			WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8151 	}
8152 }
8153 
8154 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8155 {
8156 	amdgpu_gfx_off_ctrl(adev, false);
8157 
8158 	gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8159 
8160 	amdgpu_gfx_off_ctrl(adev, true);
8161 }
8162 
8163 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8164 					uint32_t offset,
8165 					struct soc15_reg_rlcg *entries, int arr_size)
8166 {
8167 	int i;
8168 	uint32_t reg;
8169 
8170 	if (!entries)
8171 		return false;
8172 
8173 	for (i = 0; i < arr_size; i++) {
8174 		const struct soc15_reg_rlcg *entry;
8175 
8176 		entry = &entries[i];
8177 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8178 		if (offset == reg)
8179 			return true;
8180 	}
8181 
8182 	return false;
8183 }
8184 
8185 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8186 {
8187 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8188 }
8189 
8190 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8191 {
8192 	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8193 
8194 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8195 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8196 	else
8197 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8198 
8199 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8200 
8201 	/*
8202 	 * CGPG enablement required and the register to program the hysteresis value
8203 	 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8204 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
8205 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8206 	 *
8207 	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8208 	 * of CGPG enablement starting point.
8209 	 * Power/performance team will optimize it and might give a new value later.
8210 	 */
8211 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8212 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8213 		case IP_VERSION(10, 3, 1):
8214 		case IP_VERSION(10, 3, 3):
8215 		case IP_VERSION(10, 3, 6):
8216 		case IP_VERSION(10, 3, 7):
8217 			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8218 			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8219 			break;
8220 		default:
8221 			break;
8222 		}
8223 	}
8224 }
8225 
8226 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8227 {
8228 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8229 
8230 	gfx_v10_cntl_power_gating(adev, enable);
8231 
8232 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8233 }
8234 
8235 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8236 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8237 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8238 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8239 	.init = gfx_v10_0_rlc_init,
8240 	.get_csb_size = gfx_v10_0_get_csb_size,
8241 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8242 	.resume = gfx_v10_0_rlc_resume,
8243 	.stop = gfx_v10_0_rlc_stop,
8244 	.reset = gfx_v10_0_rlc_reset,
8245 	.start = gfx_v10_0_rlc_start,
8246 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8247 };
8248 
8249 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8250 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8251 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8252 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8253 	.init = gfx_v10_0_rlc_init,
8254 	.get_csb_size = gfx_v10_0_get_csb_size,
8255 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8256 	.resume = gfx_v10_0_rlc_resume,
8257 	.stop = gfx_v10_0_rlc_stop,
8258 	.reset = gfx_v10_0_rlc_reset,
8259 	.start = gfx_v10_0_rlc_start,
8260 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8261 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8262 };
8263 
8264 static int gfx_v10_0_set_powergating_state(void *handle,
8265 					  enum amd_powergating_state state)
8266 {
8267 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8268 	bool enable = (state == AMD_PG_STATE_GATE);
8269 
8270 	if (amdgpu_sriov_vf(adev))
8271 		return 0;
8272 
8273 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8274 	case IP_VERSION(10, 1, 10):
8275 	case IP_VERSION(10, 1, 1):
8276 	case IP_VERSION(10, 1, 2):
8277 	case IP_VERSION(10, 3, 0):
8278 	case IP_VERSION(10, 3, 2):
8279 	case IP_VERSION(10, 3, 4):
8280 	case IP_VERSION(10, 3, 5):
8281 		amdgpu_gfx_off_ctrl(adev, enable);
8282 		break;
8283 	case IP_VERSION(10, 3, 1):
8284 	case IP_VERSION(10, 3, 3):
8285 	case IP_VERSION(10, 3, 6):
8286 	case IP_VERSION(10, 3, 7):
8287 		if (!enable)
8288 			amdgpu_gfx_off_ctrl(adev, false);
8289 
8290 		gfx_v10_cntl_pg(adev, enable);
8291 
8292 		if (enable)
8293 			amdgpu_gfx_off_ctrl(adev, true);
8294 
8295 		break;
8296 	default:
8297 		break;
8298 	}
8299 	return 0;
8300 }
8301 
8302 static int gfx_v10_0_set_clockgating_state(void *handle,
8303 					  enum amd_clockgating_state state)
8304 {
8305 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8306 
8307 	if (amdgpu_sriov_vf(adev))
8308 		return 0;
8309 
8310 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8311 	case IP_VERSION(10, 1, 10):
8312 	case IP_VERSION(10, 1, 1):
8313 	case IP_VERSION(10, 1, 2):
8314 	case IP_VERSION(10, 3, 0):
8315 	case IP_VERSION(10, 3, 2):
8316 	case IP_VERSION(10, 3, 1):
8317 	case IP_VERSION(10, 3, 4):
8318 	case IP_VERSION(10, 3, 5):
8319 	case IP_VERSION(10, 3, 6):
8320 	case IP_VERSION(10, 3, 3):
8321 	case IP_VERSION(10, 3, 7):
8322 		gfx_v10_0_update_gfx_clock_gating(adev,
8323 						 state == AMD_CG_STATE_GATE);
8324 		break;
8325 	default:
8326 		break;
8327 	}
8328 	return 0;
8329 }
8330 
8331 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8332 {
8333 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8334 	int data;
8335 
8336 	/* AMD_CG_SUPPORT_GFX_FGCG */
8337 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8338 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8339 		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
8340 
8341 	/* AMD_CG_SUPPORT_GFX_MGCG */
8342 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8343 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8344 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
8345 
8346 	/* AMD_CG_SUPPORT_GFX_CGCG */
8347 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8348 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8349 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
8350 
8351 	/* AMD_CG_SUPPORT_GFX_CGLS */
8352 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8353 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
8354 
8355 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
8356 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8357 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8358 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8359 
8360 	/* AMD_CG_SUPPORT_GFX_CP_LS */
8361 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8362 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8363 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8364 
8365 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
8366 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8367 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8368 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8369 
8370 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
8371 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8372 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8373 }
8374 
8375 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8376 {
8377 	/* gfx10 is 32bit rptr*/
8378 	return *(uint32_t *)ring->rptr_cpu_addr;
8379 }
8380 
8381 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8382 {
8383 	struct amdgpu_device *adev = ring->adev;
8384 	u64 wptr;
8385 
8386 	/* XXX check if swapping is necessary on BE */
8387 	if (ring->use_doorbell) {
8388 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8389 	} else {
8390 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8391 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8392 	}
8393 
8394 	return wptr;
8395 }
8396 
8397 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8398 {
8399 	struct amdgpu_device *adev = ring->adev;
8400 
8401 	if (ring->use_doorbell) {
8402 		/* XXX check if swapping is necessary on BE */
8403 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8404 			     ring->wptr);
8405 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8406 	} else {
8407 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8408 			     lower_32_bits(ring->wptr));
8409 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8410 			     upper_32_bits(ring->wptr));
8411 	}
8412 }
8413 
8414 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8415 {
8416 	/* gfx10 hardware is 32bit rptr */
8417 	return *(uint32_t *)ring->rptr_cpu_addr;
8418 }
8419 
8420 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8421 {
8422 	u64 wptr;
8423 
8424 	/* XXX check if swapping is necessary on BE */
8425 	if (ring->use_doorbell)
8426 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8427 	else
8428 		BUG();
8429 	return wptr;
8430 }
8431 
8432 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8433 {
8434 	struct amdgpu_device *adev = ring->adev;
8435 
8436 	if (ring->use_doorbell) {
8437 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8438 			     ring->wptr);
8439 		WDOORBELL64(ring->doorbell_index, ring->wptr);
8440 	} else {
8441 		BUG(); /* only DOORBELL method supported on gfx10 now */
8442 	}
8443 }
8444 
8445 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8446 {
8447 	struct amdgpu_device *adev = ring->adev;
8448 	u32 ref_and_mask, reg_mem_engine;
8449 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8450 
8451 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8452 		switch (ring->me) {
8453 		case 1:
8454 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8455 			break;
8456 		case 2:
8457 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8458 			break;
8459 		default:
8460 			return;
8461 		}
8462 		reg_mem_engine = 0;
8463 	} else {
8464 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8465 		reg_mem_engine = 1; /* pfp */
8466 	}
8467 
8468 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8469 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8470 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8471 			       ref_and_mask, ref_and_mask, 0x20);
8472 }
8473 
8474 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8475 				       struct amdgpu_job *job,
8476 				       struct amdgpu_ib *ib,
8477 				       uint32_t flags)
8478 {
8479 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8480 	u32 header, control = 0;
8481 
8482 	if (ib->flags & AMDGPU_IB_FLAG_CE)
8483 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8484 	else
8485 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8486 
8487 	control |= ib->length_dw | (vmid << 24);
8488 
8489 	if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8490 		control |= INDIRECT_BUFFER_PRE_ENB(1);
8491 
8492 		if (flags & AMDGPU_IB_PREEMPTED)
8493 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
8494 
8495 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8496 			gfx_v10_0_ring_emit_de_meta(ring,
8497 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8498 	}
8499 
8500 	amdgpu_ring_write(ring, header);
8501 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8502 	amdgpu_ring_write(ring,
8503 #ifdef __BIG_ENDIAN
8504 		(2 << 0) |
8505 #endif
8506 		lower_32_bits(ib->gpu_addr));
8507 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8508 	amdgpu_ring_write(ring, control);
8509 }
8510 
8511 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8512 					   struct amdgpu_job *job,
8513 					   struct amdgpu_ib *ib,
8514 					   uint32_t flags)
8515 {
8516 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8517 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8518 
8519 	/* Currently, there is a high possibility to get wave ID mismatch
8520 	 * between ME and GDS, leading to a hw deadlock, because ME generates
8521 	 * different wave IDs than the GDS expects. This situation happens
8522 	 * randomly when at least 5 compute pipes use GDS ordered append.
8523 	 * The wave IDs generated by ME are also wrong after suspend/resume.
8524 	 * Those are probably bugs somewhere else in the kernel driver.
8525 	 *
8526 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8527 	 * GDS to 0 for this ring (me/pipe).
8528 	 */
8529 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8530 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8531 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8532 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8533 	}
8534 
8535 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8536 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8537 	amdgpu_ring_write(ring,
8538 #ifdef __BIG_ENDIAN
8539 				(2 << 0) |
8540 #endif
8541 				lower_32_bits(ib->gpu_addr));
8542 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8543 	amdgpu_ring_write(ring, control);
8544 }
8545 
8546 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8547 				     u64 seq, unsigned int flags)
8548 {
8549 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8550 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8551 
8552 	/* RELEASE_MEM - flush caches, send int */
8553 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8554 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8555 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8556 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8557 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8558 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8559 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8560 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8561 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8562 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8563 
8564 	/*
8565 	 * the address should be Qword aligned if 64bit write, Dword
8566 	 * aligned if only send 32bit data low (discard data high)
8567 	 */
8568 	if (write64bit)
8569 		BUG_ON(addr & 0x7);
8570 	else
8571 		BUG_ON(addr & 0x3);
8572 	amdgpu_ring_write(ring, lower_32_bits(addr));
8573 	amdgpu_ring_write(ring, upper_32_bits(addr));
8574 	amdgpu_ring_write(ring, lower_32_bits(seq));
8575 	amdgpu_ring_write(ring, upper_32_bits(seq));
8576 	amdgpu_ring_write(ring, 0);
8577 }
8578 
8579 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8580 {
8581 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8582 	uint32_t seq = ring->fence_drv.sync_seq;
8583 	uint64_t addr = ring->fence_drv.gpu_addr;
8584 
8585 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8586 			       upper_32_bits(addr), seq, 0xffffffff, 4);
8587 }
8588 
8589 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8590 				   uint16_t pasid, uint32_t flush_type,
8591 				   bool all_hub, uint8_t dst_sel)
8592 {
8593 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8594 	amdgpu_ring_write(ring,
8595 			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8596 			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8597 			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8598 			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8599 }
8600 
8601 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8602 					 unsigned int vmid, uint64_t pd_addr)
8603 {
8604 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8605 
8606 	/* compute doesn't have PFP */
8607 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8608 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
8609 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8610 		amdgpu_ring_write(ring, 0x0);
8611 	}
8612 }
8613 
8614 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8615 					  u64 seq, unsigned int flags)
8616 {
8617 	struct amdgpu_device *adev = ring->adev;
8618 
8619 	/* we only allocate 32bit for each seq wb address */
8620 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8621 
8622 	/* write fence seq to the "addr" */
8623 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8624 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8625 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8626 	amdgpu_ring_write(ring, lower_32_bits(addr));
8627 	amdgpu_ring_write(ring, upper_32_bits(addr));
8628 	amdgpu_ring_write(ring, lower_32_bits(seq));
8629 
8630 	if (flags & AMDGPU_FENCE_FLAG_INT) {
8631 		/* set register to trigger INT */
8632 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8633 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8634 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8635 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8636 		amdgpu_ring_write(ring, 0);
8637 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8638 	}
8639 }
8640 
8641 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8642 {
8643 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8644 	amdgpu_ring_write(ring, 0);
8645 }
8646 
8647 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8648 					 uint32_t flags)
8649 {
8650 	uint32_t dw2 = 0;
8651 
8652 	if (ring->adev->gfx.mcbp)
8653 		gfx_v10_0_ring_emit_ce_meta(ring,
8654 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8655 
8656 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8657 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8658 		/* set load_global_config & load_global_uconfig */
8659 		dw2 |= 0x8001;
8660 		/* set load_cs_sh_regs */
8661 		dw2 |= 0x01000000;
8662 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
8663 		dw2 |= 0x10002;
8664 
8665 		/* set load_ce_ram if preamble presented */
8666 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8667 			dw2 |= 0x10000000;
8668 	} else {
8669 		/* still load_ce_ram if this is the first time preamble presented
8670 		 * although there is no context switch happens.
8671 		 */
8672 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8673 			dw2 |= 0x10000000;
8674 	}
8675 
8676 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8677 	amdgpu_ring_write(ring, dw2);
8678 	amdgpu_ring_write(ring, 0);
8679 }
8680 
8681 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8682 						       uint64_t addr)
8683 {
8684 	unsigned int ret;
8685 
8686 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8687 	amdgpu_ring_write(ring, lower_32_bits(addr));
8688 	amdgpu_ring_write(ring, upper_32_bits(addr));
8689 	/* discard following DWs if *cond_exec_gpu_addr==0 */
8690 	amdgpu_ring_write(ring, 0);
8691 	ret = ring->wptr & ring->buf_mask;
8692 	/* patch dummy value later */
8693 	amdgpu_ring_write(ring, 0);
8694 
8695 	return ret;
8696 }
8697 
8698 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8699 {
8700 	int i, r = 0;
8701 	struct amdgpu_device *adev = ring->adev;
8702 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8703 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8704 	unsigned long flags;
8705 
8706 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8707 		return -EINVAL;
8708 
8709 	spin_lock_irqsave(&kiq->ring_lock, flags);
8710 
8711 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8712 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8713 		return -ENOMEM;
8714 	}
8715 
8716 	/* assert preemption condition */
8717 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8718 
8719 	/* assert IB preemption, emit the trailing fence */
8720 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8721 				   ring->trail_fence_gpu_addr,
8722 				   ++ring->trail_seq);
8723 	amdgpu_ring_commit(kiq_ring);
8724 
8725 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8726 
8727 	/* poll the trailing fence */
8728 	for (i = 0; i < adev->usec_timeout; i++) {
8729 		if (ring->trail_seq ==
8730 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8731 			break;
8732 		udelay(1);
8733 	}
8734 
8735 	if (i >= adev->usec_timeout) {
8736 		r = -EINVAL;
8737 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8738 	}
8739 
8740 	/* deassert preemption condition */
8741 	amdgpu_ring_set_preempt_cond_exec(ring, true);
8742 	return r;
8743 }
8744 
8745 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8746 {
8747 	struct amdgpu_device *adev = ring->adev;
8748 	struct v10_ce_ib_state ce_payload = {0};
8749 	uint64_t offset, ce_payload_gpu_addr;
8750 	void *ce_payload_cpu_addr;
8751 	int cnt;
8752 
8753 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8754 
8755 	offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8756 	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8757 	ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8758 
8759 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8760 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8761 				 WRITE_DATA_DST_SEL(8) |
8762 				 WR_CONFIRM) |
8763 				 WRITE_DATA_CACHE_POLICY(0));
8764 	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8765 	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8766 
8767 	if (resume)
8768 		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8769 					   sizeof(ce_payload) >> 2);
8770 	else
8771 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8772 					   sizeof(ce_payload) >> 2);
8773 }
8774 
8775 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8776 {
8777 	struct amdgpu_device *adev = ring->adev;
8778 	struct v10_de_ib_state de_payload = {0};
8779 	uint64_t offset, gds_addr, de_payload_gpu_addr;
8780 	void *de_payload_cpu_addr;
8781 	int cnt;
8782 
8783 	offset = offsetof(struct v10_gfx_meta_data, de_payload);
8784 	de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8785 	de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8786 
8787 	gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8788 			 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8789 			 PAGE_SIZE);
8790 
8791 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8792 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8793 
8794 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8795 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8796 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8797 				 WRITE_DATA_DST_SEL(8) |
8798 				 WR_CONFIRM) |
8799 				 WRITE_DATA_CACHE_POLICY(0));
8800 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8801 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8802 
8803 	if (resume)
8804 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8805 					   sizeof(de_payload) >> 2);
8806 	else
8807 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8808 					   sizeof(de_payload) >> 2);
8809 }
8810 
8811 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8812 				    bool secure)
8813 {
8814 	uint32_t v = secure ? FRAME_TMZ : 0;
8815 
8816 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8817 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8818 }
8819 
8820 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8821 				     uint32_t reg_val_offs)
8822 {
8823 	struct amdgpu_device *adev = ring->adev;
8824 
8825 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8826 	amdgpu_ring_write(ring, 0 |	/* src: register*/
8827 				(5 << 8) |	/* dst: memory */
8828 				(1 << 20));	/* write confirm */
8829 	amdgpu_ring_write(ring, reg);
8830 	amdgpu_ring_write(ring, 0);
8831 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8832 				reg_val_offs * 4));
8833 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8834 				reg_val_offs * 4));
8835 }
8836 
8837 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8838 				   uint32_t val)
8839 {
8840 	uint32_t cmd = 0;
8841 
8842 	switch (ring->funcs->type) {
8843 	case AMDGPU_RING_TYPE_GFX:
8844 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8845 		break;
8846 	case AMDGPU_RING_TYPE_KIQ:
8847 		cmd = (1 << 16); /* no inc addr */
8848 		break;
8849 	default:
8850 		cmd = WR_CONFIRM;
8851 		break;
8852 	}
8853 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8854 	amdgpu_ring_write(ring, cmd);
8855 	amdgpu_ring_write(ring, reg);
8856 	amdgpu_ring_write(ring, 0);
8857 	amdgpu_ring_write(ring, val);
8858 }
8859 
8860 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8861 					uint32_t val, uint32_t mask)
8862 {
8863 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8864 }
8865 
8866 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8867 						   uint32_t reg0, uint32_t reg1,
8868 						   uint32_t ref, uint32_t mask)
8869 {
8870 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8871 	struct amdgpu_device *adev = ring->adev;
8872 	bool fw_version_ok = false;
8873 
8874 	fw_version_ok = adev->gfx.cp_fw_write_wait;
8875 
8876 	if (fw_version_ok)
8877 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8878 				       ref, mask, 0x20);
8879 	else
8880 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8881 							   ref, mask);
8882 }
8883 
8884 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8885 					 unsigned int vmid)
8886 {
8887 	struct amdgpu_device *adev = ring->adev;
8888 	uint32_t value = 0;
8889 
8890 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8891 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8892 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8893 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8894 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8895 }
8896 
8897 static void
8898 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8899 				      uint32_t me, uint32_t pipe,
8900 				      enum amdgpu_interrupt_state state)
8901 {
8902 	uint32_t cp_int_cntl, cp_int_cntl_reg;
8903 
8904 	if (!me) {
8905 		switch (pipe) {
8906 		case 0:
8907 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8908 			break;
8909 		case 1:
8910 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8911 			break;
8912 		default:
8913 			DRM_DEBUG("invalid pipe %d\n", pipe);
8914 			return;
8915 		}
8916 	} else {
8917 		DRM_DEBUG("invalid me %d\n", me);
8918 		return;
8919 	}
8920 
8921 	switch (state) {
8922 	case AMDGPU_IRQ_STATE_DISABLE:
8923 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8924 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8925 					    TIME_STAMP_INT_ENABLE, 0);
8926 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8927 		break;
8928 	case AMDGPU_IRQ_STATE_ENABLE:
8929 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8930 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8931 					    TIME_STAMP_INT_ENABLE, 1);
8932 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8933 		break;
8934 	default:
8935 		break;
8936 	}
8937 }
8938 
8939 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8940 						     int me, int pipe,
8941 						     enum amdgpu_interrupt_state state)
8942 {
8943 	u32 mec_int_cntl, mec_int_cntl_reg;
8944 
8945 	/*
8946 	 * amdgpu controls only the first MEC. That's why this function only
8947 	 * handles the setting of interrupts for this specific MEC. All other
8948 	 * pipes' interrupts are set by amdkfd.
8949 	 */
8950 
8951 	if (me == 1) {
8952 		switch (pipe) {
8953 		case 0:
8954 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8955 			break;
8956 		case 1:
8957 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8958 			break;
8959 		case 2:
8960 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8961 			break;
8962 		case 3:
8963 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8964 			break;
8965 		default:
8966 			DRM_DEBUG("invalid pipe %d\n", pipe);
8967 			return;
8968 		}
8969 	} else {
8970 		DRM_DEBUG("invalid me %d\n", me);
8971 		return;
8972 	}
8973 
8974 	switch (state) {
8975 	case AMDGPU_IRQ_STATE_DISABLE:
8976 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8977 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8978 					     TIME_STAMP_INT_ENABLE, 0);
8979 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8980 		break;
8981 	case AMDGPU_IRQ_STATE_ENABLE:
8982 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8983 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8984 					     TIME_STAMP_INT_ENABLE, 1);
8985 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8986 		break;
8987 	default:
8988 		break;
8989 	}
8990 }
8991 
8992 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8993 					    struct amdgpu_irq_src *src,
8994 					    unsigned int type,
8995 					    enum amdgpu_interrupt_state state)
8996 {
8997 	switch (type) {
8998 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8999 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9000 		break;
9001 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9002 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9003 		break;
9004 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9005 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9006 		break;
9007 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9008 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9009 		break;
9010 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9011 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9012 		break;
9013 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9014 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9015 		break;
9016 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9017 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9018 		break;
9019 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9020 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9021 		break;
9022 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9023 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9024 		break;
9025 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9026 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9027 		break;
9028 	default:
9029 		break;
9030 	}
9031 	return 0;
9032 }
9033 
9034 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9035 			     struct amdgpu_irq_src *source,
9036 			     struct amdgpu_iv_entry *entry)
9037 {
9038 	int i;
9039 	u8 me_id, pipe_id, queue_id;
9040 	struct amdgpu_ring *ring;
9041 
9042 	DRM_DEBUG("IH: CP EOP\n");
9043 
9044 	me_id = (entry->ring_id & 0x0c) >> 2;
9045 	pipe_id = (entry->ring_id & 0x03) >> 0;
9046 	queue_id = (entry->ring_id & 0x70) >> 4;
9047 
9048 	switch (me_id) {
9049 	case 0:
9050 		if (pipe_id == 0)
9051 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9052 		else
9053 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9054 		break;
9055 	case 1:
9056 	case 2:
9057 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9058 			ring = &adev->gfx.compute_ring[i];
9059 			/* Per-queue interrupt is supported for MEC starting from VI.
9060 			 * The interrupt can only be enabled/disabled per pipe instead
9061 			 * of per queue.
9062 			 */
9063 			if ((ring->me == me_id) &&
9064 			    (ring->pipe == pipe_id) &&
9065 			    (ring->queue == queue_id))
9066 				amdgpu_fence_process(ring);
9067 		}
9068 		break;
9069 	}
9070 
9071 	return 0;
9072 }
9073 
9074 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9075 					      struct amdgpu_irq_src *source,
9076 					      unsigned int type,
9077 					      enum amdgpu_interrupt_state state)
9078 {
9079 	switch (state) {
9080 	case AMDGPU_IRQ_STATE_DISABLE:
9081 	case AMDGPU_IRQ_STATE_ENABLE:
9082 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9083 			       PRIV_REG_INT_ENABLE,
9084 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9085 		break;
9086 	default:
9087 		break;
9088 	}
9089 
9090 	return 0;
9091 }
9092 
9093 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9094 					       struct amdgpu_irq_src *source,
9095 					       unsigned int type,
9096 					       enum amdgpu_interrupt_state state)
9097 {
9098 	switch (state) {
9099 	case AMDGPU_IRQ_STATE_DISABLE:
9100 	case AMDGPU_IRQ_STATE_ENABLE:
9101 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9102 			       PRIV_INSTR_INT_ENABLE,
9103 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9104 		break;
9105 	default:
9106 		break;
9107 	}
9108 
9109 	return 0;
9110 }
9111 
9112 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9113 					struct amdgpu_iv_entry *entry)
9114 {
9115 	u8 me_id, pipe_id, queue_id;
9116 	struct amdgpu_ring *ring;
9117 	int i;
9118 
9119 	me_id = (entry->ring_id & 0x0c) >> 2;
9120 	pipe_id = (entry->ring_id & 0x03) >> 0;
9121 	queue_id = (entry->ring_id & 0x70) >> 4;
9122 
9123 	switch (me_id) {
9124 	case 0:
9125 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9126 			ring = &adev->gfx.gfx_ring[i];
9127 			/* we only enabled 1 gfx queue per pipe for now */
9128 			if (ring->me == me_id && ring->pipe == pipe_id)
9129 				drm_sched_fault(&ring->sched);
9130 		}
9131 		break;
9132 	case 1:
9133 	case 2:
9134 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9135 			ring = &adev->gfx.compute_ring[i];
9136 			if (ring->me == me_id && ring->pipe == pipe_id &&
9137 			    ring->queue == queue_id)
9138 				drm_sched_fault(&ring->sched);
9139 		}
9140 		break;
9141 	default:
9142 		BUG();
9143 	}
9144 }
9145 
9146 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9147 				  struct amdgpu_irq_src *source,
9148 				  struct amdgpu_iv_entry *entry)
9149 {
9150 	DRM_ERROR("Illegal register access in command stream\n");
9151 	gfx_v10_0_handle_priv_fault(adev, entry);
9152 	return 0;
9153 }
9154 
9155 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9156 				   struct amdgpu_irq_src *source,
9157 				   struct amdgpu_iv_entry *entry)
9158 {
9159 	DRM_ERROR("Illegal instruction in command stream\n");
9160 	gfx_v10_0_handle_priv_fault(adev, entry);
9161 	return 0;
9162 }
9163 
9164 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9165 					     struct amdgpu_irq_src *src,
9166 					     unsigned int type,
9167 					     enum amdgpu_interrupt_state state)
9168 {
9169 	uint32_t tmp, target;
9170 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9171 
9172 	if (ring->me == 1)
9173 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9174 	else
9175 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9176 	target += ring->pipe;
9177 
9178 	switch (type) {
9179 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9180 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
9181 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9182 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9183 					    GENERIC2_INT_ENABLE, 0);
9184 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9185 
9186 			tmp = RREG32_SOC15_IP(GC, target);
9187 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9188 					    GENERIC2_INT_ENABLE, 0);
9189 			WREG32_SOC15_IP(GC, target, tmp);
9190 		} else {
9191 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9192 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9193 					    GENERIC2_INT_ENABLE, 1);
9194 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9195 
9196 			tmp = RREG32_SOC15_IP(GC, target);
9197 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9198 					    GENERIC2_INT_ENABLE, 1);
9199 			WREG32_SOC15_IP(GC, target, tmp);
9200 		}
9201 		break;
9202 	default:
9203 		BUG(); /* kiq only support GENERIC2_INT now */
9204 		break;
9205 	}
9206 	return 0;
9207 }
9208 
9209 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9210 			     struct amdgpu_irq_src *source,
9211 			     struct amdgpu_iv_entry *entry)
9212 {
9213 	u8 me_id, pipe_id, queue_id;
9214 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9215 
9216 	me_id = (entry->ring_id & 0x0c) >> 2;
9217 	pipe_id = (entry->ring_id & 0x03) >> 0;
9218 	queue_id = (entry->ring_id & 0x70) >> 4;
9219 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9220 		   me_id, pipe_id, queue_id);
9221 
9222 	amdgpu_fence_process(ring);
9223 	return 0;
9224 }
9225 
9226 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9227 {
9228 	const unsigned int gcr_cntl =
9229 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9230 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9231 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9232 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9233 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9234 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9235 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9236 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9237 
9238 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9239 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9240 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9241 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9242 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9243 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9244 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9245 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9246 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9247 }
9248 
9249 static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
9250 {
9251 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9252 	uint32_t i, j, k, reg, index = 0;
9253 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9254 
9255 	if (!adev->gfx.ip_dump_core)
9256 		return;
9257 
9258 	for (i = 0; i < reg_count; i++)
9259 		drm_printf(p, "%-50s \t 0x%08x\n",
9260 			   gc_reg_list_10_1[i].reg_name,
9261 			   adev->gfx.ip_dump_core[i]);
9262 
9263 	/* print compute queue registers for all instances */
9264 	if (!adev->gfx.ip_dump_compute_queues)
9265 		return;
9266 
9267 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9268 	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9269 		   adev->gfx.mec.num_mec,
9270 		   adev->gfx.mec.num_pipe_per_mec,
9271 		   adev->gfx.mec.num_queue_per_pipe);
9272 
9273 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9274 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9275 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9276 				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9277 				for (reg = 0; reg < reg_count; reg++) {
9278 					drm_printf(p, "%-50s \t 0x%08x\n",
9279 						   gc_cp_reg_list_10[reg].reg_name,
9280 						   adev->gfx.ip_dump_compute_queues[index + reg]);
9281 				}
9282 				index += reg_count;
9283 			}
9284 		}
9285 	}
9286 
9287 	/* print gfx queue registers for all instances */
9288 	if (!adev->gfx.ip_dump_gfx_queues)
9289 		return;
9290 
9291 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9292 	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9293 		   adev->gfx.me.num_me,
9294 		   adev->gfx.me.num_pipe_per_me,
9295 		   adev->gfx.me.num_queue_per_pipe);
9296 
9297 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9298 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9299 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9300 				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9301 				for (reg = 0; reg < reg_count; reg++) {
9302 					drm_printf(p, "%-50s \t 0x%08x\n",
9303 						   gc_gfx_queue_reg_list_10[reg].reg_name,
9304 						   adev->gfx.ip_dump_gfx_queues[index + reg]);
9305 				}
9306 				index += reg_count;
9307 			}
9308 		}
9309 	}
9310 }
9311 
9312 static void gfx_v10_ip_dump(void *handle)
9313 {
9314 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9315 	uint32_t i, j, k, reg, index = 0;
9316 	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9317 
9318 	if (!adev->gfx.ip_dump_core)
9319 		return;
9320 
9321 	amdgpu_gfx_off_ctrl(adev, false);
9322 	for (i = 0; i < reg_count; i++)
9323 		adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9324 	amdgpu_gfx_off_ctrl(adev, true);
9325 
9326 	/* dump compute queue registers for all instances */
9327 	if (!adev->gfx.ip_dump_compute_queues)
9328 		return;
9329 
9330 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9331 	amdgpu_gfx_off_ctrl(adev, false);
9332 	mutex_lock(&adev->srbm_mutex);
9333 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9334 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9335 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9336 				/* ME0 is for GFX so start from 1 for CP */
9337 				nv_grbm_select(adev, 1 + i, j, k, 0);
9338 
9339 				for (reg = 0; reg < reg_count; reg++) {
9340 					adev->gfx.ip_dump_compute_queues[index + reg] =
9341 						RREG32(SOC15_REG_ENTRY_OFFSET(
9342 							gc_cp_reg_list_10[reg]));
9343 				}
9344 				index += reg_count;
9345 			}
9346 		}
9347 	}
9348 	nv_grbm_select(adev, 0, 0, 0, 0);
9349 	mutex_unlock(&adev->srbm_mutex);
9350 	amdgpu_gfx_off_ctrl(adev, true);
9351 
9352 	/* dump gfx queue registers for all instances */
9353 	if (!adev->gfx.ip_dump_gfx_queues)
9354 		return;
9355 
9356 	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9357 	amdgpu_gfx_off_ctrl(adev, false);
9358 	mutex_lock(&adev->srbm_mutex);
9359 	for (i = 0; i < adev->gfx.me.num_me; i++) {
9360 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9361 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9362 				nv_grbm_select(adev, i, j, k, 0);
9363 
9364 				for (reg = 0; reg < reg_count; reg++) {
9365 					adev->gfx.ip_dump_gfx_queues[index + reg] =
9366 						RREG32(SOC15_REG_ENTRY_OFFSET(
9367 							gc_gfx_queue_reg_list_10[reg]));
9368 				}
9369 				index += reg_count;
9370 			}
9371 		}
9372 	}
9373 	nv_grbm_select(adev, 0, 0, 0, 0);
9374 	mutex_unlock(&adev->srbm_mutex);
9375 	amdgpu_gfx_off_ctrl(adev, true);
9376 }
9377 
9378 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9379 	.name = "gfx_v10_0",
9380 	.early_init = gfx_v10_0_early_init,
9381 	.late_init = gfx_v10_0_late_init,
9382 	.sw_init = gfx_v10_0_sw_init,
9383 	.sw_fini = gfx_v10_0_sw_fini,
9384 	.hw_init = gfx_v10_0_hw_init,
9385 	.hw_fini = gfx_v10_0_hw_fini,
9386 	.suspend = gfx_v10_0_suspend,
9387 	.resume = gfx_v10_0_resume,
9388 	.is_idle = gfx_v10_0_is_idle,
9389 	.wait_for_idle = gfx_v10_0_wait_for_idle,
9390 	.soft_reset = gfx_v10_0_soft_reset,
9391 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
9392 	.set_powergating_state = gfx_v10_0_set_powergating_state,
9393 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
9394 	.dump_ip_state = gfx_v10_ip_dump,
9395 	.print_ip_state = gfx_v10_ip_print,
9396 };
9397 
9398 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9399 	.type = AMDGPU_RING_TYPE_GFX,
9400 	.align_mask = 0xff,
9401 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9402 	.support_64bit_ptrs = true,
9403 	.secure_submission_supported = true,
9404 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9405 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9406 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9407 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
9408 		5 + /* COND_EXEC */
9409 		7 + /* PIPELINE_SYNC */
9410 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9411 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9412 		4 + /* VM_FLUSH */
9413 		8 + /* FENCE for VM_FLUSH */
9414 		20 + /* GDS switch */
9415 		4 + /* double SWITCH_BUFFER,
9416 		     * the first COND_EXEC jump to the place
9417 		     * just prior to this double SWITCH_BUFFER
9418 		     */
9419 		5 + /* COND_EXEC */
9420 		7 + /* HDP_flush */
9421 		4 + /* VGT_flush */
9422 		14 + /*	CE_META */
9423 		31 + /*	DE_META */
9424 		3 + /* CNTX_CTRL */
9425 		5 + /* HDP_INVL */
9426 		8 + 8 + /* FENCE x2 */
9427 		2 + /* SWITCH_BUFFER */
9428 		8, /* gfx_v10_0_emit_mem_sync */
9429 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
9430 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9431 	.emit_fence = gfx_v10_0_ring_emit_fence,
9432 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9433 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9434 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9435 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9436 	.test_ring = gfx_v10_0_ring_test_ring,
9437 	.test_ib = gfx_v10_0_ring_test_ib,
9438 	.insert_nop = amdgpu_ring_insert_nop,
9439 	.pad_ib = amdgpu_ring_generic_pad_ib,
9440 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9441 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9442 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9443 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
9444 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9445 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9446 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9447 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9448 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9449 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9450 };
9451 
9452 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9453 	.type = AMDGPU_RING_TYPE_COMPUTE,
9454 	.align_mask = 0xff,
9455 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9456 	.support_64bit_ptrs = true,
9457 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9458 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9459 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9460 	.emit_frame_size =
9461 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9462 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9463 		5 + /* hdp invalidate */
9464 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9465 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9466 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9467 		2 + /* gfx_v10_0_ring_emit_vm_flush */
9468 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9469 		8, /* gfx_v10_0_emit_mem_sync */
9470 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9471 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9472 	.emit_fence = gfx_v10_0_ring_emit_fence,
9473 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9474 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9475 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9476 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9477 	.test_ring = gfx_v10_0_ring_test_ring,
9478 	.test_ib = gfx_v10_0_ring_test_ib,
9479 	.insert_nop = amdgpu_ring_insert_nop,
9480 	.pad_ib = amdgpu_ring_generic_pad_ib,
9481 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9482 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9483 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9484 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9485 };
9486 
9487 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9488 	.type = AMDGPU_RING_TYPE_KIQ,
9489 	.align_mask = 0xff,
9490 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9491 	.support_64bit_ptrs = true,
9492 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9493 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9494 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9495 	.emit_frame_size =
9496 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9497 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9498 		5 + /*hdp invalidate */
9499 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9500 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9501 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9502 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9503 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9504 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9505 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9506 	.test_ring = gfx_v10_0_ring_test_ring,
9507 	.test_ib = gfx_v10_0_ring_test_ib,
9508 	.insert_nop = amdgpu_ring_insert_nop,
9509 	.pad_ib = amdgpu_ring_generic_pad_ib,
9510 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
9511 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9512 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9513 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9514 };
9515 
9516 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9517 {
9518 	int i;
9519 
9520 	adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9521 
9522 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9523 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9524 
9525 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
9526 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9527 }
9528 
9529 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9530 	.set = gfx_v10_0_set_eop_interrupt_state,
9531 	.process = gfx_v10_0_eop_irq,
9532 };
9533 
9534 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9535 	.set = gfx_v10_0_set_priv_reg_fault_state,
9536 	.process = gfx_v10_0_priv_reg_irq,
9537 };
9538 
9539 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9540 	.set = gfx_v10_0_set_priv_inst_fault_state,
9541 	.process = gfx_v10_0_priv_inst_irq,
9542 };
9543 
9544 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9545 	.set = gfx_v10_0_kiq_set_interrupt_state,
9546 	.process = gfx_v10_0_kiq_irq,
9547 };
9548 
9549 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9550 {
9551 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9552 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9553 
9554 	adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9555 	adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9556 
9557 	adev->gfx.priv_reg_irq.num_types = 1;
9558 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9559 
9560 	adev->gfx.priv_inst_irq.num_types = 1;
9561 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9562 }
9563 
9564 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9565 {
9566 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9567 	case IP_VERSION(10, 1, 10):
9568 	case IP_VERSION(10, 1, 1):
9569 	case IP_VERSION(10, 1, 3):
9570 	case IP_VERSION(10, 1, 4):
9571 	case IP_VERSION(10, 3, 2):
9572 	case IP_VERSION(10, 3, 1):
9573 	case IP_VERSION(10, 3, 4):
9574 	case IP_VERSION(10, 3, 5):
9575 	case IP_VERSION(10, 3, 6):
9576 	case IP_VERSION(10, 3, 3):
9577 	case IP_VERSION(10, 3, 7):
9578 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9579 		break;
9580 	case IP_VERSION(10, 1, 2):
9581 	case IP_VERSION(10, 3, 0):
9582 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9583 		break;
9584 	default:
9585 		break;
9586 	}
9587 }
9588 
9589 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9590 {
9591 	unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9592 			    adev->gfx.config.max_sh_per_se *
9593 			    adev->gfx.config.max_shader_engines;
9594 
9595 	adev->gds.gds_size = 0x10000;
9596 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9597 	adev->gds.gws_size = 64;
9598 	adev->gds.oa_size = 16;
9599 }
9600 
9601 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9602 {
9603 	/* set gfx eng mqd */
9604 	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9605 		sizeof(struct v10_gfx_mqd);
9606 	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9607 		gfx_v10_0_gfx_mqd_init;
9608 	/* set compute eng mqd */
9609 	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9610 		sizeof(struct v10_compute_mqd);
9611 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9612 		gfx_v10_0_compute_mqd_init;
9613 }
9614 
9615 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9616 							  u32 bitmap)
9617 {
9618 	u32 data;
9619 
9620 	if (!bitmap)
9621 		return;
9622 
9623 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9624 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9625 
9626 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9627 }
9628 
9629 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9630 {
9631 	u32 disabled_mask =
9632 		~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9633 	u32 efuse_setting = 0;
9634 	u32 vbios_setting = 0;
9635 
9636 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9637 	efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9638 	efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9639 
9640 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9641 	vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9642 	vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9643 
9644 	disabled_mask |= efuse_setting | vbios_setting;
9645 
9646 	return (~disabled_mask);
9647 }
9648 
9649 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9650 {
9651 	u32 wgp_idx, wgp_active_bitmap;
9652 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
9653 
9654 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9655 	cu_active_bitmap = 0;
9656 
9657 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9658 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
9659 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9660 		if (wgp_active_bitmap & (1 << wgp_idx))
9661 			cu_active_bitmap |= cu_bitmap_per_wgp;
9662 	}
9663 
9664 	return cu_active_bitmap;
9665 }
9666 
9667 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9668 				 struct amdgpu_cu_info *cu_info)
9669 {
9670 	int i, j, k, counter, active_cu_number = 0;
9671 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9672 	unsigned int disable_masks[4 * 2];
9673 
9674 	if (!adev || !cu_info)
9675 		return -EINVAL;
9676 
9677 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9678 
9679 	mutex_lock(&adev->grbm_idx_mutex);
9680 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9681 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9682 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
9683 			if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
9684 			      IP_VERSION(10, 3, 0)) ||
9685 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9686 			      IP_VERSION(10, 3, 3)) ||
9687 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9688 			      IP_VERSION(10, 3, 6)) ||
9689 			     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9690 			      IP_VERSION(10, 3, 7))) &&
9691 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9692 				continue;
9693 			mask = 1;
9694 			ao_bitmap = 0;
9695 			counter = 0;
9696 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9697 			if (i < 4 && j < 2)
9698 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9699 					adev, disable_masks[i * 2 + j]);
9700 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9701 			cu_info->bitmap[0][i][j] = bitmap;
9702 
9703 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9704 				if (bitmap & mask) {
9705 					if (counter < adev->gfx.config.max_cu_per_sh)
9706 						ao_bitmap |= mask;
9707 					counter++;
9708 				}
9709 				mask <<= 1;
9710 			}
9711 			active_cu_number += counter;
9712 			if (i < 2 && j < 2)
9713 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9714 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9715 		}
9716 	}
9717 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9718 	mutex_unlock(&adev->grbm_idx_mutex);
9719 
9720 	cu_info->number = active_cu_number;
9721 	cu_info->ao_cu_mask = ao_cu_mask;
9722 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9723 
9724 	return 0;
9725 }
9726 
9727 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9728 {
9729 	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9730 
9731 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9732 	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9733 	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9734 
9735 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9736 	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9737 	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9738 
9739 	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9740 						adev->gfx.config.max_shader_engines);
9741 	disabled_sa = efuse_setting | vbios_setting;
9742 	disabled_sa &= max_sa_mask;
9743 
9744 	return disabled_sa;
9745 }
9746 
9747 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9748 {
9749 	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9750 	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9751 
9752 	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9753 
9754 	max_sa_per_se = adev->gfx.config.max_sh_per_se;
9755 	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9756 	max_shader_engines = adev->gfx.config.max_shader_engines;
9757 
9758 	for (se_index = 0; max_shader_engines > se_index; se_index++) {
9759 		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9760 		disabled_sa_per_se &= max_sa_per_se_mask;
9761 		if (disabled_sa_per_se == max_sa_per_se_mask) {
9762 			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9763 			break;
9764 		}
9765 	}
9766 }
9767 
9768 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9769 {
9770 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9771 		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9772 		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9773 		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9774 
9775 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9776 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9777 		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9778 		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9779 		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9780 		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9781 
9782 	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9783 		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9784 		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9785 		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9786 
9787 	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9788 
9789 	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9790 		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9791 }
9792 
9793 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9794 	.type = AMD_IP_BLOCK_TYPE_GFX,
9795 	.major = 10,
9796 	.minor = 0,
9797 	.rev = 0,
9798 	.funcs = &gfx_v10_0_ip_funcs,
9799 };
9800