1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "gfx_v10_0_cleaner_shader.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 372 /* SE status registers */ 373 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 374 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 375 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 376 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 377 }; 378 379 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 380 /* compute registers */ 381 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 382 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 383 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 384 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 385 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS), 420 /* cp header registers */ 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 425 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 426 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 427 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 428 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 429 }; 430 431 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 432 /* gfx queue registers */ 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 452 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 453 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 454 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 455 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), 456 /* gfx header registers */ 457 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 458 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 459 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 460 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 461 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 462 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 463 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 464 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 465 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 466 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 467 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 468 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 469 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 470 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 471 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 472 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 473 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 474 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 475 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 476 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 477 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 478 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 479 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 480 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 481 }; 482 483 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 524 }; 525 526 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 527 /* Pending on emulation bring up */ 528 }; 529 530 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1583 }; 1584 1585 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1624 }; 1625 1626 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1669 }; 1670 1671 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1672 /* Pending on emulation bring up */ 1673 }; 1674 1675 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2296 }; 2297 2298 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2299 /* Pending on emulation bring up */ 2300 }; 2301 2302 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3355 }; 3356 3357 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3401 }; 3402 3403 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3404 /* Pending on emulation bring up */ 3405 }; 3406 3407 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3449 3450 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3452 }; 3453 3454 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3479 3480 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3482 }; 3483 3484 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3505 }; 3506 3507 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3544 }; 3545 3546 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3579 }; 3580 3581 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3616 }; 3617 3618 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3641 }; 3642 3643 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3666 }; 3667 3668 #define DEFAULT_SH_MEM_CONFIG \ 3669 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3670 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3671 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3672 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3673 3674 /* TODO: pending on golden setting value of gb address config */ 3675 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3676 3677 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3678 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3679 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3680 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3681 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3682 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3683 struct amdgpu_cu_info *cu_info); 3684 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3685 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3686 u32 sh_num, u32 instance, int xcc_id); 3687 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3688 3689 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3690 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3691 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3692 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3693 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3694 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3695 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3696 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3697 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3698 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3699 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3700 uint16_t pasid, uint32_t flush_type, 3701 bool all_hub, uint8_t dst_sel); 3702 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3703 unsigned int vmid); 3704 3705 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3706 enum amd_powergating_state state); 3707 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3708 { 3709 struct amdgpu_device *adev = kiq_ring->adev; 3710 u64 shader_mc_addr; 3711 3712 /* Cleaner shader MC address */ 3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 3714 3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3717 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3724 } 3725 3726 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3727 struct amdgpu_ring *ring) 3728 { 3729 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3730 uint64_t wptr_addr = ring->wptr_gpu_addr; 3731 uint32_t eng_sel = 0; 3732 3733 switch (ring->funcs->type) { 3734 case AMDGPU_RING_TYPE_COMPUTE: 3735 eng_sel = 0; 3736 break; 3737 case AMDGPU_RING_TYPE_GFX: 3738 eng_sel = 4; 3739 break; 3740 case AMDGPU_RING_TYPE_MES: 3741 eng_sel = 5; 3742 break; 3743 default: 3744 WARN_ON(1); 3745 } 3746 3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3748 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3750 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3751 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3752 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3753 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3754 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3755 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3756 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3757 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3758 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3759 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3760 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3761 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3762 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3763 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3764 } 3765 3766 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3767 struct amdgpu_ring *ring, 3768 enum amdgpu_unmap_queues_action action, 3769 u64 gpu_addr, u64 seq) 3770 { 3771 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3772 3773 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3774 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3775 PACKET3_UNMAP_QUEUES_ACTION(action) | 3776 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3777 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3778 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3779 amdgpu_ring_write(kiq_ring, 3780 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3781 3782 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3783 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3784 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3785 amdgpu_ring_write(kiq_ring, seq); 3786 } else { 3787 amdgpu_ring_write(kiq_ring, 0); 3788 amdgpu_ring_write(kiq_ring, 0); 3789 amdgpu_ring_write(kiq_ring, 0); 3790 } 3791 } 3792 3793 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3794 struct amdgpu_ring *ring, 3795 u64 addr, 3796 u64 seq) 3797 { 3798 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3799 3800 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3801 amdgpu_ring_write(kiq_ring, 3802 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3803 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3804 PACKET3_QUERY_STATUS_COMMAND(2)); 3805 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3806 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3807 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3808 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3809 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3810 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3811 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3812 } 3813 3814 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3815 uint16_t pasid, uint32_t flush_type, 3816 bool all_hub) 3817 { 3818 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3819 } 3820 3821 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 3822 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 3823 uint32_t xcc_id, uint32_t vmid) 3824 { 3825 struct amdgpu_device *adev = kiq_ring->adev; 3826 unsigned i; 3827 uint32_t tmp; 3828 3829 /* enter save mode */ 3830 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3831 mutex_lock(&adev->srbm_mutex); 3832 nv_grbm_select(adev, me_id, pipe_id, queue_id, 0); 3833 3834 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 3835 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2); 3836 WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1); 3837 /* wait till dequeue take effects */ 3838 for (i = 0; i < adev->usec_timeout; i++) { 3839 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3840 break; 3841 udelay(1); 3842 } 3843 if (i >= adev->usec_timeout) 3844 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 3845 } else if (queue_type == AMDGPU_RING_TYPE_GFX) { 3846 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 3847 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 3848 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 3849 if (pipe_id == 0) 3850 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 3851 else 3852 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 3853 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp); 3854 3855 /* wait till dequeue take effects */ 3856 for (i = 0; i < adev->usec_timeout; i++) { 3857 if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1)) 3858 break; 3859 udelay(1); 3860 } 3861 if (i >= adev->usec_timeout) 3862 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 3863 } else { 3864 dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type); 3865 } 3866 3867 nv_grbm_select(adev, 0, 0, 0, 0); 3868 mutex_unlock(&adev->srbm_mutex); 3869 /* exit safe mode */ 3870 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 3871 } 3872 3873 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3874 .kiq_set_resources = gfx10_kiq_set_resources, 3875 .kiq_map_queues = gfx10_kiq_map_queues, 3876 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3877 .kiq_query_status = gfx10_kiq_query_status, 3878 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3879 .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue, 3880 .set_resources_size = 8, 3881 .map_queues_size = 7, 3882 .unmap_queues_size = 6, 3883 .query_status_size = 7, 3884 .invalidate_tlbs_size = 2, 3885 }; 3886 3887 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3888 { 3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3890 } 3891 3892 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3893 { 3894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3895 case IP_VERSION(10, 1, 10): 3896 soc15_program_register_sequence(adev, 3897 golden_settings_gc_rlc_spm_10_0_nv10, 3898 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3899 break; 3900 case IP_VERSION(10, 1, 1): 3901 soc15_program_register_sequence(adev, 3902 golden_settings_gc_rlc_spm_10_1_nv14, 3903 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3904 break; 3905 case IP_VERSION(10, 1, 2): 3906 soc15_program_register_sequence(adev, 3907 golden_settings_gc_rlc_spm_10_1_2_nv12, 3908 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3909 break; 3910 default: 3911 break; 3912 } 3913 } 3914 3915 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3916 { 3917 if (amdgpu_sriov_vf(adev)) 3918 return; 3919 3920 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3921 case IP_VERSION(10, 1, 10): 3922 soc15_program_register_sequence(adev, 3923 golden_settings_gc_10_1, 3924 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3925 soc15_program_register_sequence(adev, 3926 golden_settings_gc_10_0_nv10, 3927 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3928 break; 3929 case IP_VERSION(10, 1, 1): 3930 soc15_program_register_sequence(adev, 3931 golden_settings_gc_10_1_1, 3932 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3933 soc15_program_register_sequence(adev, 3934 golden_settings_gc_10_1_nv14, 3935 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3936 break; 3937 case IP_VERSION(10, 1, 2): 3938 soc15_program_register_sequence(adev, 3939 golden_settings_gc_10_1_2, 3940 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3941 soc15_program_register_sequence(adev, 3942 golden_settings_gc_10_1_2_nv12, 3943 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3944 break; 3945 case IP_VERSION(10, 3, 0): 3946 soc15_program_register_sequence(adev, 3947 golden_settings_gc_10_3, 3948 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3949 soc15_program_register_sequence(adev, 3950 golden_settings_gc_10_3_sienna_cichlid, 3951 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3952 break; 3953 case IP_VERSION(10, 3, 2): 3954 soc15_program_register_sequence(adev, 3955 golden_settings_gc_10_3_2, 3956 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3957 break; 3958 case IP_VERSION(10, 3, 1): 3959 soc15_program_register_sequence(adev, 3960 golden_settings_gc_10_3_vangogh, 3961 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3962 break; 3963 case IP_VERSION(10, 3, 3): 3964 soc15_program_register_sequence(adev, 3965 golden_settings_gc_10_3_3, 3966 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3967 break; 3968 case IP_VERSION(10, 3, 4): 3969 soc15_program_register_sequence(adev, 3970 golden_settings_gc_10_3_4, 3971 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3972 break; 3973 case IP_VERSION(10, 3, 5): 3974 soc15_program_register_sequence(adev, 3975 golden_settings_gc_10_3_5, 3976 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3977 break; 3978 case IP_VERSION(10, 1, 3): 3979 case IP_VERSION(10, 1, 4): 3980 soc15_program_register_sequence(adev, 3981 golden_settings_gc_10_0_cyan_skillfish, 3982 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3983 break; 3984 case IP_VERSION(10, 3, 6): 3985 soc15_program_register_sequence(adev, 3986 golden_settings_gc_10_3_6, 3987 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3988 break; 3989 case IP_VERSION(10, 3, 7): 3990 soc15_program_register_sequence(adev, 3991 golden_settings_gc_10_3_7, 3992 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3993 break; 3994 default: 3995 break; 3996 } 3997 gfx_v10_0_init_spm_golden_registers(adev); 3998 } 3999 4000 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 4001 bool wc, uint32_t reg, uint32_t val) 4002 { 4003 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4004 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 4006 amdgpu_ring_write(ring, reg); 4007 amdgpu_ring_write(ring, 0); 4008 amdgpu_ring_write(ring, val); 4009 } 4010 4011 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 4012 int mem_space, int opt, uint32_t addr0, 4013 uint32_t addr1, uint32_t ref, uint32_t mask, 4014 uint32_t inv) 4015 { 4016 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4017 amdgpu_ring_write(ring, 4018 /* memory (1) or register (0) */ 4019 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 4020 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 4021 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 4022 WAIT_REG_MEM_ENGINE(eng_sel))); 4023 4024 if (mem_space) 4025 WARN_ON(addr0 & 0x3); /* Dword align */ 4026 amdgpu_ring_write(ring, addr0); 4027 amdgpu_ring_write(ring, addr1); 4028 amdgpu_ring_write(ring, ref); 4029 amdgpu_ring_write(ring, mask); 4030 amdgpu_ring_write(ring, inv); /* poll interval */ 4031 } 4032 4033 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 4034 { 4035 struct amdgpu_device *adev = ring->adev; 4036 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4037 uint32_t tmp = 0; 4038 unsigned int i; 4039 int r; 4040 4041 WREG32(scratch, 0xCAFEDEAD); 4042 r = amdgpu_ring_alloc(ring, 3); 4043 if (r) { 4044 drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", 4045 ring->idx, r); 4046 return r; 4047 } 4048 4049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 4050 amdgpu_ring_write(ring, scratch - 4051 PACKET3_SET_UCONFIG_REG_START); 4052 amdgpu_ring_write(ring, 0xDEADBEEF); 4053 amdgpu_ring_commit(ring); 4054 4055 for (i = 0; i < adev->usec_timeout; i++) { 4056 tmp = RREG32(scratch); 4057 if (tmp == 0xDEADBEEF) 4058 break; 4059 if (amdgpu_emu_mode == 1) 4060 msleep(1); 4061 else 4062 udelay(1); 4063 } 4064 4065 if (i >= adev->usec_timeout) 4066 r = -ETIMEDOUT; 4067 4068 return r; 4069 } 4070 4071 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 4072 { 4073 struct amdgpu_device *adev = ring->adev; 4074 struct amdgpu_ib ib; 4075 struct dma_fence *f = NULL; 4076 unsigned int index; 4077 uint64_t gpu_addr; 4078 uint32_t *cpu_ptr; 4079 long r; 4080 4081 memset(&ib, 0, sizeof(ib)); 4082 4083 r = amdgpu_wb_get(adev, &index); 4084 if (r) 4085 return r; 4086 4087 gpu_addr = adev->wb.gpu_addr + (index * 4); 4088 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4089 cpu_ptr = &adev->wb.wb[index]; 4090 4091 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4092 if (r) { 4093 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 4094 goto err1; 4095 } 4096 4097 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4099 ib.ptr[2] = lower_32_bits(gpu_addr); 4100 ib.ptr[3] = upper_32_bits(gpu_addr); 4101 ib.ptr[4] = 0xDEADBEEF; 4102 ib.length_dw = 5; 4103 4104 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4105 if (r) 4106 goto err2; 4107 4108 r = dma_fence_wait_timeout(f, false, timeout); 4109 if (r == 0) { 4110 r = -ETIMEDOUT; 4111 goto err2; 4112 } else if (r < 0) { 4113 goto err2; 4114 } 4115 4116 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4117 r = 0; 4118 else 4119 r = -EINVAL; 4120 err2: 4121 amdgpu_ib_free(&ib, NULL); 4122 dma_fence_put(f); 4123 err1: 4124 amdgpu_wb_free(adev, index); 4125 return r; 4126 } 4127 4128 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4129 { 4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4131 amdgpu_ucode_release(&adev->gfx.me_fw); 4132 amdgpu_ucode_release(&adev->gfx.ce_fw); 4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4134 amdgpu_ucode_release(&adev->gfx.mec_fw); 4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4136 4137 kfree(adev->gfx.rlc.register_list_format); 4138 } 4139 4140 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4141 { 4142 adev->gfx.cp_fw_write_wait = false; 4143 4144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4145 case IP_VERSION(10, 1, 10): 4146 case IP_VERSION(10, 1, 2): 4147 case IP_VERSION(10, 1, 1): 4148 case IP_VERSION(10, 1, 3): 4149 case IP_VERSION(10, 1, 4): 4150 if ((adev->gfx.me_fw_version >= 0x00000046) && 4151 (adev->gfx.me_feature_version >= 27) && 4152 (adev->gfx.pfp_fw_version >= 0x00000068) && 4153 (adev->gfx.pfp_feature_version >= 27) && 4154 (adev->gfx.mec_fw_version >= 0x0000005b) && 4155 (adev->gfx.mec_feature_version >= 27)) 4156 adev->gfx.cp_fw_write_wait = true; 4157 break; 4158 case IP_VERSION(10, 3, 0): 4159 case IP_VERSION(10, 3, 2): 4160 case IP_VERSION(10, 3, 1): 4161 case IP_VERSION(10, 3, 4): 4162 case IP_VERSION(10, 3, 5): 4163 case IP_VERSION(10, 3, 6): 4164 case IP_VERSION(10, 3, 3): 4165 case IP_VERSION(10, 3, 7): 4166 adev->gfx.cp_fw_write_wait = true; 4167 break; 4168 default: 4169 break; 4170 } 4171 4172 if (!adev->gfx.cp_fw_write_wait) 4173 drm_warn_once(adev_to_drm(adev), "CP firmware version too old, please update!"); 4174 } 4175 4176 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4177 { 4178 bool ret = false; 4179 4180 switch (adev->pdev->revision) { 4181 case 0xc2: 4182 case 0xc3: 4183 ret = true; 4184 break; 4185 default: 4186 ret = false; 4187 break; 4188 } 4189 4190 return ret; 4191 } 4192 4193 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4194 { 4195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4196 case IP_VERSION(10, 1, 10): 4197 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4198 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4199 break; 4200 default: 4201 break; 4202 } 4203 } 4204 4205 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4206 { 4207 char fw_name[53]; 4208 char ucode_prefix[30]; 4209 const char *wks = ""; 4210 int err; 4211 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4212 uint16_t version_major; 4213 uint16_t version_minor; 4214 4215 DRM_DEBUG("\n"); 4216 4217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4218 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4219 wks = "_wks"; 4220 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4221 4222 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4223 AMDGPU_UCODE_REQUIRED, 4224 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4225 if (err) 4226 goto out; 4227 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4228 4229 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4230 AMDGPU_UCODE_REQUIRED, 4231 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4232 if (err) 4233 goto out; 4234 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4235 4236 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4237 AMDGPU_UCODE_REQUIRED, 4238 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4239 if (err) 4240 goto out; 4241 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4242 4243 if (!amdgpu_sriov_vf(adev)) { 4244 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4245 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4246 if (err) 4247 goto out; 4248 4249 /* don't validate this firmware. There are apparently firmwares 4250 * in the wild with incorrect size in the header 4251 */ 4252 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4253 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4254 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4255 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4256 if (err) 4257 goto out; 4258 } 4259 4260 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4261 AMDGPU_UCODE_REQUIRED, 4262 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4263 if (err) 4264 goto out; 4265 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4266 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4267 4268 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4269 AMDGPU_UCODE_REQUIRED, 4270 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4271 if (!err) { 4272 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4274 } else { 4275 err = 0; 4276 adev->gfx.mec2_fw = NULL; 4277 } 4278 4279 gfx_v10_0_check_fw_write_wait(adev); 4280 out: 4281 if (err) { 4282 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4283 amdgpu_ucode_release(&adev->gfx.me_fw); 4284 amdgpu_ucode_release(&adev->gfx.ce_fw); 4285 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4286 amdgpu_ucode_release(&adev->gfx.mec_fw); 4287 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4288 } 4289 4290 gfx_v10_0_check_gfxoff_flag(adev); 4291 4292 return err; 4293 } 4294 4295 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4296 { 4297 u32 count = 0; 4298 const struct cs_section_def *sect = NULL; 4299 const struct cs_extent_def *ext = NULL; 4300 4301 /* begin clear state */ 4302 count += 2; 4303 /* context control state */ 4304 count += 3; 4305 4306 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4307 for (ext = sect->section; ext->extent != NULL; ++ext) { 4308 if (sect->id == SECT_CONTEXT) 4309 count += 2 + ext->reg_count; 4310 else 4311 return 0; 4312 } 4313 } 4314 4315 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4316 count += 3; 4317 /* end clear state */ 4318 count += 2; 4319 /* clear state */ 4320 count += 2; 4321 4322 return count; 4323 } 4324 4325 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 4326 { 4327 u32 count = 0; 4328 int ctx_reg_offset; 4329 4330 if (adev->gfx.rlc.cs_data == NULL) 4331 return; 4332 if (buffer == NULL) 4333 return; 4334 4335 count = amdgpu_gfx_csb_preamble_start(buffer); 4336 count = amdgpu_gfx_csb_data_parser(adev, buffer, count); 4337 4338 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4339 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4340 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4341 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4342 4343 amdgpu_gfx_csb_preamble_end(buffer, count); 4344 } 4345 4346 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4347 { 4348 /* clear state block */ 4349 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4350 &adev->gfx.rlc.clear_state_gpu_addr, 4351 (void **)&adev->gfx.rlc.cs_ptr); 4352 4353 /* jump table block */ 4354 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4355 &adev->gfx.rlc.cp_table_gpu_addr, 4356 (void **)&adev->gfx.rlc.cp_table_ptr); 4357 } 4358 4359 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4360 { 4361 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4362 4363 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4364 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4365 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4366 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4367 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4368 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4369 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4371 case IP_VERSION(10, 3, 0): 4372 reg_access_ctrl->spare_int = 4373 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4374 break; 4375 default: 4376 reg_access_ctrl->spare_int = 4377 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4378 break; 4379 } 4380 adev->gfx.rlc.rlcg_reg_access_supported = true; 4381 } 4382 4383 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4384 { 4385 const struct cs_section_def *cs_data; 4386 int r; 4387 4388 adev->gfx.rlc.cs_data = gfx10_cs_data; 4389 4390 cs_data = adev->gfx.rlc.cs_data; 4391 4392 if (cs_data) { 4393 /* init clear state block */ 4394 r = amdgpu_gfx_rlc_init_csb(adev); 4395 if (r) 4396 return r; 4397 } 4398 4399 return 0; 4400 } 4401 4402 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4403 { 4404 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4405 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4406 } 4407 4408 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4409 { 4410 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4411 4412 amdgpu_gfx_graphics_queue_acquire(adev); 4413 } 4414 4415 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4416 { 4417 int r; 4418 u32 *hpd; 4419 const __le32 *fw_data = NULL; 4420 unsigned int fw_size; 4421 u32 *fw = NULL; 4422 size_t mec_hpd_size; 4423 4424 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4425 4426 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4427 4428 /* take ownership of the relevant compute queues */ 4429 amdgpu_gfx_compute_queue_acquire(adev); 4430 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4431 4432 if (mec_hpd_size) { 4433 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4434 AMDGPU_GEM_DOMAIN_GTT, 4435 &adev->gfx.mec.hpd_eop_obj, 4436 &adev->gfx.mec.hpd_eop_gpu_addr, 4437 (void **)&hpd); 4438 if (r) { 4439 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4440 gfx_v10_0_mec_fini(adev); 4441 return r; 4442 } 4443 4444 memset(hpd, 0, mec_hpd_size); 4445 4446 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4447 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4448 } 4449 4450 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4451 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4452 4453 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4454 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4455 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4456 4457 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4459 &adev->gfx.mec.mec_fw_obj, 4460 &adev->gfx.mec.mec_fw_gpu_addr, 4461 (void **)&fw); 4462 if (r) { 4463 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4464 gfx_v10_0_mec_fini(adev); 4465 return r; 4466 } 4467 4468 memcpy(fw, fw_data, fw_size); 4469 4470 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4472 } 4473 4474 return 0; 4475 } 4476 4477 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4478 { 4479 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4480 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4481 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4482 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4483 } 4484 4485 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4486 uint32_t thread, uint32_t regno, 4487 uint32_t num, uint32_t *out) 4488 { 4489 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4490 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4491 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4492 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4493 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4494 while (num--) 4495 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4496 } 4497 4498 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4499 { 4500 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4501 * field when performing a select_se_sh so it should be 4502 * zero here 4503 */ 4504 WARN_ON(simd != 0); 4505 4506 /* type 2 wave data */ 4507 dst[(*no_fields)++] = 2; 4508 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4513 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4514 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4515 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4516 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4517 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4518 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4519 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4520 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4521 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4522 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4523 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4524 } 4525 4526 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4527 uint32_t wave, uint32_t start, 4528 uint32_t size, uint32_t *dst) 4529 { 4530 WARN_ON(simd != 0); 4531 4532 wave_read_regs( 4533 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4534 dst); 4535 } 4536 4537 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4538 uint32_t wave, uint32_t thread, 4539 uint32_t start, uint32_t size, 4540 uint32_t *dst) 4541 { 4542 wave_read_regs( 4543 adev, wave, thread, 4544 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4545 } 4546 4547 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4548 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4549 { 4550 nv_grbm_select(adev, me, pipe, q, vm); 4551 } 4552 4553 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4554 bool enable) 4555 { 4556 uint32_t data, def; 4557 4558 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4559 4560 if (enable) 4561 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4562 else 4563 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4564 4565 if (data != def) 4566 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4567 } 4568 4569 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4570 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4571 .select_se_sh = &gfx_v10_0_select_se_sh, 4572 .read_wave_data = &gfx_v10_0_read_wave_data, 4573 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4574 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4575 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4576 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4577 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4578 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 4579 }; 4580 4581 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4582 { 4583 u32 gb_addr_config = 0; 4584 4585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4586 case IP_VERSION(10, 1, 10): 4587 case IP_VERSION(10, 1, 1): 4588 case IP_VERSION(10, 1, 2): 4589 adev->gfx.config.max_hw_contexts = 8; 4590 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4591 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4592 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4593 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4594 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4595 break; 4596 case IP_VERSION(10, 3, 0): 4597 case IP_VERSION(10, 3, 2): 4598 case IP_VERSION(10, 3, 1): 4599 case IP_VERSION(10, 3, 4): 4600 case IP_VERSION(10, 3, 5): 4601 case IP_VERSION(10, 3, 6): 4602 case IP_VERSION(10, 3, 3): 4603 case IP_VERSION(10, 3, 7): 4604 adev->gfx.config.max_hw_contexts = 8; 4605 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4606 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4607 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4608 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4609 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4610 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4611 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4612 break; 4613 case IP_VERSION(10, 1, 3): 4614 case IP_VERSION(10, 1, 4): 4615 adev->gfx.config.max_hw_contexts = 8; 4616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4617 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4620 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4621 break; 4622 default: 4623 dev_warn(adev->dev, "Unsupported GC version 0x%08x\n", 4624 amdgpu_ip_version(adev, GC_HWIP, 0)); 4625 return; 4626 } 4627 4628 adev->gfx.config.gb_addr_config = gb_addr_config; 4629 4630 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4631 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4632 GB_ADDR_CONFIG, NUM_PIPES); 4633 4634 adev->gfx.config.max_tile_pipes = 4635 adev->gfx.config.gb_addr_config_fields.num_pipes; 4636 4637 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4638 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4639 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4640 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4641 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4642 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4643 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4644 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4645 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4646 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4647 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4648 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4649 } 4650 4651 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4652 int me, int pipe, int queue) 4653 { 4654 struct amdgpu_ring *ring; 4655 unsigned int irq_type; 4656 unsigned int hw_prio; 4657 4658 ring = &adev->gfx.gfx_ring[ring_id]; 4659 4660 ring->me = me; 4661 ring->pipe = pipe; 4662 ring->queue = queue; 4663 4664 ring->ring_obj = NULL; 4665 ring->use_doorbell = true; 4666 4667 if (!ring_id) 4668 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4669 else 4670 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4671 ring->vm_hub = AMDGPU_GFXHUB(0); 4672 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4673 4674 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4675 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4676 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4677 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4678 hw_prio, NULL); 4679 } 4680 4681 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4682 int mec, int pipe, int queue) 4683 { 4684 unsigned int irq_type; 4685 struct amdgpu_ring *ring; 4686 unsigned int hw_prio; 4687 4688 ring = &adev->gfx.compute_ring[ring_id]; 4689 4690 /* mec0 is me1 */ 4691 ring->me = mec + 1; 4692 ring->pipe = pipe; 4693 ring->queue = queue; 4694 4695 ring->ring_obj = NULL; 4696 ring->use_doorbell = true; 4697 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4698 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4699 + (ring_id * GFX10_MEC_HPD_SIZE); 4700 ring->vm_hub = AMDGPU_GFXHUB(0); 4701 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4702 4703 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4704 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4705 + ring->pipe; 4706 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4707 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4708 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4709 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4710 hw_prio, NULL); 4711 } 4712 4713 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4714 { 4715 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4716 uint32_t *ptr; 4717 uint32_t inst; 4718 4719 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4720 if (!ptr) { 4721 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4722 adev->gfx.ip_dump_core = NULL; 4723 } else { 4724 adev->gfx.ip_dump_core = ptr; 4725 } 4726 4727 /* Allocate memory for compute queue registers for all the instances */ 4728 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4729 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4730 adev->gfx.mec.num_queue_per_pipe; 4731 4732 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4733 if (!ptr) { 4734 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4735 adev->gfx.ip_dump_compute_queues = NULL; 4736 } else { 4737 adev->gfx.ip_dump_compute_queues = ptr; 4738 } 4739 4740 /* Allocate memory for gfx queue registers for all the instances */ 4741 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4742 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4743 adev->gfx.me.num_queue_per_pipe; 4744 4745 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4746 if (!ptr) { 4747 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4748 adev->gfx.ip_dump_gfx_queues = NULL; 4749 } else { 4750 adev->gfx.ip_dump_gfx_queues = ptr; 4751 } 4752 } 4753 4754 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 4755 { 4756 int i, j, k, r, ring_id = 0; 4757 int xcc_id = 0; 4758 struct amdgpu_device *adev = ip_block->adev; 4759 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 4760 4761 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 4762 4763 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4764 case IP_VERSION(10, 1, 10): 4765 case IP_VERSION(10, 1, 1): 4766 case IP_VERSION(10, 1, 2): 4767 case IP_VERSION(10, 1, 3): 4768 case IP_VERSION(10, 1, 4): 4769 adev->gfx.me.num_me = 1; 4770 adev->gfx.me.num_pipe_per_me = 1; 4771 adev->gfx.me.num_queue_per_pipe = 8; 4772 adev->gfx.mec.num_mec = 2; 4773 adev->gfx.mec.num_pipe_per_mec = 4; 4774 adev->gfx.mec.num_queue_per_pipe = 8; 4775 break; 4776 case IP_VERSION(10, 3, 0): 4777 case IP_VERSION(10, 3, 2): 4778 case IP_VERSION(10, 3, 1): 4779 case IP_VERSION(10, 3, 4): 4780 case IP_VERSION(10, 3, 5): 4781 case IP_VERSION(10, 3, 6): 4782 case IP_VERSION(10, 3, 3): 4783 case IP_VERSION(10, 3, 7): 4784 adev->gfx.me.num_me = 1; 4785 adev->gfx.me.num_pipe_per_me = 2; 4786 adev->gfx.me.num_queue_per_pipe = 2; 4787 adev->gfx.mec.num_mec = 2; 4788 adev->gfx.mec.num_pipe_per_mec = 4; 4789 adev->gfx.mec.num_queue_per_pipe = 4; 4790 break; 4791 default: 4792 adev->gfx.me.num_me = 1; 4793 adev->gfx.me.num_pipe_per_me = 1; 4794 adev->gfx.me.num_queue_per_pipe = 1; 4795 adev->gfx.mec.num_mec = 1; 4796 adev->gfx.mec.num_pipe_per_mec = 4; 4797 adev->gfx.mec.num_queue_per_pipe = 8; 4798 break; 4799 } 4800 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4801 case IP_VERSION(10, 1, 10): 4802 case IP_VERSION(10, 1, 1): 4803 case IP_VERSION(10, 1, 2): 4804 adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex; 4805 adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex); 4806 if (adev->gfx.me_fw_version >= 101 && 4807 adev->gfx.pfp_fw_version >= 158 && 4808 adev->gfx.mec_fw_version >= 151) { 4809 adev->gfx.enable_cleaner_shader = true; 4810 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4811 if (r) { 4812 adev->gfx.enable_cleaner_shader = false; 4813 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4814 } 4815 } 4816 break; 4817 case IP_VERSION(10, 3, 0): 4818 case IP_VERSION(10, 3, 1): 4819 case IP_VERSION(10, 3, 2): 4820 case IP_VERSION(10, 3, 3): 4821 case IP_VERSION(10, 3, 4): 4822 case IP_VERSION(10, 3, 5): 4823 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4824 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4825 if (adev->gfx.me_fw_version >= 64 && 4826 adev->gfx.pfp_fw_version >= 100 && 4827 adev->gfx.mec_fw_version >= 122) { 4828 adev->gfx.enable_cleaner_shader = true; 4829 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4830 if (r) { 4831 adev->gfx.enable_cleaner_shader = false; 4832 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4833 } 4834 } 4835 break; 4836 case IP_VERSION(10, 3, 6): 4837 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4838 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4839 if (adev->gfx.me_fw_version >= 14 && 4840 adev->gfx.pfp_fw_version >= 17 && 4841 adev->gfx.mec_fw_version >= 24) { 4842 adev->gfx.enable_cleaner_shader = true; 4843 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4844 if (r) { 4845 adev->gfx.enable_cleaner_shader = false; 4846 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4847 } 4848 } 4849 break; 4850 case IP_VERSION(10, 3, 7): 4851 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; 4852 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); 4853 if (adev->gfx.me_fw_version >= 4 && 4854 adev->gfx.pfp_fw_version >= 9 && 4855 adev->gfx.mec_fw_version >= 12) { 4856 adev->gfx.enable_cleaner_shader = true; 4857 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 4858 if (r) { 4859 adev->gfx.enable_cleaner_shader = false; 4860 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 4861 } 4862 } 4863 break; 4864 default: 4865 adev->gfx.enable_cleaner_shader = false; 4866 break; 4867 } 4868 4869 /* KIQ event */ 4870 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4871 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4872 &adev->gfx.kiq[0].irq); 4873 if (r) 4874 return r; 4875 4876 /* EOP Event */ 4877 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4878 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4879 &adev->gfx.eop_irq); 4880 if (r) 4881 return r; 4882 4883 /* Bad opcode Event */ 4884 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4885 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4886 &adev->gfx.bad_op_irq); 4887 if (r) 4888 return r; 4889 4890 /* Privileged reg */ 4891 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4892 &adev->gfx.priv_reg_irq); 4893 if (r) 4894 return r; 4895 4896 /* Privileged inst */ 4897 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4898 &adev->gfx.priv_inst_irq); 4899 if (r) 4900 return r; 4901 4902 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4903 4904 gfx_v10_0_me_init(adev); 4905 4906 if (adev->gfx.rlc.funcs) { 4907 if (adev->gfx.rlc.funcs->init) { 4908 r = adev->gfx.rlc.funcs->init(adev); 4909 if (r) { 4910 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4911 return r; 4912 } 4913 } 4914 } 4915 4916 r = gfx_v10_0_mec_init(adev); 4917 if (r) { 4918 DRM_ERROR("Failed to init MEC BOs!\n"); 4919 return r; 4920 } 4921 4922 /* set up the gfx ring */ 4923 for (i = 0; i < adev->gfx.me.num_me; i++) { 4924 for (j = 0; j < num_queue_per_pipe; j++) { 4925 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4926 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4927 continue; 4928 4929 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4930 i, k, j); 4931 if (r) 4932 return r; 4933 ring_id++; 4934 } 4935 } 4936 } 4937 4938 ring_id = 0; 4939 /* set up the compute queues - allocate horizontally across pipes */ 4940 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4941 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4942 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4943 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4944 k, j)) 4945 continue; 4946 4947 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4948 i, k, j); 4949 if (r) 4950 return r; 4951 4952 ring_id++; 4953 } 4954 } 4955 } 4956 4957 adev->gfx.gfx_supported_reset = 4958 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4959 adev->gfx.compute_supported_reset = 4960 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4961 if (!amdgpu_sriov_vf(adev) && 4962 !adev->debug_disable_gpu_ring_reset) { 4963 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4964 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4965 } 4966 4967 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4968 if (r) { 4969 DRM_ERROR("Failed to init KIQ BOs!\n"); 4970 return r; 4971 } 4972 4973 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4974 if (r) 4975 return r; 4976 4977 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4978 if (r) 4979 return r; 4980 4981 /* allocate visible FB for rlc auto-loading fw */ 4982 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4983 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4984 if (r) 4985 return r; 4986 } 4987 4988 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4989 4990 gfx_v10_0_gpu_early_init(adev); 4991 4992 r = amdgpu_gfx_sysfs_init(adev); 4993 if (r) 4994 return r; 4995 4996 gfx_v10_0_alloc_ip_dump(adev); 4997 4998 return 0; 4999 } 5000 5001 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 5002 { 5003 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 5004 &adev->gfx.pfp.pfp_fw_gpu_addr, 5005 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5006 } 5007 5008 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 5009 { 5010 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 5011 &adev->gfx.ce.ce_fw_gpu_addr, 5012 (void **)&adev->gfx.ce.ce_fw_ptr); 5013 } 5014 5015 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 5016 { 5017 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 5018 &adev->gfx.me.me_fw_gpu_addr, 5019 (void **)&adev->gfx.me.me_fw_ptr); 5020 } 5021 5022 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 5023 { 5024 int i; 5025 struct amdgpu_device *adev = ip_block->adev; 5026 5027 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5028 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 5029 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5030 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 5031 5032 amdgpu_gfx_mqd_sw_fini(adev, 0); 5033 5034 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 5035 amdgpu_gfx_kiq_fini(adev, 0); 5036 5037 amdgpu_gfx_cleaner_shader_sw_fini(adev); 5038 5039 gfx_v10_0_pfp_fini(adev); 5040 gfx_v10_0_ce_fini(adev); 5041 gfx_v10_0_me_fini(adev); 5042 gfx_v10_0_rlc_fini(adev); 5043 gfx_v10_0_mec_fini(adev); 5044 5045 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 5046 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 5047 5048 gfx_v10_0_free_microcode(adev); 5049 amdgpu_gfx_sysfs_fini(adev); 5050 5051 kfree(adev->gfx.ip_dump_core); 5052 kfree(adev->gfx.ip_dump_compute_queues); 5053 kfree(adev->gfx.ip_dump_gfx_queues); 5054 5055 return 0; 5056 } 5057 5058 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 5059 u32 sh_num, u32 instance, int xcc_id) 5060 { 5061 u32 data; 5062 5063 if (instance == 0xffffffff) 5064 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 5065 INSTANCE_BROADCAST_WRITES, 1); 5066 else 5067 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 5068 instance); 5069 5070 if (se_num == 0xffffffff) 5071 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 5072 1); 5073 else 5074 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 5075 5076 if (sh_num == 0xffffffff) 5077 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 5078 1); 5079 else 5080 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 5081 5082 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 5083 } 5084 5085 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 5086 { 5087 u32 data, mask; 5088 5089 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5090 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5091 5092 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5093 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5094 5095 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5096 adev->gfx.config.max_sh_per_se); 5097 5098 return (~data) & mask; 5099 } 5100 5101 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5102 { 5103 int i, j; 5104 u32 data; 5105 u32 active_rbs = 0; 5106 u32 bitmap; 5107 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5108 adev->gfx.config.max_sh_per_se; 5109 5110 mutex_lock(&adev->grbm_idx_mutex); 5111 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5112 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5113 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5114 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 5115 IP_VERSION(10, 3, 0)) || 5116 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5117 IP_VERSION(10, 3, 3)) || 5118 (amdgpu_ip_version(adev, GC_HWIP, 0) == 5119 IP_VERSION(10, 3, 6))) && 5120 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5121 continue; 5122 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5123 data = gfx_v10_0_get_rb_active_bitmap(adev); 5124 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5125 rb_bitmap_width_per_sh); 5126 } 5127 } 5128 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5129 mutex_unlock(&adev->grbm_idx_mutex); 5130 5131 adev->gfx.config.backend_enable_mask = active_rbs; 5132 adev->gfx.config.num_rbs = hweight32(active_rbs); 5133 } 5134 5135 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5136 { 5137 uint32_t num_sc; 5138 uint32_t enabled_rb_per_sh; 5139 uint32_t active_rb_bitmap; 5140 uint32_t num_rb_per_sc; 5141 uint32_t num_packer_per_sc; 5142 uint32_t pa_sc_tile_steering_override; 5143 5144 /* for ASICs that integrates GFX v10.3 5145 * pa_sc_tile_steering_override should be set to 0 5146 */ 5147 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 5148 return 0; 5149 5150 /* init num_sc */ 5151 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5152 adev->gfx.config.num_sc_per_sh; 5153 /* init num_rb_per_sc */ 5154 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5155 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5156 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5157 /* init num_packer_per_sc */ 5158 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5159 5160 pa_sc_tile_steering_override = 0; 5161 pa_sc_tile_steering_override |= 5162 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5163 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5164 pa_sc_tile_steering_override |= 5165 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5166 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5167 pa_sc_tile_steering_override |= 5168 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5169 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5170 5171 return pa_sc_tile_steering_override; 5172 } 5173 5174 #define DEFAULT_SH_MEM_BASES (0x6000) 5175 5176 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5177 uint32_t first_vmid, 5178 uint32_t last_vmid) 5179 { 5180 uint32_t data; 5181 uint32_t trap_config_vmid_mask = 0; 5182 int i; 5183 5184 /* Calculate trap config vmid mask */ 5185 for (i = first_vmid; i < last_vmid; i++) 5186 trap_config_vmid_mask |= (1 << i); 5187 5188 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5189 VMID_SEL, trap_config_vmid_mask); 5190 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5191 TRAP_EN, 1); 5192 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5193 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5194 5195 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5196 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5197 } 5198 5199 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5200 { 5201 int i; 5202 uint32_t sh_mem_bases; 5203 5204 /* 5205 * Configure apertures: 5206 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5207 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5208 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5209 */ 5210 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5211 5212 mutex_lock(&adev->srbm_mutex); 5213 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5214 nv_grbm_select(adev, 0, 0, 0, i); 5215 /* CP and shaders */ 5216 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5217 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5218 } 5219 nv_grbm_select(adev, 0, 0, 0, 0); 5220 mutex_unlock(&adev->srbm_mutex); 5221 5222 /* 5223 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5224 * access. These should be enabled by FW for target VMIDs. 5225 */ 5226 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5227 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5228 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5229 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5230 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5231 } 5232 5233 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5234 AMDGPU_NUM_VMID); 5235 } 5236 5237 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5238 { 5239 int vmid; 5240 5241 /* 5242 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5243 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5244 * the driver can enable them for graphics. VMID0 should maintain 5245 * access so that HWS firmware can save/restore entries. 5246 */ 5247 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5248 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5249 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5250 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5251 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5252 } 5253 } 5254 5255 5256 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5257 { 5258 int i, j, k; 5259 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5260 u32 tmp, wgp_active_bitmap = 0; 5261 u32 gcrd_targets_disable_tcp = 0; 5262 u32 utcl_invreq_disable = 0; 5263 /* 5264 * GCRD_TARGETS_DISABLE field contains 5265 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5266 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5267 */ 5268 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5269 2 * max_wgp_per_sh + /* TCP */ 5270 max_wgp_per_sh + /* SQC */ 5271 4); /* GL1C */ 5272 /* 5273 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5274 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5275 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5276 */ 5277 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5278 2 * max_wgp_per_sh + /* TCP */ 5279 2 * max_wgp_per_sh + /* SQC */ 5280 4 + /* RMI */ 5281 1); /* SQG */ 5282 5283 mutex_lock(&adev->grbm_idx_mutex); 5284 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5285 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5286 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5287 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5288 /* 5289 * Set corresponding TCP bits for the inactive WGPs in 5290 * GCRD_SA_TARGETS_DISABLE 5291 */ 5292 gcrd_targets_disable_tcp = 0; 5293 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5294 utcl_invreq_disable = 0; 5295 5296 for (k = 0; k < max_wgp_per_sh; k++) { 5297 if (!(wgp_active_bitmap & (1 << k))) { 5298 gcrd_targets_disable_tcp |= 3 << (2 * k); 5299 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5300 utcl_invreq_disable |= (3 << (2 * k)) | 5301 (3 << (2 * (max_wgp_per_sh + k))); 5302 } 5303 } 5304 5305 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5306 /* only override TCP & SQC bits */ 5307 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5308 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5309 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5310 5311 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5312 /* only override TCP & SQC bits */ 5313 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5314 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5315 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5316 } 5317 } 5318 5319 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5320 mutex_unlock(&adev->grbm_idx_mutex); 5321 } 5322 5323 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5324 { 5325 /* TCCs are global (not instanced). */ 5326 uint32_t tcc_disable; 5327 5328 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5329 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5330 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5331 } else { 5332 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5333 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5334 } 5335 5336 adev->gfx.config.tcc_disabled_mask = 5337 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5338 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5339 } 5340 5341 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5342 { 5343 u32 tmp; 5344 int i; 5345 5346 if (!amdgpu_sriov_vf(adev)) 5347 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5348 5349 gfx_v10_0_setup_rb(adev); 5350 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5351 gfx_v10_0_get_tcc_info(adev); 5352 adev->gfx.config.pa_sc_tile_steering_override = 5353 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5354 /* Program DB_RING_CONTROL for multiple GFX pipes 5355 * Default power up value is 1. 5356 * Possible values: 5357 * 0 - split occlusion counters between gfx pipes 5358 * 1 - all occlusion counters to pipe 0 5359 * 2 - all occlusion counters to pipe 1 5360 */ 5361 WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, 5362 (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); 5363 5364 /* XXX SH_MEM regs */ 5365 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5366 mutex_lock(&adev->srbm_mutex); 5367 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5368 nv_grbm_select(adev, 0, 0, 0, i); 5369 /* CP and shaders */ 5370 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5371 if (i != 0) { 5372 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5373 (adev->gmc.private_aperture_start >> 48)); 5374 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5375 (adev->gmc.shared_aperture_start >> 48)); 5376 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5377 } 5378 } 5379 nv_grbm_select(adev, 0, 0, 0, 0); 5380 5381 mutex_unlock(&adev->srbm_mutex); 5382 5383 gfx_v10_0_init_compute_vmid(adev); 5384 gfx_v10_0_init_gds_vmid(adev); 5385 5386 } 5387 5388 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5389 int me, int pipe) 5390 { 5391 if (me != 0) 5392 return 0; 5393 5394 switch (pipe) { 5395 case 0: 5396 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5397 case 1: 5398 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5399 default: 5400 return 0; 5401 } 5402 } 5403 5404 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5405 int me, int pipe) 5406 { 5407 /* 5408 * amdgpu controls only the first MEC. That's why this function only 5409 * handles the setting of interrupts for this specific MEC. All other 5410 * pipes' interrupts are set by amdkfd. 5411 */ 5412 if (me != 1) 5413 return 0; 5414 5415 switch (pipe) { 5416 case 0: 5417 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5418 case 1: 5419 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5420 case 2: 5421 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5422 case 3: 5423 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5424 default: 5425 return 0; 5426 } 5427 } 5428 5429 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5430 bool enable) 5431 { 5432 u32 tmp, cp_int_cntl_reg; 5433 int i, j; 5434 5435 if (amdgpu_sriov_vf(adev)) 5436 return; 5437 5438 for (i = 0; i < adev->gfx.me.num_me; i++) { 5439 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5440 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5441 5442 if (cp_int_cntl_reg) { 5443 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5444 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5445 enable ? 1 : 0); 5446 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5447 enable ? 1 : 0); 5448 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5449 enable ? 1 : 0); 5450 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5451 enable ? 1 : 0); 5452 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5453 } 5454 } 5455 } 5456 } 5457 5458 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5459 { 5460 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5461 5462 /* csib */ 5463 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5464 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5465 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5466 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5467 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5468 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5469 } else { 5470 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5471 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5472 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5473 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5474 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5475 } 5476 return 0; 5477 } 5478 5479 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5480 { 5481 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5482 5483 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5484 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5485 } 5486 5487 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5488 { 5489 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5490 udelay(50); 5491 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5492 udelay(50); 5493 } 5494 5495 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5496 bool enable) 5497 { 5498 uint32_t rlc_pg_cntl; 5499 5500 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5501 5502 if (!enable) { 5503 /* RLC_PG_CNTL[23] = 0 (default) 5504 * RLC will wait for handshake acks with SMU 5505 * GFXOFF will be enabled 5506 * RLC_PG_CNTL[23] = 1 5507 * RLC will not issue any message to SMU 5508 * hence no handshake between SMU & RLC 5509 * GFXOFF will be disabled 5510 */ 5511 rlc_pg_cntl |= 0x800000; 5512 } else 5513 rlc_pg_cntl &= ~0x800000; 5514 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5515 } 5516 5517 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5518 { 5519 /* 5520 * TODO: enable rlc & smu handshake until smu 5521 * and gfxoff feature works as expected 5522 */ 5523 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5524 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5525 5526 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5527 udelay(50); 5528 } 5529 5530 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5531 { 5532 uint32_t tmp; 5533 5534 /* enable Save Restore Machine */ 5535 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5536 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5537 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5538 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5539 } 5540 5541 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5542 { 5543 const struct rlc_firmware_header_v2_0 *hdr; 5544 const __le32 *fw_data; 5545 unsigned int i, fw_size; 5546 5547 if (!adev->gfx.rlc_fw) 5548 return -EINVAL; 5549 5550 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5551 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5552 5553 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5554 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5555 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5556 5557 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5558 RLCG_UCODE_LOADING_START_ADDRESS); 5559 5560 for (i = 0; i < fw_size; i++) 5561 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5562 le32_to_cpup(fw_data++)); 5563 5564 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5565 5566 return 0; 5567 } 5568 5569 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5570 { 5571 int r; 5572 5573 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5574 adev->psp.autoload_supported) { 5575 5576 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5577 if (r) 5578 return r; 5579 5580 gfx_v10_0_init_csb(adev); 5581 5582 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5583 5584 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5585 gfx_v10_0_rlc_enable_srm(adev); 5586 } else { 5587 if (amdgpu_sriov_vf(adev)) { 5588 gfx_v10_0_init_csb(adev); 5589 return 0; 5590 } 5591 5592 adev->gfx.rlc.funcs->stop(adev); 5593 5594 /* disable CG */ 5595 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5596 5597 /* disable PG */ 5598 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5599 5600 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5601 /* legacy rlc firmware loading */ 5602 r = gfx_v10_0_rlc_load_microcode(adev); 5603 if (r) 5604 return r; 5605 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5606 /* rlc backdoor autoload firmware */ 5607 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5608 if (r) 5609 return r; 5610 } 5611 5612 gfx_v10_0_init_csb(adev); 5613 5614 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5615 5616 adev->gfx.rlc.funcs->start(adev); 5617 5618 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5619 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5620 if (r) 5621 return r; 5622 } 5623 } 5624 5625 return 0; 5626 } 5627 5628 static struct { 5629 FIRMWARE_ID id; 5630 unsigned int offset; 5631 unsigned int size; 5632 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5633 5634 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5635 { 5636 int ret; 5637 RLC_TABLE_OF_CONTENT *rlc_toc; 5638 5639 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5640 AMDGPU_GEM_DOMAIN_GTT, 5641 &adev->gfx.rlc.rlc_toc_bo, 5642 &adev->gfx.rlc.rlc_toc_gpu_addr, 5643 (void **)&adev->gfx.rlc.rlc_toc_buf); 5644 if (ret) { 5645 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5646 return ret; 5647 } 5648 5649 /* Copy toc from psp sos fw to rlc toc buffer */ 5650 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5651 5652 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5653 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5654 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5655 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5656 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5657 /* Offset needs 4KB alignment */ 5658 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5659 } 5660 5661 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5662 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5663 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5664 5665 rlc_toc++; 5666 } 5667 5668 return 0; 5669 } 5670 5671 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5672 { 5673 uint32_t total_size = 0; 5674 FIRMWARE_ID id; 5675 int ret; 5676 5677 ret = gfx_v10_0_parse_rlc_toc(adev); 5678 if (ret) { 5679 dev_err(adev->dev, "failed to parse rlc toc\n"); 5680 return 0; 5681 } 5682 5683 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5684 total_size += rlc_autoload_info[id].size; 5685 5686 /* In case the offset in rlc toc ucode is aligned */ 5687 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5688 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5689 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5690 5691 return total_size; 5692 } 5693 5694 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5695 { 5696 int r; 5697 uint32_t total_size; 5698 5699 total_size = gfx_v10_0_calc_toc_total_size(adev); 5700 5701 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5702 AMDGPU_GEM_DOMAIN_GTT, 5703 &adev->gfx.rlc.rlc_autoload_bo, 5704 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5705 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5706 if (r) { 5707 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5708 return r; 5709 } 5710 5711 return 0; 5712 } 5713 5714 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5715 { 5716 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5717 &adev->gfx.rlc.rlc_toc_gpu_addr, 5718 (void **)&adev->gfx.rlc.rlc_toc_buf); 5719 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5720 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5721 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5722 } 5723 5724 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5725 FIRMWARE_ID id, 5726 const void *fw_data, 5727 uint32_t fw_size) 5728 { 5729 uint32_t toc_offset; 5730 uint32_t toc_fw_size; 5731 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5732 5733 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5734 return; 5735 5736 toc_offset = rlc_autoload_info[id].offset; 5737 toc_fw_size = rlc_autoload_info[id].size; 5738 5739 if (fw_size == 0) 5740 fw_size = toc_fw_size; 5741 5742 if (fw_size > toc_fw_size) 5743 fw_size = toc_fw_size; 5744 5745 memcpy(ptr + toc_offset, fw_data, fw_size); 5746 5747 if (fw_size < toc_fw_size) 5748 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5749 } 5750 5751 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5752 { 5753 void *data; 5754 uint32_t size; 5755 5756 data = adev->gfx.rlc.rlc_toc_buf; 5757 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5758 5759 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5760 FIRMWARE_ID_RLC_TOC, 5761 data, size); 5762 } 5763 5764 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5765 { 5766 const __le32 *fw_data; 5767 uint32_t fw_size; 5768 const struct gfx_firmware_header_v1_0 *cp_hdr; 5769 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5770 5771 /* pfp ucode */ 5772 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5773 adev->gfx.pfp_fw->data; 5774 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5775 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5776 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5777 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5778 FIRMWARE_ID_CP_PFP, 5779 fw_data, fw_size); 5780 5781 /* ce ucode */ 5782 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5783 adev->gfx.ce_fw->data; 5784 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5785 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5786 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5787 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5788 FIRMWARE_ID_CP_CE, 5789 fw_data, fw_size); 5790 5791 /* me ucode */ 5792 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5793 adev->gfx.me_fw->data; 5794 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5795 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5796 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5797 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5798 FIRMWARE_ID_CP_ME, 5799 fw_data, fw_size); 5800 5801 /* rlc ucode */ 5802 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5803 adev->gfx.rlc_fw->data; 5804 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5805 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5806 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5807 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5808 FIRMWARE_ID_RLC_G_UCODE, 5809 fw_data, fw_size); 5810 5811 /* mec1 ucode */ 5812 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5813 adev->gfx.mec_fw->data; 5814 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5815 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5816 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5817 cp_hdr->jt_size * 4; 5818 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5819 FIRMWARE_ID_CP_MEC, 5820 fw_data, fw_size); 5821 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5822 } 5823 5824 /* Temporarily put sdma part here */ 5825 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5826 { 5827 const __le32 *fw_data; 5828 uint32_t fw_size; 5829 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5830 int i; 5831 5832 for (i = 0; i < adev->sdma.num_instances; i++) { 5833 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5834 adev->sdma.instance[i].fw->data; 5835 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5836 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5837 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5838 5839 if (i == 0) { 5840 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5841 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5842 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5843 FIRMWARE_ID_SDMA0_JT, 5844 (uint32_t *)fw_data + 5845 sdma_hdr->jt_offset, 5846 sdma_hdr->jt_size * 4); 5847 } else if (i == 1) { 5848 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5849 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5850 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5851 FIRMWARE_ID_SDMA1_JT, 5852 (uint32_t *)fw_data + 5853 sdma_hdr->jt_offset, 5854 sdma_hdr->jt_size * 4); 5855 } 5856 } 5857 } 5858 5859 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5860 { 5861 uint32_t rlc_g_offset, rlc_g_size, tmp; 5862 uint64_t gpu_addr; 5863 5864 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5865 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5866 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5867 5868 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5869 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5870 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5871 5872 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5873 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5874 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5875 5876 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5877 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5878 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5879 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5880 return -EINVAL; 5881 } 5882 5883 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5884 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5885 DRM_ERROR("RLC ROM should halt itself\n"); 5886 return -EINVAL; 5887 } 5888 5889 return 0; 5890 } 5891 5892 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5893 { 5894 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5895 uint32_t tmp; 5896 int i; 5897 uint64_t addr; 5898 5899 /* Trigger an invalidation of the L1 instruction caches */ 5900 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5901 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5902 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5903 5904 /* Wait for invalidation complete */ 5905 for (i = 0; i < usec_timeout; i++) { 5906 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5907 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5908 INVALIDATE_CACHE_COMPLETE)) 5909 break; 5910 udelay(1); 5911 } 5912 5913 if (i >= usec_timeout) { 5914 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5915 return -EINVAL; 5916 } 5917 5918 /* Program me ucode address into intruction cache address register */ 5919 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5920 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5921 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5922 lower_32_bits(addr) & 0xFFFFF000); 5923 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5924 upper_32_bits(addr)); 5925 5926 return 0; 5927 } 5928 5929 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5930 { 5931 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5932 uint32_t tmp; 5933 int i; 5934 uint64_t addr; 5935 5936 /* Trigger an invalidation of the L1 instruction caches */ 5937 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5938 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5939 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5940 5941 /* Wait for invalidation complete */ 5942 for (i = 0; i < usec_timeout; i++) { 5943 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5944 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5945 INVALIDATE_CACHE_COMPLETE)) 5946 break; 5947 udelay(1); 5948 } 5949 5950 if (i >= usec_timeout) { 5951 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5952 return -EINVAL; 5953 } 5954 5955 /* Program ce ucode address into intruction cache address register */ 5956 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5957 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5958 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5959 lower_32_bits(addr) & 0xFFFFF000); 5960 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5961 upper_32_bits(addr)); 5962 5963 return 0; 5964 } 5965 5966 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5967 { 5968 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5969 uint32_t tmp; 5970 int i; 5971 uint64_t addr; 5972 5973 /* Trigger an invalidation of the L1 instruction caches */ 5974 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5975 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5976 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5977 5978 /* Wait for invalidation complete */ 5979 for (i = 0; i < usec_timeout; i++) { 5980 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5981 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5982 INVALIDATE_CACHE_COMPLETE)) 5983 break; 5984 udelay(1); 5985 } 5986 5987 if (i >= usec_timeout) { 5988 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5989 return -EINVAL; 5990 } 5991 5992 /* Program pfp ucode address into intruction cache address register */ 5993 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5994 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5995 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5996 lower_32_bits(addr) & 0xFFFFF000); 5997 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5998 upper_32_bits(addr)); 5999 6000 return 0; 6001 } 6002 6003 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 6004 { 6005 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6006 uint32_t tmp; 6007 int i; 6008 uint64_t addr; 6009 6010 /* Trigger an invalidation of the L1 instruction caches */ 6011 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6012 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6013 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6014 6015 /* Wait for invalidation complete */ 6016 for (i = 0; i < usec_timeout; i++) { 6017 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6018 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6019 INVALIDATE_CACHE_COMPLETE)) 6020 break; 6021 udelay(1); 6022 } 6023 6024 if (i >= usec_timeout) { 6025 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6026 return -EINVAL; 6027 } 6028 6029 /* Program mec1 ucode address into intruction cache address register */ 6030 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 6031 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 6032 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 6033 lower_32_bits(addr) & 0xFFFFF000); 6034 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6035 upper_32_bits(addr)); 6036 6037 return 0; 6038 } 6039 6040 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 6041 { 6042 uint32_t cp_status; 6043 uint32_t bootload_status; 6044 int i, r; 6045 6046 for (i = 0; i < adev->usec_timeout; i++) { 6047 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 6048 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 6049 if ((cp_status == 0) && 6050 (REG_GET_FIELD(bootload_status, 6051 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 6052 break; 6053 } 6054 udelay(1); 6055 } 6056 6057 if (i >= adev->usec_timeout) { 6058 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 6059 return -ETIMEDOUT; 6060 } 6061 6062 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 6063 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 6064 if (r) 6065 return r; 6066 6067 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 6068 if (r) 6069 return r; 6070 6071 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 6072 if (r) 6073 return r; 6074 6075 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 6076 if (r) 6077 return r; 6078 } 6079 6080 return 0; 6081 } 6082 6083 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 6084 { 6085 int i; 6086 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 6087 6088 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 6089 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 6090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 6091 6092 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 6093 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 6094 else 6095 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 6096 6097 if (amdgpu_in_reset(adev) && !enable) 6098 return 0; 6099 6100 for (i = 0; i < adev->usec_timeout; i++) { 6101 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 6102 break; 6103 udelay(1); 6104 } 6105 6106 if (i >= adev->usec_timeout) 6107 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 6108 6109 return 0; 6110 } 6111 6112 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 6113 { 6114 int r; 6115 const struct gfx_firmware_header_v1_0 *pfp_hdr; 6116 const __le32 *fw_data; 6117 unsigned int i, fw_size; 6118 uint32_t tmp; 6119 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6120 6121 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 6122 adev->gfx.pfp_fw->data; 6123 6124 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 6125 6126 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 6127 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 6128 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 6129 6130 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 6131 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6132 &adev->gfx.pfp.pfp_fw_obj, 6133 &adev->gfx.pfp.pfp_fw_gpu_addr, 6134 (void **)&adev->gfx.pfp.pfp_fw_ptr); 6135 if (r) { 6136 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 6137 gfx_v10_0_pfp_fini(adev); 6138 return r; 6139 } 6140 6141 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6142 6143 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6144 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6145 6146 /* Trigger an invalidation of the L1 instruction caches */ 6147 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6148 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6149 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6150 6151 /* Wait for invalidation complete */ 6152 for (i = 0; i < usec_timeout; i++) { 6153 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6154 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6155 INVALIDATE_CACHE_COMPLETE)) 6156 break; 6157 udelay(1); 6158 } 6159 6160 if (i >= usec_timeout) { 6161 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6162 return -EINVAL; 6163 } 6164 6165 if (amdgpu_emu_mode == 1) 6166 amdgpu_device_flush_hdp(adev, NULL); 6167 6168 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6169 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6170 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6171 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6172 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6173 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6174 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6175 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6176 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6177 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6178 6179 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6180 6181 for (i = 0; i < pfp_hdr->jt_size; i++) 6182 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6183 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6184 6185 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6186 6187 return 0; 6188 } 6189 6190 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6191 { 6192 int r; 6193 const struct gfx_firmware_header_v1_0 *ce_hdr; 6194 const __le32 *fw_data; 6195 unsigned int i, fw_size; 6196 uint32_t tmp; 6197 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6198 6199 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6200 adev->gfx.ce_fw->data; 6201 6202 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6203 6204 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6205 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6206 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6207 6208 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6209 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6210 &adev->gfx.ce.ce_fw_obj, 6211 &adev->gfx.ce.ce_fw_gpu_addr, 6212 (void **)&adev->gfx.ce.ce_fw_ptr); 6213 if (r) { 6214 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6215 gfx_v10_0_ce_fini(adev); 6216 return r; 6217 } 6218 6219 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6220 6221 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6222 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6223 6224 /* Trigger an invalidation of the L1 instruction caches */ 6225 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6226 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6227 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6228 6229 /* Wait for invalidation complete */ 6230 for (i = 0; i < usec_timeout; i++) { 6231 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6232 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6233 INVALIDATE_CACHE_COMPLETE)) 6234 break; 6235 udelay(1); 6236 } 6237 6238 if (i >= usec_timeout) { 6239 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6240 return -EINVAL; 6241 } 6242 6243 if (amdgpu_emu_mode == 1) 6244 amdgpu_device_flush_hdp(adev, NULL); 6245 6246 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6247 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6248 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6249 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6250 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6251 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6252 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6253 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6254 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6255 6256 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6257 6258 for (i = 0; i < ce_hdr->jt_size; i++) 6259 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6260 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6261 6262 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6263 6264 return 0; 6265 } 6266 6267 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6268 { 6269 int r; 6270 const struct gfx_firmware_header_v1_0 *me_hdr; 6271 const __le32 *fw_data; 6272 unsigned int i, fw_size; 6273 uint32_t tmp; 6274 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6275 6276 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6277 adev->gfx.me_fw->data; 6278 6279 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6280 6281 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6282 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6283 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6284 6285 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6286 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6287 &adev->gfx.me.me_fw_obj, 6288 &adev->gfx.me.me_fw_gpu_addr, 6289 (void **)&adev->gfx.me.me_fw_ptr); 6290 if (r) { 6291 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6292 gfx_v10_0_me_fini(adev); 6293 return r; 6294 } 6295 6296 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6297 6298 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6299 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6300 6301 /* Trigger an invalidation of the L1 instruction caches */ 6302 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6303 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6304 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6305 6306 /* Wait for invalidation complete */ 6307 for (i = 0; i < usec_timeout; i++) { 6308 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6309 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6310 INVALIDATE_CACHE_COMPLETE)) 6311 break; 6312 udelay(1); 6313 } 6314 6315 if (i >= usec_timeout) { 6316 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6317 return -EINVAL; 6318 } 6319 6320 if (amdgpu_emu_mode == 1) 6321 amdgpu_device_flush_hdp(adev, NULL); 6322 6323 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6324 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6325 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6326 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6327 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6328 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6329 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6330 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6331 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6332 6333 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6334 6335 for (i = 0; i < me_hdr->jt_size; i++) 6336 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6337 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6338 6339 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6340 6341 return 0; 6342 } 6343 6344 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6345 { 6346 int r; 6347 6348 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6349 return -EINVAL; 6350 6351 gfx_v10_0_cp_gfx_enable(adev, false); 6352 6353 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6354 if (r) { 6355 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6356 return r; 6357 } 6358 6359 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6360 if (r) { 6361 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6362 return r; 6363 } 6364 6365 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6366 if (r) { 6367 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6368 return r; 6369 } 6370 6371 return 0; 6372 } 6373 6374 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6375 { 6376 struct amdgpu_ring *ring; 6377 const struct cs_section_def *sect = NULL; 6378 const struct cs_extent_def *ext = NULL; 6379 int r, i; 6380 int ctx_reg_offset; 6381 6382 /* init the CP */ 6383 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6384 adev->gfx.config.max_hw_contexts - 1); 6385 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6386 6387 gfx_v10_0_cp_gfx_enable(adev, true); 6388 6389 ring = &adev->gfx.gfx_ring[0]; 6390 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6391 if (r) { 6392 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 6393 return r; 6394 } 6395 6396 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6397 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6398 6399 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6400 amdgpu_ring_write(ring, 0x80000000); 6401 amdgpu_ring_write(ring, 0x80000000); 6402 6403 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6404 for (ext = sect->section; ext->extent != NULL; ++ext) { 6405 if (sect->id == SECT_CONTEXT) { 6406 amdgpu_ring_write(ring, 6407 PACKET3(PACKET3_SET_CONTEXT_REG, 6408 ext->reg_count)); 6409 amdgpu_ring_write(ring, ext->reg_index - 6410 PACKET3_SET_CONTEXT_REG_START); 6411 for (i = 0; i < ext->reg_count; i++) 6412 amdgpu_ring_write(ring, ext->extent[i]); 6413 } 6414 } 6415 } 6416 6417 ctx_reg_offset = 6418 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6419 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6420 amdgpu_ring_write(ring, ctx_reg_offset); 6421 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6422 6423 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6424 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6425 6426 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6427 amdgpu_ring_write(ring, 0); 6428 6429 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6430 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6431 amdgpu_ring_write(ring, 0x8000); 6432 amdgpu_ring_write(ring, 0x8000); 6433 6434 amdgpu_ring_commit(ring); 6435 6436 /* submit cs packet to copy state 0 to next available state */ 6437 if (adev->gfx.num_gfx_rings > 1) { 6438 /* maximum supported gfx ring is 2 */ 6439 ring = &adev->gfx.gfx_ring[1]; 6440 r = amdgpu_ring_alloc(ring, 2); 6441 if (r) { 6442 drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); 6443 return r; 6444 } 6445 6446 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6447 amdgpu_ring_write(ring, 0); 6448 6449 amdgpu_ring_commit(ring); 6450 } 6451 return 0; 6452 } 6453 6454 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6455 CP_PIPE_ID pipe) 6456 { 6457 u32 tmp; 6458 6459 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6460 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6461 6462 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6463 } 6464 6465 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6466 struct amdgpu_ring *ring) 6467 { 6468 u32 tmp; 6469 6470 if (!amdgpu_async_gfx_ring) { 6471 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6472 if (ring->use_doorbell) { 6473 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6474 DOORBELL_OFFSET, ring->doorbell_index); 6475 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6476 DOORBELL_EN, 1); 6477 } else { 6478 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6479 DOORBELL_EN, 0); 6480 } 6481 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6482 } 6483 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6484 case IP_VERSION(10, 3, 0): 6485 case IP_VERSION(10, 3, 2): 6486 case IP_VERSION(10, 3, 1): 6487 case IP_VERSION(10, 3, 4): 6488 case IP_VERSION(10, 3, 5): 6489 case IP_VERSION(10, 3, 6): 6490 case IP_VERSION(10, 3, 3): 6491 case IP_VERSION(10, 3, 7): 6492 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6493 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6494 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6495 6496 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6497 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6498 break; 6499 default: 6500 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6501 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6502 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6503 6504 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6505 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6506 break; 6507 } 6508 } 6509 6510 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6511 { 6512 struct amdgpu_ring *ring; 6513 u32 tmp; 6514 u32 rb_bufsz; 6515 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6516 6517 /* Set the write pointer delay */ 6518 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6519 6520 /* set the RB to use vmid 0 */ 6521 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6522 6523 /* Init gfx ring 0 for pipe 0 */ 6524 mutex_lock(&adev->srbm_mutex); 6525 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6526 6527 /* Set ring buffer size */ 6528 ring = &adev->gfx.gfx_ring[0]; 6529 rb_bufsz = order_base_2(ring->ring_size / 8); 6530 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6531 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6532 #ifdef __BIG_ENDIAN 6533 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6534 #endif 6535 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6536 6537 /* Initialize the ring buffer's write pointers */ 6538 ring->wptr = 0; 6539 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6540 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6541 6542 /* set the wb address whether it's enabled or not */ 6543 rptr_addr = ring->rptr_gpu_addr; 6544 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6545 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6546 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6547 6548 wptr_gpu_addr = ring->wptr_gpu_addr; 6549 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6550 lower_32_bits(wptr_gpu_addr)); 6551 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6552 upper_32_bits(wptr_gpu_addr)); 6553 6554 mdelay(1); 6555 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6556 6557 rb_addr = ring->gpu_addr >> 8; 6558 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6559 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6560 6561 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6562 6563 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6564 mutex_unlock(&adev->srbm_mutex); 6565 6566 /* Init gfx ring 1 for pipe 1 */ 6567 if (adev->gfx.num_gfx_rings > 1) { 6568 mutex_lock(&adev->srbm_mutex); 6569 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6570 /* maximum supported gfx ring is 2 */ 6571 ring = &adev->gfx.gfx_ring[1]; 6572 rb_bufsz = order_base_2(ring->ring_size / 8); 6573 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6574 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6575 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6576 /* Initialize the ring buffer's write pointers */ 6577 ring->wptr = 0; 6578 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6579 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6580 /* Set the wb address whether it's enabled or not */ 6581 rptr_addr = ring->rptr_gpu_addr; 6582 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6583 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6584 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6585 wptr_gpu_addr = ring->wptr_gpu_addr; 6586 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6587 lower_32_bits(wptr_gpu_addr)); 6588 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6589 upper_32_bits(wptr_gpu_addr)); 6590 6591 mdelay(1); 6592 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6593 6594 rb_addr = ring->gpu_addr >> 8; 6595 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6596 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6597 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6598 6599 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6600 mutex_unlock(&adev->srbm_mutex); 6601 } 6602 /* Switch to pipe 0 */ 6603 mutex_lock(&adev->srbm_mutex); 6604 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6605 mutex_unlock(&adev->srbm_mutex); 6606 6607 /* start the ring */ 6608 gfx_v10_0_cp_gfx_start(adev); 6609 6610 return 0; 6611 } 6612 6613 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6614 { 6615 if (enable) { 6616 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6617 case IP_VERSION(10, 3, 0): 6618 case IP_VERSION(10, 3, 2): 6619 case IP_VERSION(10, 3, 1): 6620 case IP_VERSION(10, 3, 4): 6621 case IP_VERSION(10, 3, 5): 6622 case IP_VERSION(10, 3, 6): 6623 case IP_VERSION(10, 3, 3): 6624 case IP_VERSION(10, 3, 7): 6625 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6626 break; 6627 default: 6628 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6629 break; 6630 } 6631 } else { 6632 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6633 case IP_VERSION(10, 3, 0): 6634 case IP_VERSION(10, 3, 2): 6635 case IP_VERSION(10, 3, 1): 6636 case IP_VERSION(10, 3, 4): 6637 case IP_VERSION(10, 3, 5): 6638 case IP_VERSION(10, 3, 6): 6639 case IP_VERSION(10, 3, 3): 6640 case IP_VERSION(10, 3, 7): 6641 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6642 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6643 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6644 break; 6645 default: 6646 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6647 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6648 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6649 break; 6650 } 6651 adev->gfx.kiq[0].ring.sched.ready = false; 6652 } 6653 udelay(50); 6654 } 6655 6656 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6657 { 6658 const struct gfx_firmware_header_v1_0 *mec_hdr; 6659 const __le32 *fw_data; 6660 unsigned int i; 6661 u32 tmp; 6662 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6663 6664 if (!adev->gfx.mec_fw) 6665 return -EINVAL; 6666 6667 gfx_v10_0_cp_compute_enable(adev, false); 6668 6669 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6670 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6671 6672 fw_data = (const __le32 *) 6673 (adev->gfx.mec_fw->data + 6674 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6675 6676 /* Trigger an invalidation of the L1 instruction caches */ 6677 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6678 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6679 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6680 6681 /* Wait for invalidation complete */ 6682 for (i = 0; i < usec_timeout; i++) { 6683 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6684 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6685 INVALIDATE_CACHE_COMPLETE)) 6686 break; 6687 udelay(1); 6688 } 6689 6690 if (i >= usec_timeout) { 6691 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6692 return -EINVAL; 6693 } 6694 6695 if (amdgpu_emu_mode == 1) 6696 amdgpu_device_flush_hdp(adev, NULL); 6697 6698 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6699 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6700 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6701 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6702 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6703 6704 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6705 0xFFFFF000); 6706 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6707 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6708 6709 /* MEC1 */ 6710 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6711 6712 for (i = 0; i < mec_hdr->jt_size; i++) 6713 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6714 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6715 6716 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6717 6718 /* 6719 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6720 * different microcode than MEC1. 6721 */ 6722 6723 return 0; 6724 } 6725 6726 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6727 { 6728 uint32_t tmp; 6729 struct amdgpu_device *adev = ring->adev; 6730 6731 /* tell RLC which is KIQ queue */ 6732 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6733 case IP_VERSION(10, 3, 0): 6734 case IP_VERSION(10, 3, 2): 6735 case IP_VERSION(10, 3, 1): 6736 case IP_VERSION(10, 3, 4): 6737 case IP_VERSION(10, 3, 5): 6738 case IP_VERSION(10, 3, 6): 6739 case IP_VERSION(10, 3, 3): 6740 case IP_VERSION(10, 3, 7): 6741 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6742 tmp &= 0xffffff00; 6743 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6744 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80); 6745 break; 6746 default: 6747 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6748 tmp &= 0xffffff00; 6749 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6750 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80); 6751 break; 6752 } 6753 } 6754 6755 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6756 struct v10_gfx_mqd *mqd, 6757 struct amdgpu_mqd_prop *prop) 6758 { 6759 bool priority = 0; 6760 u32 tmp; 6761 6762 /* set up default queue priority level 6763 * 0x0 = low priority, 0x1 = high priority 6764 */ 6765 if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) 6766 priority = 1; 6767 6768 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6769 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6770 mqd->cp_gfx_hqd_queue_priority = tmp; 6771 } 6772 6773 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6774 struct amdgpu_mqd_prop *prop) 6775 { 6776 struct v10_gfx_mqd *mqd = m; 6777 uint64_t hqd_gpu_addr, wb_gpu_addr; 6778 uint32_t tmp; 6779 uint32_t rb_bufsz; 6780 6781 /* set up gfx hqd wptr */ 6782 mqd->cp_gfx_hqd_wptr = 0; 6783 mqd->cp_gfx_hqd_wptr_hi = 0; 6784 6785 /* set the pointer to the MQD */ 6786 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6787 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6788 6789 /* set up mqd control */ 6790 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6791 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6792 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6793 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6794 mqd->cp_gfx_mqd_control = tmp; 6795 6796 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6797 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6798 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6799 mqd->cp_gfx_hqd_vmid = 0; 6800 6801 /* set up gfx queue priority */ 6802 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6803 6804 /* set up time quantum */ 6805 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6806 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6807 mqd->cp_gfx_hqd_quantum = tmp; 6808 6809 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6810 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6811 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6812 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6813 6814 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6815 wb_gpu_addr = prop->rptr_gpu_addr; 6816 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6817 mqd->cp_gfx_hqd_rptr_addr_hi = 6818 upper_32_bits(wb_gpu_addr) & 0xffff; 6819 6820 /* set up rb_wptr_poll addr */ 6821 wb_gpu_addr = prop->wptr_gpu_addr; 6822 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6823 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6824 6825 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6826 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6827 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6828 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6829 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6830 #ifdef __BIG_ENDIAN 6831 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6832 #endif 6833 mqd->cp_gfx_hqd_cntl = tmp; 6834 6835 /* set up cp_doorbell_control */ 6836 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6837 if (prop->use_doorbell) { 6838 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6839 DOORBELL_OFFSET, prop->doorbell_index); 6840 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6841 DOORBELL_EN, 1); 6842 } else 6843 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6844 DOORBELL_EN, 0); 6845 mqd->cp_rb_doorbell_control = tmp; 6846 6847 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6848 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6849 6850 /* active the queue */ 6851 mqd->cp_gfx_hqd_active = 1; 6852 6853 return 0; 6854 } 6855 6856 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 6857 { 6858 struct amdgpu_device *adev = ring->adev; 6859 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6860 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6861 6862 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 6863 memset((void *)mqd, 0, sizeof(*mqd)); 6864 mutex_lock(&adev->srbm_mutex); 6865 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6866 amdgpu_ring_init_mqd(ring); 6867 6868 /* 6869 * if there are 2 gfx rings, set the lower doorbell 6870 * range of the first ring, otherwise the range of 6871 * the second ring will override the first ring 6872 */ 6873 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6874 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6875 6876 nv_grbm_select(adev, 0, 0, 0, 0); 6877 mutex_unlock(&adev->srbm_mutex); 6878 if (adev->gfx.me.mqd_backup[mqd_idx]) 6879 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6880 } else { 6881 mutex_lock(&adev->srbm_mutex); 6882 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6883 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6884 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6885 6886 nv_grbm_select(adev, 0, 0, 0, 0); 6887 mutex_unlock(&adev->srbm_mutex); 6888 /* restore mqd with the backup copy */ 6889 if (adev->gfx.me.mqd_backup[mqd_idx]) 6890 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6891 /* reset the ring */ 6892 ring->wptr = 0; 6893 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6894 amdgpu_ring_clear_ring(ring); 6895 } 6896 6897 return 0; 6898 } 6899 6900 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6901 { 6902 int r, i; 6903 6904 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6905 r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 6906 if (r) 6907 return r; 6908 } 6909 6910 r = amdgpu_gfx_enable_kgq(adev, 0); 6911 if (r) 6912 return r; 6913 6914 return gfx_v10_0_cp_gfx_start(adev); 6915 } 6916 6917 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6918 struct amdgpu_mqd_prop *prop) 6919 { 6920 struct v10_compute_mqd *mqd = m; 6921 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6922 uint32_t tmp; 6923 6924 mqd->header = 0xC0310800; 6925 mqd->compute_pipelinestat_enable = 0x00000001; 6926 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6927 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6928 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6929 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6930 mqd->compute_misc_reserved = 0x00000003; 6931 6932 eop_base_addr = prop->eop_gpu_addr >> 8; 6933 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6934 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6935 6936 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6937 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6938 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6939 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6940 6941 mqd->cp_hqd_eop_control = tmp; 6942 6943 /* enable doorbell? */ 6944 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6945 6946 if (prop->use_doorbell) { 6947 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6948 DOORBELL_OFFSET, prop->doorbell_index); 6949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6950 DOORBELL_EN, 1); 6951 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6952 DOORBELL_SOURCE, 0); 6953 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6954 DOORBELL_HIT, 0); 6955 } else { 6956 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6957 DOORBELL_EN, 0); 6958 } 6959 6960 mqd->cp_hqd_pq_doorbell_control = tmp; 6961 6962 /* disable the queue if it's active */ 6963 mqd->cp_hqd_dequeue_request = 0; 6964 mqd->cp_hqd_pq_rptr = 0; 6965 mqd->cp_hqd_pq_wptr_lo = 0; 6966 mqd->cp_hqd_pq_wptr_hi = 0; 6967 6968 /* set the pointer to the MQD */ 6969 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6970 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6971 6972 /* set MQD vmid to 0 */ 6973 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6974 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6975 mqd->cp_mqd_control = tmp; 6976 6977 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6978 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6979 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6980 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6981 6982 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6983 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6984 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6985 (order_base_2(prop->queue_size / 4) - 1)); 6986 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6987 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6988 #ifdef __BIG_ENDIAN 6989 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6990 #endif 6991 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6992 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6993 prop->allow_tunneling); 6994 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6995 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6996 mqd->cp_hqd_pq_control = tmp; 6997 6998 /* set the wb address whether it's enabled or not */ 6999 wb_gpu_addr = prop->rptr_gpu_addr; 7000 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 7001 mqd->cp_hqd_pq_rptr_report_addr_hi = 7002 upper_32_bits(wb_gpu_addr) & 0xffff; 7003 7004 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7005 wb_gpu_addr = prop->wptr_gpu_addr; 7006 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 7007 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 7008 7009 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7010 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 7011 7012 /* set the vmid for the queue */ 7013 mqd->cp_hqd_vmid = 0; 7014 7015 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 7016 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 7017 mqd->cp_hqd_persistent_state = tmp; 7018 7019 /* set MIN_IB_AVAIL_SIZE */ 7020 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 7021 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 7022 mqd->cp_hqd_ib_control = tmp; 7023 7024 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 7025 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 7026 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 7027 mqd->cp_hqd_quantum = tmp; 7028 7029 /* set static priority for a compute queue/ring */ 7030 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 7031 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 7032 7033 mqd->cp_hqd_active = prop->hqd_active; 7034 7035 return 0; 7036 } 7037 7038 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 7039 { 7040 struct amdgpu_device *adev = ring->adev; 7041 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7042 int j; 7043 7044 /* inactivate the queue */ 7045 if (amdgpu_sriov_vf(adev)) 7046 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 7047 7048 /* disable wptr polling */ 7049 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 7050 7051 /* disable the queue if it's active */ 7052 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7053 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7054 for (j = 0; j < adev->usec_timeout; j++) { 7055 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7056 break; 7057 udelay(1); 7058 } 7059 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7060 mqd->cp_hqd_dequeue_request); 7061 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7062 mqd->cp_hqd_pq_rptr); 7063 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7064 mqd->cp_hqd_pq_wptr_lo); 7065 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7066 mqd->cp_hqd_pq_wptr_hi); 7067 } 7068 7069 /* disable doorbells */ 7070 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 7071 7072 /* write the EOP addr */ 7073 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7074 mqd->cp_hqd_eop_base_addr_lo); 7075 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7076 mqd->cp_hqd_eop_base_addr_hi); 7077 7078 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7079 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7080 mqd->cp_hqd_eop_control); 7081 7082 /* set the pointer to the MQD */ 7083 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7084 mqd->cp_mqd_base_addr_lo); 7085 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7086 mqd->cp_mqd_base_addr_hi); 7087 7088 /* set MQD vmid to 0 */ 7089 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7090 mqd->cp_mqd_control); 7091 7092 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7093 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7094 mqd->cp_hqd_pq_base_lo); 7095 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7096 mqd->cp_hqd_pq_base_hi); 7097 7098 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7099 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7100 mqd->cp_hqd_pq_control); 7101 7102 /* set the wb address whether it's enabled or not */ 7103 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7104 mqd->cp_hqd_pq_rptr_report_addr_lo); 7105 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7106 mqd->cp_hqd_pq_rptr_report_addr_hi); 7107 7108 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7109 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7110 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7111 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7112 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7113 7114 /* enable the doorbell if requested */ 7115 if (ring->use_doorbell) { 7116 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7117 (adev->doorbell_index.kiq * 2) << 2); 7118 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7119 (adev->doorbell_index.userqueue_end * 2) << 2); 7120 } 7121 7122 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7123 mqd->cp_hqd_pq_doorbell_control); 7124 7125 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7126 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7127 mqd->cp_hqd_pq_wptr_lo); 7128 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7129 mqd->cp_hqd_pq_wptr_hi); 7130 7131 /* set the vmid for the queue */ 7132 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7133 7134 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7135 mqd->cp_hqd_persistent_state); 7136 7137 /* activate the queue */ 7138 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7139 mqd->cp_hqd_active); 7140 7141 if (ring->use_doorbell) 7142 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7143 7144 return 0; 7145 } 7146 7147 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7148 { 7149 struct amdgpu_device *adev = ring->adev; 7150 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7151 7152 gfx_v10_0_kiq_setting(ring); 7153 7154 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7155 /* reset MQD to a clean status */ 7156 if (adev->gfx.kiq[0].mqd_backup) 7157 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7158 7159 /* reset ring buffer */ 7160 ring->wptr = 0; 7161 amdgpu_ring_clear_ring(ring); 7162 7163 mutex_lock(&adev->srbm_mutex); 7164 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7165 gfx_v10_0_kiq_init_register(ring); 7166 nv_grbm_select(adev, 0, 0, 0, 0); 7167 mutex_unlock(&adev->srbm_mutex); 7168 } else { 7169 memset((void *)mqd, 0, sizeof(*mqd)); 7170 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7171 amdgpu_ring_clear_ring(ring); 7172 mutex_lock(&adev->srbm_mutex); 7173 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7174 amdgpu_ring_init_mqd(ring); 7175 gfx_v10_0_kiq_init_register(ring); 7176 nv_grbm_select(adev, 0, 0, 0, 0); 7177 mutex_unlock(&adev->srbm_mutex); 7178 7179 if (adev->gfx.kiq[0].mqd_backup) 7180 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7181 } 7182 7183 return 0; 7184 } 7185 7186 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) 7187 { 7188 struct amdgpu_device *adev = ring->adev; 7189 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7190 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7191 7192 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { 7193 memset((void *)mqd, 0, sizeof(*mqd)); 7194 mutex_lock(&adev->srbm_mutex); 7195 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7196 amdgpu_ring_init_mqd(ring); 7197 nv_grbm_select(adev, 0, 0, 0, 0); 7198 mutex_unlock(&adev->srbm_mutex); 7199 7200 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7201 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7202 } else { 7203 /* restore MQD to a clean status */ 7204 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7205 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7206 /* reset ring buffer */ 7207 ring->wptr = 0; 7208 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7209 amdgpu_ring_clear_ring(ring); 7210 } 7211 7212 return 0; 7213 } 7214 7215 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7216 { 7217 gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 7218 return 0; 7219 } 7220 7221 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7222 { 7223 int i, r; 7224 7225 gfx_v10_0_cp_compute_enable(adev, true); 7226 7227 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7228 r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i], 7229 false); 7230 if (r) 7231 return r; 7232 } 7233 7234 return amdgpu_gfx_enable_kcq(adev, 0); 7235 } 7236 7237 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7238 { 7239 int r, i; 7240 struct amdgpu_ring *ring; 7241 7242 if (!(adev->flags & AMD_IS_APU)) 7243 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7244 7245 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7246 /* legacy firmware loading */ 7247 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7248 if (r) 7249 return r; 7250 7251 r = gfx_v10_0_cp_compute_load_microcode(adev); 7252 if (r) 7253 return r; 7254 } 7255 7256 r = gfx_v10_0_kiq_resume(adev); 7257 if (r) 7258 return r; 7259 7260 r = gfx_v10_0_kcq_resume(adev); 7261 if (r) 7262 return r; 7263 7264 if (!amdgpu_async_gfx_ring) { 7265 r = gfx_v10_0_cp_gfx_resume(adev); 7266 if (r) 7267 return r; 7268 } else { 7269 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7270 if (r) 7271 return r; 7272 } 7273 7274 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7275 ring = &adev->gfx.gfx_ring[i]; 7276 r = amdgpu_ring_test_helper(ring); 7277 if (r) 7278 return r; 7279 } 7280 7281 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7282 ring = &adev->gfx.compute_ring[i]; 7283 r = amdgpu_ring_test_helper(ring); 7284 if (r) 7285 return r; 7286 } 7287 7288 return 0; 7289 } 7290 7291 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7292 { 7293 gfx_v10_0_cp_gfx_enable(adev, enable); 7294 gfx_v10_0_cp_compute_enable(adev, enable); 7295 } 7296 7297 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7298 { 7299 uint32_t data, pattern = 0xDEADBEEF; 7300 7301 /* 7302 * check if mmVGT_ESGS_RING_SIZE_UMD 7303 * has been remapped to mmVGT_ESGS_RING_SIZE 7304 */ 7305 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7306 case IP_VERSION(10, 3, 0): 7307 case IP_VERSION(10, 3, 2): 7308 case IP_VERSION(10, 3, 4): 7309 case IP_VERSION(10, 3, 5): 7310 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7311 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7312 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7313 7314 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7315 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7316 return true; 7317 } 7318 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7319 break; 7320 case IP_VERSION(10, 3, 1): 7321 case IP_VERSION(10, 3, 3): 7322 case IP_VERSION(10, 3, 6): 7323 case IP_VERSION(10, 3, 7): 7324 return true; 7325 default: 7326 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7327 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7328 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7329 7330 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7331 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7332 return true; 7333 } 7334 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7335 break; 7336 } 7337 7338 return false; 7339 } 7340 7341 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7342 { 7343 uint32_t data; 7344 7345 if (amdgpu_sriov_vf(adev)) 7346 return; 7347 7348 /* 7349 * Initialize cam_index to 0 7350 * index will auto-inc after each data writing 7351 */ 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7353 7354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7355 case IP_VERSION(10, 3, 0): 7356 case IP_VERSION(10, 3, 2): 7357 case IP_VERSION(10, 3, 1): 7358 case IP_VERSION(10, 3, 4): 7359 case IP_VERSION(10, 3, 5): 7360 case IP_VERSION(10, 3, 6): 7361 case IP_VERSION(10, 3, 3): 7362 case IP_VERSION(10, 3, 7): 7363 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7364 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7365 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7366 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7367 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7368 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7369 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7370 7371 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7372 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7373 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7374 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7375 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7376 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7377 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7378 7379 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7380 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7381 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7382 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7383 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7384 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7385 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7386 7387 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7388 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7389 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7390 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7391 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7392 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7393 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7394 7395 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7396 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7397 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7398 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7399 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7400 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7401 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7402 7403 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7404 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7405 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7406 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7407 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7408 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7409 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7410 7411 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7412 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7413 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7414 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7415 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7416 break; 7417 default: 7418 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7419 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7420 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7421 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7422 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7423 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7424 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7425 7426 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7427 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7428 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7429 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7430 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7431 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7432 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7433 7434 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7435 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7436 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7437 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7438 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7439 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7440 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7441 7442 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7443 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7444 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7445 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7446 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7447 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7448 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7449 7450 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7451 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7452 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7453 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7454 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7455 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7456 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7457 7458 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7459 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7460 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7461 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7462 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7463 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7464 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7465 7466 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7467 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7468 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7469 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7470 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7471 break; 7472 } 7473 7474 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7475 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7476 } 7477 7478 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7479 { 7480 uint32_t data; 7481 7482 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7483 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7484 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7485 7486 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7487 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7488 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7489 } 7490 7491 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 7492 { 7493 int r; 7494 struct amdgpu_device *adev = ip_block->adev; 7495 7496 if (!amdgpu_emu_mode) 7497 gfx_v10_0_init_golden_registers(adev); 7498 7499 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 7500 adev->gfx.cleaner_shader_ptr); 7501 7502 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7503 /** 7504 * For gfx 10, rlc firmware loading relies on smu firmware is 7505 * loaded firstly, so in direct type, it has to load smc ucode 7506 * here before rlc. 7507 */ 7508 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7509 if (r) 7510 return r; 7511 gfx_v10_0_disable_gpa_mode(adev); 7512 } 7513 7514 /* if GRBM CAM not remapped, set up the remapping */ 7515 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7516 gfx_v10_0_setup_grbm_cam_remapping(adev); 7517 7518 gfx_v10_0_constants_init(adev); 7519 7520 r = gfx_v10_0_rlc_resume(adev); 7521 if (r) 7522 return r; 7523 7524 /* 7525 * init golden registers and rlc resume may override some registers, 7526 * reconfig them here 7527 */ 7528 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7529 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7530 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7531 gfx_v10_0_tcp_harvest(adev); 7532 7533 r = gfx_v10_0_cp_resume(adev); 7534 if (r) 7535 return r; 7536 7537 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7538 gfx_v10_3_program_pbb_mode(adev); 7539 7540 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7541 gfx_v10_3_set_power_brake_sequence(adev); 7542 7543 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7544 if (r) 7545 return r; 7546 7547 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7548 if (r) 7549 goto err_priv_inst; 7550 7551 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7552 if (r) 7553 goto err_bad_op; 7554 7555 return 0; 7556 7557 err_bad_op: 7558 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7559 err_priv_inst: 7560 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7561 return r; 7562 } 7563 7564 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 7565 { 7566 struct amdgpu_device *adev = ip_block->adev; 7567 7568 cancel_delayed_work_sync(&adev->gfx.idle_work); 7569 7570 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7571 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7572 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7573 7574 /* WA added for Vangogh asic fixing the SMU suspend failure 7575 * It needs to set power gating again during gfxoff control 7576 * otherwise the gfxoff disallowing will be failed to set. 7577 */ 7578 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7579 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 7580 7581 if (!adev->no_hw_access) { 7582 if (amdgpu_async_gfx_ring) { 7583 if (amdgpu_gfx_disable_kgq(adev, 0)) 7584 DRM_ERROR("KGQ disable failed\n"); 7585 } 7586 7587 if (amdgpu_gfx_disable_kcq(adev, 0)) 7588 DRM_ERROR("KCQ disable failed\n"); 7589 } 7590 7591 if (amdgpu_sriov_vf(adev)) { 7592 gfx_v10_0_cp_gfx_enable(adev, false); 7593 /* Remove the steps of clearing KIQ position. 7594 * It causes GFX hang when another Win guest is rendering. 7595 */ 7596 return 0; 7597 } 7598 gfx_v10_0_cp_enable(adev, false); 7599 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7600 7601 return 0; 7602 } 7603 7604 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) 7605 { 7606 return gfx_v10_0_hw_fini(ip_block); 7607 } 7608 7609 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) 7610 { 7611 return gfx_v10_0_hw_init(ip_block); 7612 } 7613 7614 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 7615 { 7616 struct amdgpu_device *adev = ip_block->adev; 7617 7618 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7619 GRBM_STATUS, GUI_ACTIVE)) 7620 return false; 7621 else 7622 return true; 7623 } 7624 7625 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 7626 { 7627 unsigned int i; 7628 u32 tmp; 7629 struct amdgpu_device *adev = ip_block->adev; 7630 7631 for (i = 0; i < adev->usec_timeout; i++) { 7632 /* read MC_STATUS */ 7633 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7634 GRBM_STATUS__GUI_ACTIVE_MASK; 7635 7636 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7637 return 0; 7638 udelay(1); 7639 } 7640 return -ETIMEDOUT; 7641 } 7642 7643 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) 7644 { 7645 u32 grbm_soft_reset = 0; 7646 u32 tmp; 7647 struct amdgpu_device *adev = ip_block->adev; 7648 7649 /* GRBM_STATUS */ 7650 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7651 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7652 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7653 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7654 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7655 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7656 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7657 GRBM_SOFT_RESET, SOFT_RESET_CP, 7658 1); 7659 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7660 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7661 1); 7662 } 7663 7664 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7665 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7666 GRBM_SOFT_RESET, SOFT_RESET_CP, 7667 1); 7668 } 7669 7670 /* GRBM_STATUS2 */ 7671 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7672 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7673 case IP_VERSION(10, 3, 0): 7674 case IP_VERSION(10, 3, 2): 7675 case IP_VERSION(10, 3, 1): 7676 case IP_VERSION(10, 3, 4): 7677 case IP_VERSION(10, 3, 5): 7678 case IP_VERSION(10, 3, 6): 7679 case IP_VERSION(10, 3, 3): 7680 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7681 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7682 GRBM_SOFT_RESET, 7683 SOFT_RESET_RLC, 7684 1); 7685 break; 7686 default: 7687 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7688 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7689 GRBM_SOFT_RESET, 7690 SOFT_RESET_RLC, 7691 1); 7692 break; 7693 } 7694 7695 if (grbm_soft_reset) { 7696 /* stop the rlc */ 7697 gfx_v10_0_rlc_stop(adev); 7698 7699 /* Disable GFX parsing/prefetching */ 7700 gfx_v10_0_cp_gfx_enable(adev, false); 7701 7702 /* Disable MEC parsing/prefetching */ 7703 gfx_v10_0_cp_compute_enable(adev, false); 7704 7705 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7706 tmp |= grbm_soft_reset; 7707 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7708 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7709 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7710 7711 udelay(50); 7712 7713 tmp &= ~grbm_soft_reset; 7714 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7715 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7716 7717 /* Wait a little for things to settle down */ 7718 udelay(50); 7719 } 7720 return 0; 7721 } 7722 7723 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7724 { 7725 uint64_t clock, clock_lo, clock_hi, hi_check; 7726 7727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7728 case IP_VERSION(10, 1, 3): 7729 case IP_VERSION(10, 1, 4): 7730 preempt_disable(); 7731 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7732 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7733 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7734 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7735 * roughly every 42 seconds. 7736 */ 7737 if (hi_check != clock_hi) { 7738 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7739 clock_hi = hi_check; 7740 } 7741 preempt_enable(); 7742 clock = clock_lo | (clock_hi << 32ULL); 7743 break; 7744 case IP_VERSION(10, 3, 1): 7745 case IP_VERSION(10, 3, 3): 7746 case IP_VERSION(10, 3, 7): 7747 preempt_disable(); 7748 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7749 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7750 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7751 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7752 * roughly every 42 seconds. 7753 */ 7754 if (hi_check != clock_hi) { 7755 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7756 clock_hi = hi_check; 7757 } 7758 preempt_enable(); 7759 clock = clock_lo | (clock_hi << 32ULL); 7760 break; 7761 case IP_VERSION(10, 3, 6): 7762 preempt_disable(); 7763 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7764 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7765 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7766 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7767 * roughly every 42 seconds. 7768 */ 7769 if (hi_check != clock_hi) { 7770 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7771 clock_hi = hi_check; 7772 } 7773 preempt_enable(); 7774 clock = clock_lo | (clock_hi << 32ULL); 7775 break; 7776 default: 7777 preempt_disable(); 7778 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7779 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7780 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7781 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7782 * roughly every 42 seconds. 7783 */ 7784 if (hi_check != clock_hi) { 7785 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7786 clock_hi = hi_check; 7787 } 7788 preempt_enable(); 7789 clock = clock_lo | (clock_hi << 32ULL); 7790 break; 7791 } 7792 return clock; 7793 } 7794 7795 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7796 uint32_t vmid, 7797 uint32_t gds_base, uint32_t gds_size, 7798 uint32_t gws_base, uint32_t gws_size, 7799 uint32_t oa_base, uint32_t oa_size) 7800 { 7801 struct amdgpu_device *adev = ring->adev; 7802 7803 /* GDS Base */ 7804 gfx_v10_0_write_data_to_reg(ring, 0, false, 7805 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7806 gds_base); 7807 7808 /* GDS Size */ 7809 gfx_v10_0_write_data_to_reg(ring, 0, false, 7810 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7811 gds_size); 7812 7813 /* GWS */ 7814 gfx_v10_0_write_data_to_reg(ring, 0, false, 7815 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7816 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7817 7818 /* OA */ 7819 gfx_v10_0_write_data_to_reg(ring, 0, false, 7820 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7821 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7822 } 7823 7824 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) 7825 { 7826 struct amdgpu_device *adev = ip_block->adev; 7827 7828 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7829 7830 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7831 case IP_VERSION(10, 1, 10): 7832 case IP_VERSION(10, 1, 1): 7833 case IP_VERSION(10, 1, 2): 7834 case IP_VERSION(10, 1, 3): 7835 case IP_VERSION(10, 1, 4): 7836 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7837 break; 7838 case IP_VERSION(10, 3, 0): 7839 case IP_VERSION(10, 3, 2): 7840 case IP_VERSION(10, 3, 1): 7841 case IP_VERSION(10, 3, 4): 7842 case IP_VERSION(10, 3, 5): 7843 case IP_VERSION(10, 3, 6): 7844 case IP_VERSION(10, 3, 3): 7845 case IP_VERSION(10, 3, 7): 7846 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7847 break; 7848 default: 7849 break; 7850 } 7851 7852 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7853 AMDGPU_MAX_COMPUTE_RINGS); 7854 7855 gfx_v10_0_set_kiq_pm4_funcs(adev); 7856 gfx_v10_0_set_ring_funcs(adev); 7857 gfx_v10_0_set_irq_funcs(adev); 7858 gfx_v10_0_set_gds_init(adev); 7859 gfx_v10_0_set_rlc_funcs(adev); 7860 gfx_v10_0_set_mqd_funcs(adev); 7861 7862 /* init rlcg reg access ctrl */ 7863 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7864 7865 amdgpu_init_rlc_reg_funcs(adev); 7866 7867 return gfx_v10_0_init_microcode(adev); 7868 } 7869 7870 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7871 { 7872 uint32_t rlc_cntl; 7873 7874 /* if RLC is not enabled, do nothing */ 7875 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7876 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7877 } 7878 7879 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7880 { 7881 uint32_t data; 7882 unsigned int i; 7883 7884 data = RLC_SAFE_MODE__CMD_MASK; 7885 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7886 7887 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7888 case IP_VERSION(10, 3, 0): 7889 case IP_VERSION(10, 3, 2): 7890 case IP_VERSION(10, 3, 1): 7891 case IP_VERSION(10, 3, 4): 7892 case IP_VERSION(10, 3, 5): 7893 case IP_VERSION(10, 3, 6): 7894 case IP_VERSION(10, 3, 3): 7895 case IP_VERSION(10, 3, 7): 7896 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7897 7898 /* wait for RLC_SAFE_MODE */ 7899 for (i = 0; i < adev->usec_timeout; i++) { 7900 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7901 RLC_SAFE_MODE, CMD)) 7902 break; 7903 udelay(1); 7904 } 7905 break; 7906 default: 7907 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7908 7909 /* wait for RLC_SAFE_MODE */ 7910 for (i = 0; i < adev->usec_timeout; i++) { 7911 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7912 RLC_SAFE_MODE, CMD)) 7913 break; 7914 udelay(1); 7915 } 7916 break; 7917 } 7918 } 7919 7920 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7921 { 7922 uint32_t data; 7923 7924 data = RLC_SAFE_MODE__CMD_MASK; 7925 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7926 case IP_VERSION(10, 3, 0): 7927 case IP_VERSION(10, 3, 2): 7928 case IP_VERSION(10, 3, 1): 7929 case IP_VERSION(10, 3, 4): 7930 case IP_VERSION(10, 3, 5): 7931 case IP_VERSION(10, 3, 6): 7932 case IP_VERSION(10, 3, 3): 7933 case IP_VERSION(10, 3, 7): 7934 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7935 break; 7936 default: 7937 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7938 break; 7939 } 7940 } 7941 7942 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7943 bool enable) 7944 { 7945 uint32_t data, def; 7946 7947 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7948 return; 7949 7950 /* It is disabled by HW by default */ 7951 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7952 /* 0 - Disable some blocks' MGCG */ 7953 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7954 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7955 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7956 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7957 7958 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7959 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7960 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7961 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7962 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7963 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7964 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7965 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7966 7967 if (def != data) 7968 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7969 7970 /* MGLS is a global flag to control all MGLS in GFX */ 7971 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7972 /* 2 - RLC memory Light sleep */ 7973 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7974 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7975 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7976 if (def != data) 7977 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7978 } 7979 /* 3 - CP memory Light sleep */ 7980 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7981 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7982 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7983 if (def != data) 7984 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7985 } 7986 } 7987 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7988 /* 1 - MGCG_OVERRIDE */ 7989 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7990 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7991 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7992 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7993 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7994 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7995 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7996 if (def != data) 7997 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7998 7999 /* 2 - disable MGLS in CP */ 8000 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 8001 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 8002 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 8003 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 8004 } 8005 8006 /* 3 - disable MGLS in RLC */ 8007 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 8008 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 8009 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 8010 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 8011 } 8012 8013 } 8014 } 8015 8016 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 8017 bool enable) 8018 { 8019 uint32_t data, def; 8020 8021 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 8022 return; 8023 8024 /* Enable 3D CGCG/CGLS */ 8025 if (enable) { 8026 /* write cmd to clear cgcg/cgls ov */ 8027 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8028 8029 /* unset CGCG override */ 8030 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8031 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 8032 8033 /* update CGCG and CGLS override bits */ 8034 if (def != data) 8035 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8036 8037 /* enable 3Dcgcg FSM(0x0000363f) */ 8038 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8039 data = 0; 8040 8041 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8042 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8043 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8044 8045 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8046 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8047 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8048 8049 if (def != data) 8050 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8051 8052 /* set IDLE_POLL_COUNT(0x00900100) */ 8053 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8054 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8055 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8056 if (def != data) 8057 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8058 } else { 8059 /* Disable CGCG/CGLS */ 8060 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8061 8062 /* disable cgcg, cgls should be disabled */ 8063 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8064 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8065 8066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8067 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8068 8069 /* disable cgcg and cgls in FSM */ 8070 if (def != data) 8071 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8072 } 8073 } 8074 8075 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8076 bool enable) 8077 { 8078 uint32_t def, data; 8079 8080 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8081 return; 8082 8083 if (enable) { 8084 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8085 8086 /* unset CGCG override */ 8087 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8088 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8089 8090 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8091 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8092 8093 /* update CGCG and CGLS override bits */ 8094 if (def != data) 8095 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8096 8097 /* enable cgcg FSM(0x0000363F) */ 8098 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8099 data = 0; 8100 8101 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8102 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8103 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8104 8105 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8106 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8107 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8108 8109 if (def != data) 8110 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8111 8112 /* set IDLE_POLL_COUNT(0x00900100) */ 8113 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8114 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8115 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8116 if (def != data) 8117 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8118 } else { 8119 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8120 8121 /* reset CGCG/CGLS bits */ 8122 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8123 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8124 8125 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8126 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8127 8128 /* disable cgcg and cgls in FSM */ 8129 if (def != data) 8130 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8131 } 8132 } 8133 8134 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8135 bool enable) 8136 { 8137 uint32_t def, data; 8138 8139 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8140 return; 8141 8142 if (enable) { 8143 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8144 /* unset FGCG override */ 8145 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8146 /* update FGCG override bits */ 8147 if (def != data) 8148 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8149 8150 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8151 /* unset RLC SRAM CLK GATER override */ 8152 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8153 /* update RLC SRAM CLK GATER override bits */ 8154 if (def != data) 8155 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8156 } else { 8157 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8158 /* reset FGCG bits */ 8159 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8160 /* disable FGCG*/ 8161 if (def != data) 8162 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8163 8164 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8165 /* reset RLC SRAM CLK GATER bits */ 8166 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8167 /* disable RLC SRAM CLK*/ 8168 if (def != data) 8169 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8170 } 8171 } 8172 8173 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8174 { 8175 uint32_t reg_data = 0; 8176 uint32_t reg_idx = 0; 8177 uint32_t i; 8178 8179 const uint32_t tcp_ctrl_regs[] = { 8180 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8181 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8182 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8183 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8184 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8185 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8186 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8187 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8188 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8189 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8190 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8191 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8192 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8193 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8194 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8195 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8196 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8197 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8198 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8199 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8200 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8201 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8202 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8203 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8204 }; 8205 8206 const uint32_t tcp_ctrl_regs_nv12[] = { 8207 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8208 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8209 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8210 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8211 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8212 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8213 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8214 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8215 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8216 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8217 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8218 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8219 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8220 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8221 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8222 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8223 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8224 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8225 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8226 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8227 }; 8228 8229 const uint32_t sm_ctlr_regs[] = { 8230 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8231 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8232 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8233 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8234 }; 8235 8236 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8237 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8238 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8239 tcp_ctrl_regs_nv12[i]; 8240 reg_data = RREG32(reg_idx); 8241 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8242 WREG32(reg_idx, reg_data); 8243 } 8244 } else { 8245 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8246 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8247 tcp_ctrl_regs[i]; 8248 reg_data = RREG32(reg_idx); 8249 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8250 WREG32(reg_idx, reg_data); 8251 } 8252 } 8253 8254 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8255 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8256 sm_ctlr_regs[i]; 8257 reg_data = RREG32(reg_idx); 8258 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8259 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8260 WREG32(reg_idx, reg_data); 8261 } 8262 } 8263 8264 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8265 bool enable) 8266 { 8267 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8268 8269 if (enable) { 8270 /* enable FGCG firstly*/ 8271 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8272 /* CGCG/CGLS should be enabled after MGCG/MGLS 8273 * === MGCG + MGLS === 8274 */ 8275 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8276 /* === CGCG /CGLS for GFX 3D Only === */ 8277 gfx_v10_0_update_3d_clock_gating(adev, enable); 8278 /* === CGCG + CGLS === */ 8279 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8280 8281 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8282 IP_VERSION(10, 1, 10)) || 8283 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8284 IP_VERSION(10, 1, 1)) || 8285 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8286 IP_VERSION(10, 1, 2))) 8287 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8288 } else { 8289 /* CGCG/CGLS should be disabled before MGCG/MGLS 8290 * === CGCG + CGLS === 8291 */ 8292 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8293 /* === CGCG /CGLS for GFX 3D Only === */ 8294 gfx_v10_0_update_3d_clock_gating(adev, enable); 8295 /* === MGCG + MGLS === */ 8296 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8297 /* disable fgcg at last*/ 8298 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8299 } 8300 8301 if (adev->cg_flags & 8302 (AMD_CG_SUPPORT_GFX_MGCG | 8303 AMD_CG_SUPPORT_GFX_CGLS | 8304 AMD_CG_SUPPORT_GFX_CGCG | 8305 AMD_CG_SUPPORT_GFX_3D_CGCG | 8306 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8307 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8308 8309 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8310 8311 return 0; 8312 } 8313 8314 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8315 unsigned int vmid) 8316 { 8317 u32 reg, pre_data, data; 8318 8319 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8320 /* not for *_SOC15 */ 8321 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8322 pre_data = RREG32_NO_KIQ(reg); 8323 else 8324 pre_data = RREG32(reg); 8325 8326 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8327 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8328 8329 if (pre_data != data) { 8330 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8331 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8332 } else 8333 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8334 } 8335 } 8336 8337 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 8338 struct amdgpu_ring *ring, unsigned int vmid) 8339 { 8340 amdgpu_gfx_off_ctrl(adev, false); 8341 8342 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8343 8344 amdgpu_gfx_off_ctrl(adev, true); 8345 } 8346 8347 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8348 uint32_t offset, 8349 struct soc15_reg_rlcg *entries, int arr_size) 8350 { 8351 int i; 8352 uint32_t reg; 8353 8354 if (!entries) 8355 return false; 8356 8357 for (i = 0; i < arr_size; i++) { 8358 const struct soc15_reg_rlcg *entry; 8359 8360 entry = &entries[i]; 8361 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8362 if (offset == reg) 8363 return true; 8364 } 8365 8366 return false; 8367 } 8368 8369 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8370 { 8371 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8372 } 8373 8374 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8375 { 8376 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8377 8378 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8379 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8380 else 8381 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8382 8383 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8384 8385 /* 8386 * CGPG enablement required and the register to program the hysteresis value 8387 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8388 * in refclk count. Note that RLC FW is modified to take 16 bits from 8389 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8390 * 8391 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8392 * of CGPG enablement starting point. 8393 * Power/performance team will optimize it and might give a new value later. 8394 */ 8395 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8397 case IP_VERSION(10, 3, 1): 8398 case IP_VERSION(10, 3, 3): 8399 case IP_VERSION(10, 3, 6): 8400 case IP_VERSION(10, 3, 7): 8401 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8402 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8403 break; 8404 default: 8405 break; 8406 } 8407 } 8408 } 8409 8410 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8411 { 8412 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8413 8414 gfx_v10_cntl_power_gating(adev, enable); 8415 8416 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8417 } 8418 8419 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8420 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8421 .set_safe_mode = gfx_v10_0_set_safe_mode, 8422 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8423 .init = gfx_v10_0_rlc_init, 8424 .get_csb_size = gfx_v10_0_get_csb_size, 8425 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8426 .resume = gfx_v10_0_rlc_resume, 8427 .stop = gfx_v10_0_rlc_stop, 8428 .reset = gfx_v10_0_rlc_reset, 8429 .start = gfx_v10_0_rlc_start, 8430 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8431 }; 8432 8433 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8434 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8435 .set_safe_mode = gfx_v10_0_set_safe_mode, 8436 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8437 .init = gfx_v10_0_rlc_init, 8438 .get_csb_size = gfx_v10_0_get_csb_size, 8439 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8440 .resume = gfx_v10_0_rlc_resume, 8441 .stop = gfx_v10_0_rlc_stop, 8442 .reset = gfx_v10_0_rlc_reset, 8443 .start = gfx_v10_0_rlc_start, 8444 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8445 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8446 }; 8447 8448 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 8449 enum amd_powergating_state state) 8450 { 8451 struct amdgpu_device *adev = ip_block->adev; 8452 bool enable = (state == AMD_PG_STATE_GATE); 8453 8454 if (amdgpu_sriov_vf(adev)) 8455 return 0; 8456 8457 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8458 case IP_VERSION(10, 1, 10): 8459 case IP_VERSION(10, 1, 1): 8460 case IP_VERSION(10, 1, 2): 8461 case IP_VERSION(10, 3, 0): 8462 case IP_VERSION(10, 3, 2): 8463 case IP_VERSION(10, 3, 4): 8464 case IP_VERSION(10, 3, 5): 8465 amdgpu_gfx_off_ctrl(adev, enable); 8466 break; 8467 case IP_VERSION(10, 3, 1): 8468 case IP_VERSION(10, 3, 3): 8469 case IP_VERSION(10, 3, 6): 8470 case IP_VERSION(10, 3, 7): 8471 if (!enable) 8472 amdgpu_gfx_off_ctrl(adev, false); 8473 8474 gfx_v10_cntl_pg(adev, enable); 8475 8476 if (enable) 8477 amdgpu_gfx_off_ctrl(adev, true); 8478 8479 break; 8480 default: 8481 break; 8482 } 8483 return 0; 8484 } 8485 8486 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 8487 enum amd_clockgating_state state) 8488 { 8489 struct amdgpu_device *adev = ip_block->adev; 8490 8491 if (amdgpu_sriov_vf(adev)) 8492 return 0; 8493 8494 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8495 case IP_VERSION(10, 1, 10): 8496 case IP_VERSION(10, 1, 1): 8497 case IP_VERSION(10, 1, 2): 8498 case IP_VERSION(10, 3, 0): 8499 case IP_VERSION(10, 3, 2): 8500 case IP_VERSION(10, 3, 1): 8501 case IP_VERSION(10, 3, 4): 8502 case IP_VERSION(10, 3, 5): 8503 case IP_VERSION(10, 3, 6): 8504 case IP_VERSION(10, 3, 3): 8505 case IP_VERSION(10, 3, 7): 8506 gfx_v10_0_update_gfx_clock_gating(adev, 8507 state == AMD_CG_STATE_GATE); 8508 break; 8509 default: 8510 break; 8511 } 8512 return 0; 8513 } 8514 8515 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 8516 { 8517 struct amdgpu_device *adev = ip_block->adev; 8518 int data; 8519 8520 /* AMD_CG_SUPPORT_GFX_FGCG */ 8521 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8522 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8523 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8524 8525 /* AMD_CG_SUPPORT_GFX_MGCG */ 8526 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8527 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8528 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8529 8530 /* AMD_CG_SUPPORT_GFX_CGCG */ 8531 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8532 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8533 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8534 8535 /* AMD_CG_SUPPORT_GFX_CGLS */ 8536 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8537 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8538 8539 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8540 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8541 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8542 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8543 8544 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8545 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8546 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8547 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8548 8549 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8550 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8551 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8552 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8553 8554 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8555 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8556 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8557 } 8558 8559 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8560 { 8561 /* gfx10 is 32bit rptr*/ 8562 return *(uint32_t *)ring->rptr_cpu_addr; 8563 } 8564 8565 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8566 { 8567 struct amdgpu_device *adev = ring->adev; 8568 u64 wptr; 8569 8570 /* XXX check if swapping is necessary on BE */ 8571 if (ring->use_doorbell) { 8572 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8573 } else { 8574 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8575 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8576 } 8577 8578 return wptr; 8579 } 8580 8581 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8582 { 8583 struct amdgpu_device *adev = ring->adev; 8584 8585 if (ring->use_doorbell) { 8586 /* XXX check if swapping is necessary on BE */ 8587 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8588 ring->wptr); 8589 WDOORBELL64(ring->doorbell_index, ring->wptr); 8590 } else { 8591 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8592 lower_32_bits(ring->wptr)); 8593 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8594 upper_32_bits(ring->wptr)); 8595 } 8596 } 8597 8598 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8599 { 8600 /* gfx10 hardware is 32bit rptr */ 8601 return *(uint32_t *)ring->rptr_cpu_addr; 8602 } 8603 8604 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8605 { 8606 struct amdgpu_device *adev = ring->adev; 8607 u64 wptr; 8608 8609 /* XXX check if swapping is necessary on BE */ 8610 if (ring->use_doorbell) { 8611 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8612 } else { 8613 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 8614 wptr = 0; 8615 } 8616 return wptr; 8617 } 8618 8619 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8620 { 8621 struct amdgpu_device *adev = ring->adev; 8622 8623 if (ring->use_doorbell) { 8624 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8625 ring->wptr); 8626 WDOORBELL64(ring->doorbell_index, ring->wptr); 8627 } else { 8628 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 8629 } 8630 } 8631 8632 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8633 { 8634 struct amdgpu_device *adev = ring->adev; 8635 u32 ref_and_mask, reg_mem_engine; 8636 8637 if (!adev->gfx.funcs->get_hdp_flush_mask) { 8638 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 8639 return; 8640 } 8641 8642 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 8643 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8644 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8645 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8646 ref_and_mask, ref_and_mask, 0x20); 8647 } 8648 8649 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8650 struct amdgpu_job *job, 8651 struct amdgpu_ib *ib, 8652 uint32_t flags) 8653 { 8654 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8655 u32 header, control = 0; 8656 8657 if (ib->flags & AMDGPU_IB_FLAG_CE) 8658 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8659 else 8660 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8661 8662 control |= ib->length_dw | (vmid << 24); 8663 8664 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8665 control |= INDIRECT_BUFFER_PRE_ENB(1); 8666 8667 if (flags & AMDGPU_IB_PREEMPTED) 8668 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8669 8670 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8671 gfx_v10_0_ring_emit_de_meta(ring, 8672 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8673 } 8674 8675 amdgpu_ring_write(ring, header); 8676 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 8677 amdgpu_ring_write(ring, 8678 #ifdef __BIG_ENDIAN 8679 (2 << 0) | 8680 #endif 8681 lower_32_bits(ib->gpu_addr)); 8682 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8683 amdgpu_ring_write(ring, control); 8684 } 8685 8686 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8687 struct amdgpu_job *job, 8688 struct amdgpu_ib *ib, 8689 uint32_t flags) 8690 { 8691 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8692 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8693 8694 /* Currently, there is a high possibility to get wave ID mismatch 8695 * between ME and GDS, leading to a hw deadlock, because ME generates 8696 * different wave IDs than the GDS expects. This situation happens 8697 * randomly when at least 5 compute pipes use GDS ordered append. 8698 * The wave IDs generated by ME are also wrong after suspend/resume. 8699 * Those are probably bugs somewhere else in the kernel driver. 8700 * 8701 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8702 * GDS to 0 for this ring (me/pipe). 8703 */ 8704 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8706 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8707 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8708 } 8709 8710 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8711 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 8712 amdgpu_ring_write(ring, 8713 #ifdef __BIG_ENDIAN 8714 (2 << 0) | 8715 #endif 8716 lower_32_bits(ib->gpu_addr)); 8717 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8718 amdgpu_ring_write(ring, control); 8719 } 8720 8721 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8722 u64 seq, unsigned int flags) 8723 { 8724 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8725 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8726 8727 /* RELEASE_MEM - flush caches, send int */ 8728 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8729 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8730 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8731 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8732 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8733 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8734 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8735 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8736 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8737 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8738 8739 /* 8740 * the address should be Qword aligned if 64bit write, Dword 8741 * aligned if only send 32bit data low (discard data high) 8742 */ 8743 if (write64bit) 8744 WARN_ON(addr & 0x7); 8745 else 8746 WARN_ON(addr & 0x3); 8747 amdgpu_ring_write(ring, lower_32_bits(addr)); 8748 amdgpu_ring_write(ring, upper_32_bits(addr)); 8749 amdgpu_ring_write(ring, lower_32_bits(seq)); 8750 amdgpu_ring_write(ring, upper_32_bits(seq)); 8751 amdgpu_ring_write(ring, 0); 8752 } 8753 8754 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8755 { 8756 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8757 uint32_t seq = ring->fence_drv.sync_seq; 8758 uint64_t addr = ring->fence_drv.gpu_addr; 8759 8760 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8761 upper_32_bits(addr), seq, 0xffffffff, 4); 8762 } 8763 8764 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8765 uint16_t pasid, uint32_t flush_type, 8766 bool all_hub, uint8_t dst_sel) 8767 { 8768 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8769 amdgpu_ring_write(ring, 8770 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8771 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8772 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8773 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8774 } 8775 8776 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8777 unsigned int vmid, uint64_t pd_addr) 8778 { 8779 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8780 8781 /* compute doesn't have PFP */ 8782 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8783 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8784 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8785 amdgpu_ring_write(ring, 0x0); 8786 } 8787 } 8788 8789 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8790 u64 seq, unsigned int flags) 8791 { 8792 struct amdgpu_device *adev = ring->adev; 8793 8794 /* write fence seq to the "addr" */ 8795 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8796 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8797 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8798 amdgpu_ring_write(ring, lower_32_bits(addr)); 8799 amdgpu_ring_write(ring, upper_32_bits(addr)); 8800 amdgpu_ring_write(ring, lower_32_bits(seq)); 8801 8802 if (flags & AMDGPU_FENCE_FLAG_INT) { 8803 /* set register to trigger INT */ 8804 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8805 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8806 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8807 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8808 amdgpu_ring_write(ring, 0); 8809 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8810 } 8811 } 8812 8813 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8814 { 8815 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8816 amdgpu_ring_write(ring, 0); 8817 } 8818 8819 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8820 uint32_t flags) 8821 { 8822 uint32_t dw2 = 0; 8823 8824 if (ring->adev->gfx.mcbp) 8825 gfx_v10_0_ring_emit_ce_meta(ring, 8826 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8827 8828 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8829 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8830 /* set load_global_config & load_global_uconfig */ 8831 dw2 |= 0x8001; 8832 /* set load_cs_sh_regs */ 8833 dw2 |= 0x01000000; 8834 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8835 dw2 |= 0x10002; 8836 8837 /* set load_ce_ram if preamble presented */ 8838 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8839 dw2 |= 0x10000000; 8840 } else { 8841 /* still load_ce_ram if this is the first time preamble presented 8842 * although there is no context switch happens. 8843 */ 8844 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8845 dw2 |= 0x10000000; 8846 } 8847 8848 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8849 amdgpu_ring_write(ring, dw2); 8850 amdgpu_ring_write(ring, 0); 8851 } 8852 8853 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8854 uint64_t addr) 8855 { 8856 unsigned int ret; 8857 8858 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8859 amdgpu_ring_write(ring, lower_32_bits(addr)); 8860 amdgpu_ring_write(ring, upper_32_bits(addr)); 8861 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8862 amdgpu_ring_write(ring, 0); 8863 ret = ring->wptr & ring->buf_mask; 8864 /* patch dummy value later */ 8865 amdgpu_ring_write(ring, 0); 8866 8867 return ret; 8868 } 8869 8870 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8871 { 8872 int i, r = 0; 8873 struct amdgpu_device *adev = ring->adev; 8874 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8875 struct amdgpu_ring *kiq_ring = &kiq->ring; 8876 unsigned long flags; 8877 8878 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8879 return -EINVAL; 8880 8881 spin_lock_irqsave(&kiq->ring_lock, flags); 8882 8883 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8884 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8885 return -ENOMEM; 8886 } 8887 8888 /* assert preemption condition */ 8889 amdgpu_ring_set_preempt_cond_exec(ring, false); 8890 8891 /* assert IB preemption, emit the trailing fence */ 8892 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8893 ring->trail_fence_gpu_addr, 8894 ++ring->trail_seq); 8895 amdgpu_ring_commit(kiq_ring); 8896 8897 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8898 8899 /* poll the trailing fence */ 8900 for (i = 0; i < adev->usec_timeout; i++) { 8901 if (ring->trail_seq == 8902 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8903 break; 8904 udelay(1); 8905 } 8906 8907 if (i >= adev->usec_timeout) { 8908 r = -EINVAL; 8909 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8910 } 8911 8912 /* deassert preemption condition */ 8913 amdgpu_ring_set_preempt_cond_exec(ring, true); 8914 return r; 8915 } 8916 8917 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8918 { 8919 struct amdgpu_device *adev = ring->adev; 8920 struct v10_ce_ib_state ce_payload = {0}; 8921 uint64_t offset, ce_payload_gpu_addr; 8922 void *ce_payload_cpu_addr; 8923 int cnt; 8924 8925 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8926 8927 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8928 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8929 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8930 8931 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8932 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8933 WRITE_DATA_DST_SEL(8) | 8934 WR_CONFIRM) | 8935 WRITE_DATA_CACHE_POLICY(0)); 8936 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8937 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8938 8939 if (resume) 8940 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8941 sizeof(ce_payload) >> 2); 8942 else 8943 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8944 sizeof(ce_payload) >> 2); 8945 } 8946 8947 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8948 { 8949 struct amdgpu_device *adev = ring->adev; 8950 struct v10_de_ib_state de_payload = {0}; 8951 uint64_t offset, gds_addr, de_payload_gpu_addr; 8952 void *de_payload_cpu_addr; 8953 int cnt; 8954 8955 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8956 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8957 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8958 8959 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8960 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8961 PAGE_SIZE); 8962 8963 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8964 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8965 8966 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8967 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8968 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8969 WRITE_DATA_DST_SEL(8) | 8970 WR_CONFIRM) | 8971 WRITE_DATA_CACHE_POLICY(0)); 8972 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8973 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8974 8975 if (resume) 8976 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8977 sizeof(de_payload) >> 2); 8978 else 8979 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8980 sizeof(de_payload) >> 2); 8981 } 8982 8983 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8984 bool secure) 8985 { 8986 uint32_t v = secure ? FRAME_TMZ : 0; 8987 8988 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8989 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8990 } 8991 8992 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8993 uint32_t reg_val_offs) 8994 { 8995 struct amdgpu_device *adev = ring->adev; 8996 8997 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8998 amdgpu_ring_write(ring, 0 | /* src: register*/ 8999 (5 << 8) | /* dst: memory */ 9000 (1 << 20)); /* write confirm */ 9001 amdgpu_ring_write(ring, reg); 9002 amdgpu_ring_write(ring, 0); 9003 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 9004 reg_val_offs * 4)); 9005 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 9006 reg_val_offs * 4)); 9007 } 9008 9009 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 9010 uint32_t val) 9011 { 9012 uint32_t cmd = 0; 9013 9014 switch (ring->funcs->type) { 9015 case AMDGPU_RING_TYPE_GFX: 9016 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 9017 break; 9018 case AMDGPU_RING_TYPE_KIQ: 9019 cmd = (1 << 16); /* no inc addr */ 9020 break; 9021 default: 9022 cmd = WR_CONFIRM; 9023 break; 9024 } 9025 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 9026 amdgpu_ring_write(ring, cmd); 9027 amdgpu_ring_write(ring, reg); 9028 amdgpu_ring_write(ring, 0); 9029 amdgpu_ring_write(ring, val); 9030 } 9031 9032 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 9033 uint32_t val, uint32_t mask) 9034 { 9035 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 9036 } 9037 9038 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 9039 uint32_t reg0, uint32_t reg1, 9040 uint32_t ref, uint32_t mask) 9041 { 9042 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 9043 struct amdgpu_device *adev = ring->adev; 9044 bool fw_version_ok = false; 9045 9046 fw_version_ok = adev->gfx.cp_fw_write_wait; 9047 9048 if (fw_version_ok) 9049 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 9050 ref, mask, 0x20); 9051 else 9052 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 9053 ref, mask); 9054 } 9055 9056 static void 9057 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9058 uint32_t me, uint32_t pipe, 9059 enum amdgpu_interrupt_state state) 9060 { 9061 uint32_t cp_int_cntl, cp_int_cntl_reg; 9062 9063 if (!me) { 9064 switch (pipe) { 9065 case 0: 9066 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9067 break; 9068 case 1: 9069 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9070 break; 9071 default: 9072 DRM_DEBUG("invalid pipe %d\n", pipe); 9073 return; 9074 } 9075 } else { 9076 DRM_DEBUG("invalid me %d\n", me); 9077 return; 9078 } 9079 9080 switch (state) { 9081 case AMDGPU_IRQ_STATE_DISABLE: 9082 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9083 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9084 TIME_STAMP_INT_ENABLE, 0); 9085 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9086 break; 9087 case AMDGPU_IRQ_STATE_ENABLE: 9088 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9089 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9090 TIME_STAMP_INT_ENABLE, 1); 9091 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9092 break; 9093 default: 9094 break; 9095 } 9096 } 9097 9098 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9099 int me, int pipe, 9100 enum amdgpu_interrupt_state state) 9101 { 9102 u32 mec_int_cntl, mec_int_cntl_reg; 9103 9104 /* 9105 * amdgpu controls only the first MEC. That's why this function only 9106 * handles the setting of interrupts for this specific MEC. All other 9107 * pipes' interrupts are set by amdkfd. 9108 */ 9109 9110 if (me == 1) { 9111 switch (pipe) { 9112 case 0: 9113 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9114 break; 9115 case 1: 9116 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9117 break; 9118 case 2: 9119 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9120 break; 9121 case 3: 9122 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9123 break; 9124 default: 9125 DRM_DEBUG("invalid pipe %d\n", pipe); 9126 return; 9127 } 9128 } else { 9129 DRM_DEBUG("invalid me %d\n", me); 9130 return; 9131 } 9132 9133 switch (state) { 9134 case AMDGPU_IRQ_STATE_DISABLE: 9135 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9136 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9137 TIME_STAMP_INT_ENABLE, 0); 9138 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9139 break; 9140 case AMDGPU_IRQ_STATE_ENABLE: 9141 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9142 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9143 TIME_STAMP_INT_ENABLE, 1); 9144 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9145 break; 9146 default: 9147 break; 9148 } 9149 } 9150 9151 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9152 struct amdgpu_irq_src *src, 9153 unsigned int type, 9154 enum amdgpu_interrupt_state state) 9155 { 9156 switch (type) { 9157 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9158 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9159 break; 9160 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9161 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9162 break; 9163 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9164 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9165 break; 9166 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9167 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9168 break; 9169 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9170 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9171 break; 9172 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9173 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9174 break; 9175 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9176 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9177 break; 9178 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9179 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9180 break; 9181 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9182 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9183 break; 9184 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9185 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9186 break; 9187 default: 9188 break; 9189 } 9190 return 0; 9191 } 9192 9193 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9194 struct amdgpu_irq_src *source, 9195 struct amdgpu_iv_entry *entry) 9196 { 9197 int i; 9198 u8 me_id, pipe_id, queue_id; 9199 struct amdgpu_ring *ring; 9200 9201 DRM_DEBUG("IH: CP EOP\n"); 9202 9203 me_id = (entry->ring_id & 0x0c) >> 2; 9204 pipe_id = (entry->ring_id & 0x03) >> 0; 9205 queue_id = (entry->ring_id & 0x70) >> 4; 9206 9207 switch (me_id) { 9208 case 0: 9209 if (pipe_id == 0) 9210 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9211 else 9212 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9213 break; 9214 case 1: 9215 case 2: 9216 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9217 ring = &adev->gfx.compute_ring[i]; 9218 /* Per-queue interrupt is supported for MEC starting from VI. 9219 * The interrupt can only be enabled/disabled per pipe instead 9220 * of per queue. 9221 */ 9222 if ((ring->me == me_id) && 9223 (ring->pipe == pipe_id) && 9224 (ring->queue == queue_id)) 9225 amdgpu_fence_process(ring); 9226 } 9227 break; 9228 } 9229 9230 return 0; 9231 } 9232 9233 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9234 struct amdgpu_irq_src *source, 9235 unsigned int type, 9236 enum amdgpu_interrupt_state state) 9237 { 9238 u32 cp_int_cntl_reg, cp_int_cntl; 9239 int i, j; 9240 9241 switch (state) { 9242 case AMDGPU_IRQ_STATE_DISABLE: 9243 case AMDGPU_IRQ_STATE_ENABLE: 9244 for (i = 0; i < adev->gfx.me.num_me; i++) { 9245 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9246 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9247 9248 if (cp_int_cntl_reg) { 9249 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9250 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9251 PRIV_REG_INT_ENABLE, 9252 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9253 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9254 } 9255 } 9256 } 9257 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9258 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9259 /* MECs start at 1 */ 9260 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9261 9262 if (cp_int_cntl_reg) { 9263 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9264 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9265 PRIV_REG_INT_ENABLE, 9266 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9267 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9268 } 9269 } 9270 } 9271 break; 9272 default: 9273 break; 9274 } 9275 9276 return 0; 9277 } 9278 9279 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9280 struct amdgpu_irq_src *source, 9281 unsigned type, 9282 enum amdgpu_interrupt_state state) 9283 { 9284 u32 cp_int_cntl_reg, cp_int_cntl; 9285 int i, j; 9286 9287 switch (state) { 9288 case AMDGPU_IRQ_STATE_DISABLE: 9289 case AMDGPU_IRQ_STATE_ENABLE: 9290 for (i = 0; i < adev->gfx.me.num_me; i++) { 9291 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9292 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9293 9294 if (cp_int_cntl_reg) { 9295 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9296 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9297 OPCODE_ERROR_INT_ENABLE, 9298 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9299 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9300 } 9301 } 9302 } 9303 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9304 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9305 /* MECs start at 1 */ 9306 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9307 9308 if (cp_int_cntl_reg) { 9309 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9310 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9311 OPCODE_ERROR_INT_ENABLE, 9312 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9313 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9314 } 9315 } 9316 } 9317 break; 9318 default: 9319 break; 9320 } 9321 return 0; 9322 } 9323 9324 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9325 struct amdgpu_irq_src *source, 9326 unsigned int type, 9327 enum amdgpu_interrupt_state state) 9328 { 9329 u32 cp_int_cntl_reg, cp_int_cntl; 9330 int i, j; 9331 9332 switch (state) { 9333 case AMDGPU_IRQ_STATE_DISABLE: 9334 case AMDGPU_IRQ_STATE_ENABLE: 9335 for (i = 0; i < adev->gfx.me.num_me; i++) { 9336 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9337 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9338 9339 if (cp_int_cntl_reg) { 9340 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9341 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9342 PRIV_INSTR_INT_ENABLE, 9343 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9344 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9345 } 9346 } 9347 } 9348 break; 9349 default: 9350 break; 9351 } 9352 9353 return 0; 9354 } 9355 9356 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9357 struct amdgpu_iv_entry *entry) 9358 { 9359 u8 me_id, pipe_id, queue_id; 9360 struct amdgpu_ring *ring; 9361 int i; 9362 9363 me_id = (entry->ring_id & 0x0c) >> 2; 9364 pipe_id = (entry->ring_id & 0x03) >> 0; 9365 queue_id = (entry->ring_id & 0x70) >> 4; 9366 9367 switch (me_id) { 9368 case 0: 9369 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9370 ring = &adev->gfx.gfx_ring[i]; 9371 if (ring->me == me_id && ring->pipe == pipe_id && 9372 ring->queue == queue_id) 9373 drm_sched_fault(&ring->sched); 9374 } 9375 break; 9376 case 1: 9377 case 2: 9378 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9379 ring = &adev->gfx.compute_ring[i]; 9380 if (ring->me == me_id && ring->pipe == pipe_id && 9381 ring->queue == queue_id) 9382 drm_sched_fault(&ring->sched); 9383 } 9384 break; 9385 default: 9386 break; 9387 } 9388 } 9389 9390 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9391 struct amdgpu_irq_src *source, 9392 struct amdgpu_iv_entry *entry) 9393 { 9394 DRM_ERROR("Illegal register access in command stream\n"); 9395 gfx_v10_0_handle_priv_fault(adev, entry); 9396 return 0; 9397 } 9398 9399 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9400 struct amdgpu_irq_src *source, 9401 struct amdgpu_iv_entry *entry) 9402 { 9403 DRM_ERROR("Illegal opcode in command stream\n"); 9404 gfx_v10_0_handle_priv_fault(adev, entry); 9405 return 0; 9406 } 9407 9408 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9409 struct amdgpu_irq_src *source, 9410 struct amdgpu_iv_entry *entry) 9411 { 9412 DRM_ERROR("Illegal instruction in command stream\n"); 9413 gfx_v10_0_handle_priv_fault(adev, entry); 9414 return 0; 9415 } 9416 9417 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9418 struct amdgpu_irq_src *src, 9419 unsigned int type, 9420 enum amdgpu_interrupt_state state) 9421 { 9422 uint32_t tmp, target; 9423 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9424 9425 if (ring->me == 1) 9426 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9427 else 9428 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9429 target += ring->pipe; 9430 9431 switch (type) { 9432 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9433 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9434 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9435 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9436 GENERIC2_INT_ENABLE, 0); 9437 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9438 9439 tmp = RREG32_SOC15_IP(GC, target); 9440 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9441 GENERIC2_INT_ENABLE, 0); 9442 WREG32_SOC15_IP(GC, target, tmp); 9443 } else { 9444 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9445 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9446 GENERIC2_INT_ENABLE, 1); 9447 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9448 9449 tmp = RREG32_SOC15_IP(GC, target); 9450 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9451 GENERIC2_INT_ENABLE, 1); 9452 WREG32_SOC15_IP(GC, target, tmp); 9453 } 9454 break; 9455 default: 9456 /* kiq only support GENERIC2_INT now */ 9457 break; 9458 } 9459 return 0; 9460 } 9461 9462 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9463 struct amdgpu_irq_src *source, 9464 struct amdgpu_iv_entry *entry) 9465 { 9466 u8 me_id, pipe_id, queue_id; 9467 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9468 9469 me_id = (entry->ring_id & 0x0c) >> 2; 9470 pipe_id = (entry->ring_id & 0x03) >> 0; 9471 queue_id = (entry->ring_id & 0x70) >> 4; 9472 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9473 me_id, pipe_id, queue_id); 9474 9475 amdgpu_fence_process(ring); 9476 return 0; 9477 } 9478 9479 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9480 { 9481 const unsigned int gcr_cntl = 9482 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9483 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9484 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9485 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9486 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9487 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9488 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9489 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9490 9491 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9492 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9493 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9494 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9495 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9496 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9497 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9498 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9499 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9500 } 9501 9502 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9503 { 9504 /* Header itself is a NOP packet */ 9505 if (num_nop == 1) { 9506 amdgpu_ring_write(ring, ring->funcs->nop); 9507 return; 9508 } 9509 9510 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9511 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9512 9513 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9514 amdgpu_ring_insert_nop(ring, num_nop - 1); 9515 } 9516 9517 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, 9518 unsigned int vmid, 9519 struct amdgpu_fence *timedout_fence) 9520 { 9521 struct amdgpu_device *adev = ring->adev; 9522 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9523 struct amdgpu_ring *kiq_ring = &kiq->ring; 9524 unsigned long flags; 9525 u32 tmp; 9526 u64 addr; 9527 int r; 9528 9529 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9530 return -EINVAL; 9531 9532 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 9533 9534 spin_lock_irqsave(&kiq->ring_lock, flags); 9535 9536 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) { 9537 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9538 return -ENOMEM; 9539 } 9540 9541 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + 9542 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); 9543 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 9544 if (ring->pipe == 0) 9545 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); 9546 else 9547 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); 9548 9549 gfx_v10_0_ring_emit_wreg(kiq_ring, 9550 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); 9551 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, 9552 lower_32_bits(addr), upper_32_bits(addr), 9553 0, 1, 0x20); 9554 gfx_v10_0_ring_emit_reg_wait(kiq_ring, 9555 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); 9556 amdgpu_ring_commit(kiq_ring); 9557 r = amdgpu_ring_test_ring(kiq_ring); 9558 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9559 if (r) 9560 return r; 9561 9562 r = gfx_v10_0_kgq_init_queue(ring, true); 9563 if (r) { 9564 DRM_ERROR("fail to init kgq\n"); 9565 return r; 9566 } 9567 9568 spin_lock_irqsave(&kiq->ring_lock, flags); 9569 9570 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9571 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9572 return -ENOMEM; 9573 } 9574 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9575 amdgpu_ring_commit(kiq_ring); 9576 r = amdgpu_ring_test_ring(kiq_ring); 9577 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9578 if (r) 9579 return r; 9580 9581 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 9582 } 9583 9584 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, 9585 unsigned int vmid, 9586 struct amdgpu_fence *timedout_fence) 9587 { 9588 struct amdgpu_device *adev = ring->adev; 9589 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9590 struct amdgpu_ring *kiq_ring = &kiq->ring; 9591 unsigned long flags; 9592 int i, r; 9593 9594 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9595 return -EINVAL; 9596 9597 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 9598 9599 spin_lock_irqsave(&kiq->ring_lock, flags); 9600 9601 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 9602 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9603 return -ENOMEM; 9604 } 9605 9606 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 9607 0, 0); 9608 amdgpu_ring_commit(kiq_ring); 9609 r = amdgpu_ring_test_ring(kiq_ring); 9610 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9611 if (r) 9612 return r; 9613 9614 /* make sure dequeue is complete*/ 9615 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9616 mutex_lock(&adev->srbm_mutex); 9617 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 9618 for (i = 0; i < adev->usec_timeout; i++) { 9619 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 9620 break; 9621 udelay(1); 9622 } 9623 if (i >= adev->usec_timeout) 9624 r = -ETIMEDOUT; 9625 nv_grbm_select(adev, 0, 0, 0, 0); 9626 mutex_unlock(&adev->srbm_mutex); 9627 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9628 if (r) { 9629 dev_err(adev->dev, "fail to wait on hqd deactivate\n"); 9630 return r; 9631 } 9632 9633 r = gfx_v10_0_kcq_init_queue(ring, true); 9634 if (r) { 9635 dev_err(adev->dev, "fail to init kcq\n"); 9636 return r; 9637 } 9638 9639 spin_lock_irqsave(&kiq->ring_lock, flags); 9640 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9641 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9642 return -ENOMEM; 9643 } 9644 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9645 amdgpu_ring_commit(kiq_ring); 9646 r = amdgpu_ring_test_ring(kiq_ring); 9647 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9648 if (r) 9649 return r; 9650 9651 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 9652 } 9653 9654 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 9655 { 9656 struct amdgpu_device *adev = ip_block->adev; 9657 uint32_t i, j, k, reg, index = 0; 9658 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9659 9660 if (!adev->gfx.ip_dump_core) 9661 return; 9662 9663 for (i = 0; i < reg_count; i++) 9664 drm_printf(p, "%-50s \t 0x%08x\n", 9665 gc_reg_list_10_1[i].reg_name, 9666 adev->gfx.ip_dump_core[i]); 9667 9668 /* print compute queue registers for all instances */ 9669 if (!adev->gfx.ip_dump_compute_queues) 9670 return; 9671 9672 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9673 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9674 adev->gfx.mec.num_mec, 9675 adev->gfx.mec.num_pipe_per_mec, 9676 adev->gfx.mec.num_queue_per_pipe); 9677 9678 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9679 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9680 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9681 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9682 for (reg = 0; reg < reg_count; reg++) { 9683 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9684 drm_printf(p, "%-50s \t 0x%08x\n", 9685 "mmCP_MEC_ME2_HEADER_DUMP", 9686 adev->gfx.ip_dump_compute_queues[index + reg]); 9687 else 9688 drm_printf(p, "%-50s \t 0x%08x\n", 9689 gc_cp_reg_list_10[reg].reg_name, 9690 adev->gfx.ip_dump_compute_queues[index + reg]); 9691 } 9692 index += reg_count; 9693 } 9694 } 9695 } 9696 9697 /* print gfx queue registers for all instances */ 9698 if (!adev->gfx.ip_dump_gfx_queues) 9699 return; 9700 9701 index = 0; 9702 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9703 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9704 adev->gfx.me.num_me, 9705 adev->gfx.me.num_pipe_per_me, 9706 adev->gfx.me.num_queue_per_pipe); 9707 9708 for (i = 0; i < adev->gfx.me.num_me; i++) { 9709 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9710 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9711 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9712 for (reg = 0; reg < reg_count; reg++) { 9713 drm_printf(p, "%-50s \t 0x%08x\n", 9714 gc_gfx_queue_reg_list_10[reg].reg_name, 9715 adev->gfx.ip_dump_gfx_queues[index + reg]); 9716 } 9717 index += reg_count; 9718 } 9719 } 9720 } 9721 } 9722 9723 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) 9724 { 9725 struct amdgpu_device *adev = ip_block->adev; 9726 uint32_t i, j, k, reg, index = 0; 9727 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9728 9729 if (!adev->gfx.ip_dump_core) 9730 return; 9731 9732 amdgpu_gfx_off_ctrl(adev, false); 9733 for (i = 0; i < reg_count; i++) 9734 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9735 amdgpu_gfx_off_ctrl(adev, true); 9736 9737 /* dump compute queue registers for all instances */ 9738 if (!adev->gfx.ip_dump_compute_queues) 9739 return; 9740 9741 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9742 amdgpu_gfx_off_ctrl(adev, false); 9743 mutex_lock(&adev->srbm_mutex); 9744 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9745 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9746 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9747 /* ME0 is for GFX so start from 1 for CP */ 9748 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9749 9750 for (reg = 0; reg < reg_count; reg++) { 9751 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP) 9752 adev->gfx.ip_dump_compute_queues[index + reg] = 9753 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP)); 9754 else 9755 adev->gfx.ip_dump_compute_queues[index + reg] = 9756 RREG32(SOC15_REG_ENTRY_OFFSET( 9757 gc_cp_reg_list_10[reg])); 9758 } 9759 index += reg_count; 9760 } 9761 } 9762 } 9763 nv_grbm_select(adev, 0, 0, 0, 0); 9764 mutex_unlock(&adev->srbm_mutex); 9765 amdgpu_gfx_off_ctrl(adev, true); 9766 9767 /* dump gfx queue registers for all instances */ 9768 if (!adev->gfx.ip_dump_gfx_queues) 9769 return; 9770 9771 index = 0; 9772 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9773 amdgpu_gfx_off_ctrl(adev, false); 9774 mutex_lock(&adev->srbm_mutex); 9775 for (i = 0; i < adev->gfx.me.num_me; i++) { 9776 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9777 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9778 nv_grbm_select(adev, i, j, k, 0); 9779 9780 for (reg = 0; reg < reg_count; reg++) { 9781 adev->gfx.ip_dump_gfx_queues[index + reg] = 9782 RREG32(SOC15_REG_ENTRY_OFFSET( 9783 gc_gfx_queue_reg_list_10[reg])); 9784 } 9785 index += reg_count; 9786 } 9787 } 9788 } 9789 nv_grbm_select(adev, 0, 0, 0, 0); 9790 mutex_unlock(&adev->srbm_mutex); 9791 amdgpu_gfx_off_ctrl(adev, true); 9792 } 9793 9794 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 9795 { 9796 /* Emit the cleaner shader */ 9797 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 9798 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 9799 } 9800 9801 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring) 9802 { 9803 amdgpu_gfx_profile_ring_begin_use(ring); 9804 9805 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 9806 } 9807 9808 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) 9809 { 9810 amdgpu_gfx_profile_ring_end_use(ring); 9811 9812 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 9813 } 9814 9815 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9816 .name = "gfx_v10_0", 9817 .early_init = gfx_v10_0_early_init, 9818 .sw_init = gfx_v10_0_sw_init, 9819 .sw_fini = gfx_v10_0_sw_fini, 9820 .hw_init = gfx_v10_0_hw_init, 9821 .hw_fini = gfx_v10_0_hw_fini, 9822 .suspend = gfx_v10_0_suspend, 9823 .resume = gfx_v10_0_resume, 9824 .is_idle = gfx_v10_0_is_idle, 9825 .wait_for_idle = gfx_v10_0_wait_for_idle, 9826 .soft_reset = gfx_v10_0_soft_reset, 9827 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9828 .set_powergating_state = gfx_v10_0_set_powergating_state, 9829 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9830 .dump_ip_state = gfx_v10_ip_dump, 9831 .print_ip_state = gfx_v10_ip_print, 9832 }; 9833 9834 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9835 .type = AMDGPU_RING_TYPE_GFX, 9836 .align_mask = 0xff, 9837 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9838 .support_64bit_ptrs = true, 9839 .secure_submission_supported = true, 9840 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9841 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9842 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9843 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9844 5 + /* COND_EXEC */ 9845 7 + /* PIPELINE_SYNC */ 9846 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9847 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9848 4 + /* VM_FLUSH */ 9849 8 + /* FENCE for VM_FLUSH */ 9850 20 + /* GDS switch */ 9851 4 + /* double SWITCH_BUFFER, 9852 * the first COND_EXEC jump to the place 9853 * just prior to this double SWITCH_BUFFER 9854 */ 9855 5 + /* COND_EXEC */ 9856 7 + /* HDP_flush */ 9857 4 + /* VGT_flush */ 9858 14 + /* CE_META */ 9859 31 + /* DE_META */ 9860 3 + /* CNTX_CTRL */ 9861 5 + /* HDP_INVL */ 9862 8 + 8 + /* FENCE x2 */ 9863 2 + /* SWITCH_BUFFER */ 9864 8 + /* gfx_v10_0_emit_mem_sync */ 9865 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9866 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9867 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9868 .emit_fence = gfx_v10_0_ring_emit_fence, 9869 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9870 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9871 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9872 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9873 .test_ring = gfx_v10_0_ring_test_ring, 9874 .test_ib = gfx_v10_0_ring_test_ib, 9875 .insert_nop = gfx_v10_ring_insert_nop, 9876 .pad_ib = amdgpu_ring_generic_pad_ib, 9877 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9878 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9879 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9880 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9881 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9882 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9883 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9884 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9885 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9886 .reset = gfx_v10_0_reset_kgq, 9887 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9888 .begin_use = gfx_v10_0_ring_begin_use, 9889 .end_use = gfx_v10_0_ring_end_use, 9890 }; 9891 9892 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9893 .type = AMDGPU_RING_TYPE_COMPUTE, 9894 .align_mask = 0xff, 9895 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9896 .support_64bit_ptrs = true, 9897 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9898 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9899 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9900 .emit_frame_size = 9901 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9902 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9903 5 + /* hdp invalidate */ 9904 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9905 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9906 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9907 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9908 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9909 8 + /* gfx_v10_0_emit_mem_sync */ 9910 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9911 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9912 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9913 .emit_fence = gfx_v10_0_ring_emit_fence, 9914 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9915 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9916 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9917 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9918 .test_ring = gfx_v10_0_ring_test_ring, 9919 .test_ib = gfx_v10_0_ring_test_ib, 9920 .insert_nop = gfx_v10_ring_insert_nop, 9921 .pad_ib = amdgpu_ring_generic_pad_ib, 9922 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9923 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9924 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9925 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9926 .reset = gfx_v10_0_reset_kcq, 9927 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9928 .begin_use = gfx_v10_0_ring_begin_use, 9929 .end_use = gfx_v10_0_ring_end_use, 9930 }; 9931 9932 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9933 .type = AMDGPU_RING_TYPE_KIQ, 9934 .align_mask = 0xff, 9935 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9936 .support_64bit_ptrs = true, 9937 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9938 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9939 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9940 .emit_frame_size = 9941 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9942 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9943 5 + /*hdp invalidate */ 9944 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9945 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9946 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9947 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9948 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9949 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9950 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9951 .test_ring = gfx_v10_0_ring_test_ring, 9952 .test_ib = gfx_v10_0_ring_test_ib, 9953 .insert_nop = amdgpu_ring_insert_nop, 9954 .pad_ib = amdgpu_ring_generic_pad_ib, 9955 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9956 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9957 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9958 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9959 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9960 }; 9961 9962 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9963 { 9964 int i; 9965 9966 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9967 9968 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9969 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9970 9971 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9972 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9973 } 9974 9975 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9976 .set = gfx_v10_0_set_eop_interrupt_state, 9977 .process = gfx_v10_0_eop_irq, 9978 }; 9979 9980 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9981 .set = gfx_v10_0_set_priv_reg_fault_state, 9982 .process = gfx_v10_0_priv_reg_irq, 9983 }; 9984 9985 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 9986 .set = gfx_v10_0_set_bad_op_fault_state, 9987 .process = gfx_v10_0_bad_op_irq, 9988 }; 9989 9990 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9991 .set = gfx_v10_0_set_priv_inst_fault_state, 9992 .process = gfx_v10_0_priv_inst_irq, 9993 }; 9994 9995 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9996 .set = gfx_v10_0_kiq_set_interrupt_state, 9997 .process = gfx_v10_0_kiq_irq, 9998 }; 9999 10000 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 10001 { 10002 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 10003 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 10004 10005 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 10006 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 10007 10008 adev->gfx.priv_reg_irq.num_types = 1; 10009 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 10010 10011 adev->gfx.bad_op_irq.num_types = 1; 10012 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 10013 10014 adev->gfx.priv_inst_irq.num_types = 1; 10015 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 10016 } 10017 10018 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 10019 { 10020 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 10021 case IP_VERSION(10, 1, 10): 10022 case IP_VERSION(10, 1, 1): 10023 case IP_VERSION(10, 1, 3): 10024 case IP_VERSION(10, 1, 4): 10025 case IP_VERSION(10, 3, 2): 10026 case IP_VERSION(10, 3, 1): 10027 case IP_VERSION(10, 3, 4): 10028 case IP_VERSION(10, 3, 5): 10029 case IP_VERSION(10, 3, 6): 10030 case IP_VERSION(10, 3, 3): 10031 case IP_VERSION(10, 3, 7): 10032 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 10033 break; 10034 case IP_VERSION(10, 1, 2): 10035 case IP_VERSION(10, 3, 0): 10036 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 10037 break; 10038 default: 10039 break; 10040 } 10041 } 10042 10043 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 10044 { 10045 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 10046 adev->gfx.config.max_sh_per_se * 10047 adev->gfx.config.max_shader_engines; 10048 10049 adev->gds.gds_size = 0x10000; 10050 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 10051 adev->gds.gws_size = 64; 10052 adev->gds.oa_size = 16; 10053 } 10054 10055 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 10056 { 10057 /* set gfx eng mqd */ 10058 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 10059 sizeof(struct v10_gfx_mqd); 10060 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 10061 gfx_v10_0_gfx_mqd_init; 10062 /* set compute eng mqd */ 10063 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 10064 sizeof(struct v10_compute_mqd); 10065 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 10066 gfx_v10_0_compute_mqd_init; 10067 } 10068 10069 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 10070 u32 bitmap) 10071 { 10072 u32 data; 10073 10074 if (!bitmap) 10075 return; 10076 10077 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10078 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10079 10080 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 10081 } 10082 10083 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 10084 { 10085 u32 disabled_mask = 10086 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 10087 u32 efuse_setting = 0; 10088 u32 vbios_setting = 0; 10089 10090 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 10091 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10092 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10093 10094 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 10095 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10096 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10097 10098 disabled_mask |= efuse_setting | vbios_setting; 10099 10100 return (~disabled_mask); 10101 } 10102 10103 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 10104 { 10105 u32 wgp_idx, wgp_active_bitmap; 10106 u32 cu_bitmap_per_wgp, cu_active_bitmap; 10107 10108 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 10109 cu_active_bitmap = 0; 10110 10111 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 10112 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 10113 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 10114 if (wgp_active_bitmap & (1 << wgp_idx)) 10115 cu_active_bitmap |= cu_bitmap_per_wgp; 10116 } 10117 10118 return cu_active_bitmap; 10119 } 10120 10121 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 10122 struct amdgpu_cu_info *cu_info) 10123 { 10124 int i, j, k, counter, active_cu_number = 0; 10125 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 10126 unsigned int disable_masks[4 * 2]; 10127 10128 if (!adev || !cu_info) 10129 return -EINVAL; 10130 10131 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 10132 10133 mutex_lock(&adev->grbm_idx_mutex); 10134 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 10135 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 10136 bitmap = i * adev->gfx.config.max_sh_per_se + j; 10137 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 10138 IP_VERSION(10, 3, 0)) || 10139 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10140 IP_VERSION(10, 3, 3)) || 10141 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10142 IP_VERSION(10, 3, 6)) || 10143 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10144 IP_VERSION(10, 3, 7))) && 10145 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 10146 continue; 10147 mask = 1; 10148 ao_bitmap = 0; 10149 counter = 0; 10150 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 10151 if (i < 4 && j < 2) 10152 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 10153 adev, disable_masks[i * 2 + j]); 10154 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 10155 cu_info->bitmap[0][i][j] = bitmap; 10156 10157 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 10158 if (bitmap & mask) { 10159 if (counter < adev->gfx.config.max_cu_per_sh) 10160 ao_bitmap |= mask; 10161 counter++; 10162 } 10163 mask <<= 1; 10164 } 10165 active_cu_number += counter; 10166 if (i < 2 && j < 2) 10167 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 10168 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 10169 } 10170 } 10171 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 10172 mutex_unlock(&adev->grbm_idx_mutex); 10173 10174 cu_info->number = active_cu_number; 10175 cu_info->ao_cu_mask = ao_cu_mask; 10176 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 10177 10178 return 0; 10179 } 10180 10181 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 10182 { 10183 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 10184 10185 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 10186 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10187 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10188 10189 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 10190 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10191 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10192 10193 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 10194 adev->gfx.config.max_shader_engines); 10195 disabled_sa = efuse_setting | vbios_setting; 10196 disabled_sa &= max_sa_mask; 10197 10198 return disabled_sa; 10199 } 10200 10201 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 10202 { 10203 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 10204 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 10205 10206 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 10207 10208 max_sa_per_se = adev->gfx.config.max_sh_per_se; 10209 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 10210 max_shader_engines = adev->gfx.config.max_shader_engines; 10211 10212 for (se_index = 0; max_shader_engines > se_index; se_index++) { 10213 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 10214 disabled_sa_per_se &= max_sa_per_se_mask; 10215 if (disabled_sa_per_se == max_sa_per_se_mask) { 10216 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 10217 break; 10218 } 10219 } 10220 } 10221 10222 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 10223 { 10224 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 10225 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 10226 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 10227 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 10228 10229 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 10230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 10231 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 10232 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 10233 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 10234 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 10235 10236 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 10237 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 10238 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 10239 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 10240 10241 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 10242 10243 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 10244 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 10245 } 10246 10247 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 10248 .type = AMD_IP_BLOCK_TYPE_GFX, 10249 .major = 10, 10250 .minor = 0, 10251 .rev = 0, 10252 .funcs = &gfx_v10_0_ip_funcs, 10253 }; 10254