1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /** 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 115 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 117 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 119 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 121 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 125 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 128 129 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 131 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 133 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 135 #define mmCP_HYP_CE_UCODE_DATA 0x5819 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 137 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 139 #define mmCP_HYP_ME_UCODE_DATA 0x5817 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 141 142 #define mmCPG_PSP_DEBUG 0x5c10 143 #define mmCPG_PSP_DEBUG_BASE_IDX 1 144 #define mmCPC_PSP_DEBUG 0x5c11 145 #define mmCPC_PSP_DEBUG_BASE_IDX 1 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 148 149 //CC_GC_SA_UNIT_DISABLE 150 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 154 //GC_USER_SA_UNIT_DISABLE 155 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 159 //PA_SC_ENHANCE_3 160 #define mmPA_SC_ENHANCE_3 0x1085 161 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 164 165 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 167 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 172 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 175 176 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 177 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 178 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 179 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 180 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 181 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 182 183 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 184 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 185 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 186 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 187 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 188 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 189 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 190 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 191 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 192 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 194 195 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 196 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 197 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 198 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 199 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 200 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 201 202 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 205 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 219 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 226 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 229 230 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 231 { 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 272 }; 273 274 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 275 { 276 /* Pending on emulation bring up */ 277 }; 278 279 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 280 { 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1333 }; 1334 1335 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1336 { 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1375 }; 1376 1377 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1378 { 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1419 }; 1420 1421 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1422 { 1423 static void *scratch_reg0; 1424 static void *scratch_reg1; 1425 static void *spare_int; 1426 uint32_t i = 0; 1427 uint32_t retries = 50000; 1428 1429 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1430 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1431 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1432 1433 if (amdgpu_sriov_runtime(adev)) { 1434 pr_err("shouldn't call rlcg write register during runtime\n"); 1435 return; 1436 } 1437 1438 writel(v, scratch_reg0); 1439 writel(offset | 0x80000000, scratch_reg1); 1440 writel(1, spare_int); 1441 for (i = 0; i < retries; i++) { 1442 u32 tmp; 1443 1444 tmp = readl(scratch_reg1); 1445 if (!(tmp & 0x80000000)) 1446 break; 1447 1448 udelay(10); 1449 } 1450 1451 if (i >= retries) 1452 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1453 } 1454 1455 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1456 { 1457 /* Pending on emulation bring up */ 1458 }; 1459 1460 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1461 { 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2082 }; 2083 2084 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2085 { 2086 /* Pending on emulation bring up */ 2087 }; 2088 2089 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2090 { 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3143 }; 3144 3145 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3146 { 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3189 }; 3190 3191 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3192 { 3193 /* Pending on emulation bring up */ 3194 }; 3195 3196 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3197 { 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3239 3240 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3242 }; 3243 3244 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3245 { 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3269 3270 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3272 }; 3273 3274 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3275 { 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3311 }; 3312 3313 #define DEFAULT_SH_MEM_CONFIG \ 3314 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3315 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3316 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3317 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3318 3319 3320 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3321 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3322 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3323 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3324 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3325 struct amdgpu_cu_info *cu_info); 3326 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3327 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3328 u32 sh_num, u32 instance); 3329 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3330 3331 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3332 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3333 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3334 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3335 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3336 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3337 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3338 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3339 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3340 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3341 3342 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3343 { 3344 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3345 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3346 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3347 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3348 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3349 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3350 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3351 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3352 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3353 } 3354 3355 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3356 struct amdgpu_ring *ring) 3357 { 3358 struct amdgpu_device *adev = kiq_ring->adev; 3359 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3360 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3361 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3362 3363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3364 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3366 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3367 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3368 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3369 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3370 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3371 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3372 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3373 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3374 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3375 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3376 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3377 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3378 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3379 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3380 } 3381 3382 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3383 struct amdgpu_ring *ring, 3384 enum amdgpu_unmap_queues_action action, 3385 u64 gpu_addr, u64 seq) 3386 { 3387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3388 3389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3390 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3391 PACKET3_UNMAP_QUEUES_ACTION(action) | 3392 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3393 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3394 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3395 amdgpu_ring_write(kiq_ring, 3396 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3397 3398 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3399 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3400 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3401 amdgpu_ring_write(kiq_ring, seq); 3402 } else { 3403 amdgpu_ring_write(kiq_ring, 0); 3404 amdgpu_ring_write(kiq_ring, 0); 3405 amdgpu_ring_write(kiq_ring, 0); 3406 } 3407 } 3408 3409 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3410 struct amdgpu_ring *ring, 3411 u64 addr, 3412 u64 seq) 3413 { 3414 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3415 3416 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3417 amdgpu_ring_write(kiq_ring, 3418 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3419 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3420 PACKET3_QUERY_STATUS_COMMAND(2)); 3421 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3422 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3423 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3424 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3425 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3426 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3427 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3428 } 3429 3430 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3431 uint16_t pasid, uint32_t flush_type, 3432 bool all_hub) 3433 { 3434 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3435 amdgpu_ring_write(kiq_ring, 3436 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3437 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3438 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3439 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3440 } 3441 3442 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3443 .kiq_set_resources = gfx10_kiq_set_resources, 3444 .kiq_map_queues = gfx10_kiq_map_queues, 3445 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3446 .kiq_query_status = gfx10_kiq_query_status, 3447 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3448 .set_resources_size = 8, 3449 .map_queues_size = 7, 3450 .unmap_queues_size = 6, 3451 .query_status_size = 7, 3452 .invalidate_tlbs_size = 2, 3453 }; 3454 3455 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3456 { 3457 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3458 } 3459 3460 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3461 { 3462 switch (adev->asic_type) { 3463 case CHIP_NAVI10: 3464 soc15_program_register_sequence(adev, 3465 golden_settings_gc_rlc_spm_10_0_nv10, 3466 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3467 break; 3468 case CHIP_NAVI14: 3469 soc15_program_register_sequence(adev, 3470 golden_settings_gc_rlc_spm_10_1_nv14, 3471 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3472 break; 3473 case CHIP_NAVI12: 3474 soc15_program_register_sequence(adev, 3475 golden_settings_gc_rlc_spm_10_1_2_nv12, 3476 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3477 break; 3478 default: 3479 break; 3480 } 3481 } 3482 3483 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3484 { 3485 switch (adev->asic_type) { 3486 case CHIP_NAVI10: 3487 soc15_program_register_sequence(adev, 3488 golden_settings_gc_10_1, 3489 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3490 soc15_program_register_sequence(adev, 3491 golden_settings_gc_10_0_nv10, 3492 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3493 break; 3494 case CHIP_NAVI14: 3495 soc15_program_register_sequence(adev, 3496 golden_settings_gc_10_1_1, 3497 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3498 soc15_program_register_sequence(adev, 3499 golden_settings_gc_10_1_nv14, 3500 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3501 break; 3502 case CHIP_NAVI12: 3503 soc15_program_register_sequence(adev, 3504 golden_settings_gc_10_1_2, 3505 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3506 soc15_program_register_sequence(adev, 3507 golden_settings_gc_10_1_2_nv12, 3508 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3509 break; 3510 case CHIP_SIENNA_CICHLID: 3511 soc15_program_register_sequence(adev, 3512 golden_settings_gc_10_3, 3513 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3514 soc15_program_register_sequence(adev, 3515 golden_settings_gc_10_3_sienna_cichlid, 3516 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3517 break; 3518 case CHIP_NAVY_FLOUNDER: 3519 soc15_program_register_sequence(adev, 3520 golden_settings_gc_10_3_2, 3521 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3522 break; 3523 case CHIP_VANGOGH: 3524 soc15_program_register_sequence(adev, 3525 golden_settings_gc_10_3_vangogh, 3526 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3527 break; 3528 case CHIP_DIMGREY_CAVEFISH: 3529 soc15_program_register_sequence(adev, 3530 golden_settings_gc_10_3_4, 3531 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3532 break; 3533 default: 3534 break; 3535 } 3536 gfx_v10_0_init_spm_golden_registers(adev); 3537 } 3538 3539 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3540 { 3541 adev->gfx.scratch.num_reg = 8; 3542 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3543 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3544 } 3545 3546 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3547 bool wc, uint32_t reg, uint32_t val) 3548 { 3549 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3550 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3551 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3552 amdgpu_ring_write(ring, reg); 3553 amdgpu_ring_write(ring, 0); 3554 amdgpu_ring_write(ring, val); 3555 } 3556 3557 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3558 int mem_space, int opt, uint32_t addr0, 3559 uint32_t addr1, uint32_t ref, uint32_t mask, 3560 uint32_t inv) 3561 { 3562 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3563 amdgpu_ring_write(ring, 3564 /* memory (1) or register (0) */ 3565 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3566 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3567 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3568 WAIT_REG_MEM_ENGINE(eng_sel))); 3569 3570 if (mem_space) 3571 BUG_ON(addr0 & 0x3); /* Dword align */ 3572 amdgpu_ring_write(ring, addr0); 3573 amdgpu_ring_write(ring, addr1); 3574 amdgpu_ring_write(ring, ref); 3575 amdgpu_ring_write(ring, mask); 3576 amdgpu_ring_write(ring, inv); /* poll interval */ 3577 } 3578 3579 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3580 { 3581 struct amdgpu_device *adev = ring->adev; 3582 uint32_t scratch; 3583 uint32_t tmp = 0; 3584 unsigned i; 3585 int r; 3586 3587 r = amdgpu_gfx_scratch_get(adev, &scratch); 3588 if (r) { 3589 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3590 return r; 3591 } 3592 3593 WREG32(scratch, 0xCAFEDEAD); 3594 3595 r = amdgpu_ring_alloc(ring, 3); 3596 if (r) { 3597 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3598 ring->idx, r); 3599 amdgpu_gfx_scratch_free(adev, scratch); 3600 return r; 3601 } 3602 3603 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3604 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3605 amdgpu_ring_write(ring, 0xDEADBEEF); 3606 amdgpu_ring_commit(ring); 3607 3608 for (i = 0; i < adev->usec_timeout; i++) { 3609 tmp = RREG32(scratch); 3610 if (tmp == 0xDEADBEEF) 3611 break; 3612 if (amdgpu_emu_mode == 1) 3613 msleep(1); 3614 else 3615 udelay(1); 3616 } 3617 3618 if (i >= adev->usec_timeout) 3619 r = -ETIMEDOUT; 3620 3621 amdgpu_gfx_scratch_free(adev, scratch); 3622 3623 return r; 3624 } 3625 3626 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3627 { 3628 struct amdgpu_device *adev = ring->adev; 3629 struct amdgpu_ib ib; 3630 struct dma_fence *f = NULL; 3631 unsigned index; 3632 uint64_t gpu_addr; 3633 uint32_t tmp; 3634 long r; 3635 3636 r = amdgpu_device_wb_get(adev, &index); 3637 if (r) 3638 return r; 3639 3640 gpu_addr = adev->wb.gpu_addr + (index * 4); 3641 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3642 memset(&ib, 0, sizeof(ib)); 3643 r = amdgpu_ib_get(adev, NULL, 16, 3644 AMDGPU_IB_POOL_DIRECT, &ib); 3645 if (r) 3646 goto err1; 3647 3648 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3649 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3650 ib.ptr[2] = lower_32_bits(gpu_addr); 3651 ib.ptr[3] = upper_32_bits(gpu_addr); 3652 ib.ptr[4] = 0xDEADBEEF; 3653 ib.length_dw = 5; 3654 3655 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3656 if (r) 3657 goto err2; 3658 3659 r = dma_fence_wait_timeout(f, false, timeout); 3660 if (r == 0) { 3661 r = -ETIMEDOUT; 3662 goto err2; 3663 } else if (r < 0) { 3664 goto err2; 3665 } 3666 3667 tmp = adev->wb.wb[index]; 3668 if (tmp == 0xDEADBEEF) 3669 r = 0; 3670 else 3671 r = -EINVAL; 3672 err2: 3673 amdgpu_ib_free(adev, &ib, NULL); 3674 dma_fence_put(f); 3675 err1: 3676 amdgpu_device_wb_free(adev, index); 3677 return r; 3678 } 3679 3680 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3681 { 3682 release_firmware(adev->gfx.pfp_fw); 3683 adev->gfx.pfp_fw = NULL; 3684 release_firmware(adev->gfx.me_fw); 3685 adev->gfx.me_fw = NULL; 3686 release_firmware(adev->gfx.ce_fw); 3687 adev->gfx.ce_fw = NULL; 3688 release_firmware(adev->gfx.rlc_fw); 3689 adev->gfx.rlc_fw = NULL; 3690 release_firmware(adev->gfx.mec_fw); 3691 adev->gfx.mec_fw = NULL; 3692 release_firmware(adev->gfx.mec2_fw); 3693 adev->gfx.mec2_fw = NULL; 3694 3695 kfree(adev->gfx.rlc.register_list_format); 3696 } 3697 3698 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3699 { 3700 adev->gfx.cp_fw_write_wait = false; 3701 3702 switch (adev->asic_type) { 3703 case CHIP_NAVI10: 3704 case CHIP_NAVI12: 3705 case CHIP_NAVI14: 3706 if ((adev->gfx.me_fw_version >= 0x00000046) && 3707 (adev->gfx.me_feature_version >= 27) && 3708 (adev->gfx.pfp_fw_version >= 0x00000068) && 3709 (adev->gfx.pfp_feature_version >= 27) && 3710 (adev->gfx.mec_fw_version >= 0x0000005b) && 3711 (adev->gfx.mec_feature_version >= 27)) 3712 adev->gfx.cp_fw_write_wait = true; 3713 break; 3714 case CHIP_SIENNA_CICHLID: 3715 case CHIP_NAVY_FLOUNDER: 3716 case CHIP_VANGOGH: 3717 case CHIP_DIMGREY_CAVEFISH: 3718 adev->gfx.cp_fw_write_wait = true; 3719 break; 3720 default: 3721 break; 3722 } 3723 3724 if (!adev->gfx.cp_fw_write_wait) 3725 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3726 } 3727 3728 3729 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3730 { 3731 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3732 3733 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3734 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3735 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3736 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3737 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3738 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3739 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3740 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3741 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3742 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3743 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3744 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3745 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3746 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3747 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3748 } 3749 3750 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3751 { 3752 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3753 3754 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3755 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3756 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3757 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3758 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3759 } 3760 3761 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3762 { 3763 bool ret = false; 3764 3765 switch (adev->pdev->revision) { 3766 case 0xc2: 3767 case 0xc3: 3768 ret = true; 3769 break; 3770 default: 3771 ret = false; 3772 break; 3773 } 3774 3775 return ret ; 3776 } 3777 3778 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3779 { 3780 switch (adev->asic_type) { 3781 case CHIP_NAVI10: 3782 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3783 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3784 break; 3785 default: 3786 break; 3787 } 3788 } 3789 3790 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3791 { 3792 const char *chip_name; 3793 char fw_name[40]; 3794 char wks[10]; 3795 int err; 3796 struct amdgpu_firmware_info *info = NULL; 3797 const struct common_firmware_header *header = NULL; 3798 const struct gfx_firmware_header_v1_0 *cp_hdr; 3799 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3800 unsigned int *tmp = NULL; 3801 unsigned int i = 0; 3802 uint16_t version_major; 3803 uint16_t version_minor; 3804 3805 DRM_DEBUG("\n"); 3806 3807 memset(wks, 0, sizeof(wks)); 3808 switch (adev->asic_type) { 3809 case CHIP_NAVI10: 3810 chip_name = "navi10"; 3811 break; 3812 case CHIP_NAVI14: 3813 chip_name = "navi14"; 3814 if (!(adev->pdev->device == 0x7340 && 3815 adev->pdev->revision != 0x00)) 3816 snprintf(wks, sizeof(wks), "_wks"); 3817 break; 3818 case CHIP_NAVI12: 3819 chip_name = "navi12"; 3820 break; 3821 case CHIP_SIENNA_CICHLID: 3822 chip_name = "sienna_cichlid"; 3823 break; 3824 case CHIP_NAVY_FLOUNDER: 3825 chip_name = "navy_flounder"; 3826 break; 3827 case CHIP_VANGOGH: 3828 chip_name = "vangogh"; 3829 break; 3830 case CHIP_DIMGREY_CAVEFISH: 3831 chip_name = "dimgrey_cavefish"; 3832 break; 3833 default: 3834 BUG(); 3835 } 3836 3837 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3838 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3839 if (err) 3840 goto out; 3841 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3842 if (err) 3843 goto out; 3844 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3845 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3846 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3847 3848 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3849 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3850 if (err) 3851 goto out; 3852 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3853 if (err) 3854 goto out; 3855 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3856 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3857 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3858 3859 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3860 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3861 if (err) 3862 goto out; 3863 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3864 if (err) 3865 goto out; 3866 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3867 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3868 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3869 3870 if (!amdgpu_sriov_vf(adev)) { 3871 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3872 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3873 if (err) 3874 goto out; 3875 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3876 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3877 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3878 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3879 3880 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3881 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3882 adev->gfx.rlc.save_and_restore_offset = 3883 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3884 adev->gfx.rlc.clear_state_descriptor_offset = 3885 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3886 adev->gfx.rlc.avail_scratch_ram_locations = 3887 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3888 adev->gfx.rlc.reg_restore_list_size = 3889 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3890 adev->gfx.rlc.reg_list_format_start = 3891 le32_to_cpu(rlc_hdr->reg_list_format_start); 3892 adev->gfx.rlc.reg_list_format_separate_start = 3893 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3894 adev->gfx.rlc.starting_offsets_start = 3895 le32_to_cpu(rlc_hdr->starting_offsets_start); 3896 adev->gfx.rlc.reg_list_format_size_bytes = 3897 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3898 adev->gfx.rlc.reg_list_size_bytes = 3899 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3900 adev->gfx.rlc.register_list_format = 3901 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3902 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3903 if (!adev->gfx.rlc.register_list_format) { 3904 err = -ENOMEM; 3905 goto out; 3906 } 3907 3908 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3909 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3910 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3911 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3912 3913 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3914 3915 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3916 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3917 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3918 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3919 3920 if (version_major == 2) { 3921 if (version_minor >= 1) 3922 gfx_v10_0_init_rlc_ext_microcode(adev); 3923 if (version_minor == 2) 3924 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3925 } 3926 } 3927 3928 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3929 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3930 if (err) 3931 goto out; 3932 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3933 if (err) 3934 goto out; 3935 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3936 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3937 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3938 3939 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3940 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3941 if (!err) { 3942 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3943 if (err) 3944 goto out; 3945 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3946 adev->gfx.mec2_fw->data; 3947 adev->gfx.mec2_fw_version = 3948 le32_to_cpu(cp_hdr->header.ucode_version); 3949 adev->gfx.mec2_feature_version = 3950 le32_to_cpu(cp_hdr->ucode_feature_version); 3951 } else { 3952 err = 0; 3953 adev->gfx.mec2_fw = NULL; 3954 } 3955 3956 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3957 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3958 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3959 info->fw = adev->gfx.pfp_fw; 3960 header = (const struct common_firmware_header *)info->fw->data; 3961 adev->firmware.fw_size += 3962 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3963 3964 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3965 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3966 info->fw = adev->gfx.me_fw; 3967 header = (const struct common_firmware_header *)info->fw->data; 3968 adev->firmware.fw_size += 3969 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3970 3971 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3972 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3973 info->fw = adev->gfx.ce_fw; 3974 header = (const struct common_firmware_header *)info->fw->data; 3975 adev->firmware.fw_size += 3976 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3977 3978 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3979 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3980 info->fw = adev->gfx.rlc_fw; 3981 if (info->fw) { 3982 header = (const struct common_firmware_header *)info->fw->data; 3983 adev->firmware.fw_size += 3984 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3985 } 3986 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3987 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3988 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3989 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3990 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3991 info->fw = adev->gfx.rlc_fw; 3992 adev->firmware.fw_size += 3993 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3994 3995 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3996 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3997 info->fw = adev->gfx.rlc_fw; 3998 adev->firmware.fw_size += 3999 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4000 4001 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4002 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4003 info->fw = adev->gfx.rlc_fw; 4004 adev->firmware.fw_size += 4005 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4006 4007 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4008 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4009 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4010 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4011 info->fw = adev->gfx.rlc_fw; 4012 adev->firmware.fw_size += 4013 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4014 4015 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4016 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4017 info->fw = adev->gfx.rlc_fw; 4018 adev->firmware.fw_size += 4019 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4020 } 4021 } 4022 4023 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4024 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4025 info->fw = adev->gfx.mec_fw; 4026 header = (const struct common_firmware_header *)info->fw->data; 4027 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4028 adev->firmware.fw_size += 4029 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4030 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4031 4032 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4033 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4034 info->fw = adev->gfx.mec_fw; 4035 adev->firmware.fw_size += 4036 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4037 4038 if (adev->gfx.mec2_fw) { 4039 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4040 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4041 info->fw = adev->gfx.mec2_fw; 4042 header = (const struct common_firmware_header *)info->fw->data; 4043 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4044 adev->firmware.fw_size += 4045 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4046 le32_to_cpu(cp_hdr->jt_size) * 4, 4047 PAGE_SIZE); 4048 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4049 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4050 info->fw = adev->gfx.mec2_fw; 4051 adev->firmware.fw_size += 4052 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4053 PAGE_SIZE); 4054 } 4055 } 4056 4057 gfx_v10_0_check_fw_write_wait(adev); 4058 out: 4059 if (err) { 4060 dev_err(adev->dev, 4061 "gfx10: Failed to load firmware \"%s\"\n", 4062 fw_name); 4063 release_firmware(adev->gfx.pfp_fw); 4064 adev->gfx.pfp_fw = NULL; 4065 release_firmware(adev->gfx.me_fw); 4066 adev->gfx.me_fw = NULL; 4067 release_firmware(adev->gfx.ce_fw); 4068 adev->gfx.ce_fw = NULL; 4069 release_firmware(adev->gfx.rlc_fw); 4070 adev->gfx.rlc_fw = NULL; 4071 release_firmware(adev->gfx.mec_fw); 4072 adev->gfx.mec_fw = NULL; 4073 release_firmware(adev->gfx.mec2_fw); 4074 adev->gfx.mec2_fw = NULL; 4075 } 4076 4077 gfx_v10_0_check_gfxoff_flag(adev); 4078 4079 return err; 4080 } 4081 4082 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4083 { 4084 u32 count = 0; 4085 const struct cs_section_def *sect = NULL; 4086 const struct cs_extent_def *ext = NULL; 4087 4088 /* begin clear state */ 4089 count += 2; 4090 /* context control state */ 4091 count += 3; 4092 4093 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4094 for (ext = sect->section; ext->extent != NULL; ++ext) { 4095 if (sect->id == SECT_CONTEXT) 4096 count += 2 + ext->reg_count; 4097 else 4098 return 0; 4099 } 4100 } 4101 4102 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4103 count += 3; 4104 /* end clear state */ 4105 count += 2; 4106 /* clear state */ 4107 count += 2; 4108 4109 return count; 4110 } 4111 4112 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4113 volatile u32 *buffer) 4114 { 4115 u32 count = 0, i; 4116 const struct cs_section_def *sect = NULL; 4117 const struct cs_extent_def *ext = NULL; 4118 int ctx_reg_offset; 4119 4120 if (adev->gfx.rlc.cs_data == NULL) 4121 return; 4122 if (buffer == NULL) 4123 return; 4124 4125 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4126 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4127 4128 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4129 buffer[count++] = cpu_to_le32(0x80000000); 4130 buffer[count++] = cpu_to_le32(0x80000000); 4131 4132 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4133 for (ext = sect->section; ext->extent != NULL; ++ext) { 4134 if (sect->id == SECT_CONTEXT) { 4135 buffer[count++] = 4136 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4137 buffer[count++] = cpu_to_le32(ext->reg_index - 4138 PACKET3_SET_CONTEXT_REG_START); 4139 for (i = 0; i < ext->reg_count; i++) 4140 buffer[count++] = cpu_to_le32(ext->extent[i]); 4141 } else { 4142 return; 4143 } 4144 } 4145 } 4146 4147 ctx_reg_offset = 4148 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4149 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4150 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4151 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4152 4153 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4154 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4155 4156 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4157 buffer[count++] = cpu_to_le32(0); 4158 } 4159 4160 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4161 { 4162 /* clear state block */ 4163 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4164 &adev->gfx.rlc.clear_state_gpu_addr, 4165 (void **)&adev->gfx.rlc.cs_ptr); 4166 4167 /* jump table block */ 4168 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4169 &adev->gfx.rlc.cp_table_gpu_addr, 4170 (void **)&adev->gfx.rlc.cp_table_ptr); 4171 } 4172 4173 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4174 { 4175 const struct cs_section_def *cs_data; 4176 int r; 4177 4178 adev->gfx.rlc.cs_data = gfx10_cs_data; 4179 4180 cs_data = adev->gfx.rlc.cs_data; 4181 4182 if (cs_data) { 4183 /* init clear state block */ 4184 r = amdgpu_gfx_rlc_init_csb(adev); 4185 if (r) 4186 return r; 4187 } 4188 4189 /* init spm vmid with 0xf */ 4190 if (adev->gfx.rlc.funcs->update_spm_vmid) 4191 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4192 4193 return 0; 4194 } 4195 4196 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4197 { 4198 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4199 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4200 } 4201 4202 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4203 { 4204 int r; 4205 4206 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4207 4208 amdgpu_gfx_graphics_queue_acquire(adev); 4209 4210 r = gfx_v10_0_init_microcode(adev); 4211 if (r) 4212 DRM_ERROR("Failed to load gfx firmware!\n"); 4213 4214 return r; 4215 } 4216 4217 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4218 { 4219 int r; 4220 u32 *hpd; 4221 const __le32 *fw_data = NULL; 4222 unsigned fw_size; 4223 u32 *fw = NULL; 4224 size_t mec_hpd_size; 4225 4226 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4227 4228 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4229 4230 /* take ownership of the relevant compute queues */ 4231 amdgpu_gfx_compute_queue_acquire(adev); 4232 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4233 4234 if (mec_hpd_size) { 4235 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4236 AMDGPU_GEM_DOMAIN_GTT, 4237 &adev->gfx.mec.hpd_eop_obj, 4238 &adev->gfx.mec.hpd_eop_gpu_addr, 4239 (void **)&hpd); 4240 if (r) { 4241 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4242 gfx_v10_0_mec_fini(adev); 4243 return r; 4244 } 4245 4246 memset(hpd, 0, mec_hpd_size); 4247 4248 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4249 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4250 } 4251 4252 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4253 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4254 4255 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4256 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4257 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4258 4259 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4260 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4261 &adev->gfx.mec.mec_fw_obj, 4262 &adev->gfx.mec.mec_fw_gpu_addr, 4263 (void **)&fw); 4264 if (r) { 4265 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4266 gfx_v10_0_mec_fini(adev); 4267 return r; 4268 } 4269 4270 memcpy(fw, fw_data, fw_size); 4271 4272 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4273 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4274 } 4275 4276 return 0; 4277 } 4278 4279 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4280 { 4281 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4282 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4283 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4284 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4285 } 4286 4287 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4288 uint32_t thread, uint32_t regno, 4289 uint32_t num, uint32_t *out) 4290 { 4291 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4292 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4293 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4294 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4295 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4296 while (num--) 4297 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4298 } 4299 4300 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4301 { 4302 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4303 * field when performing a select_se_sh so it should be 4304 * zero here */ 4305 WARN_ON(simd != 0); 4306 4307 /* type 2 wave data */ 4308 dst[(*no_fields)++] = 2; 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4319 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4320 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4321 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4322 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4323 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4324 } 4325 4326 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4327 uint32_t wave, uint32_t start, 4328 uint32_t size, uint32_t *dst) 4329 { 4330 WARN_ON(simd != 0); 4331 4332 wave_read_regs( 4333 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4334 dst); 4335 } 4336 4337 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4338 uint32_t wave, uint32_t thread, 4339 uint32_t start, uint32_t size, 4340 uint32_t *dst) 4341 { 4342 wave_read_regs( 4343 adev, wave, thread, 4344 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4345 } 4346 4347 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4348 u32 me, u32 pipe, u32 q, u32 vm) 4349 { 4350 nv_grbm_select(adev, me, pipe, q, vm); 4351 } 4352 4353 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4354 bool enable) 4355 { 4356 uint32_t data, def; 4357 4358 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4359 4360 if (enable) 4361 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4362 else 4363 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4364 4365 if (data != def) 4366 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4367 } 4368 4369 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4370 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4371 .select_se_sh = &gfx_v10_0_select_se_sh, 4372 .read_wave_data = &gfx_v10_0_read_wave_data, 4373 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4374 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4375 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4376 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4377 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4378 }; 4379 4380 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4381 { 4382 u32 gb_addr_config; 4383 4384 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4385 4386 switch (adev->asic_type) { 4387 case CHIP_NAVI10: 4388 case CHIP_NAVI14: 4389 case CHIP_NAVI12: 4390 adev->gfx.config.max_hw_contexts = 8; 4391 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4392 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4393 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4394 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4395 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4396 break; 4397 case CHIP_SIENNA_CICHLID: 4398 case CHIP_NAVY_FLOUNDER: 4399 case CHIP_VANGOGH: 4400 case CHIP_DIMGREY_CAVEFISH: 4401 adev->gfx.config.max_hw_contexts = 8; 4402 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4403 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4404 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4405 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4406 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4407 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4408 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4409 break; 4410 default: 4411 BUG(); 4412 break; 4413 } 4414 4415 adev->gfx.config.gb_addr_config = gb_addr_config; 4416 4417 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4418 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4419 GB_ADDR_CONFIG, NUM_PIPES); 4420 4421 adev->gfx.config.max_tile_pipes = 4422 adev->gfx.config.gb_addr_config_fields.num_pipes; 4423 4424 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4425 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4426 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4427 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4428 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4429 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4430 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4432 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4433 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4434 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4435 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4436 } 4437 4438 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4439 int me, int pipe, int queue) 4440 { 4441 int r; 4442 struct amdgpu_ring *ring; 4443 unsigned int irq_type; 4444 4445 ring = &adev->gfx.gfx_ring[ring_id]; 4446 4447 ring->me = me; 4448 ring->pipe = pipe; 4449 ring->queue = queue; 4450 4451 ring->ring_obj = NULL; 4452 ring->use_doorbell = true; 4453 4454 if (!ring_id) 4455 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4456 else 4457 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4458 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4459 4460 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4461 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4462 AMDGPU_RING_PRIO_DEFAULT, NULL); 4463 if (r) 4464 return r; 4465 return 0; 4466 } 4467 4468 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4469 int mec, int pipe, int queue) 4470 { 4471 int r; 4472 unsigned irq_type; 4473 struct amdgpu_ring *ring; 4474 unsigned int hw_prio; 4475 4476 ring = &adev->gfx.compute_ring[ring_id]; 4477 4478 /* mec0 is me1 */ 4479 ring->me = mec + 1; 4480 ring->pipe = pipe; 4481 ring->queue = queue; 4482 4483 ring->ring_obj = NULL; 4484 ring->use_doorbell = true; 4485 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4486 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4487 + (ring_id * GFX10_MEC_HPD_SIZE); 4488 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4489 4490 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4491 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4492 + ring->pipe; 4493 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4494 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4495 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4496 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4497 hw_prio, NULL); 4498 if (r) 4499 return r; 4500 4501 return 0; 4502 } 4503 4504 static int gfx_v10_0_sw_init(void *handle) 4505 { 4506 int i, j, k, r, ring_id = 0; 4507 struct amdgpu_kiq *kiq; 4508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4509 4510 switch (adev->asic_type) { 4511 case CHIP_NAVI10: 4512 case CHIP_NAVI14: 4513 case CHIP_NAVI12: 4514 adev->gfx.me.num_me = 1; 4515 adev->gfx.me.num_pipe_per_me = 1; 4516 adev->gfx.me.num_queue_per_pipe = 1; 4517 adev->gfx.mec.num_mec = 2; 4518 adev->gfx.mec.num_pipe_per_mec = 4; 4519 adev->gfx.mec.num_queue_per_pipe = 8; 4520 break; 4521 case CHIP_SIENNA_CICHLID: 4522 case CHIP_NAVY_FLOUNDER: 4523 case CHIP_VANGOGH: 4524 case CHIP_DIMGREY_CAVEFISH: 4525 adev->gfx.me.num_me = 1; 4526 adev->gfx.me.num_pipe_per_me = 1; 4527 adev->gfx.me.num_queue_per_pipe = 1; 4528 adev->gfx.mec.num_mec = 2; 4529 adev->gfx.mec.num_pipe_per_mec = 4; 4530 adev->gfx.mec.num_queue_per_pipe = 4; 4531 break; 4532 default: 4533 adev->gfx.me.num_me = 1; 4534 adev->gfx.me.num_pipe_per_me = 1; 4535 adev->gfx.me.num_queue_per_pipe = 1; 4536 adev->gfx.mec.num_mec = 1; 4537 adev->gfx.mec.num_pipe_per_mec = 4; 4538 adev->gfx.mec.num_queue_per_pipe = 8; 4539 break; 4540 } 4541 4542 /* KIQ event */ 4543 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4544 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4545 &adev->gfx.kiq.irq); 4546 if (r) 4547 return r; 4548 4549 /* EOP Event */ 4550 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4551 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4552 &adev->gfx.eop_irq); 4553 if (r) 4554 return r; 4555 4556 /* Privileged reg */ 4557 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4558 &adev->gfx.priv_reg_irq); 4559 if (r) 4560 return r; 4561 4562 /* Privileged inst */ 4563 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4564 &adev->gfx.priv_inst_irq); 4565 if (r) 4566 return r; 4567 4568 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4569 4570 gfx_v10_0_scratch_init(adev); 4571 4572 r = gfx_v10_0_me_init(adev); 4573 if (r) 4574 return r; 4575 4576 r = gfx_v10_0_rlc_init(adev); 4577 if (r) { 4578 DRM_ERROR("Failed to init rlc BOs!\n"); 4579 return r; 4580 } 4581 4582 r = gfx_v10_0_mec_init(adev); 4583 if (r) { 4584 DRM_ERROR("Failed to init MEC BOs!\n"); 4585 return r; 4586 } 4587 4588 /* set up the gfx ring */ 4589 for (i = 0; i < adev->gfx.me.num_me; i++) { 4590 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4591 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4592 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4593 continue; 4594 4595 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4596 i, k, j); 4597 if (r) 4598 return r; 4599 ring_id++; 4600 } 4601 } 4602 } 4603 4604 ring_id = 0; 4605 /* set up the compute queues - allocate horizontally across pipes */ 4606 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4607 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4608 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4609 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4610 j)) 4611 continue; 4612 4613 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4614 i, k, j); 4615 if (r) 4616 return r; 4617 4618 ring_id++; 4619 } 4620 } 4621 } 4622 4623 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4624 if (r) { 4625 DRM_ERROR("Failed to init KIQ BOs!\n"); 4626 return r; 4627 } 4628 4629 kiq = &adev->gfx.kiq; 4630 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4631 if (r) 4632 return r; 4633 4634 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4635 if (r) 4636 return r; 4637 4638 /* allocate visible FB for rlc auto-loading fw */ 4639 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4640 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4641 if (r) 4642 return r; 4643 } 4644 4645 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4646 4647 gfx_v10_0_gpu_early_init(adev); 4648 4649 return 0; 4650 } 4651 4652 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4653 { 4654 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4655 &adev->gfx.pfp.pfp_fw_gpu_addr, 4656 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4657 } 4658 4659 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4660 { 4661 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4662 &adev->gfx.ce.ce_fw_gpu_addr, 4663 (void **)&adev->gfx.ce.ce_fw_ptr); 4664 } 4665 4666 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4667 { 4668 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4669 &adev->gfx.me.me_fw_gpu_addr, 4670 (void **)&adev->gfx.me.me_fw_ptr); 4671 } 4672 4673 static int gfx_v10_0_sw_fini(void *handle) 4674 { 4675 int i; 4676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4677 4678 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4679 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4680 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4681 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4682 4683 amdgpu_gfx_mqd_sw_fini(adev); 4684 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4685 amdgpu_gfx_kiq_fini(adev); 4686 4687 gfx_v10_0_pfp_fini(adev); 4688 gfx_v10_0_ce_fini(adev); 4689 gfx_v10_0_me_fini(adev); 4690 gfx_v10_0_rlc_fini(adev); 4691 gfx_v10_0_mec_fini(adev); 4692 4693 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4694 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4695 4696 gfx_v10_0_free_microcode(adev); 4697 4698 return 0; 4699 } 4700 4701 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4702 u32 sh_num, u32 instance) 4703 { 4704 u32 data; 4705 4706 if (instance == 0xffffffff) 4707 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4708 INSTANCE_BROADCAST_WRITES, 1); 4709 else 4710 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4711 instance); 4712 4713 if (se_num == 0xffffffff) 4714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4715 1); 4716 else 4717 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4718 4719 if (sh_num == 0xffffffff) 4720 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4721 1); 4722 else 4723 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4724 4725 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4726 } 4727 4728 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4729 { 4730 u32 data, mask; 4731 4732 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4733 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4734 4735 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4736 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4737 4738 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4739 adev->gfx.config.max_sh_per_se); 4740 4741 return (~data) & mask; 4742 } 4743 4744 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4745 { 4746 int i, j; 4747 u32 data; 4748 u32 active_rbs = 0; 4749 u32 bitmap; 4750 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4751 adev->gfx.config.max_sh_per_se; 4752 4753 mutex_lock(&adev->grbm_idx_mutex); 4754 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4755 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4756 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4757 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4758 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4759 continue; 4760 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4761 data = gfx_v10_0_get_rb_active_bitmap(adev); 4762 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4763 rb_bitmap_width_per_sh); 4764 } 4765 } 4766 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4767 mutex_unlock(&adev->grbm_idx_mutex); 4768 4769 adev->gfx.config.backend_enable_mask = active_rbs; 4770 adev->gfx.config.num_rbs = hweight32(active_rbs); 4771 } 4772 4773 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4774 { 4775 uint32_t num_sc; 4776 uint32_t enabled_rb_per_sh; 4777 uint32_t active_rb_bitmap; 4778 uint32_t num_rb_per_sc; 4779 uint32_t num_packer_per_sc; 4780 uint32_t pa_sc_tile_steering_override; 4781 4782 /* for ASICs that integrates GFX v10.3 4783 * pa_sc_tile_steering_override should be set to 0 */ 4784 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4785 return 0; 4786 4787 /* init num_sc */ 4788 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4789 adev->gfx.config.num_sc_per_sh; 4790 /* init num_rb_per_sc */ 4791 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4792 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4793 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4794 /* init num_packer_per_sc */ 4795 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4796 4797 pa_sc_tile_steering_override = 0; 4798 pa_sc_tile_steering_override |= 4799 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4800 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4801 pa_sc_tile_steering_override |= 4802 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4803 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4804 pa_sc_tile_steering_override |= 4805 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4806 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4807 4808 return pa_sc_tile_steering_override; 4809 } 4810 4811 #define DEFAULT_SH_MEM_BASES (0x6000) 4812 4813 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4814 { 4815 int i; 4816 uint32_t sh_mem_bases; 4817 4818 /* 4819 * Configure apertures: 4820 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4821 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4822 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4823 */ 4824 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4825 4826 mutex_lock(&adev->srbm_mutex); 4827 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4828 nv_grbm_select(adev, 0, 0, 0, i); 4829 /* CP and shaders */ 4830 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4831 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4832 } 4833 nv_grbm_select(adev, 0, 0, 0, 0); 4834 mutex_unlock(&adev->srbm_mutex); 4835 4836 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4837 acccess. These should be enabled by FW for target VMIDs. */ 4838 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4839 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4840 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4841 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4842 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4843 } 4844 } 4845 4846 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4847 { 4848 int vmid; 4849 4850 /* 4851 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4852 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4853 * the driver can enable them for graphics. VMID0 should maintain 4854 * access so that HWS firmware can save/restore entries. 4855 */ 4856 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4857 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4858 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4859 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4860 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4861 } 4862 } 4863 4864 4865 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4866 { 4867 int i, j, k; 4868 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4869 u32 tmp, wgp_active_bitmap = 0; 4870 u32 gcrd_targets_disable_tcp = 0; 4871 u32 utcl_invreq_disable = 0; 4872 /* 4873 * GCRD_TARGETS_DISABLE field contains 4874 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4875 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4876 */ 4877 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4878 2 * max_wgp_per_sh + /* TCP */ 4879 max_wgp_per_sh + /* SQC */ 4880 4); /* GL1C */ 4881 /* 4882 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4883 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4884 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4885 */ 4886 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4887 2 * max_wgp_per_sh + /* TCP */ 4888 2 * max_wgp_per_sh + /* SQC */ 4889 4 + /* RMI */ 4890 1); /* SQG */ 4891 4892 if (adev->asic_type == CHIP_NAVI10 || 4893 adev->asic_type == CHIP_NAVI14 || 4894 adev->asic_type == CHIP_NAVI12) { 4895 mutex_lock(&adev->grbm_idx_mutex); 4896 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4897 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4898 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4899 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4900 /* 4901 * Set corresponding TCP bits for the inactive WGPs in 4902 * GCRD_SA_TARGETS_DISABLE 4903 */ 4904 gcrd_targets_disable_tcp = 0; 4905 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4906 utcl_invreq_disable = 0; 4907 4908 for (k = 0; k < max_wgp_per_sh; k++) { 4909 if (!(wgp_active_bitmap & (1 << k))) { 4910 gcrd_targets_disable_tcp |= 3 << (2 * k); 4911 utcl_invreq_disable |= (3 << (2 * k)) | 4912 (3 << (2 * (max_wgp_per_sh + k))); 4913 } 4914 } 4915 4916 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4917 /* only override TCP & SQC bits */ 4918 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4919 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4920 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4921 4922 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4923 /* only override TCP bits */ 4924 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4925 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4926 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4927 } 4928 } 4929 4930 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4931 mutex_unlock(&adev->grbm_idx_mutex); 4932 } 4933 } 4934 4935 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4936 { 4937 /* TCCs are global (not instanced). */ 4938 uint32_t tcc_disable; 4939 4940 if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 4941 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4942 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4943 } else { 4944 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4945 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4946 } 4947 4948 adev->gfx.config.tcc_disabled_mask = 4949 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4950 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4951 } 4952 4953 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4954 { 4955 u32 tmp; 4956 int i; 4957 4958 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4959 4960 gfx_v10_0_setup_rb(adev); 4961 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4962 gfx_v10_0_get_tcc_info(adev); 4963 adev->gfx.config.pa_sc_tile_steering_override = 4964 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4965 4966 /* XXX SH_MEM regs */ 4967 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4968 mutex_lock(&adev->srbm_mutex); 4969 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4970 nv_grbm_select(adev, 0, 0, 0, i); 4971 /* CP and shaders */ 4972 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4973 if (i != 0) { 4974 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4975 (adev->gmc.private_aperture_start >> 48)); 4976 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4977 (adev->gmc.shared_aperture_start >> 48)); 4978 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4979 } 4980 } 4981 nv_grbm_select(adev, 0, 0, 0, 0); 4982 4983 mutex_unlock(&adev->srbm_mutex); 4984 4985 gfx_v10_0_init_compute_vmid(adev); 4986 gfx_v10_0_init_gds_vmid(adev); 4987 4988 } 4989 4990 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4991 bool enable) 4992 { 4993 u32 tmp; 4994 4995 if (amdgpu_sriov_vf(adev)) 4996 return; 4997 4998 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4999 5000 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5001 enable ? 1 : 0); 5002 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5003 enable ? 1 : 0); 5004 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5005 enable ? 1 : 0); 5006 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5007 enable ? 1 : 0); 5008 5009 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5010 } 5011 5012 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5013 { 5014 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5015 5016 /* csib */ 5017 if (adev->asic_type == CHIP_NAVI12) { 5018 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5019 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5020 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5021 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5022 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5023 } else { 5024 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5025 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5026 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5027 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5028 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5029 } 5030 return 0; 5031 } 5032 5033 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5034 { 5035 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5036 5037 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5038 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5039 } 5040 5041 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5042 { 5043 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5044 udelay(50); 5045 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5046 udelay(50); 5047 } 5048 5049 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5050 bool enable) 5051 { 5052 uint32_t rlc_pg_cntl; 5053 5054 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5055 5056 if (!enable) { 5057 /* RLC_PG_CNTL[23] = 0 (default) 5058 * RLC will wait for handshake acks with SMU 5059 * GFXOFF will be enabled 5060 * RLC_PG_CNTL[23] = 1 5061 * RLC will not issue any message to SMU 5062 * hence no handshake between SMU & RLC 5063 * GFXOFF will be disabled 5064 */ 5065 rlc_pg_cntl |= 0x800000; 5066 } else 5067 rlc_pg_cntl &= ~0x800000; 5068 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5069 } 5070 5071 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5072 { 5073 /* TODO: enable rlc & smu handshake until smu 5074 * and gfxoff feature works as expected */ 5075 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5076 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5077 5078 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5079 udelay(50); 5080 } 5081 5082 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5083 { 5084 uint32_t tmp; 5085 5086 /* enable Save Restore Machine */ 5087 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5088 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5089 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5090 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5091 } 5092 5093 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5094 { 5095 const struct rlc_firmware_header_v2_0 *hdr; 5096 const __le32 *fw_data; 5097 unsigned i, fw_size; 5098 5099 if (!adev->gfx.rlc_fw) 5100 return -EINVAL; 5101 5102 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5103 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5104 5105 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5106 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5107 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5108 5109 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5110 RLCG_UCODE_LOADING_START_ADDRESS); 5111 5112 for (i = 0; i < fw_size; i++) 5113 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5114 le32_to_cpup(fw_data++)); 5115 5116 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5117 5118 return 0; 5119 } 5120 5121 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5122 { 5123 int r; 5124 5125 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5126 5127 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5128 if (r) 5129 return r; 5130 5131 gfx_v10_0_init_csb(adev); 5132 5133 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5134 gfx_v10_0_rlc_enable_srm(adev); 5135 } else { 5136 if (amdgpu_sriov_vf(adev)) { 5137 gfx_v10_0_init_csb(adev); 5138 return 0; 5139 } 5140 5141 adev->gfx.rlc.funcs->stop(adev); 5142 5143 /* disable CG */ 5144 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5145 5146 /* disable PG */ 5147 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5148 5149 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5150 /* legacy rlc firmware loading */ 5151 r = gfx_v10_0_rlc_load_microcode(adev); 5152 if (r) 5153 return r; 5154 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5155 /* rlc backdoor autoload firmware */ 5156 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5157 if (r) 5158 return r; 5159 } 5160 5161 gfx_v10_0_init_csb(adev); 5162 5163 adev->gfx.rlc.funcs->start(adev); 5164 5165 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5166 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5167 if (r) 5168 return r; 5169 } 5170 } 5171 return 0; 5172 } 5173 5174 static struct { 5175 FIRMWARE_ID id; 5176 unsigned int offset; 5177 unsigned int size; 5178 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5179 5180 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5181 { 5182 int ret; 5183 RLC_TABLE_OF_CONTENT *rlc_toc; 5184 5185 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5186 AMDGPU_GEM_DOMAIN_GTT, 5187 &adev->gfx.rlc.rlc_toc_bo, 5188 &adev->gfx.rlc.rlc_toc_gpu_addr, 5189 (void **)&adev->gfx.rlc.rlc_toc_buf); 5190 if (ret) { 5191 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5192 return ret; 5193 } 5194 5195 /* Copy toc from psp sos fw to rlc toc buffer */ 5196 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5197 5198 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5199 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5200 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5201 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5202 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5203 /* Offset needs 4KB alignment */ 5204 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5205 } 5206 5207 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5208 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5209 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5210 5211 rlc_toc++; 5212 } 5213 5214 return 0; 5215 } 5216 5217 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5218 { 5219 uint32_t total_size = 0; 5220 FIRMWARE_ID id; 5221 int ret; 5222 5223 ret = gfx_v10_0_parse_rlc_toc(adev); 5224 if (ret) { 5225 dev_err(adev->dev, "failed to parse rlc toc\n"); 5226 return 0; 5227 } 5228 5229 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5230 total_size += rlc_autoload_info[id].size; 5231 5232 /* In case the offset in rlc toc ucode is aligned */ 5233 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5234 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5235 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5236 5237 return total_size; 5238 } 5239 5240 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5241 { 5242 int r; 5243 uint32_t total_size; 5244 5245 total_size = gfx_v10_0_calc_toc_total_size(adev); 5246 5247 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5248 AMDGPU_GEM_DOMAIN_GTT, 5249 &adev->gfx.rlc.rlc_autoload_bo, 5250 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5251 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5252 if (r) { 5253 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5254 return r; 5255 } 5256 5257 return 0; 5258 } 5259 5260 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5261 { 5262 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5263 &adev->gfx.rlc.rlc_toc_gpu_addr, 5264 (void **)&adev->gfx.rlc.rlc_toc_buf); 5265 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5266 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5267 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5268 } 5269 5270 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5271 FIRMWARE_ID id, 5272 const void *fw_data, 5273 uint32_t fw_size) 5274 { 5275 uint32_t toc_offset; 5276 uint32_t toc_fw_size; 5277 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5278 5279 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5280 return; 5281 5282 toc_offset = rlc_autoload_info[id].offset; 5283 toc_fw_size = rlc_autoload_info[id].size; 5284 5285 if (fw_size == 0) 5286 fw_size = toc_fw_size; 5287 5288 if (fw_size > toc_fw_size) 5289 fw_size = toc_fw_size; 5290 5291 memcpy(ptr + toc_offset, fw_data, fw_size); 5292 5293 if (fw_size < toc_fw_size) 5294 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5295 } 5296 5297 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5298 { 5299 void *data; 5300 uint32_t size; 5301 5302 data = adev->gfx.rlc.rlc_toc_buf; 5303 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5304 5305 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5306 FIRMWARE_ID_RLC_TOC, 5307 data, size); 5308 } 5309 5310 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5311 { 5312 const __le32 *fw_data; 5313 uint32_t fw_size; 5314 const struct gfx_firmware_header_v1_0 *cp_hdr; 5315 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5316 5317 /* pfp ucode */ 5318 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5319 adev->gfx.pfp_fw->data; 5320 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5321 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5322 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5323 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5324 FIRMWARE_ID_CP_PFP, 5325 fw_data, fw_size); 5326 5327 /* ce ucode */ 5328 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5329 adev->gfx.ce_fw->data; 5330 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5331 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5332 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5333 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5334 FIRMWARE_ID_CP_CE, 5335 fw_data, fw_size); 5336 5337 /* me ucode */ 5338 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5339 adev->gfx.me_fw->data; 5340 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5341 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5342 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5343 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5344 FIRMWARE_ID_CP_ME, 5345 fw_data, fw_size); 5346 5347 /* rlc ucode */ 5348 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5349 adev->gfx.rlc_fw->data; 5350 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5351 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5352 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5353 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5354 FIRMWARE_ID_RLC_G_UCODE, 5355 fw_data, fw_size); 5356 5357 /* mec1 ucode */ 5358 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5359 adev->gfx.mec_fw->data; 5360 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5361 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5362 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5363 cp_hdr->jt_size * 4; 5364 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5365 FIRMWARE_ID_CP_MEC, 5366 fw_data, fw_size); 5367 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5368 } 5369 5370 /* Temporarily put sdma part here */ 5371 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5372 { 5373 const __le32 *fw_data; 5374 uint32_t fw_size; 5375 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5376 int i; 5377 5378 for (i = 0; i < adev->sdma.num_instances; i++) { 5379 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5380 adev->sdma.instance[i].fw->data; 5381 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5382 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5383 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5384 5385 if (i == 0) { 5386 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5387 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5388 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5389 FIRMWARE_ID_SDMA0_JT, 5390 (uint32_t *)fw_data + 5391 sdma_hdr->jt_offset, 5392 sdma_hdr->jt_size * 4); 5393 } else if (i == 1) { 5394 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5395 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5396 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5397 FIRMWARE_ID_SDMA1_JT, 5398 (uint32_t *)fw_data + 5399 sdma_hdr->jt_offset, 5400 sdma_hdr->jt_size * 4); 5401 } 5402 } 5403 } 5404 5405 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5406 { 5407 uint32_t rlc_g_offset, rlc_g_size, tmp; 5408 uint64_t gpu_addr; 5409 5410 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5411 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5412 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5413 5414 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5415 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5416 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5417 5418 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5419 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5420 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5421 5422 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5423 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5424 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5425 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5426 return -EINVAL; 5427 } 5428 5429 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5430 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5431 DRM_ERROR("RLC ROM should halt itself\n"); 5432 return -EINVAL; 5433 } 5434 5435 return 0; 5436 } 5437 5438 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5439 { 5440 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5441 uint32_t tmp; 5442 int i; 5443 uint64_t addr; 5444 5445 /* Trigger an invalidation of the L1 instruction caches */ 5446 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5447 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5448 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5449 5450 /* Wait for invalidation complete */ 5451 for (i = 0; i < usec_timeout; i++) { 5452 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5453 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5454 INVALIDATE_CACHE_COMPLETE)) 5455 break; 5456 udelay(1); 5457 } 5458 5459 if (i >= usec_timeout) { 5460 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5461 return -EINVAL; 5462 } 5463 5464 /* Program me ucode address into intruction cache address register */ 5465 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5466 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5467 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5468 lower_32_bits(addr) & 0xFFFFF000); 5469 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5470 upper_32_bits(addr)); 5471 5472 return 0; 5473 } 5474 5475 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5476 { 5477 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5478 uint32_t tmp; 5479 int i; 5480 uint64_t addr; 5481 5482 /* Trigger an invalidation of the L1 instruction caches */ 5483 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5484 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5485 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5486 5487 /* Wait for invalidation complete */ 5488 for (i = 0; i < usec_timeout; i++) { 5489 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5490 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5491 INVALIDATE_CACHE_COMPLETE)) 5492 break; 5493 udelay(1); 5494 } 5495 5496 if (i >= usec_timeout) { 5497 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5498 return -EINVAL; 5499 } 5500 5501 /* Program ce ucode address into intruction cache address register */ 5502 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5503 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5504 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5505 lower_32_bits(addr) & 0xFFFFF000); 5506 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5507 upper_32_bits(addr)); 5508 5509 return 0; 5510 } 5511 5512 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5513 { 5514 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5515 uint32_t tmp; 5516 int i; 5517 uint64_t addr; 5518 5519 /* Trigger an invalidation of the L1 instruction caches */ 5520 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5521 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5522 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5523 5524 /* Wait for invalidation complete */ 5525 for (i = 0; i < usec_timeout; i++) { 5526 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5527 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5528 INVALIDATE_CACHE_COMPLETE)) 5529 break; 5530 udelay(1); 5531 } 5532 5533 if (i >= usec_timeout) { 5534 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5535 return -EINVAL; 5536 } 5537 5538 /* Program pfp ucode address into intruction cache address register */ 5539 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5540 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5541 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5542 lower_32_bits(addr) & 0xFFFFF000); 5543 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5544 upper_32_bits(addr)); 5545 5546 return 0; 5547 } 5548 5549 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5550 { 5551 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5552 uint32_t tmp; 5553 int i; 5554 uint64_t addr; 5555 5556 /* Trigger an invalidation of the L1 instruction caches */ 5557 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5558 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5559 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5560 5561 /* Wait for invalidation complete */ 5562 for (i = 0; i < usec_timeout; i++) { 5563 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5564 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5565 INVALIDATE_CACHE_COMPLETE)) 5566 break; 5567 udelay(1); 5568 } 5569 5570 if (i >= usec_timeout) { 5571 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5572 return -EINVAL; 5573 } 5574 5575 /* Program mec1 ucode address into intruction cache address register */ 5576 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5577 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5578 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5579 lower_32_bits(addr) & 0xFFFFF000); 5580 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5581 upper_32_bits(addr)); 5582 5583 return 0; 5584 } 5585 5586 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5587 { 5588 uint32_t cp_status; 5589 uint32_t bootload_status; 5590 int i, r; 5591 5592 for (i = 0; i < adev->usec_timeout; i++) { 5593 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5594 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5595 if ((cp_status == 0) && 5596 (REG_GET_FIELD(bootload_status, 5597 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5598 break; 5599 } 5600 udelay(1); 5601 } 5602 5603 if (i >= adev->usec_timeout) { 5604 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5605 return -ETIMEDOUT; 5606 } 5607 5608 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5609 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5610 if (r) 5611 return r; 5612 5613 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5614 if (r) 5615 return r; 5616 5617 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5618 if (r) 5619 return r; 5620 5621 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5622 if (r) 5623 return r; 5624 } 5625 5626 return 0; 5627 } 5628 5629 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5630 { 5631 int i; 5632 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5633 5634 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5635 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5636 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5637 5638 if (adev->asic_type == CHIP_NAVI12) { 5639 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5640 } else { 5641 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5642 } 5643 5644 for (i = 0; i < adev->usec_timeout; i++) { 5645 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5646 break; 5647 udelay(1); 5648 } 5649 5650 if (i >= adev->usec_timeout) 5651 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5652 5653 return 0; 5654 } 5655 5656 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5657 { 5658 int r; 5659 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5660 const __le32 *fw_data; 5661 unsigned i, fw_size; 5662 uint32_t tmp; 5663 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5664 5665 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5666 adev->gfx.pfp_fw->data; 5667 5668 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5669 5670 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5671 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5672 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5673 5674 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5675 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5676 &adev->gfx.pfp.pfp_fw_obj, 5677 &adev->gfx.pfp.pfp_fw_gpu_addr, 5678 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5679 if (r) { 5680 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5681 gfx_v10_0_pfp_fini(adev); 5682 return r; 5683 } 5684 5685 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5686 5687 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5688 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5689 5690 /* Trigger an invalidation of the L1 instruction caches */ 5691 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5692 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5693 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5694 5695 /* Wait for invalidation complete */ 5696 for (i = 0; i < usec_timeout; i++) { 5697 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5698 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5699 INVALIDATE_CACHE_COMPLETE)) 5700 break; 5701 udelay(1); 5702 } 5703 5704 if (i >= usec_timeout) { 5705 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5706 return -EINVAL; 5707 } 5708 5709 if (amdgpu_emu_mode == 1) 5710 adev->hdp.funcs->flush_hdp(adev, NULL); 5711 5712 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5713 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5714 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5715 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5716 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5717 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5718 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5719 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5720 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5721 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5722 5723 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5724 5725 for (i = 0; i < pfp_hdr->jt_size; i++) 5726 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5727 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5728 5729 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5730 5731 return 0; 5732 } 5733 5734 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5735 { 5736 int r; 5737 const struct gfx_firmware_header_v1_0 *ce_hdr; 5738 const __le32 *fw_data; 5739 unsigned i, fw_size; 5740 uint32_t tmp; 5741 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5742 5743 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5744 adev->gfx.ce_fw->data; 5745 5746 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5747 5748 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5749 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5750 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5751 5752 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5753 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5754 &adev->gfx.ce.ce_fw_obj, 5755 &adev->gfx.ce.ce_fw_gpu_addr, 5756 (void **)&adev->gfx.ce.ce_fw_ptr); 5757 if (r) { 5758 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5759 gfx_v10_0_ce_fini(adev); 5760 return r; 5761 } 5762 5763 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5764 5765 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5766 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5767 5768 /* Trigger an invalidation of the L1 instruction caches */ 5769 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5770 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5771 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5772 5773 /* Wait for invalidation complete */ 5774 for (i = 0; i < usec_timeout; i++) { 5775 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5776 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5777 INVALIDATE_CACHE_COMPLETE)) 5778 break; 5779 udelay(1); 5780 } 5781 5782 if (i >= usec_timeout) { 5783 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5784 return -EINVAL; 5785 } 5786 5787 if (amdgpu_emu_mode == 1) 5788 adev->hdp.funcs->flush_hdp(adev, NULL); 5789 5790 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5791 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5792 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5793 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5794 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5795 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5796 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5797 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5798 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5799 5800 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5801 5802 for (i = 0; i < ce_hdr->jt_size; i++) 5803 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5804 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5805 5806 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5807 5808 return 0; 5809 } 5810 5811 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5812 { 5813 int r; 5814 const struct gfx_firmware_header_v1_0 *me_hdr; 5815 const __le32 *fw_data; 5816 unsigned i, fw_size; 5817 uint32_t tmp; 5818 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5819 5820 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5821 adev->gfx.me_fw->data; 5822 5823 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5824 5825 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5826 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5827 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5828 5829 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5830 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5831 &adev->gfx.me.me_fw_obj, 5832 &adev->gfx.me.me_fw_gpu_addr, 5833 (void **)&adev->gfx.me.me_fw_ptr); 5834 if (r) { 5835 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5836 gfx_v10_0_me_fini(adev); 5837 return r; 5838 } 5839 5840 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5841 5842 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5843 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5844 5845 /* Trigger an invalidation of the L1 instruction caches */ 5846 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5847 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5848 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5849 5850 /* Wait for invalidation complete */ 5851 for (i = 0; i < usec_timeout; i++) { 5852 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5853 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5854 INVALIDATE_CACHE_COMPLETE)) 5855 break; 5856 udelay(1); 5857 } 5858 5859 if (i >= usec_timeout) { 5860 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5861 return -EINVAL; 5862 } 5863 5864 if (amdgpu_emu_mode == 1) 5865 adev->hdp.funcs->flush_hdp(adev, NULL); 5866 5867 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5868 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5869 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5870 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5871 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5872 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5873 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5874 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5875 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5876 5877 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5878 5879 for (i = 0; i < me_hdr->jt_size; i++) 5880 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5881 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5882 5883 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5884 5885 return 0; 5886 } 5887 5888 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5889 { 5890 int r; 5891 5892 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5893 return -EINVAL; 5894 5895 gfx_v10_0_cp_gfx_enable(adev, false); 5896 5897 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5898 if (r) { 5899 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5900 return r; 5901 } 5902 5903 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5904 if (r) { 5905 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5906 return r; 5907 } 5908 5909 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5910 if (r) { 5911 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5912 return r; 5913 } 5914 5915 return 0; 5916 } 5917 5918 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5919 { 5920 struct amdgpu_ring *ring; 5921 const struct cs_section_def *sect = NULL; 5922 const struct cs_extent_def *ext = NULL; 5923 int r, i; 5924 int ctx_reg_offset; 5925 5926 /* init the CP */ 5927 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5928 adev->gfx.config.max_hw_contexts - 1); 5929 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5930 5931 gfx_v10_0_cp_gfx_enable(adev, true); 5932 5933 ring = &adev->gfx.gfx_ring[0]; 5934 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5935 if (r) { 5936 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5937 return r; 5938 } 5939 5940 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5941 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5942 5943 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5944 amdgpu_ring_write(ring, 0x80000000); 5945 amdgpu_ring_write(ring, 0x80000000); 5946 5947 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5948 for (ext = sect->section; ext->extent != NULL; ++ext) { 5949 if (sect->id == SECT_CONTEXT) { 5950 amdgpu_ring_write(ring, 5951 PACKET3(PACKET3_SET_CONTEXT_REG, 5952 ext->reg_count)); 5953 amdgpu_ring_write(ring, ext->reg_index - 5954 PACKET3_SET_CONTEXT_REG_START); 5955 for (i = 0; i < ext->reg_count; i++) 5956 amdgpu_ring_write(ring, ext->extent[i]); 5957 } 5958 } 5959 } 5960 5961 ctx_reg_offset = 5962 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5963 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5964 amdgpu_ring_write(ring, ctx_reg_offset); 5965 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5966 5967 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5968 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5969 5970 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5971 amdgpu_ring_write(ring, 0); 5972 5973 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5974 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5975 amdgpu_ring_write(ring, 0x8000); 5976 amdgpu_ring_write(ring, 0x8000); 5977 5978 amdgpu_ring_commit(ring); 5979 5980 /* submit cs packet to copy state 0 to next available state */ 5981 if (adev->gfx.num_gfx_rings > 1) { 5982 /* maximum supported gfx ring is 2 */ 5983 ring = &adev->gfx.gfx_ring[1]; 5984 r = amdgpu_ring_alloc(ring, 2); 5985 if (r) { 5986 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5987 return r; 5988 } 5989 5990 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5991 amdgpu_ring_write(ring, 0); 5992 5993 amdgpu_ring_commit(ring); 5994 } 5995 return 0; 5996 } 5997 5998 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5999 CP_PIPE_ID pipe) 6000 { 6001 u32 tmp; 6002 6003 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6004 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6005 6006 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6007 } 6008 6009 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6010 struct amdgpu_ring *ring) 6011 { 6012 u32 tmp; 6013 6014 if (!amdgpu_async_gfx_ring) { 6015 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6016 if (ring->use_doorbell) { 6017 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6018 DOORBELL_OFFSET, ring->doorbell_index); 6019 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6020 DOORBELL_EN, 1); 6021 } else { 6022 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6023 DOORBELL_EN, 0); 6024 } 6025 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6026 } 6027 switch (adev->asic_type) { 6028 case CHIP_SIENNA_CICHLID: 6029 case CHIP_NAVY_FLOUNDER: 6030 case CHIP_VANGOGH: 6031 case CHIP_DIMGREY_CAVEFISH: 6032 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6033 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6034 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6035 6036 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6037 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6038 break; 6039 default: 6040 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6041 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6042 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6043 6044 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6045 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6046 break; 6047 } 6048 } 6049 6050 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6051 { 6052 struct amdgpu_ring *ring; 6053 u32 tmp; 6054 u32 rb_bufsz; 6055 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6056 u32 i; 6057 6058 /* Set the write pointer delay */ 6059 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6060 6061 /* set the RB to use vmid 0 */ 6062 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6063 6064 /* Init gfx ring 0 for pipe 0 */ 6065 mutex_lock(&adev->srbm_mutex); 6066 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6067 6068 /* Set ring buffer size */ 6069 ring = &adev->gfx.gfx_ring[0]; 6070 rb_bufsz = order_base_2(ring->ring_size / 8); 6071 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6072 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6073 #ifdef __BIG_ENDIAN 6074 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6075 #endif 6076 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6077 6078 /* Initialize the ring buffer's write pointers */ 6079 ring->wptr = 0; 6080 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6081 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6082 6083 /* set the wb address wether it's enabled or not */ 6084 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6085 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6086 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6087 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6088 6089 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6090 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6091 lower_32_bits(wptr_gpu_addr)); 6092 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6093 upper_32_bits(wptr_gpu_addr)); 6094 6095 mdelay(1); 6096 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6097 6098 rb_addr = ring->gpu_addr >> 8; 6099 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6100 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6101 6102 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6103 6104 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6105 mutex_unlock(&adev->srbm_mutex); 6106 6107 /* Init gfx ring 1 for pipe 1 */ 6108 if (adev->gfx.num_gfx_rings > 1) { 6109 mutex_lock(&adev->srbm_mutex); 6110 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6111 /* maximum supported gfx ring is 2 */ 6112 ring = &adev->gfx.gfx_ring[1]; 6113 rb_bufsz = order_base_2(ring->ring_size / 8); 6114 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6115 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6116 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6117 /* Initialize the ring buffer's write pointers */ 6118 ring->wptr = 0; 6119 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6120 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6121 /* Set the wb address wether it's enabled or not */ 6122 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6123 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6124 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6125 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6126 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6127 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6128 lower_32_bits(wptr_gpu_addr)); 6129 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6130 upper_32_bits(wptr_gpu_addr)); 6131 6132 mdelay(1); 6133 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6134 6135 rb_addr = ring->gpu_addr >> 8; 6136 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6137 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6138 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6139 6140 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6141 mutex_unlock(&adev->srbm_mutex); 6142 } 6143 /* Switch to pipe 0 */ 6144 mutex_lock(&adev->srbm_mutex); 6145 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6146 mutex_unlock(&adev->srbm_mutex); 6147 6148 /* start the ring */ 6149 gfx_v10_0_cp_gfx_start(adev); 6150 6151 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6152 ring = &adev->gfx.gfx_ring[i]; 6153 ring->sched.ready = true; 6154 } 6155 6156 return 0; 6157 } 6158 6159 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6160 { 6161 if (enable) { 6162 switch (adev->asic_type) { 6163 case CHIP_SIENNA_CICHLID: 6164 case CHIP_NAVY_FLOUNDER: 6165 case CHIP_VANGOGH: 6166 case CHIP_DIMGREY_CAVEFISH: 6167 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6168 break; 6169 default: 6170 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6171 break; 6172 } 6173 } else { 6174 switch (adev->asic_type) { 6175 case CHIP_SIENNA_CICHLID: 6176 case CHIP_NAVY_FLOUNDER: 6177 case CHIP_VANGOGH: 6178 case CHIP_DIMGREY_CAVEFISH: 6179 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6180 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6181 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6182 break; 6183 default: 6184 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6185 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6186 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6187 break; 6188 } 6189 adev->gfx.kiq.ring.sched.ready = false; 6190 } 6191 udelay(50); 6192 } 6193 6194 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6195 { 6196 const struct gfx_firmware_header_v1_0 *mec_hdr; 6197 const __le32 *fw_data; 6198 unsigned i; 6199 u32 tmp; 6200 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6201 6202 if (!adev->gfx.mec_fw) 6203 return -EINVAL; 6204 6205 gfx_v10_0_cp_compute_enable(adev, false); 6206 6207 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6208 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6209 6210 fw_data = (const __le32 *) 6211 (adev->gfx.mec_fw->data + 6212 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6213 6214 /* Trigger an invalidation of the L1 instruction caches */ 6215 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6216 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6217 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6218 6219 /* Wait for invalidation complete */ 6220 for (i = 0; i < usec_timeout; i++) { 6221 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6222 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6223 INVALIDATE_CACHE_COMPLETE)) 6224 break; 6225 udelay(1); 6226 } 6227 6228 if (i >= usec_timeout) { 6229 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6230 return -EINVAL; 6231 } 6232 6233 if (amdgpu_emu_mode == 1) 6234 adev->hdp.funcs->flush_hdp(adev, NULL); 6235 6236 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6237 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6238 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6239 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6240 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6241 6242 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6243 0xFFFFF000); 6244 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6245 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6246 6247 /* MEC1 */ 6248 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6249 6250 for (i = 0; i < mec_hdr->jt_size; i++) 6251 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6252 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6253 6254 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6255 6256 /* 6257 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6258 * different microcode than MEC1. 6259 */ 6260 6261 return 0; 6262 } 6263 6264 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6265 { 6266 uint32_t tmp; 6267 struct amdgpu_device *adev = ring->adev; 6268 6269 /* tell RLC which is KIQ queue */ 6270 switch (adev->asic_type) { 6271 case CHIP_SIENNA_CICHLID: 6272 case CHIP_NAVY_FLOUNDER: 6273 case CHIP_VANGOGH: 6274 case CHIP_DIMGREY_CAVEFISH: 6275 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6276 tmp &= 0xffffff00; 6277 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6278 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6279 tmp |= 0x80; 6280 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6281 break; 6282 default: 6283 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6284 tmp &= 0xffffff00; 6285 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6286 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6287 tmp |= 0x80; 6288 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6289 break; 6290 } 6291 } 6292 6293 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6294 { 6295 struct amdgpu_device *adev = ring->adev; 6296 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6297 uint64_t hqd_gpu_addr, wb_gpu_addr; 6298 uint32_t tmp; 6299 uint32_t rb_bufsz; 6300 6301 /* set up gfx hqd wptr */ 6302 mqd->cp_gfx_hqd_wptr = 0; 6303 mqd->cp_gfx_hqd_wptr_hi = 0; 6304 6305 /* set the pointer to the MQD */ 6306 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6307 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6308 6309 /* set up mqd control */ 6310 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6311 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6312 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6313 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6314 mqd->cp_gfx_mqd_control = tmp; 6315 6316 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6317 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6318 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6319 mqd->cp_gfx_hqd_vmid = 0; 6320 6321 /* set up default queue priority level 6322 * 0x0 = low priority, 0x1 = high priority */ 6323 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6324 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6325 mqd->cp_gfx_hqd_queue_priority = tmp; 6326 6327 /* set up time quantum */ 6328 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6329 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6330 mqd->cp_gfx_hqd_quantum = tmp; 6331 6332 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6333 hqd_gpu_addr = ring->gpu_addr >> 8; 6334 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6335 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6336 6337 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6338 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6339 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6340 mqd->cp_gfx_hqd_rptr_addr_hi = 6341 upper_32_bits(wb_gpu_addr) & 0xffff; 6342 6343 /* set up rb_wptr_poll addr */ 6344 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6345 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6346 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6347 6348 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6349 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6350 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6351 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6352 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6353 #ifdef __BIG_ENDIAN 6354 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6355 #endif 6356 mqd->cp_gfx_hqd_cntl = tmp; 6357 6358 /* set up cp_doorbell_control */ 6359 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6360 if (ring->use_doorbell) { 6361 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6362 DOORBELL_OFFSET, ring->doorbell_index); 6363 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6364 DOORBELL_EN, 1); 6365 } else 6366 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6367 DOORBELL_EN, 0); 6368 mqd->cp_rb_doorbell_control = tmp; 6369 6370 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6371 *otherwise the range of the second ring will override the first ring */ 6372 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6373 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6374 6375 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6376 ring->wptr = 0; 6377 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6378 6379 /* active the queue */ 6380 mqd->cp_gfx_hqd_active = 1; 6381 6382 return 0; 6383 } 6384 6385 #ifdef BRING_UP_DEBUG 6386 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6387 { 6388 struct amdgpu_device *adev = ring->adev; 6389 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6390 6391 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6392 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6393 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6394 6395 /* set GFX_MQD_BASE */ 6396 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6397 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6398 6399 /* set GFX_MQD_CONTROL */ 6400 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6401 6402 /* set GFX_HQD_VMID to 0 */ 6403 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6404 6405 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6406 mqd->cp_gfx_hqd_queue_priority); 6407 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6408 6409 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6410 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6411 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6412 6413 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6414 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6415 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6416 6417 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6418 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6419 6420 /* set RB_WPTR_POLL_ADDR */ 6421 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6422 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6423 6424 /* set RB_DOORBELL_CONTROL */ 6425 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6426 6427 /* active the queue */ 6428 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6429 6430 return 0; 6431 } 6432 #endif 6433 6434 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6435 { 6436 struct amdgpu_device *adev = ring->adev; 6437 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6438 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6439 6440 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6441 memset((void *)mqd, 0, sizeof(*mqd)); 6442 mutex_lock(&adev->srbm_mutex); 6443 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6444 gfx_v10_0_gfx_mqd_init(ring); 6445 #ifdef BRING_UP_DEBUG 6446 gfx_v10_0_gfx_queue_init_register(ring); 6447 #endif 6448 nv_grbm_select(adev, 0, 0, 0, 0); 6449 mutex_unlock(&adev->srbm_mutex); 6450 if (adev->gfx.me.mqd_backup[mqd_idx]) 6451 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6452 } else if (amdgpu_in_reset(adev)) { 6453 /* reset mqd with the backup copy */ 6454 if (adev->gfx.me.mqd_backup[mqd_idx]) 6455 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6456 /* reset the ring */ 6457 ring->wptr = 0; 6458 adev->wb.wb[ring->wptr_offs] = 0; 6459 amdgpu_ring_clear_ring(ring); 6460 #ifdef BRING_UP_DEBUG 6461 mutex_lock(&adev->srbm_mutex); 6462 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6463 gfx_v10_0_gfx_queue_init_register(ring); 6464 nv_grbm_select(adev, 0, 0, 0, 0); 6465 mutex_unlock(&adev->srbm_mutex); 6466 #endif 6467 } else { 6468 amdgpu_ring_clear_ring(ring); 6469 } 6470 6471 return 0; 6472 } 6473 6474 #ifndef BRING_UP_DEBUG 6475 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6476 { 6477 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6478 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6479 int r, i; 6480 6481 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6482 return -EINVAL; 6483 6484 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6485 adev->gfx.num_gfx_rings); 6486 if (r) { 6487 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6488 return r; 6489 } 6490 6491 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6492 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6493 6494 return amdgpu_ring_test_helper(kiq_ring); 6495 } 6496 #endif 6497 6498 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6499 { 6500 int r, i; 6501 struct amdgpu_ring *ring; 6502 6503 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6504 ring = &adev->gfx.gfx_ring[i]; 6505 6506 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6507 if (unlikely(r != 0)) 6508 goto done; 6509 6510 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6511 if (!r) { 6512 r = gfx_v10_0_gfx_init_queue(ring); 6513 amdgpu_bo_kunmap(ring->mqd_obj); 6514 ring->mqd_ptr = NULL; 6515 } 6516 amdgpu_bo_unreserve(ring->mqd_obj); 6517 if (r) 6518 goto done; 6519 } 6520 #ifndef BRING_UP_DEBUG 6521 r = gfx_v10_0_kiq_enable_kgq(adev); 6522 if (r) 6523 goto done; 6524 #endif 6525 r = gfx_v10_0_cp_gfx_start(adev); 6526 if (r) 6527 goto done; 6528 6529 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6530 ring = &adev->gfx.gfx_ring[i]; 6531 ring->sched.ready = true; 6532 } 6533 done: 6534 return r; 6535 } 6536 6537 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6538 { 6539 struct amdgpu_device *adev = ring->adev; 6540 6541 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6542 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 6543 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6544 mqd->cp_hqd_queue_priority = 6545 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6546 } 6547 } 6548 } 6549 6550 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6551 { 6552 struct amdgpu_device *adev = ring->adev; 6553 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6554 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6555 uint32_t tmp; 6556 6557 mqd->header = 0xC0310800; 6558 mqd->compute_pipelinestat_enable = 0x00000001; 6559 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6560 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6561 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6562 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6563 mqd->compute_misc_reserved = 0x00000003; 6564 6565 eop_base_addr = ring->eop_gpu_addr >> 8; 6566 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6567 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6568 6569 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6570 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6571 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6572 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6573 6574 mqd->cp_hqd_eop_control = tmp; 6575 6576 /* enable doorbell? */ 6577 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6578 6579 if (ring->use_doorbell) { 6580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6581 DOORBELL_OFFSET, ring->doorbell_index); 6582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6583 DOORBELL_EN, 1); 6584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6585 DOORBELL_SOURCE, 0); 6586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6587 DOORBELL_HIT, 0); 6588 } else { 6589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6590 DOORBELL_EN, 0); 6591 } 6592 6593 mqd->cp_hqd_pq_doorbell_control = tmp; 6594 6595 /* disable the queue if it's active */ 6596 ring->wptr = 0; 6597 mqd->cp_hqd_dequeue_request = 0; 6598 mqd->cp_hqd_pq_rptr = 0; 6599 mqd->cp_hqd_pq_wptr_lo = 0; 6600 mqd->cp_hqd_pq_wptr_hi = 0; 6601 6602 /* set the pointer to the MQD */ 6603 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6604 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6605 6606 /* set MQD vmid to 0 */ 6607 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6608 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6609 mqd->cp_mqd_control = tmp; 6610 6611 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6612 hqd_gpu_addr = ring->gpu_addr >> 8; 6613 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6614 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6615 6616 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6617 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6618 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6619 (order_base_2(ring->ring_size / 4) - 1)); 6620 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6621 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6622 #ifdef __BIG_ENDIAN 6623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6624 #endif 6625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6626 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6628 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6629 mqd->cp_hqd_pq_control = tmp; 6630 6631 /* set the wb address whether it's enabled or not */ 6632 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6633 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6634 mqd->cp_hqd_pq_rptr_report_addr_hi = 6635 upper_32_bits(wb_gpu_addr) & 0xffff; 6636 6637 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6638 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6639 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6640 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6641 6642 tmp = 0; 6643 /* enable the doorbell if requested */ 6644 if (ring->use_doorbell) { 6645 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6646 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6647 DOORBELL_OFFSET, ring->doorbell_index); 6648 6649 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6650 DOORBELL_EN, 1); 6651 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6652 DOORBELL_SOURCE, 0); 6653 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6654 DOORBELL_HIT, 0); 6655 } 6656 6657 mqd->cp_hqd_pq_doorbell_control = tmp; 6658 6659 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6660 ring->wptr = 0; 6661 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6662 6663 /* set the vmid for the queue */ 6664 mqd->cp_hqd_vmid = 0; 6665 6666 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6667 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6668 mqd->cp_hqd_persistent_state = tmp; 6669 6670 /* set MIN_IB_AVAIL_SIZE */ 6671 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6672 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6673 mqd->cp_hqd_ib_control = tmp; 6674 6675 /* set static priority for a compute queue/ring */ 6676 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6677 6678 /* map_queues packet doesn't need activate the queue, 6679 * so only kiq need set this field. 6680 */ 6681 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6682 mqd->cp_hqd_active = 1; 6683 6684 return 0; 6685 } 6686 6687 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6688 { 6689 struct amdgpu_device *adev = ring->adev; 6690 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6691 int j; 6692 6693 /* inactivate the queue */ 6694 if (amdgpu_sriov_vf(adev)) 6695 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6696 6697 /* disable wptr polling */ 6698 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6699 6700 /* write the EOP addr */ 6701 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6702 mqd->cp_hqd_eop_base_addr_lo); 6703 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6704 mqd->cp_hqd_eop_base_addr_hi); 6705 6706 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6707 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6708 mqd->cp_hqd_eop_control); 6709 6710 /* enable doorbell? */ 6711 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6712 mqd->cp_hqd_pq_doorbell_control); 6713 6714 /* disable the queue if it's active */ 6715 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6716 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6717 for (j = 0; j < adev->usec_timeout; j++) { 6718 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6719 break; 6720 udelay(1); 6721 } 6722 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6723 mqd->cp_hqd_dequeue_request); 6724 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6725 mqd->cp_hqd_pq_rptr); 6726 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6727 mqd->cp_hqd_pq_wptr_lo); 6728 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6729 mqd->cp_hqd_pq_wptr_hi); 6730 } 6731 6732 /* set the pointer to the MQD */ 6733 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6734 mqd->cp_mqd_base_addr_lo); 6735 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6736 mqd->cp_mqd_base_addr_hi); 6737 6738 /* set MQD vmid to 0 */ 6739 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6740 mqd->cp_mqd_control); 6741 6742 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6743 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6744 mqd->cp_hqd_pq_base_lo); 6745 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6746 mqd->cp_hqd_pq_base_hi); 6747 6748 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6749 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6750 mqd->cp_hqd_pq_control); 6751 6752 /* set the wb address whether it's enabled or not */ 6753 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6754 mqd->cp_hqd_pq_rptr_report_addr_lo); 6755 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6756 mqd->cp_hqd_pq_rptr_report_addr_hi); 6757 6758 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6759 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6760 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6761 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6762 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6763 6764 /* enable the doorbell if requested */ 6765 if (ring->use_doorbell) { 6766 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6767 (adev->doorbell_index.kiq * 2) << 2); 6768 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6769 (adev->doorbell_index.userqueue_end * 2) << 2); 6770 } 6771 6772 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6773 mqd->cp_hqd_pq_doorbell_control); 6774 6775 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6776 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6777 mqd->cp_hqd_pq_wptr_lo); 6778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6779 mqd->cp_hqd_pq_wptr_hi); 6780 6781 /* set the vmid for the queue */ 6782 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6783 6784 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6785 mqd->cp_hqd_persistent_state); 6786 6787 /* activate the queue */ 6788 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6789 mqd->cp_hqd_active); 6790 6791 if (ring->use_doorbell) 6792 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6793 6794 return 0; 6795 } 6796 6797 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6798 { 6799 struct amdgpu_device *adev = ring->adev; 6800 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6801 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6802 6803 gfx_v10_0_kiq_setting(ring); 6804 6805 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6806 /* reset MQD to a clean status */ 6807 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6808 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6809 6810 /* reset ring buffer */ 6811 ring->wptr = 0; 6812 amdgpu_ring_clear_ring(ring); 6813 6814 mutex_lock(&adev->srbm_mutex); 6815 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6816 gfx_v10_0_kiq_init_register(ring); 6817 nv_grbm_select(adev, 0, 0, 0, 0); 6818 mutex_unlock(&adev->srbm_mutex); 6819 } else { 6820 memset((void *)mqd, 0, sizeof(*mqd)); 6821 mutex_lock(&adev->srbm_mutex); 6822 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6823 gfx_v10_0_compute_mqd_init(ring); 6824 gfx_v10_0_kiq_init_register(ring); 6825 nv_grbm_select(adev, 0, 0, 0, 0); 6826 mutex_unlock(&adev->srbm_mutex); 6827 6828 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6829 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6830 } 6831 6832 return 0; 6833 } 6834 6835 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6836 { 6837 struct amdgpu_device *adev = ring->adev; 6838 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6839 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6840 6841 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6842 memset((void *)mqd, 0, sizeof(*mqd)); 6843 mutex_lock(&adev->srbm_mutex); 6844 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6845 gfx_v10_0_compute_mqd_init(ring); 6846 nv_grbm_select(adev, 0, 0, 0, 0); 6847 mutex_unlock(&adev->srbm_mutex); 6848 6849 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6850 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6851 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6852 /* reset MQD to a clean status */ 6853 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6854 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6855 6856 /* reset ring buffer */ 6857 ring->wptr = 0; 6858 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6859 amdgpu_ring_clear_ring(ring); 6860 } else { 6861 amdgpu_ring_clear_ring(ring); 6862 } 6863 6864 return 0; 6865 } 6866 6867 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6868 { 6869 struct amdgpu_ring *ring; 6870 int r; 6871 6872 ring = &adev->gfx.kiq.ring; 6873 6874 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6875 if (unlikely(r != 0)) 6876 return r; 6877 6878 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6879 if (unlikely(r != 0)) 6880 return r; 6881 6882 gfx_v10_0_kiq_init_queue(ring); 6883 amdgpu_bo_kunmap(ring->mqd_obj); 6884 ring->mqd_ptr = NULL; 6885 amdgpu_bo_unreserve(ring->mqd_obj); 6886 ring->sched.ready = true; 6887 return 0; 6888 } 6889 6890 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6891 { 6892 struct amdgpu_ring *ring = NULL; 6893 int r = 0, i; 6894 6895 gfx_v10_0_cp_compute_enable(adev, true); 6896 6897 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6898 ring = &adev->gfx.compute_ring[i]; 6899 6900 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6901 if (unlikely(r != 0)) 6902 goto done; 6903 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6904 if (!r) { 6905 r = gfx_v10_0_kcq_init_queue(ring); 6906 amdgpu_bo_kunmap(ring->mqd_obj); 6907 ring->mqd_ptr = NULL; 6908 } 6909 amdgpu_bo_unreserve(ring->mqd_obj); 6910 if (r) 6911 goto done; 6912 } 6913 6914 r = amdgpu_gfx_enable_kcq(adev); 6915 done: 6916 return r; 6917 } 6918 6919 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6920 { 6921 int r, i; 6922 struct amdgpu_ring *ring; 6923 6924 if (!(adev->flags & AMD_IS_APU)) 6925 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6926 6927 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6928 /* legacy firmware loading */ 6929 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6930 if (r) 6931 return r; 6932 6933 r = gfx_v10_0_cp_compute_load_microcode(adev); 6934 if (r) 6935 return r; 6936 } 6937 6938 r = gfx_v10_0_kiq_resume(adev); 6939 if (r) 6940 return r; 6941 6942 r = gfx_v10_0_kcq_resume(adev); 6943 if (r) 6944 return r; 6945 6946 if (!amdgpu_async_gfx_ring) { 6947 r = gfx_v10_0_cp_gfx_resume(adev); 6948 if (r) 6949 return r; 6950 } else { 6951 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6952 if (r) 6953 return r; 6954 } 6955 6956 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6957 ring = &adev->gfx.gfx_ring[i]; 6958 r = amdgpu_ring_test_helper(ring); 6959 if (r) 6960 return r; 6961 } 6962 6963 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6964 ring = &adev->gfx.compute_ring[i]; 6965 r = amdgpu_ring_test_helper(ring); 6966 if (r) 6967 return r; 6968 } 6969 6970 return 0; 6971 } 6972 6973 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6974 { 6975 gfx_v10_0_cp_gfx_enable(adev, enable); 6976 gfx_v10_0_cp_compute_enable(adev, enable); 6977 } 6978 6979 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6980 { 6981 uint32_t data, pattern = 0xDEADBEEF; 6982 6983 /* check if mmVGT_ESGS_RING_SIZE_UMD 6984 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6985 switch (adev->asic_type) { 6986 case CHIP_SIENNA_CICHLID: 6987 case CHIP_NAVY_FLOUNDER: 6988 case CHIP_DIMGREY_CAVEFISH: 6989 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6990 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6991 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6992 6993 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6994 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6995 return true; 6996 } else { 6997 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6998 return false; 6999 } 7000 break; 7001 case CHIP_VANGOGH: 7002 return true; 7003 default: 7004 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7005 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7006 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7007 7008 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7009 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7010 return true; 7011 } else { 7012 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7013 return false; 7014 } 7015 break; 7016 } 7017 } 7018 7019 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7020 { 7021 uint32_t data; 7022 7023 /* initialize cam_index to 0 7024 * index will auto-inc after each data writting */ 7025 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7026 7027 switch (adev->asic_type) { 7028 case CHIP_SIENNA_CICHLID: 7029 case CHIP_NAVY_FLOUNDER: 7030 case CHIP_VANGOGH: 7031 case CHIP_DIMGREY_CAVEFISH: 7032 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7033 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7034 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7035 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7036 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7037 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7038 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7039 7040 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7041 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7042 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7043 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7044 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7045 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7047 7048 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7049 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7050 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7051 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7052 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7053 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7055 7056 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7057 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7058 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7059 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7060 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7061 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7063 7064 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7065 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7066 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7067 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7068 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7069 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7070 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7071 7072 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7073 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7074 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7075 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7076 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7077 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7078 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7079 7080 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7081 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7082 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7083 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7084 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7085 break; 7086 default: 7087 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7088 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7089 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7090 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7091 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7092 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7093 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7094 7095 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7096 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7097 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7098 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7099 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7100 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7101 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7102 7103 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7104 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7105 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7106 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7107 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7108 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7109 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7110 7111 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7112 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7113 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7114 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7115 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7116 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7117 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7118 7119 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7120 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7121 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7122 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7123 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7124 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7125 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7126 7127 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7128 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7129 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7130 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7131 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7132 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7133 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7134 7135 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7136 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7137 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7138 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7139 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7140 break; 7141 } 7142 7143 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7144 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7145 } 7146 7147 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7148 { 7149 uint32_t data; 7150 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7151 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7152 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7153 7154 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7155 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7156 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7157 } 7158 7159 static int gfx_v10_0_hw_init(void *handle) 7160 { 7161 int r; 7162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7163 7164 if (!amdgpu_emu_mode) 7165 gfx_v10_0_init_golden_registers(adev); 7166 7167 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7168 /** 7169 * For gfx 10, rlc firmware loading relies on smu firmware is 7170 * loaded firstly, so in direct type, it has to load smc ucode 7171 * here before rlc. 7172 */ 7173 if (!(adev->flags & AMD_IS_APU)) { 7174 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7175 if (r) 7176 return r; 7177 } 7178 gfx_v10_0_disable_gpa_mode(adev); 7179 } 7180 7181 /* if GRBM CAM not remapped, set up the remapping */ 7182 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7183 gfx_v10_0_setup_grbm_cam_remapping(adev); 7184 7185 gfx_v10_0_constants_init(adev); 7186 7187 r = gfx_v10_0_rlc_resume(adev); 7188 if (r) 7189 return r; 7190 7191 /* 7192 * init golden registers and rlc resume may override some registers, 7193 * reconfig them here 7194 */ 7195 gfx_v10_0_tcp_harvest(adev); 7196 7197 r = gfx_v10_0_cp_resume(adev); 7198 if (r) 7199 return r; 7200 7201 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7202 gfx_v10_3_program_pbb_mode(adev); 7203 7204 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7205 gfx_v10_3_set_power_brake_sequence(adev); 7206 7207 return r; 7208 } 7209 7210 #ifndef BRING_UP_DEBUG 7211 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7212 { 7213 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7214 struct amdgpu_ring *kiq_ring = &kiq->ring; 7215 int i; 7216 7217 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7218 return -EINVAL; 7219 7220 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7221 adev->gfx.num_gfx_rings)) 7222 return -ENOMEM; 7223 7224 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7225 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7226 PREEMPT_QUEUES, 0, 0); 7227 7228 return amdgpu_ring_test_helper(kiq_ring); 7229 } 7230 #endif 7231 7232 static int gfx_v10_0_hw_fini(void *handle) 7233 { 7234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7235 int r; 7236 uint32_t tmp; 7237 7238 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7239 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7240 7241 if (!adev->in_pci_err_recovery) { 7242 #ifndef BRING_UP_DEBUG 7243 if (amdgpu_async_gfx_ring) { 7244 r = gfx_v10_0_kiq_disable_kgq(adev); 7245 if (r) 7246 DRM_ERROR("KGQ disable failed\n"); 7247 } 7248 #endif 7249 if (amdgpu_gfx_disable_kcq(adev)) 7250 DRM_ERROR("KCQ disable failed\n"); 7251 } 7252 7253 if (amdgpu_sriov_vf(adev)) { 7254 gfx_v10_0_cp_gfx_enable(adev, false); 7255 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7256 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7257 tmp &= 0xffffff00; 7258 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7259 7260 return 0; 7261 } 7262 gfx_v10_0_cp_enable(adev, false); 7263 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7264 7265 return 0; 7266 } 7267 7268 static int gfx_v10_0_suspend(void *handle) 7269 { 7270 return gfx_v10_0_hw_fini(handle); 7271 } 7272 7273 static int gfx_v10_0_resume(void *handle) 7274 { 7275 return gfx_v10_0_hw_init(handle); 7276 } 7277 7278 static bool gfx_v10_0_is_idle(void *handle) 7279 { 7280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7281 7282 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7283 GRBM_STATUS, GUI_ACTIVE)) 7284 return false; 7285 else 7286 return true; 7287 } 7288 7289 static int gfx_v10_0_wait_for_idle(void *handle) 7290 { 7291 unsigned i; 7292 u32 tmp; 7293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7294 7295 for (i = 0; i < adev->usec_timeout; i++) { 7296 /* read MC_STATUS */ 7297 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7298 GRBM_STATUS__GUI_ACTIVE_MASK; 7299 7300 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7301 return 0; 7302 udelay(1); 7303 } 7304 return -ETIMEDOUT; 7305 } 7306 7307 static int gfx_v10_0_soft_reset(void *handle) 7308 { 7309 u32 grbm_soft_reset = 0; 7310 u32 tmp; 7311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7312 7313 /* GRBM_STATUS */ 7314 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7315 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7316 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7317 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7318 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7319 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7320 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7321 GRBM_SOFT_RESET, SOFT_RESET_CP, 7322 1); 7323 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7324 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7325 1); 7326 } 7327 7328 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7329 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7330 GRBM_SOFT_RESET, SOFT_RESET_CP, 7331 1); 7332 } 7333 7334 /* GRBM_STATUS2 */ 7335 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7336 switch (adev->asic_type) { 7337 case CHIP_SIENNA_CICHLID: 7338 case CHIP_NAVY_FLOUNDER: 7339 case CHIP_VANGOGH: 7340 case CHIP_DIMGREY_CAVEFISH: 7341 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7342 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7343 GRBM_SOFT_RESET, 7344 SOFT_RESET_RLC, 7345 1); 7346 break; 7347 default: 7348 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7349 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7350 GRBM_SOFT_RESET, 7351 SOFT_RESET_RLC, 7352 1); 7353 break; 7354 } 7355 7356 if (grbm_soft_reset) { 7357 /* stop the rlc */ 7358 gfx_v10_0_rlc_stop(adev); 7359 7360 /* Disable GFX parsing/prefetching */ 7361 gfx_v10_0_cp_gfx_enable(adev, false); 7362 7363 /* Disable MEC parsing/prefetching */ 7364 gfx_v10_0_cp_compute_enable(adev, false); 7365 7366 if (grbm_soft_reset) { 7367 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7368 tmp |= grbm_soft_reset; 7369 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7370 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7371 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7372 7373 udelay(50); 7374 7375 tmp &= ~grbm_soft_reset; 7376 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7377 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7378 } 7379 7380 /* Wait a little for things to settle down */ 7381 udelay(50); 7382 } 7383 return 0; 7384 } 7385 7386 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7387 { 7388 uint64_t clock; 7389 7390 amdgpu_gfx_off_ctrl(adev, false); 7391 mutex_lock(&adev->gfx.gpu_clock_mutex); 7392 switch (adev->asic_type) { 7393 case CHIP_VANGOGH: 7394 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | 7395 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); 7396 break; 7397 default: 7398 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7399 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7400 break; 7401 } 7402 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7403 amdgpu_gfx_off_ctrl(adev, true); 7404 return clock; 7405 } 7406 7407 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7408 uint32_t vmid, 7409 uint32_t gds_base, uint32_t gds_size, 7410 uint32_t gws_base, uint32_t gws_size, 7411 uint32_t oa_base, uint32_t oa_size) 7412 { 7413 struct amdgpu_device *adev = ring->adev; 7414 7415 /* GDS Base */ 7416 gfx_v10_0_write_data_to_reg(ring, 0, false, 7417 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7418 gds_base); 7419 7420 /* GDS Size */ 7421 gfx_v10_0_write_data_to_reg(ring, 0, false, 7422 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7423 gds_size); 7424 7425 /* GWS */ 7426 gfx_v10_0_write_data_to_reg(ring, 0, false, 7427 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7428 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7429 7430 /* OA */ 7431 gfx_v10_0_write_data_to_reg(ring, 0, false, 7432 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7433 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7434 } 7435 7436 static int gfx_v10_0_early_init(void *handle) 7437 { 7438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7439 7440 switch (adev->asic_type) { 7441 case CHIP_NAVI10: 7442 case CHIP_NAVI14: 7443 case CHIP_NAVI12: 7444 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7445 break; 7446 case CHIP_SIENNA_CICHLID: 7447 case CHIP_NAVY_FLOUNDER: 7448 case CHIP_VANGOGH: 7449 case CHIP_DIMGREY_CAVEFISH: 7450 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7451 break; 7452 default: 7453 break; 7454 } 7455 7456 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7457 AMDGPU_MAX_COMPUTE_RINGS); 7458 7459 gfx_v10_0_set_kiq_pm4_funcs(adev); 7460 gfx_v10_0_set_ring_funcs(adev); 7461 gfx_v10_0_set_irq_funcs(adev); 7462 gfx_v10_0_set_gds_init(adev); 7463 gfx_v10_0_set_rlc_funcs(adev); 7464 7465 return 0; 7466 } 7467 7468 static int gfx_v10_0_late_init(void *handle) 7469 { 7470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7471 int r; 7472 7473 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7474 if (r) 7475 return r; 7476 7477 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7478 if (r) 7479 return r; 7480 7481 return 0; 7482 } 7483 7484 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7485 { 7486 uint32_t rlc_cntl; 7487 7488 /* if RLC is not enabled, do nothing */ 7489 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7490 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7491 } 7492 7493 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7494 { 7495 uint32_t data; 7496 unsigned i; 7497 7498 data = RLC_SAFE_MODE__CMD_MASK; 7499 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7500 7501 switch (adev->asic_type) { 7502 case CHIP_SIENNA_CICHLID: 7503 case CHIP_NAVY_FLOUNDER: 7504 case CHIP_VANGOGH: 7505 case CHIP_DIMGREY_CAVEFISH: 7506 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7507 7508 /* wait for RLC_SAFE_MODE */ 7509 for (i = 0; i < adev->usec_timeout; i++) { 7510 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7511 RLC_SAFE_MODE, CMD)) 7512 break; 7513 udelay(1); 7514 } 7515 break; 7516 default: 7517 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7518 7519 /* wait for RLC_SAFE_MODE */ 7520 for (i = 0; i < adev->usec_timeout; i++) { 7521 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7522 RLC_SAFE_MODE, CMD)) 7523 break; 7524 udelay(1); 7525 } 7526 break; 7527 } 7528 } 7529 7530 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7531 { 7532 uint32_t data; 7533 7534 data = RLC_SAFE_MODE__CMD_MASK; 7535 switch (adev->asic_type) { 7536 case CHIP_SIENNA_CICHLID: 7537 case CHIP_NAVY_FLOUNDER: 7538 case CHIP_VANGOGH: 7539 case CHIP_DIMGREY_CAVEFISH: 7540 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7541 break; 7542 default: 7543 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7544 break; 7545 } 7546 } 7547 7548 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7549 bool enable) 7550 { 7551 uint32_t data, def; 7552 7553 /* It is disabled by HW by default */ 7554 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7555 /* 0 - Disable some blocks' MGCG */ 7556 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7557 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7558 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7559 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7560 7561 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7562 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7563 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7564 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7565 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7566 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7567 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7568 7569 if (def != data) 7570 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7571 7572 /* MGLS is a global flag to control all MGLS in GFX */ 7573 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7574 /* 2 - RLC memory Light sleep */ 7575 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7576 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7577 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7578 if (def != data) 7579 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7580 } 7581 /* 3 - CP memory Light sleep */ 7582 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7583 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7584 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7585 if (def != data) 7586 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7587 } 7588 } 7589 } else { 7590 /* 1 - MGCG_OVERRIDE */ 7591 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7592 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7593 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7594 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7595 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7596 if (def != data) 7597 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7598 7599 /* 2 - disable MGLS in CP */ 7600 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7601 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7602 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7603 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7604 } 7605 7606 /* 3 - disable MGLS in RLC */ 7607 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7608 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7609 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7610 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7611 } 7612 7613 } 7614 } 7615 7616 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7617 bool enable) 7618 { 7619 uint32_t data, def; 7620 7621 /* Enable 3D CGCG/CGLS */ 7622 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7623 /* write cmd to clear cgcg/cgls ov */ 7624 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7625 /* unset CGCG override */ 7626 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7627 /* update CGCG and CGLS override bits */ 7628 if (def != data) 7629 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7630 /* enable 3Dcgcg FSM(0x0000363f) */ 7631 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7632 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7633 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7634 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7635 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7636 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7637 if (def != data) 7638 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7639 7640 /* set IDLE_POLL_COUNT(0x00900100) */ 7641 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7642 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7643 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7644 if (def != data) 7645 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7646 } else { 7647 /* Disable CGCG/CGLS */ 7648 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7649 /* disable cgcg, cgls should be disabled */ 7650 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7651 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7652 /* disable cgcg and cgls in FSM */ 7653 if (def != data) 7654 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7655 } 7656 } 7657 7658 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7659 bool enable) 7660 { 7661 uint32_t def, data; 7662 7663 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7664 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7665 /* unset CGCG override */ 7666 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7667 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7668 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7669 else 7670 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7671 /* update CGCG and CGLS override bits */ 7672 if (def != data) 7673 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7674 7675 /* enable cgcg FSM(0x0000363F) */ 7676 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7677 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7678 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7679 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7680 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7681 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7682 if (def != data) 7683 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7684 7685 /* set IDLE_POLL_COUNT(0x00900100) */ 7686 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7687 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7688 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7689 if (def != data) 7690 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7691 } else { 7692 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7693 /* reset CGCG/CGLS bits */ 7694 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7695 /* disable cgcg and cgls in FSM */ 7696 if (def != data) 7697 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7698 } 7699 } 7700 7701 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7702 bool enable) 7703 { 7704 uint32_t def, data; 7705 7706 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7707 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7708 /* unset FGCG override */ 7709 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7710 /* update FGCG override bits */ 7711 if (def != data) 7712 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7713 7714 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7715 /* unset RLC SRAM CLK GATER override */ 7716 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7717 /* update RLC SRAM CLK GATER override bits */ 7718 if (def != data) 7719 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7720 } else { 7721 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7722 /* reset FGCG bits */ 7723 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7724 /* disable FGCG*/ 7725 if (def != data) 7726 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7727 7728 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7729 /* reset RLC SRAM CLK GATER bits */ 7730 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7731 /* disable RLC SRAM CLK*/ 7732 if (def != data) 7733 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7734 } 7735 } 7736 7737 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7738 bool enable) 7739 { 7740 amdgpu_gfx_rlc_enter_safe_mode(adev); 7741 7742 if (enable) { 7743 /* enable FGCG firstly*/ 7744 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7745 /* CGCG/CGLS should be enabled after MGCG/MGLS 7746 * === MGCG + MGLS === 7747 */ 7748 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7749 /* === CGCG /CGLS for GFX 3D Only === */ 7750 gfx_v10_0_update_3d_clock_gating(adev, enable); 7751 /* === CGCG + CGLS === */ 7752 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7753 } else { 7754 /* CGCG/CGLS should be disabled before MGCG/MGLS 7755 * === CGCG + CGLS === 7756 */ 7757 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7758 /* === CGCG /CGLS for GFX 3D Only === */ 7759 gfx_v10_0_update_3d_clock_gating(adev, enable); 7760 /* === MGCG + MGLS === */ 7761 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7762 /* disable fgcg at last*/ 7763 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7764 } 7765 7766 if (adev->cg_flags & 7767 (AMD_CG_SUPPORT_GFX_MGCG | 7768 AMD_CG_SUPPORT_GFX_CGLS | 7769 AMD_CG_SUPPORT_GFX_CGCG | 7770 AMD_CG_SUPPORT_GFX_3D_CGCG | 7771 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7772 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7773 7774 amdgpu_gfx_rlc_exit_safe_mode(adev); 7775 7776 return 0; 7777 } 7778 7779 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7780 { 7781 u32 reg, data; 7782 7783 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7784 if (amdgpu_sriov_is_pp_one_vf(adev)) 7785 data = RREG32_NO_KIQ(reg); 7786 else 7787 data = RREG32(reg); 7788 7789 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7790 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7791 7792 if (amdgpu_sriov_is_pp_one_vf(adev)) 7793 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7794 else 7795 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7796 } 7797 7798 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7799 uint32_t offset, 7800 struct soc15_reg_rlcg *entries, int arr_size) 7801 { 7802 int i; 7803 uint32_t reg; 7804 7805 if (!entries) 7806 return false; 7807 7808 for (i = 0; i < arr_size; i++) { 7809 const struct soc15_reg_rlcg *entry; 7810 7811 entry = &entries[i]; 7812 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7813 if (offset == reg) 7814 return true; 7815 } 7816 7817 return false; 7818 } 7819 7820 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7821 { 7822 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7823 } 7824 7825 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7826 { 7827 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7828 7829 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7830 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7831 else 7832 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7833 7834 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7835 7836 /* 7837 * CGPG enablement required and the register to program the hysteresis value 7838 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 7839 * in refclk count. Note that RLC FW is modified to take 16 bits from 7840 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 7841 * 7842 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20) 7843 * as part of CGPG enablement starting point. 7844 */ 7845 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) { 7846 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 7847 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 7848 } 7849 } 7850 7851 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7852 { 7853 amdgpu_gfx_rlc_enter_safe_mode(adev); 7854 7855 gfx_v10_cntl_power_gating(adev, enable); 7856 7857 amdgpu_gfx_rlc_exit_safe_mode(adev); 7858 } 7859 7860 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7861 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7862 .set_safe_mode = gfx_v10_0_set_safe_mode, 7863 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7864 .init = gfx_v10_0_rlc_init, 7865 .get_csb_size = gfx_v10_0_get_csb_size, 7866 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7867 .resume = gfx_v10_0_rlc_resume, 7868 .stop = gfx_v10_0_rlc_stop, 7869 .reset = gfx_v10_0_rlc_reset, 7870 .start = gfx_v10_0_rlc_start, 7871 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7872 }; 7873 7874 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7875 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7876 .set_safe_mode = gfx_v10_0_set_safe_mode, 7877 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7878 .init = gfx_v10_0_rlc_init, 7879 .get_csb_size = gfx_v10_0_get_csb_size, 7880 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7881 .resume = gfx_v10_0_rlc_resume, 7882 .stop = gfx_v10_0_rlc_stop, 7883 .reset = gfx_v10_0_rlc_reset, 7884 .start = gfx_v10_0_rlc_start, 7885 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7886 .rlcg_wreg = gfx_v10_rlcg_wreg, 7887 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7888 }; 7889 7890 static int gfx_v10_0_set_powergating_state(void *handle, 7891 enum amd_powergating_state state) 7892 { 7893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7894 bool enable = (state == AMD_PG_STATE_GATE); 7895 7896 if (amdgpu_sriov_vf(adev)) 7897 return 0; 7898 7899 switch (adev->asic_type) { 7900 case CHIP_NAVI10: 7901 case CHIP_NAVI14: 7902 case CHIP_NAVI12: 7903 case CHIP_SIENNA_CICHLID: 7904 case CHIP_NAVY_FLOUNDER: 7905 case CHIP_DIMGREY_CAVEFISH: 7906 amdgpu_gfx_off_ctrl(adev, enable); 7907 break; 7908 case CHIP_VANGOGH: 7909 gfx_v10_cntl_pg(adev, enable); 7910 amdgpu_gfx_off_ctrl(adev, enable); 7911 break; 7912 default: 7913 break; 7914 } 7915 return 0; 7916 } 7917 7918 static int gfx_v10_0_set_clockgating_state(void *handle, 7919 enum amd_clockgating_state state) 7920 { 7921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7922 7923 if (amdgpu_sriov_vf(adev)) 7924 return 0; 7925 7926 switch (adev->asic_type) { 7927 case CHIP_NAVI10: 7928 case CHIP_NAVI14: 7929 case CHIP_NAVI12: 7930 case CHIP_SIENNA_CICHLID: 7931 case CHIP_NAVY_FLOUNDER: 7932 case CHIP_VANGOGH: 7933 case CHIP_DIMGREY_CAVEFISH: 7934 gfx_v10_0_update_gfx_clock_gating(adev, 7935 state == AMD_CG_STATE_GATE); 7936 break; 7937 default: 7938 break; 7939 } 7940 return 0; 7941 } 7942 7943 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7944 { 7945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7946 int data; 7947 7948 /* AMD_CG_SUPPORT_GFX_FGCG */ 7949 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7950 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7951 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7952 7953 /* AMD_CG_SUPPORT_GFX_MGCG */ 7954 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7955 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7956 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7957 7958 /* AMD_CG_SUPPORT_GFX_CGCG */ 7959 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7960 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7961 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7962 7963 /* AMD_CG_SUPPORT_GFX_CGLS */ 7964 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7965 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7966 7967 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7968 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7969 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7970 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7971 7972 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7973 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7974 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7975 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7976 7977 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7978 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7979 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7980 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7981 7982 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7983 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7984 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7985 } 7986 7987 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7988 { 7989 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7990 } 7991 7992 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7993 { 7994 struct amdgpu_device *adev = ring->adev; 7995 u64 wptr; 7996 7997 /* XXX check if swapping is necessary on BE */ 7998 if (ring->use_doorbell) { 7999 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8000 } else { 8001 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8002 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8003 } 8004 8005 return wptr; 8006 } 8007 8008 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8009 { 8010 struct amdgpu_device *adev = ring->adev; 8011 8012 if (ring->use_doorbell) { 8013 /* XXX check if swapping is necessary on BE */ 8014 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8015 WDOORBELL64(ring->doorbell_index, ring->wptr); 8016 } else { 8017 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8018 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8019 } 8020 } 8021 8022 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8023 { 8024 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8025 } 8026 8027 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8028 { 8029 u64 wptr; 8030 8031 /* XXX check if swapping is necessary on BE */ 8032 if (ring->use_doorbell) 8033 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8034 else 8035 BUG(); 8036 return wptr; 8037 } 8038 8039 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8040 { 8041 struct amdgpu_device *adev = ring->adev; 8042 8043 /* XXX check if swapping is necessary on BE */ 8044 if (ring->use_doorbell) { 8045 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8046 WDOORBELL64(ring->doorbell_index, ring->wptr); 8047 } else { 8048 BUG(); /* only DOORBELL method supported on gfx10 now */ 8049 } 8050 } 8051 8052 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8053 { 8054 struct amdgpu_device *adev = ring->adev; 8055 u32 ref_and_mask, reg_mem_engine; 8056 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8057 8058 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8059 switch (ring->me) { 8060 case 1: 8061 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8062 break; 8063 case 2: 8064 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8065 break; 8066 default: 8067 return; 8068 } 8069 reg_mem_engine = 0; 8070 } else { 8071 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8072 reg_mem_engine = 1; /* pfp */ 8073 } 8074 8075 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8076 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8077 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8078 ref_and_mask, ref_and_mask, 0x20); 8079 } 8080 8081 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8082 struct amdgpu_job *job, 8083 struct amdgpu_ib *ib, 8084 uint32_t flags) 8085 { 8086 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8087 u32 header, control = 0; 8088 8089 if (ib->flags & AMDGPU_IB_FLAG_CE) 8090 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8091 else 8092 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8093 8094 control |= ib->length_dw | (vmid << 24); 8095 8096 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8097 control |= INDIRECT_BUFFER_PRE_ENB(1); 8098 8099 if (flags & AMDGPU_IB_PREEMPTED) 8100 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8101 8102 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8103 gfx_v10_0_ring_emit_de_meta(ring, 8104 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8105 } 8106 8107 amdgpu_ring_write(ring, header); 8108 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8109 amdgpu_ring_write(ring, 8110 #ifdef __BIG_ENDIAN 8111 (2 << 0) | 8112 #endif 8113 lower_32_bits(ib->gpu_addr)); 8114 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8115 amdgpu_ring_write(ring, control); 8116 } 8117 8118 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8119 struct amdgpu_job *job, 8120 struct amdgpu_ib *ib, 8121 uint32_t flags) 8122 { 8123 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8124 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8125 8126 /* Currently, there is a high possibility to get wave ID mismatch 8127 * between ME and GDS, leading to a hw deadlock, because ME generates 8128 * different wave IDs than the GDS expects. This situation happens 8129 * randomly when at least 5 compute pipes use GDS ordered append. 8130 * The wave IDs generated by ME are also wrong after suspend/resume. 8131 * Those are probably bugs somewhere else in the kernel driver. 8132 * 8133 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8134 * GDS to 0 for this ring (me/pipe). 8135 */ 8136 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8137 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8138 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8139 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8140 } 8141 8142 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8143 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8144 amdgpu_ring_write(ring, 8145 #ifdef __BIG_ENDIAN 8146 (2 << 0) | 8147 #endif 8148 lower_32_bits(ib->gpu_addr)); 8149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8150 amdgpu_ring_write(ring, control); 8151 } 8152 8153 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8154 u64 seq, unsigned flags) 8155 { 8156 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8157 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8158 8159 /* RELEASE_MEM - flush caches, send int */ 8160 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8161 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8162 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8163 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8164 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8165 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8166 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8167 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8168 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8169 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8170 8171 /* 8172 * the address should be Qword aligned if 64bit write, Dword 8173 * aligned if only send 32bit data low (discard data high) 8174 */ 8175 if (write64bit) 8176 BUG_ON(addr & 0x7); 8177 else 8178 BUG_ON(addr & 0x3); 8179 amdgpu_ring_write(ring, lower_32_bits(addr)); 8180 amdgpu_ring_write(ring, upper_32_bits(addr)); 8181 amdgpu_ring_write(ring, lower_32_bits(seq)); 8182 amdgpu_ring_write(ring, upper_32_bits(seq)); 8183 amdgpu_ring_write(ring, 0); 8184 } 8185 8186 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8187 { 8188 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8189 uint32_t seq = ring->fence_drv.sync_seq; 8190 uint64_t addr = ring->fence_drv.gpu_addr; 8191 8192 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8193 upper_32_bits(addr), seq, 0xffffffff, 4); 8194 } 8195 8196 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8197 unsigned vmid, uint64_t pd_addr) 8198 { 8199 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8200 8201 /* compute doesn't have PFP */ 8202 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8203 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8204 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8205 amdgpu_ring_write(ring, 0x0); 8206 } 8207 } 8208 8209 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8210 u64 seq, unsigned int flags) 8211 { 8212 struct amdgpu_device *adev = ring->adev; 8213 8214 /* we only allocate 32bit for each seq wb address */ 8215 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8216 8217 /* write fence seq to the "addr" */ 8218 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8219 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8220 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8221 amdgpu_ring_write(ring, lower_32_bits(addr)); 8222 amdgpu_ring_write(ring, upper_32_bits(addr)); 8223 amdgpu_ring_write(ring, lower_32_bits(seq)); 8224 8225 if (flags & AMDGPU_FENCE_FLAG_INT) { 8226 /* set register to trigger INT */ 8227 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8228 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8229 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8230 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8231 amdgpu_ring_write(ring, 0); 8232 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8233 } 8234 } 8235 8236 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8237 { 8238 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8239 amdgpu_ring_write(ring, 0); 8240 } 8241 8242 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8243 uint32_t flags) 8244 { 8245 uint32_t dw2 = 0; 8246 8247 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8248 gfx_v10_0_ring_emit_ce_meta(ring, 8249 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8250 8251 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8252 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8253 /* set load_global_config & load_global_uconfig */ 8254 dw2 |= 0x8001; 8255 /* set load_cs_sh_regs */ 8256 dw2 |= 0x01000000; 8257 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8258 dw2 |= 0x10002; 8259 8260 /* set load_ce_ram if preamble presented */ 8261 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8262 dw2 |= 0x10000000; 8263 } else { 8264 /* still load_ce_ram if this is the first time preamble presented 8265 * although there is no context switch happens. 8266 */ 8267 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8268 dw2 |= 0x10000000; 8269 } 8270 8271 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8272 amdgpu_ring_write(ring, dw2); 8273 amdgpu_ring_write(ring, 0); 8274 } 8275 8276 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8277 { 8278 unsigned ret; 8279 8280 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8281 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8282 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8283 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8284 ret = ring->wptr & ring->buf_mask; 8285 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8286 8287 return ret; 8288 } 8289 8290 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8291 { 8292 unsigned cur; 8293 BUG_ON(offset > ring->buf_mask); 8294 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8295 8296 cur = (ring->wptr - 1) & ring->buf_mask; 8297 if (likely(cur > offset)) 8298 ring->ring[offset] = cur - offset; 8299 else 8300 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8301 } 8302 8303 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8304 { 8305 int i, r = 0; 8306 struct amdgpu_device *adev = ring->adev; 8307 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8308 struct amdgpu_ring *kiq_ring = &kiq->ring; 8309 unsigned long flags; 8310 8311 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8312 return -EINVAL; 8313 8314 spin_lock_irqsave(&kiq->ring_lock, flags); 8315 8316 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8317 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8318 return -ENOMEM; 8319 } 8320 8321 /* assert preemption condition */ 8322 amdgpu_ring_set_preempt_cond_exec(ring, false); 8323 8324 /* assert IB preemption, emit the trailing fence */ 8325 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8326 ring->trail_fence_gpu_addr, 8327 ++ring->trail_seq); 8328 amdgpu_ring_commit(kiq_ring); 8329 8330 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8331 8332 /* poll the trailing fence */ 8333 for (i = 0; i < adev->usec_timeout; i++) { 8334 if (ring->trail_seq == 8335 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8336 break; 8337 udelay(1); 8338 } 8339 8340 if (i >= adev->usec_timeout) { 8341 r = -EINVAL; 8342 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8343 } 8344 8345 /* deassert preemption condition */ 8346 amdgpu_ring_set_preempt_cond_exec(ring, true); 8347 return r; 8348 } 8349 8350 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8351 { 8352 struct amdgpu_device *adev = ring->adev; 8353 struct v10_ce_ib_state ce_payload = {0}; 8354 uint64_t csa_addr; 8355 int cnt; 8356 8357 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8358 csa_addr = amdgpu_csa_vaddr(ring->adev); 8359 8360 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8361 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8362 WRITE_DATA_DST_SEL(8) | 8363 WR_CONFIRM) | 8364 WRITE_DATA_CACHE_POLICY(0)); 8365 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8366 offsetof(struct v10_gfx_meta_data, ce_payload))); 8367 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8368 offsetof(struct v10_gfx_meta_data, ce_payload))); 8369 8370 if (resume) 8371 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8372 offsetof(struct v10_gfx_meta_data, 8373 ce_payload), 8374 sizeof(ce_payload) >> 2); 8375 else 8376 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8377 sizeof(ce_payload) >> 2); 8378 } 8379 8380 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8381 { 8382 struct amdgpu_device *adev = ring->adev; 8383 struct v10_de_ib_state de_payload = {0}; 8384 uint64_t csa_addr, gds_addr; 8385 int cnt; 8386 8387 csa_addr = amdgpu_csa_vaddr(ring->adev); 8388 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8389 PAGE_SIZE); 8390 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8391 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8392 8393 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8394 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8395 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8396 WRITE_DATA_DST_SEL(8) | 8397 WR_CONFIRM) | 8398 WRITE_DATA_CACHE_POLICY(0)); 8399 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8400 offsetof(struct v10_gfx_meta_data, de_payload))); 8401 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8402 offsetof(struct v10_gfx_meta_data, de_payload))); 8403 8404 if (resume) 8405 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8406 offsetof(struct v10_gfx_meta_data, 8407 de_payload), 8408 sizeof(de_payload) >> 2); 8409 else 8410 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8411 sizeof(de_payload) >> 2); 8412 } 8413 8414 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8415 bool secure) 8416 { 8417 uint32_t v = secure ? FRAME_TMZ : 0; 8418 8419 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8420 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8421 } 8422 8423 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8424 uint32_t reg_val_offs) 8425 { 8426 struct amdgpu_device *adev = ring->adev; 8427 8428 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8429 amdgpu_ring_write(ring, 0 | /* src: register*/ 8430 (5 << 8) | /* dst: memory */ 8431 (1 << 20)); /* write confirm */ 8432 amdgpu_ring_write(ring, reg); 8433 amdgpu_ring_write(ring, 0); 8434 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8435 reg_val_offs * 4)); 8436 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8437 reg_val_offs * 4)); 8438 } 8439 8440 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8441 uint32_t val) 8442 { 8443 uint32_t cmd = 0; 8444 8445 switch (ring->funcs->type) { 8446 case AMDGPU_RING_TYPE_GFX: 8447 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8448 break; 8449 case AMDGPU_RING_TYPE_KIQ: 8450 cmd = (1 << 16); /* no inc addr */ 8451 break; 8452 default: 8453 cmd = WR_CONFIRM; 8454 break; 8455 } 8456 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8457 amdgpu_ring_write(ring, cmd); 8458 amdgpu_ring_write(ring, reg); 8459 amdgpu_ring_write(ring, 0); 8460 amdgpu_ring_write(ring, val); 8461 } 8462 8463 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8464 uint32_t val, uint32_t mask) 8465 { 8466 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8467 } 8468 8469 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8470 uint32_t reg0, uint32_t reg1, 8471 uint32_t ref, uint32_t mask) 8472 { 8473 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8474 struct amdgpu_device *adev = ring->adev; 8475 bool fw_version_ok = false; 8476 8477 fw_version_ok = adev->gfx.cp_fw_write_wait; 8478 8479 if (fw_version_ok) 8480 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8481 ref, mask, 0x20); 8482 else 8483 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8484 ref, mask); 8485 } 8486 8487 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8488 unsigned vmid) 8489 { 8490 struct amdgpu_device *adev = ring->adev; 8491 uint32_t value = 0; 8492 8493 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8494 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8495 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8496 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8497 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8498 } 8499 8500 static void 8501 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8502 uint32_t me, uint32_t pipe, 8503 enum amdgpu_interrupt_state state) 8504 { 8505 uint32_t cp_int_cntl, cp_int_cntl_reg; 8506 8507 if (!me) { 8508 switch (pipe) { 8509 case 0: 8510 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8511 break; 8512 case 1: 8513 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8514 break; 8515 default: 8516 DRM_DEBUG("invalid pipe %d\n", pipe); 8517 return; 8518 } 8519 } else { 8520 DRM_DEBUG("invalid me %d\n", me); 8521 return; 8522 } 8523 8524 switch (state) { 8525 case AMDGPU_IRQ_STATE_DISABLE: 8526 cp_int_cntl = RREG32(cp_int_cntl_reg); 8527 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8528 TIME_STAMP_INT_ENABLE, 0); 8529 WREG32(cp_int_cntl_reg, cp_int_cntl); 8530 break; 8531 case AMDGPU_IRQ_STATE_ENABLE: 8532 cp_int_cntl = RREG32(cp_int_cntl_reg); 8533 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8534 TIME_STAMP_INT_ENABLE, 1); 8535 WREG32(cp_int_cntl_reg, cp_int_cntl); 8536 break; 8537 default: 8538 break; 8539 } 8540 } 8541 8542 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8543 int me, int pipe, 8544 enum amdgpu_interrupt_state state) 8545 { 8546 u32 mec_int_cntl, mec_int_cntl_reg; 8547 8548 /* 8549 * amdgpu controls only the first MEC. That's why this function only 8550 * handles the setting of interrupts for this specific MEC. All other 8551 * pipes' interrupts are set by amdkfd. 8552 */ 8553 8554 if (me == 1) { 8555 switch (pipe) { 8556 case 0: 8557 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8558 break; 8559 case 1: 8560 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8561 break; 8562 case 2: 8563 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8564 break; 8565 case 3: 8566 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8567 break; 8568 default: 8569 DRM_DEBUG("invalid pipe %d\n", pipe); 8570 return; 8571 } 8572 } else { 8573 DRM_DEBUG("invalid me %d\n", me); 8574 return; 8575 } 8576 8577 switch (state) { 8578 case AMDGPU_IRQ_STATE_DISABLE: 8579 mec_int_cntl = RREG32(mec_int_cntl_reg); 8580 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8581 TIME_STAMP_INT_ENABLE, 0); 8582 WREG32(mec_int_cntl_reg, mec_int_cntl); 8583 break; 8584 case AMDGPU_IRQ_STATE_ENABLE: 8585 mec_int_cntl = RREG32(mec_int_cntl_reg); 8586 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8587 TIME_STAMP_INT_ENABLE, 1); 8588 WREG32(mec_int_cntl_reg, mec_int_cntl); 8589 break; 8590 default: 8591 break; 8592 } 8593 } 8594 8595 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8596 struct amdgpu_irq_src *src, 8597 unsigned type, 8598 enum amdgpu_interrupt_state state) 8599 { 8600 switch (type) { 8601 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8602 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8603 break; 8604 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8605 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8606 break; 8607 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8608 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8609 break; 8610 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8611 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8612 break; 8613 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8614 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8615 break; 8616 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8617 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8618 break; 8619 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8620 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8621 break; 8622 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8623 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8624 break; 8625 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8626 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8627 break; 8628 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8629 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8630 break; 8631 default: 8632 break; 8633 } 8634 return 0; 8635 } 8636 8637 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8638 struct amdgpu_irq_src *source, 8639 struct amdgpu_iv_entry *entry) 8640 { 8641 int i; 8642 u8 me_id, pipe_id, queue_id; 8643 struct amdgpu_ring *ring; 8644 8645 DRM_DEBUG("IH: CP EOP\n"); 8646 me_id = (entry->ring_id & 0x0c) >> 2; 8647 pipe_id = (entry->ring_id & 0x03) >> 0; 8648 queue_id = (entry->ring_id & 0x70) >> 4; 8649 8650 switch (me_id) { 8651 case 0: 8652 if (pipe_id == 0) 8653 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8654 else 8655 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8656 break; 8657 case 1: 8658 case 2: 8659 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8660 ring = &adev->gfx.compute_ring[i]; 8661 /* Per-queue interrupt is supported for MEC starting from VI. 8662 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8663 */ 8664 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8665 amdgpu_fence_process(ring); 8666 } 8667 break; 8668 } 8669 return 0; 8670 } 8671 8672 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8673 struct amdgpu_irq_src *source, 8674 unsigned type, 8675 enum amdgpu_interrupt_state state) 8676 { 8677 switch (state) { 8678 case AMDGPU_IRQ_STATE_DISABLE: 8679 case AMDGPU_IRQ_STATE_ENABLE: 8680 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8681 PRIV_REG_INT_ENABLE, 8682 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8683 break; 8684 default: 8685 break; 8686 } 8687 8688 return 0; 8689 } 8690 8691 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8692 struct amdgpu_irq_src *source, 8693 unsigned type, 8694 enum amdgpu_interrupt_state state) 8695 { 8696 switch (state) { 8697 case AMDGPU_IRQ_STATE_DISABLE: 8698 case AMDGPU_IRQ_STATE_ENABLE: 8699 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8700 PRIV_INSTR_INT_ENABLE, 8701 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8702 break; 8703 default: 8704 break; 8705 } 8706 8707 return 0; 8708 } 8709 8710 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8711 struct amdgpu_iv_entry *entry) 8712 { 8713 u8 me_id, pipe_id, queue_id; 8714 struct amdgpu_ring *ring; 8715 int i; 8716 8717 me_id = (entry->ring_id & 0x0c) >> 2; 8718 pipe_id = (entry->ring_id & 0x03) >> 0; 8719 queue_id = (entry->ring_id & 0x70) >> 4; 8720 8721 switch (me_id) { 8722 case 0: 8723 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8724 ring = &adev->gfx.gfx_ring[i]; 8725 /* we only enabled 1 gfx queue per pipe for now */ 8726 if (ring->me == me_id && ring->pipe == pipe_id) 8727 drm_sched_fault(&ring->sched); 8728 } 8729 break; 8730 case 1: 8731 case 2: 8732 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8733 ring = &adev->gfx.compute_ring[i]; 8734 if (ring->me == me_id && ring->pipe == pipe_id && 8735 ring->queue == queue_id) 8736 drm_sched_fault(&ring->sched); 8737 } 8738 break; 8739 default: 8740 BUG(); 8741 } 8742 } 8743 8744 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8745 struct amdgpu_irq_src *source, 8746 struct amdgpu_iv_entry *entry) 8747 { 8748 DRM_ERROR("Illegal register access in command stream\n"); 8749 gfx_v10_0_handle_priv_fault(adev, entry); 8750 return 0; 8751 } 8752 8753 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8754 struct amdgpu_irq_src *source, 8755 struct amdgpu_iv_entry *entry) 8756 { 8757 DRM_ERROR("Illegal instruction in command stream\n"); 8758 gfx_v10_0_handle_priv_fault(adev, entry); 8759 return 0; 8760 } 8761 8762 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8763 struct amdgpu_irq_src *src, 8764 unsigned int type, 8765 enum amdgpu_interrupt_state state) 8766 { 8767 uint32_t tmp, target; 8768 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8769 8770 if (ring->me == 1) 8771 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8772 else 8773 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8774 target += ring->pipe; 8775 8776 switch (type) { 8777 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8778 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8779 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8780 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8781 GENERIC2_INT_ENABLE, 0); 8782 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8783 8784 tmp = RREG32(target); 8785 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8786 GENERIC2_INT_ENABLE, 0); 8787 WREG32(target, tmp); 8788 } else { 8789 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8790 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8791 GENERIC2_INT_ENABLE, 1); 8792 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8793 8794 tmp = RREG32(target); 8795 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8796 GENERIC2_INT_ENABLE, 1); 8797 WREG32(target, tmp); 8798 } 8799 break; 8800 default: 8801 BUG(); /* kiq only support GENERIC2_INT now */ 8802 break; 8803 } 8804 return 0; 8805 } 8806 8807 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8808 struct amdgpu_irq_src *source, 8809 struct amdgpu_iv_entry *entry) 8810 { 8811 u8 me_id, pipe_id, queue_id; 8812 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8813 8814 me_id = (entry->ring_id & 0x0c) >> 2; 8815 pipe_id = (entry->ring_id & 0x03) >> 0; 8816 queue_id = (entry->ring_id & 0x70) >> 4; 8817 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8818 me_id, pipe_id, queue_id); 8819 8820 amdgpu_fence_process(ring); 8821 return 0; 8822 } 8823 8824 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8825 { 8826 const unsigned int gcr_cntl = 8827 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8828 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8829 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8830 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8831 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8832 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8833 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8834 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8835 8836 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8837 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8838 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8839 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8840 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8841 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8842 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8843 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8844 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8845 } 8846 8847 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8848 .name = "gfx_v10_0", 8849 .early_init = gfx_v10_0_early_init, 8850 .late_init = gfx_v10_0_late_init, 8851 .sw_init = gfx_v10_0_sw_init, 8852 .sw_fini = gfx_v10_0_sw_fini, 8853 .hw_init = gfx_v10_0_hw_init, 8854 .hw_fini = gfx_v10_0_hw_fini, 8855 .suspend = gfx_v10_0_suspend, 8856 .resume = gfx_v10_0_resume, 8857 .is_idle = gfx_v10_0_is_idle, 8858 .wait_for_idle = gfx_v10_0_wait_for_idle, 8859 .soft_reset = gfx_v10_0_soft_reset, 8860 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8861 .set_powergating_state = gfx_v10_0_set_powergating_state, 8862 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8863 }; 8864 8865 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8866 .type = AMDGPU_RING_TYPE_GFX, 8867 .align_mask = 0xff, 8868 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8869 .support_64bit_ptrs = true, 8870 .vmhub = AMDGPU_GFXHUB_0, 8871 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8872 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8873 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8874 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8875 5 + /* COND_EXEC */ 8876 7 + /* PIPELINE_SYNC */ 8877 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8878 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8879 2 + /* VM_FLUSH */ 8880 8 + /* FENCE for VM_FLUSH */ 8881 20 + /* GDS switch */ 8882 4 + /* double SWITCH_BUFFER, 8883 * the first COND_EXEC jump to the place 8884 * just prior to this double SWITCH_BUFFER 8885 */ 8886 5 + /* COND_EXEC */ 8887 7 + /* HDP_flush */ 8888 4 + /* VGT_flush */ 8889 14 + /* CE_META */ 8890 31 + /* DE_META */ 8891 3 + /* CNTX_CTRL */ 8892 5 + /* HDP_INVL */ 8893 8 + 8 + /* FENCE x2 */ 8894 2 + /* SWITCH_BUFFER */ 8895 8, /* gfx_v10_0_emit_mem_sync */ 8896 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8897 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8898 .emit_fence = gfx_v10_0_ring_emit_fence, 8899 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8900 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8901 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8902 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8903 .test_ring = gfx_v10_0_ring_test_ring, 8904 .test_ib = gfx_v10_0_ring_test_ib, 8905 .insert_nop = amdgpu_ring_insert_nop, 8906 .pad_ib = amdgpu_ring_generic_pad_ib, 8907 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8908 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8909 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8910 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8911 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8912 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8913 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8914 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8915 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8916 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8917 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8918 }; 8919 8920 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8921 .type = AMDGPU_RING_TYPE_COMPUTE, 8922 .align_mask = 0xff, 8923 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8924 .support_64bit_ptrs = true, 8925 .vmhub = AMDGPU_GFXHUB_0, 8926 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8927 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8928 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8929 .emit_frame_size = 8930 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8931 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8932 5 + /* hdp invalidate */ 8933 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8934 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8935 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8936 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8937 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8938 8, /* gfx_v10_0_emit_mem_sync */ 8939 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8940 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8941 .emit_fence = gfx_v10_0_ring_emit_fence, 8942 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8943 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8944 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8945 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8946 .test_ring = gfx_v10_0_ring_test_ring, 8947 .test_ib = gfx_v10_0_ring_test_ib, 8948 .insert_nop = amdgpu_ring_insert_nop, 8949 .pad_ib = amdgpu_ring_generic_pad_ib, 8950 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8951 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8952 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8953 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8954 }; 8955 8956 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8957 .type = AMDGPU_RING_TYPE_KIQ, 8958 .align_mask = 0xff, 8959 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8960 .support_64bit_ptrs = true, 8961 .vmhub = AMDGPU_GFXHUB_0, 8962 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8963 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8964 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8965 .emit_frame_size = 8966 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8967 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8968 5 + /*hdp invalidate */ 8969 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8970 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8971 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8972 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8973 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8974 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8975 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8976 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8977 .test_ring = gfx_v10_0_ring_test_ring, 8978 .test_ib = gfx_v10_0_ring_test_ib, 8979 .insert_nop = amdgpu_ring_insert_nop, 8980 .pad_ib = amdgpu_ring_generic_pad_ib, 8981 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8982 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8983 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8984 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8985 }; 8986 8987 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8988 { 8989 int i; 8990 8991 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8992 8993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8994 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8995 8996 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8997 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8998 } 8999 9000 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9001 .set = gfx_v10_0_set_eop_interrupt_state, 9002 .process = gfx_v10_0_eop_irq, 9003 }; 9004 9005 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9006 .set = gfx_v10_0_set_priv_reg_fault_state, 9007 .process = gfx_v10_0_priv_reg_irq, 9008 }; 9009 9010 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9011 .set = gfx_v10_0_set_priv_inst_fault_state, 9012 .process = gfx_v10_0_priv_inst_irq, 9013 }; 9014 9015 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9016 .set = gfx_v10_0_kiq_set_interrupt_state, 9017 .process = gfx_v10_0_kiq_irq, 9018 }; 9019 9020 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9021 { 9022 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9023 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9024 9025 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9026 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9027 9028 adev->gfx.priv_reg_irq.num_types = 1; 9029 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9030 9031 adev->gfx.priv_inst_irq.num_types = 1; 9032 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9033 } 9034 9035 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9036 { 9037 switch (adev->asic_type) { 9038 case CHIP_NAVI10: 9039 case CHIP_NAVI14: 9040 case CHIP_SIENNA_CICHLID: 9041 case CHIP_NAVY_FLOUNDER: 9042 case CHIP_VANGOGH: 9043 case CHIP_DIMGREY_CAVEFISH: 9044 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9045 break; 9046 case CHIP_NAVI12: 9047 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9048 break; 9049 default: 9050 break; 9051 } 9052 } 9053 9054 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9055 { 9056 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9057 adev->gfx.config.max_sh_per_se * 9058 adev->gfx.config.max_shader_engines; 9059 9060 adev->gds.gds_size = 0x10000; 9061 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9062 adev->gds.gws_size = 64; 9063 adev->gds.oa_size = 16; 9064 } 9065 9066 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9067 u32 bitmap) 9068 { 9069 u32 data; 9070 9071 if (!bitmap) 9072 return; 9073 9074 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9075 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9076 9077 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9078 } 9079 9080 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9081 { 9082 u32 data, wgp_bitmask; 9083 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9084 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9085 9086 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9087 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9088 9089 wgp_bitmask = 9090 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9091 9092 return (~data) & wgp_bitmask; 9093 } 9094 9095 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9096 { 9097 u32 wgp_idx, wgp_active_bitmap; 9098 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9099 9100 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9101 cu_active_bitmap = 0; 9102 9103 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9104 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9105 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9106 if (wgp_active_bitmap & (1 << wgp_idx)) 9107 cu_active_bitmap |= cu_bitmap_per_wgp; 9108 } 9109 9110 return cu_active_bitmap; 9111 } 9112 9113 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9114 struct amdgpu_cu_info *cu_info) 9115 { 9116 int i, j, k, counter, active_cu_number = 0; 9117 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9118 unsigned disable_masks[4 * 2]; 9119 9120 if (!adev || !cu_info) 9121 return -EINVAL; 9122 9123 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9124 9125 mutex_lock(&adev->grbm_idx_mutex); 9126 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9127 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9128 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9129 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9130 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9131 continue; 9132 mask = 1; 9133 ao_bitmap = 0; 9134 counter = 0; 9135 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9136 if (i < 4 && j < 2) 9137 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9138 adev, disable_masks[i * 2 + j]); 9139 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9140 cu_info->bitmap[i][j] = bitmap; 9141 9142 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9143 if (bitmap & mask) { 9144 if (counter < adev->gfx.config.max_cu_per_sh) 9145 ao_bitmap |= mask; 9146 counter++; 9147 } 9148 mask <<= 1; 9149 } 9150 active_cu_number += counter; 9151 if (i < 2 && j < 2) 9152 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9153 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9154 } 9155 } 9156 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9157 mutex_unlock(&adev->grbm_idx_mutex); 9158 9159 cu_info->number = active_cu_number; 9160 cu_info->ao_cu_mask = ao_cu_mask; 9161 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9162 9163 return 0; 9164 } 9165 9166 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9167 { 9168 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9169 9170 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9171 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9172 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9173 9174 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9175 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9176 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9177 9178 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9179 adev->gfx.config.max_shader_engines); 9180 disabled_sa = efuse_setting | vbios_setting; 9181 disabled_sa &= max_sa_mask; 9182 9183 return disabled_sa; 9184 } 9185 9186 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9187 { 9188 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9189 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9190 9191 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9192 9193 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9194 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9195 max_shader_engines = adev->gfx.config.max_shader_engines; 9196 9197 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9198 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9199 disabled_sa_per_se &= max_sa_per_se_mask; 9200 if (disabled_sa_per_se == max_sa_per_se_mask) { 9201 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9202 break; 9203 } 9204 } 9205 } 9206 9207 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9208 { 9209 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9210 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9211 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9212 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9213 9214 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9215 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9216 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9217 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9218 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9219 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9220 9221 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9222 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9223 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9224 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9225 9226 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9227 9228 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9229 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9230 } 9231 9232 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9233 { 9234 .type = AMD_IP_BLOCK_TYPE_GFX, 9235 .major = 10, 9236 .minor = 0, 9237 .rev = 0, 9238 .funcs = &gfx_v10_0_ip_funcs, 9239 }; 9240