1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 377 /* SE status registers */ 378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 382 }; 383 384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 385 /* compute registers */ 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) 425 }; 426 427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 428 /* gfx queue registers */ 429 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI) 452 }; 453 454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 495 }; 496 497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 498 /* Pending on emulation bring up */ 499 }; 500 501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1554 }; 1555 1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1595 }; 1596 1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1640 }; 1641 1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1643 /* Pending on emulation bring up */ 1644 }; 1645 1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2267 }; 2268 2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2270 /* Pending on emulation bring up */ 2271 }; 2272 2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3326 }; 3327 3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3372 }; 3373 3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3375 /* Pending on emulation bring up */ 3376 }; 3377 3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3420 3421 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3423 }; 3424 3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3450 3451 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3453 }; 3454 3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3476 }; 3477 3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3515 }; 3516 3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3550 }; 3551 3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3587 }; 3588 3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3612 }; 3613 3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3637 }; 3638 3639 #define DEFAULT_SH_MEM_CONFIG \ 3640 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3641 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3642 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3643 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3644 3645 /* TODO: pending on golden setting value of gb address config */ 3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3647 3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3654 struct amdgpu_cu_info *cu_info); 3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3657 u32 sh_num, u32 instance, int xcc_id); 3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3659 3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3671 uint16_t pasid, uint32_t flush_type, 3672 bool all_hub, uint8_t dst_sel); 3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3674 unsigned int vmid); 3675 3676 static int gfx_v10_0_set_powergating_state(void *handle, 3677 enum amd_powergating_state state); 3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3679 { 3680 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3681 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3682 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3683 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3684 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3685 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3686 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3687 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3688 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3689 } 3690 3691 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3692 struct amdgpu_ring *ring) 3693 { 3694 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3695 uint64_t wptr_addr = ring->wptr_gpu_addr; 3696 uint32_t eng_sel = 0; 3697 3698 switch (ring->funcs->type) { 3699 case AMDGPU_RING_TYPE_COMPUTE: 3700 eng_sel = 0; 3701 break; 3702 case AMDGPU_RING_TYPE_GFX: 3703 eng_sel = 4; 3704 break; 3705 case AMDGPU_RING_TYPE_MES: 3706 eng_sel = 5; 3707 break; 3708 default: 3709 WARN_ON(1); 3710 } 3711 3712 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3713 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3714 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3715 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3716 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3717 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3718 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3719 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3720 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3721 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3722 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3723 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3724 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3725 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3726 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3727 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3728 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3729 } 3730 3731 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3732 struct amdgpu_ring *ring, 3733 enum amdgpu_unmap_queues_action action, 3734 u64 gpu_addr, u64 seq) 3735 { 3736 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3737 3738 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3739 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3740 PACKET3_UNMAP_QUEUES_ACTION(action) | 3741 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3742 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3743 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3744 amdgpu_ring_write(kiq_ring, 3745 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3746 3747 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3748 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3749 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3750 amdgpu_ring_write(kiq_ring, seq); 3751 } else { 3752 amdgpu_ring_write(kiq_ring, 0); 3753 amdgpu_ring_write(kiq_ring, 0); 3754 amdgpu_ring_write(kiq_ring, 0); 3755 } 3756 } 3757 3758 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3759 struct amdgpu_ring *ring, 3760 u64 addr, 3761 u64 seq) 3762 { 3763 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3764 3765 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3766 amdgpu_ring_write(kiq_ring, 3767 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3768 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3769 PACKET3_QUERY_STATUS_COMMAND(2)); 3770 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3771 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3772 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3773 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3774 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3775 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3776 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3777 } 3778 3779 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3780 uint16_t pasid, uint32_t flush_type, 3781 bool all_hub) 3782 { 3783 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3784 } 3785 3786 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3787 .kiq_set_resources = gfx10_kiq_set_resources, 3788 .kiq_map_queues = gfx10_kiq_map_queues, 3789 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3790 .kiq_query_status = gfx10_kiq_query_status, 3791 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3792 .set_resources_size = 8, 3793 .map_queues_size = 7, 3794 .unmap_queues_size = 6, 3795 .query_status_size = 7, 3796 .invalidate_tlbs_size = 2, 3797 }; 3798 3799 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3800 { 3801 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3802 } 3803 3804 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3805 { 3806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3807 case IP_VERSION(10, 1, 10): 3808 soc15_program_register_sequence(adev, 3809 golden_settings_gc_rlc_spm_10_0_nv10, 3810 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3811 break; 3812 case IP_VERSION(10, 1, 1): 3813 soc15_program_register_sequence(adev, 3814 golden_settings_gc_rlc_spm_10_1_nv14, 3815 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3816 break; 3817 case IP_VERSION(10, 1, 2): 3818 soc15_program_register_sequence(adev, 3819 golden_settings_gc_rlc_spm_10_1_2_nv12, 3820 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3821 break; 3822 default: 3823 break; 3824 } 3825 } 3826 3827 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3828 { 3829 if (amdgpu_sriov_vf(adev)) 3830 return; 3831 3832 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3833 case IP_VERSION(10, 1, 10): 3834 soc15_program_register_sequence(adev, 3835 golden_settings_gc_10_1, 3836 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3837 soc15_program_register_sequence(adev, 3838 golden_settings_gc_10_0_nv10, 3839 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3840 break; 3841 case IP_VERSION(10, 1, 1): 3842 soc15_program_register_sequence(adev, 3843 golden_settings_gc_10_1_1, 3844 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3845 soc15_program_register_sequence(adev, 3846 golden_settings_gc_10_1_nv14, 3847 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3848 break; 3849 case IP_VERSION(10, 1, 2): 3850 soc15_program_register_sequence(adev, 3851 golden_settings_gc_10_1_2, 3852 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3853 soc15_program_register_sequence(adev, 3854 golden_settings_gc_10_1_2_nv12, 3855 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3856 break; 3857 case IP_VERSION(10, 3, 0): 3858 soc15_program_register_sequence(adev, 3859 golden_settings_gc_10_3, 3860 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3861 soc15_program_register_sequence(adev, 3862 golden_settings_gc_10_3_sienna_cichlid, 3863 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3864 break; 3865 case IP_VERSION(10, 3, 2): 3866 soc15_program_register_sequence(adev, 3867 golden_settings_gc_10_3_2, 3868 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3869 break; 3870 case IP_VERSION(10, 3, 1): 3871 soc15_program_register_sequence(adev, 3872 golden_settings_gc_10_3_vangogh, 3873 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3874 break; 3875 case IP_VERSION(10, 3, 3): 3876 soc15_program_register_sequence(adev, 3877 golden_settings_gc_10_3_3, 3878 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3879 break; 3880 case IP_VERSION(10, 3, 4): 3881 soc15_program_register_sequence(adev, 3882 golden_settings_gc_10_3_4, 3883 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3884 break; 3885 case IP_VERSION(10, 3, 5): 3886 soc15_program_register_sequence(adev, 3887 golden_settings_gc_10_3_5, 3888 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3889 break; 3890 case IP_VERSION(10, 1, 3): 3891 case IP_VERSION(10, 1, 4): 3892 soc15_program_register_sequence(adev, 3893 golden_settings_gc_10_0_cyan_skillfish, 3894 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3895 break; 3896 case IP_VERSION(10, 3, 6): 3897 soc15_program_register_sequence(adev, 3898 golden_settings_gc_10_3_6, 3899 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3900 break; 3901 case IP_VERSION(10, 3, 7): 3902 soc15_program_register_sequence(adev, 3903 golden_settings_gc_10_3_7, 3904 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3905 break; 3906 default: 3907 break; 3908 } 3909 gfx_v10_0_init_spm_golden_registers(adev); 3910 } 3911 3912 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3913 bool wc, uint32_t reg, uint32_t val) 3914 { 3915 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3916 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3917 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3918 amdgpu_ring_write(ring, reg); 3919 amdgpu_ring_write(ring, 0); 3920 amdgpu_ring_write(ring, val); 3921 } 3922 3923 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3924 int mem_space, int opt, uint32_t addr0, 3925 uint32_t addr1, uint32_t ref, uint32_t mask, 3926 uint32_t inv) 3927 { 3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3929 amdgpu_ring_write(ring, 3930 /* memory (1) or register (0) */ 3931 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3932 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3933 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3934 WAIT_REG_MEM_ENGINE(eng_sel))); 3935 3936 if (mem_space) 3937 BUG_ON(addr0 & 0x3); /* Dword align */ 3938 amdgpu_ring_write(ring, addr0); 3939 amdgpu_ring_write(ring, addr1); 3940 amdgpu_ring_write(ring, ref); 3941 amdgpu_ring_write(ring, mask); 3942 amdgpu_ring_write(ring, inv); /* poll interval */ 3943 } 3944 3945 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3946 { 3947 struct amdgpu_device *adev = ring->adev; 3948 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3949 uint32_t tmp = 0; 3950 unsigned int i; 3951 int r; 3952 3953 WREG32(scratch, 0xCAFEDEAD); 3954 r = amdgpu_ring_alloc(ring, 3); 3955 if (r) { 3956 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3957 ring->idx, r); 3958 return r; 3959 } 3960 3961 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3962 amdgpu_ring_write(ring, scratch - 3963 PACKET3_SET_UCONFIG_REG_START); 3964 amdgpu_ring_write(ring, 0xDEADBEEF); 3965 amdgpu_ring_commit(ring); 3966 3967 for (i = 0; i < adev->usec_timeout; i++) { 3968 tmp = RREG32(scratch); 3969 if (tmp == 0xDEADBEEF) 3970 break; 3971 if (amdgpu_emu_mode == 1) 3972 msleep(1); 3973 else 3974 udelay(1); 3975 } 3976 3977 if (i >= adev->usec_timeout) 3978 r = -ETIMEDOUT; 3979 3980 return r; 3981 } 3982 3983 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3984 { 3985 struct amdgpu_device *adev = ring->adev; 3986 struct amdgpu_ib ib; 3987 struct dma_fence *f = NULL; 3988 unsigned int index; 3989 uint64_t gpu_addr; 3990 volatile uint32_t *cpu_ptr; 3991 long r; 3992 3993 memset(&ib, 0, sizeof(ib)); 3994 3995 r = amdgpu_device_wb_get(adev, &index); 3996 if (r) 3997 return r; 3998 3999 gpu_addr = adev->wb.gpu_addr + (index * 4); 4000 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4001 cpu_ptr = &adev->wb.wb[index]; 4002 4003 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4004 if (r) { 4005 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 4006 goto err1; 4007 } 4008 4009 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4010 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4011 ib.ptr[2] = lower_32_bits(gpu_addr); 4012 ib.ptr[3] = upper_32_bits(gpu_addr); 4013 ib.ptr[4] = 0xDEADBEEF; 4014 ib.length_dw = 5; 4015 4016 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4017 if (r) 4018 goto err2; 4019 4020 r = dma_fence_wait_timeout(f, false, timeout); 4021 if (r == 0) { 4022 r = -ETIMEDOUT; 4023 goto err2; 4024 } else if (r < 0) { 4025 goto err2; 4026 } 4027 4028 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4029 r = 0; 4030 else 4031 r = -EINVAL; 4032 err2: 4033 amdgpu_ib_free(adev, &ib, NULL); 4034 dma_fence_put(f); 4035 err1: 4036 amdgpu_device_wb_free(adev, index); 4037 return r; 4038 } 4039 4040 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4041 { 4042 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4043 amdgpu_ucode_release(&adev->gfx.me_fw); 4044 amdgpu_ucode_release(&adev->gfx.ce_fw); 4045 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4046 amdgpu_ucode_release(&adev->gfx.mec_fw); 4047 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4048 4049 kfree(adev->gfx.rlc.register_list_format); 4050 } 4051 4052 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4053 { 4054 adev->gfx.cp_fw_write_wait = false; 4055 4056 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4057 case IP_VERSION(10, 1, 10): 4058 case IP_VERSION(10, 1, 2): 4059 case IP_VERSION(10, 1, 1): 4060 case IP_VERSION(10, 1, 3): 4061 case IP_VERSION(10, 1, 4): 4062 if ((adev->gfx.me_fw_version >= 0x00000046) && 4063 (adev->gfx.me_feature_version >= 27) && 4064 (adev->gfx.pfp_fw_version >= 0x00000068) && 4065 (adev->gfx.pfp_feature_version >= 27) && 4066 (adev->gfx.mec_fw_version >= 0x0000005b) && 4067 (adev->gfx.mec_feature_version >= 27)) 4068 adev->gfx.cp_fw_write_wait = true; 4069 break; 4070 case IP_VERSION(10, 3, 0): 4071 case IP_VERSION(10, 3, 2): 4072 case IP_VERSION(10, 3, 1): 4073 case IP_VERSION(10, 3, 4): 4074 case IP_VERSION(10, 3, 5): 4075 case IP_VERSION(10, 3, 6): 4076 case IP_VERSION(10, 3, 3): 4077 case IP_VERSION(10, 3, 7): 4078 adev->gfx.cp_fw_write_wait = true; 4079 break; 4080 default: 4081 break; 4082 } 4083 4084 if (!adev->gfx.cp_fw_write_wait) 4085 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4086 } 4087 4088 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4089 { 4090 bool ret = false; 4091 4092 switch (adev->pdev->revision) { 4093 case 0xc2: 4094 case 0xc3: 4095 ret = true; 4096 break; 4097 default: 4098 ret = false; 4099 break; 4100 } 4101 4102 return ret; 4103 } 4104 4105 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4106 { 4107 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4108 case IP_VERSION(10, 1, 10): 4109 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4110 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4111 break; 4112 default: 4113 break; 4114 } 4115 } 4116 4117 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4118 { 4119 char ucode_prefix[30]; 4120 const char *wks = ""; 4121 int err; 4122 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4123 uint16_t version_major; 4124 uint16_t version_minor; 4125 4126 DRM_DEBUG("\n"); 4127 4128 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4129 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4130 wks = "_wks"; 4131 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4132 4133 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4134 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4135 if (err) 4136 goto out; 4137 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4138 4139 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4140 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4141 if (err) 4142 goto out; 4143 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4144 4145 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4146 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4147 if (err) 4148 goto out; 4149 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4150 4151 if (!amdgpu_sriov_vf(adev)) { 4152 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 4153 "amdgpu/%s_rlc.bin", ucode_prefix); 4154 if (err) 4155 goto out; 4156 4157 /* don't validate this firmware. There are apparently firmwares 4158 * in the wild with incorrect size in the header 4159 */ 4160 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4161 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4162 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4163 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4164 if (err) 4165 goto out; 4166 } 4167 4168 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4169 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4170 if (err) 4171 goto out; 4172 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4173 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4174 4175 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4176 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4177 if (!err) { 4178 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4179 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4180 } else { 4181 err = 0; 4182 adev->gfx.mec2_fw = NULL; 4183 } 4184 4185 gfx_v10_0_check_fw_write_wait(adev); 4186 out: 4187 if (err) { 4188 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4189 amdgpu_ucode_release(&adev->gfx.me_fw); 4190 amdgpu_ucode_release(&adev->gfx.ce_fw); 4191 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4192 amdgpu_ucode_release(&adev->gfx.mec_fw); 4193 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4194 } 4195 4196 gfx_v10_0_check_gfxoff_flag(adev); 4197 4198 return err; 4199 } 4200 4201 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4202 { 4203 u32 count = 0; 4204 const struct cs_section_def *sect = NULL; 4205 const struct cs_extent_def *ext = NULL; 4206 4207 /* begin clear state */ 4208 count += 2; 4209 /* context control state */ 4210 count += 3; 4211 4212 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4213 for (ext = sect->section; ext->extent != NULL; ++ext) { 4214 if (sect->id == SECT_CONTEXT) 4215 count += 2 + ext->reg_count; 4216 else 4217 return 0; 4218 } 4219 } 4220 4221 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4222 count += 3; 4223 /* end clear state */ 4224 count += 2; 4225 /* clear state */ 4226 count += 2; 4227 4228 return count; 4229 } 4230 4231 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4232 volatile u32 *buffer) 4233 { 4234 u32 count = 0, i; 4235 const struct cs_section_def *sect = NULL; 4236 const struct cs_extent_def *ext = NULL; 4237 int ctx_reg_offset; 4238 4239 if (adev->gfx.rlc.cs_data == NULL) 4240 return; 4241 if (buffer == NULL) 4242 return; 4243 4244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4245 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4246 4247 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4248 buffer[count++] = cpu_to_le32(0x80000000); 4249 buffer[count++] = cpu_to_le32(0x80000000); 4250 4251 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4252 for (ext = sect->section; ext->extent != NULL; ++ext) { 4253 if (sect->id == SECT_CONTEXT) { 4254 buffer[count++] = 4255 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4256 buffer[count++] = cpu_to_le32(ext->reg_index - 4257 PACKET3_SET_CONTEXT_REG_START); 4258 for (i = 0; i < ext->reg_count; i++) 4259 buffer[count++] = cpu_to_le32(ext->extent[i]); 4260 } else { 4261 return; 4262 } 4263 } 4264 } 4265 4266 ctx_reg_offset = 4267 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4268 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4269 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4270 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4271 4272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4273 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4274 4275 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4276 buffer[count++] = cpu_to_le32(0); 4277 } 4278 4279 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4280 { 4281 /* clear state block */ 4282 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4283 &adev->gfx.rlc.clear_state_gpu_addr, 4284 (void **)&adev->gfx.rlc.cs_ptr); 4285 4286 /* jump table block */ 4287 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4288 &adev->gfx.rlc.cp_table_gpu_addr, 4289 (void **)&adev->gfx.rlc.cp_table_ptr); 4290 } 4291 4292 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4293 { 4294 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4295 4296 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4297 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4298 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4299 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4300 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4301 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4302 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4303 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4304 case IP_VERSION(10, 3, 0): 4305 reg_access_ctrl->spare_int = 4306 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4307 break; 4308 default: 4309 reg_access_ctrl->spare_int = 4310 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4311 break; 4312 } 4313 adev->gfx.rlc.rlcg_reg_access_supported = true; 4314 } 4315 4316 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4317 { 4318 const struct cs_section_def *cs_data; 4319 int r; 4320 4321 adev->gfx.rlc.cs_data = gfx10_cs_data; 4322 4323 cs_data = adev->gfx.rlc.cs_data; 4324 4325 if (cs_data) { 4326 /* init clear state block */ 4327 r = amdgpu_gfx_rlc_init_csb(adev); 4328 if (r) 4329 return r; 4330 } 4331 4332 return 0; 4333 } 4334 4335 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4336 { 4337 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4338 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4339 } 4340 4341 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4342 { 4343 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4344 4345 amdgpu_gfx_graphics_queue_acquire(adev); 4346 } 4347 4348 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4349 { 4350 int r; 4351 u32 *hpd; 4352 const __le32 *fw_data = NULL; 4353 unsigned int fw_size; 4354 u32 *fw = NULL; 4355 size_t mec_hpd_size; 4356 4357 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4358 4359 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4360 4361 /* take ownership of the relevant compute queues */ 4362 amdgpu_gfx_compute_queue_acquire(adev); 4363 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4364 4365 if (mec_hpd_size) { 4366 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4367 AMDGPU_GEM_DOMAIN_GTT, 4368 &adev->gfx.mec.hpd_eop_obj, 4369 &adev->gfx.mec.hpd_eop_gpu_addr, 4370 (void **)&hpd); 4371 if (r) { 4372 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4373 gfx_v10_0_mec_fini(adev); 4374 return r; 4375 } 4376 4377 memset(hpd, 0, mec_hpd_size); 4378 4379 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4380 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4381 } 4382 4383 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4384 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4385 4386 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4387 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4388 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4389 4390 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4391 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4392 &adev->gfx.mec.mec_fw_obj, 4393 &adev->gfx.mec.mec_fw_gpu_addr, 4394 (void **)&fw); 4395 if (r) { 4396 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4397 gfx_v10_0_mec_fini(adev); 4398 return r; 4399 } 4400 4401 memcpy(fw, fw_data, fw_size); 4402 4403 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4404 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4405 } 4406 4407 return 0; 4408 } 4409 4410 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4411 { 4412 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4413 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4414 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4415 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4416 } 4417 4418 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4419 uint32_t thread, uint32_t regno, 4420 uint32_t num, uint32_t *out) 4421 { 4422 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4423 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4424 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4425 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4426 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4427 while (num--) 4428 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4429 } 4430 4431 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4432 { 4433 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4434 * field when performing a select_se_sh so it should be 4435 * zero here 4436 */ 4437 WARN_ON(simd != 0); 4438 4439 /* type 2 wave data */ 4440 dst[(*no_fields)++] = 2; 4441 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4442 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4443 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4444 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4445 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4446 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4447 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4448 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4449 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4450 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4451 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4452 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4453 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4454 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4455 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4457 } 4458 4459 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4460 uint32_t wave, uint32_t start, 4461 uint32_t size, uint32_t *dst) 4462 { 4463 WARN_ON(simd != 0); 4464 4465 wave_read_regs( 4466 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4467 dst); 4468 } 4469 4470 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4471 uint32_t wave, uint32_t thread, 4472 uint32_t start, uint32_t size, 4473 uint32_t *dst) 4474 { 4475 wave_read_regs( 4476 adev, wave, thread, 4477 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4478 } 4479 4480 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4481 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4482 { 4483 nv_grbm_select(adev, me, pipe, q, vm); 4484 } 4485 4486 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4487 bool enable) 4488 { 4489 uint32_t data, def; 4490 4491 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4492 4493 if (enable) 4494 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4495 else 4496 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4497 4498 if (data != def) 4499 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4500 } 4501 4502 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4503 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4504 .select_se_sh = &gfx_v10_0_select_se_sh, 4505 .read_wave_data = &gfx_v10_0_read_wave_data, 4506 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4507 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4508 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4509 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4510 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4511 }; 4512 4513 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4514 { 4515 u32 gb_addr_config; 4516 4517 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4518 case IP_VERSION(10, 1, 10): 4519 case IP_VERSION(10, 1, 1): 4520 case IP_VERSION(10, 1, 2): 4521 adev->gfx.config.max_hw_contexts = 8; 4522 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4523 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4524 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4525 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4526 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4527 break; 4528 case IP_VERSION(10, 3, 0): 4529 case IP_VERSION(10, 3, 2): 4530 case IP_VERSION(10, 3, 1): 4531 case IP_VERSION(10, 3, 4): 4532 case IP_VERSION(10, 3, 5): 4533 case IP_VERSION(10, 3, 6): 4534 case IP_VERSION(10, 3, 3): 4535 case IP_VERSION(10, 3, 7): 4536 adev->gfx.config.max_hw_contexts = 8; 4537 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4538 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4539 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4540 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4541 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4542 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4543 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4544 break; 4545 case IP_VERSION(10, 1, 3): 4546 case IP_VERSION(10, 1, 4): 4547 adev->gfx.config.max_hw_contexts = 8; 4548 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4549 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4550 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4551 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4552 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4553 break; 4554 default: 4555 BUG(); 4556 break; 4557 } 4558 4559 adev->gfx.config.gb_addr_config = gb_addr_config; 4560 4561 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4562 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4563 GB_ADDR_CONFIG, NUM_PIPES); 4564 4565 adev->gfx.config.max_tile_pipes = 4566 adev->gfx.config.gb_addr_config_fields.num_pipes; 4567 4568 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4569 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4570 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4571 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4572 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4573 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4574 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4575 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4576 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4577 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4578 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4579 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4580 } 4581 4582 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4583 int me, int pipe, int queue) 4584 { 4585 struct amdgpu_ring *ring; 4586 unsigned int irq_type; 4587 unsigned int hw_prio; 4588 4589 ring = &adev->gfx.gfx_ring[ring_id]; 4590 4591 ring->me = me; 4592 ring->pipe = pipe; 4593 ring->queue = queue; 4594 4595 ring->ring_obj = NULL; 4596 ring->use_doorbell = true; 4597 4598 if (!ring_id) 4599 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4600 else 4601 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4602 ring->vm_hub = AMDGPU_GFXHUB(0); 4603 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4604 4605 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4606 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4607 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4608 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4609 hw_prio, NULL); 4610 } 4611 4612 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4613 int mec, int pipe, int queue) 4614 { 4615 unsigned int irq_type; 4616 struct amdgpu_ring *ring; 4617 unsigned int hw_prio; 4618 4619 ring = &adev->gfx.compute_ring[ring_id]; 4620 4621 /* mec0 is me1 */ 4622 ring->me = mec + 1; 4623 ring->pipe = pipe; 4624 ring->queue = queue; 4625 4626 ring->ring_obj = NULL; 4627 ring->use_doorbell = true; 4628 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4629 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4630 + (ring_id * GFX10_MEC_HPD_SIZE); 4631 ring->vm_hub = AMDGPU_GFXHUB(0); 4632 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4633 4634 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4635 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4636 + ring->pipe; 4637 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4638 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4639 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4640 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4641 hw_prio, NULL); 4642 } 4643 4644 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4645 { 4646 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4647 uint32_t *ptr; 4648 uint32_t inst; 4649 4650 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4651 if (ptr == NULL) { 4652 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4653 adev->gfx.ip_dump_core = NULL; 4654 } else { 4655 adev->gfx.ip_dump_core = ptr; 4656 } 4657 4658 /* Allocate memory for compute queue registers for all the instances */ 4659 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4660 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4661 adev->gfx.mec.num_queue_per_pipe; 4662 4663 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4664 if (ptr == NULL) { 4665 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4666 adev->gfx.ip_dump_compute_queues = NULL; 4667 } else { 4668 adev->gfx.ip_dump_compute_queues = ptr; 4669 } 4670 4671 /* Allocate memory for gfx queue registers for all the instances */ 4672 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4673 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4674 adev->gfx.me.num_queue_per_pipe; 4675 4676 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4677 if (ptr == NULL) { 4678 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4679 adev->gfx.ip_dump_gfx_queues = NULL; 4680 } else { 4681 adev->gfx.ip_dump_gfx_queues = ptr; 4682 } 4683 } 4684 4685 static int gfx_v10_0_sw_init(void *handle) 4686 { 4687 int i, j, k, r, ring_id = 0; 4688 int xcc_id = 0; 4689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4690 4691 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4692 case IP_VERSION(10, 1, 10): 4693 case IP_VERSION(10, 1, 1): 4694 case IP_VERSION(10, 1, 2): 4695 case IP_VERSION(10, 1, 3): 4696 case IP_VERSION(10, 1, 4): 4697 adev->gfx.me.num_me = 1; 4698 adev->gfx.me.num_pipe_per_me = 1; 4699 adev->gfx.me.num_queue_per_pipe = 1; 4700 adev->gfx.mec.num_mec = 2; 4701 adev->gfx.mec.num_pipe_per_mec = 4; 4702 adev->gfx.mec.num_queue_per_pipe = 8; 4703 break; 4704 case IP_VERSION(10, 3, 0): 4705 case IP_VERSION(10, 3, 2): 4706 case IP_VERSION(10, 3, 1): 4707 case IP_VERSION(10, 3, 4): 4708 case IP_VERSION(10, 3, 5): 4709 case IP_VERSION(10, 3, 6): 4710 case IP_VERSION(10, 3, 3): 4711 case IP_VERSION(10, 3, 7): 4712 adev->gfx.me.num_me = 1; 4713 adev->gfx.me.num_pipe_per_me = 2; 4714 adev->gfx.me.num_queue_per_pipe = 1; 4715 adev->gfx.mec.num_mec = 2; 4716 adev->gfx.mec.num_pipe_per_mec = 4; 4717 adev->gfx.mec.num_queue_per_pipe = 4; 4718 break; 4719 default: 4720 adev->gfx.me.num_me = 1; 4721 adev->gfx.me.num_pipe_per_me = 1; 4722 adev->gfx.me.num_queue_per_pipe = 1; 4723 adev->gfx.mec.num_mec = 1; 4724 adev->gfx.mec.num_pipe_per_mec = 4; 4725 adev->gfx.mec.num_queue_per_pipe = 8; 4726 break; 4727 } 4728 4729 /* KIQ event */ 4730 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4731 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4732 &adev->gfx.kiq[0].irq); 4733 if (r) 4734 return r; 4735 4736 /* EOP Event */ 4737 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4738 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4739 &adev->gfx.eop_irq); 4740 if (r) 4741 return r; 4742 4743 /* Bad opcode Event */ 4744 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4745 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4746 &adev->gfx.bad_op_irq); 4747 if (r) 4748 return r; 4749 4750 /* Privileged reg */ 4751 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4752 &adev->gfx.priv_reg_irq); 4753 if (r) 4754 return r; 4755 4756 /* Privileged inst */ 4757 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4758 &adev->gfx.priv_inst_irq); 4759 if (r) 4760 return r; 4761 4762 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4763 4764 gfx_v10_0_me_init(adev); 4765 4766 if (adev->gfx.rlc.funcs) { 4767 if (adev->gfx.rlc.funcs->init) { 4768 r = adev->gfx.rlc.funcs->init(adev); 4769 if (r) { 4770 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4771 return r; 4772 } 4773 } 4774 } 4775 4776 r = gfx_v10_0_mec_init(adev); 4777 if (r) { 4778 DRM_ERROR("Failed to init MEC BOs!\n"); 4779 return r; 4780 } 4781 4782 /* set up the gfx ring */ 4783 for (i = 0; i < adev->gfx.me.num_me; i++) { 4784 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4785 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4786 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4787 continue; 4788 4789 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4790 i, k, j); 4791 if (r) 4792 return r; 4793 ring_id++; 4794 } 4795 } 4796 } 4797 4798 ring_id = 0; 4799 /* set up the compute queues - allocate horizontally across pipes */ 4800 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4801 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4802 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4803 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4804 k, j)) 4805 continue; 4806 4807 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4808 i, k, j); 4809 if (r) 4810 return r; 4811 4812 ring_id++; 4813 } 4814 } 4815 } 4816 4817 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4818 if (r) { 4819 DRM_ERROR("Failed to init KIQ BOs!\n"); 4820 return r; 4821 } 4822 4823 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4824 if (r) 4825 return r; 4826 4827 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4828 if (r) 4829 return r; 4830 4831 /* allocate visible FB for rlc auto-loading fw */ 4832 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4833 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4834 if (r) 4835 return r; 4836 } 4837 4838 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4839 4840 gfx_v10_0_gpu_early_init(adev); 4841 4842 gfx_v10_0_alloc_ip_dump(adev); 4843 4844 return 0; 4845 } 4846 4847 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4848 { 4849 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4850 &adev->gfx.pfp.pfp_fw_gpu_addr, 4851 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4852 } 4853 4854 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4855 { 4856 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4857 &adev->gfx.ce.ce_fw_gpu_addr, 4858 (void **)&adev->gfx.ce.ce_fw_ptr); 4859 } 4860 4861 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4862 { 4863 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4864 &adev->gfx.me.me_fw_gpu_addr, 4865 (void **)&adev->gfx.me.me_fw_ptr); 4866 } 4867 4868 static int gfx_v10_0_sw_fini(void *handle) 4869 { 4870 int i; 4871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4872 4873 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4874 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4875 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4876 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4877 4878 amdgpu_gfx_mqd_sw_fini(adev, 0); 4879 4880 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4881 amdgpu_gfx_kiq_fini(adev, 0); 4882 4883 gfx_v10_0_pfp_fini(adev); 4884 gfx_v10_0_ce_fini(adev); 4885 gfx_v10_0_me_fini(adev); 4886 gfx_v10_0_rlc_fini(adev); 4887 gfx_v10_0_mec_fini(adev); 4888 4889 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4890 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4891 4892 gfx_v10_0_free_microcode(adev); 4893 4894 kfree(adev->gfx.ip_dump_core); 4895 kfree(adev->gfx.ip_dump_compute_queues); 4896 kfree(adev->gfx.ip_dump_gfx_queues); 4897 4898 return 0; 4899 } 4900 4901 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4902 u32 sh_num, u32 instance, int xcc_id) 4903 { 4904 u32 data; 4905 4906 if (instance == 0xffffffff) 4907 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4908 INSTANCE_BROADCAST_WRITES, 1); 4909 else 4910 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4911 instance); 4912 4913 if (se_num == 0xffffffff) 4914 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4915 1); 4916 else 4917 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4918 4919 if (sh_num == 0xffffffff) 4920 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4921 1); 4922 else 4923 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4924 4925 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4926 } 4927 4928 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4929 { 4930 u32 data, mask; 4931 4932 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4933 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4934 4935 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4936 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4937 4938 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4939 adev->gfx.config.max_sh_per_se); 4940 4941 return (~data) & mask; 4942 } 4943 4944 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4945 { 4946 int i, j; 4947 u32 data; 4948 u32 active_rbs = 0; 4949 u32 bitmap; 4950 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4951 adev->gfx.config.max_sh_per_se; 4952 4953 mutex_lock(&adev->grbm_idx_mutex); 4954 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4955 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4956 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4957 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4958 IP_VERSION(10, 3, 0)) || 4959 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4960 IP_VERSION(10, 3, 3)) || 4961 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4962 IP_VERSION(10, 3, 6))) && 4963 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4964 continue; 4965 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4966 data = gfx_v10_0_get_rb_active_bitmap(adev); 4967 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4968 rb_bitmap_width_per_sh); 4969 } 4970 } 4971 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4972 mutex_unlock(&adev->grbm_idx_mutex); 4973 4974 adev->gfx.config.backend_enable_mask = active_rbs; 4975 adev->gfx.config.num_rbs = hweight32(active_rbs); 4976 } 4977 4978 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4979 { 4980 uint32_t num_sc; 4981 uint32_t enabled_rb_per_sh; 4982 uint32_t active_rb_bitmap; 4983 uint32_t num_rb_per_sc; 4984 uint32_t num_packer_per_sc; 4985 uint32_t pa_sc_tile_steering_override; 4986 4987 /* for ASICs that integrates GFX v10.3 4988 * pa_sc_tile_steering_override should be set to 0 4989 */ 4990 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 4991 return 0; 4992 4993 /* init num_sc */ 4994 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4995 adev->gfx.config.num_sc_per_sh; 4996 /* init num_rb_per_sc */ 4997 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4998 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4999 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5000 /* init num_packer_per_sc */ 5001 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5002 5003 pa_sc_tile_steering_override = 0; 5004 pa_sc_tile_steering_override |= 5005 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5006 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5007 pa_sc_tile_steering_override |= 5008 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5009 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5010 pa_sc_tile_steering_override |= 5011 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5012 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5013 5014 return pa_sc_tile_steering_override; 5015 } 5016 5017 #define DEFAULT_SH_MEM_BASES (0x6000) 5018 5019 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5020 uint32_t first_vmid, 5021 uint32_t last_vmid) 5022 { 5023 uint32_t data; 5024 uint32_t trap_config_vmid_mask = 0; 5025 int i; 5026 5027 /* Calculate trap config vmid mask */ 5028 for (i = first_vmid; i < last_vmid; i++) 5029 trap_config_vmid_mask |= (1 << i); 5030 5031 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5032 VMID_SEL, trap_config_vmid_mask); 5033 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5034 TRAP_EN, 1); 5035 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5036 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5037 5038 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5039 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5040 } 5041 5042 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5043 { 5044 int i; 5045 uint32_t sh_mem_bases; 5046 5047 /* 5048 * Configure apertures: 5049 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5050 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5051 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5052 */ 5053 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5054 5055 mutex_lock(&adev->srbm_mutex); 5056 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5057 nv_grbm_select(adev, 0, 0, 0, i); 5058 /* CP and shaders */ 5059 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5060 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5061 } 5062 nv_grbm_select(adev, 0, 0, 0, 0); 5063 mutex_unlock(&adev->srbm_mutex); 5064 5065 /* 5066 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5067 * access. These should be enabled by FW for target VMIDs. 5068 */ 5069 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5070 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5071 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5072 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5073 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5074 } 5075 5076 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5077 AMDGPU_NUM_VMID); 5078 } 5079 5080 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5081 { 5082 int vmid; 5083 5084 /* 5085 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5086 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5087 * the driver can enable them for graphics. VMID0 should maintain 5088 * access so that HWS firmware can save/restore entries. 5089 */ 5090 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5091 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5092 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5093 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5094 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5095 } 5096 } 5097 5098 5099 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5100 { 5101 int i, j, k; 5102 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5103 u32 tmp, wgp_active_bitmap = 0; 5104 u32 gcrd_targets_disable_tcp = 0; 5105 u32 utcl_invreq_disable = 0; 5106 /* 5107 * GCRD_TARGETS_DISABLE field contains 5108 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5109 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5110 */ 5111 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5112 2 * max_wgp_per_sh + /* TCP */ 5113 max_wgp_per_sh + /* SQC */ 5114 4); /* GL1C */ 5115 /* 5116 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5117 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5118 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5119 */ 5120 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5121 2 * max_wgp_per_sh + /* TCP */ 5122 2 * max_wgp_per_sh + /* SQC */ 5123 4 + /* RMI */ 5124 1); /* SQG */ 5125 5126 mutex_lock(&adev->grbm_idx_mutex); 5127 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5128 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5129 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5130 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5131 /* 5132 * Set corresponding TCP bits for the inactive WGPs in 5133 * GCRD_SA_TARGETS_DISABLE 5134 */ 5135 gcrd_targets_disable_tcp = 0; 5136 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5137 utcl_invreq_disable = 0; 5138 5139 for (k = 0; k < max_wgp_per_sh; k++) { 5140 if (!(wgp_active_bitmap & (1 << k))) { 5141 gcrd_targets_disable_tcp |= 3 << (2 * k); 5142 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5143 utcl_invreq_disable |= (3 << (2 * k)) | 5144 (3 << (2 * (max_wgp_per_sh + k))); 5145 } 5146 } 5147 5148 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5149 /* only override TCP & SQC bits */ 5150 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5151 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5152 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5153 5154 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5155 /* only override TCP & SQC bits */ 5156 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5157 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5158 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5159 } 5160 } 5161 5162 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5163 mutex_unlock(&adev->grbm_idx_mutex); 5164 } 5165 5166 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5167 { 5168 /* TCCs are global (not instanced). */ 5169 uint32_t tcc_disable; 5170 5171 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5172 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5173 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5174 } else { 5175 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5176 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5177 } 5178 5179 adev->gfx.config.tcc_disabled_mask = 5180 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5181 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5182 } 5183 5184 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5185 { 5186 u32 tmp; 5187 int i; 5188 5189 if (!amdgpu_sriov_vf(adev)) 5190 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5191 5192 gfx_v10_0_setup_rb(adev); 5193 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5194 gfx_v10_0_get_tcc_info(adev); 5195 adev->gfx.config.pa_sc_tile_steering_override = 5196 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5197 5198 /* XXX SH_MEM regs */ 5199 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5200 mutex_lock(&adev->srbm_mutex); 5201 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5202 nv_grbm_select(adev, 0, 0, 0, i); 5203 /* CP and shaders */ 5204 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5205 if (i != 0) { 5206 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5207 (adev->gmc.private_aperture_start >> 48)); 5208 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5209 (adev->gmc.shared_aperture_start >> 48)); 5210 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5211 } 5212 } 5213 nv_grbm_select(adev, 0, 0, 0, 0); 5214 5215 mutex_unlock(&adev->srbm_mutex); 5216 5217 gfx_v10_0_init_compute_vmid(adev); 5218 gfx_v10_0_init_gds_vmid(adev); 5219 5220 } 5221 5222 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5223 int me, int pipe) 5224 { 5225 if (me != 0) 5226 return 0; 5227 5228 switch (pipe) { 5229 case 0: 5230 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5231 case 1: 5232 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5233 default: 5234 return 0; 5235 } 5236 } 5237 5238 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5239 int me, int pipe) 5240 { 5241 /* 5242 * amdgpu controls only the first MEC. That's why this function only 5243 * handles the setting of interrupts for this specific MEC. All other 5244 * pipes' interrupts are set by amdkfd. 5245 */ 5246 if (me != 1) 5247 return 0; 5248 5249 switch (pipe) { 5250 case 0: 5251 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5252 case 1: 5253 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5254 case 2: 5255 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5256 case 3: 5257 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5258 default: 5259 return 0; 5260 } 5261 } 5262 5263 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5264 bool enable) 5265 { 5266 u32 tmp, cp_int_cntl_reg; 5267 int i, j; 5268 5269 if (amdgpu_sriov_vf(adev)) 5270 return; 5271 5272 for (i = 0; i < adev->gfx.me.num_me; i++) { 5273 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5274 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5275 5276 if (cp_int_cntl_reg) { 5277 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5278 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5279 enable ? 1 : 0); 5280 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5281 enable ? 1 : 0); 5282 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5283 enable ? 1 : 0); 5284 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5285 enable ? 1 : 0); 5286 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5287 } 5288 } 5289 } 5290 } 5291 5292 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5293 { 5294 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5295 5296 /* csib */ 5297 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5298 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5299 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5300 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5301 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5302 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5303 } else { 5304 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5305 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5306 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5307 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5308 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5309 } 5310 return 0; 5311 } 5312 5313 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5314 { 5315 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5316 5317 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5318 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5319 } 5320 5321 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5322 { 5323 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5324 udelay(50); 5325 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5326 udelay(50); 5327 } 5328 5329 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5330 bool enable) 5331 { 5332 uint32_t rlc_pg_cntl; 5333 5334 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5335 5336 if (!enable) { 5337 /* RLC_PG_CNTL[23] = 0 (default) 5338 * RLC will wait for handshake acks with SMU 5339 * GFXOFF will be enabled 5340 * RLC_PG_CNTL[23] = 1 5341 * RLC will not issue any message to SMU 5342 * hence no handshake between SMU & RLC 5343 * GFXOFF will be disabled 5344 */ 5345 rlc_pg_cntl |= 0x800000; 5346 } else 5347 rlc_pg_cntl &= ~0x800000; 5348 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5349 } 5350 5351 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5352 { 5353 /* 5354 * TODO: enable rlc & smu handshake until smu 5355 * and gfxoff feature works as expected 5356 */ 5357 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5358 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5359 5360 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5361 udelay(50); 5362 } 5363 5364 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5365 { 5366 uint32_t tmp; 5367 5368 /* enable Save Restore Machine */ 5369 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5370 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5371 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5372 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5373 } 5374 5375 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5376 { 5377 const struct rlc_firmware_header_v2_0 *hdr; 5378 const __le32 *fw_data; 5379 unsigned int i, fw_size; 5380 5381 if (!adev->gfx.rlc_fw) 5382 return -EINVAL; 5383 5384 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5385 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5386 5387 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5388 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5389 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5390 5391 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5392 RLCG_UCODE_LOADING_START_ADDRESS); 5393 5394 for (i = 0; i < fw_size; i++) 5395 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5396 le32_to_cpup(fw_data++)); 5397 5398 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5399 5400 return 0; 5401 } 5402 5403 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5404 { 5405 int r; 5406 5407 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5408 adev->psp.autoload_supported) { 5409 5410 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5411 if (r) 5412 return r; 5413 5414 gfx_v10_0_init_csb(adev); 5415 5416 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5417 5418 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5419 gfx_v10_0_rlc_enable_srm(adev); 5420 } else { 5421 if (amdgpu_sriov_vf(adev)) { 5422 gfx_v10_0_init_csb(adev); 5423 return 0; 5424 } 5425 5426 adev->gfx.rlc.funcs->stop(adev); 5427 5428 /* disable CG */ 5429 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5430 5431 /* disable PG */ 5432 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5433 5434 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5435 /* legacy rlc firmware loading */ 5436 r = gfx_v10_0_rlc_load_microcode(adev); 5437 if (r) 5438 return r; 5439 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5440 /* rlc backdoor autoload firmware */ 5441 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5442 if (r) 5443 return r; 5444 } 5445 5446 gfx_v10_0_init_csb(adev); 5447 5448 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5449 5450 adev->gfx.rlc.funcs->start(adev); 5451 5452 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5453 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5454 if (r) 5455 return r; 5456 } 5457 } 5458 5459 return 0; 5460 } 5461 5462 static struct { 5463 FIRMWARE_ID id; 5464 unsigned int offset; 5465 unsigned int size; 5466 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5467 5468 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5469 { 5470 int ret; 5471 RLC_TABLE_OF_CONTENT *rlc_toc; 5472 5473 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5474 AMDGPU_GEM_DOMAIN_GTT, 5475 &adev->gfx.rlc.rlc_toc_bo, 5476 &adev->gfx.rlc.rlc_toc_gpu_addr, 5477 (void **)&adev->gfx.rlc.rlc_toc_buf); 5478 if (ret) { 5479 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5480 return ret; 5481 } 5482 5483 /* Copy toc from psp sos fw to rlc toc buffer */ 5484 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5485 5486 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5487 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5488 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5489 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5490 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5491 /* Offset needs 4KB alignment */ 5492 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5493 } 5494 5495 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5496 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5497 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5498 5499 rlc_toc++; 5500 } 5501 5502 return 0; 5503 } 5504 5505 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5506 { 5507 uint32_t total_size = 0; 5508 FIRMWARE_ID id; 5509 int ret; 5510 5511 ret = gfx_v10_0_parse_rlc_toc(adev); 5512 if (ret) { 5513 dev_err(adev->dev, "failed to parse rlc toc\n"); 5514 return 0; 5515 } 5516 5517 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5518 total_size += rlc_autoload_info[id].size; 5519 5520 /* In case the offset in rlc toc ucode is aligned */ 5521 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5522 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5523 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5524 5525 return total_size; 5526 } 5527 5528 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5529 { 5530 int r; 5531 uint32_t total_size; 5532 5533 total_size = gfx_v10_0_calc_toc_total_size(adev); 5534 5535 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5536 AMDGPU_GEM_DOMAIN_GTT, 5537 &adev->gfx.rlc.rlc_autoload_bo, 5538 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5539 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5540 if (r) { 5541 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5542 return r; 5543 } 5544 5545 return 0; 5546 } 5547 5548 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5549 { 5550 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5551 &adev->gfx.rlc.rlc_toc_gpu_addr, 5552 (void **)&adev->gfx.rlc.rlc_toc_buf); 5553 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5554 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5555 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5556 } 5557 5558 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5559 FIRMWARE_ID id, 5560 const void *fw_data, 5561 uint32_t fw_size) 5562 { 5563 uint32_t toc_offset; 5564 uint32_t toc_fw_size; 5565 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5566 5567 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5568 return; 5569 5570 toc_offset = rlc_autoload_info[id].offset; 5571 toc_fw_size = rlc_autoload_info[id].size; 5572 5573 if (fw_size == 0) 5574 fw_size = toc_fw_size; 5575 5576 if (fw_size > toc_fw_size) 5577 fw_size = toc_fw_size; 5578 5579 memcpy(ptr + toc_offset, fw_data, fw_size); 5580 5581 if (fw_size < toc_fw_size) 5582 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5583 } 5584 5585 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5586 { 5587 void *data; 5588 uint32_t size; 5589 5590 data = adev->gfx.rlc.rlc_toc_buf; 5591 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5592 5593 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5594 FIRMWARE_ID_RLC_TOC, 5595 data, size); 5596 } 5597 5598 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5599 { 5600 const __le32 *fw_data; 5601 uint32_t fw_size; 5602 const struct gfx_firmware_header_v1_0 *cp_hdr; 5603 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5604 5605 /* pfp ucode */ 5606 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5607 adev->gfx.pfp_fw->data; 5608 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5609 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5610 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5611 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5612 FIRMWARE_ID_CP_PFP, 5613 fw_data, fw_size); 5614 5615 /* ce ucode */ 5616 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5617 adev->gfx.ce_fw->data; 5618 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5619 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5620 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5621 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5622 FIRMWARE_ID_CP_CE, 5623 fw_data, fw_size); 5624 5625 /* me ucode */ 5626 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5627 adev->gfx.me_fw->data; 5628 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5629 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5630 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5631 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5632 FIRMWARE_ID_CP_ME, 5633 fw_data, fw_size); 5634 5635 /* rlc ucode */ 5636 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5637 adev->gfx.rlc_fw->data; 5638 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5639 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5640 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5641 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5642 FIRMWARE_ID_RLC_G_UCODE, 5643 fw_data, fw_size); 5644 5645 /* mec1 ucode */ 5646 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5647 adev->gfx.mec_fw->data; 5648 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5649 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5650 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5651 cp_hdr->jt_size * 4; 5652 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5653 FIRMWARE_ID_CP_MEC, 5654 fw_data, fw_size); 5655 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5656 } 5657 5658 /* Temporarily put sdma part here */ 5659 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5660 { 5661 const __le32 *fw_data; 5662 uint32_t fw_size; 5663 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5664 int i; 5665 5666 for (i = 0; i < adev->sdma.num_instances; i++) { 5667 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5668 adev->sdma.instance[i].fw->data; 5669 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5670 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5671 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5672 5673 if (i == 0) { 5674 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5675 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5676 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5677 FIRMWARE_ID_SDMA0_JT, 5678 (uint32_t *)fw_data + 5679 sdma_hdr->jt_offset, 5680 sdma_hdr->jt_size * 4); 5681 } else if (i == 1) { 5682 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5683 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5684 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5685 FIRMWARE_ID_SDMA1_JT, 5686 (uint32_t *)fw_data + 5687 sdma_hdr->jt_offset, 5688 sdma_hdr->jt_size * 4); 5689 } 5690 } 5691 } 5692 5693 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5694 { 5695 uint32_t rlc_g_offset, rlc_g_size, tmp; 5696 uint64_t gpu_addr; 5697 5698 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5699 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5700 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5701 5702 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5703 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5704 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5705 5706 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5707 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5708 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5709 5710 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5711 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5712 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5713 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5714 return -EINVAL; 5715 } 5716 5717 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5718 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5719 DRM_ERROR("RLC ROM should halt itself\n"); 5720 return -EINVAL; 5721 } 5722 5723 return 0; 5724 } 5725 5726 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5727 { 5728 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5729 uint32_t tmp; 5730 int i; 5731 uint64_t addr; 5732 5733 /* Trigger an invalidation of the L1 instruction caches */ 5734 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5735 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5736 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5737 5738 /* Wait for invalidation complete */ 5739 for (i = 0; i < usec_timeout; i++) { 5740 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5741 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5742 INVALIDATE_CACHE_COMPLETE)) 5743 break; 5744 udelay(1); 5745 } 5746 5747 if (i >= usec_timeout) { 5748 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5749 return -EINVAL; 5750 } 5751 5752 /* Program me ucode address into intruction cache address register */ 5753 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5754 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5755 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5756 lower_32_bits(addr) & 0xFFFFF000); 5757 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5758 upper_32_bits(addr)); 5759 5760 return 0; 5761 } 5762 5763 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5764 { 5765 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5766 uint32_t tmp; 5767 int i; 5768 uint64_t addr; 5769 5770 /* Trigger an invalidation of the L1 instruction caches */ 5771 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5772 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5773 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5774 5775 /* Wait for invalidation complete */ 5776 for (i = 0; i < usec_timeout; i++) { 5777 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5778 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5779 INVALIDATE_CACHE_COMPLETE)) 5780 break; 5781 udelay(1); 5782 } 5783 5784 if (i >= usec_timeout) { 5785 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5786 return -EINVAL; 5787 } 5788 5789 /* Program ce ucode address into intruction cache address register */ 5790 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5791 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5792 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5793 lower_32_bits(addr) & 0xFFFFF000); 5794 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5795 upper_32_bits(addr)); 5796 5797 return 0; 5798 } 5799 5800 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5801 { 5802 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5803 uint32_t tmp; 5804 int i; 5805 uint64_t addr; 5806 5807 /* Trigger an invalidation of the L1 instruction caches */ 5808 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5809 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5810 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5811 5812 /* Wait for invalidation complete */ 5813 for (i = 0; i < usec_timeout; i++) { 5814 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5815 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5816 INVALIDATE_CACHE_COMPLETE)) 5817 break; 5818 udelay(1); 5819 } 5820 5821 if (i >= usec_timeout) { 5822 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5823 return -EINVAL; 5824 } 5825 5826 /* Program pfp ucode address into intruction cache address register */ 5827 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5828 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5829 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5830 lower_32_bits(addr) & 0xFFFFF000); 5831 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5832 upper_32_bits(addr)); 5833 5834 return 0; 5835 } 5836 5837 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5838 { 5839 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5840 uint32_t tmp; 5841 int i; 5842 uint64_t addr; 5843 5844 /* Trigger an invalidation of the L1 instruction caches */ 5845 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5846 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5847 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5848 5849 /* Wait for invalidation complete */ 5850 for (i = 0; i < usec_timeout; i++) { 5851 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5852 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5853 INVALIDATE_CACHE_COMPLETE)) 5854 break; 5855 udelay(1); 5856 } 5857 5858 if (i >= usec_timeout) { 5859 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5860 return -EINVAL; 5861 } 5862 5863 /* Program mec1 ucode address into intruction cache address register */ 5864 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5865 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5866 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5867 lower_32_bits(addr) & 0xFFFFF000); 5868 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5869 upper_32_bits(addr)); 5870 5871 return 0; 5872 } 5873 5874 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5875 { 5876 uint32_t cp_status; 5877 uint32_t bootload_status; 5878 int i, r; 5879 5880 for (i = 0; i < adev->usec_timeout; i++) { 5881 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5882 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5883 if ((cp_status == 0) && 5884 (REG_GET_FIELD(bootload_status, 5885 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5886 break; 5887 } 5888 udelay(1); 5889 } 5890 5891 if (i >= adev->usec_timeout) { 5892 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5893 return -ETIMEDOUT; 5894 } 5895 5896 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5897 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5898 if (r) 5899 return r; 5900 5901 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5902 if (r) 5903 return r; 5904 5905 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5906 if (r) 5907 return r; 5908 5909 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5910 if (r) 5911 return r; 5912 } 5913 5914 return 0; 5915 } 5916 5917 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5918 { 5919 int i; 5920 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5921 5922 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5923 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5924 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5925 5926 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5927 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5928 else 5929 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5930 5931 if (adev->job_hang && !enable) 5932 return 0; 5933 5934 for (i = 0; i < adev->usec_timeout; i++) { 5935 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5936 break; 5937 udelay(1); 5938 } 5939 5940 if (i >= adev->usec_timeout) 5941 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5942 5943 return 0; 5944 } 5945 5946 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5947 { 5948 int r; 5949 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5950 const __le32 *fw_data; 5951 unsigned int i, fw_size; 5952 uint32_t tmp; 5953 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5954 5955 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5956 adev->gfx.pfp_fw->data; 5957 5958 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5959 5960 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5961 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5962 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5963 5964 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5965 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5966 &adev->gfx.pfp.pfp_fw_obj, 5967 &adev->gfx.pfp.pfp_fw_gpu_addr, 5968 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5969 if (r) { 5970 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5971 gfx_v10_0_pfp_fini(adev); 5972 return r; 5973 } 5974 5975 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5976 5977 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5978 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5979 5980 /* Trigger an invalidation of the L1 instruction caches */ 5981 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5982 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5983 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5984 5985 /* Wait for invalidation complete */ 5986 for (i = 0; i < usec_timeout; i++) { 5987 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5988 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5989 INVALIDATE_CACHE_COMPLETE)) 5990 break; 5991 udelay(1); 5992 } 5993 5994 if (i >= usec_timeout) { 5995 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5996 return -EINVAL; 5997 } 5998 5999 if (amdgpu_emu_mode == 1) 6000 adev->hdp.funcs->flush_hdp(adev, NULL); 6001 6002 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6003 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6004 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6005 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6006 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6007 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6008 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6009 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6010 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6011 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6012 6013 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6014 6015 for (i = 0; i < pfp_hdr->jt_size; i++) 6016 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6017 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6018 6019 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6020 6021 return 0; 6022 } 6023 6024 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6025 { 6026 int r; 6027 const struct gfx_firmware_header_v1_0 *ce_hdr; 6028 const __le32 *fw_data; 6029 unsigned int i, fw_size; 6030 uint32_t tmp; 6031 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6032 6033 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6034 adev->gfx.ce_fw->data; 6035 6036 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6037 6038 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6039 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6040 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6041 6042 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6043 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6044 &adev->gfx.ce.ce_fw_obj, 6045 &adev->gfx.ce.ce_fw_gpu_addr, 6046 (void **)&adev->gfx.ce.ce_fw_ptr); 6047 if (r) { 6048 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6049 gfx_v10_0_ce_fini(adev); 6050 return r; 6051 } 6052 6053 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6054 6055 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6056 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6057 6058 /* Trigger an invalidation of the L1 instruction caches */ 6059 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6060 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6061 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6062 6063 /* Wait for invalidation complete */ 6064 for (i = 0; i < usec_timeout; i++) { 6065 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6066 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6067 INVALIDATE_CACHE_COMPLETE)) 6068 break; 6069 udelay(1); 6070 } 6071 6072 if (i >= usec_timeout) { 6073 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6074 return -EINVAL; 6075 } 6076 6077 if (amdgpu_emu_mode == 1) 6078 adev->hdp.funcs->flush_hdp(adev, NULL); 6079 6080 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6081 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6082 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6083 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6084 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6085 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6086 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6087 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6088 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6089 6090 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6091 6092 for (i = 0; i < ce_hdr->jt_size; i++) 6093 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6094 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6095 6096 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6097 6098 return 0; 6099 } 6100 6101 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6102 { 6103 int r; 6104 const struct gfx_firmware_header_v1_0 *me_hdr; 6105 const __le32 *fw_data; 6106 unsigned int i, fw_size; 6107 uint32_t tmp; 6108 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6109 6110 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6111 adev->gfx.me_fw->data; 6112 6113 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6114 6115 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6116 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6117 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6118 6119 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6120 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6121 &adev->gfx.me.me_fw_obj, 6122 &adev->gfx.me.me_fw_gpu_addr, 6123 (void **)&adev->gfx.me.me_fw_ptr); 6124 if (r) { 6125 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6126 gfx_v10_0_me_fini(adev); 6127 return r; 6128 } 6129 6130 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6131 6132 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6133 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6134 6135 /* Trigger an invalidation of the L1 instruction caches */ 6136 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6137 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6138 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6139 6140 /* Wait for invalidation complete */ 6141 for (i = 0; i < usec_timeout; i++) { 6142 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6143 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6144 INVALIDATE_CACHE_COMPLETE)) 6145 break; 6146 udelay(1); 6147 } 6148 6149 if (i >= usec_timeout) { 6150 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6151 return -EINVAL; 6152 } 6153 6154 if (amdgpu_emu_mode == 1) 6155 adev->hdp.funcs->flush_hdp(adev, NULL); 6156 6157 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6158 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6159 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6160 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6161 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6162 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6163 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6164 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6165 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6166 6167 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6168 6169 for (i = 0; i < me_hdr->jt_size; i++) 6170 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6171 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6172 6173 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6174 6175 return 0; 6176 } 6177 6178 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6179 { 6180 int r; 6181 6182 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6183 return -EINVAL; 6184 6185 gfx_v10_0_cp_gfx_enable(adev, false); 6186 6187 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6188 if (r) { 6189 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6190 return r; 6191 } 6192 6193 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6194 if (r) { 6195 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6196 return r; 6197 } 6198 6199 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6200 if (r) { 6201 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6202 return r; 6203 } 6204 6205 return 0; 6206 } 6207 6208 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6209 { 6210 struct amdgpu_ring *ring; 6211 const struct cs_section_def *sect = NULL; 6212 const struct cs_extent_def *ext = NULL; 6213 int r, i; 6214 int ctx_reg_offset; 6215 6216 /* init the CP */ 6217 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6218 adev->gfx.config.max_hw_contexts - 1); 6219 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6220 6221 gfx_v10_0_cp_gfx_enable(adev, true); 6222 6223 ring = &adev->gfx.gfx_ring[0]; 6224 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6225 if (r) { 6226 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6227 return r; 6228 } 6229 6230 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6231 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6232 6233 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6234 amdgpu_ring_write(ring, 0x80000000); 6235 amdgpu_ring_write(ring, 0x80000000); 6236 6237 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6238 for (ext = sect->section; ext->extent != NULL; ++ext) { 6239 if (sect->id == SECT_CONTEXT) { 6240 amdgpu_ring_write(ring, 6241 PACKET3(PACKET3_SET_CONTEXT_REG, 6242 ext->reg_count)); 6243 amdgpu_ring_write(ring, ext->reg_index - 6244 PACKET3_SET_CONTEXT_REG_START); 6245 for (i = 0; i < ext->reg_count; i++) 6246 amdgpu_ring_write(ring, ext->extent[i]); 6247 } 6248 } 6249 } 6250 6251 ctx_reg_offset = 6252 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6253 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6254 amdgpu_ring_write(ring, ctx_reg_offset); 6255 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6256 6257 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6258 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6259 6260 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6261 amdgpu_ring_write(ring, 0); 6262 6263 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6264 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6265 amdgpu_ring_write(ring, 0x8000); 6266 amdgpu_ring_write(ring, 0x8000); 6267 6268 amdgpu_ring_commit(ring); 6269 6270 /* submit cs packet to copy state 0 to next available state */ 6271 if (adev->gfx.num_gfx_rings > 1) { 6272 /* maximum supported gfx ring is 2 */ 6273 ring = &adev->gfx.gfx_ring[1]; 6274 r = amdgpu_ring_alloc(ring, 2); 6275 if (r) { 6276 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6277 return r; 6278 } 6279 6280 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6281 amdgpu_ring_write(ring, 0); 6282 6283 amdgpu_ring_commit(ring); 6284 } 6285 return 0; 6286 } 6287 6288 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6289 CP_PIPE_ID pipe) 6290 { 6291 u32 tmp; 6292 6293 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6294 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6295 6296 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6297 } 6298 6299 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6300 struct amdgpu_ring *ring) 6301 { 6302 u32 tmp; 6303 6304 if (!amdgpu_async_gfx_ring) { 6305 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6306 if (ring->use_doorbell) { 6307 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6308 DOORBELL_OFFSET, ring->doorbell_index); 6309 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6310 DOORBELL_EN, 1); 6311 } else { 6312 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6313 DOORBELL_EN, 0); 6314 } 6315 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6316 } 6317 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6318 case IP_VERSION(10, 3, 0): 6319 case IP_VERSION(10, 3, 2): 6320 case IP_VERSION(10, 3, 1): 6321 case IP_VERSION(10, 3, 4): 6322 case IP_VERSION(10, 3, 5): 6323 case IP_VERSION(10, 3, 6): 6324 case IP_VERSION(10, 3, 3): 6325 case IP_VERSION(10, 3, 7): 6326 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6327 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6328 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6329 6330 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6331 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6332 break; 6333 default: 6334 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6335 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6336 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6337 6338 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6339 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6340 break; 6341 } 6342 } 6343 6344 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6345 { 6346 struct amdgpu_ring *ring; 6347 u32 tmp; 6348 u32 rb_bufsz; 6349 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6350 6351 /* Set the write pointer delay */ 6352 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6353 6354 /* set the RB to use vmid 0 */ 6355 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6356 6357 /* Init gfx ring 0 for pipe 0 */ 6358 mutex_lock(&adev->srbm_mutex); 6359 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6360 6361 /* Set ring buffer size */ 6362 ring = &adev->gfx.gfx_ring[0]; 6363 rb_bufsz = order_base_2(ring->ring_size / 8); 6364 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6365 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6366 #ifdef __BIG_ENDIAN 6367 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6368 #endif 6369 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6370 6371 /* Initialize the ring buffer's write pointers */ 6372 ring->wptr = 0; 6373 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6374 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6375 6376 /* set the wb address wether it's enabled or not */ 6377 rptr_addr = ring->rptr_gpu_addr; 6378 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6379 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6380 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6381 6382 wptr_gpu_addr = ring->wptr_gpu_addr; 6383 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6384 lower_32_bits(wptr_gpu_addr)); 6385 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6386 upper_32_bits(wptr_gpu_addr)); 6387 6388 mdelay(1); 6389 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6390 6391 rb_addr = ring->gpu_addr >> 8; 6392 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6393 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6394 6395 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6396 6397 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6398 mutex_unlock(&adev->srbm_mutex); 6399 6400 /* Init gfx ring 1 for pipe 1 */ 6401 if (adev->gfx.num_gfx_rings > 1) { 6402 mutex_lock(&adev->srbm_mutex); 6403 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6404 /* maximum supported gfx ring is 2 */ 6405 ring = &adev->gfx.gfx_ring[1]; 6406 rb_bufsz = order_base_2(ring->ring_size / 8); 6407 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6408 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6409 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6410 /* Initialize the ring buffer's write pointers */ 6411 ring->wptr = 0; 6412 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6413 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6414 /* Set the wb address wether it's enabled or not */ 6415 rptr_addr = ring->rptr_gpu_addr; 6416 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6417 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6418 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6419 wptr_gpu_addr = ring->wptr_gpu_addr; 6420 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6421 lower_32_bits(wptr_gpu_addr)); 6422 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6423 upper_32_bits(wptr_gpu_addr)); 6424 6425 mdelay(1); 6426 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6427 6428 rb_addr = ring->gpu_addr >> 8; 6429 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6430 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6431 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6432 6433 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6434 mutex_unlock(&adev->srbm_mutex); 6435 } 6436 /* Switch to pipe 0 */ 6437 mutex_lock(&adev->srbm_mutex); 6438 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6439 mutex_unlock(&adev->srbm_mutex); 6440 6441 /* start the ring */ 6442 gfx_v10_0_cp_gfx_start(adev); 6443 6444 return 0; 6445 } 6446 6447 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6448 { 6449 if (enable) { 6450 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6451 case IP_VERSION(10, 3, 0): 6452 case IP_VERSION(10, 3, 2): 6453 case IP_VERSION(10, 3, 1): 6454 case IP_VERSION(10, 3, 4): 6455 case IP_VERSION(10, 3, 5): 6456 case IP_VERSION(10, 3, 6): 6457 case IP_VERSION(10, 3, 3): 6458 case IP_VERSION(10, 3, 7): 6459 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6460 break; 6461 default: 6462 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6463 break; 6464 } 6465 } else { 6466 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6467 case IP_VERSION(10, 3, 0): 6468 case IP_VERSION(10, 3, 2): 6469 case IP_VERSION(10, 3, 1): 6470 case IP_VERSION(10, 3, 4): 6471 case IP_VERSION(10, 3, 5): 6472 case IP_VERSION(10, 3, 6): 6473 case IP_VERSION(10, 3, 3): 6474 case IP_VERSION(10, 3, 7): 6475 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6476 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6477 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6478 break; 6479 default: 6480 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6481 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6482 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6483 break; 6484 } 6485 adev->gfx.kiq[0].ring.sched.ready = false; 6486 } 6487 udelay(50); 6488 } 6489 6490 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6491 { 6492 const struct gfx_firmware_header_v1_0 *mec_hdr; 6493 const __le32 *fw_data; 6494 unsigned int i; 6495 u32 tmp; 6496 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6497 6498 if (!adev->gfx.mec_fw) 6499 return -EINVAL; 6500 6501 gfx_v10_0_cp_compute_enable(adev, false); 6502 6503 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6504 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6505 6506 fw_data = (const __le32 *) 6507 (adev->gfx.mec_fw->data + 6508 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6509 6510 /* Trigger an invalidation of the L1 instruction caches */ 6511 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6512 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6513 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6514 6515 /* Wait for invalidation complete */ 6516 for (i = 0; i < usec_timeout; i++) { 6517 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6518 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6519 INVALIDATE_CACHE_COMPLETE)) 6520 break; 6521 udelay(1); 6522 } 6523 6524 if (i >= usec_timeout) { 6525 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6526 return -EINVAL; 6527 } 6528 6529 if (amdgpu_emu_mode == 1) 6530 adev->hdp.funcs->flush_hdp(adev, NULL); 6531 6532 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6533 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6534 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6535 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6536 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6537 6538 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6539 0xFFFFF000); 6540 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6541 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6542 6543 /* MEC1 */ 6544 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6545 6546 for (i = 0; i < mec_hdr->jt_size; i++) 6547 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6548 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6549 6550 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6551 6552 /* 6553 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6554 * different microcode than MEC1. 6555 */ 6556 6557 return 0; 6558 } 6559 6560 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6561 { 6562 uint32_t tmp; 6563 struct amdgpu_device *adev = ring->adev; 6564 6565 /* tell RLC which is KIQ queue */ 6566 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6567 case IP_VERSION(10, 3, 0): 6568 case IP_VERSION(10, 3, 2): 6569 case IP_VERSION(10, 3, 1): 6570 case IP_VERSION(10, 3, 4): 6571 case IP_VERSION(10, 3, 5): 6572 case IP_VERSION(10, 3, 6): 6573 case IP_VERSION(10, 3, 3): 6574 case IP_VERSION(10, 3, 7): 6575 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6576 tmp &= 0xffffff00; 6577 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6578 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6579 tmp |= 0x80; 6580 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6581 break; 6582 default: 6583 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6584 tmp &= 0xffffff00; 6585 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6586 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6587 tmp |= 0x80; 6588 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6589 break; 6590 } 6591 } 6592 6593 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6594 struct v10_gfx_mqd *mqd, 6595 struct amdgpu_mqd_prop *prop) 6596 { 6597 bool priority = 0; 6598 u32 tmp; 6599 6600 /* set up default queue priority level 6601 * 0x0 = low priority, 0x1 = high priority 6602 */ 6603 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6604 priority = 1; 6605 6606 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6607 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6608 mqd->cp_gfx_hqd_queue_priority = tmp; 6609 } 6610 6611 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6612 struct amdgpu_mqd_prop *prop) 6613 { 6614 struct v10_gfx_mqd *mqd = m; 6615 uint64_t hqd_gpu_addr, wb_gpu_addr; 6616 uint32_t tmp; 6617 uint32_t rb_bufsz; 6618 6619 /* set up gfx hqd wptr */ 6620 mqd->cp_gfx_hqd_wptr = 0; 6621 mqd->cp_gfx_hqd_wptr_hi = 0; 6622 6623 /* set the pointer to the MQD */ 6624 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6625 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6626 6627 /* set up mqd control */ 6628 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6629 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6630 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6631 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6632 mqd->cp_gfx_mqd_control = tmp; 6633 6634 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6635 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6636 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6637 mqd->cp_gfx_hqd_vmid = 0; 6638 6639 /* set up gfx queue priority */ 6640 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6641 6642 /* set up time quantum */ 6643 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6644 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6645 mqd->cp_gfx_hqd_quantum = tmp; 6646 6647 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6648 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6649 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6650 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6651 6652 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6653 wb_gpu_addr = prop->rptr_gpu_addr; 6654 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6655 mqd->cp_gfx_hqd_rptr_addr_hi = 6656 upper_32_bits(wb_gpu_addr) & 0xffff; 6657 6658 /* set up rb_wptr_poll addr */ 6659 wb_gpu_addr = prop->wptr_gpu_addr; 6660 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6661 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6662 6663 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6664 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6665 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6666 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6667 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6668 #ifdef __BIG_ENDIAN 6669 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6670 #endif 6671 mqd->cp_gfx_hqd_cntl = tmp; 6672 6673 /* set up cp_doorbell_control */ 6674 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6675 if (prop->use_doorbell) { 6676 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6677 DOORBELL_OFFSET, prop->doorbell_index); 6678 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6679 DOORBELL_EN, 1); 6680 } else 6681 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6682 DOORBELL_EN, 0); 6683 mqd->cp_rb_doorbell_control = tmp; 6684 6685 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6686 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6687 6688 /* active the queue */ 6689 mqd->cp_gfx_hqd_active = 1; 6690 6691 return 0; 6692 } 6693 6694 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6695 { 6696 struct amdgpu_device *adev = ring->adev; 6697 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6698 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6699 6700 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6701 memset((void *)mqd, 0, sizeof(*mqd)); 6702 mutex_lock(&adev->srbm_mutex); 6703 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6704 amdgpu_ring_init_mqd(ring); 6705 6706 /* 6707 * if there are 2 gfx rings, set the lower doorbell 6708 * range of the first ring, otherwise the range of 6709 * the second ring will override the first ring 6710 */ 6711 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6712 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6713 6714 nv_grbm_select(adev, 0, 0, 0, 0); 6715 mutex_unlock(&adev->srbm_mutex); 6716 if (adev->gfx.me.mqd_backup[mqd_idx]) 6717 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6718 } else { 6719 mutex_lock(&adev->srbm_mutex); 6720 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6721 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6722 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6723 6724 nv_grbm_select(adev, 0, 0, 0, 0); 6725 mutex_unlock(&adev->srbm_mutex); 6726 /* restore mqd with the backup copy */ 6727 if (adev->gfx.me.mqd_backup[mqd_idx]) 6728 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6729 /* reset the ring */ 6730 ring->wptr = 0; 6731 *ring->wptr_cpu_addr = 0; 6732 amdgpu_ring_clear_ring(ring); 6733 } 6734 6735 return 0; 6736 } 6737 6738 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6739 { 6740 int r, i; 6741 struct amdgpu_ring *ring; 6742 6743 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6744 ring = &adev->gfx.gfx_ring[i]; 6745 6746 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6747 if (unlikely(r != 0)) 6748 return r; 6749 6750 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6751 if (!r) { 6752 r = gfx_v10_0_gfx_init_queue(ring); 6753 amdgpu_bo_kunmap(ring->mqd_obj); 6754 ring->mqd_ptr = NULL; 6755 } 6756 amdgpu_bo_unreserve(ring->mqd_obj); 6757 if (r) 6758 return r; 6759 } 6760 6761 r = amdgpu_gfx_enable_kgq(adev, 0); 6762 if (r) 6763 return r; 6764 6765 return gfx_v10_0_cp_gfx_start(adev); 6766 } 6767 6768 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6769 struct amdgpu_mqd_prop *prop) 6770 { 6771 struct v10_compute_mqd *mqd = m; 6772 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6773 uint32_t tmp; 6774 6775 mqd->header = 0xC0310800; 6776 mqd->compute_pipelinestat_enable = 0x00000001; 6777 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6778 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6779 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6780 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6781 mqd->compute_misc_reserved = 0x00000003; 6782 6783 eop_base_addr = prop->eop_gpu_addr >> 8; 6784 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6785 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6786 6787 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6788 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6789 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6790 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6791 6792 mqd->cp_hqd_eop_control = tmp; 6793 6794 /* enable doorbell? */ 6795 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6796 6797 if (prop->use_doorbell) { 6798 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6799 DOORBELL_OFFSET, prop->doorbell_index); 6800 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6801 DOORBELL_EN, 1); 6802 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6803 DOORBELL_SOURCE, 0); 6804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6805 DOORBELL_HIT, 0); 6806 } else { 6807 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6808 DOORBELL_EN, 0); 6809 } 6810 6811 mqd->cp_hqd_pq_doorbell_control = tmp; 6812 6813 /* disable the queue if it's active */ 6814 mqd->cp_hqd_dequeue_request = 0; 6815 mqd->cp_hqd_pq_rptr = 0; 6816 mqd->cp_hqd_pq_wptr_lo = 0; 6817 mqd->cp_hqd_pq_wptr_hi = 0; 6818 6819 /* set the pointer to the MQD */ 6820 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6821 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6822 6823 /* set MQD vmid to 0 */ 6824 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6825 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6826 mqd->cp_mqd_control = tmp; 6827 6828 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6829 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6830 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6831 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6832 6833 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6834 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6836 (order_base_2(prop->queue_size / 4) - 1)); 6837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6838 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6839 #ifdef __BIG_ENDIAN 6840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6841 #endif 6842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6843 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6844 prop->allow_tunneling); 6845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6846 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6847 mqd->cp_hqd_pq_control = tmp; 6848 6849 /* set the wb address whether it's enabled or not */ 6850 wb_gpu_addr = prop->rptr_gpu_addr; 6851 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6852 mqd->cp_hqd_pq_rptr_report_addr_hi = 6853 upper_32_bits(wb_gpu_addr) & 0xffff; 6854 6855 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6856 wb_gpu_addr = prop->wptr_gpu_addr; 6857 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6858 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6859 6860 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6861 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6862 6863 /* set the vmid for the queue */ 6864 mqd->cp_hqd_vmid = 0; 6865 6866 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6867 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6868 mqd->cp_hqd_persistent_state = tmp; 6869 6870 /* set MIN_IB_AVAIL_SIZE */ 6871 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6872 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6873 mqd->cp_hqd_ib_control = tmp; 6874 6875 /* set static priority for a compute queue/ring */ 6876 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6877 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6878 6879 mqd->cp_hqd_active = prop->hqd_active; 6880 6881 return 0; 6882 } 6883 6884 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6885 { 6886 struct amdgpu_device *adev = ring->adev; 6887 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6888 int j; 6889 6890 /* inactivate the queue */ 6891 if (amdgpu_sriov_vf(adev)) 6892 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6893 6894 /* disable wptr polling */ 6895 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6896 6897 /* disable the queue if it's active */ 6898 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6899 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6900 for (j = 0; j < adev->usec_timeout; j++) { 6901 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6902 break; 6903 udelay(1); 6904 } 6905 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6906 mqd->cp_hqd_dequeue_request); 6907 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6908 mqd->cp_hqd_pq_rptr); 6909 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6910 mqd->cp_hqd_pq_wptr_lo); 6911 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6912 mqd->cp_hqd_pq_wptr_hi); 6913 } 6914 6915 /* disable doorbells */ 6916 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6917 6918 /* write the EOP addr */ 6919 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6920 mqd->cp_hqd_eop_base_addr_lo); 6921 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6922 mqd->cp_hqd_eop_base_addr_hi); 6923 6924 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6925 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6926 mqd->cp_hqd_eop_control); 6927 6928 /* set the pointer to the MQD */ 6929 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6930 mqd->cp_mqd_base_addr_lo); 6931 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6932 mqd->cp_mqd_base_addr_hi); 6933 6934 /* set MQD vmid to 0 */ 6935 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6936 mqd->cp_mqd_control); 6937 6938 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6939 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6940 mqd->cp_hqd_pq_base_lo); 6941 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6942 mqd->cp_hqd_pq_base_hi); 6943 6944 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6945 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6946 mqd->cp_hqd_pq_control); 6947 6948 /* set the wb address whether it's enabled or not */ 6949 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6950 mqd->cp_hqd_pq_rptr_report_addr_lo); 6951 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6952 mqd->cp_hqd_pq_rptr_report_addr_hi); 6953 6954 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6955 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6956 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6957 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6958 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6959 6960 /* enable the doorbell if requested */ 6961 if (ring->use_doorbell) { 6962 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6963 (adev->doorbell_index.kiq * 2) << 2); 6964 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6965 (adev->doorbell_index.userqueue_end * 2) << 2); 6966 } 6967 6968 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6969 mqd->cp_hqd_pq_doorbell_control); 6970 6971 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6972 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6973 mqd->cp_hqd_pq_wptr_lo); 6974 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6975 mqd->cp_hqd_pq_wptr_hi); 6976 6977 /* set the vmid for the queue */ 6978 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6979 6980 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6981 mqd->cp_hqd_persistent_state); 6982 6983 /* activate the queue */ 6984 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6985 mqd->cp_hqd_active); 6986 6987 if (ring->use_doorbell) 6988 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6989 6990 return 0; 6991 } 6992 6993 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6994 { 6995 struct amdgpu_device *adev = ring->adev; 6996 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6997 6998 gfx_v10_0_kiq_setting(ring); 6999 7000 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7001 /* reset MQD to a clean status */ 7002 if (adev->gfx.kiq[0].mqd_backup) 7003 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7004 7005 /* reset ring buffer */ 7006 ring->wptr = 0; 7007 amdgpu_ring_clear_ring(ring); 7008 7009 mutex_lock(&adev->srbm_mutex); 7010 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7011 gfx_v10_0_kiq_init_register(ring); 7012 nv_grbm_select(adev, 0, 0, 0, 0); 7013 mutex_unlock(&adev->srbm_mutex); 7014 } else { 7015 memset((void *)mqd, 0, sizeof(*mqd)); 7016 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7017 amdgpu_ring_clear_ring(ring); 7018 mutex_lock(&adev->srbm_mutex); 7019 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7020 amdgpu_ring_init_mqd(ring); 7021 gfx_v10_0_kiq_init_register(ring); 7022 nv_grbm_select(adev, 0, 0, 0, 0); 7023 mutex_unlock(&adev->srbm_mutex); 7024 7025 if (adev->gfx.kiq[0].mqd_backup) 7026 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7027 } 7028 7029 return 0; 7030 } 7031 7032 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 7033 { 7034 struct amdgpu_device *adev = ring->adev; 7035 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7036 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7037 7038 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 7039 memset((void *)mqd, 0, sizeof(*mqd)); 7040 mutex_lock(&adev->srbm_mutex); 7041 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7042 amdgpu_ring_init_mqd(ring); 7043 nv_grbm_select(adev, 0, 0, 0, 0); 7044 mutex_unlock(&adev->srbm_mutex); 7045 7046 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7047 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7048 } else { 7049 /* restore MQD to a clean status */ 7050 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7051 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7052 /* reset ring buffer */ 7053 ring->wptr = 0; 7054 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7055 amdgpu_ring_clear_ring(ring); 7056 } 7057 7058 return 0; 7059 } 7060 7061 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7062 { 7063 struct amdgpu_ring *ring; 7064 int r; 7065 7066 ring = &adev->gfx.kiq[0].ring; 7067 7068 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7069 if (unlikely(r != 0)) 7070 return r; 7071 7072 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7073 if (unlikely(r != 0)) { 7074 amdgpu_bo_unreserve(ring->mqd_obj); 7075 return r; 7076 } 7077 7078 gfx_v10_0_kiq_init_queue(ring); 7079 amdgpu_bo_kunmap(ring->mqd_obj); 7080 ring->mqd_ptr = NULL; 7081 amdgpu_bo_unreserve(ring->mqd_obj); 7082 return 0; 7083 } 7084 7085 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7086 { 7087 struct amdgpu_ring *ring = NULL; 7088 int r = 0, i; 7089 7090 gfx_v10_0_cp_compute_enable(adev, true); 7091 7092 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7093 ring = &adev->gfx.compute_ring[i]; 7094 7095 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7096 if (unlikely(r != 0)) 7097 goto done; 7098 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7099 if (!r) { 7100 r = gfx_v10_0_kcq_init_queue(ring); 7101 amdgpu_bo_kunmap(ring->mqd_obj); 7102 ring->mqd_ptr = NULL; 7103 } 7104 amdgpu_bo_unreserve(ring->mqd_obj); 7105 if (r) 7106 goto done; 7107 } 7108 7109 r = amdgpu_gfx_enable_kcq(adev, 0); 7110 done: 7111 return r; 7112 } 7113 7114 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7115 { 7116 int r, i; 7117 struct amdgpu_ring *ring; 7118 7119 if (!(adev->flags & AMD_IS_APU)) 7120 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7121 7122 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7123 /* legacy firmware loading */ 7124 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7125 if (r) 7126 return r; 7127 7128 r = gfx_v10_0_cp_compute_load_microcode(adev); 7129 if (r) 7130 return r; 7131 } 7132 7133 r = gfx_v10_0_kiq_resume(adev); 7134 if (r) 7135 return r; 7136 7137 r = gfx_v10_0_kcq_resume(adev); 7138 if (r) 7139 return r; 7140 7141 if (!amdgpu_async_gfx_ring) { 7142 r = gfx_v10_0_cp_gfx_resume(adev); 7143 if (r) 7144 return r; 7145 } else { 7146 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7147 if (r) 7148 return r; 7149 } 7150 7151 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7152 ring = &adev->gfx.gfx_ring[i]; 7153 r = amdgpu_ring_test_helper(ring); 7154 if (r) 7155 return r; 7156 } 7157 7158 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7159 ring = &adev->gfx.compute_ring[i]; 7160 r = amdgpu_ring_test_helper(ring); 7161 if (r) 7162 return r; 7163 } 7164 7165 return 0; 7166 } 7167 7168 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7169 { 7170 gfx_v10_0_cp_gfx_enable(adev, enable); 7171 gfx_v10_0_cp_compute_enable(adev, enable); 7172 } 7173 7174 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7175 { 7176 uint32_t data, pattern = 0xDEADBEEF; 7177 7178 /* 7179 * check if mmVGT_ESGS_RING_SIZE_UMD 7180 * has been remapped to mmVGT_ESGS_RING_SIZE 7181 */ 7182 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7183 case IP_VERSION(10, 3, 0): 7184 case IP_VERSION(10, 3, 2): 7185 case IP_VERSION(10, 3, 4): 7186 case IP_VERSION(10, 3, 5): 7187 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7188 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7189 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7190 7191 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7192 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7193 return true; 7194 } 7195 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7196 break; 7197 case IP_VERSION(10, 3, 1): 7198 case IP_VERSION(10, 3, 3): 7199 case IP_VERSION(10, 3, 6): 7200 case IP_VERSION(10, 3, 7): 7201 return true; 7202 default: 7203 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7204 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7205 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7206 7207 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7208 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7209 return true; 7210 } 7211 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7212 break; 7213 } 7214 7215 return false; 7216 } 7217 7218 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7219 { 7220 uint32_t data; 7221 7222 if (amdgpu_sriov_vf(adev)) 7223 return; 7224 7225 /* 7226 * Initialize cam_index to 0 7227 * index will auto-inc after each data writing 7228 */ 7229 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7230 7231 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7232 case IP_VERSION(10, 3, 0): 7233 case IP_VERSION(10, 3, 2): 7234 case IP_VERSION(10, 3, 1): 7235 case IP_VERSION(10, 3, 4): 7236 case IP_VERSION(10, 3, 5): 7237 case IP_VERSION(10, 3, 6): 7238 case IP_VERSION(10, 3, 3): 7239 case IP_VERSION(10, 3, 7): 7240 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7241 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7242 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7243 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7244 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7245 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7246 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7247 7248 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7249 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7250 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7251 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7252 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7253 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7254 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7255 7256 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7257 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7258 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7259 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7260 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7261 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7262 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7263 7264 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7265 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7266 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7267 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7268 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7269 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7270 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7271 7272 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7273 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7274 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7275 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7276 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7277 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7278 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7279 7280 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7281 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7282 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7283 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7284 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7285 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7286 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7287 7288 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7289 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7290 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7291 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7292 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7293 break; 7294 default: 7295 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7296 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7297 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7298 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7299 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7300 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7301 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7302 7303 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7304 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7305 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7306 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7307 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7308 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7309 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7310 7311 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7312 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7313 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7314 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7315 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7316 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7317 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7318 7319 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7320 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7321 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7322 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7323 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7324 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7325 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7326 7327 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7328 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7329 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7330 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7331 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7332 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7333 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7334 7335 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7336 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7337 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7338 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7339 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7340 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7341 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7342 7343 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7344 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7345 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7346 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7347 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7348 break; 7349 } 7350 7351 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7353 } 7354 7355 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7356 { 7357 uint32_t data; 7358 7359 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7360 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7361 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7362 7363 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7364 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7365 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7366 } 7367 7368 static int gfx_v10_0_hw_init(void *handle) 7369 { 7370 int r; 7371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7372 7373 if (!amdgpu_emu_mode) 7374 gfx_v10_0_init_golden_registers(adev); 7375 7376 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7377 /** 7378 * For gfx 10, rlc firmware loading relies on smu firmware is 7379 * loaded firstly, so in direct type, it has to load smc ucode 7380 * here before rlc. 7381 */ 7382 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7383 if (r) 7384 return r; 7385 gfx_v10_0_disable_gpa_mode(adev); 7386 } 7387 7388 /* if GRBM CAM not remapped, set up the remapping */ 7389 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7390 gfx_v10_0_setup_grbm_cam_remapping(adev); 7391 7392 gfx_v10_0_constants_init(adev); 7393 7394 r = gfx_v10_0_rlc_resume(adev); 7395 if (r) 7396 return r; 7397 7398 /* 7399 * init golden registers and rlc resume may override some registers, 7400 * reconfig them here 7401 */ 7402 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7403 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7404 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7405 gfx_v10_0_tcp_harvest(adev); 7406 7407 r = gfx_v10_0_cp_resume(adev); 7408 if (r) 7409 return r; 7410 7411 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7412 gfx_v10_3_program_pbb_mode(adev); 7413 7414 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7415 gfx_v10_3_set_power_brake_sequence(adev); 7416 7417 return r; 7418 } 7419 7420 static int gfx_v10_0_hw_fini(void *handle) 7421 { 7422 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7423 7424 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7425 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7426 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7427 7428 /* WA added for Vangogh asic fixing the SMU suspend failure 7429 * It needs to set power gating again during gfxoff control 7430 * otherwise the gfxoff disallowing will be failed to set. 7431 */ 7432 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7433 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); 7434 7435 if (!adev->no_hw_access) { 7436 if (amdgpu_async_gfx_ring) { 7437 if (amdgpu_gfx_disable_kgq(adev, 0)) 7438 DRM_ERROR("KGQ disable failed\n"); 7439 } 7440 7441 if (amdgpu_gfx_disable_kcq(adev, 0)) 7442 DRM_ERROR("KCQ disable failed\n"); 7443 } 7444 7445 if (amdgpu_sriov_vf(adev)) { 7446 gfx_v10_0_cp_gfx_enable(adev, false); 7447 /* Remove the steps of clearing KIQ position. 7448 * It causes GFX hang when another Win guest is rendering. 7449 */ 7450 return 0; 7451 } 7452 gfx_v10_0_cp_enable(adev, false); 7453 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7454 7455 return 0; 7456 } 7457 7458 static int gfx_v10_0_suspend(void *handle) 7459 { 7460 return gfx_v10_0_hw_fini(handle); 7461 } 7462 7463 static int gfx_v10_0_resume(void *handle) 7464 { 7465 return gfx_v10_0_hw_init(handle); 7466 } 7467 7468 static bool gfx_v10_0_is_idle(void *handle) 7469 { 7470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7471 7472 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7473 GRBM_STATUS, GUI_ACTIVE)) 7474 return false; 7475 else 7476 return true; 7477 } 7478 7479 static int gfx_v10_0_wait_for_idle(void *handle) 7480 { 7481 unsigned int i; 7482 u32 tmp; 7483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7484 7485 for (i = 0; i < adev->usec_timeout; i++) { 7486 /* read MC_STATUS */ 7487 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7488 GRBM_STATUS__GUI_ACTIVE_MASK; 7489 7490 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7491 return 0; 7492 udelay(1); 7493 } 7494 return -ETIMEDOUT; 7495 } 7496 7497 static int gfx_v10_0_soft_reset(void *handle) 7498 { 7499 u32 grbm_soft_reset = 0; 7500 u32 tmp; 7501 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7502 7503 /* GRBM_STATUS */ 7504 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7505 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7506 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7507 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7508 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7509 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7510 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7511 GRBM_SOFT_RESET, SOFT_RESET_CP, 7512 1); 7513 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7514 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7515 1); 7516 } 7517 7518 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7519 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7520 GRBM_SOFT_RESET, SOFT_RESET_CP, 7521 1); 7522 } 7523 7524 /* GRBM_STATUS2 */ 7525 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7526 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7527 case IP_VERSION(10, 3, 0): 7528 case IP_VERSION(10, 3, 2): 7529 case IP_VERSION(10, 3, 1): 7530 case IP_VERSION(10, 3, 4): 7531 case IP_VERSION(10, 3, 5): 7532 case IP_VERSION(10, 3, 6): 7533 case IP_VERSION(10, 3, 3): 7534 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7535 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7536 GRBM_SOFT_RESET, 7537 SOFT_RESET_RLC, 7538 1); 7539 break; 7540 default: 7541 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7542 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7543 GRBM_SOFT_RESET, 7544 SOFT_RESET_RLC, 7545 1); 7546 break; 7547 } 7548 7549 if (grbm_soft_reset) { 7550 /* stop the rlc */ 7551 gfx_v10_0_rlc_stop(adev); 7552 7553 /* Disable GFX parsing/prefetching */ 7554 gfx_v10_0_cp_gfx_enable(adev, false); 7555 7556 /* Disable MEC parsing/prefetching */ 7557 gfx_v10_0_cp_compute_enable(adev, false); 7558 7559 if (grbm_soft_reset) { 7560 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7561 tmp |= grbm_soft_reset; 7562 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7563 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7564 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7565 7566 udelay(50); 7567 7568 tmp &= ~grbm_soft_reset; 7569 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7570 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7571 } 7572 7573 /* Wait a little for things to settle down */ 7574 udelay(50); 7575 } 7576 return 0; 7577 } 7578 7579 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7580 { 7581 uint64_t clock, clock_lo, clock_hi, hi_check; 7582 7583 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7584 case IP_VERSION(10, 1, 3): 7585 case IP_VERSION(10, 1, 4): 7586 preempt_disable(); 7587 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7588 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7589 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7590 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7591 * roughly every 42 seconds. 7592 */ 7593 if (hi_check != clock_hi) { 7594 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7595 clock_hi = hi_check; 7596 } 7597 preempt_enable(); 7598 clock = clock_lo | (clock_hi << 32ULL); 7599 break; 7600 case IP_VERSION(10, 3, 1): 7601 case IP_VERSION(10, 3, 3): 7602 case IP_VERSION(10, 3, 7): 7603 preempt_disable(); 7604 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7605 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7606 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7607 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7608 * roughly every 42 seconds. 7609 */ 7610 if (hi_check != clock_hi) { 7611 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7612 clock_hi = hi_check; 7613 } 7614 preempt_enable(); 7615 clock = clock_lo | (clock_hi << 32ULL); 7616 break; 7617 case IP_VERSION(10, 3, 6): 7618 preempt_disable(); 7619 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7620 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7621 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7622 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7623 * roughly every 42 seconds. 7624 */ 7625 if (hi_check != clock_hi) { 7626 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7627 clock_hi = hi_check; 7628 } 7629 preempt_enable(); 7630 clock = clock_lo | (clock_hi << 32ULL); 7631 break; 7632 default: 7633 preempt_disable(); 7634 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7635 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7636 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7637 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7638 * roughly every 42 seconds. 7639 */ 7640 if (hi_check != clock_hi) { 7641 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7642 clock_hi = hi_check; 7643 } 7644 preempt_enable(); 7645 clock = clock_lo | (clock_hi << 32ULL); 7646 break; 7647 } 7648 return clock; 7649 } 7650 7651 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7652 uint32_t vmid, 7653 uint32_t gds_base, uint32_t gds_size, 7654 uint32_t gws_base, uint32_t gws_size, 7655 uint32_t oa_base, uint32_t oa_size) 7656 { 7657 struct amdgpu_device *adev = ring->adev; 7658 7659 /* GDS Base */ 7660 gfx_v10_0_write_data_to_reg(ring, 0, false, 7661 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7662 gds_base); 7663 7664 /* GDS Size */ 7665 gfx_v10_0_write_data_to_reg(ring, 0, false, 7666 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7667 gds_size); 7668 7669 /* GWS */ 7670 gfx_v10_0_write_data_to_reg(ring, 0, false, 7671 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7672 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7673 7674 /* OA */ 7675 gfx_v10_0_write_data_to_reg(ring, 0, false, 7676 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7677 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7678 } 7679 7680 static int gfx_v10_0_early_init(void *handle) 7681 { 7682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7683 7684 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7685 7686 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7687 case IP_VERSION(10, 1, 10): 7688 case IP_VERSION(10, 1, 1): 7689 case IP_VERSION(10, 1, 2): 7690 case IP_VERSION(10, 1, 3): 7691 case IP_VERSION(10, 1, 4): 7692 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7693 break; 7694 case IP_VERSION(10, 3, 0): 7695 case IP_VERSION(10, 3, 2): 7696 case IP_VERSION(10, 3, 1): 7697 case IP_VERSION(10, 3, 4): 7698 case IP_VERSION(10, 3, 5): 7699 case IP_VERSION(10, 3, 6): 7700 case IP_VERSION(10, 3, 3): 7701 case IP_VERSION(10, 3, 7): 7702 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7703 break; 7704 default: 7705 break; 7706 } 7707 7708 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7709 AMDGPU_MAX_COMPUTE_RINGS); 7710 7711 gfx_v10_0_set_kiq_pm4_funcs(adev); 7712 gfx_v10_0_set_ring_funcs(adev); 7713 gfx_v10_0_set_irq_funcs(adev); 7714 gfx_v10_0_set_gds_init(adev); 7715 gfx_v10_0_set_rlc_funcs(adev); 7716 gfx_v10_0_set_mqd_funcs(adev); 7717 7718 /* init rlcg reg access ctrl */ 7719 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7720 7721 return gfx_v10_0_init_microcode(adev); 7722 } 7723 7724 static int gfx_v10_0_late_init(void *handle) 7725 { 7726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7727 int r; 7728 7729 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7730 if (r) 7731 return r; 7732 7733 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7734 if (r) 7735 return r; 7736 7737 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7738 if (r) 7739 return r; 7740 7741 return 0; 7742 } 7743 7744 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7745 { 7746 uint32_t rlc_cntl; 7747 7748 /* if RLC is not enabled, do nothing */ 7749 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7750 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7751 } 7752 7753 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7754 { 7755 uint32_t data; 7756 unsigned int i; 7757 7758 data = RLC_SAFE_MODE__CMD_MASK; 7759 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7760 7761 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7762 case IP_VERSION(10, 3, 0): 7763 case IP_VERSION(10, 3, 2): 7764 case IP_VERSION(10, 3, 1): 7765 case IP_VERSION(10, 3, 4): 7766 case IP_VERSION(10, 3, 5): 7767 case IP_VERSION(10, 3, 6): 7768 case IP_VERSION(10, 3, 3): 7769 case IP_VERSION(10, 3, 7): 7770 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7771 7772 /* wait for RLC_SAFE_MODE */ 7773 for (i = 0; i < adev->usec_timeout; i++) { 7774 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7775 RLC_SAFE_MODE, CMD)) 7776 break; 7777 udelay(1); 7778 } 7779 break; 7780 default: 7781 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7782 7783 /* wait for RLC_SAFE_MODE */ 7784 for (i = 0; i < adev->usec_timeout; i++) { 7785 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7786 RLC_SAFE_MODE, CMD)) 7787 break; 7788 udelay(1); 7789 } 7790 break; 7791 } 7792 } 7793 7794 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7795 { 7796 uint32_t data; 7797 7798 data = RLC_SAFE_MODE__CMD_MASK; 7799 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7800 case IP_VERSION(10, 3, 0): 7801 case IP_VERSION(10, 3, 2): 7802 case IP_VERSION(10, 3, 1): 7803 case IP_VERSION(10, 3, 4): 7804 case IP_VERSION(10, 3, 5): 7805 case IP_VERSION(10, 3, 6): 7806 case IP_VERSION(10, 3, 3): 7807 case IP_VERSION(10, 3, 7): 7808 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7809 break; 7810 default: 7811 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7812 break; 7813 } 7814 } 7815 7816 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7817 bool enable) 7818 { 7819 uint32_t data, def; 7820 7821 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7822 return; 7823 7824 /* It is disabled by HW by default */ 7825 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7826 /* 0 - Disable some blocks' MGCG */ 7827 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7828 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7829 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7830 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7831 7832 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7833 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7834 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7835 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7836 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7837 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7838 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7839 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7840 7841 if (def != data) 7842 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7843 7844 /* MGLS is a global flag to control all MGLS in GFX */ 7845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7846 /* 2 - RLC memory Light sleep */ 7847 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7848 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7849 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7850 if (def != data) 7851 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7852 } 7853 /* 3 - CP memory Light sleep */ 7854 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7855 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7856 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7857 if (def != data) 7858 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7859 } 7860 } 7861 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7862 /* 1 - MGCG_OVERRIDE */ 7863 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7864 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7865 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7866 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7867 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7868 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7869 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7870 if (def != data) 7871 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7872 7873 /* 2 - disable MGLS in CP */ 7874 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7875 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7876 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7877 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7878 } 7879 7880 /* 3 - disable MGLS in RLC */ 7881 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7882 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7883 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7884 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7885 } 7886 7887 } 7888 } 7889 7890 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7891 bool enable) 7892 { 7893 uint32_t data, def; 7894 7895 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7896 return; 7897 7898 /* Enable 3D CGCG/CGLS */ 7899 if (enable) { 7900 /* write cmd to clear cgcg/cgls ov */ 7901 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7902 7903 /* unset CGCG override */ 7904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7905 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7906 7907 /* update CGCG and CGLS override bits */ 7908 if (def != data) 7909 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7910 7911 /* enable 3Dcgcg FSM(0x0000363f) */ 7912 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7913 data = 0; 7914 7915 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7916 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7917 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7918 7919 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7920 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7921 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7922 7923 if (def != data) 7924 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7925 7926 /* set IDLE_POLL_COUNT(0x00900100) */ 7927 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7928 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7929 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7930 if (def != data) 7931 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7932 } else { 7933 /* Disable CGCG/CGLS */ 7934 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7935 7936 /* disable cgcg, cgls should be disabled */ 7937 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7938 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7939 7940 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7941 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7942 7943 /* disable cgcg and cgls in FSM */ 7944 if (def != data) 7945 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7946 } 7947 } 7948 7949 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7950 bool enable) 7951 { 7952 uint32_t def, data; 7953 7954 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7955 return; 7956 7957 if (enable) { 7958 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7959 7960 /* unset CGCG override */ 7961 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7962 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7963 7964 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7965 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7966 7967 /* update CGCG and CGLS override bits */ 7968 if (def != data) 7969 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7970 7971 /* enable cgcg FSM(0x0000363F) */ 7972 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7973 data = 0; 7974 7975 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7976 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7977 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7978 7979 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7980 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7981 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7982 7983 if (def != data) 7984 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7985 7986 /* set IDLE_POLL_COUNT(0x00900100) */ 7987 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7988 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7989 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7990 if (def != data) 7991 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7992 } else { 7993 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7994 7995 /* reset CGCG/CGLS bits */ 7996 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7997 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7998 7999 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8000 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8001 8002 /* disable cgcg and cgls in FSM */ 8003 if (def != data) 8004 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8005 } 8006 } 8007 8008 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8009 bool enable) 8010 { 8011 uint32_t def, data; 8012 8013 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8014 return; 8015 8016 if (enable) { 8017 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8018 /* unset FGCG override */ 8019 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8020 /* update FGCG override bits */ 8021 if (def != data) 8022 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8023 8024 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8025 /* unset RLC SRAM CLK GATER override */ 8026 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8027 /* update RLC SRAM CLK GATER override bits */ 8028 if (def != data) 8029 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8030 } else { 8031 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8032 /* reset FGCG bits */ 8033 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8034 /* disable FGCG*/ 8035 if (def != data) 8036 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8037 8038 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8039 /* reset RLC SRAM CLK GATER bits */ 8040 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8041 /* disable RLC SRAM CLK*/ 8042 if (def != data) 8043 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8044 } 8045 } 8046 8047 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8048 { 8049 uint32_t reg_data = 0; 8050 uint32_t reg_idx = 0; 8051 uint32_t i; 8052 8053 const uint32_t tcp_ctrl_regs[] = { 8054 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8055 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8056 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8057 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8058 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8059 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8060 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8061 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8062 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8063 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8064 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8065 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8066 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8067 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8068 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8069 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8070 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8071 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8072 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8073 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8074 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8075 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8076 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8077 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8078 }; 8079 8080 const uint32_t tcp_ctrl_regs_nv12[] = { 8081 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8082 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8083 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8084 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8085 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8086 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8087 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8088 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8089 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8090 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8091 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8092 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8093 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8094 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8095 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8096 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8097 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8098 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8099 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8100 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8101 }; 8102 8103 const uint32_t sm_ctlr_regs[] = { 8104 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8105 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8106 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8107 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8108 }; 8109 8110 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8111 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8112 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8113 tcp_ctrl_regs_nv12[i]; 8114 reg_data = RREG32(reg_idx); 8115 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8116 WREG32(reg_idx, reg_data); 8117 } 8118 } else { 8119 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8120 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8121 tcp_ctrl_regs[i]; 8122 reg_data = RREG32(reg_idx); 8123 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8124 WREG32(reg_idx, reg_data); 8125 } 8126 } 8127 8128 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8129 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8130 sm_ctlr_regs[i]; 8131 reg_data = RREG32(reg_idx); 8132 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8133 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8134 WREG32(reg_idx, reg_data); 8135 } 8136 } 8137 8138 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8139 bool enable) 8140 { 8141 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8142 8143 if (enable) { 8144 /* enable FGCG firstly*/ 8145 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8146 /* CGCG/CGLS should be enabled after MGCG/MGLS 8147 * === MGCG + MGLS === 8148 */ 8149 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8150 /* === CGCG /CGLS for GFX 3D Only === */ 8151 gfx_v10_0_update_3d_clock_gating(adev, enable); 8152 /* === CGCG + CGLS === */ 8153 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8154 8155 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8156 IP_VERSION(10, 1, 10)) || 8157 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8158 IP_VERSION(10, 1, 1)) || 8159 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8160 IP_VERSION(10, 1, 2))) 8161 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8162 } else { 8163 /* CGCG/CGLS should be disabled before MGCG/MGLS 8164 * === CGCG + CGLS === 8165 */ 8166 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8167 /* === CGCG /CGLS for GFX 3D Only === */ 8168 gfx_v10_0_update_3d_clock_gating(adev, enable); 8169 /* === MGCG + MGLS === */ 8170 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8171 /* disable fgcg at last*/ 8172 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8173 } 8174 8175 if (adev->cg_flags & 8176 (AMD_CG_SUPPORT_GFX_MGCG | 8177 AMD_CG_SUPPORT_GFX_CGLS | 8178 AMD_CG_SUPPORT_GFX_CGCG | 8179 AMD_CG_SUPPORT_GFX_3D_CGCG | 8180 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8181 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8182 8183 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8184 8185 return 0; 8186 } 8187 8188 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8189 unsigned int vmid) 8190 { 8191 u32 reg, pre_data, data; 8192 8193 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8194 /* not for *_SOC15 */ 8195 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8196 pre_data = RREG32_NO_KIQ(reg); 8197 else 8198 pre_data = RREG32(reg); 8199 8200 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8201 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8202 8203 if (pre_data != data) { 8204 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8205 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8206 } else 8207 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8208 } 8209 } 8210 8211 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8212 { 8213 amdgpu_gfx_off_ctrl(adev, false); 8214 8215 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8216 8217 amdgpu_gfx_off_ctrl(adev, true); 8218 } 8219 8220 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8221 uint32_t offset, 8222 struct soc15_reg_rlcg *entries, int arr_size) 8223 { 8224 int i; 8225 uint32_t reg; 8226 8227 if (!entries) 8228 return false; 8229 8230 for (i = 0; i < arr_size; i++) { 8231 const struct soc15_reg_rlcg *entry; 8232 8233 entry = &entries[i]; 8234 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8235 if (offset == reg) 8236 return true; 8237 } 8238 8239 return false; 8240 } 8241 8242 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8243 { 8244 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8245 } 8246 8247 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8248 { 8249 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8250 8251 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8252 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8253 else 8254 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8255 8256 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8257 8258 /* 8259 * CGPG enablement required and the register to program the hysteresis value 8260 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8261 * in refclk count. Note that RLC FW is modified to take 16 bits from 8262 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8263 * 8264 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8265 * of CGPG enablement starting point. 8266 * Power/performance team will optimize it and might give a new value later. 8267 */ 8268 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8269 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8270 case IP_VERSION(10, 3, 1): 8271 case IP_VERSION(10, 3, 3): 8272 case IP_VERSION(10, 3, 6): 8273 case IP_VERSION(10, 3, 7): 8274 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8275 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8276 break; 8277 default: 8278 break; 8279 } 8280 } 8281 } 8282 8283 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8284 { 8285 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8286 8287 gfx_v10_cntl_power_gating(adev, enable); 8288 8289 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8290 } 8291 8292 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8293 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8294 .set_safe_mode = gfx_v10_0_set_safe_mode, 8295 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8296 .init = gfx_v10_0_rlc_init, 8297 .get_csb_size = gfx_v10_0_get_csb_size, 8298 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8299 .resume = gfx_v10_0_rlc_resume, 8300 .stop = gfx_v10_0_rlc_stop, 8301 .reset = gfx_v10_0_rlc_reset, 8302 .start = gfx_v10_0_rlc_start, 8303 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8304 }; 8305 8306 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8307 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8308 .set_safe_mode = gfx_v10_0_set_safe_mode, 8309 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8310 .init = gfx_v10_0_rlc_init, 8311 .get_csb_size = gfx_v10_0_get_csb_size, 8312 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8313 .resume = gfx_v10_0_rlc_resume, 8314 .stop = gfx_v10_0_rlc_stop, 8315 .reset = gfx_v10_0_rlc_reset, 8316 .start = gfx_v10_0_rlc_start, 8317 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8318 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8319 }; 8320 8321 static int gfx_v10_0_set_powergating_state(void *handle, 8322 enum amd_powergating_state state) 8323 { 8324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8325 bool enable = (state == AMD_PG_STATE_GATE); 8326 8327 if (amdgpu_sriov_vf(adev)) 8328 return 0; 8329 8330 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8331 case IP_VERSION(10, 1, 10): 8332 case IP_VERSION(10, 1, 1): 8333 case IP_VERSION(10, 1, 2): 8334 case IP_VERSION(10, 3, 0): 8335 case IP_VERSION(10, 3, 2): 8336 case IP_VERSION(10, 3, 4): 8337 case IP_VERSION(10, 3, 5): 8338 amdgpu_gfx_off_ctrl(adev, enable); 8339 break; 8340 case IP_VERSION(10, 3, 1): 8341 case IP_VERSION(10, 3, 3): 8342 case IP_VERSION(10, 3, 6): 8343 case IP_VERSION(10, 3, 7): 8344 if (!enable) 8345 amdgpu_gfx_off_ctrl(adev, false); 8346 8347 gfx_v10_cntl_pg(adev, enable); 8348 8349 if (enable) 8350 amdgpu_gfx_off_ctrl(adev, true); 8351 8352 break; 8353 default: 8354 break; 8355 } 8356 return 0; 8357 } 8358 8359 static int gfx_v10_0_set_clockgating_state(void *handle, 8360 enum amd_clockgating_state state) 8361 { 8362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8363 8364 if (amdgpu_sriov_vf(adev)) 8365 return 0; 8366 8367 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8368 case IP_VERSION(10, 1, 10): 8369 case IP_VERSION(10, 1, 1): 8370 case IP_VERSION(10, 1, 2): 8371 case IP_VERSION(10, 3, 0): 8372 case IP_VERSION(10, 3, 2): 8373 case IP_VERSION(10, 3, 1): 8374 case IP_VERSION(10, 3, 4): 8375 case IP_VERSION(10, 3, 5): 8376 case IP_VERSION(10, 3, 6): 8377 case IP_VERSION(10, 3, 3): 8378 case IP_VERSION(10, 3, 7): 8379 gfx_v10_0_update_gfx_clock_gating(adev, 8380 state == AMD_CG_STATE_GATE); 8381 break; 8382 default: 8383 break; 8384 } 8385 return 0; 8386 } 8387 8388 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8389 { 8390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8391 int data; 8392 8393 /* AMD_CG_SUPPORT_GFX_FGCG */ 8394 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8395 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8396 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8397 8398 /* AMD_CG_SUPPORT_GFX_MGCG */ 8399 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8400 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8401 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8402 8403 /* AMD_CG_SUPPORT_GFX_CGCG */ 8404 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8405 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8406 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8407 8408 /* AMD_CG_SUPPORT_GFX_CGLS */ 8409 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8410 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8411 8412 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8413 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8414 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8415 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8416 8417 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8418 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8419 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8420 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8421 8422 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8423 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8424 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8425 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8426 8427 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8428 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8429 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8430 } 8431 8432 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8433 { 8434 /* gfx10 is 32bit rptr*/ 8435 return *(uint32_t *)ring->rptr_cpu_addr; 8436 } 8437 8438 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8439 { 8440 struct amdgpu_device *adev = ring->adev; 8441 u64 wptr; 8442 8443 /* XXX check if swapping is necessary on BE */ 8444 if (ring->use_doorbell) { 8445 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8446 } else { 8447 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8448 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8449 } 8450 8451 return wptr; 8452 } 8453 8454 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8455 { 8456 struct amdgpu_device *adev = ring->adev; 8457 8458 if (ring->use_doorbell) { 8459 /* XXX check if swapping is necessary on BE */ 8460 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8461 ring->wptr); 8462 WDOORBELL64(ring->doorbell_index, ring->wptr); 8463 } else { 8464 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8465 lower_32_bits(ring->wptr)); 8466 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8467 upper_32_bits(ring->wptr)); 8468 } 8469 } 8470 8471 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8472 { 8473 /* gfx10 hardware is 32bit rptr */ 8474 return *(uint32_t *)ring->rptr_cpu_addr; 8475 } 8476 8477 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8478 { 8479 u64 wptr; 8480 8481 /* XXX check if swapping is necessary on BE */ 8482 if (ring->use_doorbell) 8483 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8484 else 8485 BUG(); 8486 return wptr; 8487 } 8488 8489 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8490 { 8491 struct amdgpu_device *adev = ring->adev; 8492 8493 if (ring->use_doorbell) { 8494 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8495 ring->wptr); 8496 WDOORBELL64(ring->doorbell_index, ring->wptr); 8497 } else { 8498 BUG(); /* only DOORBELL method supported on gfx10 now */ 8499 } 8500 } 8501 8502 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8503 { 8504 struct amdgpu_device *adev = ring->adev; 8505 u32 ref_and_mask, reg_mem_engine; 8506 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8507 8508 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8509 switch (ring->me) { 8510 case 1: 8511 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8512 break; 8513 case 2: 8514 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8515 break; 8516 default: 8517 return; 8518 } 8519 reg_mem_engine = 0; 8520 } else { 8521 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8522 reg_mem_engine = 1; /* pfp */ 8523 } 8524 8525 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8526 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8527 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8528 ref_and_mask, ref_and_mask, 0x20); 8529 } 8530 8531 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8532 struct amdgpu_job *job, 8533 struct amdgpu_ib *ib, 8534 uint32_t flags) 8535 { 8536 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8537 u32 header, control = 0; 8538 8539 if (ib->flags & AMDGPU_IB_FLAG_CE) 8540 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8541 else 8542 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8543 8544 control |= ib->length_dw | (vmid << 24); 8545 8546 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8547 control |= INDIRECT_BUFFER_PRE_ENB(1); 8548 8549 if (flags & AMDGPU_IB_PREEMPTED) 8550 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8551 8552 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8553 gfx_v10_0_ring_emit_de_meta(ring, 8554 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8555 } 8556 8557 amdgpu_ring_write(ring, header); 8558 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8559 amdgpu_ring_write(ring, 8560 #ifdef __BIG_ENDIAN 8561 (2 << 0) | 8562 #endif 8563 lower_32_bits(ib->gpu_addr)); 8564 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8565 amdgpu_ring_write(ring, control); 8566 } 8567 8568 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8569 struct amdgpu_job *job, 8570 struct amdgpu_ib *ib, 8571 uint32_t flags) 8572 { 8573 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8574 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8575 8576 /* Currently, there is a high possibility to get wave ID mismatch 8577 * between ME and GDS, leading to a hw deadlock, because ME generates 8578 * different wave IDs than the GDS expects. This situation happens 8579 * randomly when at least 5 compute pipes use GDS ordered append. 8580 * The wave IDs generated by ME are also wrong after suspend/resume. 8581 * Those are probably bugs somewhere else in the kernel driver. 8582 * 8583 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8584 * GDS to 0 for this ring (me/pipe). 8585 */ 8586 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8587 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8588 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8589 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8590 } 8591 8592 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8593 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8594 amdgpu_ring_write(ring, 8595 #ifdef __BIG_ENDIAN 8596 (2 << 0) | 8597 #endif 8598 lower_32_bits(ib->gpu_addr)); 8599 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8600 amdgpu_ring_write(ring, control); 8601 } 8602 8603 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8604 u64 seq, unsigned int flags) 8605 { 8606 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8607 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8608 8609 /* RELEASE_MEM - flush caches, send int */ 8610 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8611 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8612 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8613 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8614 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8615 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8616 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8617 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8618 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8619 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8620 8621 /* 8622 * the address should be Qword aligned if 64bit write, Dword 8623 * aligned if only send 32bit data low (discard data high) 8624 */ 8625 if (write64bit) 8626 BUG_ON(addr & 0x7); 8627 else 8628 BUG_ON(addr & 0x3); 8629 amdgpu_ring_write(ring, lower_32_bits(addr)); 8630 amdgpu_ring_write(ring, upper_32_bits(addr)); 8631 amdgpu_ring_write(ring, lower_32_bits(seq)); 8632 amdgpu_ring_write(ring, upper_32_bits(seq)); 8633 amdgpu_ring_write(ring, 0); 8634 } 8635 8636 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8637 { 8638 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8639 uint32_t seq = ring->fence_drv.sync_seq; 8640 uint64_t addr = ring->fence_drv.gpu_addr; 8641 8642 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8643 upper_32_bits(addr), seq, 0xffffffff, 4); 8644 } 8645 8646 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8647 uint16_t pasid, uint32_t flush_type, 8648 bool all_hub, uint8_t dst_sel) 8649 { 8650 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8651 amdgpu_ring_write(ring, 8652 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8653 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8654 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8655 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8656 } 8657 8658 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8659 unsigned int vmid, uint64_t pd_addr) 8660 { 8661 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8662 8663 /* compute doesn't have PFP */ 8664 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8665 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8666 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8667 amdgpu_ring_write(ring, 0x0); 8668 } 8669 } 8670 8671 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8672 u64 seq, unsigned int flags) 8673 { 8674 struct amdgpu_device *adev = ring->adev; 8675 8676 /* we only allocate 32bit for each seq wb address */ 8677 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8678 8679 /* write fence seq to the "addr" */ 8680 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8681 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8682 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8683 amdgpu_ring_write(ring, lower_32_bits(addr)); 8684 amdgpu_ring_write(ring, upper_32_bits(addr)); 8685 amdgpu_ring_write(ring, lower_32_bits(seq)); 8686 8687 if (flags & AMDGPU_FENCE_FLAG_INT) { 8688 /* set register to trigger INT */ 8689 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8690 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8691 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8692 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8693 amdgpu_ring_write(ring, 0); 8694 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8695 } 8696 } 8697 8698 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8699 { 8700 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8701 amdgpu_ring_write(ring, 0); 8702 } 8703 8704 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8705 uint32_t flags) 8706 { 8707 uint32_t dw2 = 0; 8708 8709 if (ring->adev->gfx.mcbp) 8710 gfx_v10_0_ring_emit_ce_meta(ring, 8711 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8712 8713 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8714 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8715 /* set load_global_config & load_global_uconfig */ 8716 dw2 |= 0x8001; 8717 /* set load_cs_sh_regs */ 8718 dw2 |= 0x01000000; 8719 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8720 dw2 |= 0x10002; 8721 8722 /* set load_ce_ram if preamble presented */ 8723 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8724 dw2 |= 0x10000000; 8725 } else { 8726 /* still load_ce_ram if this is the first time preamble presented 8727 * although there is no context switch happens. 8728 */ 8729 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8730 dw2 |= 0x10000000; 8731 } 8732 8733 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8734 amdgpu_ring_write(ring, dw2); 8735 amdgpu_ring_write(ring, 0); 8736 } 8737 8738 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8739 uint64_t addr) 8740 { 8741 unsigned int ret; 8742 8743 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8744 amdgpu_ring_write(ring, lower_32_bits(addr)); 8745 amdgpu_ring_write(ring, upper_32_bits(addr)); 8746 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8747 amdgpu_ring_write(ring, 0); 8748 ret = ring->wptr & ring->buf_mask; 8749 /* patch dummy value later */ 8750 amdgpu_ring_write(ring, 0); 8751 8752 return ret; 8753 } 8754 8755 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8756 { 8757 int i, r = 0; 8758 struct amdgpu_device *adev = ring->adev; 8759 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8760 struct amdgpu_ring *kiq_ring = &kiq->ring; 8761 unsigned long flags; 8762 8763 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8764 return -EINVAL; 8765 8766 spin_lock_irqsave(&kiq->ring_lock, flags); 8767 8768 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8769 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8770 return -ENOMEM; 8771 } 8772 8773 /* assert preemption condition */ 8774 amdgpu_ring_set_preempt_cond_exec(ring, false); 8775 8776 /* assert IB preemption, emit the trailing fence */ 8777 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8778 ring->trail_fence_gpu_addr, 8779 ++ring->trail_seq); 8780 amdgpu_ring_commit(kiq_ring); 8781 8782 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8783 8784 /* poll the trailing fence */ 8785 for (i = 0; i < adev->usec_timeout; i++) { 8786 if (ring->trail_seq == 8787 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8788 break; 8789 udelay(1); 8790 } 8791 8792 if (i >= adev->usec_timeout) { 8793 r = -EINVAL; 8794 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8795 } 8796 8797 /* deassert preemption condition */ 8798 amdgpu_ring_set_preempt_cond_exec(ring, true); 8799 return r; 8800 } 8801 8802 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8803 { 8804 struct amdgpu_device *adev = ring->adev; 8805 struct v10_ce_ib_state ce_payload = {0}; 8806 uint64_t offset, ce_payload_gpu_addr; 8807 void *ce_payload_cpu_addr; 8808 int cnt; 8809 8810 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8811 8812 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8813 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8814 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8815 8816 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8817 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8818 WRITE_DATA_DST_SEL(8) | 8819 WR_CONFIRM) | 8820 WRITE_DATA_CACHE_POLICY(0)); 8821 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8822 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8823 8824 if (resume) 8825 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8826 sizeof(ce_payload) >> 2); 8827 else 8828 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8829 sizeof(ce_payload) >> 2); 8830 } 8831 8832 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8833 { 8834 struct amdgpu_device *adev = ring->adev; 8835 struct v10_de_ib_state de_payload = {0}; 8836 uint64_t offset, gds_addr, de_payload_gpu_addr; 8837 void *de_payload_cpu_addr; 8838 int cnt; 8839 8840 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8841 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8842 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8843 8844 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8845 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8846 PAGE_SIZE); 8847 8848 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8849 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8850 8851 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8852 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8853 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8854 WRITE_DATA_DST_SEL(8) | 8855 WR_CONFIRM) | 8856 WRITE_DATA_CACHE_POLICY(0)); 8857 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8858 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8859 8860 if (resume) 8861 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8862 sizeof(de_payload) >> 2); 8863 else 8864 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8865 sizeof(de_payload) >> 2); 8866 } 8867 8868 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8869 bool secure) 8870 { 8871 uint32_t v = secure ? FRAME_TMZ : 0; 8872 8873 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8874 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8875 } 8876 8877 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8878 uint32_t reg_val_offs) 8879 { 8880 struct amdgpu_device *adev = ring->adev; 8881 8882 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8883 amdgpu_ring_write(ring, 0 | /* src: register*/ 8884 (5 << 8) | /* dst: memory */ 8885 (1 << 20)); /* write confirm */ 8886 amdgpu_ring_write(ring, reg); 8887 amdgpu_ring_write(ring, 0); 8888 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8889 reg_val_offs * 4)); 8890 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8891 reg_val_offs * 4)); 8892 } 8893 8894 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8895 uint32_t val) 8896 { 8897 uint32_t cmd = 0; 8898 8899 switch (ring->funcs->type) { 8900 case AMDGPU_RING_TYPE_GFX: 8901 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8902 break; 8903 case AMDGPU_RING_TYPE_KIQ: 8904 cmd = (1 << 16); /* no inc addr */ 8905 break; 8906 default: 8907 cmd = WR_CONFIRM; 8908 break; 8909 } 8910 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8911 amdgpu_ring_write(ring, cmd); 8912 amdgpu_ring_write(ring, reg); 8913 amdgpu_ring_write(ring, 0); 8914 amdgpu_ring_write(ring, val); 8915 } 8916 8917 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8918 uint32_t val, uint32_t mask) 8919 { 8920 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8921 } 8922 8923 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8924 uint32_t reg0, uint32_t reg1, 8925 uint32_t ref, uint32_t mask) 8926 { 8927 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8928 struct amdgpu_device *adev = ring->adev; 8929 bool fw_version_ok = false; 8930 8931 fw_version_ok = adev->gfx.cp_fw_write_wait; 8932 8933 if (fw_version_ok) 8934 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8935 ref, mask, 0x20); 8936 else 8937 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8938 ref, mask); 8939 } 8940 8941 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8942 unsigned int vmid) 8943 { 8944 struct amdgpu_device *adev = ring->adev; 8945 uint32_t value = 0; 8946 8947 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8948 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8949 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8950 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8951 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8952 } 8953 8954 static void 8955 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8956 uint32_t me, uint32_t pipe, 8957 enum amdgpu_interrupt_state state) 8958 { 8959 uint32_t cp_int_cntl, cp_int_cntl_reg; 8960 8961 if (!me) { 8962 switch (pipe) { 8963 case 0: 8964 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8965 break; 8966 case 1: 8967 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8968 break; 8969 default: 8970 DRM_DEBUG("invalid pipe %d\n", pipe); 8971 return; 8972 } 8973 } else { 8974 DRM_DEBUG("invalid me %d\n", me); 8975 return; 8976 } 8977 8978 switch (state) { 8979 case AMDGPU_IRQ_STATE_DISABLE: 8980 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8981 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8982 TIME_STAMP_INT_ENABLE, 0); 8983 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8984 break; 8985 case AMDGPU_IRQ_STATE_ENABLE: 8986 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8987 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8988 TIME_STAMP_INT_ENABLE, 1); 8989 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8990 break; 8991 default: 8992 break; 8993 } 8994 } 8995 8996 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8997 int me, int pipe, 8998 enum amdgpu_interrupt_state state) 8999 { 9000 u32 mec_int_cntl, mec_int_cntl_reg; 9001 9002 /* 9003 * amdgpu controls only the first MEC. That's why this function only 9004 * handles the setting of interrupts for this specific MEC. All other 9005 * pipes' interrupts are set by amdkfd. 9006 */ 9007 9008 if (me == 1) { 9009 switch (pipe) { 9010 case 0: 9011 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9012 break; 9013 case 1: 9014 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9015 break; 9016 case 2: 9017 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9018 break; 9019 case 3: 9020 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9021 break; 9022 default: 9023 DRM_DEBUG("invalid pipe %d\n", pipe); 9024 return; 9025 } 9026 } else { 9027 DRM_DEBUG("invalid me %d\n", me); 9028 return; 9029 } 9030 9031 switch (state) { 9032 case AMDGPU_IRQ_STATE_DISABLE: 9033 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9034 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9035 TIME_STAMP_INT_ENABLE, 0); 9036 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9037 break; 9038 case AMDGPU_IRQ_STATE_ENABLE: 9039 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9040 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9041 TIME_STAMP_INT_ENABLE, 1); 9042 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9043 break; 9044 default: 9045 break; 9046 } 9047 } 9048 9049 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9050 struct amdgpu_irq_src *src, 9051 unsigned int type, 9052 enum amdgpu_interrupt_state state) 9053 { 9054 switch (type) { 9055 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9056 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9057 break; 9058 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9059 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9060 break; 9061 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9062 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9063 break; 9064 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9065 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9066 break; 9067 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9068 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9069 break; 9070 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9071 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9072 break; 9073 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9074 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9075 break; 9076 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9077 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9078 break; 9079 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9080 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9081 break; 9082 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9083 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9084 break; 9085 default: 9086 break; 9087 } 9088 return 0; 9089 } 9090 9091 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9092 struct amdgpu_irq_src *source, 9093 struct amdgpu_iv_entry *entry) 9094 { 9095 int i; 9096 u8 me_id, pipe_id, queue_id; 9097 struct amdgpu_ring *ring; 9098 9099 DRM_DEBUG("IH: CP EOP\n"); 9100 9101 me_id = (entry->ring_id & 0x0c) >> 2; 9102 pipe_id = (entry->ring_id & 0x03) >> 0; 9103 queue_id = (entry->ring_id & 0x70) >> 4; 9104 9105 switch (me_id) { 9106 case 0: 9107 if (pipe_id == 0) 9108 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9109 else 9110 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9111 break; 9112 case 1: 9113 case 2: 9114 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9115 ring = &adev->gfx.compute_ring[i]; 9116 /* Per-queue interrupt is supported for MEC starting from VI. 9117 * The interrupt can only be enabled/disabled per pipe instead 9118 * of per queue. 9119 */ 9120 if ((ring->me == me_id) && 9121 (ring->pipe == pipe_id) && 9122 (ring->queue == queue_id)) 9123 amdgpu_fence_process(ring); 9124 } 9125 break; 9126 } 9127 9128 return 0; 9129 } 9130 9131 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9132 struct amdgpu_irq_src *source, 9133 unsigned int type, 9134 enum amdgpu_interrupt_state state) 9135 { 9136 u32 cp_int_cntl_reg, cp_int_cntl; 9137 int i, j; 9138 9139 switch (state) { 9140 case AMDGPU_IRQ_STATE_DISABLE: 9141 case AMDGPU_IRQ_STATE_ENABLE: 9142 for (i = 0; i < adev->gfx.me.num_me; i++) { 9143 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9144 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9145 9146 if (cp_int_cntl_reg) { 9147 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9148 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9149 PRIV_REG_INT_ENABLE, 9150 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9151 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9152 } 9153 } 9154 } 9155 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9156 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9157 /* MECs start at 1 */ 9158 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9159 9160 if (cp_int_cntl_reg) { 9161 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9162 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9163 PRIV_REG_INT_ENABLE, 9164 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9165 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9166 } 9167 } 9168 } 9169 break; 9170 default: 9171 break; 9172 } 9173 9174 return 0; 9175 } 9176 9177 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9178 struct amdgpu_irq_src *source, 9179 unsigned type, 9180 enum amdgpu_interrupt_state state) 9181 { 9182 u32 cp_int_cntl_reg, cp_int_cntl; 9183 int i, j; 9184 9185 switch (state) { 9186 case AMDGPU_IRQ_STATE_DISABLE: 9187 case AMDGPU_IRQ_STATE_ENABLE: 9188 for (i = 0; i < adev->gfx.me.num_me; i++) { 9189 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9190 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9191 9192 if (cp_int_cntl_reg) { 9193 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9194 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9195 OPCODE_ERROR_INT_ENABLE, 9196 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9197 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9198 } 9199 } 9200 } 9201 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9202 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9203 /* MECs start at 1 */ 9204 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9205 9206 if (cp_int_cntl_reg) { 9207 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9208 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9209 OPCODE_ERROR_INT_ENABLE, 9210 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9211 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9212 } 9213 } 9214 } 9215 break; 9216 default: 9217 break; 9218 } 9219 return 0; 9220 } 9221 9222 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9223 struct amdgpu_irq_src *source, 9224 unsigned int type, 9225 enum amdgpu_interrupt_state state) 9226 { 9227 u32 cp_int_cntl_reg, cp_int_cntl; 9228 int i, j; 9229 9230 switch (state) { 9231 case AMDGPU_IRQ_STATE_DISABLE: 9232 case AMDGPU_IRQ_STATE_ENABLE: 9233 for (i = 0; i < adev->gfx.me.num_me; i++) { 9234 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9235 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9236 9237 if (cp_int_cntl_reg) { 9238 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9239 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9240 PRIV_INSTR_INT_ENABLE, 9241 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9242 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9243 } 9244 } 9245 } 9246 break; 9247 default: 9248 break; 9249 } 9250 9251 return 0; 9252 } 9253 9254 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9255 struct amdgpu_iv_entry *entry) 9256 { 9257 u8 me_id, pipe_id, queue_id; 9258 struct amdgpu_ring *ring; 9259 int i; 9260 9261 me_id = (entry->ring_id & 0x0c) >> 2; 9262 pipe_id = (entry->ring_id & 0x03) >> 0; 9263 queue_id = (entry->ring_id & 0x70) >> 4; 9264 9265 switch (me_id) { 9266 case 0: 9267 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9268 ring = &adev->gfx.gfx_ring[i]; 9269 if (ring->me == me_id && ring->pipe == pipe_id && 9270 ring->queue == queue_id) 9271 drm_sched_fault(&ring->sched); 9272 } 9273 break; 9274 case 1: 9275 case 2: 9276 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9277 ring = &adev->gfx.compute_ring[i]; 9278 if (ring->me == me_id && ring->pipe == pipe_id && 9279 ring->queue == queue_id) 9280 drm_sched_fault(&ring->sched); 9281 } 9282 break; 9283 default: 9284 BUG(); 9285 } 9286 } 9287 9288 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9289 struct amdgpu_irq_src *source, 9290 struct amdgpu_iv_entry *entry) 9291 { 9292 DRM_ERROR("Illegal register access in command stream\n"); 9293 gfx_v10_0_handle_priv_fault(adev, entry); 9294 return 0; 9295 } 9296 9297 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9298 struct amdgpu_irq_src *source, 9299 struct amdgpu_iv_entry *entry) 9300 { 9301 DRM_ERROR("Illegal opcode in command stream \n"); 9302 gfx_v10_0_handle_priv_fault(adev, entry); 9303 return 0; 9304 } 9305 9306 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9307 struct amdgpu_irq_src *source, 9308 struct amdgpu_iv_entry *entry) 9309 { 9310 DRM_ERROR("Illegal instruction in command stream\n"); 9311 gfx_v10_0_handle_priv_fault(adev, entry); 9312 return 0; 9313 } 9314 9315 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9316 struct amdgpu_irq_src *src, 9317 unsigned int type, 9318 enum amdgpu_interrupt_state state) 9319 { 9320 uint32_t tmp, target; 9321 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9322 9323 if (ring->me == 1) 9324 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9325 else 9326 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9327 target += ring->pipe; 9328 9329 switch (type) { 9330 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9331 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9332 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9333 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9334 GENERIC2_INT_ENABLE, 0); 9335 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9336 9337 tmp = RREG32_SOC15_IP(GC, target); 9338 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9339 GENERIC2_INT_ENABLE, 0); 9340 WREG32_SOC15_IP(GC, target, tmp); 9341 } else { 9342 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9343 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9344 GENERIC2_INT_ENABLE, 1); 9345 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9346 9347 tmp = RREG32_SOC15_IP(GC, target); 9348 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9349 GENERIC2_INT_ENABLE, 1); 9350 WREG32_SOC15_IP(GC, target, tmp); 9351 } 9352 break; 9353 default: 9354 BUG(); /* kiq only support GENERIC2_INT now */ 9355 break; 9356 } 9357 return 0; 9358 } 9359 9360 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9361 struct amdgpu_irq_src *source, 9362 struct amdgpu_iv_entry *entry) 9363 { 9364 u8 me_id, pipe_id, queue_id; 9365 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9366 9367 me_id = (entry->ring_id & 0x0c) >> 2; 9368 pipe_id = (entry->ring_id & 0x03) >> 0; 9369 queue_id = (entry->ring_id & 0x70) >> 4; 9370 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9371 me_id, pipe_id, queue_id); 9372 9373 amdgpu_fence_process(ring); 9374 return 0; 9375 } 9376 9377 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9378 { 9379 const unsigned int gcr_cntl = 9380 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9381 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9382 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9383 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9384 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9385 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9386 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9387 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9388 9389 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9390 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9391 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9392 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9393 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9394 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9395 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9396 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9397 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9398 } 9399 9400 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9401 { 9402 int i; 9403 9404 /* Header itself is a NOP packet */ 9405 if (num_nop == 1) { 9406 amdgpu_ring_write(ring, ring->funcs->nop); 9407 return; 9408 } 9409 9410 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9411 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9412 9413 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9414 for (i = 1; i < num_nop; i++) 9415 amdgpu_ring_write(ring, ring->funcs->nop); 9416 } 9417 9418 static void gfx_v10_ip_print(void *handle, struct drm_printer *p) 9419 { 9420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9421 uint32_t i, j, k, reg, index = 0; 9422 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9423 9424 if (!adev->gfx.ip_dump_core) 9425 return; 9426 9427 for (i = 0; i < reg_count; i++) 9428 drm_printf(p, "%-50s \t 0x%08x\n", 9429 gc_reg_list_10_1[i].reg_name, 9430 adev->gfx.ip_dump_core[i]); 9431 9432 /* print compute queue registers for all instances */ 9433 if (!adev->gfx.ip_dump_compute_queues) 9434 return; 9435 9436 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9437 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9438 adev->gfx.mec.num_mec, 9439 adev->gfx.mec.num_pipe_per_mec, 9440 adev->gfx.mec.num_queue_per_pipe); 9441 9442 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9443 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9444 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9445 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9446 for (reg = 0; reg < reg_count; reg++) { 9447 drm_printf(p, "%-50s \t 0x%08x\n", 9448 gc_cp_reg_list_10[reg].reg_name, 9449 adev->gfx.ip_dump_compute_queues[index + reg]); 9450 } 9451 index += reg_count; 9452 } 9453 } 9454 } 9455 9456 /* print gfx queue registers for all instances */ 9457 if (!adev->gfx.ip_dump_gfx_queues) 9458 return; 9459 9460 index = 0; 9461 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9462 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9463 adev->gfx.me.num_me, 9464 adev->gfx.me.num_pipe_per_me, 9465 adev->gfx.me.num_queue_per_pipe); 9466 9467 for (i = 0; i < adev->gfx.me.num_me; i++) { 9468 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9469 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9470 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9471 for (reg = 0; reg < reg_count; reg++) { 9472 drm_printf(p, "%-50s \t 0x%08x\n", 9473 gc_gfx_queue_reg_list_10[reg].reg_name, 9474 adev->gfx.ip_dump_gfx_queues[index + reg]); 9475 } 9476 index += reg_count; 9477 } 9478 } 9479 } 9480 } 9481 9482 static void gfx_v10_ip_dump(void *handle) 9483 { 9484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9485 uint32_t i, j, k, reg, index = 0; 9486 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9487 9488 if (!adev->gfx.ip_dump_core) 9489 return; 9490 9491 amdgpu_gfx_off_ctrl(adev, false); 9492 for (i = 0; i < reg_count; i++) 9493 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9494 amdgpu_gfx_off_ctrl(adev, true); 9495 9496 /* dump compute queue registers for all instances */ 9497 if (!adev->gfx.ip_dump_compute_queues) 9498 return; 9499 9500 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9501 amdgpu_gfx_off_ctrl(adev, false); 9502 mutex_lock(&adev->srbm_mutex); 9503 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9504 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9505 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9506 /* ME0 is for GFX so start from 1 for CP */ 9507 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9508 9509 for (reg = 0; reg < reg_count; reg++) { 9510 adev->gfx.ip_dump_compute_queues[index + reg] = 9511 RREG32(SOC15_REG_ENTRY_OFFSET( 9512 gc_cp_reg_list_10[reg])); 9513 } 9514 index += reg_count; 9515 } 9516 } 9517 } 9518 nv_grbm_select(adev, 0, 0, 0, 0); 9519 mutex_unlock(&adev->srbm_mutex); 9520 amdgpu_gfx_off_ctrl(adev, true); 9521 9522 /* dump gfx queue registers for all instances */ 9523 if (!adev->gfx.ip_dump_gfx_queues) 9524 return; 9525 9526 index = 0; 9527 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9528 amdgpu_gfx_off_ctrl(adev, false); 9529 mutex_lock(&adev->srbm_mutex); 9530 for (i = 0; i < adev->gfx.me.num_me; i++) { 9531 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9532 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9533 nv_grbm_select(adev, i, j, k, 0); 9534 9535 for (reg = 0; reg < reg_count; reg++) { 9536 adev->gfx.ip_dump_gfx_queues[index + reg] = 9537 RREG32(SOC15_REG_ENTRY_OFFSET( 9538 gc_gfx_queue_reg_list_10[reg])); 9539 } 9540 index += reg_count; 9541 } 9542 } 9543 } 9544 nv_grbm_select(adev, 0, 0, 0, 0); 9545 mutex_unlock(&adev->srbm_mutex); 9546 amdgpu_gfx_off_ctrl(adev, true); 9547 } 9548 9549 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9550 .name = "gfx_v10_0", 9551 .early_init = gfx_v10_0_early_init, 9552 .late_init = gfx_v10_0_late_init, 9553 .sw_init = gfx_v10_0_sw_init, 9554 .sw_fini = gfx_v10_0_sw_fini, 9555 .hw_init = gfx_v10_0_hw_init, 9556 .hw_fini = gfx_v10_0_hw_fini, 9557 .suspend = gfx_v10_0_suspend, 9558 .resume = gfx_v10_0_resume, 9559 .is_idle = gfx_v10_0_is_idle, 9560 .wait_for_idle = gfx_v10_0_wait_for_idle, 9561 .soft_reset = gfx_v10_0_soft_reset, 9562 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9563 .set_powergating_state = gfx_v10_0_set_powergating_state, 9564 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9565 .dump_ip_state = gfx_v10_ip_dump, 9566 .print_ip_state = gfx_v10_ip_print, 9567 }; 9568 9569 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9570 .type = AMDGPU_RING_TYPE_GFX, 9571 .align_mask = 0xff, 9572 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9573 .support_64bit_ptrs = true, 9574 .secure_submission_supported = true, 9575 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9576 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9577 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9578 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9579 5 + /* COND_EXEC */ 9580 7 + /* PIPELINE_SYNC */ 9581 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9582 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9583 4 + /* VM_FLUSH */ 9584 8 + /* FENCE for VM_FLUSH */ 9585 20 + /* GDS switch */ 9586 4 + /* double SWITCH_BUFFER, 9587 * the first COND_EXEC jump to the place 9588 * just prior to this double SWITCH_BUFFER 9589 */ 9590 5 + /* COND_EXEC */ 9591 7 + /* HDP_flush */ 9592 4 + /* VGT_flush */ 9593 14 + /* CE_META */ 9594 31 + /* DE_META */ 9595 3 + /* CNTX_CTRL */ 9596 5 + /* HDP_INVL */ 9597 8 + 8 + /* FENCE x2 */ 9598 2 + /* SWITCH_BUFFER */ 9599 8, /* gfx_v10_0_emit_mem_sync */ 9600 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9601 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9602 .emit_fence = gfx_v10_0_ring_emit_fence, 9603 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9604 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9605 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9606 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9607 .test_ring = gfx_v10_0_ring_test_ring, 9608 .test_ib = gfx_v10_0_ring_test_ib, 9609 .insert_nop = gfx_v10_ring_insert_nop, 9610 .pad_ib = amdgpu_ring_generic_pad_ib, 9611 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9612 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9613 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9614 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9615 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9616 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9617 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9618 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9619 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9620 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9621 }; 9622 9623 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9624 .type = AMDGPU_RING_TYPE_COMPUTE, 9625 .align_mask = 0xff, 9626 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9627 .support_64bit_ptrs = true, 9628 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9629 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9630 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9631 .emit_frame_size = 9632 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9633 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9634 5 + /* hdp invalidate */ 9635 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9636 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9637 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9638 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9639 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9640 8, /* gfx_v10_0_emit_mem_sync */ 9641 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9642 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9643 .emit_fence = gfx_v10_0_ring_emit_fence, 9644 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9645 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9646 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9647 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9648 .test_ring = gfx_v10_0_ring_test_ring, 9649 .test_ib = gfx_v10_0_ring_test_ib, 9650 .insert_nop = gfx_v10_ring_insert_nop, 9651 .pad_ib = amdgpu_ring_generic_pad_ib, 9652 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9653 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9654 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9655 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9656 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9657 }; 9658 9659 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9660 .type = AMDGPU_RING_TYPE_KIQ, 9661 .align_mask = 0xff, 9662 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9663 .support_64bit_ptrs = true, 9664 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9665 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9666 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9667 .emit_frame_size = 9668 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9669 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9670 5 + /*hdp invalidate */ 9671 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9672 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9673 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9674 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9675 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9676 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9677 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9678 .test_ring = gfx_v10_0_ring_test_ring, 9679 .test_ib = gfx_v10_0_ring_test_ib, 9680 .insert_nop = amdgpu_ring_insert_nop, 9681 .pad_ib = amdgpu_ring_generic_pad_ib, 9682 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9683 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9684 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9685 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9686 }; 9687 9688 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9689 { 9690 int i; 9691 9692 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9693 9694 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9695 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9696 9697 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9698 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9699 } 9700 9701 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9702 .set = gfx_v10_0_set_eop_interrupt_state, 9703 .process = gfx_v10_0_eop_irq, 9704 }; 9705 9706 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9707 .set = gfx_v10_0_set_priv_reg_fault_state, 9708 .process = gfx_v10_0_priv_reg_irq, 9709 }; 9710 9711 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 9712 .set = gfx_v10_0_set_bad_op_fault_state, 9713 .process = gfx_v10_0_bad_op_irq, 9714 }; 9715 9716 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9717 .set = gfx_v10_0_set_priv_inst_fault_state, 9718 .process = gfx_v10_0_priv_inst_irq, 9719 }; 9720 9721 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9722 .set = gfx_v10_0_kiq_set_interrupt_state, 9723 .process = gfx_v10_0_kiq_irq, 9724 }; 9725 9726 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9727 { 9728 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9729 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9730 9731 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9732 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9733 9734 adev->gfx.priv_reg_irq.num_types = 1; 9735 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9736 9737 adev->gfx.bad_op_irq.num_types = 1; 9738 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 9739 9740 adev->gfx.priv_inst_irq.num_types = 1; 9741 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9742 } 9743 9744 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9745 { 9746 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9747 case IP_VERSION(10, 1, 10): 9748 case IP_VERSION(10, 1, 1): 9749 case IP_VERSION(10, 1, 3): 9750 case IP_VERSION(10, 1, 4): 9751 case IP_VERSION(10, 3, 2): 9752 case IP_VERSION(10, 3, 1): 9753 case IP_VERSION(10, 3, 4): 9754 case IP_VERSION(10, 3, 5): 9755 case IP_VERSION(10, 3, 6): 9756 case IP_VERSION(10, 3, 3): 9757 case IP_VERSION(10, 3, 7): 9758 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9759 break; 9760 case IP_VERSION(10, 1, 2): 9761 case IP_VERSION(10, 3, 0): 9762 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9763 break; 9764 default: 9765 break; 9766 } 9767 } 9768 9769 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9770 { 9771 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9772 adev->gfx.config.max_sh_per_se * 9773 adev->gfx.config.max_shader_engines; 9774 9775 adev->gds.gds_size = 0x10000; 9776 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9777 adev->gds.gws_size = 64; 9778 adev->gds.oa_size = 16; 9779 } 9780 9781 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9782 { 9783 /* set gfx eng mqd */ 9784 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9785 sizeof(struct v10_gfx_mqd); 9786 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9787 gfx_v10_0_gfx_mqd_init; 9788 /* set compute eng mqd */ 9789 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9790 sizeof(struct v10_compute_mqd); 9791 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9792 gfx_v10_0_compute_mqd_init; 9793 } 9794 9795 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9796 u32 bitmap) 9797 { 9798 u32 data; 9799 9800 if (!bitmap) 9801 return; 9802 9803 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9804 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9805 9806 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9807 } 9808 9809 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9810 { 9811 u32 disabled_mask = 9812 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9813 u32 efuse_setting = 0; 9814 u32 vbios_setting = 0; 9815 9816 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9817 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9818 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9819 9820 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9821 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9822 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9823 9824 disabled_mask |= efuse_setting | vbios_setting; 9825 9826 return (~disabled_mask); 9827 } 9828 9829 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9830 { 9831 u32 wgp_idx, wgp_active_bitmap; 9832 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9833 9834 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9835 cu_active_bitmap = 0; 9836 9837 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9838 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9839 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9840 if (wgp_active_bitmap & (1 << wgp_idx)) 9841 cu_active_bitmap |= cu_bitmap_per_wgp; 9842 } 9843 9844 return cu_active_bitmap; 9845 } 9846 9847 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9848 struct amdgpu_cu_info *cu_info) 9849 { 9850 int i, j, k, counter, active_cu_number = 0; 9851 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9852 unsigned int disable_masks[4 * 2]; 9853 9854 if (!adev || !cu_info) 9855 return -EINVAL; 9856 9857 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9858 9859 mutex_lock(&adev->grbm_idx_mutex); 9860 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9861 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9862 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9863 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 9864 IP_VERSION(10, 3, 0)) || 9865 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9866 IP_VERSION(10, 3, 3)) || 9867 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9868 IP_VERSION(10, 3, 6)) || 9869 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9870 IP_VERSION(10, 3, 7))) && 9871 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9872 continue; 9873 mask = 1; 9874 ao_bitmap = 0; 9875 counter = 0; 9876 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9877 if (i < 4 && j < 2) 9878 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9879 adev, disable_masks[i * 2 + j]); 9880 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9881 cu_info->bitmap[0][i][j] = bitmap; 9882 9883 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9884 if (bitmap & mask) { 9885 if (counter < adev->gfx.config.max_cu_per_sh) 9886 ao_bitmap |= mask; 9887 counter++; 9888 } 9889 mask <<= 1; 9890 } 9891 active_cu_number += counter; 9892 if (i < 2 && j < 2) 9893 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9894 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9895 } 9896 } 9897 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9898 mutex_unlock(&adev->grbm_idx_mutex); 9899 9900 cu_info->number = active_cu_number; 9901 cu_info->ao_cu_mask = ao_cu_mask; 9902 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9903 9904 return 0; 9905 } 9906 9907 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9908 { 9909 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9910 9911 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9912 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9913 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9914 9915 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9916 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9917 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9918 9919 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9920 adev->gfx.config.max_shader_engines); 9921 disabled_sa = efuse_setting | vbios_setting; 9922 disabled_sa &= max_sa_mask; 9923 9924 return disabled_sa; 9925 } 9926 9927 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9928 { 9929 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9930 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9931 9932 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9933 9934 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9935 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9936 max_shader_engines = adev->gfx.config.max_shader_engines; 9937 9938 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9939 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9940 disabled_sa_per_se &= max_sa_per_se_mask; 9941 if (disabled_sa_per_se == max_sa_per_se_mask) { 9942 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9943 break; 9944 } 9945 } 9946 } 9947 9948 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9949 { 9950 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9951 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9952 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9953 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9954 9955 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9956 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9957 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9958 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9959 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9960 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9961 9962 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9963 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9964 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9965 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9966 9967 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9968 9969 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9970 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9971 } 9972 9973 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9974 .type = AMD_IP_BLOCK_TYPE_GFX, 9975 .major = 10, 9976 .minor = 0, 9977 .rev = 0, 9978 .funcs = &gfx_v10_0_ip_funcs, 9979 }; 9980