1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) 370 }; 371 372 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 413 }; 414 415 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 416 /* Pending on emulation bring up */ 417 }; 418 419 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1472 }; 1473 1474 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1513 }; 1514 1515 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1558 }; 1559 1560 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1561 /* Pending on emulation bring up */ 1562 }; 1563 1564 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2185 }; 2186 2187 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2188 /* Pending on emulation bring up */ 2189 }; 2190 2191 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3244 }; 3245 3246 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3290 }; 3291 3292 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3293 /* Pending on emulation bring up */ 3294 }; 3295 3296 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3338 3339 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3341 }; 3342 3343 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3368 3369 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3371 }; 3372 3373 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3394 }; 3395 3396 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3433 }; 3434 3435 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3468 }; 3469 3470 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3505 }; 3506 3507 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3530 }; 3531 3532 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3555 }; 3556 3557 #define DEFAULT_SH_MEM_CONFIG \ 3558 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3559 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3560 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3561 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3562 3563 /* TODO: pending on golden setting value of gb address config */ 3564 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3565 3566 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3567 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3568 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3569 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3570 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3571 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3572 struct amdgpu_cu_info *cu_info); 3573 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3574 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3575 u32 sh_num, u32 instance, int xcc_id); 3576 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3577 3578 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3579 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3580 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3581 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3582 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3583 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3584 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3585 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3586 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3587 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3588 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3589 uint16_t pasid, uint32_t flush_type, 3590 bool all_hub, uint8_t dst_sel); 3591 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3592 unsigned int vmid); 3593 3594 static int gfx_v10_0_set_powergating_state(void *handle, 3595 enum amd_powergating_state state); 3596 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3597 { 3598 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3599 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3600 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3601 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3602 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3603 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3604 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3605 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3606 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3607 } 3608 3609 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3610 struct amdgpu_ring *ring) 3611 { 3612 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3613 uint64_t wptr_addr = ring->wptr_gpu_addr; 3614 uint32_t eng_sel = 0; 3615 3616 switch (ring->funcs->type) { 3617 case AMDGPU_RING_TYPE_COMPUTE: 3618 eng_sel = 0; 3619 break; 3620 case AMDGPU_RING_TYPE_GFX: 3621 eng_sel = 4; 3622 break; 3623 case AMDGPU_RING_TYPE_MES: 3624 eng_sel = 5; 3625 break; 3626 default: 3627 WARN_ON(1); 3628 } 3629 3630 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3631 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3632 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3633 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3634 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3635 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3636 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3637 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3638 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3639 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3640 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3641 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3642 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3643 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3644 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3645 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3646 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3647 } 3648 3649 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3650 struct amdgpu_ring *ring, 3651 enum amdgpu_unmap_queues_action action, 3652 u64 gpu_addr, u64 seq) 3653 { 3654 struct amdgpu_device *adev = kiq_ring->adev; 3655 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3656 3657 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3658 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3659 return; 3660 } 3661 3662 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3663 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3664 PACKET3_UNMAP_QUEUES_ACTION(action) | 3665 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3666 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3667 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3668 amdgpu_ring_write(kiq_ring, 3669 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3670 3671 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3672 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3673 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3674 amdgpu_ring_write(kiq_ring, seq); 3675 } else { 3676 amdgpu_ring_write(kiq_ring, 0); 3677 amdgpu_ring_write(kiq_ring, 0); 3678 amdgpu_ring_write(kiq_ring, 0); 3679 } 3680 } 3681 3682 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3683 struct amdgpu_ring *ring, 3684 u64 addr, 3685 u64 seq) 3686 { 3687 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3688 3689 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3690 amdgpu_ring_write(kiq_ring, 3691 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3692 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3693 PACKET3_QUERY_STATUS_COMMAND(2)); 3694 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3695 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3696 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3697 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3698 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3699 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3700 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3701 } 3702 3703 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3704 uint16_t pasid, uint32_t flush_type, 3705 bool all_hub) 3706 { 3707 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3708 } 3709 3710 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3711 .kiq_set_resources = gfx10_kiq_set_resources, 3712 .kiq_map_queues = gfx10_kiq_map_queues, 3713 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3714 .kiq_query_status = gfx10_kiq_query_status, 3715 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3716 .set_resources_size = 8, 3717 .map_queues_size = 7, 3718 .unmap_queues_size = 6, 3719 .query_status_size = 7, 3720 .invalidate_tlbs_size = 2, 3721 }; 3722 3723 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3724 { 3725 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3726 } 3727 3728 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3729 { 3730 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3731 case IP_VERSION(10, 1, 10): 3732 soc15_program_register_sequence(adev, 3733 golden_settings_gc_rlc_spm_10_0_nv10, 3734 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3735 break; 3736 case IP_VERSION(10, 1, 1): 3737 soc15_program_register_sequence(adev, 3738 golden_settings_gc_rlc_spm_10_1_nv14, 3739 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3740 break; 3741 case IP_VERSION(10, 1, 2): 3742 soc15_program_register_sequence(adev, 3743 golden_settings_gc_rlc_spm_10_1_2_nv12, 3744 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3745 break; 3746 default: 3747 break; 3748 } 3749 } 3750 3751 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3752 { 3753 if (amdgpu_sriov_vf(adev)) 3754 return; 3755 3756 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3757 case IP_VERSION(10, 1, 10): 3758 soc15_program_register_sequence(adev, 3759 golden_settings_gc_10_1, 3760 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3761 soc15_program_register_sequence(adev, 3762 golden_settings_gc_10_0_nv10, 3763 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3764 break; 3765 case IP_VERSION(10, 1, 1): 3766 soc15_program_register_sequence(adev, 3767 golden_settings_gc_10_1_1, 3768 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3769 soc15_program_register_sequence(adev, 3770 golden_settings_gc_10_1_nv14, 3771 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3772 break; 3773 case IP_VERSION(10, 1, 2): 3774 soc15_program_register_sequence(adev, 3775 golden_settings_gc_10_1_2, 3776 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3777 soc15_program_register_sequence(adev, 3778 golden_settings_gc_10_1_2_nv12, 3779 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3780 break; 3781 case IP_VERSION(10, 3, 0): 3782 soc15_program_register_sequence(adev, 3783 golden_settings_gc_10_3, 3784 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3785 soc15_program_register_sequence(adev, 3786 golden_settings_gc_10_3_sienna_cichlid, 3787 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3788 break; 3789 case IP_VERSION(10, 3, 2): 3790 soc15_program_register_sequence(adev, 3791 golden_settings_gc_10_3_2, 3792 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3793 break; 3794 case IP_VERSION(10, 3, 1): 3795 soc15_program_register_sequence(adev, 3796 golden_settings_gc_10_3_vangogh, 3797 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3798 break; 3799 case IP_VERSION(10, 3, 3): 3800 soc15_program_register_sequence(adev, 3801 golden_settings_gc_10_3_3, 3802 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3803 break; 3804 case IP_VERSION(10, 3, 4): 3805 soc15_program_register_sequence(adev, 3806 golden_settings_gc_10_3_4, 3807 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3808 break; 3809 case IP_VERSION(10, 3, 5): 3810 soc15_program_register_sequence(adev, 3811 golden_settings_gc_10_3_5, 3812 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3813 break; 3814 case IP_VERSION(10, 1, 3): 3815 case IP_VERSION(10, 1, 4): 3816 soc15_program_register_sequence(adev, 3817 golden_settings_gc_10_0_cyan_skillfish, 3818 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3819 break; 3820 case IP_VERSION(10, 3, 6): 3821 soc15_program_register_sequence(adev, 3822 golden_settings_gc_10_3_6, 3823 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3824 break; 3825 case IP_VERSION(10, 3, 7): 3826 soc15_program_register_sequence(adev, 3827 golden_settings_gc_10_3_7, 3828 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3829 break; 3830 default: 3831 break; 3832 } 3833 gfx_v10_0_init_spm_golden_registers(adev); 3834 } 3835 3836 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3837 bool wc, uint32_t reg, uint32_t val) 3838 { 3839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3840 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3841 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3842 amdgpu_ring_write(ring, reg); 3843 amdgpu_ring_write(ring, 0); 3844 amdgpu_ring_write(ring, val); 3845 } 3846 3847 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3848 int mem_space, int opt, uint32_t addr0, 3849 uint32_t addr1, uint32_t ref, uint32_t mask, 3850 uint32_t inv) 3851 { 3852 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3853 amdgpu_ring_write(ring, 3854 /* memory (1) or register (0) */ 3855 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3856 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3857 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3858 WAIT_REG_MEM_ENGINE(eng_sel))); 3859 3860 if (mem_space) 3861 BUG_ON(addr0 & 0x3); /* Dword align */ 3862 amdgpu_ring_write(ring, addr0); 3863 amdgpu_ring_write(ring, addr1); 3864 amdgpu_ring_write(ring, ref); 3865 amdgpu_ring_write(ring, mask); 3866 amdgpu_ring_write(ring, inv); /* poll interval */ 3867 } 3868 3869 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3870 { 3871 struct amdgpu_device *adev = ring->adev; 3872 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3873 uint32_t tmp = 0; 3874 unsigned int i; 3875 int r; 3876 3877 WREG32(scratch, 0xCAFEDEAD); 3878 r = amdgpu_ring_alloc(ring, 3); 3879 if (r) { 3880 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3881 ring->idx, r); 3882 return r; 3883 } 3884 3885 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3886 amdgpu_ring_write(ring, scratch - 3887 PACKET3_SET_UCONFIG_REG_START); 3888 amdgpu_ring_write(ring, 0xDEADBEEF); 3889 amdgpu_ring_commit(ring); 3890 3891 for (i = 0; i < adev->usec_timeout; i++) { 3892 tmp = RREG32(scratch); 3893 if (tmp == 0xDEADBEEF) 3894 break; 3895 if (amdgpu_emu_mode == 1) 3896 msleep(1); 3897 else 3898 udelay(1); 3899 } 3900 3901 if (i >= adev->usec_timeout) 3902 r = -ETIMEDOUT; 3903 3904 return r; 3905 } 3906 3907 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3908 { 3909 struct amdgpu_device *adev = ring->adev; 3910 struct amdgpu_ib ib; 3911 struct dma_fence *f = NULL; 3912 unsigned int index; 3913 uint64_t gpu_addr; 3914 volatile uint32_t *cpu_ptr; 3915 long r; 3916 3917 memset(&ib, 0, sizeof(ib)); 3918 3919 if (ring->is_mes_queue) { 3920 uint32_t padding, offset; 3921 3922 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3923 padding = amdgpu_mes_ctx_get_offs(ring, 3924 AMDGPU_MES_CTX_PADDING_OFFS); 3925 3926 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3927 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3928 3929 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3930 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3931 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3932 } else { 3933 r = amdgpu_device_wb_get(adev, &index); 3934 if (r) 3935 return r; 3936 3937 gpu_addr = adev->wb.gpu_addr + (index * 4); 3938 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3939 cpu_ptr = &adev->wb.wb[index]; 3940 3941 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3942 if (r) { 3943 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3944 goto err1; 3945 } 3946 } 3947 3948 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3949 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3950 ib.ptr[2] = lower_32_bits(gpu_addr); 3951 ib.ptr[3] = upper_32_bits(gpu_addr); 3952 ib.ptr[4] = 0xDEADBEEF; 3953 ib.length_dw = 5; 3954 3955 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3956 if (r) 3957 goto err2; 3958 3959 r = dma_fence_wait_timeout(f, false, timeout); 3960 if (r == 0) { 3961 r = -ETIMEDOUT; 3962 goto err2; 3963 } else if (r < 0) { 3964 goto err2; 3965 } 3966 3967 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3968 r = 0; 3969 else 3970 r = -EINVAL; 3971 err2: 3972 if (!ring->is_mes_queue) 3973 amdgpu_ib_free(adev, &ib, NULL); 3974 dma_fence_put(f); 3975 err1: 3976 if (!ring->is_mes_queue) 3977 amdgpu_device_wb_free(adev, index); 3978 return r; 3979 } 3980 3981 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3982 { 3983 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3984 amdgpu_ucode_release(&adev->gfx.me_fw); 3985 amdgpu_ucode_release(&adev->gfx.ce_fw); 3986 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3987 amdgpu_ucode_release(&adev->gfx.mec_fw); 3988 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3989 3990 kfree(adev->gfx.rlc.register_list_format); 3991 } 3992 3993 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3994 { 3995 adev->gfx.cp_fw_write_wait = false; 3996 3997 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3998 case IP_VERSION(10, 1, 10): 3999 case IP_VERSION(10, 1, 2): 4000 case IP_VERSION(10, 1, 1): 4001 case IP_VERSION(10, 1, 3): 4002 case IP_VERSION(10, 1, 4): 4003 if ((adev->gfx.me_fw_version >= 0x00000046) && 4004 (adev->gfx.me_feature_version >= 27) && 4005 (adev->gfx.pfp_fw_version >= 0x00000068) && 4006 (adev->gfx.pfp_feature_version >= 27) && 4007 (adev->gfx.mec_fw_version >= 0x0000005b) && 4008 (adev->gfx.mec_feature_version >= 27)) 4009 adev->gfx.cp_fw_write_wait = true; 4010 break; 4011 case IP_VERSION(10, 3, 0): 4012 case IP_VERSION(10, 3, 2): 4013 case IP_VERSION(10, 3, 1): 4014 case IP_VERSION(10, 3, 4): 4015 case IP_VERSION(10, 3, 5): 4016 case IP_VERSION(10, 3, 6): 4017 case IP_VERSION(10, 3, 3): 4018 case IP_VERSION(10, 3, 7): 4019 adev->gfx.cp_fw_write_wait = true; 4020 break; 4021 default: 4022 break; 4023 } 4024 4025 if (!adev->gfx.cp_fw_write_wait) 4026 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4027 } 4028 4029 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4030 { 4031 bool ret = false; 4032 4033 switch (adev->pdev->revision) { 4034 case 0xc2: 4035 case 0xc3: 4036 ret = true; 4037 break; 4038 default: 4039 ret = false; 4040 break; 4041 } 4042 4043 return ret; 4044 } 4045 4046 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4047 { 4048 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4049 case IP_VERSION(10, 1, 10): 4050 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4051 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4052 break; 4053 default: 4054 break; 4055 } 4056 } 4057 4058 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4059 { 4060 char fw_name[53]; 4061 char ucode_prefix[30]; 4062 const char *wks = ""; 4063 int err; 4064 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4065 uint16_t version_major; 4066 uint16_t version_minor; 4067 4068 DRM_DEBUG("\n"); 4069 4070 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4071 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4072 wks = "_wks"; 4073 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4074 4075 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4076 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 4077 if (err) 4078 goto out; 4079 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4080 4081 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4082 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 4083 if (err) 4084 goto out; 4085 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4086 4087 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4088 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 4089 if (err) 4090 goto out; 4091 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4092 4093 if (!amdgpu_sriov_vf(adev)) { 4094 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4095 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4096 if (err) 4097 goto out; 4098 4099 /* don't validate this firmware. There are apparently firmwares 4100 * in the wild with incorrect size in the header 4101 */ 4102 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4103 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4104 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4105 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4106 if (err) 4107 goto out; 4108 } 4109 4110 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4111 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4112 if (err) 4113 goto out; 4114 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4115 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4116 4117 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4118 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4119 if (!err) { 4120 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4121 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4122 } else { 4123 err = 0; 4124 adev->gfx.mec2_fw = NULL; 4125 } 4126 4127 gfx_v10_0_check_fw_write_wait(adev); 4128 out: 4129 if (err) { 4130 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4131 amdgpu_ucode_release(&adev->gfx.me_fw); 4132 amdgpu_ucode_release(&adev->gfx.ce_fw); 4133 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4134 amdgpu_ucode_release(&adev->gfx.mec_fw); 4135 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4136 } 4137 4138 gfx_v10_0_check_gfxoff_flag(adev); 4139 4140 return err; 4141 } 4142 4143 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4144 { 4145 u32 count = 0; 4146 const struct cs_section_def *sect = NULL; 4147 const struct cs_extent_def *ext = NULL; 4148 4149 /* begin clear state */ 4150 count += 2; 4151 /* context control state */ 4152 count += 3; 4153 4154 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4155 for (ext = sect->section; ext->extent != NULL; ++ext) { 4156 if (sect->id == SECT_CONTEXT) 4157 count += 2 + ext->reg_count; 4158 else 4159 return 0; 4160 } 4161 } 4162 4163 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4164 count += 3; 4165 /* end clear state */ 4166 count += 2; 4167 /* clear state */ 4168 count += 2; 4169 4170 return count; 4171 } 4172 4173 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4174 volatile u32 *buffer) 4175 { 4176 u32 count = 0, i; 4177 const struct cs_section_def *sect = NULL; 4178 const struct cs_extent_def *ext = NULL; 4179 int ctx_reg_offset; 4180 4181 if (adev->gfx.rlc.cs_data == NULL) 4182 return; 4183 if (buffer == NULL) 4184 return; 4185 4186 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4187 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4188 4189 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4190 buffer[count++] = cpu_to_le32(0x80000000); 4191 buffer[count++] = cpu_to_le32(0x80000000); 4192 4193 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4194 for (ext = sect->section; ext->extent != NULL; ++ext) { 4195 if (sect->id == SECT_CONTEXT) { 4196 buffer[count++] = 4197 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4198 buffer[count++] = cpu_to_le32(ext->reg_index - 4199 PACKET3_SET_CONTEXT_REG_START); 4200 for (i = 0; i < ext->reg_count; i++) 4201 buffer[count++] = cpu_to_le32(ext->extent[i]); 4202 } else { 4203 return; 4204 } 4205 } 4206 } 4207 4208 ctx_reg_offset = 4209 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4210 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4211 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4212 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4213 4214 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4215 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4216 4217 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4218 buffer[count++] = cpu_to_le32(0); 4219 } 4220 4221 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4222 { 4223 /* clear state block */ 4224 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4225 &adev->gfx.rlc.clear_state_gpu_addr, 4226 (void **)&adev->gfx.rlc.cs_ptr); 4227 4228 /* jump table block */ 4229 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4230 &adev->gfx.rlc.cp_table_gpu_addr, 4231 (void **)&adev->gfx.rlc.cp_table_ptr); 4232 } 4233 4234 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4235 { 4236 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4237 4238 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4239 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4240 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4241 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4242 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4243 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4244 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4245 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4246 case IP_VERSION(10, 3, 0): 4247 reg_access_ctrl->spare_int = 4248 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4249 break; 4250 default: 4251 reg_access_ctrl->spare_int = 4252 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4253 break; 4254 } 4255 adev->gfx.rlc.rlcg_reg_access_supported = true; 4256 } 4257 4258 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4259 { 4260 const struct cs_section_def *cs_data; 4261 int r; 4262 4263 adev->gfx.rlc.cs_data = gfx10_cs_data; 4264 4265 cs_data = adev->gfx.rlc.cs_data; 4266 4267 if (cs_data) { 4268 /* init clear state block */ 4269 r = amdgpu_gfx_rlc_init_csb(adev); 4270 if (r) 4271 return r; 4272 } 4273 4274 return 0; 4275 } 4276 4277 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4278 { 4279 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4280 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4281 } 4282 4283 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4284 { 4285 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4286 4287 amdgpu_gfx_graphics_queue_acquire(adev); 4288 } 4289 4290 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4291 { 4292 int r; 4293 u32 *hpd; 4294 const __le32 *fw_data = NULL; 4295 unsigned int fw_size; 4296 u32 *fw = NULL; 4297 size_t mec_hpd_size; 4298 4299 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4300 4301 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4302 4303 /* take ownership of the relevant compute queues */ 4304 amdgpu_gfx_compute_queue_acquire(adev); 4305 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4306 4307 if (mec_hpd_size) { 4308 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4309 AMDGPU_GEM_DOMAIN_GTT, 4310 &adev->gfx.mec.hpd_eop_obj, 4311 &adev->gfx.mec.hpd_eop_gpu_addr, 4312 (void **)&hpd); 4313 if (r) { 4314 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4315 gfx_v10_0_mec_fini(adev); 4316 return r; 4317 } 4318 4319 memset(hpd, 0, mec_hpd_size); 4320 4321 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4322 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4323 } 4324 4325 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4326 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4327 4328 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4329 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4330 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4331 4332 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4333 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4334 &adev->gfx.mec.mec_fw_obj, 4335 &adev->gfx.mec.mec_fw_gpu_addr, 4336 (void **)&fw); 4337 if (r) { 4338 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4339 gfx_v10_0_mec_fini(adev); 4340 return r; 4341 } 4342 4343 memcpy(fw, fw_data, fw_size); 4344 4345 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4346 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4347 } 4348 4349 return 0; 4350 } 4351 4352 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4353 { 4354 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4355 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4356 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4357 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4358 } 4359 4360 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4361 uint32_t thread, uint32_t regno, 4362 uint32_t num, uint32_t *out) 4363 { 4364 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4365 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4366 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4367 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4368 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4369 while (num--) 4370 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4371 } 4372 4373 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4374 { 4375 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4376 * field when performing a select_se_sh so it should be 4377 * zero here 4378 */ 4379 WARN_ON(simd != 0); 4380 4381 /* type 2 wave data */ 4382 dst[(*no_fields)++] = 2; 4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4385 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4386 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4387 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4388 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4389 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4390 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4391 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4392 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4393 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4394 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4396 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4397 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4398 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4399 } 4400 4401 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4402 uint32_t wave, uint32_t start, 4403 uint32_t size, uint32_t *dst) 4404 { 4405 WARN_ON(simd != 0); 4406 4407 wave_read_regs( 4408 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4409 dst); 4410 } 4411 4412 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4413 uint32_t wave, uint32_t thread, 4414 uint32_t start, uint32_t size, 4415 uint32_t *dst) 4416 { 4417 wave_read_regs( 4418 adev, wave, thread, 4419 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4420 } 4421 4422 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4423 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4424 { 4425 nv_grbm_select(adev, me, pipe, q, vm); 4426 } 4427 4428 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4429 bool enable) 4430 { 4431 uint32_t data, def; 4432 4433 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4434 4435 if (enable) 4436 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4437 else 4438 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4439 4440 if (data != def) 4441 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4442 } 4443 4444 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4445 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4446 .select_se_sh = &gfx_v10_0_select_se_sh, 4447 .read_wave_data = &gfx_v10_0_read_wave_data, 4448 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4449 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4450 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4451 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4452 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4453 }; 4454 4455 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4456 { 4457 u32 gb_addr_config; 4458 4459 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4460 case IP_VERSION(10, 1, 10): 4461 case IP_VERSION(10, 1, 1): 4462 case IP_VERSION(10, 1, 2): 4463 adev->gfx.config.max_hw_contexts = 8; 4464 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4465 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4466 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4467 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4468 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4469 break; 4470 case IP_VERSION(10, 3, 0): 4471 case IP_VERSION(10, 3, 2): 4472 case IP_VERSION(10, 3, 1): 4473 case IP_VERSION(10, 3, 4): 4474 case IP_VERSION(10, 3, 5): 4475 case IP_VERSION(10, 3, 6): 4476 case IP_VERSION(10, 3, 3): 4477 case IP_VERSION(10, 3, 7): 4478 adev->gfx.config.max_hw_contexts = 8; 4479 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4480 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4481 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4482 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4483 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4484 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4485 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4486 break; 4487 case IP_VERSION(10, 1, 3): 4488 case IP_VERSION(10, 1, 4): 4489 adev->gfx.config.max_hw_contexts = 8; 4490 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4491 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4492 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4493 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4494 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4495 break; 4496 default: 4497 BUG(); 4498 break; 4499 } 4500 4501 adev->gfx.config.gb_addr_config = gb_addr_config; 4502 4503 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4504 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4505 GB_ADDR_CONFIG, NUM_PIPES); 4506 4507 adev->gfx.config.max_tile_pipes = 4508 adev->gfx.config.gb_addr_config_fields.num_pipes; 4509 4510 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4511 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4512 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4513 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4514 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4515 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4516 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4517 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4518 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4519 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4520 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4521 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4522 } 4523 4524 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4525 int me, int pipe, int queue) 4526 { 4527 struct amdgpu_ring *ring; 4528 unsigned int irq_type; 4529 unsigned int hw_prio; 4530 4531 ring = &adev->gfx.gfx_ring[ring_id]; 4532 4533 ring->me = me; 4534 ring->pipe = pipe; 4535 ring->queue = queue; 4536 4537 ring->ring_obj = NULL; 4538 ring->use_doorbell = true; 4539 4540 if (!ring_id) 4541 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4542 else 4543 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4544 ring->vm_hub = AMDGPU_GFXHUB(0); 4545 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4546 4547 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4548 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4549 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4550 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4551 hw_prio, NULL); 4552 } 4553 4554 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4555 int mec, int pipe, int queue) 4556 { 4557 unsigned int irq_type; 4558 struct amdgpu_ring *ring; 4559 unsigned int hw_prio; 4560 4561 ring = &adev->gfx.compute_ring[ring_id]; 4562 4563 /* mec0 is me1 */ 4564 ring->me = mec + 1; 4565 ring->pipe = pipe; 4566 ring->queue = queue; 4567 4568 ring->ring_obj = NULL; 4569 ring->use_doorbell = true; 4570 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4571 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4572 + (ring_id * GFX10_MEC_HPD_SIZE); 4573 ring->vm_hub = AMDGPU_GFXHUB(0); 4574 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4575 4576 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4577 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4578 + ring->pipe; 4579 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4580 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4581 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4582 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4583 hw_prio, NULL); 4584 } 4585 4586 static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) 4587 { 4588 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4589 uint32_t *ptr; 4590 4591 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4592 if (ptr == NULL) { 4593 DRM_ERROR("Failed to allocate memory for IP Dump\n"); 4594 adev->gfx.ip_dump = NULL; 4595 } else { 4596 adev->gfx.ip_dump = ptr; 4597 } 4598 } 4599 4600 static int gfx_v10_0_sw_init(void *handle) 4601 { 4602 int i, j, k, r, ring_id = 0; 4603 int xcc_id = 0; 4604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4605 4606 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4607 case IP_VERSION(10, 1, 10): 4608 case IP_VERSION(10, 1, 1): 4609 case IP_VERSION(10, 1, 2): 4610 case IP_VERSION(10, 1, 3): 4611 case IP_VERSION(10, 1, 4): 4612 adev->gfx.me.num_me = 1; 4613 adev->gfx.me.num_pipe_per_me = 1; 4614 adev->gfx.me.num_queue_per_pipe = 1; 4615 adev->gfx.mec.num_mec = 2; 4616 adev->gfx.mec.num_pipe_per_mec = 4; 4617 adev->gfx.mec.num_queue_per_pipe = 8; 4618 break; 4619 case IP_VERSION(10, 3, 0): 4620 case IP_VERSION(10, 3, 2): 4621 case IP_VERSION(10, 3, 1): 4622 case IP_VERSION(10, 3, 4): 4623 case IP_VERSION(10, 3, 5): 4624 case IP_VERSION(10, 3, 6): 4625 case IP_VERSION(10, 3, 3): 4626 case IP_VERSION(10, 3, 7): 4627 adev->gfx.me.num_me = 1; 4628 adev->gfx.me.num_pipe_per_me = 2; 4629 adev->gfx.me.num_queue_per_pipe = 1; 4630 adev->gfx.mec.num_mec = 2; 4631 adev->gfx.mec.num_pipe_per_mec = 4; 4632 adev->gfx.mec.num_queue_per_pipe = 4; 4633 break; 4634 default: 4635 adev->gfx.me.num_me = 1; 4636 adev->gfx.me.num_pipe_per_me = 1; 4637 adev->gfx.me.num_queue_per_pipe = 1; 4638 adev->gfx.mec.num_mec = 1; 4639 adev->gfx.mec.num_pipe_per_mec = 4; 4640 adev->gfx.mec.num_queue_per_pipe = 8; 4641 break; 4642 } 4643 4644 /* KIQ event */ 4645 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4646 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4647 &adev->gfx.kiq[0].irq); 4648 if (r) 4649 return r; 4650 4651 /* EOP Event */ 4652 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4653 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4654 &adev->gfx.eop_irq); 4655 if (r) 4656 return r; 4657 4658 /* Privileged reg */ 4659 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4660 &adev->gfx.priv_reg_irq); 4661 if (r) 4662 return r; 4663 4664 /* Privileged inst */ 4665 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4666 &adev->gfx.priv_inst_irq); 4667 if (r) 4668 return r; 4669 4670 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4671 4672 gfx_v10_0_me_init(adev); 4673 4674 if (adev->gfx.rlc.funcs) { 4675 if (adev->gfx.rlc.funcs->init) { 4676 r = adev->gfx.rlc.funcs->init(adev); 4677 if (r) { 4678 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4679 return r; 4680 } 4681 } 4682 } 4683 4684 r = gfx_v10_0_mec_init(adev); 4685 if (r) { 4686 DRM_ERROR("Failed to init MEC BOs!\n"); 4687 return r; 4688 } 4689 4690 /* set up the gfx ring */ 4691 for (i = 0; i < adev->gfx.me.num_me; i++) { 4692 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4693 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4694 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4695 continue; 4696 4697 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4698 i, k, j); 4699 if (r) 4700 return r; 4701 ring_id++; 4702 } 4703 } 4704 } 4705 4706 ring_id = 0; 4707 /* set up the compute queues - allocate horizontally across pipes */ 4708 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4709 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4710 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4711 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4712 k, j)) 4713 continue; 4714 4715 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4716 i, k, j); 4717 if (r) 4718 return r; 4719 4720 ring_id++; 4721 } 4722 } 4723 } 4724 4725 if (!adev->enable_mes_kiq) { 4726 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4727 if (r) { 4728 DRM_ERROR("Failed to init KIQ BOs!\n"); 4729 return r; 4730 } 4731 4732 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4733 if (r) 4734 return r; 4735 } 4736 4737 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4738 if (r) 4739 return r; 4740 4741 /* allocate visible FB for rlc auto-loading fw */ 4742 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4743 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4744 if (r) 4745 return r; 4746 } 4747 4748 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4749 4750 gfx_v10_0_gpu_early_init(adev); 4751 4752 gfx_v10_0_alloc_dump_mem(adev); 4753 4754 return 0; 4755 } 4756 4757 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4758 { 4759 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4760 &adev->gfx.pfp.pfp_fw_gpu_addr, 4761 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4762 } 4763 4764 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4765 { 4766 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4767 &adev->gfx.ce.ce_fw_gpu_addr, 4768 (void **)&adev->gfx.ce.ce_fw_ptr); 4769 } 4770 4771 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4772 { 4773 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4774 &adev->gfx.me.me_fw_gpu_addr, 4775 (void **)&adev->gfx.me.me_fw_ptr); 4776 } 4777 4778 static int gfx_v10_0_sw_fini(void *handle) 4779 { 4780 int i; 4781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4782 4783 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4784 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4785 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4786 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4787 4788 amdgpu_gfx_mqd_sw_fini(adev, 0); 4789 4790 if (!adev->enable_mes_kiq) { 4791 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4792 amdgpu_gfx_kiq_fini(adev, 0); 4793 } 4794 4795 gfx_v10_0_pfp_fini(adev); 4796 gfx_v10_0_ce_fini(adev); 4797 gfx_v10_0_me_fini(adev); 4798 gfx_v10_0_rlc_fini(adev); 4799 gfx_v10_0_mec_fini(adev); 4800 4801 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4802 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4803 4804 gfx_v10_0_free_microcode(adev); 4805 4806 kfree(adev->gfx.ip_dump); 4807 4808 return 0; 4809 } 4810 4811 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4812 u32 sh_num, u32 instance, int xcc_id) 4813 { 4814 u32 data; 4815 4816 if (instance == 0xffffffff) 4817 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4818 INSTANCE_BROADCAST_WRITES, 1); 4819 else 4820 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4821 instance); 4822 4823 if (se_num == 0xffffffff) 4824 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4825 1); 4826 else 4827 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4828 4829 if (sh_num == 0xffffffff) 4830 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4831 1); 4832 else 4833 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4834 4835 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4836 } 4837 4838 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4839 { 4840 u32 data, mask; 4841 4842 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4843 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4844 4845 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4846 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4847 4848 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4849 adev->gfx.config.max_sh_per_se); 4850 4851 return (~data) & mask; 4852 } 4853 4854 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4855 { 4856 int i, j; 4857 u32 data; 4858 u32 active_rbs = 0; 4859 u32 bitmap; 4860 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4861 adev->gfx.config.max_sh_per_se; 4862 4863 mutex_lock(&adev->grbm_idx_mutex); 4864 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4865 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4866 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4867 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4868 IP_VERSION(10, 3, 0)) || 4869 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4870 IP_VERSION(10, 3, 3)) || 4871 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4872 IP_VERSION(10, 3, 6))) && 4873 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4874 continue; 4875 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4876 data = gfx_v10_0_get_rb_active_bitmap(adev); 4877 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4878 rb_bitmap_width_per_sh); 4879 } 4880 } 4881 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4882 mutex_unlock(&adev->grbm_idx_mutex); 4883 4884 adev->gfx.config.backend_enable_mask = active_rbs; 4885 adev->gfx.config.num_rbs = hweight32(active_rbs); 4886 } 4887 4888 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4889 { 4890 uint32_t num_sc; 4891 uint32_t enabled_rb_per_sh; 4892 uint32_t active_rb_bitmap; 4893 uint32_t num_rb_per_sc; 4894 uint32_t num_packer_per_sc; 4895 uint32_t pa_sc_tile_steering_override; 4896 4897 /* for ASICs that integrates GFX v10.3 4898 * pa_sc_tile_steering_override should be set to 0 4899 */ 4900 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 4901 return 0; 4902 4903 /* init num_sc */ 4904 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4905 adev->gfx.config.num_sc_per_sh; 4906 /* init num_rb_per_sc */ 4907 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4908 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4909 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4910 /* init num_packer_per_sc */ 4911 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4912 4913 pa_sc_tile_steering_override = 0; 4914 pa_sc_tile_steering_override |= 4915 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4916 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4917 pa_sc_tile_steering_override |= 4918 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4919 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4920 pa_sc_tile_steering_override |= 4921 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4922 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4923 4924 return pa_sc_tile_steering_override; 4925 } 4926 4927 #define DEFAULT_SH_MEM_BASES (0x6000) 4928 4929 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4930 uint32_t first_vmid, 4931 uint32_t last_vmid) 4932 { 4933 uint32_t data; 4934 uint32_t trap_config_vmid_mask = 0; 4935 int i; 4936 4937 /* Calculate trap config vmid mask */ 4938 for (i = first_vmid; i < last_vmid; i++) 4939 trap_config_vmid_mask |= (1 << i); 4940 4941 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4942 VMID_SEL, trap_config_vmid_mask); 4943 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4944 TRAP_EN, 1); 4945 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4946 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4947 4948 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4949 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4950 } 4951 4952 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4953 { 4954 int i; 4955 uint32_t sh_mem_bases; 4956 4957 /* 4958 * Configure apertures: 4959 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4960 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4961 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4962 */ 4963 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4964 4965 mutex_lock(&adev->srbm_mutex); 4966 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4967 nv_grbm_select(adev, 0, 0, 0, i); 4968 /* CP and shaders */ 4969 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4970 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4971 } 4972 nv_grbm_select(adev, 0, 0, 0, 0); 4973 mutex_unlock(&adev->srbm_mutex); 4974 4975 /* 4976 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4977 * access. These should be enabled by FW for target VMIDs. 4978 */ 4979 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4980 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4981 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4982 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4983 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4984 } 4985 4986 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4987 AMDGPU_NUM_VMID); 4988 } 4989 4990 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4991 { 4992 int vmid; 4993 4994 /* 4995 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4996 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4997 * the driver can enable them for graphics. VMID0 should maintain 4998 * access so that HWS firmware can save/restore entries. 4999 */ 5000 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5001 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5002 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5003 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5004 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5005 } 5006 } 5007 5008 5009 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5010 { 5011 int i, j, k; 5012 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5013 u32 tmp, wgp_active_bitmap = 0; 5014 u32 gcrd_targets_disable_tcp = 0; 5015 u32 utcl_invreq_disable = 0; 5016 /* 5017 * GCRD_TARGETS_DISABLE field contains 5018 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5019 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5020 */ 5021 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5022 2 * max_wgp_per_sh + /* TCP */ 5023 max_wgp_per_sh + /* SQC */ 5024 4); /* GL1C */ 5025 /* 5026 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5027 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5028 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5029 */ 5030 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5031 2 * max_wgp_per_sh + /* TCP */ 5032 2 * max_wgp_per_sh + /* SQC */ 5033 4 + /* RMI */ 5034 1); /* SQG */ 5035 5036 mutex_lock(&adev->grbm_idx_mutex); 5037 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5038 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5039 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5040 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5041 /* 5042 * Set corresponding TCP bits for the inactive WGPs in 5043 * GCRD_SA_TARGETS_DISABLE 5044 */ 5045 gcrd_targets_disable_tcp = 0; 5046 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5047 utcl_invreq_disable = 0; 5048 5049 for (k = 0; k < max_wgp_per_sh; k++) { 5050 if (!(wgp_active_bitmap & (1 << k))) { 5051 gcrd_targets_disable_tcp |= 3 << (2 * k); 5052 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5053 utcl_invreq_disable |= (3 << (2 * k)) | 5054 (3 << (2 * (max_wgp_per_sh + k))); 5055 } 5056 } 5057 5058 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5059 /* only override TCP & SQC bits */ 5060 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5061 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5062 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5063 5064 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5065 /* only override TCP & SQC bits */ 5066 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5067 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5068 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5069 } 5070 } 5071 5072 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5073 mutex_unlock(&adev->grbm_idx_mutex); 5074 } 5075 5076 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5077 { 5078 /* TCCs are global (not instanced). */ 5079 uint32_t tcc_disable; 5080 5081 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5082 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5083 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5084 } else { 5085 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5086 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5087 } 5088 5089 adev->gfx.config.tcc_disabled_mask = 5090 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5091 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5092 } 5093 5094 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5095 { 5096 u32 tmp; 5097 int i; 5098 5099 if (!amdgpu_sriov_vf(adev)) 5100 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5101 5102 gfx_v10_0_setup_rb(adev); 5103 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5104 gfx_v10_0_get_tcc_info(adev); 5105 adev->gfx.config.pa_sc_tile_steering_override = 5106 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5107 5108 /* XXX SH_MEM regs */ 5109 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5110 mutex_lock(&adev->srbm_mutex); 5111 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5112 nv_grbm_select(adev, 0, 0, 0, i); 5113 /* CP and shaders */ 5114 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5115 if (i != 0) { 5116 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5117 (adev->gmc.private_aperture_start >> 48)); 5118 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5119 (adev->gmc.shared_aperture_start >> 48)); 5120 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5121 } 5122 } 5123 nv_grbm_select(adev, 0, 0, 0, 0); 5124 5125 mutex_unlock(&adev->srbm_mutex); 5126 5127 gfx_v10_0_init_compute_vmid(adev); 5128 gfx_v10_0_init_gds_vmid(adev); 5129 5130 } 5131 5132 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5133 bool enable) 5134 { 5135 u32 tmp; 5136 5137 if (amdgpu_sriov_vf(adev)) 5138 return; 5139 5140 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5141 5142 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5143 enable ? 1 : 0); 5144 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5145 enable ? 1 : 0); 5146 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5147 enable ? 1 : 0); 5148 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5149 enable ? 1 : 0); 5150 5151 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5152 } 5153 5154 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5155 { 5156 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5157 5158 /* csib */ 5159 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5160 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5161 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5162 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5163 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5164 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5165 } else { 5166 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5167 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5168 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5169 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5170 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5171 } 5172 return 0; 5173 } 5174 5175 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5176 { 5177 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5178 5179 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5180 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5181 } 5182 5183 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5184 { 5185 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5186 udelay(50); 5187 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5188 udelay(50); 5189 } 5190 5191 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5192 bool enable) 5193 { 5194 uint32_t rlc_pg_cntl; 5195 5196 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5197 5198 if (!enable) { 5199 /* RLC_PG_CNTL[23] = 0 (default) 5200 * RLC will wait for handshake acks with SMU 5201 * GFXOFF will be enabled 5202 * RLC_PG_CNTL[23] = 1 5203 * RLC will not issue any message to SMU 5204 * hence no handshake between SMU & RLC 5205 * GFXOFF will be disabled 5206 */ 5207 rlc_pg_cntl |= 0x800000; 5208 } else 5209 rlc_pg_cntl &= ~0x800000; 5210 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5211 } 5212 5213 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5214 { 5215 /* 5216 * TODO: enable rlc & smu handshake until smu 5217 * and gfxoff feature works as expected 5218 */ 5219 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5220 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5221 5222 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5223 udelay(50); 5224 } 5225 5226 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5227 { 5228 uint32_t tmp; 5229 5230 /* enable Save Restore Machine */ 5231 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5232 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5233 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5234 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5235 } 5236 5237 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5238 { 5239 const struct rlc_firmware_header_v2_0 *hdr; 5240 const __le32 *fw_data; 5241 unsigned int i, fw_size; 5242 5243 if (!adev->gfx.rlc_fw) 5244 return -EINVAL; 5245 5246 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5247 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5248 5249 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5250 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5251 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5252 5253 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5254 RLCG_UCODE_LOADING_START_ADDRESS); 5255 5256 for (i = 0; i < fw_size; i++) 5257 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5258 le32_to_cpup(fw_data++)); 5259 5260 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5261 5262 return 0; 5263 } 5264 5265 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5266 { 5267 int r; 5268 5269 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5270 adev->psp.autoload_supported) { 5271 5272 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5273 if (r) 5274 return r; 5275 5276 gfx_v10_0_init_csb(adev); 5277 5278 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5279 5280 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5281 gfx_v10_0_rlc_enable_srm(adev); 5282 } else { 5283 if (amdgpu_sriov_vf(adev)) { 5284 gfx_v10_0_init_csb(adev); 5285 return 0; 5286 } 5287 5288 adev->gfx.rlc.funcs->stop(adev); 5289 5290 /* disable CG */ 5291 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5292 5293 /* disable PG */ 5294 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5295 5296 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5297 /* legacy rlc firmware loading */ 5298 r = gfx_v10_0_rlc_load_microcode(adev); 5299 if (r) 5300 return r; 5301 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5302 /* rlc backdoor autoload firmware */ 5303 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5304 if (r) 5305 return r; 5306 } 5307 5308 gfx_v10_0_init_csb(adev); 5309 5310 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5311 5312 adev->gfx.rlc.funcs->start(adev); 5313 5314 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5315 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5316 if (r) 5317 return r; 5318 } 5319 } 5320 5321 return 0; 5322 } 5323 5324 static struct { 5325 FIRMWARE_ID id; 5326 unsigned int offset; 5327 unsigned int size; 5328 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5329 5330 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5331 { 5332 int ret; 5333 RLC_TABLE_OF_CONTENT *rlc_toc; 5334 5335 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5336 AMDGPU_GEM_DOMAIN_GTT, 5337 &adev->gfx.rlc.rlc_toc_bo, 5338 &adev->gfx.rlc.rlc_toc_gpu_addr, 5339 (void **)&adev->gfx.rlc.rlc_toc_buf); 5340 if (ret) { 5341 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5342 return ret; 5343 } 5344 5345 /* Copy toc from psp sos fw to rlc toc buffer */ 5346 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5347 5348 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5349 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5350 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5351 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5352 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5353 /* Offset needs 4KB alignment */ 5354 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5355 } 5356 5357 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5358 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5359 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5360 5361 rlc_toc++; 5362 } 5363 5364 return 0; 5365 } 5366 5367 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5368 { 5369 uint32_t total_size = 0; 5370 FIRMWARE_ID id; 5371 int ret; 5372 5373 ret = gfx_v10_0_parse_rlc_toc(adev); 5374 if (ret) { 5375 dev_err(adev->dev, "failed to parse rlc toc\n"); 5376 return 0; 5377 } 5378 5379 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5380 total_size += rlc_autoload_info[id].size; 5381 5382 /* In case the offset in rlc toc ucode is aligned */ 5383 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5384 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5385 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5386 5387 return total_size; 5388 } 5389 5390 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5391 { 5392 int r; 5393 uint32_t total_size; 5394 5395 total_size = gfx_v10_0_calc_toc_total_size(adev); 5396 5397 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5398 AMDGPU_GEM_DOMAIN_GTT, 5399 &adev->gfx.rlc.rlc_autoload_bo, 5400 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5401 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5402 if (r) { 5403 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5404 return r; 5405 } 5406 5407 return 0; 5408 } 5409 5410 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5411 { 5412 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5413 &adev->gfx.rlc.rlc_toc_gpu_addr, 5414 (void **)&adev->gfx.rlc.rlc_toc_buf); 5415 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5416 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5417 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5418 } 5419 5420 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5421 FIRMWARE_ID id, 5422 const void *fw_data, 5423 uint32_t fw_size) 5424 { 5425 uint32_t toc_offset; 5426 uint32_t toc_fw_size; 5427 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5428 5429 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5430 return; 5431 5432 toc_offset = rlc_autoload_info[id].offset; 5433 toc_fw_size = rlc_autoload_info[id].size; 5434 5435 if (fw_size == 0) 5436 fw_size = toc_fw_size; 5437 5438 if (fw_size > toc_fw_size) 5439 fw_size = toc_fw_size; 5440 5441 memcpy(ptr + toc_offset, fw_data, fw_size); 5442 5443 if (fw_size < toc_fw_size) 5444 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5445 } 5446 5447 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5448 { 5449 void *data; 5450 uint32_t size; 5451 5452 data = adev->gfx.rlc.rlc_toc_buf; 5453 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5454 5455 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5456 FIRMWARE_ID_RLC_TOC, 5457 data, size); 5458 } 5459 5460 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5461 { 5462 const __le32 *fw_data; 5463 uint32_t fw_size; 5464 const struct gfx_firmware_header_v1_0 *cp_hdr; 5465 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5466 5467 /* pfp ucode */ 5468 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5469 adev->gfx.pfp_fw->data; 5470 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5471 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5472 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5473 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5474 FIRMWARE_ID_CP_PFP, 5475 fw_data, fw_size); 5476 5477 /* ce ucode */ 5478 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5479 adev->gfx.ce_fw->data; 5480 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5481 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5482 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5483 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5484 FIRMWARE_ID_CP_CE, 5485 fw_data, fw_size); 5486 5487 /* me ucode */ 5488 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5489 adev->gfx.me_fw->data; 5490 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5491 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5492 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5493 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5494 FIRMWARE_ID_CP_ME, 5495 fw_data, fw_size); 5496 5497 /* rlc ucode */ 5498 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5499 adev->gfx.rlc_fw->data; 5500 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5501 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5502 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5503 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5504 FIRMWARE_ID_RLC_G_UCODE, 5505 fw_data, fw_size); 5506 5507 /* mec1 ucode */ 5508 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5509 adev->gfx.mec_fw->data; 5510 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5511 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5512 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5513 cp_hdr->jt_size * 4; 5514 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5515 FIRMWARE_ID_CP_MEC, 5516 fw_data, fw_size); 5517 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5518 } 5519 5520 /* Temporarily put sdma part here */ 5521 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5522 { 5523 const __le32 *fw_data; 5524 uint32_t fw_size; 5525 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5526 int i; 5527 5528 for (i = 0; i < adev->sdma.num_instances; i++) { 5529 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5530 adev->sdma.instance[i].fw->data; 5531 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5532 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5533 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5534 5535 if (i == 0) { 5536 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5537 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5538 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5539 FIRMWARE_ID_SDMA0_JT, 5540 (uint32_t *)fw_data + 5541 sdma_hdr->jt_offset, 5542 sdma_hdr->jt_size * 4); 5543 } else if (i == 1) { 5544 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5545 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5546 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5547 FIRMWARE_ID_SDMA1_JT, 5548 (uint32_t *)fw_data + 5549 sdma_hdr->jt_offset, 5550 sdma_hdr->jt_size * 4); 5551 } 5552 } 5553 } 5554 5555 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5556 { 5557 uint32_t rlc_g_offset, rlc_g_size, tmp; 5558 uint64_t gpu_addr; 5559 5560 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5561 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5562 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5563 5564 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5565 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5566 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5567 5568 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5569 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5570 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5571 5572 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5573 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5574 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5575 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5576 return -EINVAL; 5577 } 5578 5579 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5580 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5581 DRM_ERROR("RLC ROM should halt itself\n"); 5582 return -EINVAL; 5583 } 5584 5585 return 0; 5586 } 5587 5588 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5589 { 5590 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5591 uint32_t tmp; 5592 int i; 5593 uint64_t addr; 5594 5595 /* Trigger an invalidation of the L1 instruction caches */ 5596 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5597 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5598 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5599 5600 /* Wait for invalidation complete */ 5601 for (i = 0; i < usec_timeout; i++) { 5602 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5603 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5604 INVALIDATE_CACHE_COMPLETE)) 5605 break; 5606 udelay(1); 5607 } 5608 5609 if (i >= usec_timeout) { 5610 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5611 return -EINVAL; 5612 } 5613 5614 /* Program me ucode address into intruction cache address register */ 5615 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5616 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5617 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5618 lower_32_bits(addr) & 0xFFFFF000); 5619 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5620 upper_32_bits(addr)); 5621 5622 return 0; 5623 } 5624 5625 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5626 { 5627 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5628 uint32_t tmp; 5629 int i; 5630 uint64_t addr; 5631 5632 /* Trigger an invalidation of the L1 instruction caches */ 5633 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5634 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5635 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5636 5637 /* Wait for invalidation complete */ 5638 for (i = 0; i < usec_timeout; i++) { 5639 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5640 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5641 INVALIDATE_CACHE_COMPLETE)) 5642 break; 5643 udelay(1); 5644 } 5645 5646 if (i >= usec_timeout) { 5647 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5648 return -EINVAL; 5649 } 5650 5651 /* Program ce ucode address into intruction cache address register */ 5652 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5653 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5654 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5655 lower_32_bits(addr) & 0xFFFFF000); 5656 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5657 upper_32_bits(addr)); 5658 5659 return 0; 5660 } 5661 5662 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5663 { 5664 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5665 uint32_t tmp; 5666 int i; 5667 uint64_t addr; 5668 5669 /* Trigger an invalidation of the L1 instruction caches */ 5670 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5671 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5672 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5673 5674 /* Wait for invalidation complete */ 5675 for (i = 0; i < usec_timeout; i++) { 5676 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5677 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5678 INVALIDATE_CACHE_COMPLETE)) 5679 break; 5680 udelay(1); 5681 } 5682 5683 if (i >= usec_timeout) { 5684 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5685 return -EINVAL; 5686 } 5687 5688 /* Program pfp ucode address into intruction cache address register */ 5689 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5690 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5691 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5692 lower_32_bits(addr) & 0xFFFFF000); 5693 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5694 upper_32_bits(addr)); 5695 5696 return 0; 5697 } 5698 5699 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5700 { 5701 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5702 uint32_t tmp; 5703 int i; 5704 uint64_t addr; 5705 5706 /* Trigger an invalidation of the L1 instruction caches */ 5707 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5708 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5709 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5710 5711 /* Wait for invalidation complete */ 5712 for (i = 0; i < usec_timeout; i++) { 5713 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5714 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5715 INVALIDATE_CACHE_COMPLETE)) 5716 break; 5717 udelay(1); 5718 } 5719 5720 if (i >= usec_timeout) { 5721 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5722 return -EINVAL; 5723 } 5724 5725 /* Program mec1 ucode address into intruction cache address register */ 5726 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5727 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5728 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5729 lower_32_bits(addr) & 0xFFFFF000); 5730 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5731 upper_32_bits(addr)); 5732 5733 return 0; 5734 } 5735 5736 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5737 { 5738 uint32_t cp_status; 5739 uint32_t bootload_status; 5740 int i, r; 5741 5742 for (i = 0; i < adev->usec_timeout; i++) { 5743 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5744 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5745 if ((cp_status == 0) && 5746 (REG_GET_FIELD(bootload_status, 5747 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5748 break; 5749 } 5750 udelay(1); 5751 } 5752 5753 if (i >= adev->usec_timeout) { 5754 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5755 return -ETIMEDOUT; 5756 } 5757 5758 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5759 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5760 if (r) 5761 return r; 5762 5763 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5764 if (r) 5765 return r; 5766 5767 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5768 if (r) 5769 return r; 5770 5771 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5772 if (r) 5773 return r; 5774 } 5775 5776 return 0; 5777 } 5778 5779 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5780 { 5781 int i; 5782 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5783 5784 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5785 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5786 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5787 5788 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5789 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5790 else 5791 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5792 5793 if (adev->job_hang && !enable) 5794 return 0; 5795 5796 for (i = 0; i < adev->usec_timeout; i++) { 5797 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5798 break; 5799 udelay(1); 5800 } 5801 5802 if (i >= adev->usec_timeout) 5803 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5804 5805 return 0; 5806 } 5807 5808 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5809 { 5810 int r; 5811 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5812 const __le32 *fw_data; 5813 unsigned int i, fw_size; 5814 uint32_t tmp; 5815 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5816 5817 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5818 adev->gfx.pfp_fw->data; 5819 5820 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5821 5822 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5823 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5824 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5825 5826 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5827 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5828 &adev->gfx.pfp.pfp_fw_obj, 5829 &adev->gfx.pfp.pfp_fw_gpu_addr, 5830 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5831 if (r) { 5832 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5833 gfx_v10_0_pfp_fini(adev); 5834 return r; 5835 } 5836 5837 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5838 5839 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5840 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5841 5842 /* Trigger an invalidation of the L1 instruction caches */ 5843 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5844 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5845 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5846 5847 /* Wait for invalidation complete */ 5848 for (i = 0; i < usec_timeout; i++) { 5849 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5850 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5851 INVALIDATE_CACHE_COMPLETE)) 5852 break; 5853 udelay(1); 5854 } 5855 5856 if (i >= usec_timeout) { 5857 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5858 return -EINVAL; 5859 } 5860 5861 if (amdgpu_emu_mode == 1) 5862 adev->hdp.funcs->flush_hdp(adev, NULL); 5863 5864 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5865 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5866 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5867 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5868 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5869 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5870 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5871 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5872 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5873 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5874 5875 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5876 5877 for (i = 0; i < pfp_hdr->jt_size; i++) 5878 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5879 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5880 5881 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5882 5883 return 0; 5884 } 5885 5886 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5887 { 5888 int r; 5889 const struct gfx_firmware_header_v1_0 *ce_hdr; 5890 const __le32 *fw_data; 5891 unsigned int i, fw_size; 5892 uint32_t tmp; 5893 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5894 5895 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5896 adev->gfx.ce_fw->data; 5897 5898 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5899 5900 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5901 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5902 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5903 5904 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5905 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5906 &adev->gfx.ce.ce_fw_obj, 5907 &adev->gfx.ce.ce_fw_gpu_addr, 5908 (void **)&adev->gfx.ce.ce_fw_ptr); 5909 if (r) { 5910 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5911 gfx_v10_0_ce_fini(adev); 5912 return r; 5913 } 5914 5915 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5916 5917 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5918 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5919 5920 /* Trigger an invalidation of the L1 instruction caches */ 5921 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5922 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5923 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5924 5925 /* Wait for invalidation complete */ 5926 for (i = 0; i < usec_timeout; i++) { 5927 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5928 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5929 INVALIDATE_CACHE_COMPLETE)) 5930 break; 5931 udelay(1); 5932 } 5933 5934 if (i >= usec_timeout) { 5935 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5936 return -EINVAL; 5937 } 5938 5939 if (amdgpu_emu_mode == 1) 5940 adev->hdp.funcs->flush_hdp(adev, NULL); 5941 5942 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5943 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5944 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5945 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5946 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5947 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5948 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5949 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5950 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5951 5952 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5953 5954 for (i = 0; i < ce_hdr->jt_size; i++) 5955 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5956 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5957 5958 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5959 5960 return 0; 5961 } 5962 5963 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5964 { 5965 int r; 5966 const struct gfx_firmware_header_v1_0 *me_hdr; 5967 const __le32 *fw_data; 5968 unsigned int i, fw_size; 5969 uint32_t tmp; 5970 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5971 5972 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5973 adev->gfx.me_fw->data; 5974 5975 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5976 5977 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5978 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5979 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5980 5981 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5982 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5983 &adev->gfx.me.me_fw_obj, 5984 &adev->gfx.me.me_fw_gpu_addr, 5985 (void **)&adev->gfx.me.me_fw_ptr); 5986 if (r) { 5987 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5988 gfx_v10_0_me_fini(adev); 5989 return r; 5990 } 5991 5992 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5993 5994 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5995 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5996 5997 /* Trigger an invalidation of the L1 instruction caches */ 5998 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5999 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6000 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6001 6002 /* Wait for invalidation complete */ 6003 for (i = 0; i < usec_timeout; i++) { 6004 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6005 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6006 INVALIDATE_CACHE_COMPLETE)) 6007 break; 6008 udelay(1); 6009 } 6010 6011 if (i >= usec_timeout) { 6012 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6013 return -EINVAL; 6014 } 6015 6016 if (amdgpu_emu_mode == 1) 6017 adev->hdp.funcs->flush_hdp(adev, NULL); 6018 6019 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6020 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6021 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6022 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6023 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6024 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6025 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6026 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6027 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6028 6029 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6030 6031 for (i = 0; i < me_hdr->jt_size; i++) 6032 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6033 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6034 6035 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6036 6037 return 0; 6038 } 6039 6040 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6041 { 6042 int r; 6043 6044 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6045 return -EINVAL; 6046 6047 gfx_v10_0_cp_gfx_enable(adev, false); 6048 6049 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6050 if (r) { 6051 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6052 return r; 6053 } 6054 6055 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6056 if (r) { 6057 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6058 return r; 6059 } 6060 6061 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6062 if (r) { 6063 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6064 return r; 6065 } 6066 6067 return 0; 6068 } 6069 6070 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6071 { 6072 struct amdgpu_ring *ring; 6073 const struct cs_section_def *sect = NULL; 6074 const struct cs_extent_def *ext = NULL; 6075 int r, i; 6076 int ctx_reg_offset; 6077 6078 /* init the CP */ 6079 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6080 adev->gfx.config.max_hw_contexts - 1); 6081 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6082 6083 gfx_v10_0_cp_gfx_enable(adev, true); 6084 6085 ring = &adev->gfx.gfx_ring[0]; 6086 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6087 if (r) { 6088 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6089 return r; 6090 } 6091 6092 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6093 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6094 6095 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6096 amdgpu_ring_write(ring, 0x80000000); 6097 amdgpu_ring_write(ring, 0x80000000); 6098 6099 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6100 for (ext = sect->section; ext->extent != NULL; ++ext) { 6101 if (sect->id == SECT_CONTEXT) { 6102 amdgpu_ring_write(ring, 6103 PACKET3(PACKET3_SET_CONTEXT_REG, 6104 ext->reg_count)); 6105 amdgpu_ring_write(ring, ext->reg_index - 6106 PACKET3_SET_CONTEXT_REG_START); 6107 for (i = 0; i < ext->reg_count; i++) 6108 amdgpu_ring_write(ring, ext->extent[i]); 6109 } 6110 } 6111 } 6112 6113 ctx_reg_offset = 6114 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6115 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6116 amdgpu_ring_write(ring, ctx_reg_offset); 6117 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6118 6119 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6120 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6121 6122 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6123 amdgpu_ring_write(ring, 0); 6124 6125 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6126 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6127 amdgpu_ring_write(ring, 0x8000); 6128 amdgpu_ring_write(ring, 0x8000); 6129 6130 amdgpu_ring_commit(ring); 6131 6132 /* submit cs packet to copy state 0 to next available state */ 6133 if (adev->gfx.num_gfx_rings > 1) { 6134 /* maximum supported gfx ring is 2 */ 6135 ring = &adev->gfx.gfx_ring[1]; 6136 r = amdgpu_ring_alloc(ring, 2); 6137 if (r) { 6138 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6139 return r; 6140 } 6141 6142 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6143 amdgpu_ring_write(ring, 0); 6144 6145 amdgpu_ring_commit(ring); 6146 } 6147 return 0; 6148 } 6149 6150 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6151 CP_PIPE_ID pipe) 6152 { 6153 u32 tmp; 6154 6155 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6156 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6157 6158 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6159 } 6160 6161 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6162 struct amdgpu_ring *ring) 6163 { 6164 u32 tmp; 6165 6166 if (!amdgpu_async_gfx_ring) { 6167 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6168 if (ring->use_doorbell) { 6169 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6170 DOORBELL_OFFSET, ring->doorbell_index); 6171 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6172 DOORBELL_EN, 1); 6173 } else { 6174 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6175 DOORBELL_EN, 0); 6176 } 6177 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6178 } 6179 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6180 case IP_VERSION(10, 3, 0): 6181 case IP_VERSION(10, 3, 2): 6182 case IP_VERSION(10, 3, 1): 6183 case IP_VERSION(10, 3, 4): 6184 case IP_VERSION(10, 3, 5): 6185 case IP_VERSION(10, 3, 6): 6186 case IP_VERSION(10, 3, 3): 6187 case IP_VERSION(10, 3, 7): 6188 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6189 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6190 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6191 6192 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6193 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6194 break; 6195 default: 6196 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6197 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6198 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6199 6200 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6201 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6202 break; 6203 } 6204 } 6205 6206 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6207 { 6208 struct amdgpu_ring *ring; 6209 u32 tmp; 6210 u32 rb_bufsz; 6211 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6212 6213 /* Set the write pointer delay */ 6214 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6215 6216 /* set the RB to use vmid 0 */ 6217 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6218 6219 /* Init gfx ring 0 for pipe 0 */ 6220 mutex_lock(&adev->srbm_mutex); 6221 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6222 6223 /* Set ring buffer size */ 6224 ring = &adev->gfx.gfx_ring[0]; 6225 rb_bufsz = order_base_2(ring->ring_size / 8); 6226 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6227 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6228 #ifdef __BIG_ENDIAN 6229 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6230 #endif 6231 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6232 6233 /* Initialize the ring buffer's write pointers */ 6234 ring->wptr = 0; 6235 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6236 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6237 6238 /* set the wb address wether it's enabled or not */ 6239 rptr_addr = ring->rptr_gpu_addr; 6240 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6241 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6242 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6243 6244 wptr_gpu_addr = ring->wptr_gpu_addr; 6245 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6246 lower_32_bits(wptr_gpu_addr)); 6247 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6248 upper_32_bits(wptr_gpu_addr)); 6249 6250 mdelay(1); 6251 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6252 6253 rb_addr = ring->gpu_addr >> 8; 6254 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6255 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6256 6257 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6258 6259 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6260 mutex_unlock(&adev->srbm_mutex); 6261 6262 /* Init gfx ring 1 for pipe 1 */ 6263 if (adev->gfx.num_gfx_rings > 1) { 6264 mutex_lock(&adev->srbm_mutex); 6265 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6266 /* maximum supported gfx ring is 2 */ 6267 ring = &adev->gfx.gfx_ring[1]; 6268 rb_bufsz = order_base_2(ring->ring_size / 8); 6269 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6270 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6271 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6272 /* Initialize the ring buffer's write pointers */ 6273 ring->wptr = 0; 6274 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6275 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6276 /* Set the wb address wether it's enabled or not */ 6277 rptr_addr = ring->rptr_gpu_addr; 6278 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6279 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6280 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6281 wptr_gpu_addr = ring->wptr_gpu_addr; 6282 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6283 lower_32_bits(wptr_gpu_addr)); 6284 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6285 upper_32_bits(wptr_gpu_addr)); 6286 6287 mdelay(1); 6288 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6289 6290 rb_addr = ring->gpu_addr >> 8; 6291 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6292 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6293 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6294 6295 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6296 mutex_unlock(&adev->srbm_mutex); 6297 } 6298 /* Switch to pipe 0 */ 6299 mutex_lock(&adev->srbm_mutex); 6300 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6301 mutex_unlock(&adev->srbm_mutex); 6302 6303 /* start the ring */ 6304 gfx_v10_0_cp_gfx_start(adev); 6305 6306 return 0; 6307 } 6308 6309 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6310 { 6311 if (enable) { 6312 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6313 case IP_VERSION(10, 3, 0): 6314 case IP_VERSION(10, 3, 2): 6315 case IP_VERSION(10, 3, 1): 6316 case IP_VERSION(10, 3, 4): 6317 case IP_VERSION(10, 3, 5): 6318 case IP_VERSION(10, 3, 6): 6319 case IP_VERSION(10, 3, 3): 6320 case IP_VERSION(10, 3, 7): 6321 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6322 break; 6323 default: 6324 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6325 break; 6326 } 6327 } else { 6328 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6329 case IP_VERSION(10, 3, 0): 6330 case IP_VERSION(10, 3, 2): 6331 case IP_VERSION(10, 3, 1): 6332 case IP_VERSION(10, 3, 4): 6333 case IP_VERSION(10, 3, 5): 6334 case IP_VERSION(10, 3, 6): 6335 case IP_VERSION(10, 3, 3): 6336 case IP_VERSION(10, 3, 7): 6337 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6338 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6339 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6340 break; 6341 default: 6342 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6343 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6344 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6345 break; 6346 } 6347 adev->gfx.kiq[0].ring.sched.ready = false; 6348 } 6349 udelay(50); 6350 } 6351 6352 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6353 { 6354 const struct gfx_firmware_header_v1_0 *mec_hdr; 6355 const __le32 *fw_data; 6356 unsigned int i; 6357 u32 tmp; 6358 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6359 6360 if (!adev->gfx.mec_fw) 6361 return -EINVAL; 6362 6363 gfx_v10_0_cp_compute_enable(adev, false); 6364 6365 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6366 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6367 6368 fw_data = (const __le32 *) 6369 (adev->gfx.mec_fw->data + 6370 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6371 6372 /* Trigger an invalidation of the L1 instruction caches */ 6373 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6374 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6375 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6376 6377 /* Wait for invalidation complete */ 6378 for (i = 0; i < usec_timeout; i++) { 6379 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6380 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6381 INVALIDATE_CACHE_COMPLETE)) 6382 break; 6383 udelay(1); 6384 } 6385 6386 if (i >= usec_timeout) { 6387 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6388 return -EINVAL; 6389 } 6390 6391 if (amdgpu_emu_mode == 1) 6392 adev->hdp.funcs->flush_hdp(adev, NULL); 6393 6394 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6395 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6396 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6397 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6398 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6399 6400 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6401 0xFFFFF000); 6402 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6403 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6404 6405 /* MEC1 */ 6406 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6407 6408 for (i = 0; i < mec_hdr->jt_size; i++) 6409 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6410 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6411 6412 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6413 6414 /* 6415 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6416 * different microcode than MEC1. 6417 */ 6418 6419 return 0; 6420 } 6421 6422 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6423 { 6424 uint32_t tmp; 6425 struct amdgpu_device *adev = ring->adev; 6426 6427 /* tell RLC which is KIQ queue */ 6428 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6429 case IP_VERSION(10, 3, 0): 6430 case IP_VERSION(10, 3, 2): 6431 case IP_VERSION(10, 3, 1): 6432 case IP_VERSION(10, 3, 4): 6433 case IP_VERSION(10, 3, 5): 6434 case IP_VERSION(10, 3, 6): 6435 case IP_VERSION(10, 3, 3): 6436 case IP_VERSION(10, 3, 7): 6437 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6438 tmp &= 0xffffff00; 6439 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6440 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6441 tmp |= 0x80; 6442 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6443 break; 6444 default: 6445 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6446 tmp &= 0xffffff00; 6447 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6448 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6449 tmp |= 0x80; 6450 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6451 break; 6452 } 6453 } 6454 6455 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6456 struct v10_gfx_mqd *mqd, 6457 struct amdgpu_mqd_prop *prop) 6458 { 6459 bool priority = 0; 6460 u32 tmp; 6461 6462 /* set up default queue priority level 6463 * 0x0 = low priority, 0x1 = high priority 6464 */ 6465 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6466 priority = 1; 6467 6468 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6469 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6470 mqd->cp_gfx_hqd_queue_priority = tmp; 6471 } 6472 6473 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6474 struct amdgpu_mqd_prop *prop) 6475 { 6476 struct v10_gfx_mqd *mqd = m; 6477 uint64_t hqd_gpu_addr, wb_gpu_addr; 6478 uint32_t tmp; 6479 uint32_t rb_bufsz; 6480 6481 /* set up gfx hqd wptr */ 6482 mqd->cp_gfx_hqd_wptr = 0; 6483 mqd->cp_gfx_hqd_wptr_hi = 0; 6484 6485 /* set the pointer to the MQD */ 6486 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6487 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6488 6489 /* set up mqd control */ 6490 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6491 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6492 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6493 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6494 mqd->cp_gfx_mqd_control = tmp; 6495 6496 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6497 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6498 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6499 mqd->cp_gfx_hqd_vmid = 0; 6500 6501 /* set up gfx queue priority */ 6502 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6503 6504 /* set up time quantum */ 6505 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6506 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6507 mqd->cp_gfx_hqd_quantum = tmp; 6508 6509 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6510 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6511 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6512 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6513 6514 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6515 wb_gpu_addr = prop->rptr_gpu_addr; 6516 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6517 mqd->cp_gfx_hqd_rptr_addr_hi = 6518 upper_32_bits(wb_gpu_addr) & 0xffff; 6519 6520 /* set up rb_wptr_poll addr */ 6521 wb_gpu_addr = prop->wptr_gpu_addr; 6522 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6523 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6524 6525 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6526 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6527 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6528 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6529 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6530 #ifdef __BIG_ENDIAN 6531 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6532 #endif 6533 mqd->cp_gfx_hqd_cntl = tmp; 6534 6535 /* set up cp_doorbell_control */ 6536 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6537 if (prop->use_doorbell) { 6538 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6539 DOORBELL_OFFSET, prop->doorbell_index); 6540 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6541 DOORBELL_EN, 1); 6542 } else 6543 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6544 DOORBELL_EN, 0); 6545 mqd->cp_rb_doorbell_control = tmp; 6546 6547 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6548 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6549 6550 /* active the queue */ 6551 mqd->cp_gfx_hqd_active = 1; 6552 6553 return 0; 6554 } 6555 6556 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6557 { 6558 struct amdgpu_device *adev = ring->adev; 6559 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6560 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6561 6562 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6563 memset((void *)mqd, 0, sizeof(*mqd)); 6564 mutex_lock(&adev->srbm_mutex); 6565 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6566 amdgpu_ring_init_mqd(ring); 6567 6568 /* 6569 * if there are 2 gfx rings, set the lower doorbell 6570 * range of the first ring, otherwise the range of 6571 * the second ring will override the first ring 6572 */ 6573 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6574 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6575 6576 nv_grbm_select(adev, 0, 0, 0, 0); 6577 mutex_unlock(&adev->srbm_mutex); 6578 if (adev->gfx.me.mqd_backup[mqd_idx]) 6579 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6580 } else { 6581 mutex_lock(&adev->srbm_mutex); 6582 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6583 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6584 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6585 6586 nv_grbm_select(adev, 0, 0, 0, 0); 6587 mutex_unlock(&adev->srbm_mutex); 6588 /* restore mqd with the backup copy */ 6589 if (adev->gfx.me.mqd_backup[mqd_idx]) 6590 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6591 /* reset the ring */ 6592 ring->wptr = 0; 6593 *ring->wptr_cpu_addr = 0; 6594 amdgpu_ring_clear_ring(ring); 6595 } 6596 6597 return 0; 6598 } 6599 6600 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6601 { 6602 int r, i; 6603 struct amdgpu_ring *ring; 6604 6605 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6606 ring = &adev->gfx.gfx_ring[i]; 6607 6608 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6609 if (unlikely(r != 0)) 6610 return r; 6611 6612 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6613 if (!r) { 6614 r = gfx_v10_0_gfx_init_queue(ring); 6615 amdgpu_bo_kunmap(ring->mqd_obj); 6616 ring->mqd_ptr = NULL; 6617 } 6618 amdgpu_bo_unreserve(ring->mqd_obj); 6619 if (r) 6620 return r; 6621 } 6622 6623 r = amdgpu_gfx_enable_kgq(adev, 0); 6624 if (r) 6625 return r; 6626 6627 return gfx_v10_0_cp_gfx_start(adev); 6628 } 6629 6630 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6631 struct amdgpu_mqd_prop *prop) 6632 { 6633 struct v10_compute_mqd *mqd = m; 6634 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6635 uint32_t tmp; 6636 6637 mqd->header = 0xC0310800; 6638 mqd->compute_pipelinestat_enable = 0x00000001; 6639 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6640 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6641 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6642 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6643 mqd->compute_misc_reserved = 0x00000003; 6644 6645 eop_base_addr = prop->eop_gpu_addr >> 8; 6646 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6647 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6648 6649 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6650 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6651 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6652 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6653 6654 mqd->cp_hqd_eop_control = tmp; 6655 6656 /* enable doorbell? */ 6657 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6658 6659 if (prop->use_doorbell) { 6660 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6661 DOORBELL_OFFSET, prop->doorbell_index); 6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6663 DOORBELL_EN, 1); 6664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6665 DOORBELL_SOURCE, 0); 6666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6667 DOORBELL_HIT, 0); 6668 } else { 6669 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6670 DOORBELL_EN, 0); 6671 } 6672 6673 mqd->cp_hqd_pq_doorbell_control = tmp; 6674 6675 /* disable the queue if it's active */ 6676 mqd->cp_hqd_dequeue_request = 0; 6677 mqd->cp_hqd_pq_rptr = 0; 6678 mqd->cp_hqd_pq_wptr_lo = 0; 6679 mqd->cp_hqd_pq_wptr_hi = 0; 6680 6681 /* set the pointer to the MQD */ 6682 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6683 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6684 6685 /* set MQD vmid to 0 */ 6686 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6687 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6688 mqd->cp_mqd_control = tmp; 6689 6690 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6691 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6692 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6693 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6694 6695 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6696 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6697 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6698 (order_base_2(prop->queue_size / 4) - 1)); 6699 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6700 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6701 #ifdef __BIG_ENDIAN 6702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6703 #endif 6704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6705 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6706 prop->allow_tunneling); 6707 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6708 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6709 mqd->cp_hqd_pq_control = tmp; 6710 6711 /* set the wb address whether it's enabled or not */ 6712 wb_gpu_addr = prop->rptr_gpu_addr; 6713 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6714 mqd->cp_hqd_pq_rptr_report_addr_hi = 6715 upper_32_bits(wb_gpu_addr) & 0xffff; 6716 6717 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6718 wb_gpu_addr = prop->wptr_gpu_addr; 6719 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6720 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6721 6722 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6723 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6724 6725 /* set the vmid for the queue */ 6726 mqd->cp_hqd_vmid = 0; 6727 6728 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6729 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6730 mqd->cp_hqd_persistent_state = tmp; 6731 6732 /* set MIN_IB_AVAIL_SIZE */ 6733 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6734 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6735 mqd->cp_hqd_ib_control = tmp; 6736 6737 /* set static priority for a compute queue/ring */ 6738 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6739 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6740 6741 mqd->cp_hqd_active = prop->hqd_active; 6742 6743 return 0; 6744 } 6745 6746 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6747 { 6748 struct amdgpu_device *adev = ring->adev; 6749 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6750 int j; 6751 6752 /* inactivate the queue */ 6753 if (amdgpu_sriov_vf(adev)) 6754 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6755 6756 /* disable wptr polling */ 6757 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6758 6759 /* disable the queue if it's active */ 6760 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6761 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6762 for (j = 0; j < adev->usec_timeout; j++) { 6763 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6764 break; 6765 udelay(1); 6766 } 6767 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6768 mqd->cp_hqd_dequeue_request); 6769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6770 mqd->cp_hqd_pq_rptr); 6771 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6772 mqd->cp_hqd_pq_wptr_lo); 6773 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6774 mqd->cp_hqd_pq_wptr_hi); 6775 } 6776 6777 /* disable doorbells */ 6778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6779 6780 /* write the EOP addr */ 6781 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6782 mqd->cp_hqd_eop_base_addr_lo); 6783 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6784 mqd->cp_hqd_eop_base_addr_hi); 6785 6786 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6787 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6788 mqd->cp_hqd_eop_control); 6789 6790 /* set the pointer to the MQD */ 6791 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6792 mqd->cp_mqd_base_addr_lo); 6793 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6794 mqd->cp_mqd_base_addr_hi); 6795 6796 /* set MQD vmid to 0 */ 6797 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6798 mqd->cp_mqd_control); 6799 6800 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6801 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6802 mqd->cp_hqd_pq_base_lo); 6803 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6804 mqd->cp_hqd_pq_base_hi); 6805 6806 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6807 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6808 mqd->cp_hqd_pq_control); 6809 6810 /* set the wb address whether it's enabled or not */ 6811 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6812 mqd->cp_hqd_pq_rptr_report_addr_lo); 6813 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6814 mqd->cp_hqd_pq_rptr_report_addr_hi); 6815 6816 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6817 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6818 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6819 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6820 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6821 6822 /* enable the doorbell if requested */ 6823 if (ring->use_doorbell) { 6824 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6825 (adev->doorbell_index.kiq * 2) << 2); 6826 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6827 (adev->doorbell_index.userqueue_end * 2) << 2); 6828 } 6829 6830 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6831 mqd->cp_hqd_pq_doorbell_control); 6832 6833 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6834 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6835 mqd->cp_hqd_pq_wptr_lo); 6836 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6837 mqd->cp_hqd_pq_wptr_hi); 6838 6839 /* set the vmid for the queue */ 6840 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6841 6842 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6843 mqd->cp_hqd_persistent_state); 6844 6845 /* activate the queue */ 6846 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6847 mqd->cp_hqd_active); 6848 6849 if (ring->use_doorbell) 6850 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6851 6852 return 0; 6853 } 6854 6855 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6856 { 6857 struct amdgpu_device *adev = ring->adev; 6858 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6859 6860 gfx_v10_0_kiq_setting(ring); 6861 6862 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6863 /* reset MQD to a clean status */ 6864 if (adev->gfx.kiq[0].mqd_backup) 6865 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6866 6867 /* reset ring buffer */ 6868 ring->wptr = 0; 6869 amdgpu_ring_clear_ring(ring); 6870 6871 mutex_lock(&adev->srbm_mutex); 6872 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6873 gfx_v10_0_kiq_init_register(ring); 6874 nv_grbm_select(adev, 0, 0, 0, 0); 6875 mutex_unlock(&adev->srbm_mutex); 6876 } else { 6877 memset((void *)mqd, 0, sizeof(*mqd)); 6878 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6879 amdgpu_ring_clear_ring(ring); 6880 mutex_lock(&adev->srbm_mutex); 6881 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6882 amdgpu_ring_init_mqd(ring); 6883 gfx_v10_0_kiq_init_register(ring); 6884 nv_grbm_select(adev, 0, 0, 0, 0); 6885 mutex_unlock(&adev->srbm_mutex); 6886 6887 if (adev->gfx.kiq[0].mqd_backup) 6888 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6889 } 6890 6891 return 0; 6892 } 6893 6894 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6895 { 6896 struct amdgpu_device *adev = ring->adev; 6897 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6898 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6899 6900 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6901 memset((void *)mqd, 0, sizeof(*mqd)); 6902 mutex_lock(&adev->srbm_mutex); 6903 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6904 amdgpu_ring_init_mqd(ring); 6905 nv_grbm_select(adev, 0, 0, 0, 0); 6906 mutex_unlock(&adev->srbm_mutex); 6907 6908 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6909 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6910 } else { 6911 /* restore MQD to a clean status */ 6912 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6913 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6914 /* reset ring buffer */ 6915 ring->wptr = 0; 6916 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6917 amdgpu_ring_clear_ring(ring); 6918 } 6919 6920 return 0; 6921 } 6922 6923 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6924 { 6925 struct amdgpu_ring *ring; 6926 int r; 6927 6928 ring = &adev->gfx.kiq[0].ring; 6929 6930 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6931 if (unlikely(r != 0)) 6932 return r; 6933 6934 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6935 if (unlikely(r != 0)) { 6936 amdgpu_bo_unreserve(ring->mqd_obj); 6937 return r; 6938 } 6939 6940 gfx_v10_0_kiq_init_queue(ring); 6941 amdgpu_bo_kunmap(ring->mqd_obj); 6942 ring->mqd_ptr = NULL; 6943 amdgpu_bo_unreserve(ring->mqd_obj); 6944 return 0; 6945 } 6946 6947 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6948 { 6949 struct amdgpu_ring *ring = NULL; 6950 int r = 0, i; 6951 6952 gfx_v10_0_cp_compute_enable(adev, true); 6953 6954 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6955 ring = &adev->gfx.compute_ring[i]; 6956 6957 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6958 if (unlikely(r != 0)) 6959 goto done; 6960 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6961 if (!r) { 6962 r = gfx_v10_0_kcq_init_queue(ring); 6963 amdgpu_bo_kunmap(ring->mqd_obj); 6964 ring->mqd_ptr = NULL; 6965 } 6966 amdgpu_bo_unreserve(ring->mqd_obj); 6967 if (r) 6968 goto done; 6969 } 6970 6971 r = amdgpu_gfx_enable_kcq(adev, 0); 6972 done: 6973 return r; 6974 } 6975 6976 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6977 { 6978 int r, i; 6979 struct amdgpu_ring *ring; 6980 6981 if (!(adev->flags & AMD_IS_APU)) 6982 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6983 6984 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6985 /* legacy firmware loading */ 6986 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6987 if (r) 6988 return r; 6989 6990 r = gfx_v10_0_cp_compute_load_microcode(adev); 6991 if (r) 6992 return r; 6993 } 6994 6995 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6996 r = amdgpu_mes_kiq_hw_init(adev); 6997 else 6998 r = gfx_v10_0_kiq_resume(adev); 6999 if (r) 7000 return r; 7001 7002 r = gfx_v10_0_kcq_resume(adev); 7003 if (r) 7004 return r; 7005 7006 if (!amdgpu_async_gfx_ring) { 7007 r = gfx_v10_0_cp_gfx_resume(adev); 7008 if (r) 7009 return r; 7010 } else { 7011 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7012 if (r) 7013 return r; 7014 } 7015 7016 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7017 ring = &adev->gfx.gfx_ring[i]; 7018 r = amdgpu_ring_test_helper(ring); 7019 if (r) 7020 return r; 7021 } 7022 7023 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7024 ring = &adev->gfx.compute_ring[i]; 7025 r = amdgpu_ring_test_helper(ring); 7026 if (r) 7027 return r; 7028 } 7029 7030 return 0; 7031 } 7032 7033 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7034 { 7035 gfx_v10_0_cp_gfx_enable(adev, enable); 7036 gfx_v10_0_cp_compute_enable(adev, enable); 7037 } 7038 7039 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7040 { 7041 uint32_t data, pattern = 0xDEADBEEF; 7042 7043 /* 7044 * check if mmVGT_ESGS_RING_SIZE_UMD 7045 * has been remapped to mmVGT_ESGS_RING_SIZE 7046 */ 7047 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7048 case IP_VERSION(10, 3, 0): 7049 case IP_VERSION(10, 3, 2): 7050 case IP_VERSION(10, 3, 4): 7051 case IP_VERSION(10, 3, 5): 7052 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7053 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7054 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7055 7056 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7057 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7058 return true; 7059 } 7060 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7061 break; 7062 case IP_VERSION(10, 3, 1): 7063 case IP_VERSION(10, 3, 3): 7064 case IP_VERSION(10, 3, 6): 7065 case IP_VERSION(10, 3, 7): 7066 return true; 7067 default: 7068 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7069 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7070 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7071 7072 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7073 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7074 return true; 7075 } 7076 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7077 break; 7078 } 7079 7080 return false; 7081 } 7082 7083 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7084 { 7085 uint32_t data; 7086 7087 if (amdgpu_sriov_vf(adev)) 7088 return; 7089 7090 /* 7091 * Initialize cam_index to 0 7092 * index will auto-inc after each data writing 7093 */ 7094 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7095 7096 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7097 case IP_VERSION(10, 3, 0): 7098 case IP_VERSION(10, 3, 2): 7099 case IP_VERSION(10, 3, 1): 7100 case IP_VERSION(10, 3, 4): 7101 case IP_VERSION(10, 3, 5): 7102 case IP_VERSION(10, 3, 6): 7103 case IP_VERSION(10, 3, 3): 7104 case IP_VERSION(10, 3, 7): 7105 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7106 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7107 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7108 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7109 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7110 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7111 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7112 7113 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7114 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7115 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7116 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7117 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7118 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7119 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7120 7121 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7122 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7123 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7124 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7125 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7126 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7127 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7128 7129 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7130 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7131 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7132 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7133 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7134 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7135 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7136 7137 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7138 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7139 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7140 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7141 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7142 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7143 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7144 7145 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7146 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7147 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7148 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7149 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7150 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7151 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7152 7153 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7154 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7155 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7156 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7157 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7158 break; 7159 default: 7160 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7161 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7162 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7163 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7164 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7165 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7166 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7167 7168 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7169 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7170 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7171 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7172 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7173 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7174 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7175 7176 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7177 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7178 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7179 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7180 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7181 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7182 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7183 7184 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7185 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7186 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7187 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7188 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7189 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7190 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7191 7192 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7193 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7194 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7195 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7196 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7197 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7198 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7199 7200 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7201 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7202 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7203 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7204 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7205 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7206 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7207 7208 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7209 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7210 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7211 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7212 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7213 break; 7214 } 7215 7216 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7217 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7218 } 7219 7220 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7221 { 7222 uint32_t data; 7223 7224 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7225 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7226 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7227 7228 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7229 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7230 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7231 } 7232 7233 static int gfx_v10_0_hw_init(void *handle) 7234 { 7235 int r; 7236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7237 7238 if (!amdgpu_emu_mode) 7239 gfx_v10_0_init_golden_registers(adev); 7240 7241 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7242 /** 7243 * For gfx 10, rlc firmware loading relies on smu firmware is 7244 * loaded firstly, so in direct type, it has to load smc ucode 7245 * here before rlc. 7246 */ 7247 if (!(adev->flags & AMD_IS_APU)) { 7248 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7249 if (r) 7250 return r; 7251 } 7252 gfx_v10_0_disable_gpa_mode(adev); 7253 } 7254 7255 /* if GRBM CAM not remapped, set up the remapping */ 7256 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7257 gfx_v10_0_setup_grbm_cam_remapping(adev); 7258 7259 gfx_v10_0_constants_init(adev); 7260 7261 r = gfx_v10_0_rlc_resume(adev); 7262 if (r) 7263 return r; 7264 7265 /* 7266 * init golden registers and rlc resume may override some registers, 7267 * reconfig them here 7268 */ 7269 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7270 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7271 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7272 gfx_v10_0_tcp_harvest(adev); 7273 7274 r = gfx_v10_0_cp_resume(adev); 7275 if (r) 7276 return r; 7277 7278 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7279 gfx_v10_3_program_pbb_mode(adev); 7280 7281 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7282 gfx_v10_3_set_power_brake_sequence(adev); 7283 7284 return r; 7285 } 7286 7287 static int gfx_v10_0_hw_fini(void *handle) 7288 { 7289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7290 7291 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7292 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7293 7294 /* WA added for Vangogh asic fixing the SMU suspend failure 7295 * It needs to set power gating again during gfxoff control 7296 * otherwise the gfxoff disallowing will be failed to set. 7297 */ 7298 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7299 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); 7300 7301 if (!adev->no_hw_access) { 7302 if (amdgpu_async_gfx_ring) { 7303 if (amdgpu_gfx_disable_kgq(adev, 0)) 7304 DRM_ERROR("KGQ disable failed\n"); 7305 } 7306 7307 if (amdgpu_gfx_disable_kcq(adev, 0)) 7308 DRM_ERROR("KCQ disable failed\n"); 7309 } 7310 7311 if (amdgpu_sriov_vf(adev)) { 7312 gfx_v10_0_cp_gfx_enable(adev, false); 7313 /* Remove the steps of clearing KIQ position. 7314 * It causes GFX hang when another Win guest is rendering. 7315 */ 7316 return 0; 7317 } 7318 gfx_v10_0_cp_enable(adev, false); 7319 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7320 7321 return 0; 7322 } 7323 7324 static int gfx_v10_0_suspend(void *handle) 7325 { 7326 return gfx_v10_0_hw_fini(handle); 7327 } 7328 7329 static int gfx_v10_0_resume(void *handle) 7330 { 7331 return gfx_v10_0_hw_init(handle); 7332 } 7333 7334 static bool gfx_v10_0_is_idle(void *handle) 7335 { 7336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7337 7338 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7339 GRBM_STATUS, GUI_ACTIVE)) 7340 return false; 7341 else 7342 return true; 7343 } 7344 7345 static int gfx_v10_0_wait_for_idle(void *handle) 7346 { 7347 unsigned int i; 7348 u32 tmp; 7349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7350 7351 for (i = 0; i < adev->usec_timeout; i++) { 7352 /* read MC_STATUS */ 7353 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7354 GRBM_STATUS__GUI_ACTIVE_MASK; 7355 7356 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7357 return 0; 7358 udelay(1); 7359 } 7360 return -ETIMEDOUT; 7361 } 7362 7363 static int gfx_v10_0_soft_reset(void *handle) 7364 { 7365 u32 grbm_soft_reset = 0; 7366 u32 tmp; 7367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7368 7369 /* GRBM_STATUS */ 7370 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7371 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7372 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7373 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7374 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7375 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7376 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7377 GRBM_SOFT_RESET, SOFT_RESET_CP, 7378 1); 7379 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7380 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7381 1); 7382 } 7383 7384 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7385 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7386 GRBM_SOFT_RESET, SOFT_RESET_CP, 7387 1); 7388 } 7389 7390 /* GRBM_STATUS2 */ 7391 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7392 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7393 case IP_VERSION(10, 3, 0): 7394 case IP_VERSION(10, 3, 2): 7395 case IP_VERSION(10, 3, 1): 7396 case IP_VERSION(10, 3, 4): 7397 case IP_VERSION(10, 3, 5): 7398 case IP_VERSION(10, 3, 6): 7399 case IP_VERSION(10, 3, 3): 7400 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7401 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7402 GRBM_SOFT_RESET, 7403 SOFT_RESET_RLC, 7404 1); 7405 break; 7406 default: 7407 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7408 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7409 GRBM_SOFT_RESET, 7410 SOFT_RESET_RLC, 7411 1); 7412 break; 7413 } 7414 7415 if (grbm_soft_reset) { 7416 /* stop the rlc */ 7417 gfx_v10_0_rlc_stop(adev); 7418 7419 /* Disable GFX parsing/prefetching */ 7420 gfx_v10_0_cp_gfx_enable(adev, false); 7421 7422 /* Disable MEC parsing/prefetching */ 7423 gfx_v10_0_cp_compute_enable(adev, false); 7424 7425 if (grbm_soft_reset) { 7426 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7427 tmp |= grbm_soft_reset; 7428 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7429 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7430 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7431 7432 udelay(50); 7433 7434 tmp &= ~grbm_soft_reset; 7435 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7436 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7437 } 7438 7439 /* Wait a little for things to settle down */ 7440 udelay(50); 7441 } 7442 return 0; 7443 } 7444 7445 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7446 { 7447 uint64_t clock, clock_lo, clock_hi, hi_check; 7448 7449 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7450 case IP_VERSION(10, 1, 3): 7451 case IP_VERSION(10, 1, 4): 7452 preempt_disable(); 7453 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7454 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7455 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7456 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7457 * roughly every 42 seconds. 7458 */ 7459 if (hi_check != clock_hi) { 7460 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7461 clock_hi = hi_check; 7462 } 7463 preempt_enable(); 7464 clock = clock_lo | (clock_hi << 32ULL); 7465 break; 7466 case IP_VERSION(10, 3, 1): 7467 case IP_VERSION(10, 3, 3): 7468 case IP_VERSION(10, 3, 7): 7469 preempt_disable(); 7470 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7471 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7472 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7473 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7474 * roughly every 42 seconds. 7475 */ 7476 if (hi_check != clock_hi) { 7477 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7478 clock_hi = hi_check; 7479 } 7480 preempt_enable(); 7481 clock = clock_lo | (clock_hi << 32ULL); 7482 break; 7483 case IP_VERSION(10, 3, 6): 7484 preempt_disable(); 7485 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7486 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7487 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7488 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7489 * roughly every 42 seconds. 7490 */ 7491 if (hi_check != clock_hi) { 7492 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7493 clock_hi = hi_check; 7494 } 7495 preempt_enable(); 7496 clock = clock_lo | (clock_hi << 32ULL); 7497 break; 7498 default: 7499 preempt_disable(); 7500 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7501 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7502 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7503 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7504 * roughly every 42 seconds. 7505 */ 7506 if (hi_check != clock_hi) { 7507 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7508 clock_hi = hi_check; 7509 } 7510 preempt_enable(); 7511 clock = clock_lo | (clock_hi << 32ULL); 7512 break; 7513 } 7514 return clock; 7515 } 7516 7517 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7518 uint32_t vmid, 7519 uint32_t gds_base, uint32_t gds_size, 7520 uint32_t gws_base, uint32_t gws_size, 7521 uint32_t oa_base, uint32_t oa_size) 7522 { 7523 struct amdgpu_device *adev = ring->adev; 7524 7525 /* GDS Base */ 7526 gfx_v10_0_write_data_to_reg(ring, 0, false, 7527 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7528 gds_base); 7529 7530 /* GDS Size */ 7531 gfx_v10_0_write_data_to_reg(ring, 0, false, 7532 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7533 gds_size); 7534 7535 /* GWS */ 7536 gfx_v10_0_write_data_to_reg(ring, 0, false, 7537 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7538 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7539 7540 /* OA */ 7541 gfx_v10_0_write_data_to_reg(ring, 0, false, 7542 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7543 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7544 } 7545 7546 static int gfx_v10_0_early_init(void *handle) 7547 { 7548 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7549 7550 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7551 7552 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7553 case IP_VERSION(10, 1, 10): 7554 case IP_VERSION(10, 1, 1): 7555 case IP_VERSION(10, 1, 2): 7556 case IP_VERSION(10, 1, 3): 7557 case IP_VERSION(10, 1, 4): 7558 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7559 break; 7560 case IP_VERSION(10, 3, 0): 7561 case IP_VERSION(10, 3, 2): 7562 case IP_VERSION(10, 3, 1): 7563 case IP_VERSION(10, 3, 4): 7564 case IP_VERSION(10, 3, 5): 7565 case IP_VERSION(10, 3, 6): 7566 case IP_VERSION(10, 3, 3): 7567 case IP_VERSION(10, 3, 7): 7568 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7569 break; 7570 default: 7571 break; 7572 } 7573 7574 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7575 AMDGPU_MAX_COMPUTE_RINGS); 7576 7577 gfx_v10_0_set_kiq_pm4_funcs(adev); 7578 gfx_v10_0_set_ring_funcs(adev); 7579 gfx_v10_0_set_irq_funcs(adev); 7580 gfx_v10_0_set_gds_init(adev); 7581 gfx_v10_0_set_rlc_funcs(adev); 7582 gfx_v10_0_set_mqd_funcs(adev); 7583 7584 /* init rlcg reg access ctrl */ 7585 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7586 7587 return gfx_v10_0_init_microcode(adev); 7588 } 7589 7590 static int gfx_v10_0_late_init(void *handle) 7591 { 7592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7593 int r; 7594 7595 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7596 if (r) 7597 return r; 7598 7599 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7600 if (r) 7601 return r; 7602 7603 return 0; 7604 } 7605 7606 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7607 { 7608 uint32_t rlc_cntl; 7609 7610 /* if RLC is not enabled, do nothing */ 7611 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7612 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7613 } 7614 7615 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7616 { 7617 uint32_t data; 7618 unsigned int i; 7619 7620 data = RLC_SAFE_MODE__CMD_MASK; 7621 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7622 7623 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7624 case IP_VERSION(10, 3, 0): 7625 case IP_VERSION(10, 3, 2): 7626 case IP_VERSION(10, 3, 1): 7627 case IP_VERSION(10, 3, 4): 7628 case IP_VERSION(10, 3, 5): 7629 case IP_VERSION(10, 3, 6): 7630 case IP_VERSION(10, 3, 3): 7631 case IP_VERSION(10, 3, 7): 7632 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7633 7634 /* wait for RLC_SAFE_MODE */ 7635 for (i = 0; i < adev->usec_timeout; i++) { 7636 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7637 RLC_SAFE_MODE, CMD)) 7638 break; 7639 udelay(1); 7640 } 7641 break; 7642 default: 7643 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7644 7645 /* wait for RLC_SAFE_MODE */ 7646 for (i = 0; i < adev->usec_timeout; i++) { 7647 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7648 RLC_SAFE_MODE, CMD)) 7649 break; 7650 udelay(1); 7651 } 7652 break; 7653 } 7654 } 7655 7656 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7657 { 7658 uint32_t data; 7659 7660 data = RLC_SAFE_MODE__CMD_MASK; 7661 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7662 case IP_VERSION(10, 3, 0): 7663 case IP_VERSION(10, 3, 2): 7664 case IP_VERSION(10, 3, 1): 7665 case IP_VERSION(10, 3, 4): 7666 case IP_VERSION(10, 3, 5): 7667 case IP_VERSION(10, 3, 6): 7668 case IP_VERSION(10, 3, 3): 7669 case IP_VERSION(10, 3, 7): 7670 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7671 break; 7672 default: 7673 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7674 break; 7675 } 7676 } 7677 7678 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7679 bool enable) 7680 { 7681 uint32_t data, def; 7682 7683 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7684 return; 7685 7686 /* It is disabled by HW by default */ 7687 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7688 /* 0 - Disable some blocks' MGCG */ 7689 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7690 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7691 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7692 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7693 7694 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7695 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7696 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7697 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7698 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7699 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7700 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7701 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7702 7703 if (def != data) 7704 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7705 7706 /* MGLS is a global flag to control all MGLS in GFX */ 7707 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7708 /* 2 - RLC memory Light sleep */ 7709 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7710 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7711 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7712 if (def != data) 7713 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7714 } 7715 /* 3 - CP memory Light sleep */ 7716 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7717 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7718 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7719 if (def != data) 7720 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7721 } 7722 } 7723 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7724 /* 1 - MGCG_OVERRIDE */ 7725 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7726 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7727 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7728 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7729 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7730 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7731 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7732 if (def != data) 7733 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7734 7735 /* 2 - disable MGLS in CP */ 7736 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7737 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7738 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7739 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7740 } 7741 7742 /* 3 - disable MGLS in RLC */ 7743 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7744 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7745 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7746 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7747 } 7748 7749 } 7750 } 7751 7752 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7753 bool enable) 7754 { 7755 uint32_t data, def; 7756 7757 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7758 return; 7759 7760 /* Enable 3D CGCG/CGLS */ 7761 if (enable) { 7762 /* write cmd to clear cgcg/cgls ov */ 7763 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7764 7765 /* unset CGCG override */ 7766 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7767 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7768 7769 /* update CGCG and CGLS override bits */ 7770 if (def != data) 7771 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7772 7773 /* enable 3Dcgcg FSM(0x0000363f) */ 7774 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7775 data = 0; 7776 7777 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7778 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7779 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7780 7781 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7782 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7783 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7784 7785 if (def != data) 7786 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7787 7788 /* set IDLE_POLL_COUNT(0x00900100) */ 7789 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7790 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7791 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7792 if (def != data) 7793 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7794 } else { 7795 /* Disable CGCG/CGLS */ 7796 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7797 7798 /* disable cgcg, cgls should be disabled */ 7799 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7800 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7801 7802 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7803 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7804 7805 /* disable cgcg and cgls in FSM */ 7806 if (def != data) 7807 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7808 } 7809 } 7810 7811 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7812 bool enable) 7813 { 7814 uint32_t def, data; 7815 7816 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7817 return; 7818 7819 if (enable) { 7820 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7821 7822 /* unset CGCG override */ 7823 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7824 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7825 7826 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7827 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7828 7829 /* update CGCG and CGLS override bits */ 7830 if (def != data) 7831 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7832 7833 /* enable cgcg FSM(0x0000363F) */ 7834 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7835 data = 0; 7836 7837 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7838 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7839 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7840 7841 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7842 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7843 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7844 7845 if (def != data) 7846 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7847 7848 /* set IDLE_POLL_COUNT(0x00900100) */ 7849 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7850 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7851 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7852 if (def != data) 7853 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7854 } else { 7855 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7856 7857 /* reset CGCG/CGLS bits */ 7858 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7859 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7860 7861 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7862 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7863 7864 /* disable cgcg and cgls in FSM */ 7865 if (def != data) 7866 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7867 } 7868 } 7869 7870 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7871 bool enable) 7872 { 7873 uint32_t def, data; 7874 7875 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7876 return; 7877 7878 if (enable) { 7879 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7880 /* unset FGCG override */ 7881 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7882 /* update FGCG override bits */ 7883 if (def != data) 7884 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7885 7886 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7887 /* unset RLC SRAM CLK GATER override */ 7888 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7889 /* update RLC SRAM CLK GATER override bits */ 7890 if (def != data) 7891 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7892 } else { 7893 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7894 /* reset FGCG bits */ 7895 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7896 /* disable FGCG*/ 7897 if (def != data) 7898 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7899 7900 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7901 /* reset RLC SRAM CLK GATER bits */ 7902 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7903 /* disable RLC SRAM CLK*/ 7904 if (def != data) 7905 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7906 } 7907 } 7908 7909 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7910 { 7911 uint32_t reg_data = 0; 7912 uint32_t reg_idx = 0; 7913 uint32_t i; 7914 7915 const uint32_t tcp_ctrl_regs[] = { 7916 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7917 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7918 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7919 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7920 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7921 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7922 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7923 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7924 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7925 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7926 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7927 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7928 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7929 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7930 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7931 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7932 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7933 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7934 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7935 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7936 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7937 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7938 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7939 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7940 }; 7941 7942 const uint32_t tcp_ctrl_regs_nv12[] = { 7943 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7944 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7945 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7946 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7947 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7948 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7949 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7950 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7951 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7952 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7953 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7954 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7955 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7956 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7957 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7958 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7959 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7960 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7961 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7962 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7963 }; 7964 7965 const uint32_t sm_ctlr_regs[] = { 7966 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7967 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7968 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7969 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7970 }; 7971 7972 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 7973 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7974 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7975 tcp_ctrl_regs_nv12[i]; 7976 reg_data = RREG32(reg_idx); 7977 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7978 WREG32(reg_idx, reg_data); 7979 } 7980 } else { 7981 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7982 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7983 tcp_ctrl_regs[i]; 7984 reg_data = RREG32(reg_idx); 7985 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7986 WREG32(reg_idx, reg_data); 7987 } 7988 } 7989 7990 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7991 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7992 sm_ctlr_regs[i]; 7993 reg_data = RREG32(reg_idx); 7994 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7995 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7996 WREG32(reg_idx, reg_data); 7997 } 7998 } 7999 8000 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8001 bool enable) 8002 { 8003 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8004 8005 if (enable) { 8006 /* enable FGCG firstly*/ 8007 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8008 /* CGCG/CGLS should be enabled after MGCG/MGLS 8009 * === MGCG + MGLS === 8010 */ 8011 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8012 /* === CGCG /CGLS for GFX 3D Only === */ 8013 gfx_v10_0_update_3d_clock_gating(adev, enable); 8014 /* === CGCG + CGLS === */ 8015 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8016 8017 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8018 IP_VERSION(10, 1, 10)) || 8019 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8020 IP_VERSION(10, 1, 1)) || 8021 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8022 IP_VERSION(10, 1, 2))) 8023 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8024 } else { 8025 /* CGCG/CGLS should be disabled before MGCG/MGLS 8026 * === CGCG + CGLS === 8027 */ 8028 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8029 /* === CGCG /CGLS for GFX 3D Only === */ 8030 gfx_v10_0_update_3d_clock_gating(adev, enable); 8031 /* === MGCG + MGLS === */ 8032 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8033 /* disable fgcg at last*/ 8034 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8035 } 8036 8037 if (adev->cg_flags & 8038 (AMD_CG_SUPPORT_GFX_MGCG | 8039 AMD_CG_SUPPORT_GFX_CGLS | 8040 AMD_CG_SUPPORT_GFX_CGCG | 8041 AMD_CG_SUPPORT_GFX_3D_CGCG | 8042 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8043 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8044 8045 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8046 8047 return 0; 8048 } 8049 8050 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8051 unsigned int vmid) 8052 { 8053 u32 data; 8054 8055 /* not for *_SOC15 */ 8056 data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL); 8057 8058 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8059 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8060 8061 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8062 } 8063 8064 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8065 { 8066 amdgpu_gfx_off_ctrl(adev, false); 8067 8068 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8069 8070 amdgpu_gfx_off_ctrl(adev, true); 8071 } 8072 8073 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8074 uint32_t offset, 8075 struct soc15_reg_rlcg *entries, int arr_size) 8076 { 8077 int i; 8078 uint32_t reg; 8079 8080 if (!entries) 8081 return false; 8082 8083 for (i = 0; i < arr_size; i++) { 8084 const struct soc15_reg_rlcg *entry; 8085 8086 entry = &entries[i]; 8087 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8088 if (offset == reg) 8089 return true; 8090 } 8091 8092 return false; 8093 } 8094 8095 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8096 { 8097 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8098 } 8099 8100 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8101 { 8102 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8103 8104 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8105 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8106 else 8107 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8108 8109 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8110 8111 /* 8112 * CGPG enablement required and the register to program the hysteresis value 8113 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8114 * in refclk count. Note that RLC FW is modified to take 16 bits from 8115 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8116 * 8117 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8118 * of CGPG enablement starting point. 8119 * Power/performance team will optimize it and might give a new value later. 8120 */ 8121 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8122 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8123 case IP_VERSION(10, 3, 1): 8124 case IP_VERSION(10, 3, 3): 8125 case IP_VERSION(10, 3, 6): 8126 case IP_VERSION(10, 3, 7): 8127 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8128 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8129 break; 8130 default: 8131 break; 8132 } 8133 } 8134 } 8135 8136 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8137 { 8138 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8139 8140 gfx_v10_cntl_power_gating(adev, enable); 8141 8142 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8143 } 8144 8145 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8146 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8147 .set_safe_mode = gfx_v10_0_set_safe_mode, 8148 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8149 .init = gfx_v10_0_rlc_init, 8150 .get_csb_size = gfx_v10_0_get_csb_size, 8151 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8152 .resume = gfx_v10_0_rlc_resume, 8153 .stop = gfx_v10_0_rlc_stop, 8154 .reset = gfx_v10_0_rlc_reset, 8155 .start = gfx_v10_0_rlc_start, 8156 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8157 }; 8158 8159 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8160 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8161 .set_safe_mode = gfx_v10_0_set_safe_mode, 8162 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8163 .init = gfx_v10_0_rlc_init, 8164 .get_csb_size = gfx_v10_0_get_csb_size, 8165 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8166 .resume = gfx_v10_0_rlc_resume, 8167 .stop = gfx_v10_0_rlc_stop, 8168 .reset = gfx_v10_0_rlc_reset, 8169 .start = gfx_v10_0_rlc_start, 8170 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8171 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8172 }; 8173 8174 static int gfx_v10_0_set_powergating_state(void *handle, 8175 enum amd_powergating_state state) 8176 { 8177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8178 bool enable = (state == AMD_PG_STATE_GATE); 8179 8180 if (amdgpu_sriov_vf(adev)) 8181 return 0; 8182 8183 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8184 case IP_VERSION(10, 1, 10): 8185 case IP_VERSION(10, 1, 1): 8186 case IP_VERSION(10, 1, 2): 8187 case IP_VERSION(10, 3, 0): 8188 case IP_VERSION(10, 3, 2): 8189 case IP_VERSION(10, 3, 4): 8190 case IP_VERSION(10, 3, 5): 8191 amdgpu_gfx_off_ctrl(adev, enable); 8192 break; 8193 case IP_VERSION(10, 3, 1): 8194 case IP_VERSION(10, 3, 3): 8195 case IP_VERSION(10, 3, 6): 8196 case IP_VERSION(10, 3, 7): 8197 if (!enable) 8198 amdgpu_gfx_off_ctrl(adev, false); 8199 8200 gfx_v10_cntl_pg(adev, enable); 8201 8202 if (enable) 8203 amdgpu_gfx_off_ctrl(adev, true); 8204 8205 break; 8206 default: 8207 break; 8208 } 8209 return 0; 8210 } 8211 8212 static int gfx_v10_0_set_clockgating_state(void *handle, 8213 enum amd_clockgating_state state) 8214 { 8215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8216 8217 if (amdgpu_sriov_vf(adev)) 8218 return 0; 8219 8220 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8221 case IP_VERSION(10, 1, 10): 8222 case IP_VERSION(10, 1, 1): 8223 case IP_VERSION(10, 1, 2): 8224 case IP_VERSION(10, 3, 0): 8225 case IP_VERSION(10, 3, 2): 8226 case IP_VERSION(10, 3, 1): 8227 case IP_VERSION(10, 3, 4): 8228 case IP_VERSION(10, 3, 5): 8229 case IP_VERSION(10, 3, 6): 8230 case IP_VERSION(10, 3, 3): 8231 case IP_VERSION(10, 3, 7): 8232 gfx_v10_0_update_gfx_clock_gating(adev, 8233 state == AMD_CG_STATE_GATE); 8234 break; 8235 default: 8236 break; 8237 } 8238 return 0; 8239 } 8240 8241 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8242 { 8243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8244 int data; 8245 8246 /* AMD_CG_SUPPORT_GFX_FGCG */ 8247 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8248 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8249 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8250 8251 /* AMD_CG_SUPPORT_GFX_MGCG */ 8252 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8253 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8254 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8255 8256 /* AMD_CG_SUPPORT_GFX_CGCG */ 8257 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8258 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8259 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8260 8261 /* AMD_CG_SUPPORT_GFX_CGLS */ 8262 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8263 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8264 8265 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8266 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8267 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8268 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8269 8270 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8271 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8272 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8273 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8274 8275 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8276 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8277 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8278 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8279 8280 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8281 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8282 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8283 } 8284 8285 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8286 { 8287 /* gfx10 is 32bit rptr*/ 8288 return *(uint32_t *)ring->rptr_cpu_addr; 8289 } 8290 8291 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8292 { 8293 struct amdgpu_device *adev = ring->adev; 8294 u64 wptr; 8295 8296 /* XXX check if swapping is necessary on BE */ 8297 if (ring->use_doorbell) { 8298 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8299 } else { 8300 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8301 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8302 } 8303 8304 return wptr; 8305 } 8306 8307 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8308 { 8309 struct amdgpu_device *adev = ring->adev; 8310 uint32_t *wptr_saved; 8311 uint32_t *is_queue_unmap; 8312 uint64_t aggregated_db_index; 8313 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8314 uint64_t wptr_tmp; 8315 8316 if (ring->is_mes_queue) { 8317 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8318 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8319 sizeof(uint32_t)); 8320 aggregated_db_index = 8321 amdgpu_mes_get_aggregated_doorbell_index(adev, 8322 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8323 8324 wptr_tmp = ring->wptr & ring->buf_mask; 8325 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8326 *wptr_saved = wptr_tmp; 8327 /* assume doorbell always being used by mes mapped queue */ 8328 if (*is_queue_unmap) { 8329 WDOORBELL64(aggregated_db_index, wptr_tmp); 8330 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8331 } else { 8332 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8333 8334 if (*is_queue_unmap) 8335 WDOORBELL64(aggregated_db_index, wptr_tmp); 8336 } 8337 } else { 8338 if (ring->use_doorbell) { 8339 /* XXX check if swapping is necessary on BE */ 8340 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8341 ring->wptr); 8342 WDOORBELL64(ring->doorbell_index, ring->wptr); 8343 } else { 8344 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8345 lower_32_bits(ring->wptr)); 8346 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8347 upper_32_bits(ring->wptr)); 8348 } 8349 } 8350 } 8351 8352 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8353 { 8354 /* gfx10 hardware is 32bit rptr */ 8355 return *(uint32_t *)ring->rptr_cpu_addr; 8356 } 8357 8358 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8359 { 8360 u64 wptr; 8361 8362 /* XXX check if swapping is necessary on BE */ 8363 if (ring->use_doorbell) 8364 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8365 else 8366 BUG(); 8367 return wptr; 8368 } 8369 8370 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8371 { 8372 struct amdgpu_device *adev = ring->adev; 8373 uint32_t *wptr_saved; 8374 uint32_t *is_queue_unmap; 8375 uint64_t aggregated_db_index; 8376 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8377 uint64_t wptr_tmp; 8378 8379 if (ring->is_mes_queue) { 8380 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8381 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8382 sizeof(uint32_t)); 8383 aggregated_db_index = 8384 amdgpu_mes_get_aggregated_doorbell_index(adev, 8385 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8386 8387 wptr_tmp = ring->wptr & ring->buf_mask; 8388 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8389 *wptr_saved = wptr_tmp; 8390 /* assume doorbell always used by mes mapped queue */ 8391 if (*is_queue_unmap) { 8392 WDOORBELL64(aggregated_db_index, wptr_tmp); 8393 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8394 } else { 8395 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8396 8397 if (*is_queue_unmap) 8398 WDOORBELL64(aggregated_db_index, wptr_tmp); 8399 } 8400 } else { 8401 /* XXX check if swapping is necessary on BE */ 8402 if (ring->use_doorbell) { 8403 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8404 ring->wptr); 8405 WDOORBELL64(ring->doorbell_index, ring->wptr); 8406 } else { 8407 BUG(); /* only DOORBELL method supported on gfx10 now */ 8408 } 8409 } 8410 } 8411 8412 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8413 { 8414 struct amdgpu_device *adev = ring->adev; 8415 u32 ref_and_mask, reg_mem_engine; 8416 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8417 8418 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8419 switch (ring->me) { 8420 case 1: 8421 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8422 break; 8423 case 2: 8424 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8425 break; 8426 default: 8427 return; 8428 } 8429 reg_mem_engine = 0; 8430 } else { 8431 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8432 reg_mem_engine = 1; /* pfp */ 8433 } 8434 8435 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8436 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8437 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8438 ref_and_mask, ref_and_mask, 0x20); 8439 } 8440 8441 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8442 struct amdgpu_job *job, 8443 struct amdgpu_ib *ib, 8444 uint32_t flags) 8445 { 8446 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8447 u32 header, control = 0; 8448 8449 if (ib->flags & AMDGPU_IB_FLAG_CE) 8450 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8451 else 8452 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8453 8454 control |= ib->length_dw | (vmid << 24); 8455 8456 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8457 control |= INDIRECT_BUFFER_PRE_ENB(1); 8458 8459 if (flags & AMDGPU_IB_PREEMPTED) 8460 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8461 8462 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8463 gfx_v10_0_ring_emit_de_meta(ring, 8464 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8465 } 8466 8467 if (ring->is_mes_queue) 8468 /* inherit vmid from mqd */ 8469 control |= 0x400000; 8470 8471 amdgpu_ring_write(ring, header); 8472 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8473 amdgpu_ring_write(ring, 8474 #ifdef __BIG_ENDIAN 8475 (2 << 0) | 8476 #endif 8477 lower_32_bits(ib->gpu_addr)); 8478 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8479 amdgpu_ring_write(ring, control); 8480 } 8481 8482 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8483 struct amdgpu_job *job, 8484 struct amdgpu_ib *ib, 8485 uint32_t flags) 8486 { 8487 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8488 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8489 8490 if (ring->is_mes_queue) 8491 /* inherit vmid from mqd */ 8492 control |= 0x40000000; 8493 8494 /* Currently, there is a high possibility to get wave ID mismatch 8495 * between ME and GDS, leading to a hw deadlock, because ME generates 8496 * different wave IDs than the GDS expects. This situation happens 8497 * randomly when at least 5 compute pipes use GDS ordered append. 8498 * The wave IDs generated by ME are also wrong after suspend/resume. 8499 * Those are probably bugs somewhere else in the kernel driver. 8500 * 8501 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8502 * GDS to 0 for this ring (me/pipe). 8503 */ 8504 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8505 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8506 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8507 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8508 } 8509 8510 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8511 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8512 amdgpu_ring_write(ring, 8513 #ifdef __BIG_ENDIAN 8514 (2 << 0) | 8515 #endif 8516 lower_32_bits(ib->gpu_addr)); 8517 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8518 amdgpu_ring_write(ring, control); 8519 } 8520 8521 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8522 u64 seq, unsigned int flags) 8523 { 8524 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8525 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8526 8527 /* RELEASE_MEM - flush caches, send int */ 8528 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8529 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8530 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8531 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8532 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8533 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8534 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8535 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8536 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8537 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8538 8539 /* 8540 * the address should be Qword aligned if 64bit write, Dword 8541 * aligned if only send 32bit data low (discard data high) 8542 */ 8543 if (write64bit) 8544 BUG_ON(addr & 0x7); 8545 else 8546 BUG_ON(addr & 0x3); 8547 amdgpu_ring_write(ring, lower_32_bits(addr)); 8548 amdgpu_ring_write(ring, upper_32_bits(addr)); 8549 amdgpu_ring_write(ring, lower_32_bits(seq)); 8550 amdgpu_ring_write(ring, upper_32_bits(seq)); 8551 amdgpu_ring_write(ring, ring->is_mes_queue ? 8552 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8553 } 8554 8555 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8556 { 8557 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8558 uint32_t seq = ring->fence_drv.sync_seq; 8559 uint64_t addr = ring->fence_drv.gpu_addr; 8560 8561 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8562 upper_32_bits(addr), seq, 0xffffffff, 4); 8563 } 8564 8565 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8566 uint16_t pasid, uint32_t flush_type, 8567 bool all_hub, uint8_t dst_sel) 8568 { 8569 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8570 amdgpu_ring_write(ring, 8571 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8572 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8573 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8574 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8575 } 8576 8577 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8578 unsigned int vmid, uint64_t pd_addr) 8579 { 8580 if (ring->is_mes_queue) 8581 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8582 else 8583 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8584 8585 /* compute doesn't have PFP */ 8586 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8587 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8588 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8589 amdgpu_ring_write(ring, 0x0); 8590 } 8591 } 8592 8593 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8594 u64 seq, unsigned int flags) 8595 { 8596 struct amdgpu_device *adev = ring->adev; 8597 8598 /* we only allocate 32bit for each seq wb address */ 8599 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8600 8601 /* write fence seq to the "addr" */ 8602 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8603 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8604 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8605 amdgpu_ring_write(ring, lower_32_bits(addr)); 8606 amdgpu_ring_write(ring, upper_32_bits(addr)); 8607 amdgpu_ring_write(ring, lower_32_bits(seq)); 8608 8609 if (flags & AMDGPU_FENCE_FLAG_INT) { 8610 /* set register to trigger INT */ 8611 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8612 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8613 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8614 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8615 amdgpu_ring_write(ring, 0); 8616 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8617 } 8618 } 8619 8620 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8621 { 8622 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8623 amdgpu_ring_write(ring, 0); 8624 } 8625 8626 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8627 uint32_t flags) 8628 { 8629 uint32_t dw2 = 0; 8630 8631 if (ring->adev->gfx.mcbp) 8632 gfx_v10_0_ring_emit_ce_meta(ring, 8633 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8634 8635 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8636 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8637 /* set load_global_config & load_global_uconfig */ 8638 dw2 |= 0x8001; 8639 /* set load_cs_sh_regs */ 8640 dw2 |= 0x01000000; 8641 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8642 dw2 |= 0x10002; 8643 8644 /* set load_ce_ram if preamble presented */ 8645 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8646 dw2 |= 0x10000000; 8647 } else { 8648 /* still load_ce_ram if this is the first time preamble presented 8649 * although there is no context switch happens. 8650 */ 8651 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8652 dw2 |= 0x10000000; 8653 } 8654 8655 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8656 amdgpu_ring_write(ring, dw2); 8657 amdgpu_ring_write(ring, 0); 8658 } 8659 8660 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8661 uint64_t addr) 8662 { 8663 unsigned int ret; 8664 8665 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8666 amdgpu_ring_write(ring, lower_32_bits(addr)); 8667 amdgpu_ring_write(ring, upper_32_bits(addr)); 8668 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8669 amdgpu_ring_write(ring, 0); 8670 ret = ring->wptr & ring->buf_mask; 8671 /* patch dummy value later */ 8672 amdgpu_ring_write(ring, 0); 8673 8674 return ret; 8675 } 8676 8677 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8678 { 8679 int i, r = 0; 8680 struct amdgpu_device *adev = ring->adev; 8681 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8682 struct amdgpu_ring *kiq_ring = &kiq->ring; 8683 unsigned long flags; 8684 8685 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8686 return -EINVAL; 8687 8688 spin_lock_irqsave(&kiq->ring_lock, flags); 8689 8690 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8691 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8692 return -ENOMEM; 8693 } 8694 8695 /* assert preemption condition */ 8696 amdgpu_ring_set_preempt_cond_exec(ring, false); 8697 8698 /* assert IB preemption, emit the trailing fence */ 8699 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8700 ring->trail_fence_gpu_addr, 8701 ++ring->trail_seq); 8702 amdgpu_ring_commit(kiq_ring); 8703 8704 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8705 8706 /* poll the trailing fence */ 8707 for (i = 0; i < adev->usec_timeout; i++) { 8708 if (ring->trail_seq == 8709 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8710 break; 8711 udelay(1); 8712 } 8713 8714 if (i >= adev->usec_timeout) { 8715 r = -EINVAL; 8716 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8717 } 8718 8719 /* deassert preemption condition */ 8720 amdgpu_ring_set_preempt_cond_exec(ring, true); 8721 return r; 8722 } 8723 8724 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8725 { 8726 struct amdgpu_device *adev = ring->adev; 8727 struct v10_ce_ib_state ce_payload = {0}; 8728 uint64_t offset, ce_payload_gpu_addr; 8729 void *ce_payload_cpu_addr; 8730 int cnt; 8731 8732 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8733 8734 if (ring->is_mes_queue) { 8735 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8736 gfx[0].gfx_meta_data) + 8737 offsetof(struct v10_gfx_meta_data, ce_payload); 8738 ce_payload_gpu_addr = 8739 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8740 ce_payload_cpu_addr = 8741 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8742 } else { 8743 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8744 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8745 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8746 } 8747 8748 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8749 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8750 WRITE_DATA_DST_SEL(8) | 8751 WR_CONFIRM) | 8752 WRITE_DATA_CACHE_POLICY(0)); 8753 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8754 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8755 8756 if (resume) 8757 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8758 sizeof(ce_payload) >> 2); 8759 else 8760 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8761 sizeof(ce_payload) >> 2); 8762 } 8763 8764 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8765 { 8766 struct amdgpu_device *adev = ring->adev; 8767 struct v10_de_ib_state de_payload = {0}; 8768 uint64_t offset, gds_addr, de_payload_gpu_addr; 8769 void *de_payload_cpu_addr; 8770 int cnt; 8771 8772 if (ring->is_mes_queue) { 8773 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8774 gfx[0].gfx_meta_data) + 8775 offsetof(struct v10_gfx_meta_data, de_payload); 8776 de_payload_gpu_addr = 8777 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8778 de_payload_cpu_addr = 8779 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8780 8781 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8782 gfx[0].gds_backup) + 8783 offsetof(struct v10_gfx_meta_data, de_payload); 8784 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8785 } else { 8786 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8787 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8788 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8789 8790 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8791 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8792 PAGE_SIZE); 8793 } 8794 8795 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8796 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8797 8798 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8799 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8800 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8801 WRITE_DATA_DST_SEL(8) | 8802 WR_CONFIRM) | 8803 WRITE_DATA_CACHE_POLICY(0)); 8804 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8805 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8806 8807 if (resume) 8808 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8809 sizeof(de_payload) >> 2); 8810 else 8811 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8812 sizeof(de_payload) >> 2); 8813 } 8814 8815 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8816 bool secure) 8817 { 8818 uint32_t v = secure ? FRAME_TMZ : 0; 8819 8820 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8821 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8822 } 8823 8824 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8825 uint32_t reg_val_offs) 8826 { 8827 struct amdgpu_device *adev = ring->adev; 8828 8829 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8830 amdgpu_ring_write(ring, 0 | /* src: register*/ 8831 (5 << 8) | /* dst: memory */ 8832 (1 << 20)); /* write confirm */ 8833 amdgpu_ring_write(ring, reg); 8834 amdgpu_ring_write(ring, 0); 8835 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8836 reg_val_offs * 4)); 8837 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8838 reg_val_offs * 4)); 8839 } 8840 8841 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8842 uint32_t val) 8843 { 8844 uint32_t cmd = 0; 8845 8846 switch (ring->funcs->type) { 8847 case AMDGPU_RING_TYPE_GFX: 8848 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8849 break; 8850 case AMDGPU_RING_TYPE_KIQ: 8851 cmd = (1 << 16); /* no inc addr */ 8852 break; 8853 default: 8854 cmd = WR_CONFIRM; 8855 break; 8856 } 8857 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8858 amdgpu_ring_write(ring, cmd); 8859 amdgpu_ring_write(ring, reg); 8860 amdgpu_ring_write(ring, 0); 8861 amdgpu_ring_write(ring, val); 8862 } 8863 8864 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8865 uint32_t val, uint32_t mask) 8866 { 8867 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8868 } 8869 8870 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8871 uint32_t reg0, uint32_t reg1, 8872 uint32_t ref, uint32_t mask) 8873 { 8874 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8875 struct amdgpu_device *adev = ring->adev; 8876 bool fw_version_ok = false; 8877 8878 fw_version_ok = adev->gfx.cp_fw_write_wait; 8879 8880 if (fw_version_ok) 8881 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8882 ref, mask, 0x20); 8883 else 8884 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8885 ref, mask); 8886 } 8887 8888 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8889 unsigned int vmid) 8890 { 8891 struct amdgpu_device *adev = ring->adev; 8892 uint32_t value = 0; 8893 8894 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8895 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8896 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8897 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8898 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8899 } 8900 8901 static void 8902 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8903 uint32_t me, uint32_t pipe, 8904 enum amdgpu_interrupt_state state) 8905 { 8906 uint32_t cp_int_cntl, cp_int_cntl_reg; 8907 8908 if (!me) { 8909 switch (pipe) { 8910 case 0: 8911 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8912 break; 8913 case 1: 8914 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8915 break; 8916 default: 8917 DRM_DEBUG("invalid pipe %d\n", pipe); 8918 return; 8919 } 8920 } else { 8921 DRM_DEBUG("invalid me %d\n", me); 8922 return; 8923 } 8924 8925 switch (state) { 8926 case AMDGPU_IRQ_STATE_DISABLE: 8927 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8928 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8929 TIME_STAMP_INT_ENABLE, 0); 8930 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8931 break; 8932 case AMDGPU_IRQ_STATE_ENABLE: 8933 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8934 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8935 TIME_STAMP_INT_ENABLE, 1); 8936 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8937 break; 8938 default: 8939 break; 8940 } 8941 } 8942 8943 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8944 int me, int pipe, 8945 enum amdgpu_interrupt_state state) 8946 { 8947 u32 mec_int_cntl, mec_int_cntl_reg; 8948 8949 /* 8950 * amdgpu controls only the first MEC. That's why this function only 8951 * handles the setting of interrupts for this specific MEC. All other 8952 * pipes' interrupts are set by amdkfd. 8953 */ 8954 8955 if (me == 1) { 8956 switch (pipe) { 8957 case 0: 8958 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8959 break; 8960 case 1: 8961 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8962 break; 8963 case 2: 8964 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8965 break; 8966 case 3: 8967 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8968 break; 8969 default: 8970 DRM_DEBUG("invalid pipe %d\n", pipe); 8971 return; 8972 } 8973 } else { 8974 DRM_DEBUG("invalid me %d\n", me); 8975 return; 8976 } 8977 8978 switch (state) { 8979 case AMDGPU_IRQ_STATE_DISABLE: 8980 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8981 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8982 TIME_STAMP_INT_ENABLE, 0); 8983 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8984 break; 8985 case AMDGPU_IRQ_STATE_ENABLE: 8986 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8987 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8988 TIME_STAMP_INT_ENABLE, 1); 8989 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8990 break; 8991 default: 8992 break; 8993 } 8994 } 8995 8996 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8997 struct amdgpu_irq_src *src, 8998 unsigned int type, 8999 enum amdgpu_interrupt_state state) 9000 { 9001 switch (type) { 9002 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9003 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9004 break; 9005 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9006 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9007 break; 9008 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9009 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9010 break; 9011 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9012 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9013 break; 9014 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9015 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9016 break; 9017 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9018 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9019 break; 9020 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9021 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9022 break; 9023 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9024 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9025 break; 9026 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9027 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9028 break; 9029 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9030 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9031 break; 9032 default: 9033 break; 9034 } 9035 return 0; 9036 } 9037 9038 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9039 struct amdgpu_irq_src *source, 9040 struct amdgpu_iv_entry *entry) 9041 { 9042 int i; 9043 u8 me_id, pipe_id, queue_id; 9044 struct amdgpu_ring *ring; 9045 uint32_t mes_queue_id = entry->src_data[0]; 9046 9047 DRM_DEBUG("IH: CP EOP\n"); 9048 9049 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 9050 struct amdgpu_mes_queue *queue; 9051 9052 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 9053 9054 spin_lock(&adev->mes.queue_id_lock); 9055 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 9056 if (queue) { 9057 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 9058 amdgpu_fence_process(queue->ring); 9059 } 9060 spin_unlock(&adev->mes.queue_id_lock); 9061 } else { 9062 me_id = (entry->ring_id & 0x0c) >> 2; 9063 pipe_id = (entry->ring_id & 0x03) >> 0; 9064 queue_id = (entry->ring_id & 0x70) >> 4; 9065 9066 switch (me_id) { 9067 case 0: 9068 if (pipe_id == 0) 9069 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9070 else 9071 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9072 break; 9073 case 1: 9074 case 2: 9075 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9076 ring = &adev->gfx.compute_ring[i]; 9077 /* Per-queue interrupt is supported for MEC starting from VI. 9078 * The interrupt can only be enabled/disabled per pipe instead 9079 * of per queue. 9080 */ 9081 if ((ring->me == me_id) && 9082 (ring->pipe == pipe_id) && 9083 (ring->queue == queue_id)) 9084 amdgpu_fence_process(ring); 9085 } 9086 break; 9087 } 9088 } 9089 9090 return 0; 9091 } 9092 9093 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9094 struct amdgpu_irq_src *source, 9095 unsigned int type, 9096 enum amdgpu_interrupt_state state) 9097 { 9098 switch (state) { 9099 case AMDGPU_IRQ_STATE_DISABLE: 9100 case AMDGPU_IRQ_STATE_ENABLE: 9101 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9102 PRIV_REG_INT_ENABLE, 9103 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9104 break; 9105 default: 9106 break; 9107 } 9108 9109 return 0; 9110 } 9111 9112 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9113 struct amdgpu_irq_src *source, 9114 unsigned int type, 9115 enum amdgpu_interrupt_state state) 9116 { 9117 switch (state) { 9118 case AMDGPU_IRQ_STATE_DISABLE: 9119 case AMDGPU_IRQ_STATE_ENABLE: 9120 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9121 PRIV_INSTR_INT_ENABLE, 9122 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9123 break; 9124 default: 9125 break; 9126 } 9127 9128 return 0; 9129 } 9130 9131 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9132 struct amdgpu_iv_entry *entry) 9133 { 9134 u8 me_id, pipe_id, queue_id; 9135 struct amdgpu_ring *ring; 9136 int i; 9137 9138 me_id = (entry->ring_id & 0x0c) >> 2; 9139 pipe_id = (entry->ring_id & 0x03) >> 0; 9140 queue_id = (entry->ring_id & 0x70) >> 4; 9141 9142 switch (me_id) { 9143 case 0: 9144 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9145 ring = &adev->gfx.gfx_ring[i]; 9146 /* we only enabled 1 gfx queue per pipe for now */ 9147 if (ring->me == me_id && ring->pipe == pipe_id) 9148 drm_sched_fault(&ring->sched); 9149 } 9150 break; 9151 case 1: 9152 case 2: 9153 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9154 ring = &adev->gfx.compute_ring[i]; 9155 if (ring->me == me_id && ring->pipe == pipe_id && 9156 ring->queue == queue_id) 9157 drm_sched_fault(&ring->sched); 9158 } 9159 break; 9160 default: 9161 BUG(); 9162 } 9163 } 9164 9165 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9166 struct amdgpu_irq_src *source, 9167 struct amdgpu_iv_entry *entry) 9168 { 9169 DRM_ERROR("Illegal register access in command stream\n"); 9170 gfx_v10_0_handle_priv_fault(adev, entry); 9171 return 0; 9172 } 9173 9174 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9175 struct amdgpu_irq_src *source, 9176 struct amdgpu_iv_entry *entry) 9177 { 9178 DRM_ERROR("Illegal instruction in command stream\n"); 9179 gfx_v10_0_handle_priv_fault(adev, entry); 9180 return 0; 9181 } 9182 9183 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9184 struct amdgpu_irq_src *src, 9185 unsigned int type, 9186 enum amdgpu_interrupt_state state) 9187 { 9188 uint32_t tmp, target; 9189 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9190 9191 if (ring->me == 1) 9192 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9193 else 9194 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9195 target += ring->pipe; 9196 9197 switch (type) { 9198 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9199 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9200 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9201 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9202 GENERIC2_INT_ENABLE, 0); 9203 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9204 9205 tmp = RREG32_SOC15_IP(GC, target); 9206 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9207 GENERIC2_INT_ENABLE, 0); 9208 WREG32_SOC15_IP(GC, target, tmp); 9209 } else { 9210 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9211 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9212 GENERIC2_INT_ENABLE, 1); 9213 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9214 9215 tmp = RREG32_SOC15_IP(GC, target); 9216 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9217 GENERIC2_INT_ENABLE, 1); 9218 WREG32_SOC15_IP(GC, target, tmp); 9219 } 9220 break; 9221 default: 9222 BUG(); /* kiq only support GENERIC2_INT now */ 9223 break; 9224 } 9225 return 0; 9226 } 9227 9228 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9229 struct amdgpu_irq_src *source, 9230 struct amdgpu_iv_entry *entry) 9231 { 9232 u8 me_id, pipe_id, queue_id; 9233 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9234 9235 me_id = (entry->ring_id & 0x0c) >> 2; 9236 pipe_id = (entry->ring_id & 0x03) >> 0; 9237 queue_id = (entry->ring_id & 0x70) >> 4; 9238 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9239 me_id, pipe_id, queue_id); 9240 9241 amdgpu_fence_process(ring); 9242 return 0; 9243 } 9244 9245 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9246 { 9247 const unsigned int gcr_cntl = 9248 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9249 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9250 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9251 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9252 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9253 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9254 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9255 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9256 9257 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9258 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9259 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9260 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9261 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9262 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9263 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9264 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9265 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9266 } 9267 9268 static void gfx_v10_ip_print(void *handle, struct drm_printer *p) 9269 { 9270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9271 uint32_t i; 9272 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9273 9274 if (!adev->gfx.ip_dump) 9275 return; 9276 9277 for (i = 0; i < reg_count; i++) 9278 drm_printf(p, "%-50s \t 0x%08x\n", 9279 gc_reg_list_10_1[i].reg_name, 9280 adev->gfx.ip_dump[i]); 9281 } 9282 9283 static void gfx_v10_ip_dump(void *handle) 9284 { 9285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 9286 uint32_t i; 9287 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9288 9289 if (!adev->gfx.ip_dump) 9290 return; 9291 9292 amdgpu_gfx_off_ctrl(adev, false); 9293 for (i = 0; i < reg_count; i++) 9294 adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9295 amdgpu_gfx_off_ctrl(adev, true); 9296 } 9297 9298 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9299 .name = "gfx_v10_0", 9300 .early_init = gfx_v10_0_early_init, 9301 .late_init = gfx_v10_0_late_init, 9302 .sw_init = gfx_v10_0_sw_init, 9303 .sw_fini = gfx_v10_0_sw_fini, 9304 .hw_init = gfx_v10_0_hw_init, 9305 .hw_fini = gfx_v10_0_hw_fini, 9306 .suspend = gfx_v10_0_suspend, 9307 .resume = gfx_v10_0_resume, 9308 .is_idle = gfx_v10_0_is_idle, 9309 .wait_for_idle = gfx_v10_0_wait_for_idle, 9310 .soft_reset = gfx_v10_0_soft_reset, 9311 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9312 .set_powergating_state = gfx_v10_0_set_powergating_state, 9313 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9314 .dump_ip_state = gfx_v10_ip_dump, 9315 .print_ip_state = gfx_v10_ip_print, 9316 }; 9317 9318 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9319 .type = AMDGPU_RING_TYPE_GFX, 9320 .align_mask = 0xff, 9321 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9322 .support_64bit_ptrs = true, 9323 .secure_submission_supported = true, 9324 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9325 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9326 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9327 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9328 5 + /* COND_EXEC */ 9329 7 + /* PIPELINE_SYNC */ 9330 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9331 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9332 4 + /* VM_FLUSH */ 9333 8 + /* FENCE for VM_FLUSH */ 9334 20 + /* GDS switch */ 9335 4 + /* double SWITCH_BUFFER, 9336 * the first COND_EXEC jump to the place 9337 * just prior to this double SWITCH_BUFFER 9338 */ 9339 5 + /* COND_EXEC */ 9340 7 + /* HDP_flush */ 9341 4 + /* VGT_flush */ 9342 14 + /* CE_META */ 9343 31 + /* DE_META */ 9344 3 + /* CNTX_CTRL */ 9345 5 + /* HDP_INVL */ 9346 8 + 8 + /* FENCE x2 */ 9347 2 + /* SWITCH_BUFFER */ 9348 8, /* gfx_v10_0_emit_mem_sync */ 9349 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9350 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9351 .emit_fence = gfx_v10_0_ring_emit_fence, 9352 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9353 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9354 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9355 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9356 .test_ring = gfx_v10_0_ring_test_ring, 9357 .test_ib = gfx_v10_0_ring_test_ib, 9358 .insert_nop = amdgpu_ring_insert_nop, 9359 .pad_ib = amdgpu_ring_generic_pad_ib, 9360 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9361 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9362 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9363 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9364 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9365 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9366 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9367 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9368 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9369 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9370 }; 9371 9372 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9373 .type = AMDGPU_RING_TYPE_COMPUTE, 9374 .align_mask = 0xff, 9375 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9376 .support_64bit_ptrs = true, 9377 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9378 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9379 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9380 .emit_frame_size = 9381 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9382 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9383 5 + /* hdp invalidate */ 9384 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9385 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9386 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9387 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9388 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9389 8, /* gfx_v10_0_emit_mem_sync */ 9390 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9391 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9392 .emit_fence = gfx_v10_0_ring_emit_fence, 9393 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9394 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9395 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9396 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9397 .test_ring = gfx_v10_0_ring_test_ring, 9398 .test_ib = gfx_v10_0_ring_test_ib, 9399 .insert_nop = amdgpu_ring_insert_nop, 9400 .pad_ib = amdgpu_ring_generic_pad_ib, 9401 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9402 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9403 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9404 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9405 }; 9406 9407 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9408 .type = AMDGPU_RING_TYPE_KIQ, 9409 .align_mask = 0xff, 9410 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9411 .support_64bit_ptrs = true, 9412 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9413 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9414 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9415 .emit_frame_size = 9416 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9417 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9418 5 + /*hdp invalidate */ 9419 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9420 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9421 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9422 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9423 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9424 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9425 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9426 .test_ring = gfx_v10_0_ring_test_ring, 9427 .test_ib = gfx_v10_0_ring_test_ib, 9428 .insert_nop = amdgpu_ring_insert_nop, 9429 .pad_ib = amdgpu_ring_generic_pad_ib, 9430 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9431 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9432 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9433 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9434 }; 9435 9436 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9437 { 9438 int i; 9439 9440 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9441 9442 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9443 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9444 9445 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9446 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9447 } 9448 9449 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9450 .set = gfx_v10_0_set_eop_interrupt_state, 9451 .process = gfx_v10_0_eop_irq, 9452 }; 9453 9454 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9455 .set = gfx_v10_0_set_priv_reg_fault_state, 9456 .process = gfx_v10_0_priv_reg_irq, 9457 }; 9458 9459 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9460 .set = gfx_v10_0_set_priv_inst_fault_state, 9461 .process = gfx_v10_0_priv_inst_irq, 9462 }; 9463 9464 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9465 .set = gfx_v10_0_kiq_set_interrupt_state, 9466 .process = gfx_v10_0_kiq_irq, 9467 }; 9468 9469 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9470 { 9471 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9472 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9473 9474 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9475 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9476 9477 adev->gfx.priv_reg_irq.num_types = 1; 9478 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9479 9480 adev->gfx.priv_inst_irq.num_types = 1; 9481 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9482 } 9483 9484 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9485 { 9486 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9487 case IP_VERSION(10, 1, 10): 9488 case IP_VERSION(10, 1, 1): 9489 case IP_VERSION(10, 1, 3): 9490 case IP_VERSION(10, 1, 4): 9491 case IP_VERSION(10, 3, 2): 9492 case IP_VERSION(10, 3, 1): 9493 case IP_VERSION(10, 3, 4): 9494 case IP_VERSION(10, 3, 5): 9495 case IP_VERSION(10, 3, 6): 9496 case IP_VERSION(10, 3, 3): 9497 case IP_VERSION(10, 3, 7): 9498 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9499 break; 9500 case IP_VERSION(10, 1, 2): 9501 case IP_VERSION(10, 3, 0): 9502 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9503 break; 9504 default: 9505 break; 9506 } 9507 } 9508 9509 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9510 { 9511 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9512 adev->gfx.config.max_sh_per_se * 9513 adev->gfx.config.max_shader_engines; 9514 9515 adev->gds.gds_size = 0x10000; 9516 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9517 adev->gds.gws_size = 64; 9518 adev->gds.oa_size = 16; 9519 } 9520 9521 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9522 { 9523 /* set gfx eng mqd */ 9524 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9525 sizeof(struct v10_gfx_mqd); 9526 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9527 gfx_v10_0_gfx_mqd_init; 9528 /* set compute eng mqd */ 9529 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9530 sizeof(struct v10_compute_mqd); 9531 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9532 gfx_v10_0_compute_mqd_init; 9533 } 9534 9535 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9536 u32 bitmap) 9537 { 9538 u32 data; 9539 9540 if (!bitmap) 9541 return; 9542 9543 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9544 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9545 9546 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9547 } 9548 9549 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9550 { 9551 u32 disabled_mask = 9552 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9553 u32 efuse_setting = 0; 9554 u32 vbios_setting = 0; 9555 9556 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9557 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9558 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9559 9560 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9561 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9562 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9563 9564 disabled_mask |= efuse_setting | vbios_setting; 9565 9566 return (~disabled_mask); 9567 } 9568 9569 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9570 { 9571 u32 wgp_idx, wgp_active_bitmap; 9572 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9573 9574 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9575 cu_active_bitmap = 0; 9576 9577 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9578 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9579 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9580 if (wgp_active_bitmap & (1 << wgp_idx)) 9581 cu_active_bitmap |= cu_bitmap_per_wgp; 9582 } 9583 9584 return cu_active_bitmap; 9585 } 9586 9587 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9588 struct amdgpu_cu_info *cu_info) 9589 { 9590 int i, j, k, counter, active_cu_number = 0; 9591 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9592 unsigned int disable_masks[4 * 2]; 9593 9594 if (!adev || !cu_info) 9595 return -EINVAL; 9596 9597 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9598 9599 mutex_lock(&adev->grbm_idx_mutex); 9600 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9601 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9602 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9603 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 9604 IP_VERSION(10, 3, 0)) || 9605 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9606 IP_VERSION(10, 3, 3)) || 9607 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9608 IP_VERSION(10, 3, 6)) || 9609 (amdgpu_ip_version(adev, GC_HWIP, 0) == 9610 IP_VERSION(10, 3, 7))) && 9611 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9612 continue; 9613 mask = 1; 9614 ao_bitmap = 0; 9615 counter = 0; 9616 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9617 if (i < 4 && j < 2) 9618 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9619 adev, disable_masks[i * 2 + j]); 9620 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9621 cu_info->bitmap[0][i][j] = bitmap; 9622 9623 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9624 if (bitmap & mask) { 9625 if (counter < adev->gfx.config.max_cu_per_sh) 9626 ao_bitmap |= mask; 9627 counter++; 9628 } 9629 mask <<= 1; 9630 } 9631 active_cu_number += counter; 9632 if (i < 2 && j < 2) 9633 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9634 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9635 } 9636 } 9637 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9638 mutex_unlock(&adev->grbm_idx_mutex); 9639 9640 cu_info->number = active_cu_number; 9641 cu_info->ao_cu_mask = ao_cu_mask; 9642 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9643 9644 return 0; 9645 } 9646 9647 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9648 { 9649 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9650 9651 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9652 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9653 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9654 9655 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9656 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9657 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9658 9659 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9660 adev->gfx.config.max_shader_engines); 9661 disabled_sa = efuse_setting | vbios_setting; 9662 disabled_sa &= max_sa_mask; 9663 9664 return disabled_sa; 9665 } 9666 9667 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9668 { 9669 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9670 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9671 9672 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9673 9674 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9675 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9676 max_shader_engines = adev->gfx.config.max_shader_engines; 9677 9678 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9679 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9680 disabled_sa_per_se &= max_sa_per_se_mask; 9681 if (disabled_sa_per_se == max_sa_per_se_mask) { 9682 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9683 break; 9684 } 9685 } 9686 } 9687 9688 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9689 { 9690 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9691 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9692 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9693 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9694 9695 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9696 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9697 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9698 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9699 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9700 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9701 9702 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9703 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9704 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9705 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9706 9707 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9708 9709 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9710 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9711 } 9712 9713 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9714 .type = AMD_IP_BLOCK_TYPE_GFX, 9715 .major = 10, 9716 .minor = 0, 9717 .rev = 0, 9718 .funcs = &gfx_v10_0_ip_funcs, 9719 }; 9720