1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define RLCG_VFGATE_DISABLED 0x4000000 60 #define RLCG_WRONG_OPERATION_TYPE 0x2000000 61 #define RLCG_NOT_IN_RANGE 0x1000000 62 63 #define F32_CE_PROGRAM_RAM_SIZE 65536 64 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 65 66 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 67 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 69 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 70 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 71 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 72 73 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 74 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 75 76 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 77 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 78 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 79 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 80 81 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 82 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 83 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 84 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 85 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 86 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 87 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 88 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 90 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 92 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 94 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 96 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 97 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 98 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 99 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 100 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 101 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 102 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 103 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 104 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 105 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 106 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 107 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 108 109 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 111 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 113 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 114 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 115 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 116 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 117 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 118 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 119 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 120 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 121 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 122 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 124 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 125 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 126 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 127 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 128 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 129 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 130 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 131 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 132 133 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 134 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 135 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 136 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 137 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 138 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_DATA 0x5819 140 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 141 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 142 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_DATA 0x5817 144 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 145 146 #define mmCPG_PSP_DEBUG 0x5c10 147 #define mmCPG_PSP_DEBUG_BASE_IDX 1 148 #define mmCPC_PSP_DEBUG 0x5c11 149 #define mmCPC_PSP_DEBUG_BASE_IDX 1 150 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 151 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 152 153 //CC_GC_SA_UNIT_DISABLE 154 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 155 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 156 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 157 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 158 //GC_USER_SA_UNIT_DISABLE 159 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 160 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 161 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 162 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 163 //PA_SC_ENHANCE_3 164 #define mmPA_SC_ENHANCE_3 0x1085 165 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 166 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 167 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 168 169 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 170 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 171 172 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 173 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 174 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 175 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 177 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 178 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 179 180 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 181 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 182 183 #define GFX_RLCG_GC_WRITE_OLD (0x8 << 28) 184 #define GFX_RLCG_GC_WRITE (0x0 << 28) 185 #define GFX_RLCG_GC_READ (0x1 << 28) 186 #define GFX_RLCG_MMHUB_WRITE (0x2 << 28) 187 188 #define RLCG_ERROR_REPORT_ENABLED(adev) \ 189 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 190 191 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 196 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 197 198 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 216 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 222 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 223 224 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 229 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 230 231 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 236 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 237 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 243 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 244 245 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 250 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 251 252 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 257 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 258 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish_ce.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish_pfp.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish_me.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec2.bin"); 264 MODULE_FIRMWARE("amdgpu/cyan_skillfish_rlc.bin"); 265 266 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 267 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 268 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 269 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 270 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 271 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 272 273 static const struct soc15_reg_golden golden_settings_gc_10_0[] = 274 { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 276 /* TA_GRAD_ADJ_UCONFIG -> TA_GRAD_ADJ */ 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382), 278 /* VGT_TF_RING_SIZE_UMD -> VGT_TF_RING_SIZE */ 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2262c24e), 280 /* VGT_HS_OFFCHIP_PARAM_UMD -> VGT_HS_OFFCHIP_PARAM */ 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226cc24f), 282 /* VGT_TF_MEMORY_BASE_UMD -> VGT_TF_MEMORY_BASE */ 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226ec250), 284 /* VGT_TF_MEMORY_BASE_HI_UMD -> VGT_TF_MEMORY_BASE_HI */ 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2278c261), 286 /* VGT_ESGS_RING_SIZE_UMD -> VGT_ESGS_RING_SIZE */ 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2232c240), 288 /* VGT_GSVS_RING_SIZE_UMD -> VGT_GSVS_RING_SIZE */ 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2233c241), 290 }; 291 292 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 293 { 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 334 }; 335 336 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 337 { 338 /* Pending on emulation bring up */ 339 }; 340 341 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 342 { 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1395 }; 1396 1397 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1398 { 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1437 }; 1438 1439 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1440 { 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1483 }; 1484 1485 static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, 1486 int write, u32 *rlcg_flag) 1487 { 1488 switch (hwip) { 1489 case GC_HWIP: 1490 if (amdgpu_sriov_reg_indirect_gc(adev)) { 1491 *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; 1492 1493 return true; 1494 /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */ 1495 } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) { 1496 *rlcg_flag = GFX_RLCG_GC_WRITE_OLD; 1497 1498 return true; 1499 } 1500 1501 break; 1502 case MMHUB_HWIP: 1503 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 1504 (acc_flags & AMDGPU_REGS_RLC) && write) { 1505 *rlcg_flag = GFX_RLCG_MMHUB_WRITE; 1506 return true; 1507 } 1508 1509 break; 1510 default: 1511 DRM_DEBUG("Not program register by RLCG\n"); 1512 } 1513 1514 return false; 1515 } 1516 1517 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag) 1518 { 1519 static void *scratch_reg0; 1520 static void *scratch_reg1; 1521 static void *scratch_reg2; 1522 static void *scratch_reg3; 1523 static void *spare_int; 1524 static uint32_t grbm_cntl; 1525 static uint32_t grbm_idx; 1526 uint32_t i = 0; 1527 uint32_t retries = 50000; 1528 u32 ret = 0; 1529 u32 tmp; 1530 1531 scratch_reg0 = adev->rmmio + 1532 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; 1533 scratch_reg1 = adev->rmmio + 1534 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; 1535 scratch_reg2 = adev->rmmio + 1536 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; 1537 scratch_reg3 = adev->rmmio + 1538 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; 1539 1540 if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 1541 spare_int = adev->rmmio + 1542 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX] 1543 + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4; 1544 } else { 1545 spare_int = adev->rmmio + 1546 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; 1547 } 1548 1549 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1550 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1551 1552 if (offset == grbm_cntl || offset == grbm_idx) { 1553 if (offset == grbm_cntl) 1554 writel(v, scratch_reg2); 1555 else if (offset == grbm_idx) 1556 writel(v, scratch_reg3); 1557 1558 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1559 } else { 1560 writel(v, scratch_reg0); 1561 writel(offset | flag, scratch_reg1); 1562 writel(1, spare_int); 1563 1564 for (i = 0; i < retries; i++) { 1565 tmp = readl(scratch_reg1); 1566 if (!(tmp & flag)) 1567 break; 1568 1569 udelay(10); 1570 } 1571 1572 if (i >= retries) { 1573 if (RLCG_ERROR_REPORT_ENABLED(adev)) { 1574 if (tmp & RLCG_VFGATE_DISABLED) 1575 pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset); 1576 else if (tmp & RLCG_WRONG_OPERATION_TYPE) 1577 pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset); 1578 else if (tmp & RLCG_NOT_IN_RANGE) 1579 pr_err("The register is not in range, program reg:0x%05x failed!\n", offset); 1580 else 1581 pr_err("Unknown error type, program reg:0x%05x failed!\n", offset); 1582 } else 1583 pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset); 1584 } 1585 } 1586 1587 ret = readl(scratch_reg0); 1588 1589 return ret; 1590 } 1591 1592 static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip) 1593 { 1594 u32 rlcg_flag; 1595 1596 if (!amdgpu_sriov_runtime(adev) && 1597 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) { 1598 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag); 1599 return; 1600 } 1601 1602 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1603 WREG32_NO_KIQ(offset, value); 1604 else 1605 WREG32(offset, value); 1606 } 1607 1608 static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip) 1609 { 1610 u32 rlcg_flag; 1611 1612 if (!amdgpu_sriov_runtime(adev) && 1613 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag)) 1614 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag); 1615 1616 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1617 return RREG32_NO_KIQ(offset); 1618 else 1619 return RREG32(offset); 1620 } 1621 1622 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1623 { 1624 /* Pending on emulation bring up */ 1625 }; 1626 1627 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1628 { 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2249 }; 2250 2251 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2252 { 2253 /* Pending on emulation bring up */ 2254 }; 2255 2256 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2257 { 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3310 }; 3311 3312 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3313 { 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3357 }; 3358 3359 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3360 { 3361 /* Pending on emulation bring up */ 3362 }; 3363 3364 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3365 { 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3407 3408 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3410 }; 3411 3412 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3413 { 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3438 3439 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3441 }; 3442 3443 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3444 { 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3465 }; 3466 3467 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3468 { 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3505 }; 3506 3507 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3540 }; 3541 3542 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_PSP_DEBUG, 0x0000003f, 0x00000000), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_PSP_DEBUG, 0x0000003f, 0x00000000), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3579 }; 3580 3581 #define DEFAULT_SH_MEM_CONFIG \ 3582 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3583 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3584 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3585 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3586 3587 /* TODO: pending on golden setting value of gb address config */ 3588 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3589 3590 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3591 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3592 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3593 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3594 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3595 struct amdgpu_cu_info *cu_info); 3596 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3597 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3598 u32 sh_num, u32 instance); 3599 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3600 3601 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3602 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3603 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3604 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3605 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3606 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3607 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3608 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3609 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3610 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3611 3612 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3613 { 3614 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3615 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3616 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3617 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3618 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3619 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3620 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3621 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3622 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3623 } 3624 3625 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3626 struct amdgpu_ring *ring) 3627 { 3628 struct amdgpu_device *adev = kiq_ring->adev; 3629 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3630 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3631 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3632 3633 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3634 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3635 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3636 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3637 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3638 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3639 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3640 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3641 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3642 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3643 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3644 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3645 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3646 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3647 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3648 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3649 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3650 } 3651 3652 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3653 struct amdgpu_ring *ring, 3654 enum amdgpu_unmap_queues_action action, 3655 u64 gpu_addr, u64 seq) 3656 { 3657 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3658 3659 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3660 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3661 PACKET3_UNMAP_QUEUES_ACTION(action) | 3662 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3663 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3664 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3665 amdgpu_ring_write(kiq_ring, 3666 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3667 3668 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3669 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3670 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3671 amdgpu_ring_write(kiq_ring, seq); 3672 } else { 3673 amdgpu_ring_write(kiq_ring, 0); 3674 amdgpu_ring_write(kiq_ring, 0); 3675 amdgpu_ring_write(kiq_ring, 0); 3676 } 3677 } 3678 3679 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3680 struct amdgpu_ring *ring, 3681 u64 addr, 3682 u64 seq) 3683 { 3684 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3685 3686 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3687 amdgpu_ring_write(kiq_ring, 3688 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3689 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3690 PACKET3_QUERY_STATUS_COMMAND(2)); 3691 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3692 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3693 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3694 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3695 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3696 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3697 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3698 } 3699 3700 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3701 uint16_t pasid, uint32_t flush_type, 3702 bool all_hub) 3703 { 3704 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3705 amdgpu_ring_write(kiq_ring, 3706 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3707 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3708 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3709 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3710 } 3711 3712 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3713 .kiq_set_resources = gfx10_kiq_set_resources, 3714 .kiq_map_queues = gfx10_kiq_map_queues, 3715 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3716 .kiq_query_status = gfx10_kiq_query_status, 3717 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3718 .set_resources_size = 8, 3719 .map_queues_size = 7, 3720 .unmap_queues_size = 6, 3721 .query_status_size = 7, 3722 .invalidate_tlbs_size = 2, 3723 }; 3724 3725 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3726 { 3727 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3728 } 3729 3730 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3731 { 3732 switch (adev->asic_type) { 3733 case CHIP_NAVI10: 3734 soc15_program_register_sequence(adev, 3735 golden_settings_gc_rlc_spm_10_0_nv10, 3736 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3737 break; 3738 case CHIP_NAVI14: 3739 soc15_program_register_sequence(adev, 3740 golden_settings_gc_rlc_spm_10_1_nv14, 3741 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3742 break; 3743 case CHIP_NAVI12: 3744 soc15_program_register_sequence(adev, 3745 golden_settings_gc_rlc_spm_10_1_2_nv12, 3746 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3747 break; 3748 default: 3749 break; 3750 } 3751 } 3752 3753 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3754 { 3755 switch (adev->asic_type) { 3756 case CHIP_NAVI10: 3757 soc15_program_register_sequence(adev, 3758 golden_settings_gc_10_1, 3759 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3760 soc15_program_register_sequence(adev, 3761 golden_settings_gc_10_0_nv10, 3762 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3763 break; 3764 case CHIP_NAVI14: 3765 soc15_program_register_sequence(adev, 3766 golden_settings_gc_10_1_1, 3767 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3768 soc15_program_register_sequence(adev, 3769 golden_settings_gc_10_1_nv14, 3770 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3771 break; 3772 case CHIP_NAVI12: 3773 soc15_program_register_sequence(adev, 3774 golden_settings_gc_10_1_2, 3775 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3776 soc15_program_register_sequence(adev, 3777 golden_settings_gc_10_1_2_nv12, 3778 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3779 break; 3780 case CHIP_SIENNA_CICHLID: 3781 soc15_program_register_sequence(adev, 3782 golden_settings_gc_10_3, 3783 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3784 soc15_program_register_sequence(adev, 3785 golden_settings_gc_10_3_sienna_cichlid, 3786 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3787 break; 3788 case CHIP_NAVY_FLOUNDER: 3789 soc15_program_register_sequence(adev, 3790 golden_settings_gc_10_3_2, 3791 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3792 break; 3793 case CHIP_VANGOGH: 3794 soc15_program_register_sequence(adev, 3795 golden_settings_gc_10_3_vangogh, 3796 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3797 break; 3798 case CHIP_YELLOW_CARP: 3799 soc15_program_register_sequence(adev, 3800 golden_settings_gc_10_3_3, 3801 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3802 break; 3803 case CHIP_DIMGREY_CAVEFISH: 3804 soc15_program_register_sequence(adev, 3805 golden_settings_gc_10_3_4, 3806 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3807 break; 3808 case CHIP_BEIGE_GOBY: 3809 soc15_program_register_sequence(adev, 3810 golden_settings_gc_10_3_5, 3811 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3812 break; 3813 case CHIP_CYAN_SKILLFISH: 3814 soc15_program_register_sequence(adev, 3815 golden_settings_gc_10_0, 3816 (const u32)ARRAY_SIZE(golden_settings_gc_10_0)); 3817 soc15_program_register_sequence(adev, 3818 golden_settings_gc_10_0_cyan_skillfish, 3819 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3820 break; 3821 default: 3822 break; 3823 } 3824 gfx_v10_0_init_spm_golden_registers(adev); 3825 } 3826 3827 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3828 { 3829 adev->gfx.scratch.num_reg = 8; 3830 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3831 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3832 } 3833 3834 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3835 bool wc, uint32_t reg, uint32_t val) 3836 { 3837 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3838 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3839 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3840 amdgpu_ring_write(ring, reg); 3841 amdgpu_ring_write(ring, 0); 3842 amdgpu_ring_write(ring, val); 3843 } 3844 3845 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3846 int mem_space, int opt, uint32_t addr0, 3847 uint32_t addr1, uint32_t ref, uint32_t mask, 3848 uint32_t inv) 3849 { 3850 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3851 amdgpu_ring_write(ring, 3852 /* memory (1) or register (0) */ 3853 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3854 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3855 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3856 WAIT_REG_MEM_ENGINE(eng_sel))); 3857 3858 if (mem_space) 3859 BUG_ON(addr0 & 0x3); /* Dword align */ 3860 amdgpu_ring_write(ring, addr0); 3861 amdgpu_ring_write(ring, addr1); 3862 amdgpu_ring_write(ring, ref); 3863 amdgpu_ring_write(ring, mask); 3864 amdgpu_ring_write(ring, inv); /* poll interval */ 3865 } 3866 3867 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3868 { 3869 struct amdgpu_device *adev = ring->adev; 3870 uint32_t scratch; 3871 uint32_t tmp = 0; 3872 unsigned i; 3873 int r; 3874 3875 r = amdgpu_gfx_scratch_get(adev, &scratch); 3876 if (r) { 3877 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3878 return r; 3879 } 3880 3881 WREG32(scratch, 0xCAFEDEAD); 3882 3883 r = amdgpu_ring_alloc(ring, 3); 3884 if (r) { 3885 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3886 ring->idx, r); 3887 amdgpu_gfx_scratch_free(adev, scratch); 3888 return r; 3889 } 3890 3891 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3892 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3893 amdgpu_ring_write(ring, 0xDEADBEEF); 3894 amdgpu_ring_commit(ring); 3895 3896 for (i = 0; i < adev->usec_timeout; i++) { 3897 tmp = RREG32(scratch); 3898 if (tmp == 0xDEADBEEF) 3899 break; 3900 if (amdgpu_emu_mode == 1) 3901 msleep(1); 3902 else 3903 udelay(1); 3904 } 3905 3906 if (i >= adev->usec_timeout) 3907 r = -ETIMEDOUT; 3908 3909 amdgpu_gfx_scratch_free(adev, scratch); 3910 3911 return r; 3912 } 3913 3914 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3915 { 3916 struct amdgpu_device *adev = ring->adev; 3917 struct amdgpu_ib ib; 3918 struct dma_fence *f = NULL; 3919 unsigned index; 3920 uint64_t gpu_addr; 3921 uint32_t tmp; 3922 long r; 3923 3924 r = amdgpu_device_wb_get(adev, &index); 3925 if (r) 3926 return r; 3927 3928 gpu_addr = adev->wb.gpu_addr + (index * 4); 3929 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3930 memset(&ib, 0, sizeof(ib)); 3931 r = amdgpu_ib_get(adev, NULL, 16, 3932 AMDGPU_IB_POOL_DIRECT, &ib); 3933 if (r) 3934 goto err1; 3935 3936 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3937 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3938 ib.ptr[2] = lower_32_bits(gpu_addr); 3939 ib.ptr[3] = upper_32_bits(gpu_addr); 3940 ib.ptr[4] = 0xDEADBEEF; 3941 ib.length_dw = 5; 3942 3943 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3944 if (r) 3945 goto err2; 3946 3947 r = dma_fence_wait_timeout(f, false, timeout); 3948 if (r == 0) { 3949 r = -ETIMEDOUT; 3950 goto err2; 3951 } else if (r < 0) { 3952 goto err2; 3953 } 3954 3955 tmp = adev->wb.wb[index]; 3956 if (tmp == 0xDEADBEEF) 3957 r = 0; 3958 else 3959 r = -EINVAL; 3960 err2: 3961 amdgpu_ib_free(adev, &ib, NULL); 3962 dma_fence_put(f); 3963 err1: 3964 amdgpu_device_wb_free(adev, index); 3965 return r; 3966 } 3967 3968 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3969 { 3970 release_firmware(adev->gfx.pfp_fw); 3971 adev->gfx.pfp_fw = NULL; 3972 release_firmware(adev->gfx.me_fw); 3973 adev->gfx.me_fw = NULL; 3974 release_firmware(adev->gfx.ce_fw); 3975 adev->gfx.ce_fw = NULL; 3976 release_firmware(adev->gfx.rlc_fw); 3977 adev->gfx.rlc_fw = NULL; 3978 release_firmware(adev->gfx.mec_fw); 3979 adev->gfx.mec_fw = NULL; 3980 release_firmware(adev->gfx.mec2_fw); 3981 adev->gfx.mec2_fw = NULL; 3982 3983 kfree(adev->gfx.rlc.register_list_format); 3984 } 3985 3986 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3987 { 3988 adev->gfx.cp_fw_write_wait = false; 3989 3990 switch (adev->asic_type) { 3991 case CHIP_NAVI10: 3992 case CHIP_NAVI12: 3993 case CHIP_NAVI14: 3994 case CHIP_CYAN_SKILLFISH: 3995 if ((adev->gfx.me_fw_version >= 0x00000046) && 3996 (adev->gfx.me_feature_version >= 27) && 3997 (adev->gfx.pfp_fw_version >= 0x00000068) && 3998 (adev->gfx.pfp_feature_version >= 27) && 3999 (adev->gfx.mec_fw_version >= 0x0000005b) && 4000 (adev->gfx.mec_feature_version >= 27)) 4001 adev->gfx.cp_fw_write_wait = true; 4002 break; 4003 case CHIP_SIENNA_CICHLID: 4004 case CHIP_NAVY_FLOUNDER: 4005 case CHIP_VANGOGH: 4006 case CHIP_DIMGREY_CAVEFISH: 4007 case CHIP_BEIGE_GOBY: 4008 case CHIP_YELLOW_CARP: 4009 adev->gfx.cp_fw_write_wait = true; 4010 break; 4011 default: 4012 break; 4013 } 4014 4015 if (!adev->gfx.cp_fw_write_wait) 4016 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4017 } 4018 4019 4020 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 4021 { 4022 const struct rlc_firmware_header_v2_1 *rlc_hdr; 4023 4024 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 4025 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 4026 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 4027 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 4028 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 4029 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 4030 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 4031 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 4032 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 4033 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 4034 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 4035 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 4036 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 4037 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 4038 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 4039 } 4040 4041 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 4042 { 4043 const struct rlc_firmware_header_v2_2 *rlc_hdr; 4044 4045 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 4046 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 4047 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 4048 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 4049 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 4050 } 4051 4052 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4053 { 4054 bool ret = false; 4055 4056 switch (adev->pdev->revision) { 4057 case 0xc2: 4058 case 0xc3: 4059 ret = true; 4060 break; 4061 default: 4062 ret = false; 4063 break; 4064 } 4065 4066 return ret ; 4067 } 4068 4069 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4070 { 4071 switch (adev->asic_type) { 4072 case CHIP_NAVI10: 4073 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4074 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4075 break; 4076 default: 4077 break; 4078 } 4079 } 4080 4081 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4082 { 4083 const char *chip_name; 4084 char fw_name[40]; 4085 char *wks = ""; 4086 int err; 4087 struct amdgpu_firmware_info *info = NULL; 4088 const struct common_firmware_header *header = NULL; 4089 const struct gfx_firmware_header_v1_0 *cp_hdr; 4090 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4091 unsigned int *tmp = NULL; 4092 unsigned int i = 0; 4093 uint16_t version_major; 4094 uint16_t version_minor; 4095 4096 DRM_DEBUG("\n"); 4097 4098 switch (adev->asic_type) { 4099 case CHIP_NAVI10: 4100 chip_name = "navi10"; 4101 break; 4102 case CHIP_NAVI14: 4103 chip_name = "navi14"; 4104 if (!(adev->pdev->device == 0x7340 && 4105 adev->pdev->revision != 0x00)) 4106 wks = "_wks"; 4107 break; 4108 case CHIP_NAVI12: 4109 chip_name = "navi12"; 4110 break; 4111 case CHIP_SIENNA_CICHLID: 4112 chip_name = "sienna_cichlid"; 4113 break; 4114 case CHIP_NAVY_FLOUNDER: 4115 chip_name = "navy_flounder"; 4116 break; 4117 case CHIP_VANGOGH: 4118 chip_name = "vangogh"; 4119 break; 4120 case CHIP_DIMGREY_CAVEFISH: 4121 chip_name = "dimgrey_cavefish"; 4122 break; 4123 case CHIP_BEIGE_GOBY: 4124 chip_name = "beige_goby"; 4125 break; 4126 case CHIP_YELLOW_CARP: 4127 chip_name = "yellow_carp"; 4128 break; 4129 case CHIP_CYAN_SKILLFISH: 4130 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 4131 chip_name = "cyan_skillfish2"; 4132 else 4133 chip_name = "cyan_skillfish"; 4134 break; 4135 default: 4136 BUG(); 4137 } 4138 4139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 4140 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 4141 if (err) 4142 goto out; 4143 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 4144 if (err) 4145 goto out; 4146 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 4147 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4148 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4149 4150 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 4151 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 4152 if (err) 4153 goto out; 4154 err = amdgpu_ucode_validate(adev->gfx.me_fw); 4155 if (err) 4156 goto out; 4157 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 4158 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4159 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4160 4161 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 4162 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 4163 if (err) 4164 goto out; 4165 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 4166 if (err) 4167 goto out; 4168 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 4169 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4170 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4171 4172 if (!amdgpu_sriov_vf(adev)) { 4173 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 4174 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4175 if (err) 4176 goto out; 4177 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 4178 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4179 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4180 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4181 4182 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 4183 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 4184 adev->gfx.rlc.save_and_restore_offset = 4185 le32_to_cpu(rlc_hdr->save_and_restore_offset); 4186 adev->gfx.rlc.clear_state_descriptor_offset = 4187 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 4188 adev->gfx.rlc.avail_scratch_ram_locations = 4189 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 4190 adev->gfx.rlc.reg_restore_list_size = 4191 le32_to_cpu(rlc_hdr->reg_restore_list_size); 4192 adev->gfx.rlc.reg_list_format_start = 4193 le32_to_cpu(rlc_hdr->reg_list_format_start); 4194 adev->gfx.rlc.reg_list_format_separate_start = 4195 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 4196 adev->gfx.rlc.starting_offsets_start = 4197 le32_to_cpu(rlc_hdr->starting_offsets_start); 4198 adev->gfx.rlc.reg_list_format_size_bytes = 4199 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 4200 adev->gfx.rlc.reg_list_size_bytes = 4201 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 4202 adev->gfx.rlc.register_list_format = 4203 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 4204 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 4205 if (!adev->gfx.rlc.register_list_format) { 4206 err = -ENOMEM; 4207 goto out; 4208 } 4209 4210 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4211 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 4212 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 4213 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 4214 4215 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 4216 4217 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4218 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 4219 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 4220 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 4221 4222 if (version_major == 2) { 4223 if (version_minor >= 1) 4224 gfx_v10_0_init_rlc_ext_microcode(adev); 4225 if (version_minor == 2) 4226 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 4227 } 4228 } 4229 4230 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 4231 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 4232 if (err) 4233 goto out; 4234 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 4235 if (err) 4236 goto out; 4237 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4238 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4239 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4240 4241 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 4242 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 4243 if (!err) { 4244 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 4245 if (err) 4246 goto out; 4247 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 4248 adev->gfx.mec2_fw->data; 4249 adev->gfx.mec2_fw_version = 4250 le32_to_cpu(cp_hdr->header.ucode_version); 4251 adev->gfx.mec2_feature_version = 4252 le32_to_cpu(cp_hdr->ucode_feature_version); 4253 } else { 4254 err = 0; 4255 adev->gfx.mec2_fw = NULL; 4256 } 4257 4258 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 4259 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 4260 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 4261 info->fw = adev->gfx.pfp_fw; 4262 header = (const struct common_firmware_header *)info->fw->data; 4263 adev->firmware.fw_size += 4264 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4265 4266 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 4267 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 4268 info->fw = adev->gfx.me_fw; 4269 header = (const struct common_firmware_header *)info->fw->data; 4270 adev->firmware.fw_size += 4271 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4272 4273 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 4274 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 4275 info->fw = adev->gfx.ce_fw; 4276 header = (const struct common_firmware_header *)info->fw->data; 4277 adev->firmware.fw_size += 4278 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4279 4280 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 4281 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 4282 info->fw = adev->gfx.rlc_fw; 4283 if (info->fw) { 4284 header = (const struct common_firmware_header *)info->fw->data; 4285 adev->firmware.fw_size += 4286 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4287 } 4288 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 4289 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 4290 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 4291 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 4292 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 4293 info->fw = adev->gfx.rlc_fw; 4294 adev->firmware.fw_size += 4295 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 4296 4297 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 4298 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 4299 info->fw = adev->gfx.rlc_fw; 4300 adev->firmware.fw_size += 4301 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4302 4303 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4304 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4305 info->fw = adev->gfx.rlc_fw; 4306 adev->firmware.fw_size += 4307 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4308 4309 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4310 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4311 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4312 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4313 info->fw = adev->gfx.rlc_fw; 4314 adev->firmware.fw_size += 4315 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4316 4317 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4318 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4319 info->fw = adev->gfx.rlc_fw; 4320 adev->firmware.fw_size += 4321 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4322 } 4323 } 4324 4325 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4326 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4327 info->fw = adev->gfx.mec_fw; 4328 header = (const struct common_firmware_header *)info->fw->data; 4329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4330 adev->firmware.fw_size += 4331 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4332 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4333 4334 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4335 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4336 info->fw = adev->gfx.mec_fw; 4337 adev->firmware.fw_size += 4338 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4339 4340 if (adev->gfx.mec2_fw) { 4341 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4342 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4343 info->fw = adev->gfx.mec2_fw; 4344 header = (const struct common_firmware_header *)info->fw->data; 4345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4346 adev->firmware.fw_size += 4347 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4348 le32_to_cpu(cp_hdr->jt_size) * 4, 4349 PAGE_SIZE); 4350 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4351 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4352 info->fw = adev->gfx.mec2_fw; 4353 adev->firmware.fw_size += 4354 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4355 PAGE_SIZE); 4356 } 4357 } 4358 4359 gfx_v10_0_check_fw_write_wait(adev); 4360 out: 4361 if (err) { 4362 dev_err(adev->dev, 4363 "gfx10: Failed to load firmware \"%s\"\n", 4364 fw_name); 4365 release_firmware(adev->gfx.pfp_fw); 4366 adev->gfx.pfp_fw = NULL; 4367 release_firmware(adev->gfx.me_fw); 4368 adev->gfx.me_fw = NULL; 4369 release_firmware(adev->gfx.ce_fw); 4370 adev->gfx.ce_fw = NULL; 4371 release_firmware(adev->gfx.rlc_fw); 4372 adev->gfx.rlc_fw = NULL; 4373 release_firmware(adev->gfx.mec_fw); 4374 adev->gfx.mec_fw = NULL; 4375 release_firmware(adev->gfx.mec2_fw); 4376 adev->gfx.mec2_fw = NULL; 4377 } 4378 4379 gfx_v10_0_check_gfxoff_flag(adev); 4380 4381 return err; 4382 } 4383 4384 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4385 { 4386 u32 count = 0; 4387 const struct cs_section_def *sect = NULL; 4388 const struct cs_extent_def *ext = NULL; 4389 4390 /* begin clear state */ 4391 count += 2; 4392 /* context control state */ 4393 count += 3; 4394 4395 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4396 for (ext = sect->section; ext->extent != NULL; ++ext) { 4397 if (sect->id == SECT_CONTEXT) 4398 count += 2 + ext->reg_count; 4399 else 4400 return 0; 4401 } 4402 } 4403 4404 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4405 count += 3; 4406 /* end clear state */ 4407 count += 2; 4408 /* clear state */ 4409 count += 2; 4410 4411 return count; 4412 } 4413 4414 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4415 volatile u32 *buffer) 4416 { 4417 u32 count = 0, i; 4418 const struct cs_section_def *sect = NULL; 4419 const struct cs_extent_def *ext = NULL; 4420 int ctx_reg_offset; 4421 4422 if (adev->gfx.rlc.cs_data == NULL) 4423 return; 4424 if (buffer == NULL) 4425 return; 4426 4427 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4428 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4429 4430 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4431 buffer[count++] = cpu_to_le32(0x80000000); 4432 buffer[count++] = cpu_to_le32(0x80000000); 4433 4434 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4435 for (ext = sect->section; ext->extent != NULL; ++ext) { 4436 if (sect->id == SECT_CONTEXT) { 4437 buffer[count++] = 4438 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4439 buffer[count++] = cpu_to_le32(ext->reg_index - 4440 PACKET3_SET_CONTEXT_REG_START); 4441 for (i = 0; i < ext->reg_count; i++) 4442 buffer[count++] = cpu_to_le32(ext->extent[i]); 4443 } else { 4444 return; 4445 } 4446 } 4447 } 4448 4449 ctx_reg_offset = 4450 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4451 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4452 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4453 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4454 4455 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4456 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4457 4458 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4459 buffer[count++] = cpu_to_le32(0); 4460 } 4461 4462 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4463 { 4464 /* clear state block */ 4465 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4466 &adev->gfx.rlc.clear_state_gpu_addr, 4467 (void **)&adev->gfx.rlc.cs_ptr); 4468 4469 /* jump table block */ 4470 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4471 &adev->gfx.rlc.cp_table_gpu_addr, 4472 (void **)&adev->gfx.rlc.cp_table_ptr); 4473 } 4474 4475 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4476 { 4477 const struct cs_section_def *cs_data; 4478 int r; 4479 4480 adev->gfx.rlc.cs_data = gfx10_cs_data; 4481 4482 cs_data = adev->gfx.rlc.cs_data; 4483 4484 if (cs_data) { 4485 /* init clear state block */ 4486 r = amdgpu_gfx_rlc_init_csb(adev); 4487 if (r) 4488 return r; 4489 } 4490 4491 /* init spm vmid with 0xf */ 4492 if (adev->gfx.rlc.funcs->update_spm_vmid) 4493 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4494 4495 return 0; 4496 } 4497 4498 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4499 { 4500 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4501 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4502 } 4503 4504 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4505 { 4506 int r; 4507 4508 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4509 4510 amdgpu_gfx_graphics_queue_acquire(adev); 4511 4512 r = gfx_v10_0_init_microcode(adev); 4513 if (r) 4514 DRM_ERROR("Failed to load gfx firmware!\n"); 4515 4516 return r; 4517 } 4518 4519 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4520 { 4521 int r; 4522 u32 *hpd; 4523 const __le32 *fw_data = NULL; 4524 unsigned fw_size; 4525 u32 *fw = NULL; 4526 size_t mec_hpd_size; 4527 4528 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4529 4530 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4531 4532 /* take ownership of the relevant compute queues */ 4533 amdgpu_gfx_compute_queue_acquire(adev); 4534 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4535 4536 if (mec_hpd_size) { 4537 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4538 AMDGPU_GEM_DOMAIN_GTT, 4539 &adev->gfx.mec.hpd_eop_obj, 4540 &adev->gfx.mec.hpd_eop_gpu_addr, 4541 (void **)&hpd); 4542 if (r) { 4543 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4544 gfx_v10_0_mec_fini(adev); 4545 return r; 4546 } 4547 4548 memset(hpd, 0, mec_hpd_size); 4549 4550 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4551 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4552 } 4553 4554 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4555 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4556 4557 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4558 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4559 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4560 4561 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4562 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4563 &adev->gfx.mec.mec_fw_obj, 4564 &adev->gfx.mec.mec_fw_gpu_addr, 4565 (void **)&fw); 4566 if (r) { 4567 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4568 gfx_v10_0_mec_fini(adev); 4569 return r; 4570 } 4571 4572 memcpy(fw, fw_data, fw_size); 4573 4574 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4575 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4576 } 4577 4578 return 0; 4579 } 4580 4581 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4582 { 4583 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4584 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4585 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4586 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4587 } 4588 4589 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4590 uint32_t thread, uint32_t regno, 4591 uint32_t num, uint32_t *out) 4592 { 4593 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4594 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4595 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4596 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4597 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4598 while (num--) 4599 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4600 } 4601 4602 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4603 { 4604 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4605 * field when performing a select_se_sh so it should be 4606 * zero here */ 4607 WARN_ON(simd != 0); 4608 4609 /* type 2 wave data */ 4610 dst[(*no_fields)++] = 2; 4611 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4612 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4613 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4614 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4615 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4616 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4617 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4618 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4619 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4620 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4621 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4622 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4623 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4624 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4625 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4626 } 4627 4628 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4629 uint32_t wave, uint32_t start, 4630 uint32_t size, uint32_t *dst) 4631 { 4632 WARN_ON(simd != 0); 4633 4634 wave_read_regs( 4635 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4636 dst); 4637 } 4638 4639 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4640 uint32_t wave, uint32_t thread, 4641 uint32_t start, uint32_t size, 4642 uint32_t *dst) 4643 { 4644 wave_read_regs( 4645 adev, wave, thread, 4646 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4647 } 4648 4649 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4650 u32 me, u32 pipe, u32 q, u32 vm) 4651 { 4652 nv_grbm_select(adev, me, pipe, q, vm); 4653 } 4654 4655 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4656 bool enable) 4657 { 4658 uint32_t data, def; 4659 4660 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4661 4662 if (enable) 4663 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4664 else 4665 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4666 4667 if (data != def) 4668 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4669 } 4670 4671 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4672 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4673 .select_se_sh = &gfx_v10_0_select_se_sh, 4674 .read_wave_data = &gfx_v10_0_read_wave_data, 4675 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4676 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4677 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4678 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4679 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4680 }; 4681 4682 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4683 { 4684 u32 gb_addr_config; 4685 4686 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4687 4688 switch (adev->asic_type) { 4689 case CHIP_NAVI10: 4690 case CHIP_NAVI14: 4691 case CHIP_NAVI12: 4692 adev->gfx.config.max_hw_contexts = 8; 4693 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4694 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4695 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4696 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4697 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4698 break; 4699 case CHIP_SIENNA_CICHLID: 4700 case CHIP_NAVY_FLOUNDER: 4701 case CHIP_VANGOGH: 4702 case CHIP_DIMGREY_CAVEFISH: 4703 case CHIP_BEIGE_GOBY: 4704 case CHIP_YELLOW_CARP: 4705 adev->gfx.config.max_hw_contexts = 8; 4706 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4707 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4708 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4709 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4710 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4711 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4712 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4713 break; 4714 case CHIP_CYAN_SKILLFISH: 4715 adev->gfx.config.max_hw_contexts = 8; 4716 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4717 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4718 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4719 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4720 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4721 break; 4722 default: 4723 BUG(); 4724 break; 4725 } 4726 4727 adev->gfx.config.gb_addr_config = gb_addr_config; 4728 4729 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4730 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4731 GB_ADDR_CONFIG, NUM_PIPES); 4732 4733 adev->gfx.config.max_tile_pipes = 4734 adev->gfx.config.gb_addr_config_fields.num_pipes; 4735 4736 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4737 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4738 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4739 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4740 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4741 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4742 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4743 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4744 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4745 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4746 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4747 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4748 } 4749 4750 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4751 int me, int pipe, int queue) 4752 { 4753 int r; 4754 struct amdgpu_ring *ring; 4755 unsigned int irq_type; 4756 4757 ring = &adev->gfx.gfx_ring[ring_id]; 4758 4759 ring->me = me; 4760 ring->pipe = pipe; 4761 ring->queue = queue; 4762 4763 ring->ring_obj = NULL; 4764 ring->use_doorbell = true; 4765 4766 if (!ring_id) 4767 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4768 else 4769 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4770 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4771 4772 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4773 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4774 AMDGPU_RING_PRIO_DEFAULT, NULL); 4775 if (r) 4776 return r; 4777 return 0; 4778 } 4779 4780 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4781 int mec, int pipe, int queue) 4782 { 4783 int r; 4784 unsigned irq_type; 4785 struct amdgpu_ring *ring; 4786 unsigned int hw_prio; 4787 4788 ring = &adev->gfx.compute_ring[ring_id]; 4789 4790 /* mec0 is me1 */ 4791 ring->me = mec + 1; 4792 ring->pipe = pipe; 4793 ring->queue = queue; 4794 4795 ring->ring_obj = NULL; 4796 ring->use_doorbell = true; 4797 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4798 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4799 + (ring_id * GFX10_MEC_HPD_SIZE); 4800 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4801 4802 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4803 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4804 + ring->pipe; 4805 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4806 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4807 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4808 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4809 hw_prio, NULL); 4810 if (r) 4811 return r; 4812 4813 return 0; 4814 } 4815 4816 static int gfx_v10_0_sw_init(void *handle) 4817 { 4818 int i, j, k, r, ring_id = 0; 4819 struct amdgpu_kiq *kiq; 4820 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4821 4822 switch (adev->asic_type) { 4823 case CHIP_NAVI10: 4824 case CHIP_NAVI14: 4825 case CHIP_NAVI12: 4826 case CHIP_CYAN_SKILLFISH: 4827 adev->gfx.me.num_me = 1; 4828 adev->gfx.me.num_pipe_per_me = 1; 4829 adev->gfx.me.num_queue_per_pipe = 1; 4830 adev->gfx.mec.num_mec = 2; 4831 adev->gfx.mec.num_pipe_per_mec = 4; 4832 adev->gfx.mec.num_queue_per_pipe = 8; 4833 break; 4834 case CHIP_SIENNA_CICHLID: 4835 case CHIP_NAVY_FLOUNDER: 4836 case CHIP_VANGOGH: 4837 case CHIP_DIMGREY_CAVEFISH: 4838 case CHIP_BEIGE_GOBY: 4839 case CHIP_YELLOW_CARP: 4840 adev->gfx.me.num_me = 1; 4841 adev->gfx.me.num_pipe_per_me = 1; 4842 adev->gfx.me.num_queue_per_pipe = 1; 4843 adev->gfx.mec.num_mec = 2; 4844 adev->gfx.mec.num_pipe_per_mec = 4; 4845 adev->gfx.mec.num_queue_per_pipe = 4; 4846 break; 4847 default: 4848 adev->gfx.me.num_me = 1; 4849 adev->gfx.me.num_pipe_per_me = 1; 4850 adev->gfx.me.num_queue_per_pipe = 1; 4851 adev->gfx.mec.num_mec = 1; 4852 adev->gfx.mec.num_pipe_per_mec = 4; 4853 adev->gfx.mec.num_queue_per_pipe = 8; 4854 break; 4855 } 4856 4857 /* KIQ event */ 4858 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4859 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4860 &adev->gfx.kiq.irq); 4861 if (r) 4862 return r; 4863 4864 /* EOP Event */ 4865 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4866 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4867 &adev->gfx.eop_irq); 4868 if (r) 4869 return r; 4870 4871 /* Privileged reg */ 4872 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4873 &adev->gfx.priv_reg_irq); 4874 if (r) 4875 return r; 4876 4877 /* Privileged inst */ 4878 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4879 &adev->gfx.priv_inst_irq); 4880 if (r) 4881 return r; 4882 4883 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4884 4885 gfx_v10_0_scratch_init(adev); 4886 4887 r = gfx_v10_0_me_init(adev); 4888 if (r) 4889 return r; 4890 4891 r = gfx_v10_0_rlc_init(adev); 4892 if (r) { 4893 DRM_ERROR("Failed to init rlc BOs!\n"); 4894 return r; 4895 } 4896 4897 r = gfx_v10_0_mec_init(adev); 4898 if (r) { 4899 DRM_ERROR("Failed to init MEC BOs!\n"); 4900 return r; 4901 } 4902 4903 /* set up the gfx ring */ 4904 for (i = 0; i < adev->gfx.me.num_me; i++) { 4905 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4906 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4907 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4908 continue; 4909 4910 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4911 i, k, j); 4912 if (r) 4913 return r; 4914 ring_id++; 4915 } 4916 } 4917 } 4918 4919 ring_id = 0; 4920 /* set up the compute queues - allocate horizontally across pipes */ 4921 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4922 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4923 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4924 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4925 j)) 4926 continue; 4927 4928 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4929 i, k, j); 4930 if (r) 4931 return r; 4932 4933 ring_id++; 4934 } 4935 } 4936 } 4937 4938 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4939 if (r) { 4940 DRM_ERROR("Failed to init KIQ BOs!\n"); 4941 return r; 4942 } 4943 4944 kiq = &adev->gfx.kiq; 4945 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4946 if (r) 4947 return r; 4948 4949 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4950 if (r) 4951 return r; 4952 4953 /* allocate visible FB for rlc auto-loading fw */ 4954 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4955 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4956 if (r) 4957 return r; 4958 } 4959 4960 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4961 4962 gfx_v10_0_gpu_early_init(adev); 4963 4964 return 0; 4965 } 4966 4967 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4968 { 4969 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4970 &adev->gfx.pfp.pfp_fw_gpu_addr, 4971 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4972 } 4973 4974 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4975 { 4976 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4977 &adev->gfx.ce.ce_fw_gpu_addr, 4978 (void **)&adev->gfx.ce.ce_fw_ptr); 4979 } 4980 4981 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4982 { 4983 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4984 &adev->gfx.me.me_fw_gpu_addr, 4985 (void **)&adev->gfx.me.me_fw_ptr); 4986 } 4987 4988 static int gfx_v10_0_sw_fini(void *handle) 4989 { 4990 int i; 4991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4992 4993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4994 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4995 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4996 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4997 4998 amdgpu_gfx_mqd_sw_fini(adev); 4999 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 5000 amdgpu_gfx_kiq_fini(adev); 5001 5002 gfx_v10_0_pfp_fini(adev); 5003 gfx_v10_0_ce_fini(adev); 5004 gfx_v10_0_me_fini(adev); 5005 gfx_v10_0_rlc_fini(adev); 5006 gfx_v10_0_mec_fini(adev); 5007 5008 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 5009 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 5010 5011 gfx_v10_0_free_microcode(adev); 5012 5013 return 0; 5014 } 5015 5016 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 5017 u32 sh_num, u32 instance) 5018 { 5019 u32 data; 5020 5021 if (instance == 0xffffffff) 5022 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 5023 INSTANCE_BROADCAST_WRITES, 1); 5024 else 5025 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 5026 instance); 5027 5028 if (se_num == 0xffffffff) 5029 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 5030 1); 5031 else 5032 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 5033 5034 if (sh_num == 0xffffffff) 5035 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 5036 1); 5037 else 5038 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 5039 5040 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 5041 } 5042 5043 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 5044 { 5045 u32 data, mask; 5046 5047 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5048 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5049 5050 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5051 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5052 5053 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5054 adev->gfx.config.max_sh_per_se); 5055 5056 return (~data) & mask; 5057 } 5058 5059 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5060 { 5061 int i, j; 5062 u32 data; 5063 u32 active_rbs = 0; 5064 u32 bitmap; 5065 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5066 adev->gfx.config.max_sh_per_se; 5067 5068 mutex_lock(&adev->grbm_idx_mutex); 5069 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5070 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5071 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5072 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 5073 (adev->asic_type == CHIP_YELLOW_CARP)) && 5074 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5075 continue; 5076 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5077 data = gfx_v10_0_get_rb_active_bitmap(adev); 5078 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5079 rb_bitmap_width_per_sh); 5080 } 5081 } 5082 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5083 mutex_unlock(&adev->grbm_idx_mutex); 5084 5085 adev->gfx.config.backend_enable_mask = active_rbs; 5086 adev->gfx.config.num_rbs = hweight32(active_rbs); 5087 } 5088 5089 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5090 { 5091 uint32_t num_sc; 5092 uint32_t enabled_rb_per_sh; 5093 uint32_t active_rb_bitmap; 5094 uint32_t num_rb_per_sc; 5095 uint32_t num_packer_per_sc; 5096 uint32_t pa_sc_tile_steering_override; 5097 5098 /* for ASICs that integrates GFX v10.3 5099 * pa_sc_tile_steering_override should be set to 0 */ 5100 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 5101 return 0; 5102 5103 /* init num_sc */ 5104 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5105 adev->gfx.config.num_sc_per_sh; 5106 /* init num_rb_per_sc */ 5107 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5108 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5109 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5110 /* init num_packer_per_sc */ 5111 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5112 5113 pa_sc_tile_steering_override = 0; 5114 pa_sc_tile_steering_override |= 5115 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5116 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5117 pa_sc_tile_steering_override |= 5118 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5119 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5120 pa_sc_tile_steering_override |= 5121 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5122 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5123 5124 return pa_sc_tile_steering_override; 5125 } 5126 5127 #define DEFAULT_SH_MEM_BASES (0x6000) 5128 5129 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5130 { 5131 int i; 5132 uint32_t sh_mem_bases; 5133 5134 /* 5135 * Configure apertures: 5136 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5137 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5138 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5139 */ 5140 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5141 5142 mutex_lock(&adev->srbm_mutex); 5143 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5144 nv_grbm_select(adev, 0, 0, 0, i); 5145 /* CP and shaders */ 5146 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5147 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5148 } 5149 nv_grbm_select(adev, 0, 0, 0, 0); 5150 mutex_unlock(&adev->srbm_mutex); 5151 5152 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 5153 acccess. These should be enabled by FW for target VMIDs. */ 5154 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5155 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5156 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5157 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5158 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5159 } 5160 } 5161 5162 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5163 { 5164 int vmid; 5165 5166 /* 5167 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5168 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5169 * the driver can enable them for graphics. VMID0 should maintain 5170 * access so that HWS firmware can save/restore entries. 5171 */ 5172 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5173 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5174 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5175 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5176 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5177 } 5178 } 5179 5180 5181 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5182 { 5183 int i, j, k; 5184 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5185 u32 tmp, wgp_active_bitmap = 0; 5186 u32 gcrd_targets_disable_tcp = 0; 5187 u32 utcl_invreq_disable = 0; 5188 /* 5189 * GCRD_TARGETS_DISABLE field contains 5190 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5191 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5192 */ 5193 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5194 2 * max_wgp_per_sh + /* TCP */ 5195 max_wgp_per_sh + /* SQC */ 5196 4); /* GL1C */ 5197 /* 5198 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5199 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5200 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5201 */ 5202 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5203 2 * max_wgp_per_sh + /* TCP */ 5204 2 * max_wgp_per_sh + /* SQC */ 5205 4 + /* RMI */ 5206 1); /* SQG */ 5207 5208 mutex_lock(&adev->grbm_idx_mutex); 5209 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5210 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5211 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5212 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5213 /* 5214 * Set corresponding TCP bits for the inactive WGPs in 5215 * GCRD_SA_TARGETS_DISABLE 5216 */ 5217 gcrd_targets_disable_tcp = 0; 5218 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5219 utcl_invreq_disable = 0; 5220 5221 for (k = 0; k < max_wgp_per_sh; k++) { 5222 if (!(wgp_active_bitmap & (1 << k))) { 5223 gcrd_targets_disable_tcp |= 3 << (2 * k); 5224 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5225 utcl_invreq_disable |= (3 << (2 * k)) | 5226 (3 << (2 * (max_wgp_per_sh + k))); 5227 } 5228 } 5229 5230 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5231 /* only override TCP & SQC bits */ 5232 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5233 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5234 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5235 5236 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5237 /* only override TCP & SQC bits */ 5238 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5239 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5240 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5241 } 5242 } 5243 5244 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5245 mutex_unlock(&adev->grbm_idx_mutex); 5246 } 5247 5248 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5249 { 5250 /* TCCs are global (not instanced). */ 5251 uint32_t tcc_disable; 5252 5253 if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 5254 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5255 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5256 } else { 5257 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5258 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5259 } 5260 5261 adev->gfx.config.tcc_disabled_mask = 5262 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5263 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5264 } 5265 5266 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5267 { 5268 u32 tmp; 5269 int i; 5270 5271 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5272 5273 gfx_v10_0_setup_rb(adev); 5274 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5275 gfx_v10_0_get_tcc_info(adev); 5276 adev->gfx.config.pa_sc_tile_steering_override = 5277 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5278 5279 /* XXX SH_MEM regs */ 5280 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5281 mutex_lock(&adev->srbm_mutex); 5282 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 5283 nv_grbm_select(adev, 0, 0, 0, i); 5284 /* CP and shaders */ 5285 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5286 if (i != 0) { 5287 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5288 (adev->gmc.private_aperture_start >> 48)); 5289 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5290 (adev->gmc.shared_aperture_start >> 48)); 5291 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5292 } 5293 } 5294 nv_grbm_select(adev, 0, 0, 0, 0); 5295 5296 mutex_unlock(&adev->srbm_mutex); 5297 5298 gfx_v10_0_init_compute_vmid(adev); 5299 gfx_v10_0_init_gds_vmid(adev); 5300 5301 } 5302 5303 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5304 bool enable) 5305 { 5306 u32 tmp; 5307 5308 if (amdgpu_sriov_vf(adev)) 5309 return; 5310 5311 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5312 5313 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5314 enable ? 1 : 0); 5315 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5316 enable ? 1 : 0); 5317 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5318 enable ? 1 : 0); 5319 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5320 enable ? 1 : 0); 5321 5322 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5323 } 5324 5325 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5326 { 5327 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5328 5329 /* csib */ 5330 if (adev->asic_type == CHIP_NAVI12) { 5331 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5332 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5333 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5334 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5335 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5336 } else { 5337 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5338 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5339 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5340 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5341 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5342 } 5343 return 0; 5344 } 5345 5346 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5347 { 5348 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5349 5350 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5351 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5352 } 5353 5354 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5355 { 5356 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5357 udelay(50); 5358 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5359 udelay(50); 5360 } 5361 5362 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5363 bool enable) 5364 { 5365 uint32_t rlc_pg_cntl; 5366 5367 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5368 5369 if (!enable) { 5370 /* RLC_PG_CNTL[23] = 0 (default) 5371 * RLC will wait for handshake acks with SMU 5372 * GFXOFF will be enabled 5373 * RLC_PG_CNTL[23] = 1 5374 * RLC will not issue any message to SMU 5375 * hence no handshake between SMU & RLC 5376 * GFXOFF will be disabled 5377 */ 5378 rlc_pg_cntl |= 0x800000; 5379 } else 5380 rlc_pg_cntl &= ~0x800000; 5381 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5382 } 5383 5384 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5385 { 5386 /* TODO: enable rlc & smu handshake until smu 5387 * and gfxoff feature works as expected */ 5388 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5389 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5390 5391 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5392 udelay(50); 5393 } 5394 5395 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5396 { 5397 uint32_t tmp; 5398 5399 /* enable Save Restore Machine */ 5400 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5401 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5402 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5403 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5404 } 5405 5406 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5407 { 5408 const struct rlc_firmware_header_v2_0 *hdr; 5409 const __le32 *fw_data; 5410 unsigned i, fw_size; 5411 5412 if (!adev->gfx.rlc_fw) 5413 return -EINVAL; 5414 5415 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5416 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5417 5418 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5419 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5420 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5421 5422 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5423 RLCG_UCODE_LOADING_START_ADDRESS); 5424 5425 for (i = 0; i < fw_size; i++) 5426 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5427 le32_to_cpup(fw_data++)); 5428 5429 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5430 5431 return 0; 5432 } 5433 5434 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5435 { 5436 int r; 5437 5438 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5439 adev->psp.autoload_supported) { 5440 5441 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5442 if (r) 5443 return r; 5444 5445 gfx_v10_0_init_csb(adev); 5446 5447 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5448 gfx_v10_0_rlc_enable_srm(adev); 5449 } else { 5450 if (amdgpu_sriov_vf(adev)) { 5451 gfx_v10_0_init_csb(adev); 5452 return 0; 5453 } 5454 5455 adev->gfx.rlc.funcs->stop(adev); 5456 5457 /* disable CG */ 5458 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5459 5460 /* disable PG */ 5461 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5462 5463 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5464 /* legacy rlc firmware loading */ 5465 r = gfx_v10_0_rlc_load_microcode(adev); 5466 if (r) 5467 return r; 5468 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5469 /* rlc backdoor autoload firmware */ 5470 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5471 if (r) 5472 return r; 5473 } 5474 5475 gfx_v10_0_init_csb(adev); 5476 5477 adev->gfx.rlc.funcs->start(adev); 5478 5479 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5480 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5481 if (r) 5482 return r; 5483 } 5484 } 5485 return 0; 5486 } 5487 5488 static struct { 5489 FIRMWARE_ID id; 5490 unsigned int offset; 5491 unsigned int size; 5492 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5493 5494 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5495 { 5496 int ret; 5497 RLC_TABLE_OF_CONTENT *rlc_toc; 5498 5499 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5500 AMDGPU_GEM_DOMAIN_GTT, 5501 &adev->gfx.rlc.rlc_toc_bo, 5502 &adev->gfx.rlc.rlc_toc_gpu_addr, 5503 (void **)&adev->gfx.rlc.rlc_toc_buf); 5504 if (ret) { 5505 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5506 return ret; 5507 } 5508 5509 /* Copy toc from psp sos fw to rlc toc buffer */ 5510 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5511 5512 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5513 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5514 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5515 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5516 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5517 /* Offset needs 4KB alignment */ 5518 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5519 } 5520 5521 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5522 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5523 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5524 5525 rlc_toc++; 5526 } 5527 5528 return 0; 5529 } 5530 5531 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5532 { 5533 uint32_t total_size = 0; 5534 FIRMWARE_ID id; 5535 int ret; 5536 5537 ret = gfx_v10_0_parse_rlc_toc(adev); 5538 if (ret) { 5539 dev_err(adev->dev, "failed to parse rlc toc\n"); 5540 return 0; 5541 } 5542 5543 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5544 total_size += rlc_autoload_info[id].size; 5545 5546 /* In case the offset in rlc toc ucode is aligned */ 5547 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5548 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5549 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5550 5551 return total_size; 5552 } 5553 5554 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5555 { 5556 int r; 5557 uint32_t total_size; 5558 5559 total_size = gfx_v10_0_calc_toc_total_size(adev); 5560 5561 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5562 AMDGPU_GEM_DOMAIN_GTT, 5563 &adev->gfx.rlc.rlc_autoload_bo, 5564 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5565 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5566 if (r) { 5567 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5568 return r; 5569 } 5570 5571 return 0; 5572 } 5573 5574 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5575 { 5576 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5577 &adev->gfx.rlc.rlc_toc_gpu_addr, 5578 (void **)&adev->gfx.rlc.rlc_toc_buf); 5579 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5580 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5581 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5582 } 5583 5584 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5585 FIRMWARE_ID id, 5586 const void *fw_data, 5587 uint32_t fw_size) 5588 { 5589 uint32_t toc_offset; 5590 uint32_t toc_fw_size; 5591 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5592 5593 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5594 return; 5595 5596 toc_offset = rlc_autoload_info[id].offset; 5597 toc_fw_size = rlc_autoload_info[id].size; 5598 5599 if (fw_size == 0) 5600 fw_size = toc_fw_size; 5601 5602 if (fw_size > toc_fw_size) 5603 fw_size = toc_fw_size; 5604 5605 memcpy(ptr + toc_offset, fw_data, fw_size); 5606 5607 if (fw_size < toc_fw_size) 5608 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5609 } 5610 5611 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5612 { 5613 void *data; 5614 uint32_t size; 5615 5616 data = adev->gfx.rlc.rlc_toc_buf; 5617 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5618 5619 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5620 FIRMWARE_ID_RLC_TOC, 5621 data, size); 5622 } 5623 5624 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5625 { 5626 const __le32 *fw_data; 5627 uint32_t fw_size; 5628 const struct gfx_firmware_header_v1_0 *cp_hdr; 5629 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5630 5631 /* pfp ucode */ 5632 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5633 adev->gfx.pfp_fw->data; 5634 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5635 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5636 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5637 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5638 FIRMWARE_ID_CP_PFP, 5639 fw_data, fw_size); 5640 5641 /* ce ucode */ 5642 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5643 adev->gfx.ce_fw->data; 5644 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5645 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5646 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5647 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5648 FIRMWARE_ID_CP_CE, 5649 fw_data, fw_size); 5650 5651 /* me ucode */ 5652 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5653 adev->gfx.me_fw->data; 5654 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5655 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5656 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5657 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5658 FIRMWARE_ID_CP_ME, 5659 fw_data, fw_size); 5660 5661 /* rlc ucode */ 5662 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5663 adev->gfx.rlc_fw->data; 5664 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5665 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5666 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5667 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5668 FIRMWARE_ID_RLC_G_UCODE, 5669 fw_data, fw_size); 5670 5671 /* mec1 ucode */ 5672 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5673 adev->gfx.mec_fw->data; 5674 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5675 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5676 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5677 cp_hdr->jt_size * 4; 5678 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5679 FIRMWARE_ID_CP_MEC, 5680 fw_data, fw_size); 5681 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5682 } 5683 5684 /* Temporarily put sdma part here */ 5685 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5686 { 5687 const __le32 *fw_data; 5688 uint32_t fw_size; 5689 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5690 int i; 5691 5692 for (i = 0; i < adev->sdma.num_instances; i++) { 5693 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5694 adev->sdma.instance[i].fw->data; 5695 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5696 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5697 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5698 5699 if (i == 0) { 5700 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5701 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5702 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5703 FIRMWARE_ID_SDMA0_JT, 5704 (uint32_t *)fw_data + 5705 sdma_hdr->jt_offset, 5706 sdma_hdr->jt_size * 4); 5707 } else if (i == 1) { 5708 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5709 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5710 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5711 FIRMWARE_ID_SDMA1_JT, 5712 (uint32_t *)fw_data + 5713 sdma_hdr->jt_offset, 5714 sdma_hdr->jt_size * 4); 5715 } 5716 } 5717 } 5718 5719 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5720 { 5721 uint32_t rlc_g_offset, rlc_g_size, tmp; 5722 uint64_t gpu_addr; 5723 5724 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5725 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5726 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5727 5728 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5729 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5730 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5731 5732 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5733 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5734 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5735 5736 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5737 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5738 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5739 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5740 return -EINVAL; 5741 } 5742 5743 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5744 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5745 DRM_ERROR("RLC ROM should halt itself\n"); 5746 return -EINVAL; 5747 } 5748 5749 return 0; 5750 } 5751 5752 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5753 { 5754 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5755 uint32_t tmp; 5756 int i; 5757 uint64_t addr; 5758 5759 /* Trigger an invalidation of the L1 instruction caches */ 5760 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5761 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5762 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5763 5764 /* Wait for invalidation complete */ 5765 for (i = 0; i < usec_timeout; i++) { 5766 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5767 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5768 INVALIDATE_CACHE_COMPLETE)) 5769 break; 5770 udelay(1); 5771 } 5772 5773 if (i >= usec_timeout) { 5774 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5775 return -EINVAL; 5776 } 5777 5778 /* Program me ucode address into intruction cache address register */ 5779 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5780 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5781 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5782 lower_32_bits(addr) & 0xFFFFF000); 5783 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5784 upper_32_bits(addr)); 5785 5786 return 0; 5787 } 5788 5789 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5790 { 5791 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5792 uint32_t tmp; 5793 int i; 5794 uint64_t addr; 5795 5796 /* Trigger an invalidation of the L1 instruction caches */ 5797 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5798 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5799 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5800 5801 /* Wait for invalidation complete */ 5802 for (i = 0; i < usec_timeout; i++) { 5803 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5804 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5805 INVALIDATE_CACHE_COMPLETE)) 5806 break; 5807 udelay(1); 5808 } 5809 5810 if (i >= usec_timeout) { 5811 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5812 return -EINVAL; 5813 } 5814 5815 /* Program ce ucode address into intruction cache address register */ 5816 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5817 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5818 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5819 lower_32_bits(addr) & 0xFFFFF000); 5820 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5821 upper_32_bits(addr)); 5822 5823 return 0; 5824 } 5825 5826 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5827 { 5828 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5829 uint32_t tmp; 5830 int i; 5831 uint64_t addr; 5832 5833 /* Trigger an invalidation of the L1 instruction caches */ 5834 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5835 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5836 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5837 5838 /* Wait for invalidation complete */ 5839 for (i = 0; i < usec_timeout; i++) { 5840 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5841 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5842 INVALIDATE_CACHE_COMPLETE)) 5843 break; 5844 udelay(1); 5845 } 5846 5847 if (i >= usec_timeout) { 5848 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5849 return -EINVAL; 5850 } 5851 5852 /* Program pfp ucode address into intruction cache address register */ 5853 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5854 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5855 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5856 lower_32_bits(addr) & 0xFFFFF000); 5857 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5858 upper_32_bits(addr)); 5859 5860 return 0; 5861 } 5862 5863 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5864 { 5865 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5866 uint32_t tmp; 5867 int i; 5868 uint64_t addr; 5869 5870 /* Trigger an invalidation of the L1 instruction caches */ 5871 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5872 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5873 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5874 5875 /* Wait for invalidation complete */ 5876 for (i = 0; i < usec_timeout; i++) { 5877 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5878 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5879 INVALIDATE_CACHE_COMPLETE)) 5880 break; 5881 udelay(1); 5882 } 5883 5884 if (i >= usec_timeout) { 5885 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5886 return -EINVAL; 5887 } 5888 5889 /* Program mec1 ucode address into intruction cache address register */ 5890 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5891 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5892 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5893 lower_32_bits(addr) & 0xFFFFF000); 5894 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5895 upper_32_bits(addr)); 5896 5897 return 0; 5898 } 5899 5900 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5901 { 5902 uint32_t cp_status; 5903 uint32_t bootload_status; 5904 int i, r; 5905 5906 for (i = 0; i < adev->usec_timeout; i++) { 5907 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5908 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5909 if ((cp_status == 0) && 5910 (REG_GET_FIELD(bootload_status, 5911 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5912 break; 5913 } 5914 udelay(1); 5915 } 5916 5917 if (i >= adev->usec_timeout) { 5918 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5919 return -ETIMEDOUT; 5920 } 5921 5922 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5923 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5924 if (r) 5925 return r; 5926 5927 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5928 if (r) 5929 return r; 5930 5931 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5932 if (r) 5933 return r; 5934 5935 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5936 if (r) 5937 return r; 5938 } 5939 5940 return 0; 5941 } 5942 5943 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5944 { 5945 int i; 5946 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5947 5948 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5949 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5950 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5951 5952 if (adev->asic_type == CHIP_NAVI12) { 5953 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5954 } else { 5955 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5956 } 5957 5958 for (i = 0; i < adev->usec_timeout; i++) { 5959 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5960 break; 5961 udelay(1); 5962 } 5963 5964 if (i >= adev->usec_timeout) 5965 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5966 5967 return 0; 5968 } 5969 5970 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5971 { 5972 int r; 5973 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5974 const __le32 *fw_data; 5975 unsigned i, fw_size; 5976 uint32_t tmp; 5977 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5978 5979 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5980 adev->gfx.pfp_fw->data; 5981 5982 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5983 5984 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5985 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5986 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5987 5988 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5989 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5990 &adev->gfx.pfp.pfp_fw_obj, 5991 &adev->gfx.pfp.pfp_fw_gpu_addr, 5992 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5993 if (r) { 5994 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5995 gfx_v10_0_pfp_fini(adev); 5996 return r; 5997 } 5998 5999 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6000 6001 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6002 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6003 6004 /* Trigger an invalidation of the L1 instruction caches */ 6005 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6006 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6007 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6008 6009 /* Wait for invalidation complete */ 6010 for (i = 0; i < usec_timeout; i++) { 6011 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6012 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6013 INVALIDATE_CACHE_COMPLETE)) 6014 break; 6015 udelay(1); 6016 } 6017 6018 if (i >= usec_timeout) { 6019 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6020 return -EINVAL; 6021 } 6022 6023 if (amdgpu_emu_mode == 1) 6024 adev->hdp.funcs->flush_hdp(adev, NULL); 6025 6026 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6027 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6028 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6029 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6030 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6031 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6032 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6033 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6034 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6035 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6036 6037 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6038 6039 for (i = 0; i < pfp_hdr->jt_size; i++) 6040 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6041 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6042 6043 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6044 6045 return 0; 6046 } 6047 6048 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6049 { 6050 int r; 6051 const struct gfx_firmware_header_v1_0 *ce_hdr; 6052 const __le32 *fw_data; 6053 unsigned i, fw_size; 6054 uint32_t tmp; 6055 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6056 6057 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6058 adev->gfx.ce_fw->data; 6059 6060 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6061 6062 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6063 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6064 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6065 6066 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6067 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6068 &adev->gfx.ce.ce_fw_obj, 6069 &adev->gfx.ce.ce_fw_gpu_addr, 6070 (void **)&adev->gfx.ce.ce_fw_ptr); 6071 if (r) { 6072 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6073 gfx_v10_0_ce_fini(adev); 6074 return r; 6075 } 6076 6077 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6078 6079 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6080 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6081 6082 /* Trigger an invalidation of the L1 instruction caches */ 6083 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6084 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6085 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6086 6087 /* Wait for invalidation complete */ 6088 for (i = 0; i < usec_timeout; i++) { 6089 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6090 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6091 INVALIDATE_CACHE_COMPLETE)) 6092 break; 6093 udelay(1); 6094 } 6095 6096 if (i >= usec_timeout) { 6097 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6098 return -EINVAL; 6099 } 6100 6101 if (amdgpu_emu_mode == 1) 6102 adev->hdp.funcs->flush_hdp(adev, NULL); 6103 6104 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6105 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6106 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6107 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6108 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6109 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6110 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6111 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6112 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6113 6114 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6115 6116 for (i = 0; i < ce_hdr->jt_size; i++) 6117 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6118 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6119 6120 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6121 6122 return 0; 6123 } 6124 6125 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6126 { 6127 int r; 6128 const struct gfx_firmware_header_v1_0 *me_hdr; 6129 const __le32 *fw_data; 6130 unsigned i, fw_size; 6131 uint32_t tmp; 6132 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6133 6134 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6135 adev->gfx.me_fw->data; 6136 6137 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6138 6139 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6140 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6141 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6142 6143 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6144 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6145 &adev->gfx.me.me_fw_obj, 6146 &adev->gfx.me.me_fw_gpu_addr, 6147 (void **)&adev->gfx.me.me_fw_ptr); 6148 if (r) { 6149 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6150 gfx_v10_0_me_fini(adev); 6151 return r; 6152 } 6153 6154 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6155 6156 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6157 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6158 6159 /* Trigger an invalidation of the L1 instruction caches */ 6160 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6161 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6162 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6163 6164 /* Wait for invalidation complete */ 6165 for (i = 0; i < usec_timeout; i++) { 6166 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6167 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6168 INVALIDATE_CACHE_COMPLETE)) 6169 break; 6170 udelay(1); 6171 } 6172 6173 if (i >= usec_timeout) { 6174 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6175 return -EINVAL; 6176 } 6177 6178 if (amdgpu_emu_mode == 1) 6179 adev->hdp.funcs->flush_hdp(adev, NULL); 6180 6181 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6182 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6183 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6184 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6185 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6186 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6187 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6188 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6189 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6190 6191 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6192 6193 for (i = 0; i < me_hdr->jt_size; i++) 6194 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6195 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6196 6197 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6198 6199 return 0; 6200 } 6201 6202 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6203 { 6204 int r; 6205 6206 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6207 return -EINVAL; 6208 6209 gfx_v10_0_cp_gfx_enable(adev, false); 6210 6211 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6212 if (r) { 6213 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6214 return r; 6215 } 6216 6217 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6218 if (r) { 6219 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6220 return r; 6221 } 6222 6223 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6224 if (r) { 6225 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6226 return r; 6227 } 6228 6229 return 0; 6230 } 6231 6232 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6233 { 6234 struct amdgpu_ring *ring; 6235 const struct cs_section_def *sect = NULL; 6236 const struct cs_extent_def *ext = NULL; 6237 int r, i; 6238 int ctx_reg_offset; 6239 6240 /* init the CP */ 6241 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6242 adev->gfx.config.max_hw_contexts - 1); 6243 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6244 6245 gfx_v10_0_cp_gfx_enable(adev, true); 6246 6247 ring = &adev->gfx.gfx_ring[0]; 6248 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6249 if (r) { 6250 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6251 return r; 6252 } 6253 6254 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6255 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6256 6257 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6258 amdgpu_ring_write(ring, 0x80000000); 6259 amdgpu_ring_write(ring, 0x80000000); 6260 6261 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6262 for (ext = sect->section; ext->extent != NULL; ++ext) { 6263 if (sect->id == SECT_CONTEXT) { 6264 amdgpu_ring_write(ring, 6265 PACKET3(PACKET3_SET_CONTEXT_REG, 6266 ext->reg_count)); 6267 amdgpu_ring_write(ring, ext->reg_index - 6268 PACKET3_SET_CONTEXT_REG_START); 6269 for (i = 0; i < ext->reg_count; i++) 6270 amdgpu_ring_write(ring, ext->extent[i]); 6271 } 6272 } 6273 } 6274 6275 ctx_reg_offset = 6276 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6277 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6278 amdgpu_ring_write(ring, ctx_reg_offset); 6279 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6280 6281 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6282 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6283 6284 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6285 amdgpu_ring_write(ring, 0); 6286 6287 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6288 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6289 amdgpu_ring_write(ring, 0x8000); 6290 amdgpu_ring_write(ring, 0x8000); 6291 6292 amdgpu_ring_commit(ring); 6293 6294 /* submit cs packet to copy state 0 to next available state */ 6295 if (adev->gfx.num_gfx_rings > 1) { 6296 /* maximum supported gfx ring is 2 */ 6297 ring = &adev->gfx.gfx_ring[1]; 6298 r = amdgpu_ring_alloc(ring, 2); 6299 if (r) { 6300 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6301 return r; 6302 } 6303 6304 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6305 amdgpu_ring_write(ring, 0); 6306 6307 amdgpu_ring_commit(ring); 6308 } 6309 return 0; 6310 } 6311 6312 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6313 CP_PIPE_ID pipe) 6314 { 6315 u32 tmp; 6316 6317 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6318 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6319 6320 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6321 } 6322 6323 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6324 struct amdgpu_ring *ring) 6325 { 6326 u32 tmp; 6327 6328 if (!amdgpu_async_gfx_ring) { 6329 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6330 if (ring->use_doorbell) { 6331 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6332 DOORBELL_OFFSET, ring->doorbell_index); 6333 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6334 DOORBELL_EN, 1); 6335 } else { 6336 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6337 DOORBELL_EN, 0); 6338 } 6339 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6340 } 6341 switch (adev->asic_type) { 6342 case CHIP_SIENNA_CICHLID: 6343 case CHIP_NAVY_FLOUNDER: 6344 case CHIP_VANGOGH: 6345 case CHIP_DIMGREY_CAVEFISH: 6346 case CHIP_BEIGE_GOBY: 6347 case CHIP_YELLOW_CARP: 6348 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6349 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6350 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6351 6352 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6353 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6354 break; 6355 default: 6356 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6357 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6358 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6359 6360 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6361 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6362 break; 6363 } 6364 } 6365 6366 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6367 { 6368 struct amdgpu_ring *ring; 6369 u32 tmp; 6370 u32 rb_bufsz; 6371 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6372 u32 i; 6373 6374 /* Set the write pointer delay */ 6375 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6376 6377 /* set the RB to use vmid 0 */ 6378 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6379 6380 /* Init gfx ring 0 for pipe 0 */ 6381 mutex_lock(&adev->srbm_mutex); 6382 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6383 6384 /* Set ring buffer size */ 6385 ring = &adev->gfx.gfx_ring[0]; 6386 rb_bufsz = order_base_2(ring->ring_size / 8); 6387 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6388 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6389 #ifdef __BIG_ENDIAN 6390 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6391 #endif 6392 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6393 6394 /* Initialize the ring buffer's write pointers */ 6395 ring->wptr = 0; 6396 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6397 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6398 6399 /* set the wb address wether it's enabled or not */ 6400 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6401 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6402 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6403 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6404 6405 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6406 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6407 lower_32_bits(wptr_gpu_addr)); 6408 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6409 upper_32_bits(wptr_gpu_addr)); 6410 6411 mdelay(1); 6412 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6413 6414 rb_addr = ring->gpu_addr >> 8; 6415 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6416 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6417 6418 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6419 6420 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6421 mutex_unlock(&adev->srbm_mutex); 6422 6423 /* Init gfx ring 1 for pipe 1 */ 6424 if (adev->gfx.num_gfx_rings > 1) { 6425 mutex_lock(&adev->srbm_mutex); 6426 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6427 /* maximum supported gfx ring is 2 */ 6428 ring = &adev->gfx.gfx_ring[1]; 6429 rb_bufsz = order_base_2(ring->ring_size / 8); 6430 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6431 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6432 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6433 /* Initialize the ring buffer's write pointers */ 6434 ring->wptr = 0; 6435 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6436 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6437 /* Set the wb address wether it's enabled or not */ 6438 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6439 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6440 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6441 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6442 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6443 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6444 lower_32_bits(wptr_gpu_addr)); 6445 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6446 upper_32_bits(wptr_gpu_addr)); 6447 6448 mdelay(1); 6449 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6450 6451 rb_addr = ring->gpu_addr >> 8; 6452 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6453 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6454 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6455 6456 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6457 mutex_unlock(&adev->srbm_mutex); 6458 } 6459 /* Switch to pipe 0 */ 6460 mutex_lock(&adev->srbm_mutex); 6461 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6462 mutex_unlock(&adev->srbm_mutex); 6463 6464 /* start the ring */ 6465 gfx_v10_0_cp_gfx_start(adev); 6466 6467 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6468 ring = &adev->gfx.gfx_ring[i]; 6469 ring->sched.ready = true; 6470 } 6471 6472 return 0; 6473 } 6474 6475 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6476 { 6477 if (enable) { 6478 switch (adev->asic_type) { 6479 case CHIP_SIENNA_CICHLID: 6480 case CHIP_NAVY_FLOUNDER: 6481 case CHIP_VANGOGH: 6482 case CHIP_DIMGREY_CAVEFISH: 6483 case CHIP_BEIGE_GOBY: 6484 case CHIP_YELLOW_CARP: 6485 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6486 break; 6487 default: 6488 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6489 break; 6490 } 6491 } else { 6492 switch (adev->asic_type) { 6493 case CHIP_SIENNA_CICHLID: 6494 case CHIP_NAVY_FLOUNDER: 6495 case CHIP_VANGOGH: 6496 case CHIP_DIMGREY_CAVEFISH: 6497 case CHIP_BEIGE_GOBY: 6498 case CHIP_YELLOW_CARP: 6499 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6500 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6501 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6502 break; 6503 default: 6504 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6505 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6506 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6507 break; 6508 } 6509 adev->gfx.kiq.ring.sched.ready = false; 6510 } 6511 udelay(50); 6512 } 6513 6514 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6515 { 6516 const struct gfx_firmware_header_v1_0 *mec_hdr; 6517 const __le32 *fw_data; 6518 unsigned i; 6519 u32 tmp; 6520 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6521 6522 if (!adev->gfx.mec_fw) 6523 return -EINVAL; 6524 6525 gfx_v10_0_cp_compute_enable(adev, false); 6526 6527 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6528 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6529 6530 fw_data = (const __le32 *) 6531 (adev->gfx.mec_fw->data + 6532 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6533 6534 /* Trigger an invalidation of the L1 instruction caches */ 6535 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6536 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6537 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6538 6539 /* Wait for invalidation complete */ 6540 for (i = 0; i < usec_timeout; i++) { 6541 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6542 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6543 INVALIDATE_CACHE_COMPLETE)) 6544 break; 6545 udelay(1); 6546 } 6547 6548 if (i >= usec_timeout) { 6549 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6550 return -EINVAL; 6551 } 6552 6553 if (amdgpu_emu_mode == 1) 6554 adev->hdp.funcs->flush_hdp(adev, NULL); 6555 6556 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6557 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6558 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6559 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6560 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6561 6562 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6563 0xFFFFF000); 6564 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6565 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6566 6567 /* MEC1 */ 6568 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6569 6570 for (i = 0; i < mec_hdr->jt_size; i++) 6571 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6572 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6573 6574 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6575 6576 /* 6577 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6578 * different microcode than MEC1. 6579 */ 6580 6581 return 0; 6582 } 6583 6584 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6585 { 6586 uint32_t tmp; 6587 struct amdgpu_device *adev = ring->adev; 6588 6589 /* tell RLC which is KIQ queue */ 6590 switch (adev->asic_type) { 6591 case CHIP_SIENNA_CICHLID: 6592 case CHIP_NAVY_FLOUNDER: 6593 case CHIP_VANGOGH: 6594 case CHIP_DIMGREY_CAVEFISH: 6595 case CHIP_BEIGE_GOBY: 6596 case CHIP_YELLOW_CARP: 6597 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6598 tmp &= 0xffffff00; 6599 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6600 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6601 tmp |= 0x80; 6602 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6603 break; 6604 default: 6605 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6606 tmp &= 0xffffff00; 6607 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6608 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6609 tmp |= 0x80; 6610 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6611 break; 6612 } 6613 } 6614 6615 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6616 { 6617 struct amdgpu_device *adev = ring->adev; 6618 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6619 uint64_t hqd_gpu_addr, wb_gpu_addr; 6620 uint32_t tmp; 6621 uint32_t rb_bufsz; 6622 6623 /* set up gfx hqd wptr */ 6624 mqd->cp_gfx_hqd_wptr = 0; 6625 mqd->cp_gfx_hqd_wptr_hi = 0; 6626 6627 /* set the pointer to the MQD */ 6628 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6629 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6630 6631 /* set up mqd control */ 6632 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6633 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6634 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6635 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6636 mqd->cp_gfx_mqd_control = tmp; 6637 6638 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6639 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6640 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6641 mqd->cp_gfx_hqd_vmid = 0; 6642 6643 /* set up default queue priority level 6644 * 0x0 = low priority, 0x1 = high priority */ 6645 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6646 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6647 mqd->cp_gfx_hqd_queue_priority = tmp; 6648 6649 /* set up time quantum */ 6650 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6651 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6652 mqd->cp_gfx_hqd_quantum = tmp; 6653 6654 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6655 hqd_gpu_addr = ring->gpu_addr >> 8; 6656 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6657 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6658 6659 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6660 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6661 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6662 mqd->cp_gfx_hqd_rptr_addr_hi = 6663 upper_32_bits(wb_gpu_addr) & 0xffff; 6664 6665 /* set up rb_wptr_poll addr */ 6666 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6667 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6668 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6669 6670 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6671 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6672 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6673 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6674 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6675 #ifdef __BIG_ENDIAN 6676 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6677 #endif 6678 mqd->cp_gfx_hqd_cntl = tmp; 6679 6680 /* set up cp_doorbell_control */ 6681 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6682 if (ring->use_doorbell) { 6683 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6684 DOORBELL_OFFSET, ring->doorbell_index); 6685 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6686 DOORBELL_EN, 1); 6687 } else 6688 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6689 DOORBELL_EN, 0); 6690 mqd->cp_rb_doorbell_control = tmp; 6691 6692 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6693 *otherwise the range of the second ring will override the first ring */ 6694 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6695 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6696 6697 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6698 ring->wptr = 0; 6699 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6700 6701 /* active the queue */ 6702 mqd->cp_gfx_hqd_active = 1; 6703 6704 return 0; 6705 } 6706 6707 #ifdef BRING_UP_DEBUG 6708 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6709 { 6710 struct amdgpu_device *adev = ring->adev; 6711 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6712 6713 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6714 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6715 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6716 6717 /* set GFX_MQD_BASE */ 6718 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6719 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6720 6721 /* set GFX_MQD_CONTROL */ 6722 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6723 6724 /* set GFX_HQD_VMID to 0 */ 6725 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6726 6727 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6728 mqd->cp_gfx_hqd_queue_priority); 6729 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6730 6731 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6732 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6733 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6734 6735 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6736 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6737 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6738 6739 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6740 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6741 6742 /* set RB_WPTR_POLL_ADDR */ 6743 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6744 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6745 6746 /* set RB_DOORBELL_CONTROL */ 6747 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6748 6749 /* active the queue */ 6750 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6751 6752 return 0; 6753 } 6754 #endif 6755 6756 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6757 { 6758 struct amdgpu_device *adev = ring->adev; 6759 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6760 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6761 6762 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6763 memset((void *)mqd, 0, sizeof(*mqd)); 6764 mutex_lock(&adev->srbm_mutex); 6765 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6766 gfx_v10_0_gfx_mqd_init(ring); 6767 #ifdef BRING_UP_DEBUG 6768 gfx_v10_0_gfx_queue_init_register(ring); 6769 #endif 6770 nv_grbm_select(adev, 0, 0, 0, 0); 6771 mutex_unlock(&adev->srbm_mutex); 6772 if (adev->gfx.me.mqd_backup[mqd_idx]) 6773 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6774 } else if (amdgpu_in_reset(adev)) { 6775 /* reset mqd with the backup copy */ 6776 if (adev->gfx.me.mqd_backup[mqd_idx]) 6777 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6778 /* reset the ring */ 6779 ring->wptr = 0; 6780 adev->wb.wb[ring->wptr_offs] = 0; 6781 amdgpu_ring_clear_ring(ring); 6782 #ifdef BRING_UP_DEBUG 6783 mutex_lock(&adev->srbm_mutex); 6784 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6785 gfx_v10_0_gfx_queue_init_register(ring); 6786 nv_grbm_select(adev, 0, 0, 0, 0); 6787 mutex_unlock(&adev->srbm_mutex); 6788 #endif 6789 } else { 6790 amdgpu_ring_clear_ring(ring); 6791 } 6792 6793 return 0; 6794 } 6795 6796 #ifndef BRING_UP_DEBUG 6797 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6798 { 6799 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6800 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6801 int r, i; 6802 6803 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6804 return -EINVAL; 6805 6806 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6807 adev->gfx.num_gfx_rings); 6808 if (r) { 6809 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6810 return r; 6811 } 6812 6813 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6814 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6815 6816 return amdgpu_ring_test_helper(kiq_ring); 6817 } 6818 #endif 6819 6820 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6821 { 6822 int r, i; 6823 struct amdgpu_ring *ring; 6824 6825 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6826 ring = &adev->gfx.gfx_ring[i]; 6827 6828 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6829 if (unlikely(r != 0)) 6830 goto done; 6831 6832 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6833 if (!r) { 6834 r = gfx_v10_0_gfx_init_queue(ring); 6835 amdgpu_bo_kunmap(ring->mqd_obj); 6836 ring->mqd_ptr = NULL; 6837 } 6838 amdgpu_bo_unreserve(ring->mqd_obj); 6839 if (r) 6840 goto done; 6841 } 6842 #ifndef BRING_UP_DEBUG 6843 r = gfx_v10_0_kiq_enable_kgq(adev); 6844 if (r) 6845 goto done; 6846 #endif 6847 r = gfx_v10_0_cp_gfx_start(adev); 6848 if (r) 6849 goto done; 6850 6851 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6852 ring = &adev->gfx.gfx_ring[i]; 6853 ring->sched.ready = true; 6854 } 6855 done: 6856 return r; 6857 } 6858 6859 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6860 { 6861 struct amdgpu_device *adev = ring->adev; 6862 6863 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6864 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 6865 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6866 mqd->cp_hqd_queue_priority = 6867 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6868 } 6869 } 6870 } 6871 6872 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6873 { 6874 struct amdgpu_device *adev = ring->adev; 6875 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6876 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6877 uint32_t tmp; 6878 6879 mqd->header = 0xC0310800; 6880 mqd->compute_pipelinestat_enable = 0x00000001; 6881 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6882 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6883 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6884 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6885 mqd->compute_misc_reserved = 0x00000003; 6886 6887 eop_base_addr = ring->eop_gpu_addr >> 8; 6888 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6889 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6890 6891 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6892 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6893 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6894 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6895 6896 mqd->cp_hqd_eop_control = tmp; 6897 6898 /* enable doorbell? */ 6899 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6900 6901 if (ring->use_doorbell) { 6902 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6903 DOORBELL_OFFSET, ring->doorbell_index); 6904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6905 DOORBELL_EN, 1); 6906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6907 DOORBELL_SOURCE, 0); 6908 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6909 DOORBELL_HIT, 0); 6910 } else { 6911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6912 DOORBELL_EN, 0); 6913 } 6914 6915 mqd->cp_hqd_pq_doorbell_control = tmp; 6916 6917 /* disable the queue if it's active */ 6918 ring->wptr = 0; 6919 mqd->cp_hqd_dequeue_request = 0; 6920 mqd->cp_hqd_pq_rptr = 0; 6921 mqd->cp_hqd_pq_wptr_lo = 0; 6922 mqd->cp_hqd_pq_wptr_hi = 0; 6923 6924 /* set the pointer to the MQD */ 6925 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6926 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6927 6928 /* set MQD vmid to 0 */ 6929 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6930 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6931 mqd->cp_mqd_control = tmp; 6932 6933 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6934 hqd_gpu_addr = ring->gpu_addr >> 8; 6935 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6936 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6937 6938 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6939 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6940 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6941 (order_base_2(ring->ring_size / 4) - 1)); 6942 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6943 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6944 #ifdef __BIG_ENDIAN 6945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6946 #endif 6947 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6950 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6951 mqd->cp_hqd_pq_control = tmp; 6952 6953 /* set the wb address whether it's enabled or not */ 6954 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6955 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6956 mqd->cp_hqd_pq_rptr_report_addr_hi = 6957 upper_32_bits(wb_gpu_addr) & 0xffff; 6958 6959 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6960 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6961 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6962 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6963 6964 tmp = 0; 6965 /* enable the doorbell if requested */ 6966 if (ring->use_doorbell) { 6967 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6968 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6969 DOORBELL_OFFSET, ring->doorbell_index); 6970 6971 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6972 DOORBELL_EN, 1); 6973 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6974 DOORBELL_SOURCE, 0); 6975 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6976 DOORBELL_HIT, 0); 6977 } 6978 6979 mqd->cp_hqd_pq_doorbell_control = tmp; 6980 6981 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6982 ring->wptr = 0; 6983 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6984 6985 /* set the vmid for the queue */ 6986 mqd->cp_hqd_vmid = 0; 6987 6988 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6989 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6990 mqd->cp_hqd_persistent_state = tmp; 6991 6992 /* set MIN_IB_AVAIL_SIZE */ 6993 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6994 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6995 mqd->cp_hqd_ib_control = tmp; 6996 6997 /* set static priority for a compute queue/ring */ 6998 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6999 7000 /* map_queues packet doesn't need activate the queue, 7001 * so only kiq need set this field. 7002 */ 7003 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 7004 mqd->cp_hqd_active = 1; 7005 7006 return 0; 7007 } 7008 7009 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 7010 { 7011 struct amdgpu_device *adev = ring->adev; 7012 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7013 int j; 7014 7015 /* inactivate the queue */ 7016 if (amdgpu_sriov_vf(adev)) 7017 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 7018 7019 /* disable wptr polling */ 7020 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 7021 7022 /* write the EOP addr */ 7023 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7024 mqd->cp_hqd_eop_base_addr_lo); 7025 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7026 mqd->cp_hqd_eop_base_addr_hi); 7027 7028 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7029 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7030 mqd->cp_hqd_eop_control); 7031 7032 /* enable doorbell? */ 7033 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7034 mqd->cp_hqd_pq_doorbell_control); 7035 7036 /* disable the queue if it's active */ 7037 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7038 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7039 for (j = 0; j < adev->usec_timeout; j++) { 7040 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7041 break; 7042 udelay(1); 7043 } 7044 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7045 mqd->cp_hqd_dequeue_request); 7046 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7047 mqd->cp_hqd_pq_rptr); 7048 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7049 mqd->cp_hqd_pq_wptr_lo); 7050 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7051 mqd->cp_hqd_pq_wptr_hi); 7052 } 7053 7054 /* set the pointer to the MQD */ 7055 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7056 mqd->cp_mqd_base_addr_lo); 7057 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7058 mqd->cp_mqd_base_addr_hi); 7059 7060 /* set MQD vmid to 0 */ 7061 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7062 mqd->cp_mqd_control); 7063 7064 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7065 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7066 mqd->cp_hqd_pq_base_lo); 7067 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7068 mqd->cp_hqd_pq_base_hi); 7069 7070 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7071 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7072 mqd->cp_hqd_pq_control); 7073 7074 /* set the wb address whether it's enabled or not */ 7075 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7076 mqd->cp_hqd_pq_rptr_report_addr_lo); 7077 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7078 mqd->cp_hqd_pq_rptr_report_addr_hi); 7079 7080 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7081 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7082 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7083 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7084 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7085 7086 /* enable the doorbell if requested */ 7087 if (ring->use_doorbell) { 7088 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7089 (adev->doorbell_index.kiq * 2) << 2); 7090 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7091 (adev->doorbell_index.userqueue_end * 2) << 2); 7092 } 7093 7094 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7095 mqd->cp_hqd_pq_doorbell_control); 7096 7097 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7098 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7099 mqd->cp_hqd_pq_wptr_lo); 7100 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7101 mqd->cp_hqd_pq_wptr_hi); 7102 7103 /* set the vmid for the queue */ 7104 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7105 7106 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7107 mqd->cp_hqd_persistent_state); 7108 7109 /* activate the queue */ 7110 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7111 mqd->cp_hqd_active); 7112 7113 if (ring->use_doorbell) 7114 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7115 7116 return 0; 7117 } 7118 7119 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7120 { 7121 struct amdgpu_device *adev = ring->adev; 7122 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7123 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 7124 7125 gfx_v10_0_kiq_setting(ring); 7126 7127 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7128 /* reset MQD to a clean status */ 7129 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7130 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7131 7132 /* reset ring buffer */ 7133 ring->wptr = 0; 7134 amdgpu_ring_clear_ring(ring); 7135 7136 mutex_lock(&adev->srbm_mutex); 7137 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7138 gfx_v10_0_kiq_init_register(ring); 7139 nv_grbm_select(adev, 0, 0, 0, 0); 7140 mutex_unlock(&adev->srbm_mutex); 7141 } else { 7142 memset((void *)mqd, 0, sizeof(*mqd)); 7143 mutex_lock(&adev->srbm_mutex); 7144 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7145 gfx_v10_0_compute_mqd_init(ring); 7146 gfx_v10_0_kiq_init_register(ring); 7147 nv_grbm_select(adev, 0, 0, 0, 0); 7148 mutex_unlock(&adev->srbm_mutex); 7149 7150 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7151 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7152 } 7153 7154 return 0; 7155 } 7156 7157 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 7158 { 7159 struct amdgpu_device *adev = ring->adev; 7160 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7161 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7162 7163 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 7164 memset((void *)mqd, 0, sizeof(*mqd)); 7165 mutex_lock(&adev->srbm_mutex); 7166 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7167 gfx_v10_0_compute_mqd_init(ring); 7168 nv_grbm_select(adev, 0, 0, 0, 0); 7169 mutex_unlock(&adev->srbm_mutex); 7170 7171 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7172 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7173 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7174 /* reset MQD to a clean status */ 7175 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7176 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7177 7178 /* reset ring buffer */ 7179 ring->wptr = 0; 7180 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 7181 amdgpu_ring_clear_ring(ring); 7182 } else { 7183 amdgpu_ring_clear_ring(ring); 7184 } 7185 7186 return 0; 7187 } 7188 7189 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7190 { 7191 struct amdgpu_ring *ring; 7192 int r; 7193 7194 ring = &adev->gfx.kiq.ring; 7195 7196 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7197 if (unlikely(r != 0)) 7198 return r; 7199 7200 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7201 if (unlikely(r != 0)) 7202 return r; 7203 7204 gfx_v10_0_kiq_init_queue(ring); 7205 amdgpu_bo_kunmap(ring->mqd_obj); 7206 ring->mqd_ptr = NULL; 7207 amdgpu_bo_unreserve(ring->mqd_obj); 7208 ring->sched.ready = true; 7209 return 0; 7210 } 7211 7212 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7213 { 7214 struct amdgpu_ring *ring = NULL; 7215 int r = 0, i; 7216 7217 gfx_v10_0_cp_compute_enable(adev, true); 7218 7219 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7220 ring = &adev->gfx.compute_ring[i]; 7221 7222 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7223 if (unlikely(r != 0)) 7224 goto done; 7225 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7226 if (!r) { 7227 r = gfx_v10_0_kcq_init_queue(ring); 7228 amdgpu_bo_kunmap(ring->mqd_obj); 7229 ring->mqd_ptr = NULL; 7230 } 7231 amdgpu_bo_unreserve(ring->mqd_obj); 7232 if (r) 7233 goto done; 7234 } 7235 7236 r = amdgpu_gfx_enable_kcq(adev); 7237 done: 7238 return r; 7239 } 7240 7241 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7242 { 7243 int r, i; 7244 struct amdgpu_ring *ring; 7245 7246 if (!(adev->flags & AMD_IS_APU)) 7247 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7248 7249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7250 /* legacy firmware loading */ 7251 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7252 if (r) 7253 return r; 7254 7255 r = gfx_v10_0_cp_compute_load_microcode(adev); 7256 if (r) 7257 return r; 7258 } 7259 7260 r = gfx_v10_0_kiq_resume(adev); 7261 if (r) 7262 return r; 7263 7264 r = gfx_v10_0_kcq_resume(adev); 7265 if (r) 7266 return r; 7267 7268 if (!amdgpu_async_gfx_ring) { 7269 r = gfx_v10_0_cp_gfx_resume(adev); 7270 if (r) 7271 return r; 7272 } else { 7273 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7274 if (r) 7275 return r; 7276 } 7277 7278 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7279 ring = &adev->gfx.gfx_ring[i]; 7280 r = amdgpu_ring_test_helper(ring); 7281 if (r) 7282 return r; 7283 } 7284 7285 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7286 ring = &adev->gfx.compute_ring[i]; 7287 r = amdgpu_ring_test_helper(ring); 7288 if (r) 7289 return r; 7290 } 7291 7292 return 0; 7293 } 7294 7295 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7296 { 7297 gfx_v10_0_cp_gfx_enable(adev, enable); 7298 gfx_v10_0_cp_compute_enable(adev, enable); 7299 } 7300 7301 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7302 { 7303 uint32_t data, pattern = 0xDEADBEEF; 7304 7305 /* check if mmVGT_ESGS_RING_SIZE_UMD 7306 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7307 switch (adev->asic_type) { 7308 case CHIP_SIENNA_CICHLID: 7309 case CHIP_NAVY_FLOUNDER: 7310 case CHIP_DIMGREY_CAVEFISH: 7311 case CHIP_BEIGE_GOBY: 7312 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7313 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7314 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7315 7316 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7317 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7318 return true; 7319 } else { 7320 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7321 return false; 7322 } 7323 break; 7324 case CHIP_VANGOGH: 7325 case CHIP_YELLOW_CARP: 7326 return true; 7327 default: 7328 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7329 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7330 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7331 7332 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7333 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7334 return true; 7335 } else { 7336 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7337 return false; 7338 } 7339 break; 7340 } 7341 } 7342 7343 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7344 { 7345 uint32_t data; 7346 7347 if (amdgpu_sriov_vf(adev)) 7348 return; 7349 7350 /* initialize cam_index to 0 7351 * index will auto-inc after each data writting */ 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7353 7354 switch (adev->asic_type) { 7355 case CHIP_SIENNA_CICHLID: 7356 case CHIP_NAVY_FLOUNDER: 7357 case CHIP_VANGOGH: 7358 case CHIP_DIMGREY_CAVEFISH: 7359 case CHIP_BEIGE_GOBY: 7360 case CHIP_YELLOW_CARP: 7361 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7362 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7363 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7364 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7365 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7366 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7367 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7368 7369 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7370 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7371 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7372 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7373 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7374 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7375 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7376 7377 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7378 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7379 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7380 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7381 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7382 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7383 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7384 7385 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7386 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7387 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7388 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7389 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7390 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7391 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7392 7393 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7394 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7395 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7396 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7397 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7398 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7399 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7400 7401 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7402 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7403 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7404 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7405 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7406 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7407 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7408 7409 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7410 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7411 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7412 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7413 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7414 break; 7415 default: 7416 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7417 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7418 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7419 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7420 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7421 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7422 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7423 7424 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7425 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7426 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7427 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7428 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7429 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7430 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7431 7432 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7433 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7434 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7435 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7436 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7437 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7438 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7439 7440 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7441 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7442 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7443 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7444 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7445 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7446 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7447 7448 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7449 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7450 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7451 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7452 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7453 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7454 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7455 7456 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7457 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7458 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7459 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7460 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7461 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7462 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7463 7464 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7465 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7466 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7467 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7468 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7469 break; 7470 } 7471 7472 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7473 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7474 } 7475 7476 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7477 { 7478 uint32_t data; 7479 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7480 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7481 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7482 7483 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7484 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7485 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7486 } 7487 7488 static int gfx_v10_0_hw_init(void *handle) 7489 { 7490 int r; 7491 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7492 7493 if (!amdgpu_emu_mode) 7494 gfx_v10_0_init_golden_registers(adev); 7495 7496 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7497 /** 7498 * For gfx 10, rlc firmware loading relies on smu firmware is 7499 * loaded firstly, so in direct type, it has to load smc ucode 7500 * here before rlc. 7501 */ 7502 if (!(adev->flags & AMD_IS_APU)) { 7503 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7504 if (r) 7505 return r; 7506 } 7507 gfx_v10_0_disable_gpa_mode(adev); 7508 } 7509 7510 /* if GRBM CAM not remapped, set up the remapping */ 7511 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7512 gfx_v10_0_setup_grbm_cam_remapping(adev); 7513 7514 gfx_v10_0_constants_init(adev); 7515 7516 r = gfx_v10_0_rlc_resume(adev); 7517 if (r) 7518 return r; 7519 7520 /* 7521 * init golden registers and rlc resume may override some registers, 7522 * reconfig them here 7523 */ 7524 if (adev->asic_type == CHIP_NAVI10 || 7525 adev->asic_type == CHIP_NAVI14 || 7526 adev->asic_type == CHIP_NAVI12) 7527 gfx_v10_0_tcp_harvest(adev); 7528 7529 r = gfx_v10_0_cp_resume(adev); 7530 if (r) 7531 return r; 7532 7533 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7534 gfx_v10_3_program_pbb_mode(adev); 7535 7536 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7537 gfx_v10_3_set_power_brake_sequence(adev); 7538 7539 return r; 7540 } 7541 7542 #ifndef BRING_UP_DEBUG 7543 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7544 { 7545 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7546 struct amdgpu_ring *kiq_ring = &kiq->ring; 7547 int i; 7548 7549 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7550 return -EINVAL; 7551 7552 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7553 adev->gfx.num_gfx_rings)) 7554 return -ENOMEM; 7555 7556 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7557 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7558 PREEMPT_QUEUES, 0, 0); 7559 7560 return amdgpu_ring_test_helper(kiq_ring); 7561 } 7562 #endif 7563 7564 static int gfx_v10_0_hw_fini(void *handle) 7565 { 7566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7567 int r; 7568 uint32_t tmp; 7569 7570 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7571 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7572 7573 if (!adev->no_hw_access) { 7574 #ifndef BRING_UP_DEBUG 7575 if (amdgpu_async_gfx_ring) { 7576 r = gfx_v10_0_kiq_disable_kgq(adev); 7577 if (r) 7578 DRM_ERROR("KGQ disable failed\n"); 7579 } 7580 #endif 7581 if (amdgpu_gfx_disable_kcq(adev)) 7582 DRM_ERROR("KCQ disable failed\n"); 7583 } 7584 7585 if (amdgpu_sriov_vf(adev)) { 7586 gfx_v10_0_cp_gfx_enable(adev, false); 7587 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7588 if (adev->asic_type >= CHIP_SIENNA_CICHLID) { 7589 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 7590 tmp &= 0xffffff00; 7591 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 7592 } else { 7593 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7594 tmp &= 0xffffff00; 7595 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7596 } 7597 7598 return 0; 7599 } 7600 gfx_v10_0_cp_enable(adev, false); 7601 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7602 7603 return 0; 7604 } 7605 7606 static int gfx_v10_0_suspend(void *handle) 7607 { 7608 return gfx_v10_0_hw_fini(handle); 7609 } 7610 7611 static int gfx_v10_0_resume(void *handle) 7612 { 7613 return gfx_v10_0_hw_init(handle); 7614 } 7615 7616 static bool gfx_v10_0_is_idle(void *handle) 7617 { 7618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7619 7620 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7621 GRBM_STATUS, GUI_ACTIVE)) 7622 return false; 7623 else 7624 return true; 7625 } 7626 7627 static int gfx_v10_0_wait_for_idle(void *handle) 7628 { 7629 unsigned i; 7630 u32 tmp; 7631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7632 7633 for (i = 0; i < adev->usec_timeout; i++) { 7634 /* read MC_STATUS */ 7635 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7636 GRBM_STATUS__GUI_ACTIVE_MASK; 7637 7638 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7639 return 0; 7640 udelay(1); 7641 } 7642 return -ETIMEDOUT; 7643 } 7644 7645 static int gfx_v10_0_soft_reset(void *handle) 7646 { 7647 u32 grbm_soft_reset = 0; 7648 u32 tmp; 7649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7650 7651 /* GRBM_STATUS */ 7652 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7653 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7654 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7655 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7656 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7657 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7658 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7659 GRBM_SOFT_RESET, SOFT_RESET_CP, 7660 1); 7661 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7662 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7663 1); 7664 } 7665 7666 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7667 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7668 GRBM_SOFT_RESET, SOFT_RESET_CP, 7669 1); 7670 } 7671 7672 /* GRBM_STATUS2 */ 7673 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7674 switch (adev->asic_type) { 7675 case CHIP_SIENNA_CICHLID: 7676 case CHIP_NAVY_FLOUNDER: 7677 case CHIP_VANGOGH: 7678 case CHIP_DIMGREY_CAVEFISH: 7679 case CHIP_BEIGE_GOBY: 7680 case CHIP_YELLOW_CARP: 7681 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7682 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7683 GRBM_SOFT_RESET, 7684 SOFT_RESET_RLC, 7685 1); 7686 break; 7687 default: 7688 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7689 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7690 GRBM_SOFT_RESET, 7691 SOFT_RESET_RLC, 7692 1); 7693 break; 7694 } 7695 7696 if (grbm_soft_reset) { 7697 /* stop the rlc */ 7698 gfx_v10_0_rlc_stop(adev); 7699 7700 /* Disable GFX parsing/prefetching */ 7701 gfx_v10_0_cp_gfx_enable(adev, false); 7702 7703 /* Disable MEC parsing/prefetching */ 7704 gfx_v10_0_cp_compute_enable(adev, false); 7705 7706 if (grbm_soft_reset) { 7707 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7708 tmp |= grbm_soft_reset; 7709 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7710 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7711 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7712 7713 udelay(50); 7714 7715 tmp &= ~grbm_soft_reset; 7716 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7717 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7718 } 7719 7720 /* Wait a little for things to settle down */ 7721 udelay(50); 7722 } 7723 return 0; 7724 } 7725 7726 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7727 { 7728 uint64_t clock, clock_lo, clock_hi, hi_check; 7729 7730 switch (adev->asic_type) { 7731 case CHIP_VANGOGH: 7732 case CHIP_YELLOW_CARP: 7733 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | 7734 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); 7735 break; 7736 default: 7737 preempt_disable(); 7738 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7739 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7740 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7741 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7742 * roughly every 42 seconds. 7743 */ 7744 if (hi_check != clock_hi) { 7745 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7746 clock_hi = hi_check; 7747 } 7748 preempt_enable(); 7749 clock = clock_lo | (clock_hi << 32ULL); 7750 break; 7751 } 7752 return clock; 7753 } 7754 7755 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7756 uint32_t vmid, 7757 uint32_t gds_base, uint32_t gds_size, 7758 uint32_t gws_base, uint32_t gws_size, 7759 uint32_t oa_base, uint32_t oa_size) 7760 { 7761 struct amdgpu_device *adev = ring->adev; 7762 7763 /* GDS Base */ 7764 gfx_v10_0_write_data_to_reg(ring, 0, false, 7765 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7766 gds_base); 7767 7768 /* GDS Size */ 7769 gfx_v10_0_write_data_to_reg(ring, 0, false, 7770 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7771 gds_size); 7772 7773 /* GWS */ 7774 gfx_v10_0_write_data_to_reg(ring, 0, false, 7775 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7776 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7777 7778 /* OA */ 7779 gfx_v10_0_write_data_to_reg(ring, 0, false, 7780 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7781 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7782 } 7783 7784 static int gfx_v10_0_early_init(void *handle) 7785 { 7786 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7787 7788 switch (adev->asic_type) { 7789 case CHIP_NAVI10: 7790 case CHIP_NAVI14: 7791 case CHIP_NAVI12: 7792 case CHIP_CYAN_SKILLFISH: 7793 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7794 break; 7795 case CHIP_SIENNA_CICHLID: 7796 case CHIP_NAVY_FLOUNDER: 7797 case CHIP_VANGOGH: 7798 case CHIP_DIMGREY_CAVEFISH: 7799 case CHIP_BEIGE_GOBY: 7800 case CHIP_YELLOW_CARP: 7801 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7802 break; 7803 default: 7804 break; 7805 } 7806 7807 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7808 AMDGPU_MAX_COMPUTE_RINGS); 7809 7810 gfx_v10_0_set_kiq_pm4_funcs(adev); 7811 gfx_v10_0_set_ring_funcs(adev); 7812 gfx_v10_0_set_irq_funcs(adev); 7813 gfx_v10_0_set_gds_init(adev); 7814 gfx_v10_0_set_rlc_funcs(adev); 7815 7816 return 0; 7817 } 7818 7819 static int gfx_v10_0_late_init(void *handle) 7820 { 7821 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7822 int r; 7823 7824 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7825 if (r) 7826 return r; 7827 7828 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7829 if (r) 7830 return r; 7831 7832 return 0; 7833 } 7834 7835 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7836 { 7837 uint32_t rlc_cntl; 7838 7839 /* if RLC is not enabled, do nothing */ 7840 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7841 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7842 } 7843 7844 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7845 { 7846 uint32_t data; 7847 unsigned i; 7848 7849 data = RLC_SAFE_MODE__CMD_MASK; 7850 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7851 7852 switch (adev->asic_type) { 7853 case CHIP_SIENNA_CICHLID: 7854 case CHIP_NAVY_FLOUNDER: 7855 case CHIP_VANGOGH: 7856 case CHIP_DIMGREY_CAVEFISH: 7857 case CHIP_BEIGE_GOBY: 7858 case CHIP_YELLOW_CARP: 7859 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7860 7861 /* wait for RLC_SAFE_MODE */ 7862 for (i = 0; i < adev->usec_timeout; i++) { 7863 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7864 RLC_SAFE_MODE, CMD)) 7865 break; 7866 udelay(1); 7867 } 7868 break; 7869 default: 7870 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7871 7872 /* wait for RLC_SAFE_MODE */ 7873 for (i = 0; i < adev->usec_timeout; i++) { 7874 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7875 RLC_SAFE_MODE, CMD)) 7876 break; 7877 udelay(1); 7878 } 7879 break; 7880 } 7881 } 7882 7883 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7884 { 7885 uint32_t data; 7886 7887 data = RLC_SAFE_MODE__CMD_MASK; 7888 switch (adev->asic_type) { 7889 case CHIP_SIENNA_CICHLID: 7890 case CHIP_NAVY_FLOUNDER: 7891 case CHIP_VANGOGH: 7892 case CHIP_DIMGREY_CAVEFISH: 7893 case CHIP_BEIGE_GOBY: 7894 case CHIP_YELLOW_CARP: 7895 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7896 break; 7897 default: 7898 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7899 break; 7900 } 7901 } 7902 7903 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7904 bool enable) 7905 { 7906 uint32_t data, def; 7907 7908 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7909 return; 7910 7911 /* It is disabled by HW by default */ 7912 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7913 /* 0 - Disable some blocks' MGCG */ 7914 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7915 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7916 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7917 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7918 7919 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7920 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7921 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7922 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7923 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7924 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7925 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7926 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7927 7928 if (def != data) 7929 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7930 7931 /* MGLS is a global flag to control all MGLS in GFX */ 7932 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7933 /* 2 - RLC memory Light sleep */ 7934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7935 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7936 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7937 if (def != data) 7938 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7939 } 7940 /* 3 - CP memory Light sleep */ 7941 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7942 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7943 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7944 if (def != data) 7945 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7946 } 7947 } 7948 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7949 /* 1 - MGCG_OVERRIDE */ 7950 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7951 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7952 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7953 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7954 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7955 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7956 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7957 if (def != data) 7958 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7959 7960 /* 2 - disable MGLS in CP */ 7961 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7962 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7963 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7964 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7965 } 7966 7967 /* 3 - disable MGLS in RLC */ 7968 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7969 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7970 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7971 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7972 } 7973 7974 } 7975 } 7976 7977 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7978 bool enable) 7979 { 7980 uint32_t data, def; 7981 7982 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7983 return; 7984 7985 /* Enable 3D CGCG/CGLS */ 7986 if (enable) { 7987 /* write cmd to clear cgcg/cgls ov */ 7988 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7989 7990 /* unset CGCG override */ 7991 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7992 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7993 7994 /* update CGCG and CGLS override bits */ 7995 if (def != data) 7996 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7997 7998 /* enable 3Dcgcg FSM(0x0000363f) */ 7999 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8000 data = 0; 8001 8002 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8003 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8004 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8005 8006 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8007 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8008 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8009 8010 if (def != data) 8011 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8012 8013 /* set IDLE_POLL_COUNT(0x00900100) */ 8014 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8015 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8016 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8017 if (def != data) 8018 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8019 } else { 8020 /* Disable CGCG/CGLS */ 8021 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8022 8023 /* disable cgcg, cgls should be disabled */ 8024 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8025 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8026 8027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8028 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8029 8030 /* disable cgcg and cgls in FSM */ 8031 if (def != data) 8032 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8033 } 8034 } 8035 8036 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8037 bool enable) 8038 { 8039 uint32_t def, data; 8040 8041 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8042 return; 8043 8044 if (enable) { 8045 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8046 8047 /* unset CGCG override */ 8048 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8049 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8050 8051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8052 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8053 8054 /* update CGCG and CGLS override bits */ 8055 if (def != data) 8056 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8057 8058 /* enable cgcg FSM(0x0000363F) */ 8059 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8060 data = 0; 8061 8062 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8063 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8064 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8065 8066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8067 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8068 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8069 8070 if (def != data) 8071 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8072 8073 /* set IDLE_POLL_COUNT(0x00900100) */ 8074 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8075 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8076 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8077 if (def != data) 8078 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8079 } else { 8080 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8081 8082 /* reset CGCG/CGLS bits */ 8083 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8084 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8085 8086 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8087 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8088 8089 /* disable cgcg and cgls in FSM */ 8090 if (def != data) 8091 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8092 } 8093 } 8094 8095 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8096 bool enable) 8097 { 8098 uint32_t def, data; 8099 8100 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8101 return; 8102 8103 if (enable) { 8104 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8105 /* unset FGCG override */ 8106 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8107 /* update FGCG override bits */ 8108 if (def != data) 8109 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8110 8111 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8112 /* unset RLC SRAM CLK GATER override */ 8113 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8114 /* update RLC SRAM CLK GATER override bits */ 8115 if (def != data) 8116 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8117 } else { 8118 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8119 /* reset FGCG bits */ 8120 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8121 /* disable FGCG*/ 8122 if (def != data) 8123 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8124 8125 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8126 /* reset RLC SRAM CLK GATER bits */ 8127 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8128 /* disable RLC SRAM CLK*/ 8129 if (def != data) 8130 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8131 } 8132 } 8133 8134 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8135 { 8136 uint32_t reg_data = 0; 8137 uint32_t reg_idx = 0; 8138 uint32_t i; 8139 8140 const uint32_t tcp_ctrl_regs[] = { 8141 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8142 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8143 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8144 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8145 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8146 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8147 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8148 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8149 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8150 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8151 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8152 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8153 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8154 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8155 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8156 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8157 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8158 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8159 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8160 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8161 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8162 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8163 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8164 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8165 }; 8166 8167 const uint32_t tcp_ctrl_regs_nv12[] = { 8168 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8169 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8170 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8171 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8172 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8173 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8174 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8175 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8176 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8177 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8178 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8179 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8180 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8181 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8182 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8183 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8184 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8185 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8186 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8187 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8188 }; 8189 8190 const uint32_t sm_ctlr_regs[] = { 8191 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8192 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8193 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8194 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8195 }; 8196 8197 if (adev->asic_type == CHIP_NAVI12) { 8198 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8199 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8200 tcp_ctrl_regs_nv12[i]; 8201 reg_data = RREG32(reg_idx); 8202 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8203 WREG32(reg_idx, reg_data); 8204 } 8205 } else { 8206 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8207 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8208 tcp_ctrl_regs[i]; 8209 reg_data = RREG32(reg_idx); 8210 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8211 WREG32(reg_idx, reg_data); 8212 } 8213 } 8214 8215 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8216 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8217 sm_ctlr_regs[i]; 8218 reg_data = RREG32(reg_idx); 8219 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8220 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8221 WREG32(reg_idx, reg_data); 8222 } 8223 } 8224 8225 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8226 bool enable) 8227 { 8228 amdgpu_gfx_rlc_enter_safe_mode(adev); 8229 8230 if (enable) { 8231 /* enable FGCG firstly*/ 8232 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8233 /* CGCG/CGLS should be enabled after MGCG/MGLS 8234 * === MGCG + MGLS === 8235 */ 8236 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8237 /* === CGCG /CGLS for GFX 3D Only === */ 8238 gfx_v10_0_update_3d_clock_gating(adev, enable); 8239 /* === CGCG + CGLS === */ 8240 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8241 8242 if ((adev->asic_type >= CHIP_NAVI10) && 8243 (adev->asic_type <= CHIP_NAVI12)) 8244 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8245 } else { 8246 /* CGCG/CGLS should be disabled before MGCG/MGLS 8247 * === CGCG + CGLS === 8248 */ 8249 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8250 /* === CGCG /CGLS for GFX 3D Only === */ 8251 gfx_v10_0_update_3d_clock_gating(adev, enable); 8252 /* === MGCG + MGLS === */ 8253 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8254 /* disable fgcg at last*/ 8255 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8256 } 8257 8258 if (adev->cg_flags & 8259 (AMD_CG_SUPPORT_GFX_MGCG | 8260 AMD_CG_SUPPORT_GFX_CGLS | 8261 AMD_CG_SUPPORT_GFX_CGCG | 8262 AMD_CG_SUPPORT_GFX_3D_CGCG | 8263 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8264 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8265 8266 amdgpu_gfx_rlc_exit_safe_mode(adev); 8267 8268 return 0; 8269 } 8270 8271 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 8272 { 8273 u32 reg, data; 8274 /* not for *_SOC15 */ 8275 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8276 if (amdgpu_sriov_is_pp_one_vf(adev)) 8277 data = RREG32_NO_KIQ(reg); 8278 else 8279 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 8280 8281 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8282 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8283 8284 if (amdgpu_sriov_is_pp_one_vf(adev)) 8285 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8286 else 8287 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8288 } 8289 8290 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8291 uint32_t offset, 8292 struct soc15_reg_rlcg *entries, int arr_size) 8293 { 8294 int i; 8295 uint32_t reg; 8296 8297 if (!entries) 8298 return false; 8299 8300 for (i = 0; i < arr_size; i++) { 8301 const struct soc15_reg_rlcg *entry; 8302 8303 entry = &entries[i]; 8304 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8305 if (offset == reg) 8306 return true; 8307 } 8308 8309 return false; 8310 } 8311 8312 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8313 { 8314 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8315 } 8316 8317 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8318 { 8319 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8320 8321 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8322 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8323 else 8324 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8325 8326 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8327 8328 /* 8329 * CGPG enablement required and the register to program the hysteresis value 8330 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8331 * in refclk count. Note that RLC FW is modified to take 16 bits from 8332 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8333 * 8334 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8335 * of CGPG enablement starting point. 8336 * Power/performance team will optimize it and might give a new value later. 8337 */ 8338 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8339 switch (adev->asic_type) { 8340 case CHIP_VANGOGH: 8341 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8342 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8343 break; 8344 case CHIP_YELLOW_CARP: 8345 data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8346 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8347 break; 8348 default: 8349 break; 8350 } 8351 } 8352 } 8353 8354 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8355 { 8356 amdgpu_gfx_rlc_enter_safe_mode(adev); 8357 8358 gfx_v10_cntl_power_gating(adev, enable); 8359 8360 amdgpu_gfx_rlc_exit_safe_mode(adev); 8361 } 8362 8363 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8364 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8365 .set_safe_mode = gfx_v10_0_set_safe_mode, 8366 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8367 .init = gfx_v10_0_rlc_init, 8368 .get_csb_size = gfx_v10_0_get_csb_size, 8369 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8370 .resume = gfx_v10_0_rlc_resume, 8371 .stop = gfx_v10_0_rlc_stop, 8372 .reset = gfx_v10_0_rlc_reset, 8373 .start = gfx_v10_0_rlc_start, 8374 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8375 }; 8376 8377 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8378 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8379 .set_safe_mode = gfx_v10_0_set_safe_mode, 8380 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8381 .init = gfx_v10_0_rlc_init, 8382 .get_csb_size = gfx_v10_0_get_csb_size, 8383 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8384 .resume = gfx_v10_0_rlc_resume, 8385 .stop = gfx_v10_0_rlc_stop, 8386 .reset = gfx_v10_0_rlc_reset, 8387 .start = gfx_v10_0_rlc_start, 8388 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8389 .sriov_wreg = gfx_v10_sriov_wreg, 8390 .sriov_rreg = gfx_v10_sriov_rreg, 8391 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8392 }; 8393 8394 static int gfx_v10_0_set_powergating_state(void *handle, 8395 enum amd_powergating_state state) 8396 { 8397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8398 bool enable = (state == AMD_PG_STATE_GATE); 8399 8400 if (amdgpu_sriov_vf(adev)) 8401 return 0; 8402 8403 switch (adev->asic_type) { 8404 case CHIP_NAVI10: 8405 case CHIP_NAVI14: 8406 case CHIP_NAVI12: 8407 case CHIP_SIENNA_CICHLID: 8408 case CHIP_NAVY_FLOUNDER: 8409 case CHIP_DIMGREY_CAVEFISH: 8410 case CHIP_BEIGE_GOBY: 8411 amdgpu_gfx_off_ctrl(adev, enable); 8412 break; 8413 case CHIP_VANGOGH: 8414 case CHIP_YELLOW_CARP: 8415 gfx_v10_cntl_pg(adev, enable); 8416 amdgpu_gfx_off_ctrl(adev, enable); 8417 break; 8418 default: 8419 break; 8420 } 8421 return 0; 8422 } 8423 8424 static int gfx_v10_0_set_clockgating_state(void *handle, 8425 enum amd_clockgating_state state) 8426 { 8427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8428 8429 if (amdgpu_sriov_vf(adev)) 8430 return 0; 8431 8432 switch (adev->asic_type) { 8433 case CHIP_NAVI10: 8434 case CHIP_NAVI14: 8435 case CHIP_NAVI12: 8436 case CHIP_SIENNA_CICHLID: 8437 case CHIP_NAVY_FLOUNDER: 8438 case CHIP_VANGOGH: 8439 case CHIP_DIMGREY_CAVEFISH: 8440 case CHIP_BEIGE_GOBY: 8441 case CHIP_YELLOW_CARP: 8442 gfx_v10_0_update_gfx_clock_gating(adev, 8443 state == AMD_CG_STATE_GATE); 8444 break; 8445 default: 8446 break; 8447 } 8448 return 0; 8449 } 8450 8451 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 8452 { 8453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8454 int data; 8455 8456 /* AMD_CG_SUPPORT_GFX_FGCG */ 8457 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8458 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8459 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8460 8461 /* AMD_CG_SUPPORT_GFX_MGCG */ 8462 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8463 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8464 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8465 8466 /* AMD_CG_SUPPORT_GFX_CGCG */ 8467 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8468 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8469 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8470 8471 /* AMD_CG_SUPPORT_GFX_CGLS */ 8472 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8473 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8474 8475 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8476 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8477 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8478 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8479 8480 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8481 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8482 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8483 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8484 8485 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8486 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8487 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8488 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8489 8490 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8491 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8492 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8493 } 8494 8495 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8496 { 8497 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 8498 } 8499 8500 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8501 { 8502 struct amdgpu_device *adev = ring->adev; 8503 u64 wptr; 8504 8505 /* XXX check if swapping is necessary on BE */ 8506 if (ring->use_doorbell) { 8507 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8508 } else { 8509 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8510 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8511 } 8512 8513 return wptr; 8514 } 8515 8516 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8517 { 8518 struct amdgpu_device *adev = ring->adev; 8519 8520 if (ring->use_doorbell) { 8521 /* XXX check if swapping is necessary on BE */ 8522 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8523 WDOORBELL64(ring->doorbell_index, ring->wptr); 8524 } else { 8525 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8526 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8527 } 8528 } 8529 8530 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8531 { 8532 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8533 } 8534 8535 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8536 { 8537 u64 wptr; 8538 8539 /* XXX check if swapping is necessary on BE */ 8540 if (ring->use_doorbell) 8541 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8542 else 8543 BUG(); 8544 return wptr; 8545 } 8546 8547 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8548 { 8549 struct amdgpu_device *adev = ring->adev; 8550 8551 /* XXX check if swapping is necessary on BE */ 8552 if (ring->use_doorbell) { 8553 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8554 WDOORBELL64(ring->doorbell_index, ring->wptr); 8555 } else { 8556 BUG(); /* only DOORBELL method supported on gfx10 now */ 8557 } 8558 } 8559 8560 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8561 { 8562 struct amdgpu_device *adev = ring->adev; 8563 u32 ref_and_mask, reg_mem_engine; 8564 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8565 8566 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8567 switch (ring->me) { 8568 case 1: 8569 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8570 break; 8571 case 2: 8572 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8573 break; 8574 default: 8575 return; 8576 } 8577 reg_mem_engine = 0; 8578 } else { 8579 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8580 reg_mem_engine = 1; /* pfp */ 8581 } 8582 8583 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8584 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8585 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8586 ref_and_mask, ref_and_mask, 0x20); 8587 } 8588 8589 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8590 struct amdgpu_job *job, 8591 struct amdgpu_ib *ib, 8592 uint32_t flags) 8593 { 8594 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8595 u32 header, control = 0; 8596 8597 if (ib->flags & AMDGPU_IB_FLAG_CE) 8598 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8599 else 8600 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8601 8602 control |= ib->length_dw | (vmid << 24); 8603 8604 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8605 control |= INDIRECT_BUFFER_PRE_ENB(1); 8606 8607 if (flags & AMDGPU_IB_PREEMPTED) 8608 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8609 8610 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8611 gfx_v10_0_ring_emit_de_meta(ring, 8612 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8613 } 8614 8615 amdgpu_ring_write(ring, header); 8616 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8617 amdgpu_ring_write(ring, 8618 #ifdef __BIG_ENDIAN 8619 (2 << 0) | 8620 #endif 8621 lower_32_bits(ib->gpu_addr)); 8622 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8623 amdgpu_ring_write(ring, control); 8624 } 8625 8626 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8627 struct amdgpu_job *job, 8628 struct amdgpu_ib *ib, 8629 uint32_t flags) 8630 { 8631 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8632 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8633 8634 /* Currently, there is a high possibility to get wave ID mismatch 8635 * between ME and GDS, leading to a hw deadlock, because ME generates 8636 * different wave IDs than the GDS expects. This situation happens 8637 * randomly when at least 5 compute pipes use GDS ordered append. 8638 * The wave IDs generated by ME are also wrong after suspend/resume. 8639 * Those are probably bugs somewhere else in the kernel driver. 8640 * 8641 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8642 * GDS to 0 for this ring (me/pipe). 8643 */ 8644 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8645 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8646 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8647 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8648 } 8649 8650 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8651 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8652 amdgpu_ring_write(ring, 8653 #ifdef __BIG_ENDIAN 8654 (2 << 0) | 8655 #endif 8656 lower_32_bits(ib->gpu_addr)); 8657 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8658 amdgpu_ring_write(ring, control); 8659 } 8660 8661 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8662 u64 seq, unsigned flags) 8663 { 8664 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8665 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8666 8667 /* RELEASE_MEM - flush caches, send int */ 8668 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8669 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8670 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8671 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8672 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8673 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8674 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8675 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8676 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8677 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8678 8679 /* 8680 * the address should be Qword aligned if 64bit write, Dword 8681 * aligned if only send 32bit data low (discard data high) 8682 */ 8683 if (write64bit) 8684 BUG_ON(addr & 0x7); 8685 else 8686 BUG_ON(addr & 0x3); 8687 amdgpu_ring_write(ring, lower_32_bits(addr)); 8688 amdgpu_ring_write(ring, upper_32_bits(addr)); 8689 amdgpu_ring_write(ring, lower_32_bits(seq)); 8690 amdgpu_ring_write(ring, upper_32_bits(seq)); 8691 amdgpu_ring_write(ring, 0); 8692 } 8693 8694 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8695 { 8696 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8697 uint32_t seq = ring->fence_drv.sync_seq; 8698 uint64_t addr = ring->fence_drv.gpu_addr; 8699 8700 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8701 upper_32_bits(addr), seq, 0xffffffff, 4); 8702 } 8703 8704 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8705 unsigned vmid, uint64_t pd_addr) 8706 { 8707 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8708 8709 /* compute doesn't have PFP */ 8710 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8711 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8712 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8713 amdgpu_ring_write(ring, 0x0); 8714 } 8715 } 8716 8717 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8718 u64 seq, unsigned int flags) 8719 { 8720 struct amdgpu_device *adev = ring->adev; 8721 8722 /* we only allocate 32bit for each seq wb address */ 8723 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8724 8725 /* write fence seq to the "addr" */ 8726 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8727 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8728 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8729 amdgpu_ring_write(ring, lower_32_bits(addr)); 8730 amdgpu_ring_write(ring, upper_32_bits(addr)); 8731 amdgpu_ring_write(ring, lower_32_bits(seq)); 8732 8733 if (flags & AMDGPU_FENCE_FLAG_INT) { 8734 /* set register to trigger INT */ 8735 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8736 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8737 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8738 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8739 amdgpu_ring_write(ring, 0); 8740 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8741 } 8742 } 8743 8744 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8745 { 8746 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8747 amdgpu_ring_write(ring, 0); 8748 } 8749 8750 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8751 uint32_t flags) 8752 { 8753 uint32_t dw2 = 0; 8754 8755 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8756 gfx_v10_0_ring_emit_ce_meta(ring, 8757 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8758 8759 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8760 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8761 /* set load_global_config & load_global_uconfig */ 8762 dw2 |= 0x8001; 8763 /* set load_cs_sh_regs */ 8764 dw2 |= 0x01000000; 8765 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8766 dw2 |= 0x10002; 8767 8768 /* set load_ce_ram if preamble presented */ 8769 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8770 dw2 |= 0x10000000; 8771 } else { 8772 /* still load_ce_ram if this is the first time preamble presented 8773 * although there is no context switch happens. 8774 */ 8775 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8776 dw2 |= 0x10000000; 8777 } 8778 8779 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8780 amdgpu_ring_write(ring, dw2); 8781 amdgpu_ring_write(ring, 0); 8782 } 8783 8784 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8785 { 8786 unsigned ret; 8787 8788 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8789 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8790 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8791 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8792 ret = ring->wptr & ring->buf_mask; 8793 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8794 8795 return ret; 8796 } 8797 8798 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8799 { 8800 unsigned cur; 8801 BUG_ON(offset > ring->buf_mask); 8802 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8803 8804 cur = (ring->wptr - 1) & ring->buf_mask; 8805 if (likely(cur > offset)) 8806 ring->ring[offset] = cur - offset; 8807 else 8808 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8809 } 8810 8811 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8812 { 8813 int i, r = 0; 8814 struct amdgpu_device *adev = ring->adev; 8815 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8816 struct amdgpu_ring *kiq_ring = &kiq->ring; 8817 unsigned long flags; 8818 8819 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8820 return -EINVAL; 8821 8822 spin_lock_irqsave(&kiq->ring_lock, flags); 8823 8824 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8825 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8826 return -ENOMEM; 8827 } 8828 8829 /* assert preemption condition */ 8830 amdgpu_ring_set_preempt_cond_exec(ring, false); 8831 8832 /* assert IB preemption, emit the trailing fence */ 8833 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8834 ring->trail_fence_gpu_addr, 8835 ++ring->trail_seq); 8836 amdgpu_ring_commit(kiq_ring); 8837 8838 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8839 8840 /* poll the trailing fence */ 8841 for (i = 0; i < adev->usec_timeout; i++) { 8842 if (ring->trail_seq == 8843 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8844 break; 8845 udelay(1); 8846 } 8847 8848 if (i >= adev->usec_timeout) { 8849 r = -EINVAL; 8850 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8851 } 8852 8853 /* deassert preemption condition */ 8854 amdgpu_ring_set_preempt_cond_exec(ring, true); 8855 return r; 8856 } 8857 8858 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8859 { 8860 struct amdgpu_device *adev = ring->adev; 8861 struct v10_ce_ib_state ce_payload = {0}; 8862 uint64_t csa_addr; 8863 int cnt; 8864 8865 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8866 csa_addr = amdgpu_csa_vaddr(ring->adev); 8867 8868 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8869 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8870 WRITE_DATA_DST_SEL(8) | 8871 WR_CONFIRM) | 8872 WRITE_DATA_CACHE_POLICY(0)); 8873 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8874 offsetof(struct v10_gfx_meta_data, ce_payload))); 8875 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8876 offsetof(struct v10_gfx_meta_data, ce_payload))); 8877 8878 if (resume) 8879 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8880 offsetof(struct v10_gfx_meta_data, 8881 ce_payload), 8882 sizeof(ce_payload) >> 2); 8883 else 8884 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8885 sizeof(ce_payload) >> 2); 8886 } 8887 8888 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8889 { 8890 struct amdgpu_device *adev = ring->adev; 8891 struct v10_de_ib_state de_payload = {0}; 8892 uint64_t csa_addr, gds_addr; 8893 int cnt; 8894 8895 csa_addr = amdgpu_csa_vaddr(ring->adev); 8896 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8897 PAGE_SIZE); 8898 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8899 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8900 8901 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8902 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8903 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8904 WRITE_DATA_DST_SEL(8) | 8905 WR_CONFIRM) | 8906 WRITE_DATA_CACHE_POLICY(0)); 8907 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8908 offsetof(struct v10_gfx_meta_data, de_payload))); 8909 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8910 offsetof(struct v10_gfx_meta_data, de_payload))); 8911 8912 if (resume) 8913 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8914 offsetof(struct v10_gfx_meta_data, 8915 de_payload), 8916 sizeof(de_payload) >> 2); 8917 else 8918 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8919 sizeof(de_payload) >> 2); 8920 } 8921 8922 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8923 bool secure) 8924 { 8925 uint32_t v = secure ? FRAME_TMZ : 0; 8926 8927 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8928 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8929 } 8930 8931 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8932 uint32_t reg_val_offs) 8933 { 8934 struct amdgpu_device *adev = ring->adev; 8935 8936 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8937 amdgpu_ring_write(ring, 0 | /* src: register*/ 8938 (5 << 8) | /* dst: memory */ 8939 (1 << 20)); /* write confirm */ 8940 amdgpu_ring_write(ring, reg); 8941 amdgpu_ring_write(ring, 0); 8942 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8943 reg_val_offs * 4)); 8944 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8945 reg_val_offs * 4)); 8946 } 8947 8948 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8949 uint32_t val) 8950 { 8951 uint32_t cmd = 0; 8952 8953 switch (ring->funcs->type) { 8954 case AMDGPU_RING_TYPE_GFX: 8955 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8956 break; 8957 case AMDGPU_RING_TYPE_KIQ: 8958 cmd = (1 << 16); /* no inc addr */ 8959 break; 8960 default: 8961 cmd = WR_CONFIRM; 8962 break; 8963 } 8964 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8965 amdgpu_ring_write(ring, cmd); 8966 amdgpu_ring_write(ring, reg); 8967 amdgpu_ring_write(ring, 0); 8968 amdgpu_ring_write(ring, val); 8969 } 8970 8971 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8972 uint32_t val, uint32_t mask) 8973 { 8974 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8975 } 8976 8977 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8978 uint32_t reg0, uint32_t reg1, 8979 uint32_t ref, uint32_t mask) 8980 { 8981 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8982 struct amdgpu_device *adev = ring->adev; 8983 bool fw_version_ok = false; 8984 8985 fw_version_ok = adev->gfx.cp_fw_write_wait; 8986 8987 if (fw_version_ok) 8988 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8989 ref, mask, 0x20); 8990 else 8991 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8992 ref, mask); 8993 } 8994 8995 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8996 unsigned vmid) 8997 { 8998 struct amdgpu_device *adev = ring->adev; 8999 uint32_t value = 0; 9000 9001 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 9002 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 9003 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 9004 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 9005 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 9006 } 9007 9008 static void 9009 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9010 uint32_t me, uint32_t pipe, 9011 enum amdgpu_interrupt_state state) 9012 { 9013 uint32_t cp_int_cntl, cp_int_cntl_reg; 9014 9015 if (!me) { 9016 switch (pipe) { 9017 case 0: 9018 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9019 break; 9020 case 1: 9021 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9022 break; 9023 default: 9024 DRM_DEBUG("invalid pipe %d\n", pipe); 9025 return; 9026 } 9027 } else { 9028 DRM_DEBUG("invalid me %d\n", me); 9029 return; 9030 } 9031 9032 switch (state) { 9033 case AMDGPU_IRQ_STATE_DISABLE: 9034 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9035 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9036 TIME_STAMP_INT_ENABLE, 0); 9037 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9038 break; 9039 case AMDGPU_IRQ_STATE_ENABLE: 9040 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9041 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9042 TIME_STAMP_INT_ENABLE, 1); 9043 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9044 break; 9045 default: 9046 break; 9047 } 9048 } 9049 9050 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9051 int me, int pipe, 9052 enum amdgpu_interrupt_state state) 9053 { 9054 u32 mec_int_cntl, mec_int_cntl_reg; 9055 9056 /* 9057 * amdgpu controls only the first MEC. That's why this function only 9058 * handles the setting of interrupts for this specific MEC. All other 9059 * pipes' interrupts are set by amdkfd. 9060 */ 9061 9062 if (me == 1) { 9063 switch (pipe) { 9064 case 0: 9065 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9066 break; 9067 case 1: 9068 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9069 break; 9070 case 2: 9071 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9072 break; 9073 case 3: 9074 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9075 break; 9076 default: 9077 DRM_DEBUG("invalid pipe %d\n", pipe); 9078 return; 9079 } 9080 } else { 9081 DRM_DEBUG("invalid me %d\n", me); 9082 return; 9083 } 9084 9085 switch (state) { 9086 case AMDGPU_IRQ_STATE_DISABLE: 9087 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9088 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9089 TIME_STAMP_INT_ENABLE, 0); 9090 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9091 break; 9092 case AMDGPU_IRQ_STATE_ENABLE: 9093 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9094 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9095 TIME_STAMP_INT_ENABLE, 1); 9096 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9097 break; 9098 default: 9099 break; 9100 } 9101 } 9102 9103 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9104 struct amdgpu_irq_src *src, 9105 unsigned type, 9106 enum amdgpu_interrupt_state state) 9107 { 9108 switch (type) { 9109 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9110 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9111 break; 9112 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9113 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9114 break; 9115 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9116 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9117 break; 9118 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9119 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9120 break; 9121 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9122 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9123 break; 9124 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9125 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9126 break; 9127 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9128 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9129 break; 9130 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9131 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9132 break; 9133 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9134 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9135 break; 9136 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9137 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9138 break; 9139 default: 9140 break; 9141 } 9142 return 0; 9143 } 9144 9145 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9146 struct amdgpu_irq_src *source, 9147 struct amdgpu_iv_entry *entry) 9148 { 9149 int i; 9150 u8 me_id, pipe_id, queue_id; 9151 struct amdgpu_ring *ring; 9152 9153 DRM_DEBUG("IH: CP EOP\n"); 9154 me_id = (entry->ring_id & 0x0c) >> 2; 9155 pipe_id = (entry->ring_id & 0x03) >> 0; 9156 queue_id = (entry->ring_id & 0x70) >> 4; 9157 9158 switch (me_id) { 9159 case 0: 9160 if (pipe_id == 0) 9161 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9162 else 9163 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9164 break; 9165 case 1: 9166 case 2: 9167 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9168 ring = &adev->gfx.compute_ring[i]; 9169 /* Per-queue interrupt is supported for MEC starting from VI. 9170 * The interrupt can only be enabled/disabled per pipe instead of per queue. 9171 */ 9172 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 9173 amdgpu_fence_process(ring); 9174 } 9175 break; 9176 } 9177 return 0; 9178 } 9179 9180 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9181 struct amdgpu_irq_src *source, 9182 unsigned type, 9183 enum amdgpu_interrupt_state state) 9184 { 9185 switch (state) { 9186 case AMDGPU_IRQ_STATE_DISABLE: 9187 case AMDGPU_IRQ_STATE_ENABLE: 9188 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9189 PRIV_REG_INT_ENABLE, 9190 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9191 break; 9192 default: 9193 break; 9194 } 9195 9196 return 0; 9197 } 9198 9199 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9200 struct amdgpu_irq_src *source, 9201 unsigned type, 9202 enum amdgpu_interrupt_state state) 9203 { 9204 switch (state) { 9205 case AMDGPU_IRQ_STATE_DISABLE: 9206 case AMDGPU_IRQ_STATE_ENABLE: 9207 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9208 PRIV_INSTR_INT_ENABLE, 9209 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9210 break; 9211 default: 9212 break; 9213 } 9214 9215 return 0; 9216 } 9217 9218 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9219 struct amdgpu_iv_entry *entry) 9220 { 9221 u8 me_id, pipe_id, queue_id; 9222 struct amdgpu_ring *ring; 9223 int i; 9224 9225 me_id = (entry->ring_id & 0x0c) >> 2; 9226 pipe_id = (entry->ring_id & 0x03) >> 0; 9227 queue_id = (entry->ring_id & 0x70) >> 4; 9228 9229 switch (me_id) { 9230 case 0: 9231 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9232 ring = &adev->gfx.gfx_ring[i]; 9233 /* we only enabled 1 gfx queue per pipe for now */ 9234 if (ring->me == me_id && ring->pipe == pipe_id) 9235 drm_sched_fault(&ring->sched); 9236 } 9237 break; 9238 case 1: 9239 case 2: 9240 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9241 ring = &adev->gfx.compute_ring[i]; 9242 if (ring->me == me_id && ring->pipe == pipe_id && 9243 ring->queue == queue_id) 9244 drm_sched_fault(&ring->sched); 9245 } 9246 break; 9247 default: 9248 BUG(); 9249 } 9250 } 9251 9252 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9253 struct amdgpu_irq_src *source, 9254 struct amdgpu_iv_entry *entry) 9255 { 9256 DRM_ERROR("Illegal register access in command stream\n"); 9257 gfx_v10_0_handle_priv_fault(adev, entry); 9258 return 0; 9259 } 9260 9261 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9262 struct amdgpu_irq_src *source, 9263 struct amdgpu_iv_entry *entry) 9264 { 9265 DRM_ERROR("Illegal instruction in command stream\n"); 9266 gfx_v10_0_handle_priv_fault(adev, entry); 9267 return 0; 9268 } 9269 9270 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9271 struct amdgpu_irq_src *src, 9272 unsigned int type, 9273 enum amdgpu_interrupt_state state) 9274 { 9275 uint32_t tmp, target; 9276 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9277 9278 if (ring->me == 1) 9279 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9280 else 9281 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9282 target += ring->pipe; 9283 9284 switch (type) { 9285 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9286 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9287 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9288 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9289 GENERIC2_INT_ENABLE, 0); 9290 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9291 9292 tmp = RREG32_SOC15_IP(GC, target); 9293 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9294 GENERIC2_INT_ENABLE, 0); 9295 WREG32_SOC15_IP(GC, target, tmp); 9296 } else { 9297 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9298 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9299 GENERIC2_INT_ENABLE, 1); 9300 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9301 9302 tmp = RREG32_SOC15_IP(GC, target); 9303 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9304 GENERIC2_INT_ENABLE, 1); 9305 WREG32_SOC15_IP(GC, target, tmp); 9306 } 9307 break; 9308 default: 9309 BUG(); /* kiq only support GENERIC2_INT now */ 9310 break; 9311 } 9312 return 0; 9313 } 9314 9315 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9316 struct amdgpu_irq_src *source, 9317 struct amdgpu_iv_entry *entry) 9318 { 9319 u8 me_id, pipe_id, queue_id; 9320 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9321 9322 me_id = (entry->ring_id & 0x0c) >> 2; 9323 pipe_id = (entry->ring_id & 0x03) >> 0; 9324 queue_id = (entry->ring_id & 0x70) >> 4; 9325 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9326 me_id, pipe_id, queue_id); 9327 9328 amdgpu_fence_process(ring); 9329 return 0; 9330 } 9331 9332 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9333 { 9334 const unsigned int gcr_cntl = 9335 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9336 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9337 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9338 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9339 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9340 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9341 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9342 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9343 9344 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9345 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9346 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9347 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9348 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9349 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9350 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9351 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9352 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9353 } 9354 9355 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9356 .name = "gfx_v10_0", 9357 .early_init = gfx_v10_0_early_init, 9358 .late_init = gfx_v10_0_late_init, 9359 .sw_init = gfx_v10_0_sw_init, 9360 .sw_fini = gfx_v10_0_sw_fini, 9361 .hw_init = gfx_v10_0_hw_init, 9362 .hw_fini = gfx_v10_0_hw_fini, 9363 .suspend = gfx_v10_0_suspend, 9364 .resume = gfx_v10_0_resume, 9365 .is_idle = gfx_v10_0_is_idle, 9366 .wait_for_idle = gfx_v10_0_wait_for_idle, 9367 .soft_reset = gfx_v10_0_soft_reset, 9368 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9369 .set_powergating_state = gfx_v10_0_set_powergating_state, 9370 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9371 }; 9372 9373 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9374 .type = AMDGPU_RING_TYPE_GFX, 9375 .align_mask = 0xff, 9376 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9377 .support_64bit_ptrs = true, 9378 .vmhub = AMDGPU_GFXHUB_0, 9379 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9380 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9381 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9382 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9383 5 + /* COND_EXEC */ 9384 7 + /* PIPELINE_SYNC */ 9385 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9386 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9387 2 + /* VM_FLUSH */ 9388 8 + /* FENCE for VM_FLUSH */ 9389 20 + /* GDS switch */ 9390 4 + /* double SWITCH_BUFFER, 9391 * the first COND_EXEC jump to the place 9392 * just prior to this double SWITCH_BUFFER 9393 */ 9394 5 + /* COND_EXEC */ 9395 7 + /* HDP_flush */ 9396 4 + /* VGT_flush */ 9397 14 + /* CE_META */ 9398 31 + /* DE_META */ 9399 3 + /* CNTX_CTRL */ 9400 5 + /* HDP_INVL */ 9401 8 + 8 + /* FENCE x2 */ 9402 2 + /* SWITCH_BUFFER */ 9403 8, /* gfx_v10_0_emit_mem_sync */ 9404 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9405 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9406 .emit_fence = gfx_v10_0_ring_emit_fence, 9407 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9408 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9409 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9410 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9411 .test_ring = gfx_v10_0_ring_test_ring, 9412 .test_ib = gfx_v10_0_ring_test_ib, 9413 .insert_nop = amdgpu_ring_insert_nop, 9414 .pad_ib = amdgpu_ring_generic_pad_ib, 9415 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9416 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9417 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9418 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9419 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9420 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9421 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9422 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9423 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9424 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9425 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9426 }; 9427 9428 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9429 .type = AMDGPU_RING_TYPE_COMPUTE, 9430 .align_mask = 0xff, 9431 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9432 .support_64bit_ptrs = true, 9433 .vmhub = AMDGPU_GFXHUB_0, 9434 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9435 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9436 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9437 .emit_frame_size = 9438 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9439 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9440 5 + /* hdp invalidate */ 9441 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9442 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9443 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9444 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9445 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9446 8, /* gfx_v10_0_emit_mem_sync */ 9447 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9448 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9449 .emit_fence = gfx_v10_0_ring_emit_fence, 9450 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9451 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9452 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9453 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9454 .test_ring = gfx_v10_0_ring_test_ring, 9455 .test_ib = gfx_v10_0_ring_test_ib, 9456 .insert_nop = amdgpu_ring_insert_nop, 9457 .pad_ib = amdgpu_ring_generic_pad_ib, 9458 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9459 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9460 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9461 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9462 }; 9463 9464 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9465 .type = AMDGPU_RING_TYPE_KIQ, 9466 .align_mask = 0xff, 9467 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9468 .support_64bit_ptrs = true, 9469 .vmhub = AMDGPU_GFXHUB_0, 9470 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9471 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9472 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9473 .emit_frame_size = 9474 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9475 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9476 5 + /*hdp invalidate */ 9477 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9478 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9479 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9480 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9481 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9482 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9483 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9484 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9485 .test_ring = gfx_v10_0_ring_test_ring, 9486 .test_ib = gfx_v10_0_ring_test_ib, 9487 .insert_nop = amdgpu_ring_insert_nop, 9488 .pad_ib = amdgpu_ring_generic_pad_ib, 9489 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9490 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9491 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9492 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9493 }; 9494 9495 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9496 { 9497 int i; 9498 9499 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9500 9501 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9502 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9503 9504 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9505 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9506 } 9507 9508 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9509 .set = gfx_v10_0_set_eop_interrupt_state, 9510 .process = gfx_v10_0_eop_irq, 9511 }; 9512 9513 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9514 .set = gfx_v10_0_set_priv_reg_fault_state, 9515 .process = gfx_v10_0_priv_reg_irq, 9516 }; 9517 9518 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9519 .set = gfx_v10_0_set_priv_inst_fault_state, 9520 .process = gfx_v10_0_priv_inst_irq, 9521 }; 9522 9523 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9524 .set = gfx_v10_0_kiq_set_interrupt_state, 9525 .process = gfx_v10_0_kiq_irq, 9526 }; 9527 9528 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9529 { 9530 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9531 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9532 9533 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9534 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9535 9536 adev->gfx.priv_reg_irq.num_types = 1; 9537 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9538 9539 adev->gfx.priv_inst_irq.num_types = 1; 9540 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9541 } 9542 9543 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9544 { 9545 switch (adev->asic_type) { 9546 case CHIP_NAVI10: 9547 case CHIP_NAVI14: 9548 case CHIP_NAVY_FLOUNDER: 9549 case CHIP_VANGOGH: 9550 case CHIP_DIMGREY_CAVEFISH: 9551 case CHIP_BEIGE_GOBY: 9552 case CHIP_YELLOW_CARP: 9553 case CHIP_CYAN_SKILLFISH: 9554 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9555 break; 9556 case CHIP_NAVI12: 9557 case CHIP_SIENNA_CICHLID: 9558 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9559 break; 9560 default: 9561 break; 9562 } 9563 } 9564 9565 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9566 { 9567 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9568 adev->gfx.config.max_sh_per_se * 9569 adev->gfx.config.max_shader_engines; 9570 9571 adev->gds.gds_size = 0x10000; 9572 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9573 adev->gds.gws_size = 64; 9574 adev->gds.oa_size = 16; 9575 } 9576 9577 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9578 u32 bitmap) 9579 { 9580 u32 data; 9581 9582 if (!bitmap) 9583 return; 9584 9585 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9586 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9587 9588 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9589 } 9590 9591 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9592 { 9593 u32 disabled_mask = 9594 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9595 u32 efuse_setting = 0; 9596 u32 vbios_setting = 0; 9597 9598 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9599 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9600 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9601 9602 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9603 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9604 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9605 9606 disabled_mask |= efuse_setting | vbios_setting; 9607 9608 return (~disabled_mask); 9609 } 9610 9611 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9612 { 9613 u32 wgp_idx, wgp_active_bitmap; 9614 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9615 9616 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9617 cu_active_bitmap = 0; 9618 9619 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9620 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9621 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9622 if (wgp_active_bitmap & (1 << wgp_idx)) 9623 cu_active_bitmap |= cu_bitmap_per_wgp; 9624 } 9625 9626 return cu_active_bitmap; 9627 } 9628 9629 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9630 struct amdgpu_cu_info *cu_info) 9631 { 9632 int i, j, k, counter, active_cu_number = 0; 9633 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9634 unsigned disable_masks[4 * 2]; 9635 9636 if (!adev || !cu_info) 9637 return -EINVAL; 9638 9639 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9640 9641 mutex_lock(&adev->grbm_idx_mutex); 9642 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9643 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9644 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9645 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 9646 (adev->asic_type == CHIP_YELLOW_CARP)) && 9647 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9648 continue; 9649 mask = 1; 9650 ao_bitmap = 0; 9651 counter = 0; 9652 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9653 if (i < 4 && j < 2) 9654 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9655 adev, disable_masks[i * 2 + j]); 9656 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9657 cu_info->bitmap[i][j] = bitmap; 9658 9659 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9660 if (bitmap & mask) { 9661 if (counter < adev->gfx.config.max_cu_per_sh) 9662 ao_bitmap |= mask; 9663 counter++; 9664 } 9665 mask <<= 1; 9666 } 9667 active_cu_number += counter; 9668 if (i < 2 && j < 2) 9669 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9670 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9671 } 9672 } 9673 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9674 mutex_unlock(&adev->grbm_idx_mutex); 9675 9676 cu_info->number = active_cu_number; 9677 cu_info->ao_cu_mask = ao_cu_mask; 9678 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9679 9680 return 0; 9681 } 9682 9683 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9684 { 9685 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9686 9687 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9688 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9689 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9690 9691 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9692 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9693 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9694 9695 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9696 adev->gfx.config.max_shader_engines); 9697 disabled_sa = efuse_setting | vbios_setting; 9698 disabled_sa &= max_sa_mask; 9699 9700 return disabled_sa; 9701 } 9702 9703 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9704 { 9705 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9706 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9707 9708 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9709 9710 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9711 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9712 max_shader_engines = adev->gfx.config.max_shader_engines; 9713 9714 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9715 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9716 disabled_sa_per_se &= max_sa_per_se_mask; 9717 if (disabled_sa_per_se == max_sa_per_se_mask) { 9718 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9719 break; 9720 } 9721 } 9722 } 9723 9724 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9725 { 9726 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9727 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9728 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9729 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9730 9731 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9732 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9733 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9734 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9735 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9736 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9737 9738 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9739 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9740 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9741 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9742 9743 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9744 9745 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9746 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9747 } 9748 9749 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9750 { 9751 .type = AMD_IP_BLOCK_TYPE_GFX, 9752 .major = 10, 9753 .minor = 0, 9754 .rev = 0, 9755 .funcs = &gfx_v10_0_ip_funcs, 9756 }; 9757