1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 114 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 119 120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 139 140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 146 #define mmCP_HYP_CE_UCODE_DATA 0x5819 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 150 #define mmCP_HYP_ME_UCODE_DATA 0x5817 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 152 153 #define mmCPG_PSP_DEBUG 0x5c10 154 #define mmCPG_PSP_DEBUG_BASE_IDX 1 155 #define mmCPC_PSP_DEBUG 0x5c11 156 #define mmCPC_PSP_DEBUG_BASE_IDX 1 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 159 160 //CC_GC_SA_UNIT_DISABLE 161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //GC_USER_SA_UNIT_DISABLE 166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 170 //PA_SC_ENHANCE_3 171 #define mmPA_SC_ENHANCE_3 0x1085 172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 175 176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 178 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 183 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 186 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 189 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 196 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 229 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 236 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 243 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 250 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 257 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 264 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 271 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 278 279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = { 280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS), 281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2), 282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3), 283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1), 284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2), 285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1), 286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1), 287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT), 288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT), 289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT), 290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2), 291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2), 292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS), 293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR), 294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0), 295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE), 296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR), 297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR), 298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE), 299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR), 300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR), 301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE), 302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR), 303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR), 304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE), 305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR), 307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ), 308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ), 309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ), 310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ), 311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO), 312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI), 313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ), 314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO), 315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI), 316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ), 317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO), 318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI), 319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ), 320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO), 321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI), 322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ), 323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS), 324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS), 325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS), 326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT), 327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT), 328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS), 329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2), 330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS), 331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS), 332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS), 333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS), 334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS), 335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS), 336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS), 337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS), 338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL), 339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS), 340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG), 341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL), 342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL), 343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR), 344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR), 345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR), 346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR), 347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR), 348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR), 349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR), 350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS), 351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT), 352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND), 353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE), 354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1), 355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2), 356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3), 357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4), 358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE), 359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE), 360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE), 361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2), 362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS), 363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS), 364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT), 365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6), 366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A), 367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B), 368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR), 369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST), 370 /* cp header registers */ 371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP), 372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP), 373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP), 374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP), 375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP), 376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP), 377 /* SE status registers */ 378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0), 379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1), 380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2), 381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) 382 }; 383 384 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = { 385 /* compute registers */ 386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID), 387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE), 388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY), 389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY), 390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM), 391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE), 392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI), 393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR), 394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL), 398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR), 399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI), 400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR), 401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL), 402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL), 406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR), 407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR), 408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS), 409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO), 410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI), 411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL), 412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET), 413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE), 414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET), 415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE), 416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE), 417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR), 418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM), 419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO), 420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI), 421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET), 424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) 425 }; 426 427 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = { 428 /* gfx queue registers */ 429 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE), 430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY), 431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE), 432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI), 433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET), 434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR), 435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR), 436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI), 437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST), 438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED), 439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL), 440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0), 441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0), 442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO), 443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI), 444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET), 445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR), 446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR), 447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI), 448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR), 449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI), 450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI) 452 }; 453 454 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 495 }; 496 497 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 498 /* Pending on emulation bring up */ 499 }; 500 501 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1554 }; 1555 1556 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1595 }; 1596 1597 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1640 }; 1641 1642 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1643 /* Pending on emulation bring up */ 1644 }; 1645 1646 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2267 }; 2268 2269 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2270 /* Pending on emulation bring up */ 2271 }; 2272 2273 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3326 }; 3327 3328 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3372 }; 3373 3374 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3375 /* Pending on emulation bring up */ 3376 }; 3377 3378 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3420 3421 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3423 }; 3424 3425 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3450 3451 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3453 }; 3454 3455 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3476 }; 3477 3478 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3515 }; 3516 3517 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3550 }; 3551 3552 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3587 }; 3588 3589 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3612 }; 3613 3614 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3637 }; 3638 3639 #define DEFAULT_SH_MEM_CONFIG \ 3640 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3641 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3642 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3643 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3644 3645 /* TODO: pending on golden setting value of gb address config */ 3646 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3647 3648 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3649 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3651 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3652 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3653 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3654 struct amdgpu_cu_info *cu_info); 3655 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3656 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3657 u32 sh_num, u32 instance, int xcc_id); 3658 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3659 3660 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3661 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3662 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3663 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3664 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3665 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3666 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3667 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3668 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3669 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3670 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3671 uint16_t pasid, uint32_t flush_type, 3672 bool all_hub, uint8_t dst_sel); 3673 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3674 unsigned int vmid); 3675 3676 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3677 enum amd_powergating_state state); 3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3679 { 3680 struct amdgpu_device *adev = kiq_ring->adev; 3681 u64 shader_mc_addr; 3682 3683 /* Cleaner shader MC address */ 3684 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 3685 3686 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3687 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3688 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3689 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3690 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3691 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 3692 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 3693 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3694 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3695 } 3696 3697 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3698 struct amdgpu_ring *ring) 3699 { 3700 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3701 uint64_t wptr_addr = ring->wptr_gpu_addr; 3702 uint32_t eng_sel = 0; 3703 3704 switch (ring->funcs->type) { 3705 case AMDGPU_RING_TYPE_COMPUTE: 3706 eng_sel = 0; 3707 break; 3708 case AMDGPU_RING_TYPE_GFX: 3709 eng_sel = 4; 3710 break; 3711 case AMDGPU_RING_TYPE_MES: 3712 eng_sel = 5; 3713 break; 3714 default: 3715 WARN_ON(1); 3716 } 3717 3718 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3719 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3720 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3721 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3722 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3723 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3724 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3725 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3726 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3727 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3728 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3729 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3730 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3731 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3732 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3733 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3734 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3735 } 3736 3737 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3738 struct amdgpu_ring *ring, 3739 enum amdgpu_unmap_queues_action action, 3740 u64 gpu_addr, u64 seq) 3741 { 3742 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3743 3744 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3745 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3746 PACKET3_UNMAP_QUEUES_ACTION(action) | 3747 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3748 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3749 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3750 amdgpu_ring_write(kiq_ring, 3751 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3752 3753 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3754 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3755 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3756 amdgpu_ring_write(kiq_ring, seq); 3757 } else { 3758 amdgpu_ring_write(kiq_ring, 0); 3759 amdgpu_ring_write(kiq_ring, 0); 3760 amdgpu_ring_write(kiq_ring, 0); 3761 } 3762 } 3763 3764 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3765 struct amdgpu_ring *ring, 3766 u64 addr, 3767 u64 seq) 3768 { 3769 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3770 3771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3772 amdgpu_ring_write(kiq_ring, 3773 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3774 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3775 PACKET3_QUERY_STATUS_COMMAND(2)); 3776 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3777 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3778 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3779 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3780 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3781 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3782 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3783 } 3784 3785 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3786 uint16_t pasid, uint32_t flush_type, 3787 bool all_hub) 3788 { 3789 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3790 } 3791 3792 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3793 .kiq_set_resources = gfx10_kiq_set_resources, 3794 .kiq_map_queues = gfx10_kiq_map_queues, 3795 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3796 .kiq_query_status = gfx10_kiq_query_status, 3797 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3798 .set_resources_size = 8, 3799 .map_queues_size = 7, 3800 .unmap_queues_size = 6, 3801 .query_status_size = 7, 3802 .invalidate_tlbs_size = 2, 3803 }; 3804 3805 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3806 { 3807 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3808 } 3809 3810 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3811 { 3812 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3813 case IP_VERSION(10, 1, 10): 3814 soc15_program_register_sequence(adev, 3815 golden_settings_gc_rlc_spm_10_0_nv10, 3816 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3817 break; 3818 case IP_VERSION(10, 1, 1): 3819 soc15_program_register_sequence(adev, 3820 golden_settings_gc_rlc_spm_10_1_nv14, 3821 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3822 break; 3823 case IP_VERSION(10, 1, 2): 3824 soc15_program_register_sequence(adev, 3825 golden_settings_gc_rlc_spm_10_1_2_nv12, 3826 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3827 break; 3828 default: 3829 break; 3830 } 3831 } 3832 3833 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3834 { 3835 if (amdgpu_sriov_vf(adev)) 3836 return; 3837 3838 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3839 case IP_VERSION(10, 1, 10): 3840 soc15_program_register_sequence(adev, 3841 golden_settings_gc_10_1, 3842 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3843 soc15_program_register_sequence(adev, 3844 golden_settings_gc_10_0_nv10, 3845 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3846 break; 3847 case IP_VERSION(10, 1, 1): 3848 soc15_program_register_sequence(adev, 3849 golden_settings_gc_10_1_1, 3850 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3851 soc15_program_register_sequence(adev, 3852 golden_settings_gc_10_1_nv14, 3853 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3854 break; 3855 case IP_VERSION(10, 1, 2): 3856 soc15_program_register_sequence(adev, 3857 golden_settings_gc_10_1_2, 3858 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3859 soc15_program_register_sequence(adev, 3860 golden_settings_gc_10_1_2_nv12, 3861 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3862 break; 3863 case IP_VERSION(10, 3, 0): 3864 soc15_program_register_sequence(adev, 3865 golden_settings_gc_10_3, 3866 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3867 soc15_program_register_sequence(adev, 3868 golden_settings_gc_10_3_sienna_cichlid, 3869 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3870 break; 3871 case IP_VERSION(10, 3, 2): 3872 soc15_program_register_sequence(adev, 3873 golden_settings_gc_10_3_2, 3874 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3875 break; 3876 case IP_VERSION(10, 3, 1): 3877 soc15_program_register_sequence(adev, 3878 golden_settings_gc_10_3_vangogh, 3879 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3880 break; 3881 case IP_VERSION(10, 3, 3): 3882 soc15_program_register_sequence(adev, 3883 golden_settings_gc_10_3_3, 3884 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3885 break; 3886 case IP_VERSION(10, 3, 4): 3887 soc15_program_register_sequence(adev, 3888 golden_settings_gc_10_3_4, 3889 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3890 break; 3891 case IP_VERSION(10, 3, 5): 3892 soc15_program_register_sequence(adev, 3893 golden_settings_gc_10_3_5, 3894 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3895 break; 3896 case IP_VERSION(10, 1, 3): 3897 case IP_VERSION(10, 1, 4): 3898 soc15_program_register_sequence(adev, 3899 golden_settings_gc_10_0_cyan_skillfish, 3900 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3901 break; 3902 case IP_VERSION(10, 3, 6): 3903 soc15_program_register_sequence(adev, 3904 golden_settings_gc_10_3_6, 3905 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3906 break; 3907 case IP_VERSION(10, 3, 7): 3908 soc15_program_register_sequence(adev, 3909 golden_settings_gc_10_3_7, 3910 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3911 break; 3912 default: 3913 break; 3914 } 3915 gfx_v10_0_init_spm_golden_registers(adev); 3916 } 3917 3918 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3919 bool wc, uint32_t reg, uint32_t val) 3920 { 3921 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3922 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3923 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3924 amdgpu_ring_write(ring, reg); 3925 amdgpu_ring_write(ring, 0); 3926 amdgpu_ring_write(ring, val); 3927 } 3928 3929 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3930 int mem_space, int opt, uint32_t addr0, 3931 uint32_t addr1, uint32_t ref, uint32_t mask, 3932 uint32_t inv) 3933 { 3934 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3935 amdgpu_ring_write(ring, 3936 /* memory (1) or register (0) */ 3937 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3938 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3939 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3940 WAIT_REG_MEM_ENGINE(eng_sel))); 3941 3942 if (mem_space) 3943 BUG_ON(addr0 & 0x3); /* Dword align */ 3944 amdgpu_ring_write(ring, addr0); 3945 amdgpu_ring_write(ring, addr1); 3946 amdgpu_ring_write(ring, ref); 3947 amdgpu_ring_write(ring, mask); 3948 amdgpu_ring_write(ring, inv); /* poll interval */ 3949 } 3950 3951 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3952 { 3953 struct amdgpu_device *adev = ring->adev; 3954 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3955 uint32_t tmp = 0; 3956 unsigned int i; 3957 int r; 3958 3959 WREG32(scratch, 0xCAFEDEAD); 3960 r = amdgpu_ring_alloc(ring, 3); 3961 if (r) { 3962 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3963 ring->idx, r); 3964 return r; 3965 } 3966 3967 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3968 amdgpu_ring_write(ring, scratch - 3969 PACKET3_SET_UCONFIG_REG_START); 3970 amdgpu_ring_write(ring, 0xDEADBEEF); 3971 amdgpu_ring_commit(ring); 3972 3973 for (i = 0; i < adev->usec_timeout; i++) { 3974 tmp = RREG32(scratch); 3975 if (tmp == 0xDEADBEEF) 3976 break; 3977 if (amdgpu_emu_mode == 1) 3978 msleep(1); 3979 else 3980 udelay(1); 3981 } 3982 3983 if (i >= adev->usec_timeout) 3984 r = -ETIMEDOUT; 3985 3986 return r; 3987 } 3988 3989 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3990 { 3991 struct amdgpu_device *adev = ring->adev; 3992 struct amdgpu_ib ib; 3993 struct dma_fence *f = NULL; 3994 unsigned int index; 3995 uint64_t gpu_addr; 3996 volatile uint32_t *cpu_ptr; 3997 long r; 3998 3999 memset(&ib, 0, sizeof(ib)); 4000 4001 r = amdgpu_device_wb_get(adev, &index); 4002 if (r) 4003 return r; 4004 4005 gpu_addr = adev->wb.gpu_addr + (index * 4); 4006 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 4007 cpu_ptr = &adev->wb.wb[index]; 4008 4009 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 4010 if (r) { 4011 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 4012 goto err1; 4013 } 4014 4015 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 4016 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 4017 ib.ptr[2] = lower_32_bits(gpu_addr); 4018 ib.ptr[3] = upper_32_bits(gpu_addr); 4019 ib.ptr[4] = 0xDEADBEEF; 4020 ib.length_dw = 5; 4021 4022 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4023 if (r) 4024 goto err2; 4025 4026 r = dma_fence_wait_timeout(f, false, timeout); 4027 if (r == 0) { 4028 r = -ETIMEDOUT; 4029 goto err2; 4030 } else if (r < 0) { 4031 goto err2; 4032 } 4033 4034 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 4035 r = 0; 4036 else 4037 r = -EINVAL; 4038 err2: 4039 amdgpu_ib_free(adev, &ib, NULL); 4040 dma_fence_put(f); 4041 err1: 4042 amdgpu_device_wb_free(adev, index); 4043 return r; 4044 } 4045 4046 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 4047 { 4048 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4049 amdgpu_ucode_release(&adev->gfx.me_fw); 4050 amdgpu_ucode_release(&adev->gfx.ce_fw); 4051 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4052 amdgpu_ucode_release(&adev->gfx.mec_fw); 4053 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4054 4055 kfree(adev->gfx.rlc.register_list_format); 4056 } 4057 4058 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 4059 { 4060 adev->gfx.cp_fw_write_wait = false; 4061 4062 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4063 case IP_VERSION(10, 1, 10): 4064 case IP_VERSION(10, 1, 2): 4065 case IP_VERSION(10, 1, 1): 4066 case IP_VERSION(10, 1, 3): 4067 case IP_VERSION(10, 1, 4): 4068 if ((adev->gfx.me_fw_version >= 0x00000046) && 4069 (adev->gfx.me_feature_version >= 27) && 4070 (adev->gfx.pfp_fw_version >= 0x00000068) && 4071 (adev->gfx.pfp_feature_version >= 27) && 4072 (adev->gfx.mec_fw_version >= 0x0000005b) && 4073 (adev->gfx.mec_feature_version >= 27)) 4074 adev->gfx.cp_fw_write_wait = true; 4075 break; 4076 case IP_VERSION(10, 3, 0): 4077 case IP_VERSION(10, 3, 2): 4078 case IP_VERSION(10, 3, 1): 4079 case IP_VERSION(10, 3, 4): 4080 case IP_VERSION(10, 3, 5): 4081 case IP_VERSION(10, 3, 6): 4082 case IP_VERSION(10, 3, 3): 4083 case IP_VERSION(10, 3, 7): 4084 adev->gfx.cp_fw_write_wait = true; 4085 break; 4086 default: 4087 break; 4088 } 4089 4090 if (!adev->gfx.cp_fw_write_wait) 4091 DRM_WARN_ONCE("CP firmware version too old, please update!"); 4092 } 4093 4094 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4095 { 4096 bool ret = false; 4097 4098 switch (adev->pdev->revision) { 4099 case 0xc2: 4100 case 0xc3: 4101 ret = true; 4102 break; 4103 default: 4104 ret = false; 4105 break; 4106 } 4107 4108 return ret; 4109 } 4110 4111 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4112 { 4113 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4114 case IP_VERSION(10, 1, 10): 4115 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4116 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4117 break; 4118 default: 4119 break; 4120 } 4121 } 4122 4123 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4124 { 4125 char fw_name[53]; 4126 char ucode_prefix[30]; 4127 const char *wks = ""; 4128 int err; 4129 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4130 uint16_t version_major; 4131 uint16_t version_minor; 4132 4133 DRM_DEBUG("\n"); 4134 4135 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) && 4136 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 4137 wks = "_wks"; 4138 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 4139 4140 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 4141 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 4142 if (err) 4143 goto out; 4144 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4145 4146 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 4147 "amdgpu/%s_me%s.bin", ucode_prefix, wks); 4148 if (err) 4149 goto out; 4150 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4151 4152 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, 4153 "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 4154 if (err) 4155 goto out; 4156 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4157 4158 if (!amdgpu_sriov_vf(adev)) { 4159 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4160 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4161 if (err) 4162 goto out; 4163 4164 /* don't validate this firmware. There are apparently firmwares 4165 * in the wild with incorrect size in the header 4166 */ 4167 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4168 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4169 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4170 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4171 if (err) 4172 goto out; 4173 } 4174 4175 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 4176 "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4177 if (err) 4178 goto out; 4179 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4180 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4181 4182 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, 4183 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4184 if (!err) { 4185 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4186 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4187 } else { 4188 err = 0; 4189 adev->gfx.mec2_fw = NULL; 4190 } 4191 4192 gfx_v10_0_check_fw_write_wait(adev); 4193 out: 4194 if (err) { 4195 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4196 amdgpu_ucode_release(&adev->gfx.me_fw); 4197 amdgpu_ucode_release(&adev->gfx.ce_fw); 4198 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4199 amdgpu_ucode_release(&adev->gfx.mec_fw); 4200 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4201 } 4202 4203 gfx_v10_0_check_gfxoff_flag(adev); 4204 4205 return err; 4206 } 4207 4208 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4209 { 4210 u32 count = 0; 4211 const struct cs_section_def *sect = NULL; 4212 const struct cs_extent_def *ext = NULL; 4213 4214 /* begin clear state */ 4215 count += 2; 4216 /* context control state */ 4217 count += 3; 4218 4219 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4220 for (ext = sect->section; ext->extent != NULL; ++ext) { 4221 if (sect->id == SECT_CONTEXT) 4222 count += 2 + ext->reg_count; 4223 else 4224 return 0; 4225 } 4226 } 4227 4228 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4229 count += 3; 4230 /* end clear state */ 4231 count += 2; 4232 /* clear state */ 4233 count += 2; 4234 4235 return count; 4236 } 4237 4238 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4239 volatile u32 *buffer) 4240 { 4241 u32 count = 0, i; 4242 const struct cs_section_def *sect = NULL; 4243 const struct cs_extent_def *ext = NULL; 4244 int ctx_reg_offset; 4245 4246 if (adev->gfx.rlc.cs_data == NULL) 4247 return; 4248 if (buffer == NULL) 4249 return; 4250 4251 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4252 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4253 4254 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4255 buffer[count++] = cpu_to_le32(0x80000000); 4256 buffer[count++] = cpu_to_le32(0x80000000); 4257 4258 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4259 for (ext = sect->section; ext->extent != NULL; ++ext) { 4260 if (sect->id == SECT_CONTEXT) { 4261 buffer[count++] = 4262 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4263 buffer[count++] = cpu_to_le32(ext->reg_index - 4264 PACKET3_SET_CONTEXT_REG_START); 4265 for (i = 0; i < ext->reg_count; i++) 4266 buffer[count++] = cpu_to_le32(ext->extent[i]); 4267 } else { 4268 return; 4269 } 4270 } 4271 } 4272 4273 ctx_reg_offset = 4274 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4275 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4276 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4277 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4278 4279 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4280 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4281 4282 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4283 buffer[count++] = cpu_to_le32(0); 4284 } 4285 4286 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4287 { 4288 /* clear state block */ 4289 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4290 &adev->gfx.rlc.clear_state_gpu_addr, 4291 (void **)&adev->gfx.rlc.cs_ptr); 4292 4293 /* jump table block */ 4294 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4295 &adev->gfx.rlc.cp_table_gpu_addr, 4296 (void **)&adev->gfx.rlc.cp_table_ptr); 4297 } 4298 4299 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4300 { 4301 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4302 4303 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4304 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4305 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4306 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4307 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4308 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4309 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4310 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4311 case IP_VERSION(10, 3, 0): 4312 reg_access_ctrl->spare_int = 4313 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4314 break; 4315 default: 4316 reg_access_ctrl->spare_int = 4317 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4318 break; 4319 } 4320 adev->gfx.rlc.rlcg_reg_access_supported = true; 4321 } 4322 4323 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4324 { 4325 const struct cs_section_def *cs_data; 4326 int r; 4327 4328 adev->gfx.rlc.cs_data = gfx10_cs_data; 4329 4330 cs_data = adev->gfx.rlc.cs_data; 4331 4332 if (cs_data) { 4333 /* init clear state block */ 4334 r = amdgpu_gfx_rlc_init_csb(adev); 4335 if (r) 4336 return r; 4337 } 4338 4339 return 0; 4340 } 4341 4342 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4343 { 4344 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4345 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4346 } 4347 4348 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4349 { 4350 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4351 4352 amdgpu_gfx_graphics_queue_acquire(adev); 4353 } 4354 4355 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4356 { 4357 int r; 4358 u32 *hpd; 4359 const __le32 *fw_data = NULL; 4360 unsigned int fw_size; 4361 u32 *fw = NULL; 4362 size_t mec_hpd_size; 4363 4364 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4365 4366 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4367 4368 /* take ownership of the relevant compute queues */ 4369 amdgpu_gfx_compute_queue_acquire(adev); 4370 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4371 4372 if (mec_hpd_size) { 4373 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4374 AMDGPU_GEM_DOMAIN_GTT, 4375 &adev->gfx.mec.hpd_eop_obj, 4376 &adev->gfx.mec.hpd_eop_gpu_addr, 4377 (void **)&hpd); 4378 if (r) { 4379 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4380 gfx_v10_0_mec_fini(adev); 4381 return r; 4382 } 4383 4384 memset(hpd, 0, mec_hpd_size); 4385 4386 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4387 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4388 } 4389 4390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4391 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4392 4393 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4394 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4395 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4396 4397 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4398 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4399 &adev->gfx.mec.mec_fw_obj, 4400 &adev->gfx.mec.mec_fw_gpu_addr, 4401 (void **)&fw); 4402 if (r) { 4403 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4404 gfx_v10_0_mec_fini(adev); 4405 return r; 4406 } 4407 4408 memcpy(fw, fw_data, fw_size); 4409 4410 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4411 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4412 } 4413 4414 return 0; 4415 } 4416 4417 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4418 { 4419 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4420 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4421 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4422 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4423 } 4424 4425 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4426 uint32_t thread, uint32_t regno, 4427 uint32_t num, uint32_t *out) 4428 { 4429 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4430 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4431 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4432 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4433 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4434 while (num--) 4435 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4436 } 4437 4438 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4439 { 4440 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4441 * field when performing a select_se_sh so it should be 4442 * zero here 4443 */ 4444 WARN_ON(simd != 0); 4445 4446 /* type 2 wave data */ 4447 dst[(*no_fields)++] = 2; 4448 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4449 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4450 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4451 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4452 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4453 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4454 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4455 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4457 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4458 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4459 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4460 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4461 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4462 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4463 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4464 } 4465 4466 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4467 uint32_t wave, uint32_t start, 4468 uint32_t size, uint32_t *dst) 4469 { 4470 WARN_ON(simd != 0); 4471 4472 wave_read_regs( 4473 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4474 dst); 4475 } 4476 4477 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4478 uint32_t wave, uint32_t thread, 4479 uint32_t start, uint32_t size, 4480 uint32_t *dst) 4481 { 4482 wave_read_regs( 4483 adev, wave, thread, 4484 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4485 } 4486 4487 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4488 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4489 { 4490 nv_grbm_select(adev, me, pipe, q, vm); 4491 } 4492 4493 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4494 bool enable) 4495 { 4496 uint32_t data, def; 4497 4498 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4499 4500 if (enable) 4501 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4502 else 4503 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4504 4505 if (data != def) 4506 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4507 } 4508 4509 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4510 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4511 .select_se_sh = &gfx_v10_0_select_se_sh, 4512 .read_wave_data = &gfx_v10_0_read_wave_data, 4513 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4514 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4515 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4516 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4517 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4518 }; 4519 4520 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4521 { 4522 u32 gb_addr_config; 4523 4524 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4525 case IP_VERSION(10, 1, 10): 4526 case IP_VERSION(10, 1, 1): 4527 case IP_VERSION(10, 1, 2): 4528 adev->gfx.config.max_hw_contexts = 8; 4529 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4530 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4531 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4532 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4533 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4534 break; 4535 case IP_VERSION(10, 3, 0): 4536 case IP_VERSION(10, 3, 2): 4537 case IP_VERSION(10, 3, 1): 4538 case IP_VERSION(10, 3, 4): 4539 case IP_VERSION(10, 3, 5): 4540 case IP_VERSION(10, 3, 6): 4541 case IP_VERSION(10, 3, 3): 4542 case IP_VERSION(10, 3, 7): 4543 adev->gfx.config.max_hw_contexts = 8; 4544 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4545 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4546 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4547 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4548 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4549 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4550 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4551 break; 4552 case IP_VERSION(10, 1, 3): 4553 case IP_VERSION(10, 1, 4): 4554 adev->gfx.config.max_hw_contexts = 8; 4555 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4556 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4557 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4558 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4559 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4560 break; 4561 default: 4562 BUG(); 4563 break; 4564 } 4565 4566 adev->gfx.config.gb_addr_config = gb_addr_config; 4567 4568 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4569 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4570 GB_ADDR_CONFIG, NUM_PIPES); 4571 4572 adev->gfx.config.max_tile_pipes = 4573 adev->gfx.config.gb_addr_config_fields.num_pipes; 4574 4575 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4576 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4577 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4578 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4579 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4580 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4581 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4582 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4583 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4584 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4585 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4586 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4587 } 4588 4589 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4590 int me, int pipe, int queue) 4591 { 4592 struct amdgpu_ring *ring; 4593 unsigned int irq_type; 4594 unsigned int hw_prio; 4595 4596 ring = &adev->gfx.gfx_ring[ring_id]; 4597 4598 ring->me = me; 4599 ring->pipe = pipe; 4600 ring->queue = queue; 4601 4602 ring->ring_obj = NULL; 4603 ring->use_doorbell = true; 4604 4605 if (!ring_id) 4606 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4607 else 4608 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4609 ring->vm_hub = AMDGPU_GFXHUB(0); 4610 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4611 4612 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4613 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4614 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4615 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4616 hw_prio, NULL); 4617 } 4618 4619 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4620 int mec, int pipe, int queue) 4621 { 4622 unsigned int irq_type; 4623 struct amdgpu_ring *ring; 4624 unsigned int hw_prio; 4625 4626 ring = &adev->gfx.compute_ring[ring_id]; 4627 4628 /* mec0 is me1 */ 4629 ring->me = mec + 1; 4630 ring->pipe = pipe; 4631 ring->queue = queue; 4632 4633 ring->ring_obj = NULL; 4634 ring->use_doorbell = true; 4635 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4636 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4637 + (ring_id * GFX10_MEC_HPD_SIZE); 4638 ring->vm_hub = AMDGPU_GFXHUB(0); 4639 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4640 4641 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4642 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4643 + ring->pipe; 4644 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4645 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4646 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4647 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4648 hw_prio, NULL); 4649 } 4650 4651 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) 4652 { 4653 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 4654 uint32_t *ptr; 4655 uint32_t inst; 4656 4657 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 4658 if (!ptr) { 4659 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 4660 adev->gfx.ip_dump_core = NULL; 4661 } else { 4662 adev->gfx.ip_dump_core = ptr; 4663 } 4664 4665 /* Allocate memory for compute queue registers for all the instances */ 4666 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 4667 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4668 adev->gfx.mec.num_queue_per_pipe; 4669 4670 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4671 if (!ptr) { 4672 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 4673 adev->gfx.ip_dump_compute_queues = NULL; 4674 } else { 4675 adev->gfx.ip_dump_compute_queues = ptr; 4676 } 4677 4678 /* Allocate memory for gfx queue registers for all the instances */ 4679 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 4680 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 4681 adev->gfx.me.num_queue_per_pipe; 4682 4683 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 4684 if (!ptr) { 4685 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 4686 adev->gfx.ip_dump_gfx_queues = NULL; 4687 } else { 4688 adev->gfx.ip_dump_gfx_queues = ptr; 4689 } 4690 } 4691 4692 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 4693 { 4694 int i, j, k, r, ring_id = 0; 4695 int xcc_id = 0; 4696 struct amdgpu_device *adev = ip_block->adev; 4697 4698 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4699 case IP_VERSION(10, 1, 10): 4700 case IP_VERSION(10, 1, 1): 4701 case IP_VERSION(10, 1, 2): 4702 case IP_VERSION(10, 1, 3): 4703 case IP_VERSION(10, 1, 4): 4704 adev->gfx.me.num_me = 1; 4705 adev->gfx.me.num_pipe_per_me = 1; 4706 adev->gfx.me.num_queue_per_pipe = 1; 4707 adev->gfx.mec.num_mec = 2; 4708 adev->gfx.mec.num_pipe_per_mec = 4; 4709 adev->gfx.mec.num_queue_per_pipe = 8; 4710 break; 4711 case IP_VERSION(10, 3, 0): 4712 case IP_VERSION(10, 3, 2): 4713 case IP_VERSION(10, 3, 1): 4714 case IP_VERSION(10, 3, 4): 4715 case IP_VERSION(10, 3, 5): 4716 case IP_VERSION(10, 3, 6): 4717 case IP_VERSION(10, 3, 3): 4718 case IP_VERSION(10, 3, 7): 4719 adev->gfx.me.num_me = 1; 4720 adev->gfx.me.num_pipe_per_me = 2; 4721 adev->gfx.me.num_queue_per_pipe = 1; 4722 adev->gfx.mec.num_mec = 2; 4723 adev->gfx.mec.num_pipe_per_mec = 4; 4724 adev->gfx.mec.num_queue_per_pipe = 4; 4725 break; 4726 default: 4727 adev->gfx.me.num_me = 1; 4728 adev->gfx.me.num_pipe_per_me = 1; 4729 adev->gfx.me.num_queue_per_pipe = 1; 4730 adev->gfx.mec.num_mec = 1; 4731 adev->gfx.mec.num_pipe_per_mec = 4; 4732 adev->gfx.mec.num_queue_per_pipe = 8; 4733 break; 4734 } 4735 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4736 default: 4737 adev->gfx.enable_cleaner_shader = false; 4738 break; 4739 } 4740 4741 /* KIQ event */ 4742 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4743 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4744 &adev->gfx.kiq[0].irq); 4745 if (r) 4746 return r; 4747 4748 /* EOP Event */ 4749 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4750 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4751 &adev->gfx.eop_irq); 4752 if (r) 4753 return r; 4754 4755 /* Bad opcode Event */ 4756 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4757 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR, 4758 &adev->gfx.bad_op_irq); 4759 if (r) 4760 return r; 4761 4762 /* Privileged reg */ 4763 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4764 &adev->gfx.priv_reg_irq); 4765 if (r) 4766 return r; 4767 4768 /* Privileged inst */ 4769 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4770 &adev->gfx.priv_inst_irq); 4771 if (r) 4772 return r; 4773 4774 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4775 4776 gfx_v10_0_me_init(adev); 4777 4778 if (adev->gfx.rlc.funcs) { 4779 if (adev->gfx.rlc.funcs->init) { 4780 r = adev->gfx.rlc.funcs->init(adev); 4781 if (r) { 4782 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4783 return r; 4784 } 4785 } 4786 } 4787 4788 r = gfx_v10_0_mec_init(adev); 4789 if (r) { 4790 DRM_ERROR("Failed to init MEC BOs!\n"); 4791 return r; 4792 } 4793 4794 /* set up the gfx ring */ 4795 for (i = 0; i < adev->gfx.me.num_me; i++) { 4796 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4797 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4798 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4799 continue; 4800 4801 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4802 i, k, j); 4803 if (r) 4804 return r; 4805 ring_id++; 4806 } 4807 } 4808 } 4809 4810 ring_id = 0; 4811 /* set up the compute queues - allocate horizontally across pipes */ 4812 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4813 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4814 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4815 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4816 k, j)) 4817 continue; 4818 4819 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4820 i, k, j); 4821 if (r) 4822 return r; 4823 4824 ring_id++; 4825 } 4826 } 4827 } 4828 /* TODO: Add queue reset mask when FW fully supports it */ 4829 adev->gfx.gfx_supported_reset = 4830 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4831 adev->gfx.compute_supported_reset = 4832 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4833 4834 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4835 if (r) { 4836 DRM_ERROR("Failed to init KIQ BOs!\n"); 4837 return r; 4838 } 4839 4840 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 4841 if (r) 4842 return r; 4843 4844 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4845 if (r) 4846 return r; 4847 4848 /* allocate visible FB for rlc auto-loading fw */ 4849 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4850 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4851 if (r) 4852 return r; 4853 } 4854 4855 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4856 4857 gfx_v10_0_gpu_early_init(adev); 4858 4859 gfx_v10_0_alloc_ip_dump(adev); 4860 4861 r = amdgpu_gfx_sysfs_init(adev); 4862 if (r) 4863 return r; 4864 4865 return 0; 4866 } 4867 4868 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4869 { 4870 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4871 &adev->gfx.pfp.pfp_fw_gpu_addr, 4872 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4873 } 4874 4875 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4876 { 4877 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4878 &adev->gfx.ce.ce_fw_gpu_addr, 4879 (void **)&adev->gfx.ce.ce_fw_ptr); 4880 } 4881 4882 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4883 { 4884 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4885 &adev->gfx.me.me_fw_gpu_addr, 4886 (void **)&adev->gfx.me.me_fw_ptr); 4887 } 4888 4889 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 4890 { 4891 int i; 4892 struct amdgpu_device *adev = ip_block->adev; 4893 4894 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4895 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4896 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4897 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4898 4899 amdgpu_gfx_mqd_sw_fini(adev, 0); 4900 4901 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4902 amdgpu_gfx_kiq_fini(adev, 0); 4903 4904 amdgpu_gfx_cleaner_shader_sw_fini(adev); 4905 4906 gfx_v10_0_pfp_fini(adev); 4907 gfx_v10_0_ce_fini(adev); 4908 gfx_v10_0_me_fini(adev); 4909 gfx_v10_0_rlc_fini(adev); 4910 gfx_v10_0_mec_fini(adev); 4911 4912 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4913 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4914 4915 gfx_v10_0_free_microcode(adev); 4916 amdgpu_gfx_sysfs_fini(adev); 4917 4918 kfree(adev->gfx.ip_dump_core); 4919 kfree(adev->gfx.ip_dump_compute_queues); 4920 kfree(adev->gfx.ip_dump_gfx_queues); 4921 4922 return 0; 4923 } 4924 4925 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4926 u32 sh_num, u32 instance, int xcc_id) 4927 { 4928 u32 data; 4929 4930 if (instance == 0xffffffff) 4931 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4932 INSTANCE_BROADCAST_WRITES, 1); 4933 else 4934 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4935 instance); 4936 4937 if (se_num == 0xffffffff) 4938 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4939 1); 4940 else 4941 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4942 4943 if (sh_num == 0xffffffff) 4944 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4945 1); 4946 else 4947 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4948 4949 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4950 } 4951 4952 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4953 { 4954 u32 data, mask; 4955 4956 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4957 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4958 4959 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4960 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4961 4962 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4963 adev->gfx.config.max_sh_per_se); 4964 4965 return (~data) & mask; 4966 } 4967 4968 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4969 { 4970 int i, j; 4971 u32 data; 4972 u32 active_rbs = 0; 4973 u32 bitmap; 4974 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4975 adev->gfx.config.max_sh_per_se; 4976 4977 mutex_lock(&adev->grbm_idx_mutex); 4978 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4979 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4980 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4981 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 4982 IP_VERSION(10, 3, 0)) || 4983 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4984 IP_VERSION(10, 3, 3)) || 4985 (amdgpu_ip_version(adev, GC_HWIP, 0) == 4986 IP_VERSION(10, 3, 6))) && 4987 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4988 continue; 4989 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4990 data = gfx_v10_0_get_rb_active_bitmap(adev); 4991 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4992 rb_bitmap_width_per_sh); 4993 } 4994 } 4995 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4996 mutex_unlock(&adev->grbm_idx_mutex); 4997 4998 adev->gfx.config.backend_enable_mask = active_rbs; 4999 adev->gfx.config.num_rbs = hweight32(active_rbs); 5000 } 5001 5002 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5003 { 5004 uint32_t num_sc; 5005 uint32_t enabled_rb_per_sh; 5006 uint32_t active_rb_bitmap; 5007 uint32_t num_rb_per_sc; 5008 uint32_t num_packer_per_sc; 5009 uint32_t pa_sc_tile_steering_override; 5010 5011 /* for ASICs that integrates GFX v10.3 5012 * pa_sc_tile_steering_override should be set to 0 5013 */ 5014 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) 5015 return 0; 5016 5017 /* init num_sc */ 5018 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5019 adev->gfx.config.num_sc_per_sh; 5020 /* init num_rb_per_sc */ 5021 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5022 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5023 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5024 /* init num_packer_per_sc */ 5025 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5026 5027 pa_sc_tile_steering_override = 0; 5028 pa_sc_tile_steering_override |= 5029 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5030 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5031 pa_sc_tile_steering_override |= 5032 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5033 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5034 pa_sc_tile_steering_override |= 5035 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5036 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5037 5038 return pa_sc_tile_steering_override; 5039 } 5040 5041 #define DEFAULT_SH_MEM_BASES (0x6000) 5042 5043 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 5044 uint32_t first_vmid, 5045 uint32_t last_vmid) 5046 { 5047 uint32_t data; 5048 uint32_t trap_config_vmid_mask = 0; 5049 int i; 5050 5051 /* Calculate trap config vmid mask */ 5052 for (i = first_vmid; i < last_vmid; i++) 5053 trap_config_vmid_mask |= (1 << i); 5054 5055 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 5056 VMID_SEL, trap_config_vmid_mask); 5057 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 5058 TRAP_EN, 1); 5059 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 5060 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 5061 5062 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 5063 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 5064 } 5065 5066 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5067 { 5068 int i; 5069 uint32_t sh_mem_bases; 5070 5071 /* 5072 * Configure apertures: 5073 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5074 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5075 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5076 */ 5077 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5078 5079 mutex_lock(&adev->srbm_mutex); 5080 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5081 nv_grbm_select(adev, 0, 0, 0, i); 5082 /* CP and shaders */ 5083 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5084 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5085 } 5086 nv_grbm_select(adev, 0, 0, 0, 0); 5087 mutex_unlock(&adev->srbm_mutex); 5088 5089 /* 5090 * Initialize all compute VMIDs to have no GDS, GWS, or OA 5091 * access. These should be enabled by FW for target VMIDs. 5092 */ 5093 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5094 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5095 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5096 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5097 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5098 } 5099 5100 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 5101 AMDGPU_NUM_VMID); 5102 } 5103 5104 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5105 { 5106 int vmid; 5107 5108 /* 5109 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5110 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5111 * the driver can enable them for graphics. VMID0 should maintain 5112 * access so that HWS firmware can save/restore entries. 5113 */ 5114 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5115 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5116 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5117 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5118 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5119 } 5120 } 5121 5122 5123 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5124 { 5125 int i, j, k; 5126 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5127 u32 tmp, wgp_active_bitmap = 0; 5128 u32 gcrd_targets_disable_tcp = 0; 5129 u32 utcl_invreq_disable = 0; 5130 /* 5131 * GCRD_TARGETS_DISABLE field contains 5132 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5133 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5134 */ 5135 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5136 2 * max_wgp_per_sh + /* TCP */ 5137 max_wgp_per_sh + /* SQC */ 5138 4); /* GL1C */ 5139 /* 5140 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5141 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5142 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5143 */ 5144 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5145 2 * max_wgp_per_sh + /* TCP */ 5146 2 * max_wgp_per_sh + /* SQC */ 5147 4 + /* RMI */ 5148 1); /* SQG */ 5149 5150 mutex_lock(&adev->grbm_idx_mutex); 5151 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5152 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5153 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5154 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5155 /* 5156 * Set corresponding TCP bits for the inactive WGPs in 5157 * GCRD_SA_TARGETS_DISABLE 5158 */ 5159 gcrd_targets_disable_tcp = 0; 5160 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5161 utcl_invreq_disable = 0; 5162 5163 for (k = 0; k < max_wgp_per_sh; k++) { 5164 if (!(wgp_active_bitmap & (1 << k))) { 5165 gcrd_targets_disable_tcp |= 3 << (2 * k); 5166 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5167 utcl_invreq_disable |= (3 << (2 * k)) | 5168 (3 << (2 * (max_wgp_per_sh + k))); 5169 } 5170 } 5171 5172 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5173 /* only override TCP & SQC bits */ 5174 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5175 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5176 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5177 5178 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5179 /* only override TCP & SQC bits */ 5180 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5181 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5182 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5183 } 5184 } 5185 5186 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5187 mutex_unlock(&adev->grbm_idx_mutex); 5188 } 5189 5190 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5191 { 5192 /* TCCs are global (not instanced). */ 5193 uint32_t tcc_disable; 5194 5195 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) { 5196 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5197 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5198 } else { 5199 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5200 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5201 } 5202 5203 adev->gfx.config.tcc_disabled_mask = 5204 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5205 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5206 } 5207 5208 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5209 { 5210 u32 tmp; 5211 int i; 5212 5213 if (!amdgpu_sriov_vf(adev)) 5214 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5215 5216 gfx_v10_0_setup_rb(adev); 5217 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5218 gfx_v10_0_get_tcc_info(adev); 5219 adev->gfx.config.pa_sc_tile_steering_override = 5220 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5221 5222 /* XXX SH_MEM regs */ 5223 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5224 mutex_lock(&adev->srbm_mutex); 5225 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5226 nv_grbm_select(adev, 0, 0, 0, i); 5227 /* CP and shaders */ 5228 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5229 if (i != 0) { 5230 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5231 (adev->gmc.private_aperture_start >> 48)); 5232 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5233 (adev->gmc.shared_aperture_start >> 48)); 5234 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5235 } 5236 } 5237 nv_grbm_select(adev, 0, 0, 0, 0); 5238 5239 mutex_unlock(&adev->srbm_mutex); 5240 5241 gfx_v10_0_init_compute_vmid(adev); 5242 gfx_v10_0_init_gds_vmid(adev); 5243 5244 } 5245 5246 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev, 5247 int me, int pipe) 5248 { 5249 if (me != 0) 5250 return 0; 5251 5252 switch (pipe) { 5253 case 0: 5254 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 5255 case 1: 5256 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 5257 default: 5258 return 0; 5259 } 5260 } 5261 5262 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev, 5263 int me, int pipe) 5264 { 5265 /* 5266 * amdgpu controls only the first MEC. That's why this function only 5267 * handles the setting of interrupts for this specific MEC. All other 5268 * pipes' interrupts are set by amdkfd. 5269 */ 5270 if (me != 1) 5271 return 0; 5272 5273 switch (pipe) { 5274 case 0: 5275 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5276 case 1: 5277 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5278 case 2: 5279 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5280 case 3: 5281 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5282 default: 5283 return 0; 5284 } 5285 } 5286 5287 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5288 bool enable) 5289 { 5290 u32 tmp, cp_int_cntl_reg; 5291 int i, j; 5292 5293 if (amdgpu_sriov_vf(adev)) 5294 return; 5295 5296 for (i = 0; i < adev->gfx.me.num_me; i++) { 5297 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5298 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 5299 5300 if (cp_int_cntl_reg) { 5301 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5302 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5303 enable ? 1 : 0); 5304 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5305 enable ? 1 : 0); 5306 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5307 enable ? 1 : 0); 5308 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5309 enable ? 1 : 0); 5310 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 5311 } 5312 } 5313 } 5314 } 5315 5316 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5317 { 5318 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5319 5320 /* csib */ 5321 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 5322 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5323 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5324 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5325 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5326 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5327 } else { 5328 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5329 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5330 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5331 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5332 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5333 } 5334 return 0; 5335 } 5336 5337 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5338 { 5339 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5340 5341 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5342 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5343 } 5344 5345 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5346 { 5347 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5348 udelay(50); 5349 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5350 udelay(50); 5351 } 5352 5353 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5354 bool enable) 5355 { 5356 uint32_t rlc_pg_cntl; 5357 5358 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5359 5360 if (!enable) { 5361 /* RLC_PG_CNTL[23] = 0 (default) 5362 * RLC will wait for handshake acks with SMU 5363 * GFXOFF will be enabled 5364 * RLC_PG_CNTL[23] = 1 5365 * RLC will not issue any message to SMU 5366 * hence no handshake between SMU & RLC 5367 * GFXOFF will be disabled 5368 */ 5369 rlc_pg_cntl |= 0x800000; 5370 } else 5371 rlc_pg_cntl &= ~0x800000; 5372 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5373 } 5374 5375 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5376 { 5377 /* 5378 * TODO: enable rlc & smu handshake until smu 5379 * and gfxoff feature works as expected 5380 */ 5381 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5382 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5383 5384 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5385 udelay(50); 5386 } 5387 5388 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5389 { 5390 uint32_t tmp; 5391 5392 /* enable Save Restore Machine */ 5393 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5394 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5395 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5396 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5397 } 5398 5399 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5400 { 5401 const struct rlc_firmware_header_v2_0 *hdr; 5402 const __le32 *fw_data; 5403 unsigned int i, fw_size; 5404 5405 if (!adev->gfx.rlc_fw) 5406 return -EINVAL; 5407 5408 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5409 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5410 5411 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5412 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5413 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5414 5415 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5416 RLCG_UCODE_LOADING_START_ADDRESS); 5417 5418 for (i = 0; i < fw_size; i++) 5419 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5420 le32_to_cpup(fw_data++)); 5421 5422 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5423 5424 return 0; 5425 } 5426 5427 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5428 { 5429 int r; 5430 5431 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5432 adev->psp.autoload_supported) { 5433 5434 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5435 if (r) 5436 return r; 5437 5438 gfx_v10_0_init_csb(adev); 5439 5440 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5441 5442 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5443 gfx_v10_0_rlc_enable_srm(adev); 5444 } else { 5445 if (amdgpu_sriov_vf(adev)) { 5446 gfx_v10_0_init_csb(adev); 5447 return 0; 5448 } 5449 5450 adev->gfx.rlc.funcs->stop(adev); 5451 5452 /* disable CG */ 5453 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5454 5455 /* disable PG */ 5456 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5457 5458 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5459 /* legacy rlc firmware loading */ 5460 r = gfx_v10_0_rlc_load_microcode(adev); 5461 if (r) 5462 return r; 5463 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5464 /* rlc backdoor autoload firmware */ 5465 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5466 if (r) 5467 return r; 5468 } 5469 5470 gfx_v10_0_init_csb(adev); 5471 5472 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5473 5474 adev->gfx.rlc.funcs->start(adev); 5475 5476 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5477 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5478 if (r) 5479 return r; 5480 } 5481 } 5482 5483 return 0; 5484 } 5485 5486 static struct { 5487 FIRMWARE_ID id; 5488 unsigned int offset; 5489 unsigned int size; 5490 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5491 5492 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5493 { 5494 int ret; 5495 RLC_TABLE_OF_CONTENT *rlc_toc; 5496 5497 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5498 AMDGPU_GEM_DOMAIN_GTT, 5499 &adev->gfx.rlc.rlc_toc_bo, 5500 &adev->gfx.rlc.rlc_toc_gpu_addr, 5501 (void **)&adev->gfx.rlc.rlc_toc_buf); 5502 if (ret) { 5503 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5504 return ret; 5505 } 5506 5507 /* Copy toc from psp sos fw to rlc toc buffer */ 5508 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5509 5510 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5511 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5512 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5513 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5514 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5515 /* Offset needs 4KB alignment */ 5516 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5517 } 5518 5519 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5520 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5521 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5522 5523 rlc_toc++; 5524 } 5525 5526 return 0; 5527 } 5528 5529 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5530 { 5531 uint32_t total_size = 0; 5532 FIRMWARE_ID id; 5533 int ret; 5534 5535 ret = gfx_v10_0_parse_rlc_toc(adev); 5536 if (ret) { 5537 dev_err(adev->dev, "failed to parse rlc toc\n"); 5538 return 0; 5539 } 5540 5541 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5542 total_size += rlc_autoload_info[id].size; 5543 5544 /* In case the offset in rlc toc ucode is aligned */ 5545 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5546 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5547 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5548 5549 return total_size; 5550 } 5551 5552 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5553 { 5554 int r; 5555 uint32_t total_size; 5556 5557 total_size = gfx_v10_0_calc_toc_total_size(adev); 5558 5559 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5560 AMDGPU_GEM_DOMAIN_GTT, 5561 &adev->gfx.rlc.rlc_autoload_bo, 5562 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5563 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5564 if (r) { 5565 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5566 return r; 5567 } 5568 5569 return 0; 5570 } 5571 5572 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5573 { 5574 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5575 &adev->gfx.rlc.rlc_toc_gpu_addr, 5576 (void **)&adev->gfx.rlc.rlc_toc_buf); 5577 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5578 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5579 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5580 } 5581 5582 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5583 FIRMWARE_ID id, 5584 const void *fw_data, 5585 uint32_t fw_size) 5586 { 5587 uint32_t toc_offset; 5588 uint32_t toc_fw_size; 5589 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5590 5591 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5592 return; 5593 5594 toc_offset = rlc_autoload_info[id].offset; 5595 toc_fw_size = rlc_autoload_info[id].size; 5596 5597 if (fw_size == 0) 5598 fw_size = toc_fw_size; 5599 5600 if (fw_size > toc_fw_size) 5601 fw_size = toc_fw_size; 5602 5603 memcpy(ptr + toc_offset, fw_data, fw_size); 5604 5605 if (fw_size < toc_fw_size) 5606 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5607 } 5608 5609 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5610 { 5611 void *data; 5612 uint32_t size; 5613 5614 data = adev->gfx.rlc.rlc_toc_buf; 5615 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5616 5617 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5618 FIRMWARE_ID_RLC_TOC, 5619 data, size); 5620 } 5621 5622 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5623 { 5624 const __le32 *fw_data; 5625 uint32_t fw_size; 5626 const struct gfx_firmware_header_v1_0 *cp_hdr; 5627 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5628 5629 /* pfp ucode */ 5630 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5631 adev->gfx.pfp_fw->data; 5632 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5633 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5634 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5635 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5636 FIRMWARE_ID_CP_PFP, 5637 fw_data, fw_size); 5638 5639 /* ce ucode */ 5640 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5641 adev->gfx.ce_fw->data; 5642 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5643 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5644 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5645 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5646 FIRMWARE_ID_CP_CE, 5647 fw_data, fw_size); 5648 5649 /* me ucode */ 5650 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5651 adev->gfx.me_fw->data; 5652 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5653 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5654 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5655 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5656 FIRMWARE_ID_CP_ME, 5657 fw_data, fw_size); 5658 5659 /* rlc ucode */ 5660 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5661 adev->gfx.rlc_fw->data; 5662 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5663 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5664 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5665 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5666 FIRMWARE_ID_RLC_G_UCODE, 5667 fw_data, fw_size); 5668 5669 /* mec1 ucode */ 5670 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5671 adev->gfx.mec_fw->data; 5672 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5673 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5674 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5675 cp_hdr->jt_size * 4; 5676 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5677 FIRMWARE_ID_CP_MEC, 5678 fw_data, fw_size); 5679 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5680 } 5681 5682 /* Temporarily put sdma part here */ 5683 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5684 { 5685 const __le32 *fw_data; 5686 uint32_t fw_size; 5687 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5688 int i; 5689 5690 for (i = 0; i < adev->sdma.num_instances; i++) { 5691 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5692 adev->sdma.instance[i].fw->data; 5693 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5694 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5695 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5696 5697 if (i == 0) { 5698 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5699 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5700 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5701 FIRMWARE_ID_SDMA0_JT, 5702 (uint32_t *)fw_data + 5703 sdma_hdr->jt_offset, 5704 sdma_hdr->jt_size * 4); 5705 } else if (i == 1) { 5706 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5707 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5708 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5709 FIRMWARE_ID_SDMA1_JT, 5710 (uint32_t *)fw_data + 5711 sdma_hdr->jt_offset, 5712 sdma_hdr->jt_size * 4); 5713 } 5714 } 5715 } 5716 5717 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5718 { 5719 uint32_t rlc_g_offset, rlc_g_size, tmp; 5720 uint64_t gpu_addr; 5721 5722 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5723 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5724 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5725 5726 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5727 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5728 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5729 5730 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5731 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5732 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5733 5734 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5735 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5736 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5737 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5738 return -EINVAL; 5739 } 5740 5741 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5742 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5743 DRM_ERROR("RLC ROM should halt itself\n"); 5744 return -EINVAL; 5745 } 5746 5747 return 0; 5748 } 5749 5750 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5751 { 5752 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5753 uint32_t tmp; 5754 int i; 5755 uint64_t addr; 5756 5757 /* Trigger an invalidation of the L1 instruction caches */ 5758 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5759 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5760 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5761 5762 /* Wait for invalidation complete */ 5763 for (i = 0; i < usec_timeout; i++) { 5764 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5765 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5766 INVALIDATE_CACHE_COMPLETE)) 5767 break; 5768 udelay(1); 5769 } 5770 5771 if (i >= usec_timeout) { 5772 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5773 return -EINVAL; 5774 } 5775 5776 /* Program me ucode address into intruction cache address register */ 5777 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5778 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5779 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5780 lower_32_bits(addr) & 0xFFFFF000); 5781 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5782 upper_32_bits(addr)); 5783 5784 return 0; 5785 } 5786 5787 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5788 { 5789 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5790 uint32_t tmp; 5791 int i; 5792 uint64_t addr; 5793 5794 /* Trigger an invalidation of the L1 instruction caches */ 5795 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5796 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5797 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5798 5799 /* Wait for invalidation complete */ 5800 for (i = 0; i < usec_timeout; i++) { 5801 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5802 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5803 INVALIDATE_CACHE_COMPLETE)) 5804 break; 5805 udelay(1); 5806 } 5807 5808 if (i >= usec_timeout) { 5809 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5810 return -EINVAL; 5811 } 5812 5813 /* Program ce ucode address into intruction cache address register */ 5814 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5815 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5816 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5817 lower_32_bits(addr) & 0xFFFFF000); 5818 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5819 upper_32_bits(addr)); 5820 5821 return 0; 5822 } 5823 5824 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5825 { 5826 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5827 uint32_t tmp; 5828 int i; 5829 uint64_t addr; 5830 5831 /* Trigger an invalidation of the L1 instruction caches */ 5832 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5833 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5834 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5835 5836 /* Wait for invalidation complete */ 5837 for (i = 0; i < usec_timeout; i++) { 5838 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5839 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5840 INVALIDATE_CACHE_COMPLETE)) 5841 break; 5842 udelay(1); 5843 } 5844 5845 if (i >= usec_timeout) { 5846 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5847 return -EINVAL; 5848 } 5849 5850 /* Program pfp ucode address into intruction cache address register */ 5851 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5852 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5853 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5854 lower_32_bits(addr) & 0xFFFFF000); 5855 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5856 upper_32_bits(addr)); 5857 5858 return 0; 5859 } 5860 5861 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5862 { 5863 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5864 uint32_t tmp; 5865 int i; 5866 uint64_t addr; 5867 5868 /* Trigger an invalidation of the L1 instruction caches */ 5869 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5870 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5871 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5872 5873 /* Wait for invalidation complete */ 5874 for (i = 0; i < usec_timeout; i++) { 5875 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5876 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5877 INVALIDATE_CACHE_COMPLETE)) 5878 break; 5879 udelay(1); 5880 } 5881 5882 if (i >= usec_timeout) { 5883 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5884 return -EINVAL; 5885 } 5886 5887 /* Program mec1 ucode address into intruction cache address register */ 5888 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5889 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5890 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5891 lower_32_bits(addr) & 0xFFFFF000); 5892 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5893 upper_32_bits(addr)); 5894 5895 return 0; 5896 } 5897 5898 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5899 { 5900 uint32_t cp_status; 5901 uint32_t bootload_status; 5902 int i, r; 5903 5904 for (i = 0; i < adev->usec_timeout; i++) { 5905 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5906 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5907 if ((cp_status == 0) && 5908 (REG_GET_FIELD(bootload_status, 5909 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5910 break; 5911 } 5912 udelay(1); 5913 } 5914 5915 if (i >= adev->usec_timeout) { 5916 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5917 return -ETIMEDOUT; 5918 } 5919 5920 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5921 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5922 if (r) 5923 return r; 5924 5925 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5926 if (r) 5927 return r; 5928 5929 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5930 if (r) 5931 return r; 5932 5933 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5934 if (r) 5935 return r; 5936 } 5937 5938 return 0; 5939 } 5940 5941 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5942 { 5943 int i; 5944 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5945 5946 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5947 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5948 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5949 5950 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 5951 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5952 else 5953 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5954 5955 if (adev->job_hang && !enable) 5956 return 0; 5957 5958 for (i = 0; i < adev->usec_timeout; i++) { 5959 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5960 break; 5961 udelay(1); 5962 } 5963 5964 if (i >= adev->usec_timeout) 5965 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5966 5967 return 0; 5968 } 5969 5970 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5971 { 5972 int r; 5973 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5974 const __le32 *fw_data; 5975 unsigned int i, fw_size; 5976 uint32_t tmp; 5977 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5978 5979 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5980 adev->gfx.pfp_fw->data; 5981 5982 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5983 5984 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5985 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5986 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5987 5988 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5989 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5990 &adev->gfx.pfp.pfp_fw_obj, 5991 &adev->gfx.pfp.pfp_fw_gpu_addr, 5992 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5993 if (r) { 5994 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5995 gfx_v10_0_pfp_fini(adev); 5996 return r; 5997 } 5998 5999 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 6000 6001 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 6002 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 6003 6004 /* Trigger an invalidation of the L1 instruction caches */ 6005 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6006 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6007 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 6008 6009 /* Wait for invalidation complete */ 6010 for (i = 0; i < usec_timeout; i++) { 6011 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 6012 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 6013 INVALIDATE_CACHE_COMPLETE)) 6014 break; 6015 udelay(1); 6016 } 6017 6018 if (i >= usec_timeout) { 6019 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6020 return -EINVAL; 6021 } 6022 6023 if (amdgpu_emu_mode == 1) 6024 adev->hdp.funcs->flush_hdp(adev, NULL); 6025 6026 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6027 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6028 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6029 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6030 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6031 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6032 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6033 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6034 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6035 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6036 6037 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6038 6039 for (i = 0; i < pfp_hdr->jt_size; i++) 6040 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6041 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6042 6043 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6044 6045 return 0; 6046 } 6047 6048 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6049 { 6050 int r; 6051 const struct gfx_firmware_header_v1_0 *ce_hdr; 6052 const __le32 *fw_data; 6053 unsigned int i, fw_size; 6054 uint32_t tmp; 6055 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6056 6057 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6058 adev->gfx.ce_fw->data; 6059 6060 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6061 6062 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6063 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6064 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6065 6066 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6067 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6068 &adev->gfx.ce.ce_fw_obj, 6069 &adev->gfx.ce.ce_fw_gpu_addr, 6070 (void **)&adev->gfx.ce.ce_fw_ptr); 6071 if (r) { 6072 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6073 gfx_v10_0_ce_fini(adev); 6074 return r; 6075 } 6076 6077 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6078 6079 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6080 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6081 6082 /* Trigger an invalidation of the L1 instruction caches */ 6083 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6084 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6085 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6086 6087 /* Wait for invalidation complete */ 6088 for (i = 0; i < usec_timeout; i++) { 6089 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6090 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6091 INVALIDATE_CACHE_COMPLETE)) 6092 break; 6093 udelay(1); 6094 } 6095 6096 if (i >= usec_timeout) { 6097 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6098 return -EINVAL; 6099 } 6100 6101 if (amdgpu_emu_mode == 1) 6102 adev->hdp.funcs->flush_hdp(adev, NULL); 6103 6104 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6105 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6106 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6107 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6108 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6109 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6110 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6111 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6112 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6113 6114 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6115 6116 for (i = 0; i < ce_hdr->jt_size; i++) 6117 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6118 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6119 6120 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6121 6122 return 0; 6123 } 6124 6125 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6126 { 6127 int r; 6128 const struct gfx_firmware_header_v1_0 *me_hdr; 6129 const __le32 *fw_data; 6130 unsigned int i, fw_size; 6131 uint32_t tmp; 6132 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6133 6134 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6135 adev->gfx.me_fw->data; 6136 6137 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6138 6139 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6140 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6141 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6142 6143 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6144 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6145 &adev->gfx.me.me_fw_obj, 6146 &adev->gfx.me.me_fw_gpu_addr, 6147 (void **)&adev->gfx.me.me_fw_ptr); 6148 if (r) { 6149 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6150 gfx_v10_0_me_fini(adev); 6151 return r; 6152 } 6153 6154 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6155 6156 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6157 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6158 6159 /* Trigger an invalidation of the L1 instruction caches */ 6160 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6161 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6162 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6163 6164 /* Wait for invalidation complete */ 6165 for (i = 0; i < usec_timeout; i++) { 6166 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6167 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6168 INVALIDATE_CACHE_COMPLETE)) 6169 break; 6170 udelay(1); 6171 } 6172 6173 if (i >= usec_timeout) { 6174 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6175 return -EINVAL; 6176 } 6177 6178 if (amdgpu_emu_mode == 1) 6179 adev->hdp.funcs->flush_hdp(adev, NULL); 6180 6181 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6182 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6183 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6184 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6185 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6186 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6187 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6188 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6189 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6190 6191 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6192 6193 for (i = 0; i < me_hdr->jt_size; i++) 6194 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6195 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6196 6197 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6198 6199 return 0; 6200 } 6201 6202 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6203 { 6204 int r; 6205 6206 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6207 return -EINVAL; 6208 6209 gfx_v10_0_cp_gfx_enable(adev, false); 6210 6211 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6212 if (r) { 6213 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6214 return r; 6215 } 6216 6217 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6218 if (r) { 6219 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6220 return r; 6221 } 6222 6223 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6224 if (r) { 6225 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6226 return r; 6227 } 6228 6229 return 0; 6230 } 6231 6232 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6233 { 6234 struct amdgpu_ring *ring; 6235 const struct cs_section_def *sect = NULL; 6236 const struct cs_extent_def *ext = NULL; 6237 int r, i; 6238 int ctx_reg_offset; 6239 6240 /* init the CP */ 6241 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6242 adev->gfx.config.max_hw_contexts - 1); 6243 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6244 6245 gfx_v10_0_cp_gfx_enable(adev, true); 6246 6247 ring = &adev->gfx.gfx_ring[0]; 6248 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6249 if (r) { 6250 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6251 return r; 6252 } 6253 6254 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6255 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6256 6257 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6258 amdgpu_ring_write(ring, 0x80000000); 6259 amdgpu_ring_write(ring, 0x80000000); 6260 6261 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6262 for (ext = sect->section; ext->extent != NULL; ++ext) { 6263 if (sect->id == SECT_CONTEXT) { 6264 amdgpu_ring_write(ring, 6265 PACKET3(PACKET3_SET_CONTEXT_REG, 6266 ext->reg_count)); 6267 amdgpu_ring_write(ring, ext->reg_index - 6268 PACKET3_SET_CONTEXT_REG_START); 6269 for (i = 0; i < ext->reg_count; i++) 6270 amdgpu_ring_write(ring, ext->extent[i]); 6271 } 6272 } 6273 } 6274 6275 ctx_reg_offset = 6276 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6277 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6278 amdgpu_ring_write(ring, ctx_reg_offset); 6279 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6280 6281 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6282 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6283 6284 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6285 amdgpu_ring_write(ring, 0); 6286 6287 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6288 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6289 amdgpu_ring_write(ring, 0x8000); 6290 amdgpu_ring_write(ring, 0x8000); 6291 6292 amdgpu_ring_commit(ring); 6293 6294 /* submit cs packet to copy state 0 to next available state */ 6295 if (adev->gfx.num_gfx_rings > 1) { 6296 /* maximum supported gfx ring is 2 */ 6297 ring = &adev->gfx.gfx_ring[1]; 6298 r = amdgpu_ring_alloc(ring, 2); 6299 if (r) { 6300 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6301 return r; 6302 } 6303 6304 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6305 amdgpu_ring_write(ring, 0); 6306 6307 amdgpu_ring_commit(ring); 6308 } 6309 return 0; 6310 } 6311 6312 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6313 CP_PIPE_ID pipe) 6314 { 6315 u32 tmp; 6316 6317 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6318 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6319 6320 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6321 } 6322 6323 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6324 struct amdgpu_ring *ring) 6325 { 6326 u32 tmp; 6327 6328 if (!amdgpu_async_gfx_ring) { 6329 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6330 if (ring->use_doorbell) { 6331 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6332 DOORBELL_OFFSET, ring->doorbell_index); 6333 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6334 DOORBELL_EN, 1); 6335 } else { 6336 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6337 DOORBELL_EN, 0); 6338 } 6339 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6340 } 6341 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6342 case IP_VERSION(10, 3, 0): 6343 case IP_VERSION(10, 3, 2): 6344 case IP_VERSION(10, 3, 1): 6345 case IP_VERSION(10, 3, 4): 6346 case IP_VERSION(10, 3, 5): 6347 case IP_VERSION(10, 3, 6): 6348 case IP_VERSION(10, 3, 3): 6349 case IP_VERSION(10, 3, 7): 6350 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6351 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6352 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6353 6354 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6355 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6356 break; 6357 default: 6358 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6359 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6360 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6361 6362 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6363 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6364 break; 6365 } 6366 } 6367 6368 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6369 { 6370 struct amdgpu_ring *ring; 6371 u32 tmp; 6372 u32 rb_bufsz; 6373 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6374 6375 /* Set the write pointer delay */ 6376 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6377 6378 /* set the RB to use vmid 0 */ 6379 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6380 6381 /* Init gfx ring 0 for pipe 0 */ 6382 mutex_lock(&adev->srbm_mutex); 6383 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6384 6385 /* Set ring buffer size */ 6386 ring = &adev->gfx.gfx_ring[0]; 6387 rb_bufsz = order_base_2(ring->ring_size / 8); 6388 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6389 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6390 #ifdef __BIG_ENDIAN 6391 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6392 #endif 6393 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6394 6395 /* Initialize the ring buffer's write pointers */ 6396 ring->wptr = 0; 6397 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6398 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6399 6400 /* set the wb address whether it's enabled or not */ 6401 rptr_addr = ring->rptr_gpu_addr; 6402 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6403 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6404 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6405 6406 wptr_gpu_addr = ring->wptr_gpu_addr; 6407 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6408 lower_32_bits(wptr_gpu_addr)); 6409 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6410 upper_32_bits(wptr_gpu_addr)); 6411 6412 mdelay(1); 6413 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6414 6415 rb_addr = ring->gpu_addr >> 8; 6416 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6417 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6418 6419 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6420 6421 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6422 mutex_unlock(&adev->srbm_mutex); 6423 6424 /* Init gfx ring 1 for pipe 1 */ 6425 if (adev->gfx.num_gfx_rings > 1) { 6426 mutex_lock(&adev->srbm_mutex); 6427 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6428 /* maximum supported gfx ring is 2 */ 6429 ring = &adev->gfx.gfx_ring[1]; 6430 rb_bufsz = order_base_2(ring->ring_size / 8); 6431 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6432 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6433 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6434 /* Initialize the ring buffer's write pointers */ 6435 ring->wptr = 0; 6436 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6437 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6438 /* Set the wb address whether it's enabled or not */ 6439 rptr_addr = ring->rptr_gpu_addr; 6440 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6441 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6442 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6443 wptr_gpu_addr = ring->wptr_gpu_addr; 6444 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6445 lower_32_bits(wptr_gpu_addr)); 6446 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6447 upper_32_bits(wptr_gpu_addr)); 6448 6449 mdelay(1); 6450 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6451 6452 rb_addr = ring->gpu_addr >> 8; 6453 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6454 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6455 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6456 6457 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6458 mutex_unlock(&adev->srbm_mutex); 6459 } 6460 /* Switch to pipe 0 */ 6461 mutex_lock(&adev->srbm_mutex); 6462 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6463 mutex_unlock(&adev->srbm_mutex); 6464 6465 /* start the ring */ 6466 gfx_v10_0_cp_gfx_start(adev); 6467 6468 return 0; 6469 } 6470 6471 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6472 { 6473 if (enable) { 6474 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6475 case IP_VERSION(10, 3, 0): 6476 case IP_VERSION(10, 3, 2): 6477 case IP_VERSION(10, 3, 1): 6478 case IP_VERSION(10, 3, 4): 6479 case IP_VERSION(10, 3, 5): 6480 case IP_VERSION(10, 3, 6): 6481 case IP_VERSION(10, 3, 3): 6482 case IP_VERSION(10, 3, 7): 6483 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6484 break; 6485 default: 6486 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6487 break; 6488 } 6489 } else { 6490 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6491 case IP_VERSION(10, 3, 0): 6492 case IP_VERSION(10, 3, 2): 6493 case IP_VERSION(10, 3, 1): 6494 case IP_VERSION(10, 3, 4): 6495 case IP_VERSION(10, 3, 5): 6496 case IP_VERSION(10, 3, 6): 6497 case IP_VERSION(10, 3, 3): 6498 case IP_VERSION(10, 3, 7): 6499 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6500 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6501 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6502 break; 6503 default: 6504 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6505 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6506 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6507 break; 6508 } 6509 adev->gfx.kiq[0].ring.sched.ready = false; 6510 } 6511 udelay(50); 6512 } 6513 6514 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6515 { 6516 const struct gfx_firmware_header_v1_0 *mec_hdr; 6517 const __le32 *fw_data; 6518 unsigned int i; 6519 u32 tmp; 6520 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6521 6522 if (!adev->gfx.mec_fw) 6523 return -EINVAL; 6524 6525 gfx_v10_0_cp_compute_enable(adev, false); 6526 6527 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6528 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6529 6530 fw_data = (const __le32 *) 6531 (adev->gfx.mec_fw->data + 6532 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6533 6534 /* Trigger an invalidation of the L1 instruction caches */ 6535 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6536 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6537 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6538 6539 /* Wait for invalidation complete */ 6540 for (i = 0; i < usec_timeout; i++) { 6541 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6542 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6543 INVALIDATE_CACHE_COMPLETE)) 6544 break; 6545 udelay(1); 6546 } 6547 6548 if (i >= usec_timeout) { 6549 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6550 return -EINVAL; 6551 } 6552 6553 if (amdgpu_emu_mode == 1) 6554 adev->hdp.funcs->flush_hdp(adev, NULL); 6555 6556 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6557 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6558 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6559 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6560 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6561 6562 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6563 0xFFFFF000); 6564 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6565 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6566 6567 /* MEC1 */ 6568 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6569 6570 for (i = 0; i < mec_hdr->jt_size; i++) 6571 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6572 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6573 6574 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6575 6576 /* 6577 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6578 * different microcode than MEC1. 6579 */ 6580 6581 return 0; 6582 } 6583 6584 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6585 { 6586 uint32_t tmp; 6587 struct amdgpu_device *adev = ring->adev; 6588 6589 /* tell RLC which is KIQ queue */ 6590 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 6591 case IP_VERSION(10, 3, 0): 6592 case IP_VERSION(10, 3, 2): 6593 case IP_VERSION(10, 3, 1): 6594 case IP_VERSION(10, 3, 4): 6595 case IP_VERSION(10, 3, 5): 6596 case IP_VERSION(10, 3, 6): 6597 case IP_VERSION(10, 3, 3): 6598 case IP_VERSION(10, 3, 7): 6599 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6600 tmp &= 0xffffff00; 6601 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6602 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80); 6603 break; 6604 default: 6605 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6606 tmp &= 0xffffff00; 6607 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6608 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80); 6609 break; 6610 } 6611 } 6612 6613 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6614 struct v10_gfx_mqd *mqd, 6615 struct amdgpu_mqd_prop *prop) 6616 { 6617 bool priority = 0; 6618 u32 tmp; 6619 6620 /* set up default queue priority level 6621 * 0x0 = low priority, 0x1 = high priority 6622 */ 6623 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6624 priority = 1; 6625 6626 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6627 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6628 mqd->cp_gfx_hqd_queue_priority = tmp; 6629 } 6630 6631 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6632 struct amdgpu_mqd_prop *prop) 6633 { 6634 struct v10_gfx_mqd *mqd = m; 6635 uint64_t hqd_gpu_addr, wb_gpu_addr; 6636 uint32_t tmp; 6637 uint32_t rb_bufsz; 6638 6639 /* set up gfx hqd wptr */ 6640 mqd->cp_gfx_hqd_wptr = 0; 6641 mqd->cp_gfx_hqd_wptr_hi = 0; 6642 6643 /* set the pointer to the MQD */ 6644 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6645 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6646 6647 /* set up mqd control */ 6648 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6649 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6650 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6651 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6652 mqd->cp_gfx_mqd_control = tmp; 6653 6654 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6655 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6656 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6657 mqd->cp_gfx_hqd_vmid = 0; 6658 6659 /* set up gfx queue priority */ 6660 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6661 6662 /* set up time quantum */ 6663 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6664 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6665 mqd->cp_gfx_hqd_quantum = tmp; 6666 6667 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6668 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6669 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6670 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6671 6672 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6673 wb_gpu_addr = prop->rptr_gpu_addr; 6674 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6675 mqd->cp_gfx_hqd_rptr_addr_hi = 6676 upper_32_bits(wb_gpu_addr) & 0xffff; 6677 6678 /* set up rb_wptr_poll addr */ 6679 wb_gpu_addr = prop->wptr_gpu_addr; 6680 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6681 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6682 6683 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6684 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6685 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6686 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6687 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6688 #ifdef __BIG_ENDIAN 6689 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6690 #endif 6691 mqd->cp_gfx_hqd_cntl = tmp; 6692 6693 /* set up cp_doorbell_control */ 6694 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6695 if (prop->use_doorbell) { 6696 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6697 DOORBELL_OFFSET, prop->doorbell_index); 6698 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6699 DOORBELL_EN, 1); 6700 } else 6701 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6702 DOORBELL_EN, 0); 6703 mqd->cp_rb_doorbell_control = tmp; 6704 6705 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6706 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6707 6708 /* active the queue */ 6709 mqd->cp_gfx_hqd_active = 1; 6710 6711 return 0; 6712 } 6713 6714 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 6715 { 6716 struct amdgpu_device *adev = ring->adev; 6717 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6718 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6719 6720 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 6721 memset((void *)mqd, 0, sizeof(*mqd)); 6722 mutex_lock(&adev->srbm_mutex); 6723 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6724 amdgpu_ring_init_mqd(ring); 6725 6726 /* 6727 * if there are 2 gfx rings, set the lower doorbell 6728 * range of the first ring, otherwise the range of 6729 * the second ring will override the first ring 6730 */ 6731 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6732 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6733 6734 nv_grbm_select(adev, 0, 0, 0, 0); 6735 mutex_unlock(&adev->srbm_mutex); 6736 if (adev->gfx.me.mqd_backup[mqd_idx]) 6737 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6738 } else { 6739 mutex_lock(&adev->srbm_mutex); 6740 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6741 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6742 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6743 6744 nv_grbm_select(adev, 0, 0, 0, 0); 6745 mutex_unlock(&adev->srbm_mutex); 6746 /* restore mqd with the backup copy */ 6747 if (adev->gfx.me.mqd_backup[mqd_idx]) 6748 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6749 /* reset the ring */ 6750 ring->wptr = 0; 6751 *ring->wptr_cpu_addr = 0; 6752 amdgpu_ring_clear_ring(ring); 6753 } 6754 6755 return 0; 6756 } 6757 6758 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6759 { 6760 int r, i; 6761 struct amdgpu_ring *ring; 6762 6763 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6764 ring = &adev->gfx.gfx_ring[i]; 6765 6766 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6767 if (unlikely(r != 0)) 6768 return r; 6769 6770 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6771 if (!r) { 6772 r = gfx_v10_0_kgq_init_queue(ring, false); 6773 amdgpu_bo_kunmap(ring->mqd_obj); 6774 ring->mqd_ptr = NULL; 6775 } 6776 amdgpu_bo_unreserve(ring->mqd_obj); 6777 if (r) 6778 return r; 6779 } 6780 6781 r = amdgpu_gfx_enable_kgq(adev, 0); 6782 if (r) 6783 return r; 6784 6785 return gfx_v10_0_cp_gfx_start(adev); 6786 } 6787 6788 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6789 struct amdgpu_mqd_prop *prop) 6790 { 6791 struct v10_compute_mqd *mqd = m; 6792 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6793 uint32_t tmp; 6794 6795 mqd->header = 0xC0310800; 6796 mqd->compute_pipelinestat_enable = 0x00000001; 6797 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6798 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6799 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6800 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6801 mqd->compute_misc_reserved = 0x00000003; 6802 6803 eop_base_addr = prop->eop_gpu_addr >> 8; 6804 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6805 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6806 6807 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6808 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6809 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6810 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6811 6812 mqd->cp_hqd_eop_control = tmp; 6813 6814 /* enable doorbell? */ 6815 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6816 6817 if (prop->use_doorbell) { 6818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6819 DOORBELL_OFFSET, prop->doorbell_index); 6820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6821 DOORBELL_EN, 1); 6822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6823 DOORBELL_SOURCE, 0); 6824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6825 DOORBELL_HIT, 0); 6826 } else { 6827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6828 DOORBELL_EN, 0); 6829 } 6830 6831 mqd->cp_hqd_pq_doorbell_control = tmp; 6832 6833 /* disable the queue if it's active */ 6834 mqd->cp_hqd_dequeue_request = 0; 6835 mqd->cp_hqd_pq_rptr = 0; 6836 mqd->cp_hqd_pq_wptr_lo = 0; 6837 mqd->cp_hqd_pq_wptr_hi = 0; 6838 6839 /* set the pointer to the MQD */ 6840 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6841 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6842 6843 /* set MQD vmid to 0 */ 6844 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6845 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6846 mqd->cp_mqd_control = tmp; 6847 6848 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6849 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6850 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6851 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6852 6853 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6854 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6856 (order_base_2(prop->queue_size / 4) - 1)); 6857 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6858 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6859 #ifdef __BIG_ENDIAN 6860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6861 #endif 6862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 6864 prop->allow_tunneling); 6865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6866 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6867 mqd->cp_hqd_pq_control = tmp; 6868 6869 /* set the wb address whether it's enabled or not */ 6870 wb_gpu_addr = prop->rptr_gpu_addr; 6871 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6872 mqd->cp_hqd_pq_rptr_report_addr_hi = 6873 upper_32_bits(wb_gpu_addr) & 0xffff; 6874 6875 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6876 wb_gpu_addr = prop->wptr_gpu_addr; 6877 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6878 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6879 6880 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6881 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6882 6883 /* set the vmid for the queue */ 6884 mqd->cp_hqd_vmid = 0; 6885 6886 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6887 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6888 mqd->cp_hqd_persistent_state = tmp; 6889 6890 /* set MIN_IB_AVAIL_SIZE */ 6891 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6892 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6893 mqd->cp_hqd_ib_control = tmp; 6894 6895 /* set static priority for a compute queue/ring */ 6896 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6897 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6898 6899 mqd->cp_hqd_active = prop->hqd_active; 6900 6901 return 0; 6902 } 6903 6904 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6905 { 6906 struct amdgpu_device *adev = ring->adev; 6907 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6908 int j; 6909 6910 /* inactivate the queue */ 6911 if (amdgpu_sriov_vf(adev)) 6912 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6913 6914 /* disable wptr polling */ 6915 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6916 6917 /* disable the queue if it's active */ 6918 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6919 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6920 for (j = 0; j < adev->usec_timeout; j++) { 6921 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6922 break; 6923 udelay(1); 6924 } 6925 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6926 mqd->cp_hqd_dequeue_request); 6927 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6928 mqd->cp_hqd_pq_rptr); 6929 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6930 mqd->cp_hqd_pq_wptr_lo); 6931 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6932 mqd->cp_hqd_pq_wptr_hi); 6933 } 6934 6935 /* disable doorbells */ 6936 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6937 6938 /* write the EOP addr */ 6939 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6940 mqd->cp_hqd_eop_base_addr_lo); 6941 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6942 mqd->cp_hqd_eop_base_addr_hi); 6943 6944 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6945 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6946 mqd->cp_hqd_eop_control); 6947 6948 /* set the pointer to the MQD */ 6949 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6950 mqd->cp_mqd_base_addr_lo); 6951 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6952 mqd->cp_mqd_base_addr_hi); 6953 6954 /* set MQD vmid to 0 */ 6955 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6956 mqd->cp_mqd_control); 6957 6958 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6959 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6960 mqd->cp_hqd_pq_base_lo); 6961 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6962 mqd->cp_hqd_pq_base_hi); 6963 6964 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6965 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6966 mqd->cp_hqd_pq_control); 6967 6968 /* set the wb address whether it's enabled or not */ 6969 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6970 mqd->cp_hqd_pq_rptr_report_addr_lo); 6971 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6972 mqd->cp_hqd_pq_rptr_report_addr_hi); 6973 6974 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6975 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6976 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6977 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6978 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6979 6980 /* enable the doorbell if requested */ 6981 if (ring->use_doorbell) { 6982 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6983 (adev->doorbell_index.kiq * 2) << 2); 6984 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6985 (adev->doorbell_index.userqueue_end * 2) << 2); 6986 } 6987 6988 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6989 mqd->cp_hqd_pq_doorbell_control); 6990 6991 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6992 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6993 mqd->cp_hqd_pq_wptr_lo); 6994 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6995 mqd->cp_hqd_pq_wptr_hi); 6996 6997 /* set the vmid for the queue */ 6998 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6999 7000 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7001 mqd->cp_hqd_persistent_state); 7002 7003 /* activate the queue */ 7004 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7005 mqd->cp_hqd_active); 7006 7007 if (ring->use_doorbell) 7008 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7009 7010 return 0; 7011 } 7012 7013 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7014 { 7015 struct amdgpu_device *adev = ring->adev; 7016 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7017 7018 gfx_v10_0_kiq_setting(ring); 7019 7020 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7021 /* reset MQD to a clean status */ 7022 if (adev->gfx.kiq[0].mqd_backup) 7023 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 7024 7025 /* reset ring buffer */ 7026 ring->wptr = 0; 7027 amdgpu_ring_clear_ring(ring); 7028 7029 mutex_lock(&adev->srbm_mutex); 7030 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7031 gfx_v10_0_kiq_init_register(ring); 7032 nv_grbm_select(adev, 0, 0, 0, 0); 7033 mutex_unlock(&adev->srbm_mutex); 7034 } else { 7035 memset((void *)mqd, 0, sizeof(*mqd)); 7036 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 7037 amdgpu_ring_clear_ring(ring); 7038 mutex_lock(&adev->srbm_mutex); 7039 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7040 amdgpu_ring_init_mqd(ring); 7041 gfx_v10_0_kiq_init_register(ring); 7042 nv_grbm_select(adev, 0, 0, 0, 0); 7043 mutex_unlock(&adev->srbm_mutex); 7044 7045 if (adev->gfx.kiq[0].mqd_backup) 7046 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 7047 } 7048 7049 return 0; 7050 } 7051 7052 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) 7053 { 7054 struct amdgpu_device *adev = ring->adev; 7055 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7056 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7057 7058 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { 7059 memset((void *)mqd, 0, sizeof(*mqd)); 7060 mutex_lock(&adev->srbm_mutex); 7061 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7062 amdgpu_ring_init_mqd(ring); 7063 nv_grbm_select(adev, 0, 0, 0, 0); 7064 mutex_unlock(&adev->srbm_mutex); 7065 7066 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7067 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7068 } else { 7069 /* restore MQD to a clean status */ 7070 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7071 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7072 /* reset ring buffer */ 7073 ring->wptr = 0; 7074 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 7075 amdgpu_ring_clear_ring(ring); 7076 } 7077 7078 return 0; 7079 } 7080 7081 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7082 { 7083 struct amdgpu_ring *ring; 7084 int r; 7085 7086 ring = &adev->gfx.kiq[0].ring; 7087 7088 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7089 if (unlikely(r != 0)) 7090 return r; 7091 7092 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7093 if (unlikely(r != 0)) { 7094 amdgpu_bo_unreserve(ring->mqd_obj); 7095 return r; 7096 } 7097 7098 gfx_v10_0_kiq_init_queue(ring); 7099 amdgpu_bo_kunmap(ring->mqd_obj); 7100 ring->mqd_ptr = NULL; 7101 amdgpu_bo_unreserve(ring->mqd_obj); 7102 return 0; 7103 } 7104 7105 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7106 { 7107 struct amdgpu_ring *ring = NULL; 7108 int r = 0, i; 7109 7110 gfx_v10_0_cp_compute_enable(adev, true); 7111 7112 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7113 ring = &adev->gfx.compute_ring[i]; 7114 7115 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7116 if (unlikely(r != 0)) 7117 goto done; 7118 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7119 if (!r) { 7120 r = gfx_v10_0_kcq_init_queue(ring, false); 7121 amdgpu_bo_kunmap(ring->mqd_obj); 7122 ring->mqd_ptr = NULL; 7123 } 7124 amdgpu_bo_unreserve(ring->mqd_obj); 7125 if (r) 7126 goto done; 7127 } 7128 7129 r = amdgpu_gfx_enable_kcq(adev, 0); 7130 done: 7131 return r; 7132 } 7133 7134 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7135 { 7136 int r, i; 7137 struct amdgpu_ring *ring; 7138 7139 if (!(adev->flags & AMD_IS_APU)) 7140 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7141 7142 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7143 /* legacy firmware loading */ 7144 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7145 if (r) 7146 return r; 7147 7148 r = gfx_v10_0_cp_compute_load_microcode(adev); 7149 if (r) 7150 return r; 7151 } 7152 7153 r = gfx_v10_0_kiq_resume(adev); 7154 if (r) 7155 return r; 7156 7157 r = gfx_v10_0_kcq_resume(adev); 7158 if (r) 7159 return r; 7160 7161 if (!amdgpu_async_gfx_ring) { 7162 r = gfx_v10_0_cp_gfx_resume(adev); 7163 if (r) 7164 return r; 7165 } else { 7166 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7167 if (r) 7168 return r; 7169 } 7170 7171 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7172 ring = &adev->gfx.gfx_ring[i]; 7173 r = amdgpu_ring_test_helper(ring); 7174 if (r) 7175 return r; 7176 } 7177 7178 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7179 ring = &adev->gfx.compute_ring[i]; 7180 r = amdgpu_ring_test_helper(ring); 7181 if (r) 7182 return r; 7183 } 7184 7185 return 0; 7186 } 7187 7188 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7189 { 7190 gfx_v10_0_cp_gfx_enable(adev, enable); 7191 gfx_v10_0_cp_compute_enable(adev, enable); 7192 } 7193 7194 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7195 { 7196 uint32_t data, pattern = 0xDEADBEEF; 7197 7198 /* 7199 * check if mmVGT_ESGS_RING_SIZE_UMD 7200 * has been remapped to mmVGT_ESGS_RING_SIZE 7201 */ 7202 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7203 case IP_VERSION(10, 3, 0): 7204 case IP_VERSION(10, 3, 2): 7205 case IP_VERSION(10, 3, 4): 7206 case IP_VERSION(10, 3, 5): 7207 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7208 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7209 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7210 7211 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7212 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7213 return true; 7214 } 7215 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7216 break; 7217 case IP_VERSION(10, 3, 1): 7218 case IP_VERSION(10, 3, 3): 7219 case IP_VERSION(10, 3, 6): 7220 case IP_VERSION(10, 3, 7): 7221 return true; 7222 default: 7223 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7224 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7225 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7226 7227 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7228 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7229 return true; 7230 } 7231 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7232 break; 7233 } 7234 7235 return false; 7236 } 7237 7238 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7239 { 7240 uint32_t data; 7241 7242 if (amdgpu_sriov_vf(adev)) 7243 return; 7244 7245 /* 7246 * Initialize cam_index to 0 7247 * index will auto-inc after each data writing 7248 */ 7249 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7250 7251 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7252 case IP_VERSION(10, 3, 0): 7253 case IP_VERSION(10, 3, 2): 7254 case IP_VERSION(10, 3, 1): 7255 case IP_VERSION(10, 3, 4): 7256 case IP_VERSION(10, 3, 5): 7257 case IP_VERSION(10, 3, 6): 7258 case IP_VERSION(10, 3, 3): 7259 case IP_VERSION(10, 3, 7): 7260 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7261 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7262 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7263 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7264 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7265 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7266 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7267 7268 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7269 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7270 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7271 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7272 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7273 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7274 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7275 7276 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7277 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7278 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7279 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7280 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7281 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7282 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7283 7284 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7285 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7286 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7287 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7288 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7289 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7290 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7291 7292 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7293 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7294 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7295 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7296 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7297 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7298 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7299 7300 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7301 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7302 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7303 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7304 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7305 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7306 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7307 7308 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7309 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7310 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7311 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7312 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7313 break; 7314 default: 7315 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7316 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7317 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7318 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7319 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7320 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7321 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7322 7323 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7324 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7325 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7326 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7327 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7328 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7329 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7330 7331 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7332 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7333 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7334 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7335 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7336 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7337 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7338 7339 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7340 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7341 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7342 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7343 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7344 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7345 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7346 7347 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7348 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7349 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7350 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7351 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7353 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7354 7355 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7356 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7357 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7358 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7359 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7360 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7361 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7362 7363 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7364 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7365 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7366 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7367 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7368 break; 7369 } 7370 7371 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7372 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7373 } 7374 7375 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7376 { 7377 uint32_t data; 7378 7379 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7380 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7381 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7382 7383 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7384 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7385 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7386 } 7387 7388 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 7389 { 7390 int r; 7391 struct amdgpu_device *adev = ip_block->adev; 7392 7393 if (!amdgpu_emu_mode) 7394 gfx_v10_0_init_golden_registers(adev); 7395 7396 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 7397 adev->gfx.cleaner_shader_ptr); 7398 7399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7400 /** 7401 * For gfx 10, rlc firmware loading relies on smu firmware is 7402 * loaded firstly, so in direct type, it has to load smc ucode 7403 * here before rlc. 7404 */ 7405 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7406 if (r) 7407 return r; 7408 gfx_v10_0_disable_gpa_mode(adev); 7409 } 7410 7411 /* if GRBM CAM not remapped, set up the remapping */ 7412 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7413 gfx_v10_0_setup_grbm_cam_remapping(adev); 7414 7415 gfx_v10_0_constants_init(adev); 7416 7417 r = gfx_v10_0_rlc_resume(adev); 7418 if (r) 7419 return r; 7420 7421 /* 7422 * init golden registers and rlc resume may override some registers, 7423 * reconfig them here 7424 */ 7425 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) || 7426 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) || 7427 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) 7428 gfx_v10_0_tcp_harvest(adev); 7429 7430 r = gfx_v10_0_cp_resume(adev); 7431 if (r) 7432 return r; 7433 7434 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 7435 gfx_v10_3_program_pbb_mode(adev); 7436 7437 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev)) 7438 gfx_v10_3_set_power_brake_sequence(adev); 7439 7440 return r; 7441 } 7442 7443 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 7444 { 7445 struct amdgpu_device *adev = ip_block->adev; 7446 7447 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7448 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7449 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 7450 7451 /* WA added for Vangogh asic fixing the SMU suspend failure 7452 * It needs to set power gating again during gfxoff control 7453 * otherwise the gfxoff disallowing will be failed to set. 7454 */ 7455 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) 7456 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE); 7457 7458 if (!adev->no_hw_access) { 7459 if (amdgpu_async_gfx_ring) { 7460 if (amdgpu_gfx_disable_kgq(adev, 0)) 7461 DRM_ERROR("KGQ disable failed\n"); 7462 } 7463 7464 if (amdgpu_gfx_disable_kcq(adev, 0)) 7465 DRM_ERROR("KCQ disable failed\n"); 7466 } 7467 7468 if (amdgpu_sriov_vf(adev)) { 7469 gfx_v10_0_cp_gfx_enable(adev, false); 7470 /* Remove the steps of clearing KIQ position. 7471 * It causes GFX hang when another Win guest is rendering. 7472 */ 7473 return 0; 7474 } 7475 gfx_v10_0_cp_enable(adev, false); 7476 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7477 7478 return 0; 7479 } 7480 7481 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) 7482 { 7483 return gfx_v10_0_hw_fini(ip_block); 7484 } 7485 7486 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) 7487 { 7488 return gfx_v10_0_hw_init(ip_block); 7489 } 7490 7491 static bool gfx_v10_0_is_idle(void *handle) 7492 { 7493 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7494 7495 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7496 GRBM_STATUS, GUI_ACTIVE)) 7497 return false; 7498 else 7499 return true; 7500 } 7501 7502 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 7503 { 7504 unsigned int i; 7505 u32 tmp; 7506 struct amdgpu_device *adev = ip_block->adev; 7507 7508 for (i = 0; i < adev->usec_timeout; i++) { 7509 /* read MC_STATUS */ 7510 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7511 GRBM_STATUS__GUI_ACTIVE_MASK; 7512 7513 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7514 return 0; 7515 udelay(1); 7516 } 7517 return -ETIMEDOUT; 7518 } 7519 7520 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) 7521 { 7522 u32 grbm_soft_reset = 0; 7523 u32 tmp; 7524 struct amdgpu_device *adev = ip_block->adev; 7525 7526 /* GRBM_STATUS */ 7527 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7528 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7529 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7530 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7531 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7532 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7533 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7534 GRBM_SOFT_RESET, SOFT_RESET_CP, 7535 1); 7536 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7537 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7538 1); 7539 } 7540 7541 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7542 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7543 GRBM_SOFT_RESET, SOFT_RESET_CP, 7544 1); 7545 } 7546 7547 /* GRBM_STATUS2 */ 7548 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7549 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7550 case IP_VERSION(10, 3, 0): 7551 case IP_VERSION(10, 3, 2): 7552 case IP_VERSION(10, 3, 1): 7553 case IP_VERSION(10, 3, 4): 7554 case IP_VERSION(10, 3, 5): 7555 case IP_VERSION(10, 3, 6): 7556 case IP_VERSION(10, 3, 3): 7557 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7558 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7559 GRBM_SOFT_RESET, 7560 SOFT_RESET_RLC, 7561 1); 7562 break; 7563 default: 7564 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7565 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7566 GRBM_SOFT_RESET, 7567 SOFT_RESET_RLC, 7568 1); 7569 break; 7570 } 7571 7572 if (grbm_soft_reset) { 7573 /* stop the rlc */ 7574 gfx_v10_0_rlc_stop(adev); 7575 7576 /* Disable GFX parsing/prefetching */ 7577 gfx_v10_0_cp_gfx_enable(adev, false); 7578 7579 /* Disable MEC parsing/prefetching */ 7580 gfx_v10_0_cp_compute_enable(adev, false); 7581 7582 if (grbm_soft_reset) { 7583 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7584 tmp |= grbm_soft_reset; 7585 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7586 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7587 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7588 7589 udelay(50); 7590 7591 tmp &= ~grbm_soft_reset; 7592 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7593 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7594 } 7595 7596 /* Wait a little for things to settle down */ 7597 udelay(50); 7598 } 7599 return 0; 7600 } 7601 7602 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7603 { 7604 uint64_t clock, clock_lo, clock_hi, hi_check; 7605 7606 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7607 case IP_VERSION(10, 1, 3): 7608 case IP_VERSION(10, 1, 4): 7609 preempt_disable(); 7610 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7611 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7612 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish); 7613 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7614 * roughly every 42 seconds. 7615 */ 7616 if (hi_check != clock_hi) { 7617 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish); 7618 clock_hi = hi_check; 7619 } 7620 preempt_enable(); 7621 clock = clock_lo | (clock_hi << 32ULL); 7622 break; 7623 case IP_VERSION(10, 3, 1): 7624 case IP_VERSION(10, 3, 3): 7625 case IP_VERSION(10, 3, 7): 7626 preempt_disable(); 7627 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7628 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7629 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7630 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7631 * roughly every 42 seconds. 7632 */ 7633 if (hi_check != clock_hi) { 7634 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7635 clock_hi = hi_check; 7636 } 7637 preempt_enable(); 7638 clock = clock_lo | (clock_hi << 32ULL); 7639 break; 7640 case IP_VERSION(10, 3, 6): 7641 preempt_disable(); 7642 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7643 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7644 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7645 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7646 * roughly every 42 seconds. 7647 */ 7648 if (hi_check != clock_hi) { 7649 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7650 clock_hi = hi_check; 7651 } 7652 preempt_enable(); 7653 clock = clock_lo | (clock_hi << 32ULL); 7654 break; 7655 default: 7656 preempt_disable(); 7657 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7658 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7659 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7660 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7661 * roughly every 42 seconds. 7662 */ 7663 if (hi_check != clock_hi) { 7664 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7665 clock_hi = hi_check; 7666 } 7667 preempt_enable(); 7668 clock = clock_lo | (clock_hi << 32ULL); 7669 break; 7670 } 7671 return clock; 7672 } 7673 7674 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7675 uint32_t vmid, 7676 uint32_t gds_base, uint32_t gds_size, 7677 uint32_t gws_base, uint32_t gws_size, 7678 uint32_t oa_base, uint32_t oa_size) 7679 { 7680 struct amdgpu_device *adev = ring->adev; 7681 7682 /* GDS Base */ 7683 gfx_v10_0_write_data_to_reg(ring, 0, false, 7684 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7685 gds_base); 7686 7687 /* GDS Size */ 7688 gfx_v10_0_write_data_to_reg(ring, 0, false, 7689 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7690 gds_size); 7691 7692 /* GWS */ 7693 gfx_v10_0_write_data_to_reg(ring, 0, false, 7694 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7695 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7696 7697 /* OA */ 7698 gfx_v10_0_write_data_to_reg(ring, 0, false, 7699 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7700 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7701 } 7702 7703 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) 7704 { 7705 struct amdgpu_device *adev = ip_block->adev; 7706 7707 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7708 7709 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7710 case IP_VERSION(10, 1, 10): 7711 case IP_VERSION(10, 1, 1): 7712 case IP_VERSION(10, 1, 2): 7713 case IP_VERSION(10, 1, 3): 7714 case IP_VERSION(10, 1, 4): 7715 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7716 break; 7717 case IP_VERSION(10, 3, 0): 7718 case IP_VERSION(10, 3, 2): 7719 case IP_VERSION(10, 3, 1): 7720 case IP_VERSION(10, 3, 4): 7721 case IP_VERSION(10, 3, 5): 7722 case IP_VERSION(10, 3, 6): 7723 case IP_VERSION(10, 3, 3): 7724 case IP_VERSION(10, 3, 7): 7725 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7726 break; 7727 default: 7728 break; 7729 } 7730 7731 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7732 AMDGPU_MAX_COMPUTE_RINGS); 7733 7734 gfx_v10_0_set_kiq_pm4_funcs(adev); 7735 gfx_v10_0_set_ring_funcs(adev); 7736 gfx_v10_0_set_irq_funcs(adev); 7737 gfx_v10_0_set_gds_init(adev); 7738 gfx_v10_0_set_rlc_funcs(adev); 7739 gfx_v10_0_set_mqd_funcs(adev); 7740 7741 /* init rlcg reg access ctrl */ 7742 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7743 7744 return gfx_v10_0_init_microcode(adev); 7745 } 7746 7747 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) 7748 { 7749 struct amdgpu_device *adev = ip_block->adev; 7750 int r; 7751 7752 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7753 if (r) 7754 return r; 7755 7756 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7757 if (r) 7758 return r; 7759 7760 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 7761 if (r) 7762 return r; 7763 7764 return 0; 7765 } 7766 7767 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7768 { 7769 uint32_t rlc_cntl; 7770 7771 /* if RLC is not enabled, do nothing */ 7772 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7773 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7774 } 7775 7776 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7777 { 7778 uint32_t data; 7779 unsigned int i; 7780 7781 data = RLC_SAFE_MODE__CMD_MASK; 7782 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7783 7784 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7785 case IP_VERSION(10, 3, 0): 7786 case IP_VERSION(10, 3, 2): 7787 case IP_VERSION(10, 3, 1): 7788 case IP_VERSION(10, 3, 4): 7789 case IP_VERSION(10, 3, 5): 7790 case IP_VERSION(10, 3, 6): 7791 case IP_VERSION(10, 3, 3): 7792 case IP_VERSION(10, 3, 7): 7793 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7794 7795 /* wait for RLC_SAFE_MODE */ 7796 for (i = 0; i < adev->usec_timeout; i++) { 7797 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7798 RLC_SAFE_MODE, CMD)) 7799 break; 7800 udelay(1); 7801 } 7802 break; 7803 default: 7804 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7805 7806 /* wait for RLC_SAFE_MODE */ 7807 for (i = 0; i < adev->usec_timeout; i++) { 7808 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7809 RLC_SAFE_MODE, CMD)) 7810 break; 7811 udelay(1); 7812 } 7813 break; 7814 } 7815 } 7816 7817 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7818 { 7819 uint32_t data; 7820 7821 data = RLC_SAFE_MODE__CMD_MASK; 7822 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 7823 case IP_VERSION(10, 3, 0): 7824 case IP_VERSION(10, 3, 2): 7825 case IP_VERSION(10, 3, 1): 7826 case IP_VERSION(10, 3, 4): 7827 case IP_VERSION(10, 3, 5): 7828 case IP_VERSION(10, 3, 6): 7829 case IP_VERSION(10, 3, 3): 7830 case IP_VERSION(10, 3, 7): 7831 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7832 break; 7833 default: 7834 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7835 break; 7836 } 7837 } 7838 7839 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7840 bool enable) 7841 { 7842 uint32_t data, def; 7843 7844 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7845 return; 7846 7847 /* It is disabled by HW by default */ 7848 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7849 /* 0 - Disable some blocks' MGCG */ 7850 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7851 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7852 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7853 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7854 7855 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7856 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7857 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7858 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7859 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7860 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7861 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7862 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7863 7864 if (def != data) 7865 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7866 7867 /* MGLS is a global flag to control all MGLS in GFX */ 7868 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7869 /* 2 - RLC memory Light sleep */ 7870 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7871 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7872 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7873 if (def != data) 7874 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7875 } 7876 /* 3 - CP memory Light sleep */ 7877 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7878 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7879 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7880 if (def != data) 7881 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7882 } 7883 } 7884 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7885 /* 1 - MGCG_OVERRIDE */ 7886 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7887 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7888 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7889 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7890 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7891 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7892 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7893 if (def != data) 7894 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7895 7896 /* 2 - disable MGLS in CP */ 7897 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7898 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7899 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7900 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7901 } 7902 7903 /* 3 - disable MGLS in RLC */ 7904 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7905 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7906 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7907 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7908 } 7909 7910 } 7911 } 7912 7913 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7914 bool enable) 7915 { 7916 uint32_t data, def; 7917 7918 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7919 return; 7920 7921 /* Enable 3D CGCG/CGLS */ 7922 if (enable) { 7923 /* write cmd to clear cgcg/cgls ov */ 7924 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7925 7926 /* unset CGCG override */ 7927 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7928 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7929 7930 /* update CGCG and CGLS override bits */ 7931 if (def != data) 7932 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7933 7934 /* enable 3Dcgcg FSM(0x0000363f) */ 7935 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7936 data = 0; 7937 7938 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7939 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7940 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7941 7942 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7943 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7944 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7945 7946 if (def != data) 7947 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7948 7949 /* set IDLE_POLL_COUNT(0x00900100) */ 7950 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7951 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7952 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7953 if (def != data) 7954 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7955 } else { 7956 /* Disable CGCG/CGLS */ 7957 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7958 7959 /* disable cgcg, cgls should be disabled */ 7960 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7961 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7962 7963 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7964 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7965 7966 /* disable cgcg and cgls in FSM */ 7967 if (def != data) 7968 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7969 } 7970 } 7971 7972 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7973 bool enable) 7974 { 7975 uint32_t def, data; 7976 7977 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7978 return; 7979 7980 if (enable) { 7981 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7982 7983 /* unset CGCG override */ 7984 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7985 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7986 7987 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7988 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7989 7990 /* update CGCG and CGLS override bits */ 7991 if (def != data) 7992 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7993 7994 /* enable cgcg FSM(0x0000363F) */ 7995 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7996 data = 0; 7997 7998 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7999 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8000 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8001 8002 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8003 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8004 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8005 8006 if (def != data) 8007 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8008 8009 /* set IDLE_POLL_COUNT(0x00900100) */ 8010 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8011 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8012 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8013 if (def != data) 8014 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8015 } else { 8016 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8017 8018 /* reset CGCG/CGLS bits */ 8019 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8020 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8021 8022 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8023 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8024 8025 /* disable cgcg and cgls in FSM */ 8026 if (def != data) 8027 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8028 } 8029 } 8030 8031 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8032 bool enable) 8033 { 8034 uint32_t def, data; 8035 8036 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8037 return; 8038 8039 if (enable) { 8040 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8041 /* unset FGCG override */ 8042 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8043 /* update FGCG override bits */ 8044 if (def != data) 8045 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8046 8047 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8048 /* unset RLC SRAM CLK GATER override */ 8049 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8050 /* update RLC SRAM CLK GATER override bits */ 8051 if (def != data) 8052 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8053 } else { 8054 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8055 /* reset FGCG bits */ 8056 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8057 /* disable FGCG*/ 8058 if (def != data) 8059 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8060 8061 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8062 /* reset RLC SRAM CLK GATER bits */ 8063 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8064 /* disable RLC SRAM CLK*/ 8065 if (def != data) 8066 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8067 } 8068 } 8069 8070 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8071 { 8072 uint32_t reg_data = 0; 8073 uint32_t reg_idx = 0; 8074 uint32_t i; 8075 8076 const uint32_t tcp_ctrl_regs[] = { 8077 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8078 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8079 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8080 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8081 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8082 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8083 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8084 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8085 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8086 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8087 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8088 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8089 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8090 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8091 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8092 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8093 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8094 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8095 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8096 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8097 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8098 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8099 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8100 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8101 }; 8102 8103 const uint32_t tcp_ctrl_regs_nv12[] = { 8104 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8105 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8106 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8107 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8108 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8109 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8110 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8111 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8112 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8113 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8114 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8115 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8116 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8117 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8118 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8119 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8120 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8121 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8122 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8123 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8124 }; 8125 8126 const uint32_t sm_ctlr_regs[] = { 8127 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8128 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8129 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8130 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8131 }; 8132 8133 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) { 8134 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8135 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8136 tcp_ctrl_regs_nv12[i]; 8137 reg_data = RREG32(reg_idx); 8138 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8139 WREG32(reg_idx, reg_data); 8140 } 8141 } else { 8142 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8143 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8144 tcp_ctrl_regs[i]; 8145 reg_data = RREG32(reg_idx); 8146 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8147 WREG32(reg_idx, reg_data); 8148 } 8149 } 8150 8151 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8152 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8153 sm_ctlr_regs[i]; 8154 reg_data = RREG32(reg_idx); 8155 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8156 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8157 WREG32(reg_idx, reg_data); 8158 } 8159 } 8160 8161 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8162 bool enable) 8163 { 8164 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8165 8166 if (enable) { 8167 /* enable FGCG firstly*/ 8168 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8169 /* CGCG/CGLS should be enabled after MGCG/MGLS 8170 * === MGCG + MGLS === 8171 */ 8172 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8173 /* === CGCG /CGLS for GFX 3D Only === */ 8174 gfx_v10_0_update_3d_clock_gating(adev, enable); 8175 /* === CGCG + CGLS === */ 8176 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8177 8178 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 8179 IP_VERSION(10, 1, 10)) || 8180 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8181 IP_VERSION(10, 1, 1)) || 8182 (amdgpu_ip_version(adev, GC_HWIP, 0) == 8183 IP_VERSION(10, 1, 2))) 8184 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8185 } else { 8186 /* CGCG/CGLS should be disabled before MGCG/MGLS 8187 * === CGCG + CGLS === 8188 */ 8189 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8190 /* === CGCG /CGLS for GFX 3D Only === */ 8191 gfx_v10_0_update_3d_clock_gating(adev, enable); 8192 /* === MGCG + MGLS === */ 8193 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8194 /* disable fgcg at last*/ 8195 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8196 } 8197 8198 if (adev->cg_flags & 8199 (AMD_CG_SUPPORT_GFX_MGCG | 8200 AMD_CG_SUPPORT_GFX_CGLS | 8201 AMD_CG_SUPPORT_GFX_CGCG | 8202 AMD_CG_SUPPORT_GFX_3D_CGCG | 8203 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8204 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8205 8206 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8207 8208 return 0; 8209 } 8210 8211 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 8212 unsigned int vmid) 8213 { 8214 u32 reg, pre_data, data; 8215 8216 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8217 /* not for *_SOC15 */ 8218 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 8219 pre_data = RREG32_NO_KIQ(reg); 8220 else 8221 pre_data = RREG32(reg); 8222 8223 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 8224 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8225 8226 if (pre_data != data) { 8227 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 8228 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8229 } else 8230 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8231 } 8232 } 8233 8234 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) 8235 { 8236 amdgpu_gfx_off_ctrl(adev, false); 8237 8238 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 8239 8240 amdgpu_gfx_off_ctrl(adev, true); 8241 } 8242 8243 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8244 uint32_t offset, 8245 struct soc15_reg_rlcg *entries, int arr_size) 8246 { 8247 int i; 8248 uint32_t reg; 8249 8250 if (!entries) 8251 return false; 8252 8253 for (i = 0; i < arr_size; i++) { 8254 const struct soc15_reg_rlcg *entry; 8255 8256 entry = &entries[i]; 8257 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8258 if (offset == reg) 8259 return true; 8260 } 8261 8262 return false; 8263 } 8264 8265 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8266 { 8267 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8268 } 8269 8270 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8271 { 8272 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8273 8274 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8275 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8276 else 8277 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8278 8279 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8280 8281 /* 8282 * CGPG enablement required and the register to program the hysteresis value 8283 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8284 * in refclk count. Note that RLC FW is modified to take 16 bits from 8285 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8286 * 8287 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8288 * of CGPG enablement starting point. 8289 * Power/performance team will optimize it and might give a new value later. 8290 */ 8291 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8292 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8293 case IP_VERSION(10, 3, 1): 8294 case IP_VERSION(10, 3, 3): 8295 case IP_VERSION(10, 3, 6): 8296 case IP_VERSION(10, 3, 7): 8297 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8298 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8299 break; 8300 default: 8301 break; 8302 } 8303 } 8304 } 8305 8306 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8307 { 8308 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8309 8310 gfx_v10_cntl_power_gating(adev, enable); 8311 8312 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8313 } 8314 8315 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8316 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8317 .set_safe_mode = gfx_v10_0_set_safe_mode, 8318 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8319 .init = gfx_v10_0_rlc_init, 8320 .get_csb_size = gfx_v10_0_get_csb_size, 8321 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8322 .resume = gfx_v10_0_rlc_resume, 8323 .stop = gfx_v10_0_rlc_stop, 8324 .reset = gfx_v10_0_rlc_reset, 8325 .start = gfx_v10_0_rlc_start, 8326 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8327 }; 8328 8329 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8330 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8331 .set_safe_mode = gfx_v10_0_set_safe_mode, 8332 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8333 .init = gfx_v10_0_rlc_init, 8334 .get_csb_size = gfx_v10_0_get_csb_size, 8335 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8336 .resume = gfx_v10_0_rlc_resume, 8337 .stop = gfx_v10_0_rlc_stop, 8338 .reset = gfx_v10_0_rlc_reset, 8339 .start = gfx_v10_0_rlc_start, 8340 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8341 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8342 }; 8343 8344 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 8345 enum amd_powergating_state state) 8346 { 8347 struct amdgpu_device *adev = ip_block->adev; 8348 bool enable = (state == AMD_PG_STATE_GATE); 8349 8350 if (amdgpu_sriov_vf(adev)) 8351 return 0; 8352 8353 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8354 case IP_VERSION(10, 1, 10): 8355 case IP_VERSION(10, 1, 1): 8356 case IP_VERSION(10, 1, 2): 8357 case IP_VERSION(10, 3, 0): 8358 case IP_VERSION(10, 3, 2): 8359 case IP_VERSION(10, 3, 4): 8360 case IP_VERSION(10, 3, 5): 8361 amdgpu_gfx_off_ctrl(adev, enable); 8362 break; 8363 case IP_VERSION(10, 3, 1): 8364 case IP_VERSION(10, 3, 3): 8365 case IP_VERSION(10, 3, 6): 8366 case IP_VERSION(10, 3, 7): 8367 if (!enable) 8368 amdgpu_gfx_off_ctrl(adev, false); 8369 8370 gfx_v10_cntl_pg(adev, enable); 8371 8372 if (enable) 8373 amdgpu_gfx_off_ctrl(adev, true); 8374 8375 break; 8376 default: 8377 break; 8378 } 8379 return 0; 8380 } 8381 8382 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 8383 enum amd_clockgating_state state) 8384 { 8385 struct amdgpu_device *adev = ip_block->adev; 8386 8387 if (amdgpu_sriov_vf(adev)) 8388 return 0; 8389 8390 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 8391 case IP_VERSION(10, 1, 10): 8392 case IP_VERSION(10, 1, 1): 8393 case IP_VERSION(10, 1, 2): 8394 case IP_VERSION(10, 3, 0): 8395 case IP_VERSION(10, 3, 2): 8396 case IP_VERSION(10, 3, 1): 8397 case IP_VERSION(10, 3, 4): 8398 case IP_VERSION(10, 3, 5): 8399 case IP_VERSION(10, 3, 6): 8400 case IP_VERSION(10, 3, 3): 8401 case IP_VERSION(10, 3, 7): 8402 gfx_v10_0_update_gfx_clock_gating(adev, 8403 state == AMD_CG_STATE_GATE); 8404 break; 8405 default: 8406 break; 8407 } 8408 return 0; 8409 } 8410 8411 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8412 { 8413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8414 int data; 8415 8416 /* AMD_CG_SUPPORT_GFX_FGCG */ 8417 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8418 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8419 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8420 8421 /* AMD_CG_SUPPORT_GFX_MGCG */ 8422 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8423 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8424 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8425 8426 /* AMD_CG_SUPPORT_GFX_CGCG */ 8427 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8428 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8429 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8430 8431 /* AMD_CG_SUPPORT_GFX_CGLS */ 8432 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8433 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8434 8435 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8436 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8437 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8438 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8439 8440 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8441 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8442 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8443 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8444 8445 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8446 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8447 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8448 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8449 8450 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8451 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8452 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8453 } 8454 8455 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8456 { 8457 /* gfx10 is 32bit rptr*/ 8458 return *(uint32_t *)ring->rptr_cpu_addr; 8459 } 8460 8461 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8462 { 8463 struct amdgpu_device *adev = ring->adev; 8464 u64 wptr; 8465 8466 /* XXX check if swapping is necessary on BE */ 8467 if (ring->use_doorbell) { 8468 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8469 } else { 8470 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8471 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8472 } 8473 8474 return wptr; 8475 } 8476 8477 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8478 { 8479 struct amdgpu_device *adev = ring->adev; 8480 8481 if (ring->use_doorbell) { 8482 /* XXX check if swapping is necessary on BE */ 8483 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8484 ring->wptr); 8485 WDOORBELL64(ring->doorbell_index, ring->wptr); 8486 } else { 8487 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8488 lower_32_bits(ring->wptr)); 8489 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8490 upper_32_bits(ring->wptr)); 8491 } 8492 } 8493 8494 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8495 { 8496 /* gfx10 hardware is 32bit rptr */ 8497 return *(uint32_t *)ring->rptr_cpu_addr; 8498 } 8499 8500 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8501 { 8502 u64 wptr; 8503 8504 /* XXX check if swapping is necessary on BE */ 8505 if (ring->use_doorbell) 8506 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8507 else 8508 BUG(); 8509 return wptr; 8510 } 8511 8512 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8513 { 8514 struct amdgpu_device *adev = ring->adev; 8515 8516 if (ring->use_doorbell) { 8517 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8518 ring->wptr); 8519 WDOORBELL64(ring->doorbell_index, ring->wptr); 8520 } else { 8521 BUG(); /* only DOORBELL method supported on gfx10 now */ 8522 } 8523 } 8524 8525 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8526 { 8527 struct amdgpu_device *adev = ring->adev; 8528 u32 ref_and_mask, reg_mem_engine; 8529 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8530 8531 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8532 switch (ring->me) { 8533 case 1: 8534 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8535 break; 8536 case 2: 8537 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8538 break; 8539 default: 8540 return; 8541 } 8542 reg_mem_engine = 0; 8543 } else { 8544 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; 8545 reg_mem_engine = 1; /* pfp */ 8546 } 8547 8548 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8549 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8550 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8551 ref_and_mask, ref_and_mask, 0x20); 8552 } 8553 8554 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8555 struct amdgpu_job *job, 8556 struct amdgpu_ib *ib, 8557 uint32_t flags) 8558 { 8559 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8560 u32 header, control = 0; 8561 8562 if (ib->flags & AMDGPU_IB_FLAG_CE) 8563 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8564 else 8565 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8566 8567 control |= ib->length_dw | (vmid << 24); 8568 8569 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8570 control |= INDIRECT_BUFFER_PRE_ENB(1); 8571 8572 if (flags & AMDGPU_IB_PREEMPTED) 8573 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8574 8575 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8576 gfx_v10_0_ring_emit_de_meta(ring, 8577 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8578 } 8579 8580 amdgpu_ring_write(ring, header); 8581 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8582 amdgpu_ring_write(ring, 8583 #ifdef __BIG_ENDIAN 8584 (2 << 0) | 8585 #endif 8586 lower_32_bits(ib->gpu_addr)); 8587 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8588 amdgpu_ring_write(ring, control); 8589 } 8590 8591 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8592 struct amdgpu_job *job, 8593 struct amdgpu_ib *ib, 8594 uint32_t flags) 8595 { 8596 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8597 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8598 8599 /* Currently, there is a high possibility to get wave ID mismatch 8600 * between ME and GDS, leading to a hw deadlock, because ME generates 8601 * different wave IDs than the GDS expects. This situation happens 8602 * randomly when at least 5 compute pipes use GDS ordered append. 8603 * The wave IDs generated by ME are also wrong after suspend/resume. 8604 * Those are probably bugs somewhere else in the kernel driver. 8605 * 8606 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8607 * GDS to 0 for this ring (me/pipe). 8608 */ 8609 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8610 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8611 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8612 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8613 } 8614 8615 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8616 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8617 amdgpu_ring_write(ring, 8618 #ifdef __BIG_ENDIAN 8619 (2 << 0) | 8620 #endif 8621 lower_32_bits(ib->gpu_addr)); 8622 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8623 amdgpu_ring_write(ring, control); 8624 } 8625 8626 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8627 u64 seq, unsigned int flags) 8628 { 8629 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8630 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8631 8632 /* RELEASE_MEM - flush caches, send int */ 8633 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8634 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8635 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8636 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8637 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8638 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8639 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8640 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8641 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8642 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8643 8644 /* 8645 * the address should be Qword aligned if 64bit write, Dword 8646 * aligned if only send 32bit data low (discard data high) 8647 */ 8648 if (write64bit) 8649 BUG_ON(addr & 0x7); 8650 else 8651 BUG_ON(addr & 0x3); 8652 amdgpu_ring_write(ring, lower_32_bits(addr)); 8653 amdgpu_ring_write(ring, upper_32_bits(addr)); 8654 amdgpu_ring_write(ring, lower_32_bits(seq)); 8655 amdgpu_ring_write(ring, upper_32_bits(seq)); 8656 amdgpu_ring_write(ring, 0); 8657 } 8658 8659 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8660 { 8661 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8662 uint32_t seq = ring->fence_drv.sync_seq; 8663 uint64_t addr = ring->fence_drv.gpu_addr; 8664 8665 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8666 upper_32_bits(addr), seq, 0xffffffff, 4); 8667 } 8668 8669 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8670 uint16_t pasid, uint32_t flush_type, 8671 bool all_hub, uint8_t dst_sel) 8672 { 8673 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8674 amdgpu_ring_write(ring, 8675 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8676 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8677 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8678 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8679 } 8680 8681 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8682 unsigned int vmid, uint64_t pd_addr) 8683 { 8684 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8685 8686 /* compute doesn't have PFP */ 8687 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8688 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8689 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8690 amdgpu_ring_write(ring, 0x0); 8691 } 8692 } 8693 8694 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8695 u64 seq, unsigned int flags) 8696 { 8697 struct amdgpu_device *adev = ring->adev; 8698 8699 /* we only allocate 32bit for each seq wb address */ 8700 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8701 8702 /* write fence seq to the "addr" */ 8703 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8704 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8705 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8706 amdgpu_ring_write(ring, lower_32_bits(addr)); 8707 amdgpu_ring_write(ring, upper_32_bits(addr)); 8708 amdgpu_ring_write(ring, lower_32_bits(seq)); 8709 8710 if (flags & AMDGPU_FENCE_FLAG_INT) { 8711 /* set register to trigger INT */ 8712 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8713 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8714 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8715 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8716 amdgpu_ring_write(ring, 0); 8717 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8718 } 8719 } 8720 8721 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8722 { 8723 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8724 amdgpu_ring_write(ring, 0); 8725 } 8726 8727 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8728 uint32_t flags) 8729 { 8730 uint32_t dw2 = 0; 8731 8732 if (ring->adev->gfx.mcbp) 8733 gfx_v10_0_ring_emit_ce_meta(ring, 8734 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8735 8736 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8737 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8738 /* set load_global_config & load_global_uconfig */ 8739 dw2 |= 0x8001; 8740 /* set load_cs_sh_regs */ 8741 dw2 |= 0x01000000; 8742 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8743 dw2 |= 0x10002; 8744 8745 /* set load_ce_ram if preamble presented */ 8746 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8747 dw2 |= 0x10000000; 8748 } else { 8749 /* still load_ce_ram if this is the first time preamble presented 8750 * although there is no context switch happens. 8751 */ 8752 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8753 dw2 |= 0x10000000; 8754 } 8755 8756 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8757 amdgpu_ring_write(ring, dw2); 8758 amdgpu_ring_write(ring, 0); 8759 } 8760 8761 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 8762 uint64_t addr) 8763 { 8764 unsigned int ret; 8765 8766 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8767 amdgpu_ring_write(ring, lower_32_bits(addr)); 8768 amdgpu_ring_write(ring, upper_32_bits(addr)); 8769 /* discard following DWs if *cond_exec_gpu_addr==0 */ 8770 amdgpu_ring_write(ring, 0); 8771 ret = ring->wptr & ring->buf_mask; 8772 /* patch dummy value later */ 8773 amdgpu_ring_write(ring, 0); 8774 8775 return ret; 8776 } 8777 8778 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8779 { 8780 int i, r = 0; 8781 struct amdgpu_device *adev = ring->adev; 8782 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8783 struct amdgpu_ring *kiq_ring = &kiq->ring; 8784 unsigned long flags; 8785 8786 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8787 return -EINVAL; 8788 8789 spin_lock_irqsave(&kiq->ring_lock, flags); 8790 8791 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8792 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8793 return -ENOMEM; 8794 } 8795 8796 /* assert preemption condition */ 8797 amdgpu_ring_set_preempt_cond_exec(ring, false); 8798 8799 /* assert IB preemption, emit the trailing fence */ 8800 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8801 ring->trail_fence_gpu_addr, 8802 ++ring->trail_seq); 8803 amdgpu_ring_commit(kiq_ring); 8804 8805 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8806 8807 /* poll the trailing fence */ 8808 for (i = 0; i < adev->usec_timeout; i++) { 8809 if (ring->trail_seq == 8810 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8811 break; 8812 udelay(1); 8813 } 8814 8815 if (i >= adev->usec_timeout) { 8816 r = -EINVAL; 8817 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8818 } 8819 8820 /* deassert preemption condition */ 8821 amdgpu_ring_set_preempt_cond_exec(ring, true); 8822 return r; 8823 } 8824 8825 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8826 { 8827 struct amdgpu_device *adev = ring->adev; 8828 struct v10_ce_ib_state ce_payload = {0}; 8829 uint64_t offset, ce_payload_gpu_addr; 8830 void *ce_payload_cpu_addr; 8831 int cnt; 8832 8833 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8834 8835 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8836 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8837 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8838 8839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8840 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8841 WRITE_DATA_DST_SEL(8) | 8842 WR_CONFIRM) | 8843 WRITE_DATA_CACHE_POLICY(0)); 8844 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8845 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8846 8847 if (resume) 8848 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8849 sizeof(ce_payload) >> 2); 8850 else 8851 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8852 sizeof(ce_payload) >> 2); 8853 } 8854 8855 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8856 { 8857 struct amdgpu_device *adev = ring->adev; 8858 struct v10_de_ib_state de_payload = {0}; 8859 uint64_t offset, gds_addr, de_payload_gpu_addr; 8860 void *de_payload_cpu_addr; 8861 int cnt; 8862 8863 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8864 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8865 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8866 8867 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8868 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8869 PAGE_SIZE); 8870 8871 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8872 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8873 8874 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8875 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8876 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8877 WRITE_DATA_DST_SEL(8) | 8878 WR_CONFIRM) | 8879 WRITE_DATA_CACHE_POLICY(0)); 8880 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8881 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8882 8883 if (resume) 8884 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8885 sizeof(de_payload) >> 2); 8886 else 8887 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8888 sizeof(de_payload) >> 2); 8889 } 8890 8891 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8892 bool secure) 8893 { 8894 uint32_t v = secure ? FRAME_TMZ : 0; 8895 8896 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8897 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8898 } 8899 8900 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8901 uint32_t reg_val_offs) 8902 { 8903 struct amdgpu_device *adev = ring->adev; 8904 8905 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8906 amdgpu_ring_write(ring, 0 | /* src: register*/ 8907 (5 << 8) | /* dst: memory */ 8908 (1 << 20)); /* write confirm */ 8909 amdgpu_ring_write(ring, reg); 8910 amdgpu_ring_write(ring, 0); 8911 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8912 reg_val_offs * 4)); 8913 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8914 reg_val_offs * 4)); 8915 } 8916 8917 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8918 uint32_t val) 8919 { 8920 uint32_t cmd = 0; 8921 8922 switch (ring->funcs->type) { 8923 case AMDGPU_RING_TYPE_GFX: 8924 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8925 break; 8926 case AMDGPU_RING_TYPE_KIQ: 8927 cmd = (1 << 16); /* no inc addr */ 8928 break; 8929 default: 8930 cmd = WR_CONFIRM; 8931 break; 8932 } 8933 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8934 amdgpu_ring_write(ring, cmd); 8935 amdgpu_ring_write(ring, reg); 8936 amdgpu_ring_write(ring, 0); 8937 amdgpu_ring_write(ring, val); 8938 } 8939 8940 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8941 uint32_t val, uint32_t mask) 8942 { 8943 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8944 } 8945 8946 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8947 uint32_t reg0, uint32_t reg1, 8948 uint32_t ref, uint32_t mask) 8949 { 8950 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8951 struct amdgpu_device *adev = ring->adev; 8952 bool fw_version_ok = false; 8953 8954 fw_version_ok = adev->gfx.cp_fw_write_wait; 8955 8956 if (fw_version_ok) 8957 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8958 ref, mask, 0x20); 8959 else 8960 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8961 ref, mask); 8962 } 8963 8964 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8965 unsigned int vmid) 8966 { 8967 struct amdgpu_device *adev = ring->adev; 8968 uint32_t value = 0; 8969 8970 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8971 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8972 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8973 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8974 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 8975 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8976 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 8977 } 8978 8979 static void 8980 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8981 uint32_t me, uint32_t pipe, 8982 enum amdgpu_interrupt_state state) 8983 { 8984 uint32_t cp_int_cntl, cp_int_cntl_reg; 8985 8986 if (!me) { 8987 switch (pipe) { 8988 case 0: 8989 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8990 break; 8991 case 1: 8992 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8993 break; 8994 default: 8995 DRM_DEBUG("invalid pipe %d\n", pipe); 8996 return; 8997 } 8998 } else { 8999 DRM_DEBUG("invalid me %d\n", me); 9000 return; 9001 } 9002 9003 switch (state) { 9004 case AMDGPU_IRQ_STATE_DISABLE: 9005 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9006 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9007 TIME_STAMP_INT_ENABLE, 0); 9008 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9009 break; 9010 case AMDGPU_IRQ_STATE_ENABLE: 9011 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9012 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9013 TIME_STAMP_INT_ENABLE, 1); 9014 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9015 break; 9016 default: 9017 break; 9018 } 9019 } 9020 9021 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9022 int me, int pipe, 9023 enum amdgpu_interrupt_state state) 9024 { 9025 u32 mec_int_cntl, mec_int_cntl_reg; 9026 9027 /* 9028 * amdgpu controls only the first MEC. That's why this function only 9029 * handles the setting of interrupts for this specific MEC. All other 9030 * pipes' interrupts are set by amdkfd. 9031 */ 9032 9033 if (me == 1) { 9034 switch (pipe) { 9035 case 0: 9036 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9037 break; 9038 case 1: 9039 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9040 break; 9041 case 2: 9042 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9043 break; 9044 case 3: 9045 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9046 break; 9047 default: 9048 DRM_DEBUG("invalid pipe %d\n", pipe); 9049 return; 9050 } 9051 } else { 9052 DRM_DEBUG("invalid me %d\n", me); 9053 return; 9054 } 9055 9056 switch (state) { 9057 case AMDGPU_IRQ_STATE_DISABLE: 9058 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9059 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9060 TIME_STAMP_INT_ENABLE, 0); 9061 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9062 break; 9063 case AMDGPU_IRQ_STATE_ENABLE: 9064 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9065 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9066 TIME_STAMP_INT_ENABLE, 1); 9067 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9068 break; 9069 default: 9070 break; 9071 } 9072 } 9073 9074 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9075 struct amdgpu_irq_src *src, 9076 unsigned int type, 9077 enum amdgpu_interrupt_state state) 9078 { 9079 switch (type) { 9080 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9081 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9082 break; 9083 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9084 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9085 break; 9086 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9087 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9088 break; 9089 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9090 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9091 break; 9092 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9093 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9094 break; 9095 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9096 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9097 break; 9098 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9099 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9100 break; 9101 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9102 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9103 break; 9104 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9105 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9106 break; 9107 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9108 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9109 break; 9110 default: 9111 break; 9112 } 9113 return 0; 9114 } 9115 9116 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9117 struct amdgpu_irq_src *source, 9118 struct amdgpu_iv_entry *entry) 9119 { 9120 int i; 9121 u8 me_id, pipe_id, queue_id; 9122 struct amdgpu_ring *ring; 9123 9124 DRM_DEBUG("IH: CP EOP\n"); 9125 9126 me_id = (entry->ring_id & 0x0c) >> 2; 9127 pipe_id = (entry->ring_id & 0x03) >> 0; 9128 queue_id = (entry->ring_id & 0x70) >> 4; 9129 9130 switch (me_id) { 9131 case 0: 9132 if (pipe_id == 0) 9133 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9134 else 9135 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9136 break; 9137 case 1: 9138 case 2: 9139 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9140 ring = &adev->gfx.compute_ring[i]; 9141 /* Per-queue interrupt is supported for MEC starting from VI. 9142 * The interrupt can only be enabled/disabled per pipe instead 9143 * of per queue. 9144 */ 9145 if ((ring->me == me_id) && 9146 (ring->pipe == pipe_id) && 9147 (ring->queue == queue_id)) 9148 amdgpu_fence_process(ring); 9149 } 9150 break; 9151 } 9152 9153 return 0; 9154 } 9155 9156 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9157 struct amdgpu_irq_src *source, 9158 unsigned int type, 9159 enum amdgpu_interrupt_state state) 9160 { 9161 u32 cp_int_cntl_reg, cp_int_cntl; 9162 int i, j; 9163 9164 switch (state) { 9165 case AMDGPU_IRQ_STATE_DISABLE: 9166 case AMDGPU_IRQ_STATE_ENABLE: 9167 for (i = 0; i < adev->gfx.me.num_me; i++) { 9168 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9169 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9170 9171 if (cp_int_cntl_reg) { 9172 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9173 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9174 PRIV_REG_INT_ENABLE, 9175 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9176 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9177 } 9178 } 9179 } 9180 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9181 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9182 /* MECs start at 1 */ 9183 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9184 9185 if (cp_int_cntl_reg) { 9186 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9187 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9188 PRIV_REG_INT_ENABLE, 9189 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9190 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9191 } 9192 } 9193 } 9194 break; 9195 default: 9196 break; 9197 } 9198 9199 return 0; 9200 } 9201 9202 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev, 9203 struct amdgpu_irq_src *source, 9204 unsigned type, 9205 enum amdgpu_interrupt_state state) 9206 { 9207 u32 cp_int_cntl_reg, cp_int_cntl; 9208 int i, j; 9209 9210 switch (state) { 9211 case AMDGPU_IRQ_STATE_DISABLE: 9212 case AMDGPU_IRQ_STATE_ENABLE: 9213 for (i = 0; i < adev->gfx.me.num_me; i++) { 9214 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9215 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9216 9217 if (cp_int_cntl_reg) { 9218 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9219 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9220 OPCODE_ERROR_INT_ENABLE, 9221 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9222 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9223 } 9224 } 9225 } 9226 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9227 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9228 /* MECs start at 1 */ 9229 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j); 9230 9231 if (cp_int_cntl_reg) { 9232 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9233 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9234 OPCODE_ERROR_INT_ENABLE, 9235 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9236 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9237 } 9238 } 9239 } 9240 break; 9241 default: 9242 break; 9243 } 9244 return 0; 9245 } 9246 9247 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9248 struct amdgpu_irq_src *source, 9249 unsigned int type, 9250 enum amdgpu_interrupt_state state) 9251 { 9252 u32 cp_int_cntl_reg, cp_int_cntl; 9253 int i, j; 9254 9255 switch (state) { 9256 case AMDGPU_IRQ_STATE_DISABLE: 9257 case AMDGPU_IRQ_STATE_ENABLE: 9258 for (i = 0; i < adev->gfx.me.num_me; i++) { 9259 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9260 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); 9261 9262 if (cp_int_cntl_reg) { 9263 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9264 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9265 PRIV_INSTR_INT_ENABLE, 9266 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9267 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9268 } 9269 } 9270 } 9271 break; 9272 default: 9273 break; 9274 } 9275 9276 return 0; 9277 } 9278 9279 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9280 struct amdgpu_iv_entry *entry) 9281 { 9282 u8 me_id, pipe_id, queue_id; 9283 struct amdgpu_ring *ring; 9284 int i; 9285 9286 me_id = (entry->ring_id & 0x0c) >> 2; 9287 pipe_id = (entry->ring_id & 0x03) >> 0; 9288 queue_id = (entry->ring_id & 0x70) >> 4; 9289 9290 switch (me_id) { 9291 case 0: 9292 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9293 ring = &adev->gfx.gfx_ring[i]; 9294 if (ring->me == me_id && ring->pipe == pipe_id && 9295 ring->queue == queue_id) 9296 drm_sched_fault(&ring->sched); 9297 } 9298 break; 9299 case 1: 9300 case 2: 9301 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9302 ring = &adev->gfx.compute_ring[i]; 9303 if (ring->me == me_id && ring->pipe == pipe_id && 9304 ring->queue == queue_id) 9305 drm_sched_fault(&ring->sched); 9306 } 9307 break; 9308 default: 9309 BUG(); 9310 } 9311 } 9312 9313 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9314 struct amdgpu_irq_src *source, 9315 struct amdgpu_iv_entry *entry) 9316 { 9317 DRM_ERROR("Illegal register access in command stream\n"); 9318 gfx_v10_0_handle_priv_fault(adev, entry); 9319 return 0; 9320 } 9321 9322 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, 9323 struct amdgpu_irq_src *source, 9324 struct amdgpu_iv_entry *entry) 9325 { 9326 DRM_ERROR("Illegal opcode in command stream \n"); 9327 gfx_v10_0_handle_priv_fault(adev, entry); 9328 return 0; 9329 } 9330 9331 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9332 struct amdgpu_irq_src *source, 9333 struct amdgpu_iv_entry *entry) 9334 { 9335 DRM_ERROR("Illegal instruction in command stream\n"); 9336 gfx_v10_0_handle_priv_fault(adev, entry); 9337 return 0; 9338 } 9339 9340 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9341 struct amdgpu_irq_src *src, 9342 unsigned int type, 9343 enum amdgpu_interrupt_state state) 9344 { 9345 uint32_t tmp, target; 9346 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9347 9348 if (ring->me == 1) 9349 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9350 else 9351 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9352 target += ring->pipe; 9353 9354 switch (type) { 9355 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9356 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9357 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9358 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9359 GENERIC2_INT_ENABLE, 0); 9360 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9361 9362 tmp = RREG32_SOC15_IP(GC, target); 9363 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9364 GENERIC2_INT_ENABLE, 0); 9365 WREG32_SOC15_IP(GC, target, tmp); 9366 } else { 9367 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9368 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9369 GENERIC2_INT_ENABLE, 1); 9370 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9371 9372 tmp = RREG32_SOC15_IP(GC, target); 9373 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9374 GENERIC2_INT_ENABLE, 1); 9375 WREG32_SOC15_IP(GC, target, tmp); 9376 } 9377 break; 9378 default: 9379 BUG(); /* kiq only support GENERIC2_INT now */ 9380 break; 9381 } 9382 return 0; 9383 } 9384 9385 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9386 struct amdgpu_irq_src *source, 9387 struct amdgpu_iv_entry *entry) 9388 { 9389 u8 me_id, pipe_id, queue_id; 9390 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9391 9392 me_id = (entry->ring_id & 0x0c) >> 2; 9393 pipe_id = (entry->ring_id & 0x03) >> 0; 9394 queue_id = (entry->ring_id & 0x70) >> 4; 9395 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9396 me_id, pipe_id, queue_id); 9397 9398 amdgpu_fence_process(ring); 9399 return 0; 9400 } 9401 9402 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9403 { 9404 const unsigned int gcr_cntl = 9405 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9406 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9407 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9408 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9409 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9410 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9411 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9412 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9413 9414 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9415 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9416 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9417 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9418 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9419 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9420 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9421 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9422 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9423 } 9424 9425 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 9426 { 9427 /* Header itself is a NOP packet */ 9428 if (num_nop == 1) { 9429 amdgpu_ring_write(ring, ring->funcs->nop); 9430 return; 9431 } 9432 9433 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 9434 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 9435 9436 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 9437 amdgpu_ring_insert_nop(ring, num_nop - 1); 9438 } 9439 9440 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) 9441 { 9442 struct amdgpu_device *adev = ring->adev; 9443 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9444 struct amdgpu_ring *kiq_ring = &kiq->ring; 9445 unsigned long flags; 9446 u32 tmp; 9447 u64 addr; 9448 int r; 9449 9450 if (amdgpu_sriov_vf(adev)) 9451 return -EINVAL; 9452 9453 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9454 return -EINVAL; 9455 9456 spin_lock_irqsave(&kiq->ring_lock, flags); 9457 9458 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) { 9459 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9460 return -ENOMEM; 9461 } 9462 9463 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + 9464 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); 9465 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 9466 if (ring->pipe == 0) 9467 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); 9468 else 9469 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); 9470 9471 gfx_v10_0_ring_emit_wreg(kiq_ring, 9472 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); 9473 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, 9474 lower_32_bits(addr), upper_32_bits(addr), 9475 0, 1, 0x20); 9476 gfx_v10_0_ring_emit_reg_wait(kiq_ring, 9477 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); 9478 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9479 amdgpu_ring_commit(kiq_ring); 9480 9481 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9482 9483 r = amdgpu_ring_test_ring(kiq_ring); 9484 if (r) 9485 return r; 9486 9487 r = amdgpu_bo_reserve(ring->mqd_obj, false); 9488 if (unlikely(r != 0)) { 9489 DRM_ERROR("fail to resv mqd_obj\n"); 9490 return r; 9491 } 9492 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 9493 if (!r) { 9494 r = gfx_v10_0_kgq_init_queue(ring, true); 9495 amdgpu_bo_kunmap(ring->mqd_obj); 9496 ring->mqd_ptr = NULL; 9497 } 9498 amdgpu_bo_unreserve(ring->mqd_obj); 9499 if (r) { 9500 DRM_ERROR("fail to unresv mqd_obj\n"); 9501 return r; 9502 } 9503 9504 return amdgpu_ring_test_ring(ring); 9505 } 9506 9507 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, 9508 unsigned int vmid) 9509 { 9510 struct amdgpu_device *adev = ring->adev; 9511 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 9512 struct amdgpu_ring *kiq_ring = &kiq->ring; 9513 unsigned long flags; 9514 int i, r; 9515 9516 if (amdgpu_sriov_vf(adev)) 9517 return -EINVAL; 9518 9519 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 9520 return -EINVAL; 9521 9522 spin_lock_irqsave(&kiq->ring_lock, flags); 9523 9524 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 9525 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9526 return -ENOMEM; 9527 } 9528 9529 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 9530 0, 0); 9531 amdgpu_ring_commit(kiq_ring); 9532 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9533 9534 r = amdgpu_ring_test_ring(kiq_ring); 9535 if (r) 9536 return r; 9537 9538 /* make sure dequeue is complete*/ 9539 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 9540 mutex_lock(&adev->srbm_mutex); 9541 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 9542 for (i = 0; i < adev->usec_timeout; i++) { 9543 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 9544 break; 9545 udelay(1); 9546 } 9547 if (i >= adev->usec_timeout) 9548 r = -ETIMEDOUT; 9549 nv_grbm_select(adev, 0, 0, 0, 0); 9550 mutex_unlock(&adev->srbm_mutex); 9551 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 9552 if (r) { 9553 dev_err(adev->dev, "fail to wait on hqd deactivate\n"); 9554 return r; 9555 } 9556 9557 r = amdgpu_bo_reserve(ring->mqd_obj, false); 9558 if (unlikely(r != 0)) { 9559 dev_err(adev->dev, "fail to resv mqd_obj\n"); 9560 return r; 9561 } 9562 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 9563 if (!r) { 9564 r = gfx_v10_0_kcq_init_queue(ring, true); 9565 amdgpu_bo_kunmap(ring->mqd_obj); 9566 ring->mqd_ptr = NULL; 9567 } 9568 amdgpu_bo_unreserve(ring->mqd_obj); 9569 if (r) { 9570 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 9571 return r; 9572 } 9573 9574 spin_lock_irqsave(&kiq->ring_lock, flags); 9575 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { 9576 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9577 return -ENOMEM; 9578 } 9579 kiq->pmf->kiq_map_queues(kiq_ring, ring); 9580 amdgpu_ring_commit(kiq_ring); 9581 spin_unlock_irqrestore(&kiq->ring_lock, flags); 9582 9583 r = amdgpu_ring_test_ring(kiq_ring); 9584 if (r) 9585 return r; 9586 9587 return amdgpu_ring_test_ring(ring); 9588 } 9589 9590 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 9591 { 9592 struct amdgpu_device *adev = ip_block->adev; 9593 uint32_t i, j, k, reg, index = 0; 9594 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9595 9596 if (!adev->gfx.ip_dump_core) 9597 return; 9598 9599 for (i = 0; i < reg_count; i++) 9600 drm_printf(p, "%-50s \t 0x%08x\n", 9601 gc_reg_list_10_1[i].reg_name, 9602 adev->gfx.ip_dump_core[i]); 9603 9604 /* print compute queue registers for all instances */ 9605 if (!adev->gfx.ip_dump_compute_queues) 9606 return; 9607 9608 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9609 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 9610 adev->gfx.mec.num_mec, 9611 adev->gfx.mec.num_pipe_per_mec, 9612 adev->gfx.mec.num_queue_per_pipe); 9613 9614 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9615 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9616 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9617 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 9618 for (reg = 0; reg < reg_count; reg++) { 9619 drm_printf(p, "%-50s \t 0x%08x\n", 9620 gc_cp_reg_list_10[reg].reg_name, 9621 adev->gfx.ip_dump_compute_queues[index + reg]); 9622 } 9623 index += reg_count; 9624 } 9625 } 9626 } 9627 9628 /* print gfx queue registers for all instances */ 9629 if (!adev->gfx.ip_dump_gfx_queues) 9630 return; 9631 9632 index = 0; 9633 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9634 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 9635 adev->gfx.me.num_me, 9636 adev->gfx.me.num_pipe_per_me, 9637 adev->gfx.me.num_queue_per_pipe); 9638 9639 for (i = 0; i < adev->gfx.me.num_me; i++) { 9640 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9641 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9642 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 9643 for (reg = 0; reg < reg_count; reg++) { 9644 drm_printf(p, "%-50s \t 0x%08x\n", 9645 gc_gfx_queue_reg_list_10[reg].reg_name, 9646 adev->gfx.ip_dump_gfx_queues[index + reg]); 9647 } 9648 index += reg_count; 9649 } 9650 } 9651 } 9652 } 9653 9654 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) 9655 { 9656 struct amdgpu_device *adev = ip_block->adev; 9657 uint32_t i, j, k, reg, index = 0; 9658 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); 9659 9660 if (!adev->gfx.ip_dump_core) 9661 return; 9662 9663 amdgpu_gfx_off_ctrl(adev, false); 9664 for (i = 0; i < reg_count; i++) 9665 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); 9666 amdgpu_gfx_off_ctrl(adev, true); 9667 9668 /* dump compute queue registers for all instances */ 9669 if (!adev->gfx.ip_dump_compute_queues) 9670 return; 9671 9672 reg_count = ARRAY_SIZE(gc_cp_reg_list_10); 9673 amdgpu_gfx_off_ctrl(adev, false); 9674 mutex_lock(&adev->srbm_mutex); 9675 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 9676 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 9677 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 9678 /* ME0 is for GFX so start from 1 for CP */ 9679 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 9680 9681 for (reg = 0; reg < reg_count; reg++) { 9682 adev->gfx.ip_dump_compute_queues[index + reg] = 9683 RREG32(SOC15_REG_ENTRY_OFFSET( 9684 gc_cp_reg_list_10[reg])); 9685 } 9686 index += reg_count; 9687 } 9688 } 9689 } 9690 nv_grbm_select(adev, 0, 0, 0, 0); 9691 mutex_unlock(&adev->srbm_mutex); 9692 amdgpu_gfx_off_ctrl(adev, true); 9693 9694 /* dump gfx queue registers for all instances */ 9695 if (!adev->gfx.ip_dump_gfx_queues) 9696 return; 9697 9698 index = 0; 9699 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10); 9700 amdgpu_gfx_off_ctrl(adev, false); 9701 mutex_lock(&adev->srbm_mutex); 9702 for (i = 0; i < adev->gfx.me.num_me; i++) { 9703 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 9704 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 9705 nv_grbm_select(adev, i, j, k, 0); 9706 9707 for (reg = 0; reg < reg_count; reg++) { 9708 adev->gfx.ip_dump_gfx_queues[index + reg] = 9709 RREG32(SOC15_REG_ENTRY_OFFSET( 9710 gc_gfx_queue_reg_list_10[reg])); 9711 } 9712 index += reg_count; 9713 } 9714 } 9715 } 9716 nv_grbm_select(adev, 0, 0, 0, 0); 9717 mutex_unlock(&adev->srbm_mutex); 9718 amdgpu_gfx_off_ctrl(adev, true); 9719 } 9720 9721 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 9722 { 9723 /* Emit the cleaner shader */ 9724 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 9725 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 9726 } 9727 9728 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9729 .name = "gfx_v10_0", 9730 .early_init = gfx_v10_0_early_init, 9731 .late_init = gfx_v10_0_late_init, 9732 .sw_init = gfx_v10_0_sw_init, 9733 .sw_fini = gfx_v10_0_sw_fini, 9734 .hw_init = gfx_v10_0_hw_init, 9735 .hw_fini = gfx_v10_0_hw_fini, 9736 .suspend = gfx_v10_0_suspend, 9737 .resume = gfx_v10_0_resume, 9738 .is_idle = gfx_v10_0_is_idle, 9739 .wait_for_idle = gfx_v10_0_wait_for_idle, 9740 .soft_reset = gfx_v10_0_soft_reset, 9741 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9742 .set_powergating_state = gfx_v10_0_set_powergating_state, 9743 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9744 .dump_ip_state = gfx_v10_ip_dump, 9745 .print_ip_state = gfx_v10_ip_print, 9746 }; 9747 9748 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9749 .type = AMDGPU_RING_TYPE_GFX, 9750 .align_mask = 0xff, 9751 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9752 .support_64bit_ptrs = true, 9753 .secure_submission_supported = true, 9754 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9755 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9756 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9757 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9758 5 + /* COND_EXEC */ 9759 7 + /* PIPELINE_SYNC */ 9760 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9761 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9762 4 + /* VM_FLUSH */ 9763 8 + /* FENCE for VM_FLUSH */ 9764 20 + /* GDS switch */ 9765 4 + /* double SWITCH_BUFFER, 9766 * the first COND_EXEC jump to the place 9767 * just prior to this double SWITCH_BUFFER 9768 */ 9769 5 + /* COND_EXEC */ 9770 7 + /* HDP_flush */ 9771 4 + /* VGT_flush */ 9772 14 + /* CE_META */ 9773 31 + /* DE_META */ 9774 3 + /* CNTX_CTRL */ 9775 5 + /* HDP_INVL */ 9776 8 + 8 + /* FENCE x2 */ 9777 2 + /* SWITCH_BUFFER */ 9778 8 + /* gfx_v10_0_emit_mem_sync */ 9779 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9780 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9781 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9782 .emit_fence = gfx_v10_0_ring_emit_fence, 9783 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9784 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9785 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9786 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9787 .test_ring = gfx_v10_0_ring_test_ring, 9788 .test_ib = gfx_v10_0_ring_test_ib, 9789 .insert_nop = gfx_v10_ring_insert_nop, 9790 .pad_ib = amdgpu_ring_generic_pad_ib, 9791 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9792 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9793 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9794 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9795 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9796 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9797 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9798 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9799 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9800 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9801 .reset = gfx_v10_0_reset_kgq, 9802 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9803 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 9804 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 9805 }; 9806 9807 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9808 .type = AMDGPU_RING_TYPE_COMPUTE, 9809 .align_mask = 0xff, 9810 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9811 .support_64bit_ptrs = true, 9812 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9813 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9814 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9815 .emit_frame_size = 9816 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9817 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9818 5 + /* hdp invalidate */ 9819 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9820 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9821 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9822 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9823 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9824 8 + /* gfx_v10_0_emit_mem_sync */ 9825 2, /* gfx_v10_0_ring_emit_cleaner_shader */ 9826 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9827 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9828 .emit_fence = gfx_v10_0_ring_emit_fence, 9829 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9830 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9831 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9832 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9833 .test_ring = gfx_v10_0_ring_test_ring, 9834 .test_ib = gfx_v10_0_ring_test_ib, 9835 .insert_nop = gfx_v10_ring_insert_nop, 9836 .pad_ib = amdgpu_ring_generic_pad_ib, 9837 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9838 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9839 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9840 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9841 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9842 .reset = gfx_v10_0_reset_kcq, 9843 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, 9844 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 9845 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 9846 }; 9847 9848 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9849 .type = AMDGPU_RING_TYPE_KIQ, 9850 .align_mask = 0xff, 9851 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9852 .support_64bit_ptrs = true, 9853 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9854 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9855 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9856 .emit_frame_size = 9857 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9858 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9859 5 + /*hdp invalidate */ 9860 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9861 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9862 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9863 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9864 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9865 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9866 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9867 .test_ring = gfx_v10_0_ring_test_ring, 9868 .test_ib = gfx_v10_0_ring_test_ib, 9869 .insert_nop = amdgpu_ring_insert_nop, 9870 .pad_ib = amdgpu_ring_generic_pad_ib, 9871 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9872 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9873 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9874 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9875 }; 9876 9877 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9878 { 9879 int i; 9880 9881 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9882 9883 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9884 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9885 9886 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9887 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9888 } 9889 9890 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9891 .set = gfx_v10_0_set_eop_interrupt_state, 9892 .process = gfx_v10_0_eop_irq, 9893 }; 9894 9895 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9896 .set = gfx_v10_0_set_priv_reg_fault_state, 9897 .process = gfx_v10_0_priv_reg_irq, 9898 }; 9899 9900 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = { 9901 .set = gfx_v10_0_set_bad_op_fault_state, 9902 .process = gfx_v10_0_bad_op_irq, 9903 }; 9904 9905 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9906 .set = gfx_v10_0_set_priv_inst_fault_state, 9907 .process = gfx_v10_0_priv_inst_irq, 9908 }; 9909 9910 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9911 .set = gfx_v10_0_kiq_set_interrupt_state, 9912 .process = gfx_v10_0_kiq_irq, 9913 }; 9914 9915 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9916 { 9917 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9918 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9919 9920 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9921 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9922 9923 adev->gfx.priv_reg_irq.num_types = 1; 9924 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9925 9926 adev->gfx.bad_op_irq.num_types = 1; 9927 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; 9928 9929 adev->gfx.priv_inst_irq.num_types = 1; 9930 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9931 } 9932 9933 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9934 { 9935 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 9936 case IP_VERSION(10, 1, 10): 9937 case IP_VERSION(10, 1, 1): 9938 case IP_VERSION(10, 1, 3): 9939 case IP_VERSION(10, 1, 4): 9940 case IP_VERSION(10, 3, 2): 9941 case IP_VERSION(10, 3, 1): 9942 case IP_VERSION(10, 3, 4): 9943 case IP_VERSION(10, 3, 5): 9944 case IP_VERSION(10, 3, 6): 9945 case IP_VERSION(10, 3, 3): 9946 case IP_VERSION(10, 3, 7): 9947 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9948 break; 9949 case IP_VERSION(10, 1, 2): 9950 case IP_VERSION(10, 3, 0): 9951 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9952 break; 9953 default: 9954 break; 9955 } 9956 } 9957 9958 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9959 { 9960 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9961 adev->gfx.config.max_sh_per_se * 9962 adev->gfx.config.max_shader_engines; 9963 9964 adev->gds.gds_size = 0x10000; 9965 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9966 adev->gds.gws_size = 64; 9967 adev->gds.oa_size = 16; 9968 } 9969 9970 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9971 { 9972 /* set gfx eng mqd */ 9973 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9974 sizeof(struct v10_gfx_mqd); 9975 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9976 gfx_v10_0_gfx_mqd_init; 9977 /* set compute eng mqd */ 9978 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9979 sizeof(struct v10_compute_mqd); 9980 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9981 gfx_v10_0_compute_mqd_init; 9982 } 9983 9984 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9985 u32 bitmap) 9986 { 9987 u32 data; 9988 9989 if (!bitmap) 9990 return; 9991 9992 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9993 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9994 9995 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9996 } 9997 9998 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9999 { 10000 u32 disabled_mask = 10001 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 10002 u32 efuse_setting = 0; 10003 u32 vbios_setting = 0; 10004 10005 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 10006 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10007 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10008 10009 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 10010 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 10011 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 10012 10013 disabled_mask |= efuse_setting | vbios_setting; 10014 10015 return (~disabled_mask); 10016 } 10017 10018 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 10019 { 10020 u32 wgp_idx, wgp_active_bitmap; 10021 u32 cu_bitmap_per_wgp, cu_active_bitmap; 10022 10023 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 10024 cu_active_bitmap = 0; 10025 10026 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 10027 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 10028 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 10029 if (wgp_active_bitmap & (1 << wgp_idx)) 10030 cu_active_bitmap |= cu_bitmap_per_wgp; 10031 } 10032 10033 return cu_active_bitmap; 10034 } 10035 10036 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 10037 struct amdgpu_cu_info *cu_info) 10038 { 10039 int i, j, k, counter, active_cu_number = 0; 10040 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 10041 unsigned int disable_masks[4 * 2]; 10042 10043 if (!adev || !cu_info) 10044 return -EINVAL; 10045 10046 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 10047 10048 mutex_lock(&adev->grbm_idx_mutex); 10049 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 10050 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 10051 bitmap = i * adev->gfx.config.max_sh_per_se + j; 10052 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == 10053 IP_VERSION(10, 3, 0)) || 10054 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10055 IP_VERSION(10, 3, 3)) || 10056 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10057 IP_VERSION(10, 3, 6)) || 10058 (amdgpu_ip_version(adev, GC_HWIP, 0) == 10059 IP_VERSION(10, 3, 7))) && 10060 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 10061 continue; 10062 mask = 1; 10063 ao_bitmap = 0; 10064 counter = 0; 10065 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 10066 if (i < 4 && j < 2) 10067 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 10068 adev, disable_masks[i * 2 + j]); 10069 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 10070 cu_info->bitmap[0][i][j] = bitmap; 10071 10072 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 10073 if (bitmap & mask) { 10074 if (counter < adev->gfx.config.max_cu_per_sh) 10075 ao_bitmap |= mask; 10076 counter++; 10077 } 10078 mask <<= 1; 10079 } 10080 active_cu_number += counter; 10081 if (i < 2 && j < 2) 10082 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 10083 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 10084 } 10085 } 10086 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 10087 mutex_unlock(&adev->grbm_idx_mutex); 10088 10089 cu_info->number = active_cu_number; 10090 cu_info->ao_cu_mask = ao_cu_mask; 10091 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 10092 10093 return 0; 10094 } 10095 10096 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 10097 { 10098 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 10099 10100 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 10101 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10102 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10103 10104 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 10105 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 10106 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 10107 10108 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 10109 adev->gfx.config.max_shader_engines); 10110 disabled_sa = efuse_setting | vbios_setting; 10111 disabled_sa &= max_sa_mask; 10112 10113 return disabled_sa; 10114 } 10115 10116 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 10117 { 10118 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 10119 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 10120 10121 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 10122 10123 max_sa_per_se = adev->gfx.config.max_sh_per_se; 10124 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 10125 max_shader_engines = adev->gfx.config.max_shader_engines; 10126 10127 for (se_index = 0; max_shader_engines > se_index; se_index++) { 10128 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 10129 disabled_sa_per_se &= max_sa_per_se_mask; 10130 if (disabled_sa_per_se == max_sa_per_se_mask) { 10131 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 10132 break; 10133 } 10134 } 10135 } 10136 10137 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 10138 { 10139 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 10140 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 10141 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 10142 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 10143 10144 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 10145 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 10146 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 10147 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 10148 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 10149 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 10150 10151 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 10152 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 10153 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 10154 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 10155 10156 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 10157 10158 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 10159 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 10160 } 10161 10162 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 10163 .type = AMD_IP_BLOCK_TYPE_GFX, 10164 .major = 10, 10165 .minor = 0, 10166 .rev = 0, 10167 .funcs = &gfx_v10_0_ip_funcs, 10168 }; 10169