1*038d757bSTao Zhou /*
2*038d757bSTao Zhou * Copyright 2020 Advanced Micro Devices, Inc.
3*038d757bSTao Zhou *
4*038d757bSTao Zhou * Permission is hereby granted, free of charge, to any person obtaining a
5*038d757bSTao Zhou * copy of this software and associated documentation files (the "Software"),
6*038d757bSTao Zhou * to deal in the Software without restriction, including without limitation
7*038d757bSTao Zhou * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*038d757bSTao Zhou * and/or sell copies of the Software, and to permit persons to whom the
9*038d757bSTao Zhou * Software is furnished to do so, subject to the following conditions:
10*038d757bSTao Zhou *
11*038d757bSTao Zhou * The above copyright notice and this permission notice shall be included in
12*038d757bSTao Zhou * all copies or substantial portions of the Software.
13*038d757bSTao Zhou *
14*038d757bSTao Zhou * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*038d757bSTao Zhou * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*038d757bSTao Zhou * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*038d757bSTao Zhou * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*038d757bSTao Zhou * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*038d757bSTao Zhou * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*038d757bSTao Zhou * OTHER DEALINGS IN THE SOFTWARE.
21*038d757bSTao Zhou *
22*038d757bSTao Zhou */
23*038d757bSTao Zhou #include "amdgpu.h"
24*038d757bSTao Zhou #include "nv.h"
25*038d757bSTao Zhou
26*038d757bSTao Zhou #include "soc15_common.h"
27*038d757bSTao Zhou #include "soc15_hw_ip.h"
28*038d757bSTao Zhou #include "dimgrey_cavefish_ip_offset.h"
29*038d757bSTao Zhou
dimgrey_cavefish_reg_base_init(struct amdgpu_device * adev)30*038d757bSTao Zhou int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev)
31*038d757bSTao Zhou {
32*038d757bSTao Zhou /* HW has more IP blocks, only initialize the block needed by driver */
33*038d757bSTao Zhou uint32_t i;
34*038d757bSTao Zhou for (i = 0 ; i < MAX_INSTANCE ; ++i) {
35*038d757bSTao Zhou adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36*038d757bSTao Zhou adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37*038d757bSTao Zhou adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38*038d757bSTao Zhou adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39*038d757bSTao Zhou adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40*038d757bSTao Zhou adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41*038d757bSTao Zhou adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42*038d757bSTao Zhou adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
43*038d757bSTao Zhou adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44*038d757bSTao Zhou adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
45*038d757bSTao Zhou adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
46*038d757bSTao Zhou adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
47*038d757bSTao Zhou adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
48*038d757bSTao Zhou adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
49*038d757bSTao Zhou adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
50*038d757bSTao Zhou adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
51*038d757bSTao Zhou adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
52*038d757bSTao Zhou }
53*038d757bSTao Zhou return 0;
54*038d757bSTao Zhou }
55