1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "df_v3_6.h" 25 26 #include "df/df_3_6_default.h" 27 #include "df/df_3_6_offset.h" 28 #include "df/df_3_6_sh_mask.h" 29 30 static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 31 16, 32, 0, 0, 0, 2, 4, 8}; 32 33 static void df_v3_6_init(struct amdgpu_device *adev) 34 { 35 } 36 37 static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev, 38 bool enable) 39 { 40 u32 tmp; 41 42 if (enable) { 43 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); 44 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; 45 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); 46 } else 47 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, 48 mmFabricConfigAccessControl_DEFAULT); 49 } 50 51 static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) 52 { 53 u32 tmp; 54 55 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); 56 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; 57 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 58 59 return tmp; 60 } 61 62 static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev) 63 { 64 int fb_channel_number; 65 66 fb_channel_number = adev->df_funcs->get_fb_channel_number(adev); 67 if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number)) 68 fb_channel_number = 0; 69 70 return df_v3_6_channel_number[fb_channel_number]; 71 } 72 73 static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, 74 bool enable) 75 { 76 u32 tmp; 77 78 /* Put DF on broadcast mode */ 79 adev->df_funcs->enable_broadcast_mode(adev, true); 80 81 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { 82 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); 83 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 84 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY; 85 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); 86 } else { 87 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); 88 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 89 tmp |= DF_V3_6_MGCG_DISABLE; 90 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); 91 } 92 93 /* Exit broadcast mode */ 94 adev->df_funcs->enable_broadcast_mode(adev, false); 95 } 96 97 static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, 98 u32 *flags) 99 { 100 u32 tmp; 101 102 /* AMD_CG_SUPPORT_DF_MGCG */ 103 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); 104 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY) 105 *flags |= AMD_CG_SUPPORT_DF_MGCG; 106 } 107 108 const struct amdgpu_df_funcs df_v3_6_funcs = { 109 .init = df_v3_6_init, 110 .enable_broadcast_mode = df_v3_6_enable_broadcast_mode, 111 .get_fb_channel_number = df_v3_6_get_fb_channel_number, 112 .get_hbm_channel_number = df_v3_6_get_hbm_channel_number, 113 .update_medium_grain_clock_gating = 114 df_v3_6_update_medium_grain_clock_gating, 115 .get_clockgating_state = df_v3_6_get_clockgating_state, 116 }; 117