1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "cikd.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_8_0_d.h" 36 #include "dce/dce_8_0_sh_mask.h" 37 38 #include "gca/gfx_7_2_enum.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); 47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); 48 49 static const u32 crtc_offsets[6] = 50 { 51 CRTC0_REGISTER_OFFSET, 52 CRTC1_REGISTER_OFFSET, 53 CRTC2_REGISTER_OFFSET, 54 CRTC3_REGISTER_OFFSET, 55 CRTC4_REGISTER_OFFSET, 56 CRTC5_REGISTER_OFFSET 57 }; 58 59 static const uint32_t dig_offsets[] = { 60 CRTC0_REGISTER_OFFSET, 61 CRTC1_REGISTER_OFFSET, 62 CRTC2_REGISTER_OFFSET, 63 CRTC3_REGISTER_OFFSET, 64 CRTC4_REGISTER_OFFSET, 65 CRTC5_REGISTER_OFFSET, 66 (0x13830 - 0x7030) >> 2, 67 }; 68 69 static const struct { 70 uint32_t reg; 71 uint32_t vblank; 72 uint32_t vline; 73 uint32_t hpd; 74 75 } interrupt_status_offsets[6] = { { 76 .reg = mmDISP_INTERRUPT_STATUS, 77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 80 }, { 81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 85 }, { 86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 105 } }; 106 107 static const uint32_t hpd_int_control_offsets[6] = { 108 mmDC_HPD1_INT_CONTROL, 109 mmDC_HPD2_INT_CONTROL, 110 mmDC_HPD3_INT_CONTROL, 111 mmDC_HPD4_INT_CONTROL, 112 mmDC_HPD5_INT_CONTROL, 113 mmDC_HPD6_INT_CONTROL, 114 }; 115 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, 117 u32 block_offset, u32 reg) 118 { 119 unsigned long flags; 120 u32 r; 121 122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 126 127 return r; 128 } 129 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, 131 u32 block_offset, u32 reg, u32 v) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 139 } 140 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 142 { 143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 145 return true; 146 else 147 return false; 148 } 149 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 151 { 152 u32 pos1, pos2; 153 154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 156 157 if (pos1 != pos2) 158 return true; 159 else 160 return false; 161 } 162 163 /** 164 * dce_v8_0_vblank_wait - vblank wait asic callback. 165 * 166 * @adev: amdgpu_device pointer 167 * @crtc: crtc to wait for vblank on 168 * 169 * Wait for vblank on the requested crtc (evergreen+). 170 */ 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) 172 { 173 unsigned i = 0; 174 175 if (crtc >= adev->mode_info.num_crtc) 176 return; 177 178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 179 return; 180 181 /* depending on when we hit vblank, we may be close to active; if so, 182 * wait for another frame. 183 */ 184 while (dce_v8_0_is_in_vblank(adev, crtc)) { 185 if (i++ % 100 == 0) { 186 if (!dce_v8_0_is_counter_moving(adev, crtc)) 187 break; 188 } 189 } 190 191 while (!dce_v8_0_is_in_vblank(adev, crtc)) { 192 if (i++ % 100 == 0) { 193 if (!dce_v8_0_is_counter_moving(adev, crtc)) 194 break; 195 } 196 } 197 } 198 199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 200 { 201 if (crtc >= adev->mode_info.num_crtc) 202 return 0; 203 else 204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 205 } 206 207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) 208 { 209 unsigned i; 210 211 /* Enable pflip interrupts */ 212 for (i = 0; i < adev->mode_info.num_crtc; i++) 213 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 214 } 215 216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 217 { 218 unsigned i; 219 220 /* Disable pflip interrupts */ 221 for (i = 0; i < adev->mode_info.num_crtc; i++) 222 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 223 } 224 225 /** 226 * dce_v8_0_page_flip - pageflip callback. 227 * 228 * @adev: amdgpu_device pointer 229 * @crtc_id: crtc to cleanup pageflip on 230 * @crtc_base: new address of the crtc (GPU MC address) 231 * 232 * Triggers the actual pageflip by updating the primary 233 * surface base address. 234 */ 235 static void dce_v8_0_page_flip(struct amdgpu_device *adev, 236 int crtc_id, u64 crtc_base, bool async) 237 { 238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 239 240 /* flip at hsync for async, default is vsync */ 241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 243 /* update the primary scanout addresses */ 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 245 upper_32_bits(crtc_base)); 246 /* writing to the low address triggers the update */ 247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 248 lower_32_bits(crtc_base)); 249 /* post the write */ 250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 251 } 252 253 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 254 u32 *vbl, u32 *position) 255 { 256 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 257 return -EINVAL; 258 259 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 260 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 261 262 return 0; 263 } 264 265 /** 266 * dce_v8_0_hpd_sense - hpd sense callback. 267 * 268 * @adev: amdgpu_device pointer 269 * @hpd: hpd (hotplug detect) pin 270 * 271 * Checks if a digital monitor is connected (evergreen+). 272 * Returns true if connected, false if not connected. 273 */ 274 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, 275 enum amdgpu_hpd_id hpd) 276 { 277 bool connected = false; 278 279 switch (hpd) { 280 case AMDGPU_HPD_1: 281 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 282 connected = true; 283 break; 284 case AMDGPU_HPD_2: 285 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) 286 connected = true; 287 break; 288 case AMDGPU_HPD_3: 289 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) 290 connected = true; 291 break; 292 case AMDGPU_HPD_4: 293 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) 294 connected = true; 295 break; 296 case AMDGPU_HPD_5: 297 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) 298 connected = true; 299 break; 300 case AMDGPU_HPD_6: 301 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) 302 connected = true; 303 break; 304 default: 305 break; 306 } 307 308 return connected; 309 } 310 311 /** 312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback. 313 * 314 * @adev: amdgpu_device pointer 315 * @hpd: hpd (hotplug detect) pin 316 * 317 * Set the polarity of the hpd pin (evergreen+). 318 */ 319 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, 320 enum amdgpu_hpd_id hpd) 321 { 322 u32 tmp; 323 bool connected = dce_v8_0_hpd_sense(adev, hpd); 324 325 switch (hpd) { 326 case AMDGPU_HPD_1: 327 tmp = RREG32(mmDC_HPD1_INT_CONTROL); 328 if (connected) 329 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 330 else 331 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 332 WREG32(mmDC_HPD1_INT_CONTROL, tmp); 333 break; 334 case AMDGPU_HPD_2: 335 tmp = RREG32(mmDC_HPD2_INT_CONTROL); 336 if (connected) 337 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 338 else 339 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 340 WREG32(mmDC_HPD2_INT_CONTROL, tmp); 341 break; 342 case AMDGPU_HPD_3: 343 tmp = RREG32(mmDC_HPD3_INT_CONTROL); 344 if (connected) 345 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 346 else 347 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 348 WREG32(mmDC_HPD3_INT_CONTROL, tmp); 349 break; 350 case AMDGPU_HPD_4: 351 tmp = RREG32(mmDC_HPD4_INT_CONTROL); 352 if (connected) 353 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 354 else 355 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 356 WREG32(mmDC_HPD4_INT_CONTROL, tmp); 357 break; 358 case AMDGPU_HPD_5: 359 tmp = RREG32(mmDC_HPD5_INT_CONTROL); 360 if (connected) 361 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 362 else 363 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 364 WREG32(mmDC_HPD5_INT_CONTROL, tmp); 365 break; 366 case AMDGPU_HPD_6: 367 tmp = RREG32(mmDC_HPD6_INT_CONTROL); 368 if (connected) 369 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 370 else 371 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 372 WREG32(mmDC_HPD6_INT_CONTROL, tmp); 373 break; 374 default: 375 break; 376 } 377 } 378 379 /** 380 * dce_v8_0_hpd_init - hpd setup callback. 381 * 382 * @adev: amdgpu_device pointer 383 * 384 * Setup the hpd pins used by the card (evergreen+). 385 * Enable the pin, set the polarity, and enable the hpd interrupts. 386 */ 387 static void dce_v8_0_hpd_init(struct amdgpu_device *adev) 388 { 389 struct drm_device *dev = adev->ddev; 390 struct drm_connector *connector; 391 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) | 392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) | 393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 394 395 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 396 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 397 398 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 399 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 400 /* don't try to enable hpd on eDP or LVDS avoid breaking the 401 * aux dp channel on imac and help (but not completely fix) 402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 403 * also avoid interrupt storms during dpms. 404 */ 405 continue; 406 } 407 switch (amdgpu_connector->hpd.hpd) { 408 case AMDGPU_HPD_1: 409 WREG32(mmDC_HPD1_CONTROL, tmp); 410 break; 411 case AMDGPU_HPD_2: 412 WREG32(mmDC_HPD2_CONTROL, tmp); 413 break; 414 case AMDGPU_HPD_3: 415 WREG32(mmDC_HPD3_CONTROL, tmp); 416 break; 417 case AMDGPU_HPD_4: 418 WREG32(mmDC_HPD4_CONTROL, tmp); 419 break; 420 case AMDGPU_HPD_5: 421 WREG32(mmDC_HPD5_CONTROL, tmp); 422 break; 423 case AMDGPU_HPD_6: 424 WREG32(mmDC_HPD6_CONTROL, tmp); 425 break; 426 default: 427 break; 428 } 429 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 430 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 431 } 432 } 433 434 /** 435 * dce_v8_0_hpd_fini - hpd tear down callback. 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Tear down the hpd pins used by the card (evergreen+). 440 * Disable the hpd interrupts. 441 */ 442 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) 443 { 444 struct drm_device *dev = adev->ddev; 445 struct drm_connector *connector; 446 447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 448 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 449 450 switch (amdgpu_connector->hpd.hpd) { 451 case AMDGPU_HPD_1: 452 WREG32(mmDC_HPD1_CONTROL, 0); 453 break; 454 case AMDGPU_HPD_2: 455 WREG32(mmDC_HPD2_CONTROL, 0); 456 break; 457 case AMDGPU_HPD_3: 458 WREG32(mmDC_HPD3_CONTROL, 0); 459 break; 460 case AMDGPU_HPD_4: 461 WREG32(mmDC_HPD4_CONTROL, 0); 462 break; 463 case AMDGPU_HPD_5: 464 WREG32(mmDC_HPD5_CONTROL, 0); 465 break; 466 case AMDGPU_HPD_6: 467 WREG32(mmDC_HPD6_CONTROL, 0); 468 break; 469 default: 470 break; 471 } 472 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 473 } 474 } 475 476 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 477 { 478 return mmDC_GPIO_HPD_A; 479 } 480 481 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) 482 { 483 u32 crtc_hung = 0; 484 u32 crtc_status[6]; 485 u32 i, j, tmp; 486 487 for (i = 0; i < adev->mode_info.num_crtc; i++) { 488 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 489 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 490 crtc_hung |= (1 << i); 491 } 492 } 493 494 for (j = 0; j < 10; j++) { 495 for (i = 0; i < adev->mode_info.num_crtc; i++) { 496 if (crtc_hung & (1 << i)) { 497 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 498 if (tmp != crtc_status[i]) 499 crtc_hung &= ~(1 << i); 500 } 501 } 502 if (crtc_hung == 0) 503 return false; 504 udelay(100); 505 } 506 507 return true; 508 } 509 510 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 511 struct amdgpu_mode_mc_save *save) 512 { 513 u32 crtc_enabled, tmp; 514 int i; 515 516 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 517 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 518 519 /* disable VGA render */ 520 tmp = RREG32(mmVGA_RENDER_CONTROL); 521 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 522 WREG32(mmVGA_RENDER_CONTROL, tmp); 523 524 /* blank the display controllers */ 525 for (i = 0; i < adev->mode_info.num_crtc; i++) { 526 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 527 CRTC_CONTROL, CRTC_MASTER_EN); 528 if (crtc_enabled) { 529 #if 0 530 u32 frame_count; 531 int j; 532 533 save->crtc_enabled[i] = true; 534 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 535 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 536 amdgpu_display_vblank_wait(adev, i); 537 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 538 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 539 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 540 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 541 } 542 /* wait for the next frame */ 543 frame_count = amdgpu_display_vblank_get_counter(adev, i); 544 for (j = 0; j < adev->usec_timeout; j++) { 545 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 546 break; 547 udelay(1); 548 } 549 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 550 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 551 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 552 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 553 } 554 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 555 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 556 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 557 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 558 } 559 #else 560 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 561 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 562 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 563 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 564 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 565 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 566 save->crtc_enabled[i] = false; 567 /* ***** */ 568 #endif 569 } else { 570 save->crtc_enabled[i] = false; 571 } 572 } 573 } 574 575 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, 576 struct amdgpu_mode_mc_save *save) 577 { 578 u32 tmp, frame_count; 579 int i, j; 580 581 /* update crtc base addresses */ 582 for (i = 0; i < adev->mode_info.num_crtc; i++) { 583 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 584 upper_32_bits(adev->mc.vram_start)); 585 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 586 upper_32_bits(adev->mc.vram_start)); 587 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 588 (u32)adev->mc.vram_start); 589 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 590 (u32)adev->mc.vram_start); 591 592 if (save->crtc_enabled[i]) { 593 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 594 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 595 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 596 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 597 } 598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 602 } 603 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 604 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 605 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 606 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 607 } 608 for (j = 0; j < adev->usec_timeout; j++) { 609 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 610 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 611 break; 612 udelay(1); 613 } 614 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 615 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 616 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 617 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 618 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 619 /* wait for the next frame */ 620 frame_count = amdgpu_display_vblank_get_counter(adev, i); 621 for (j = 0; j < adev->usec_timeout; j++) { 622 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 623 break; 624 udelay(1); 625 } 626 } 627 } 628 629 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 630 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 631 632 /* Unlock vga access */ 633 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 634 mdelay(1); 635 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 636 } 637 638 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, 639 bool render) 640 { 641 u32 tmp; 642 643 /* Lockout access through VGA aperture*/ 644 tmp = RREG32(mmVGA_HDP_CONTROL); 645 if (render) 646 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 647 else 648 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 649 WREG32(mmVGA_HDP_CONTROL, tmp); 650 651 /* disable VGA render */ 652 tmp = RREG32(mmVGA_RENDER_CONTROL); 653 if (render) 654 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 655 else 656 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 657 WREG32(mmVGA_RENDER_CONTROL, tmp); 658 } 659 660 static void dce_v8_0_program_fmt(struct drm_encoder *encoder) 661 { 662 struct drm_device *dev = encoder->dev; 663 struct amdgpu_device *adev = dev->dev_private; 664 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 665 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 666 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 667 int bpc = 0; 668 u32 tmp = 0; 669 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 670 671 if (connector) { 672 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 673 bpc = amdgpu_connector_get_monitor_bpc(connector); 674 dither = amdgpu_connector->dither; 675 } 676 677 /* LVDS/eDP FMT is set up by atom */ 678 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 679 return; 680 681 /* not needed for analog */ 682 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 683 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 684 return; 685 686 if (bpc == 0) 687 return; 688 689 switch (bpc) { 690 case 6: 691 if (dither == AMDGPU_FMT_DITHER_ENABLE) 692 /* XXX sort out optimal dither settings */ 693 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 694 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 695 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 696 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 697 else 698 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 699 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 700 break; 701 case 8: 702 if (dither == AMDGPU_FMT_DITHER_ENABLE) 703 /* XXX sort out optimal dither settings */ 704 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 705 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 706 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 707 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 708 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 709 else 710 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 711 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 712 break; 713 case 10: 714 if (dither == AMDGPU_FMT_DITHER_ENABLE) 715 /* XXX sort out optimal dither settings */ 716 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 717 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 718 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 719 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 720 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 721 else 722 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 723 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 724 break; 725 default: 726 /* not needed */ 727 break; 728 } 729 730 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 731 } 732 733 734 /* display watermark setup */ 735 /** 736 * dce_v8_0_line_buffer_adjust - Set up the line buffer 737 * 738 * @adev: amdgpu_device pointer 739 * @amdgpu_crtc: the selected display controller 740 * @mode: the current display mode on the selected display 741 * controller 742 * 743 * Setup up the line buffer allocation for 744 * the selected display controller (CIK). 745 * Returns the line buffer size in pixels. 746 */ 747 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, 748 struct amdgpu_crtc *amdgpu_crtc, 749 struct drm_display_mode *mode) 750 { 751 u32 tmp, buffer_alloc, i; 752 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 753 /* 754 * Line Buffer Setup 755 * There are 6 line buffers, one for each display controllers. 756 * There are 3 partitions per LB. Select the number of partitions 757 * to enable based on the display width. For display widths larger 758 * than 4096, you need use to use 2 display controllers and combine 759 * them using the stereo blender. 760 */ 761 if (amdgpu_crtc->base.enabled && mode) { 762 if (mode->crtc_hdisplay < 1920) { 763 tmp = 1; 764 buffer_alloc = 2; 765 } else if (mode->crtc_hdisplay < 2560) { 766 tmp = 2; 767 buffer_alloc = 2; 768 } else if (mode->crtc_hdisplay < 4096) { 769 tmp = 0; 770 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 771 } else { 772 DRM_DEBUG_KMS("Mode too big for LB!\n"); 773 tmp = 0; 774 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 775 } 776 } else { 777 tmp = 1; 778 buffer_alloc = 0; 779 } 780 781 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, 782 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) | 783 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT)); 784 785 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 786 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 787 for (i = 0; i < adev->usec_timeout; i++) { 788 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 789 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 790 break; 791 udelay(1); 792 } 793 794 if (amdgpu_crtc->base.enabled && mode) { 795 switch (tmp) { 796 case 0: 797 default: 798 return 4096 * 2; 799 case 1: 800 return 1920 * 2; 801 case 2: 802 return 2560 * 2; 803 } 804 } 805 806 /* controller not enabled, so no lb used */ 807 return 0; 808 } 809 810 /** 811 * cik_get_number_of_dram_channels - get the number of dram channels 812 * 813 * @adev: amdgpu_device pointer 814 * 815 * Look up the number of video ram channels (CIK). 816 * Used for display watermark bandwidth calculations 817 * Returns the number of dram channels 818 */ 819 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 820 { 821 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 822 823 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 824 case 0: 825 default: 826 return 1; 827 case 1: 828 return 2; 829 case 2: 830 return 4; 831 case 3: 832 return 8; 833 case 4: 834 return 3; 835 case 5: 836 return 6; 837 case 6: 838 return 10; 839 case 7: 840 return 12; 841 case 8: 842 return 16; 843 } 844 } 845 846 struct dce8_wm_params { 847 u32 dram_channels; /* number of dram channels */ 848 u32 yclk; /* bandwidth per dram data pin in kHz */ 849 u32 sclk; /* engine clock in kHz */ 850 u32 disp_clk; /* display clock in kHz */ 851 u32 src_width; /* viewport width */ 852 u32 active_time; /* active display time in ns */ 853 u32 blank_time; /* blank time in ns */ 854 bool interlaced; /* mode is interlaced */ 855 fixed20_12 vsc; /* vertical scale ratio */ 856 u32 num_heads; /* number of active crtcs */ 857 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 858 u32 lb_size; /* line buffer allocated to pipe */ 859 u32 vtaps; /* vertical scaler taps */ 860 }; 861 862 /** 863 * dce_v8_0_dram_bandwidth - get the dram bandwidth 864 * 865 * @wm: watermark calculation data 866 * 867 * Calculate the raw dram bandwidth (CIK). 868 * Used for display watermark bandwidth calculations 869 * Returns the dram bandwidth in MBytes/s 870 */ 871 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) 872 { 873 /* Calculate raw DRAM Bandwidth */ 874 fixed20_12 dram_efficiency; /* 0.7 */ 875 fixed20_12 yclk, dram_channels, bandwidth; 876 fixed20_12 a; 877 878 a.full = dfixed_const(1000); 879 yclk.full = dfixed_const(wm->yclk); 880 yclk.full = dfixed_div(yclk, a); 881 dram_channels.full = dfixed_const(wm->dram_channels * 4); 882 a.full = dfixed_const(10); 883 dram_efficiency.full = dfixed_const(7); 884 dram_efficiency.full = dfixed_div(dram_efficiency, a); 885 bandwidth.full = dfixed_mul(dram_channels, yclk); 886 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 887 888 return dfixed_trunc(bandwidth); 889 } 890 891 /** 892 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display 893 * 894 * @wm: watermark calculation data 895 * 896 * Calculate the dram bandwidth used for display (CIK). 897 * Used for display watermark bandwidth calculations 898 * Returns the dram bandwidth for display in MBytes/s 899 */ 900 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) 901 { 902 /* Calculate DRAM Bandwidth and the part allocated to display. */ 903 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 904 fixed20_12 yclk, dram_channels, bandwidth; 905 fixed20_12 a; 906 907 a.full = dfixed_const(1000); 908 yclk.full = dfixed_const(wm->yclk); 909 yclk.full = dfixed_div(yclk, a); 910 dram_channels.full = dfixed_const(wm->dram_channels * 4); 911 a.full = dfixed_const(10); 912 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 913 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 914 bandwidth.full = dfixed_mul(dram_channels, yclk); 915 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 916 917 return dfixed_trunc(bandwidth); 918 } 919 920 /** 921 * dce_v8_0_data_return_bandwidth - get the data return bandwidth 922 * 923 * @wm: watermark calculation data 924 * 925 * Calculate the data return bandwidth used for display (CIK). 926 * Used for display watermark bandwidth calculations 927 * Returns the data return bandwidth in MBytes/s 928 */ 929 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) 930 { 931 /* Calculate the display Data return Bandwidth */ 932 fixed20_12 return_efficiency; /* 0.8 */ 933 fixed20_12 sclk, bandwidth; 934 fixed20_12 a; 935 936 a.full = dfixed_const(1000); 937 sclk.full = dfixed_const(wm->sclk); 938 sclk.full = dfixed_div(sclk, a); 939 a.full = dfixed_const(10); 940 return_efficiency.full = dfixed_const(8); 941 return_efficiency.full = dfixed_div(return_efficiency, a); 942 a.full = dfixed_const(32); 943 bandwidth.full = dfixed_mul(a, sclk); 944 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 945 946 return dfixed_trunc(bandwidth); 947 } 948 949 /** 950 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth 951 * 952 * @wm: watermark calculation data 953 * 954 * Calculate the dmif bandwidth used for display (CIK). 955 * Used for display watermark bandwidth calculations 956 * Returns the dmif bandwidth in MBytes/s 957 */ 958 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) 959 { 960 /* Calculate the DMIF Request Bandwidth */ 961 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 962 fixed20_12 disp_clk, bandwidth; 963 fixed20_12 a, b; 964 965 a.full = dfixed_const(1000); 966 disp_clk.full = dfixed_const(wm->disp_clk); 967 disp_clk.full = dfixed_div(disp_clk, a); 968 a.full = dfixed_const(32); 969 b.full = dfixed_mul(a, disp_clk); 970 971 a.full = dfixed_const(10); 972 disp_clk_request_efficiency.full = dfixed_const(8); 973 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 974 975 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 976 977 return dfixed_trunc(bandwidth); 978 } 979 980 /** 981 * dce_v8_0_available_bandwidth - get the min available bandwidth 982 * 983 * @wm: watermark calculation data 984 * 985 * Calculate the min available bandwidth used for display (CIK). 986 * Used for display watermark bandwidth calculations 987 * Returns the min available bandwidth in MBytes/s 988 */ 989 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) 990 { 991 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 992 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); 993 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); 994 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); 995 996 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 997 } 998 999 /** 1000 * dce_v8_0_average_bandwidth - get the average available bandwidth 1001 * 1002 * @wm: watermark calculation data 1003 * 1004 * Calculate the average available bandwidth used for display (CIK). 1005 * Used for display watermark bandwidth calculations 1006 * Returns the average available bandwidth in MBytes/s 1007 */ 1008 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) 1009 { 1010 /* Calculate the display mode Average Bandwidth 1011 * DisplayMode should contain the source and destination dimensions, 1012 * timing, etc. 1013 */ 1014 fixed20_12 bpp; 1015 fixed20_12 line_time; 1016 fixed20_12 src_width; 1017 fixed20_12 bandwidth; 1018 fixed20_12 a; 1019 1020 a.full = dfixed_const(1000); 1021 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1022 line_time.full = dfixed_div(line_time, a); 1023 bpp.full = dfixed_const(wm->bytes_per_pixel); 1024 src_width.full = dfixed_const(wm->src_width); 1025 bandwidth.full = dfixed_mul(src_width, bpp); 1026 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1027 bandwidth.full = dfixed_div(bandwidth, line_time); 1028 1029 return dfixed_trunc(bandwidth); 1030 } 1031 1032 /** 1033 * dce_v8_0_latency_watermark - get the latency watermark 1034 * 1035 * @wm: watermark calculation data 1036 * 1037 * Calculate the latency watermark (CIK). 1038 * Used for display watermark bandwidth calculations 1039 * Returns the latency watermark in ns 1040 */ 1041 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) 1042 { 1043 /* First calculate the latency in ns */ 1044 u32 mc_latency = 2000; /* 2000 ns. */ 1045 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); 1046 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1047 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1048 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1049 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1050 (wm->num_heads * cursor_line_pair_return_time); 1051 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1052 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1053 u32 tmp, dmif_size = 12288; 1054 fixed20_12 a, b, c; 1055 1056 if (wm->num_heads == 0) 1057 return 0; 1058 1059 a.full = dfixed_const(2); 1060 b.full = dfixed_const(1); 1061 if ((wm->vsc.full > a.full) || 1062 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1063 (wm->vtaps >= 5) || 1064 ((wm->vsc.full >= a.full) && wm->interlaced)) 1065 max_src_lines_per_dst_line = 4; 1066 else 1067 max_src_lines_per_dst_line = 2; 1068 1069 a.full = dfixed_const(available_bandwidth); 1070 b.full = dfixed_const(wm->num_heads); 1071 a.full = dfixed_div(a, b); 1072 1073 b.full = dfixed_const(mc_latency + 512); 1074 c.full = dfixed_const(wm->disp_clk); 1075 b.full = dfixed_div(b, c); 1076 1077 c.full = dfixed_const(dmif_size); 1078 b.full = dfixed_div(c, b); 1079 1080 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1081 1082 b.full = dfixed_const(1000); 1083 c.full = dfixed_const(wm->disp_clk); 1084 b.full = dfixed_div(c, b); 1085 c.full = dfixed_const(wm->bytes_per_pixel); 1086 b.full = dfixed_mul(b, c); 1087 1088 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1089 1090 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1091 b.full = dfixed_const(1000); 1092 c.full = dfixed_const(lb_fill_bw); 1093 b.full = dfixed_div(c, b); 1094 a.full = dfixed_div(a, b); 1095 line_fill_time = dfixed_trunc(a); 1096 1097 if (line_fill_time < wm->active_time) 1098 return latency; 1099 else 1100 return latency + (line_fill_time - wm->active_time); 1101 1102 } 1103 1104 /** 1105 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1106 * average and available dram bandwidth 1107 * 1108 * @wm: watermark calculation data 1109 * 1110 * Check if the display average bandwidth fits in the display 1111 * dram bandwidth (CIK). 1112 * Used for display watermark bandwidth calculations 1113 * Returns true if the display fits, false if not. 1114 */ 1115 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) 1116 { 1117 if (dce_v8_0_average_bandwidth(wm) <= 1118 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1119 return true; 1120 else 1121 return false; 1122 } 1123 1124 /** 1125 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check 1126 * average and available bandwidth 1127 * 1128 * @wm: watermark calculation data 1129 * 1130 * Check if the display average bandwidth fits in the display 1131 * available bandwidth (CIK). 1132 * Used for display watermark bandwidth calculations 1133 * Returns true if the display fits, false if not. 1134 */ 1135 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) 1136 { 1137 if (dce_v8_0_average_bandwidth(wm) <= 1138 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) 1139 return true; 1140 else 1141 return false; 1142 } 1143 1144 /** 1145 * dce_v8_0_check_latency_hiding - check latency hiding 1146 * 1147 * @wm: watermark calculation data 1148 * 1149 * Check latency hiding (CIK). 1150 * Used for display watermark bandwidth calculations 1151 * Returns true if the display fits, false if not. 1152 */ 1153 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) 1154 { 1155 u32 lb_partitions = wm->lb_size / wm->src_width; 1156 u32 line_time = wm->active_time + wm->blank_time; 1157 u32 latency_tolerant_lines; 1158 u32 latency_hiding; 1159 fixed20_12 a; 1160 1161 a.full = dfixed_const(1); 1162 if (wm->vsc.full > a.full) 1163 latency_tolerant_lines = 1; 1164 else { 1165 if (lb_partitions <= (wm->vtaps + 1)) 1166 latency_tolerant_lines = 1; 1167 else 1168 latency_tolerant_lines = 2; 1169 } 1170 1171 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1172 1173 if (dce_v8_0_latency_watermark(wm) <= latency_hiding) 1174 return true; 1175 else 1176 return false; 1177 } 1178 1179 /** 1180 * dce_v8_0_program_watermarks - program display watermarks 1181 * 1182 * @adev: amdgpu_device pointer 1183 * @amdgpu_crtc: the selected display controller 1184 * @lb_size: line buffer size 1185 * @num_heads: number of display controllers in use 1186 * 1187 * Calculate and program the display watermarks for the 1188 * selected display controller (CIK). 1189 */ 1190 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, 1191 struct amdgpu_crtc *amdgpu_crtc, 1192 u32 lb_size, u32 num_heads) 1193 { 1194 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1195 struct dce8_wm_params wm_low, wm_high; 1196 u32 pixel_period; 1197 u32 line_time = 0; 1198 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1199 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1200 1201 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1202 pixel_period = 1000000 / (u32)mode->clock; 1203 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1204 1205 /* watermark for high clocks */ 1206 if (adev->pm.dpm_enabled) { 1207 wm_high.yclk = 1208 amdgpu_dpm_get_mclk(adev, false) * 10; 1209 wm_high.sclk = 1210 amdgpu_dpm_get_sclk(adev, false) * 10; 1211 } else { 1212 wm_high.yclk = adev->pm.current_mclk * 10; 1213 wm_high.sclk = adev->pm.current_sclk * 10; 1214 } 1215 1216 wm_high.disp_clk = mode->clock; 1217 wm_high.src_width = mode->crtc_hdisplay; 1218 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1219 wm_high.blank_time = line_time - wm_high.active_time; 1220 wm_high.interlaced = false; 1221 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1222 wm_high.interlaced = true; 1223 wm_high.vsc = amdgpu_crtc->vsc; 1224 wm_high.vtaps = 1; 1225 if (amdgpu_crtc->rmx_type != RMX_OFF) 1226 wm_high.vtaps = 2; 1227 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1228 wm_high.lb_size = lb_size; 1229 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1230 wm_high.num_heads = num_heads; 1231 1232 /* set for high clocks */ 1233 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535); 1234 1235 /* possibly force display priority to high */ 1236 /* should really do this at mode validation time... */ 1237 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1238 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1239 !dce_v8_0_check_latency_hiding(&wm_high) || 1240 (adev->mode_info.disp_priority == 2)) { 1241 DRM_DEBUG_KMS("force priority to high\n"); 1242 } 1243 1244 /* watermark for low clocks */ 1245 if (adev->pm.dpm_enabled) { 1246 wm_low.yclk = 1247 amdgpu_dpm_get_mclk(adev, true) * 10; 1248 wm_low.sclk = 1249 amdgpu_dpm_get_sclk(adev, true) * 10; 1250 } else { 1251 wm_low.yclk = adev->pm.current_mclk * 10; 1252 wm_low.sclk = adev->pm.current_sclk * 10; 1253 } 1254 1255 wm_low.disp_clk = mode->clock; 1256 wm_low.src_width = mode->crtc_hdisplay; 1257 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1258 wm_low.blank_time = line_time - wm_low.active_time; 1259 wm_low.interlaced = false; 1260 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1261 wm_low.interlaced = true; 1262 wm_low.vsc = amdgpu_crtc->vsc; 1263 wm_low.vtaps = 1; 1264 if (amdgpu_crtc->rmx_type != RMX_OFF) 1265 wm_low.vtaps = 2; 1266 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1267 wm_low.lb_size = lb_size; 1268 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1269 wm_low.num_heads = num_heads; 1270 1271 /* set for low clocks */ 1272 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535); 1273 1274 /* possibly force display priority to high */ 1275 /* should really do this at mode validation time... */ 1276 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1277 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1278 !dce_v8_0_check_latency_hiding(&wm_low) || 1279 (adev->mode_info.disp_priority == 2)) { 1280 DRM_DEBUG_KMS("force priority to high\n"); 1281 } 1282 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1283 } 1284 1285 /* select wm A */ 1286 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1287 tmp = wm_mask; 1288 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1289 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1290 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1291 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1292 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1293 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1294 /* select wm B */ 1295 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1296 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1297 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1298 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1299 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1300 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1301 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1302 /* restore original selection */ 1303 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1304 1305 /* save values for DPM */ 1306 amdgpu_crtc->line_time = line_time; 1307 amdgpu_crtc->wm_high = latency_watermark_a; 1308 amdgpu_crtc->wm_low = latency_watermark_b; 1309 /* Save number of lines the linebuffer leads before the scanout */ 1310 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1311 } 1312 1313 /** 1314 * dce_v8_0_bandwidth_update - program display watermarks 1315 * 1316 * @adev: amdgpu_device pointer 1317 * 1318 * Calculate and program the display watermarks and line 1319 * buffer allocation (CIK). 1320 */ 1321 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) 1322 { 1323 struct drm_display_mode *mode = NULL; 1324 u32 num_heads = 0, lb_size; 1325 int i; 1326 1327 amdgpu_update_display_priority(adev); 1328 1329 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1330 if (adev->mode_info.crtcs[i]->base.enabled) 1331 num_heads++; 1332 } 1333 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1334 mode = &adev->mode_info.crtcs[i]->base.mode; 1335 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1336 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1337 lb_size, num_heads); 1338 } 1339 } 1340 1341 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) 1342 { 1343 int i; 1344 u32 offset, tmp; 1345 1346 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1347 offset = adev->mode_info.audio.pin[i].offset; 1348 tmp = RREG32_AUDIO_ENDPT(offset, 1349 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1350 if (((tmp & 1351 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1352 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1353 adev->mode_info.audio.pin[i].connected = false; 1354 else 1355 adev->mode_info.audio.pin[i].connected = true; 1356 } 1357 } 1358 1359 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) 1360 { 1361 int i; 1362 1363 dce_v8_0_audio_get_connected_pins(adev); 1364 1365 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1366 if (adev->mode_info.audio.pin[i].connected) 1367 return &adev->mode_info.audio.pin[i]; 1368 } 1369 DRM_ERROR("No connected audio pins found!\n"); 1370 return NULL; 1371 } 1372 1373 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1374 { 1375 struct amdgpu_device *adev = encoder->dev->dev_private; 1376 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1377 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1378 u32 offset; 1379 1380 if (!dig || !dig->afmt || !dig->afmt->pin) 1381 return; 1382 1383 offset = dig->afmt->offset; 1384 1385 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, 1386 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT)); 1387 } 1388 1389 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, 1390 struct drm_display_mode *mode) 1391 { 1392 struct amdgpu_device *adev = encoder->dev->dev_private; 1393 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1394 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1395 struct drm_connector *connector; 1396 struct amdgpu_connector *amdgpu_connector = NULL; 1397 u32 tmp = 0, offset; 1398 1399 if (!dig || !dig->afmt || !dig->afmt->pin) 1400 return; 1401 1402 offset = dig->afmt->pin->offset; 1403 1404 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1405 if (connector->encoder == encoder) { 1406 amdgpu_connector = to_amdgpu_connector(connector); 1407 break; 1408 } 1409 } 1410 1411 if (!amdgpu_connector) { 1412 DRM_ERROR("Couldn't find encoder's connector\n"); 1413 return; 1414 } 1415 1416 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1417 if (connector->latency_present[1]) 1418 tmp = 1419 (connector->video_latency[1] << 1420 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1421 (connector->audio_latency[1] << 1422 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1423 else 1424 tmp = 1425 (0 << 1426 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1427 (0 << 1428 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1429 } else { 1430 if (connector->latency_present[0]) 1431 tmp = 1432 (connector->video_latency[0] << 1433 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1434 (connector->audio_latency[0] << 1435 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1436 else 1437 tmp = 1438 (0 << 1439 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1440 (0 << 1441 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1442 1443 } 1444 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1445 } 1446 1447 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1448 { 1449 struct amdgpu_device *adev = encoder->dev->dev_private; 1450 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1451 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1452 struct drm_connector *connector; 1453 struct amdgpu_connector *amdgpu_connector = NULL; 1454 u32 offset, tmp; 1455 u8 *sadb = NULL; 1456 int sad_count; 1457 1458 if (!dig || !dig->afmt || !dig->afmt->pin) 1459 return; 1460 1461 offset = dig->afmt->pin->offset; 1462 1463 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1464 if (connector->encoder == encoder) { 1465 amdgpu_connector = to_amdgpu_connector(connector); 1466 break; 1467 } 1468 } 1469 1470 if (!amdgpu_connector) { 1471 DRM_ERROR("Couldn't find encoder's connector\n"); 1472 return; 1473 } 1474 1475 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1476 if (sad_count < 0) { 1477 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1478 sad_count = 0; 1479 } 1480 1481 /* program the speaker allocation */ 1482 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1483 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK | 1484 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK); 1485 /* set HDMI mode */ 1486 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK; 1487 if (sad_count) 1488 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); 1489 else 1490 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */ 1491 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1492 1493 kfree(sadb); 1494 } 1495 1496 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) 1497 { 1498 struct amdgpu_device *adev = encoder->dev->dev_private; 1499 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1500 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1501 u32 offset; 1502 struct drm_connector *connector; 1503 struct amdgpu_connector *amdgpu_connector = NULL; 1504 struct cea_sad *sads; 1505 int i, sad_count; 1506 1507 static const u16 eld_reg_to_type[][2] = { 1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1520 }; 1521 1522 if (!dig || !dig->afmt || !dig->afmt->pin) 1523 return; 1524 1525 offset = dig->afmt->pin->offset; 1526 1527 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1528 if (connector->encoder == encoder) { 1529 amdgpu_connector = to_amdgpu_connector(connector); 1530 break; 1531 } 1532 } 1533 1534 if (!amdgpu_connector) { 1535 DRM_ERROR("Couldn't find encoder's connector\n"); 1536 return; 1537 } 1538 1539 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1540 if (sad_count <= 0) { 1541 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1542 return; 1543 } 1544 BUG_ON(!sads); 1545 1546 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1547 u32 value = 0; 1548 u8 stereo_freqs = 0; 1549 int max_channels = -1; 1550 int j; 1551 1552 for (j = 0; j < sad_count; j++) { 1553 struct cea_sad *sad = &sads[j]; 1554 1555 if (sad->format == eld_reg_to_type[i][1]) { 1556 if (sad->channels > max_channels) { 1557 value = (sad->channels << 1558 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1559 (sad->byte2 << 1560 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1561 (sad->freq << 1562 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1563 max_channels = sad->channels; 1564 } 1565 1566 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1567 stereo_freqs |= sad->freq; 1568 else 1569 break; 1570 } 1571 } 1572 1573 value |= (stereo_freqs << 1574 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1575 1576 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1577 } 1578 1579 kfree(sads); 1580 } 1581 1582 static void dce_v8_0_audio_enable(struct amdgpu_device *adev, 1583 struct amdgpu_audio_pin *pin, 1584 bool enable) 1585 { 1586 if (!pin) 1587 return; 1588 1589 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1590 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1591 } 1592 1593 static const u32 pin_offsets[7] = 1594 { 1595 (0x1780 - 0x1780), 1596 (0x1786 - 0x1780), 1597 (0x178c - 0x1780), 1598 (0x1792 - 0x1780), 1599 (0x1798 - 0x1780), 1600 (0x179d - 0x1780), 1601 (0x17a4 - 0x1780), 1602 }; 1603 1604 static int dce_v8_0_audio_init(struct amdgpu_device *adev) 1605 { 1606 int i; 1607 1608 if (!amdgpu_audio) 1609 return 0; 1610 1611 adev->mode_info.audio.enabled = true; 1612 1613 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ 1614 adev->mode_info.audio.num_pins = 7; 1615 else if ((adev->asic_type == CHIP_KABINI) || 1616 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ 1617 adev->mode_info.audio.num_pins = 3; 1618 else if ((adev->asic_type == CHIP_BONAIRE) || 1619 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ 1620 adev->mode_info.audio.num_pins = 7; 1621 else 1622 adev->mode_info.audio.num_pins = 3; 1623 1624 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1625 adev->mode_info.audio.pin[i].channels = -1; 1626 adev->mode_info.audio.pin[i].rate = -1; 1627 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1628 adev->mode_info.audio.pin[i].status_bits = 0; 1629 adev->mode_info.audio.pin[i].category_code = 0; 1630 adev->mode_info.audio.pin[i].connected = false; 1631 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1632 adev->mode_info.audio.pin[i].id = i; 1633 /* disable audio. it will be set up later */ 1634 /* XXX remove once we switch to ip funcs */ 1635 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1636 } 1637 1638 return 0; 1639 } 1640 1641 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) 1642 { 1643 int i; 1644 1645 if (!amdgpu_audio) 1646 return; 1647 1648 if (!adev->mode_info.audio.enabled) 1649 return; 1650 1651 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1652 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1653 1654 adev->mode_info.audio.enabled = false; 1655 } 1656 1657 /* 1658 * update the N and CTS parameters for a given pixel clock rate 1659 */ 1660 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1661 { 1662 struct drm_device *dev = encoder->dev; 1663 struct amdgpu_device *adev = dev->dev_private; 1664 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1665 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1666 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1667 uint32_t offset = dig->afmt->offset; 1668 1669 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1670 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); 1671 1672 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1673 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); 1674 1675 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); 1676 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); 1677 } 1678 1679 /* 1680 * build a HDMI Video Info Frame 1681 */ 1682 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1683 void *buffer, size_t size) 1684 { 1685 struct drm_device *dev = encoder->dev; 1686 struct amdgpu_device *adev = dev->dev_private; 1687 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1688 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1689 uint32_t offset = dig->afmt->offset; 1690 uint8_t *frame = buffer + 3; 1691 uint8_t *header = buffer; 1692 1693 WREG32(mmAFMT_AVI_INFO0 + offset, 1694 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1695 WREG32(mmAFMT_AVI_INFO1 + offset, 1696 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1697 WREG32(mmAFMT_AVI_INFO2 + offset, 1698 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1699 WREG32(mmAFMT_AVI_INFO3 + offset, 1700 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1701 } 1702 1703 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1704 { 1705 struct drm_device *dev = encoder->dev; 1706 struct amdgpu_device *adev = dev->dev_private; 1707 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1708 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1709 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1710 u32 dto_phase = 24 * 1000; 1711 u32 dto_modulo = clock; 1712 1713 if (!dig || !dig->afmt) 1714 return; 1715 1716 /* XXX two dtos; generally use dto0 for hdmi */ 1717 /* Express [24MHz / target pixel clock] as an exact rational 1718 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1719 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1720 */ 1721 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); 1722 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1723 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1724 } 1725 1726 /* 1727 * update the info frames with the data from the current display mode 1728 */ 1729 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, 1730 struct drm_display_mode *mode) 1731 { 1732 struct drm_device *dev = encoder->dev; 1733 struct amdgpu_device *adev = dev->dev_private; 1734 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1735 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1736 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1737 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1738 struct hdmi_avi_infoframe frame; 1739 uint32_t offset, val; 1740 ssize_t err; 1741 int bpc = 8; 1742 1743 if (!dig || !dig->afmt) 1744 return; 1745 1746 /* Silent, r600_hdmi_enable will raise WARN for us */ 1747 if (!dig->afmt->enabled) 1748 return; 1749 offset = dig->afmt->offset; 1750 1751 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1752 if (encoder->crtc) { 1753 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1754 bpc = amdgpu_crtc->bpc; 1755 } 1756 1757 /* disable audio prior to setting up hw */ 1758 dig->afmt->pin = dce_v8_0_audio_get_pin(adev); 1759 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1760 1761 dce_v8_0_audio_set_dto(encoder, mode->clock); 1762 1763 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1764 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */ 1765 1766 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 1767 1768 val = RREG32(mmHDMI_CONTROL + offset); 1769 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1770 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; 1771 1772 switch (bpc) { 1773 case 0: 1774 case 6: 1775 case 8: 1776 case 16: 1777 default: 1778 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1779 connector->name, bpc); 1780 break; 1781 case 10: 1782 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1783 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1784 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1785 connector->name); 1786 break; 1787 case 12: 1788 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1789 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1790 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1791 connector->name); 1792 break; 1793 } 1794 1795 WREG32(mmHDMI_CONTROL + offset, val); 1796 1797 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1798 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */ 1799 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */ 1800 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */ 1801 1802 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, 1803 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */ 1804 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */ 1805 1806 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, 1807 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */ 1808 1809 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, 1810 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */ 1811 1812 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 1813 1814 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, 1815 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */ 1816 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */ 1817 1818 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1819 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */ 1820 1821 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 1822 1823 if (bpc > 8) 1824 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1825 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1826 else 1827 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1828 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */ 1829 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1830 1831 dce_v8_0_afmt_update_ACR(encoder, mode->clock); 1832 1833 WREG32(mmAFMT_60958_0 + offset, 1834 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT)); 1835 1836 WREG32(mmAFMT_60958_1 + offset, 1837 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT)); 1838 1839 WREG32(mmAFMT_60958_2 + offset, 1840 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) | 1841 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) | 1842 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) | 1843 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) | 1844 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) | 1845 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT)); 1846 1847 dce_v8_0_audio_write_speaker_allocation(encoder); 1848 1849 1850 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, 1851 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1852 1853 dce_v8_0_afmt_audio_select_pin(encoder); 1854 dce_v8_0_audio_write_sad_regs(encoder); 1855 dce_v8_0_audio_write_latency_fields(encoder, mode); 1856 1857 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1858 if (err < 0) { 1859 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1860 return; 1861 } 1862 1863 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1864 if (err < 0) { 1865 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1866 return; 1867 } 1868 1869 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1870 1871 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, 1872 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ 1873 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */ 1874 1875 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, 1876 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ 1877 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK); 1878 1879 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1880 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ 1881 1882 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 1883 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 1884 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 1885 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); 1886 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); 1887 1888 /* enable audio after to setting up hw */ 1889 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); 1890 } 1891 1892 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1893 { 1894 struct drm_device *dev = encoder->dev; 1895 struct amdgpu_device *adev = dev->dev_private; 1896 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1897 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1898 1899 if (!dig || !dig->afmt) 1900 return; 1901 1902 /* Silent, r600_hdmi_enable will raise WARN for us */ 1903 if (enable && dig->afmt->enabled) 1904 return; 1905 if (!enable && !dig->afmt->enabled) 1906 return; 1907 1908 if (!enable && dig->afmt->pin) { 1909 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1910 dig->afmt->pin = NULL; 1911 } 1912 1913 dig->afmt->enabled = enable; 1914 1915 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1916 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1917 } 1918 1919 static int dce_v8_0_afmt_init(struct amdgpu_device *adev) 1920 { 1921 int i; 1922 1923 for (i = 0; i < adev->mode_info.num_dig; i++) 1924 adev->mode_info.afmt[i] = NULL; 1925 1926 /* DCE8 has audio blocks tied to DIG encoders */ 1927 for (i = 0; i < adev->mode_info.num_dig; i++) { 1928 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1929 if (adev->mode_info.afmt[i]) { 1930 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1931 adev->mode_info.afmt[i]->id = i; 1932 } else { 1933 int j; 1934 for (j = 0; j < i; j++) { 1935 kfree(adev->mode_info.afmt[j]); 1936 adev->mode_info.afmt[j] = NULL; 1937 } 1938 return -ENOMEM; 1939 } 1940 } 1941 return 0; 1942 } 1943 1944 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) 1945 { 1946 int i; 1947 1948 for (i = 0; i < adev->mode_info.num_dig; i++) { 1949 kfree(adev->mode_info.afmt[i]); 1950 adev->mode_info.afmt[i] = NULL; 1951 } 1952 } 1953 1954 static const u32 vga_control_regs[6] = 1955 { 1956 mmD1VGA_CONTROL, 1957 mmD2VGA_CONTROL, 1958 mmD3VGA_CONTROL, 1959 mmD4VGA_CONTROL, 1960 mmD5VGA_CONTROL, 1961 mmD6VGA_CONTROL, 1962 }; 1963 1964 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) 1965 { 1966 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1967 struct drm_device *dev = crtc->dev; 1968 struct amdgpu_device *adev = dev->dev_private; 1969 u32 vga_control; 1970 1971 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1972 if (enable) 1973 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1974 else 1975 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1976 } 1977 1978 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) 1979 { 1980 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1981 struct drm_device *dev = crtc->dev; 1982 struct amdgpu_device *adev = dev->dev_private; 1983 1984 if (enable) 1985 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1986 else 1987 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1988 } 1989 1990 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 1991 struct drm_framebuffer *fb, 1992 int x, int y, int atomic) 1993 { 1994 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1995 struct drm_device *dev = crtc->dev; 1996 struct amdgpu_device *adev = dev->dev_private; 1997 struct amdgpu_framebuffer *amdgpu_fb; 1998 struct drm_framebuffer *target_fb; 1999 struct drm_gem_object *obj; 2000 struct amdgpu_bo *rbo; 2001 uint64_t fb_location, tiling_flags; 2002 uint32_t fb_format, fb_pitch_pixels; 2003 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2004 u32 pipe_config; 2005 u32 viewport_w, viewport_h; 2006 int r; 2007 bool bypass_lut = false; 2008 2009 /* no fb bound */ 2010 if (!atomic && !crtc->primary->fb) { 2011 DRM_DEBUG_KMS("No FB bound\n"); 2012 return 0; 2013 } 2014 2015 if (atomic) { 2016 amdgpu_fb = to_amdgpu_framebuffer(fb); 2017 target_fb = fb; 2018 } else { 2019 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2020 target_fb = crtc->primary->fb; 2021 } 2022 2023 /* If atomic, assume fb object is pinned & idle & fenced and 2024 * just update base pointers 2025 */ 2026 obj = amdgpu_fb->obj; 2027 rbo = gem_to_amdgpu_bo(obj); 2028 r = amdgpu_bo_reserve(rbo, false); 2029 if (unlikely(r != 0)) 2030 return r; 2031 2032 if (atomic) { 2033 fb_location = amdgpu_bo_gpu_offset(rbo); 2034 } else { 2035 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2036 if (unlikely(r != 0)) { 2037 amdgpu_bo_unreserve(rbo); 2038 return -EINVAL; 2039 } 2040 } 2041 2042 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2043 amdgpu_bo_unreserve(rbo); 2044 2045 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2046 2047 switch (target_fb->pixel_format) { 2048 case DRM_FORMAT_C8: 2049 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2050 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2051 break; 2052 case DRM_FORMAT_XRGB4444: 2053 case DRM_FORMAT_ARGB4444: 2054 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2055 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2056 #ifdef __BIG_ENDIAN 2057 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2058 #endif 2059 break; 2060 case DRM_FORMAT_XRGB1555: 2061 case DRM_FORMAT_ARGB1555: 2062 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2063 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2064 #ifdef __BIG_ENDIAN 2065 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2066 #endif 2067 break; 2068 case DRM_FORMAT_BGRX5551: 2069 case DRM_FORMAT_BGRA5551: 2070 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2071 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2072 #ifdef __BIG_ENDIAN 2073 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2074 #endif 2075 break; 2076 case DRM_FORMAT_RGB565: 2077 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2078 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2079 #ifdef __BIG_ENDIAN 2080 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2081 #endif 2082 break; 2083 case DRM_FORMAT_XRGB8888: 2084 case DRM_FORMAT_ARGB8888: 2085 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2086 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2087 #ifdef __BIG_ENDIAN 2088 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2089 #endif 2090 break; 2091 case DRM_FORMAT_XRGB2101010: 2092 case DRM_FORMAT_ARGB2101010: 2093 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2094 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2095 #ifdef __BIG_ENDIAN 2096 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2097 #endif 2098 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2099 bypass_lut = true; 2100 break; 2101 case DRM_FORMAT_BGRX1010102: 2102 case DRM_FORMAT_BGRA1010102: 2103 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2104 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2105 #ifdef __BIG_ENDIAN 2106 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2107 #endif 2108 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2109 bypass_lut = true; 2110 break; 2111 default: 2112 DRM_ERROR("Unsupported screen format %s\n", 2113 drm_get_format_name(target_fb->pixel_format)); 2114 return -EINVAL; 2115 } 2116 2117 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2118 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2119 2120 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2121 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2122 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2123 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2124 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2125 2126 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 2127 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2128 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 2129 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 2130 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 2131 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 2132 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); 2133 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2134 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2135 } 2136 2137 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 2138 2139 dce_v8_0_vga_enable(crtc, false); 2140 2141 /* Make sure surface address is updated at vertical blank rather than 2142 * horizontal blank 2143 */ 2144 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2145 2146 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2147 upper_32_bits(fb_location)); 2148 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2149 upper_32_bits(fb_location)); 2150 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2151 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2152 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2153 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2154 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2155 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2156 2157 /* 2158 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2159 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2160 * retain the full precision throughout the pipeline. 2161 */ 2162 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 2163 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0), 2164 ~LUT_10BIT_BYPASS_EN); 2165 2166 if (bypass_lut) 2167 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2168 2169 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2170 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2171 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2172 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2173 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2174 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2175 2176 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2177 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2178 2179 dce_v8_0_grph_enable(crtc, true); 2180 2181 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2182 target_fb->height); 2183 2184 x &= ~3; 2185 y &= ~1; 2186 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2187 (x << 16) | y); 2188 viewport_w = crtc->mode.hdisplay; 2189 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2190 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2191 (viewport_w << 16) | viewport_h); 2192 2193 /* set pageflip to happen only at start of vblank interval (front porch) */ 2194 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2195 2196 if (!atomic && fb && fb != crtc->primary->fb) { 2197 amdgpu_fb = to_amdgpu_framebuffer(fb); 2198 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2199 r = amdgpu_bo_reserve(rbo, false); 2200 if (unlikely(r != 0)) 2201 return r; 2202 amdgpu_bo_unpin(rbo); 2203 amdgpu_bo_unreserve(rbo); 2204 } 2205 2206 /* Bytes per pixel may have changed */ 2207 dce_v8_0_bandwidth_update(adev); 2208 2209 return 0; 2210 } 2211 2212 static void dce_v8_0_set_interleave(struct drm_crtc *crtc, 2213 struct drm_display_mode *mode) 2214 { 2215 struct drm_device *dev = crtc->dev; 2216 struct amdgpu_device *adev = dev->dev_private; 2217 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2218 2219 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2220 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 2221 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT); 2222 else 2223 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2224 } 2225 2226 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) 2227 { 2228 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2229 struct drm_device *dev = crtc->dev; 2230 struct amdgpu_device *adev = dev->dev_private; 2231 int i; 2232 2233 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2234 2235 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2236 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2237 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2238 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2239 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2240 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2241 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2242 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2243 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2244 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2245 2246 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2247 2248 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2249 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2250 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2251 2252 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2253 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2254 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2255 2256 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2257 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2258 2259 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2260 for (i = 0; i < 256; i++) { 2261 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2262 (amdgpu_crtc->lut_r[i] << 20) | 2263 (amdgpu_crtc->lut_g[i] << 10) | 2264 (amdgpu_crtc->lut_b[i] << 0)); 2265 } 2266 2267 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2268 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2269 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2270 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2271 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2272 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2273 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2274 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2275 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2276 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2277 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2278 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2279 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2280 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2281 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2282 /* XXX this only needs to be programmed once per crtc at startup, 2283 * not sure where the best place for it is 2284 */ 2285 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, 2286 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK); 2287 } 2288 2289 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) 2290 { 2291 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2292 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2293 2294 switch (amdgpu_encoder->encoder_id) { 2295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2296 if (dig->linkb) 2297 return 1; 2298 else 2299 return 0; 2300 break; 2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2302 if (dig->linkb) 2303 return 3; 2304 else 2305 return 2; 2306 break; 2307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2308 if (dig->linkb) 2309 return 5; 2310 else 2311 return 4; 2312 break; 2313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2314 return 6; 2315 break; 2316 default: 2317 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2318 return 0; 2319 } 2320 } 2321 2322 /** 2323 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc. 2324 * 2325 * @crtc: drm crtc 2326 * 2327 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2328 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2329 * monitors a dedicated PPLL must be used. If a particular board has 2330 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2331 * as there is no need to program the PLL itself. If we are not able to 2332 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2333 * avoid messing up an existing monitor. 2334 * 2335 * Asic specific PLL information 2336 * 2337 * DCE 8.x 2338 * KB/KV 2339 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2340 * CI 2341 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2342 * 2343 */ 2344 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc) 2345 { 2346 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2347 struct drm_device *dev = crtc->dev; 2348 struct amdgpu_device *adev = dev->dev_private; 2349 u32 pll_in_use; 2350 int pll; 2351 2352 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2353 if (adev->clock.dp_extclk) 2354 /* skip PPLL programming if using ext clock */ 2355 return ATOM_PPLL_INVALID; 2356 else { 2357 /* use the same PPLL for all DP monitors */ 2358 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2359 if (pll != ATOM_PPLL_INVALID) 2360 return pll; 2361 } 2362 } else { 2363 /* use the same PPLL for all monitors with the same clock */ 2364 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2365 if (pll != ATOM_PPLL_INVALID) 2366 return pll; 2367 } 2368 /* otherwise, pick one of the plls */ 2369 if ((adev->asic_type == CHIP_KABINI) || 2370 (adev->asic_type == CHIP_MULLINS)) { 2371 /* KB/ML has PPLL1 and PPLL2 */ 2372 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2373 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2374 return ATOM_PPLL2; 2375 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2376 return ATOM_PPLL1; 2377 DRM_ERROR("unable to allocate a PPLL\n"); 2378 return ATOM_PPLL_INVALID; 2379 } else { 2380 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 2381 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2382 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2383 return ATOM_PPLL2; 2384 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2385 return ATOM_PPLL1; 2386 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2387 return ATOM_PPLL0; 2388 DRM_ERROR("unable to allocate a PPLL\n"); 2389 return ATOM_PPLL_INVALID; 2390 } 2391 return ATOM_PPLL_INVALID; 2392 } 2393 2394 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2395 { 2396 struct amdgpu_device *adev = crtc->dev->dev_private; 2397 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2398 uint32_t cur_lock; 2399 2400 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2401 if (lock) 2402 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2403 else 2404 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2405 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2406 } 2407 2408 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) 2409 { 2410 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2411 struct amdgpu_device *adev = crtc->dev->dev_private; 2412 2413 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2414 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2415 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2416 } 2417 2418 static void dce_v8_0_show_cursor(struct drm_crtc *crtc) 2419 { 2420 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2421 struct amdgpu_device *adev = crtc->dev->dev_private; 2422 2423 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2424 upper_32_bits(amdgpu_crtc->cursor_addr)); 2425 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2426 lower_32_bits(amdgpu_crtc->cursor_addr)); 2427 2428 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2429 CUR_CONTROL__CURSOR_EN_MASK | 2430 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2431 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2432 } 2433 2434 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 2435 int x, int y) 2436 { 2437 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2438 struct amdgpu_device *adev = crtc->dev->dev_private; 2439 int xorigin = 0, yorigin = 0; 2440 2441 /* avivo cursor are offset into the total surface */ 2442 x += crtc->x; 2443 y += crtc->y; 2444 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2445 2446 if (x < 0) { 2447 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2448 x = 0; 2449 } 2450 if (y < 0) { 2451 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2452 y = 0; 2453 } 2454 2455 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2456 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2457 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2458 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2459 2460 amdgpu_crtc->cursor_x = x; 2461 amdgpu_crtc->cursor_y = y; 2462 2463 return 0; 2464 } 2465 2466 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, 2467 int x, int y) 2468 { 2469 int ret; 2470 2471 dce_v8_0_lock_cursor(crtc, true); 2472 ret = dce_v8_0_cursor_move_locked(crtc, x, y); 2473 dce_v8_0_lock_cursor(crtc, false); 2474 2475 return ret; 2476 } 2477 2478 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 2479 struct drm_file *file_priv, 2480 uint32_t handle, 2481 uint32_t width, 2482 uint32_t height, 2483 int32_t hot_x, 2484 int32_t hot_y) 2485 { 2486 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2487 struct drm_gem_object *obj; 2488 struct amdgpu_bo *aobj; 2489 int ret; 2490 2491 if (!handle) { 2492 /* turn off cursor */ 2493 dce_v8_0_hide_cursor(crtc); 2494 obj = NULL; 2495 goto unpin; 2496 } 2497 2498 if ((width > amdgpu_crtc->max_cursor_width) || 2499 (height > amdgpu_crtc->max_cursor_height)) { 2500 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2501 return -EINVAL; 2502 } 2503 2504 obj = drm_gem_object_lookup(file_priv, handle); 2505 if (!obj) { 2506 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2507 return -ENOENT; 2508 } 2509 2510 aobj = gem_to_amdgpu_bo(obj); 2511 ret = amdgpu_bo_reserve(aobj, false); 2512 if (ret != 0) { 2513 drm_gem_object_unreference_unlocked(obj); 2514 return ret; 2515 } 2516 2517 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2518 amdgpu_bo_unreserve(aobj); 2519 if (ret) { 2520 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2521 drm_gem_object_unreference_unlocked(obj); 2522 return ret; 2523 } 2524 2525 amdgpu_crtc->cursor_width = width; 2526 amdgpu_crtc->cursor_height = height; 2527 2528 dce_v8_0_lock_cursor(crtc, true); 2529 2530 if (hot_x != amdgpu_crtc->cursor_hot_x || 2531 hot_y != amdgpu_crtc->cursor_hot_y) { 2532 int x, y; 2533 2534 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2535 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2536 2537 dce_v8_0_cursor_move_locked(crtc, x, y); 2538 2539 amdgpu_crtc->cursor_hot_x = hot_x; 2540 amdgpu_crtc->cursor_hot_y = hot_y; 2541 } 2542 2543 dce_v8_0_show_cursor(crtc); 2544 dce_v8_0_lock_cursor(crtc, false); 2545 2546 unpin: 2547 if (amdgpu_crtc->cursor_bo) { 2548 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2549 ret = amdgpu_bo_reserve(aobj, false); 2550 if (likely(ret == 0)) { 2551 amdgpu_bo_unpin(aobj); 2552 amdgpu_bo_unreserve(aobj); 2553 } 2554 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2555 } 2556 2557 amdgpu_crtc->cursor_bo = obj; 2558 return 0; 2559 } 2560 2561 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 2562 { 2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2564 2565 if (amdgpu_crtc->cursor_bo) { 2566 dce_v8_0_lock_cursor(crtc, true); 2567 2568 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2569 amdgpu_crtc->cursor_y); 2570 2571 dce_v8_0_show_cursor(crtc); 2572 2573 dce_v8_0_lock_cursor(crtc, false); 2574 } 2575 } 2576 2577 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2578 u16 *blue, uint32_t start, uint32_t size) 2579 { 2580 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2581 int end = (start + size > 256) ? 256 : start + size, i; 2582 2583 /* userspace palettes are always correct as is */ 2584 for (i = start; i < end; i++) { 2585 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2586 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2587 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2588 } 2589 dce_v8_0_crtc_load_lut(crtc); 2590 } 2591 2592 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) 2593 { 2594 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2595 2596 drm_crtc_cleanup(crtc); 2597 kfree(amdgpu_crtc); 2598 } 2599 2600 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { 2601 .cursor_set2 = dce_v8_0_crtc_cursor_set2, 2602 .cursor_move = dce_v8_0_crtc_cursor_move, 2603 .gamma_set = dce_v8_0_crtc_gamma_set, 2604 .set_config = amdgpu_crtc_set_config, 2605 .destroy = dce_v8_0_crtc_destroy, 2606 .page_flip = amdgpu_crtc_page_flip, 2607 }; 2608 2609 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2610 { 2611 struct drm_device *dev = crtc->dev; 2612 struct amdgpu_device *adev = dev->dev_private; 2613 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2614 unsigned type; 2615 2616 switch (mode) { 2617 case DRM_MODE_DPMS_ON: 2618 amdgpu_crtc->enabled = true; 2619 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2620 dce_v8_0_vga_enable(crtc, true); 2621 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2622 dce_v8_0_vga_enable(crtc, false); 2623 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2624 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2625 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2626 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2627 drm_vblank_on(dev, amdgpu_crtc->crtc_id); 2628 dce_v8_0_crtc_load_lut(crtc); 2629 break; 2630 case DRM_MODE_DPMS_STANDBY: 2631 case DRM_MODE_DPMS_SUSPEND: 2632 case DRM_MODE_DPMS_OFF: 2633 drm_vblank_off(dev, amdgpu_crtc->crtc_id); 2634 if (amdgpu_crtc->enabled) { 2635 dce_v8_0_vga_enable(crtc, true); 2636 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2637 dce_v8_0_vga_enable(crtc, false); 2638 } 2639 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2640 amdgpu_crtc->enabled = false; 2641 break; 2642 } 2643 /* adjust pm to dpms */ 2644 amdgpu_pm_compute_clocks(adev); 2645 } 2646 2647 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc) 2648 { 2649 /* disable crtc pair power gating before programming */ 2650 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2651 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2652 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2653 } 2654 2655 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc) 2656 { 2657 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2658 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2659 } 2660 2661 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) 2662 { 2663 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2664 struct drm_device *dev = crtc->dev; 2665 struct amdgpu_device *adev = dev->dev_private; 2666 struct amdgpu_atom_ss ss; 2667 int i; 2668 2669 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2670 if (crtc->primary->fb) { 2671 int r; 2672 struct amdgpu_framebuffer *amdgpu_fb; 2673 struct amdgpu_bo *rbo; 2674 2675 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2676 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2677 r = amdgpu_bo_reserve(rbo, false); 2678 if (unlikely(r)) 2679 DRM_ERROR("failed to reserve rbo before unpin\n"); 2680 else { 2681 amdgpu_bo_unpin(rbo); 2682 amdgpu_bo_unreserve(rbo); 2683 } 2684 } 2685 /* disable the GRPH */ 2686 dce_v8_0_grph_enable(crtc, false); 2687 2688 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2689 2690 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2691 if (adev->mode_info.crtcs[i] && 2692 adev->mode_info.crtcs[i]->enabled && 2693 i != amdgpu_crtc->crtc_id && 2694 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2695 /* one other crtc is using this pll don't turn 2696 * off the pll 2697 */ 2698 goto done; 2699 } 2700 } 2701 2702 switch (amdgpu_crtc->pll_id) { 2703 case ATOM_PPLL1: 2704 case ATOM_PPLL2: 2705 /* disable the ppll */ 2706 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2707 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2708 break; 2709 case ATOM_PPLL0: 2710 /* disable the ppll */ 2711 if ((adev->asic_type == CHIP_KAVERI) || 2712 (adev->asic_type == CHIP_BONAIRE) || 2713 (adev->asic_type == CHIP_HAWAII)) 2714 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2715 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2716 break; 2717 default: 2718 break; 2719 } 2720 done: 2721 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2722 amdgpu_crtc->adjusted_clock = 0; 2723 amdgpu_crtc->encoder = NULL; 2724 amdgpu_crtc->connector = NULL; 2725 } 2726 2727 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, 2728 struct drm_display_mode *mode, 2729 struct drm_display_mode *adjusted_mode, 2730 int x, int y, struct drm_framebuffer *old_fb) 2731 { 2732 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2733 2734 if (!amdgpu_crtc->adjusted_clock) 2735 return -EINVAL; 2736 2737 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2738 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2739 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2740 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2741 amdgpu_atombios_crtc_scaler_setup(crtc); 2742 dce_v8_0_cursor_reset(crtc); 2743 /* update the hw version fpr dpm */ 2744 amdgpu_crtc->hw_mode = *adjusted_mode; 2745 2746 return 0; 2747 } 2748 2749 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, 2750 const struct drm_display_mode *mode, 2751 struct drm_display_mode *adjusted_mode) 2752 { 2753 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2754 struct drm_device *dev = crtc->dev; 2755 struct drm_encoder *encoder; 2756 2757 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2758 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2759 if (encoder->crtc == crtc) { 2760 amdgpu_crtc->encoder = encoder; 2761 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2762 break; 2763 } 2764 } 2765 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2766 amdgpu_crtc->encoder = NULL; 2767 amdgpu_crtc->connector = NULL; 2768 return false; 2769 } 2770 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2771 return false; 2772 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2773 return false; 2774 /* pick pll */ 2775 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc); 2776 /* if we can't get a PPLL for a non-DP encoder, fail */ 2777 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2778 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2779 return false; 2780 2781 return true; 2782 } 2783 2784 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2785 struct drm_framebuffer *old_fb) 2786 { 2787 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2788 } 2789 2790 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2791 struct drm_framebuffer *fb, 2792 int x, int y, enum mode_set_atomic state) 2793 { 2794 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); 2795 } 2796 2797 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { 2798 .dpms = dce_v8_0_crtc_dpms, 2799 .mode_fixup = dce_v8_0_crtc_mode_fixup, 2800 .mode_set = dce_v8_0_crtc_mode_set, 2801 .mode_set_base = dce_v8_0_crtc_set_base, 2802 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, 2803 .prepare = dce_v8_0_crtc_prepare, 2804 .commit = dce_v8_0_crtc_commit, 2805 .load_lut = dce_v8_0_crtc_load_lut, 2806 .disable = dce_v8_0_crtc_disable, 2807 }; 2808 2809 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) 2810 { 2811 struct amdgpu_crtc *amdgpu_crtc; 2812 int i; 2813 2814 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2815 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2816 if (amdgpu_crtc == NULL) 2817 return -ENOMEM; 2818 2819 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); 2820 2821 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2822 amdgpu_crtc->crtc_id = index; 2823 adev->mode_info.crtcs[index] = amdgpu_crtc; 2824 2825 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 2826 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 2827 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2828 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2829 2830 for (i = 0; i < 256; i++) { 2831 amdgpu_crtc->lut_r[i] = i << 2; 2832 amdgpu_crtc->lut_g[i] = i << 2; 2833 amdgpu_crtc->lut_b[i] = i << 2; 2834 } 2835 2836 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2837 2838 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2839 amdgpu_crtc->adjusted_clock = 0; 2840 amdgpu_crtc->encoder = NULL; 2841 amdgpu_crtc->connector = NULL; 2842 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); 2843 2844 return 0; 2845 } 2846 2847 static int dce_v8_0_early_init(void *handle) 2848 { 2849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2850 2851 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2852 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2853 2854 dce_v8_0_set_display_funcs(adev); 2855 dce_v8_0_set_irq_funcs(adev); 2856 2857 switch (adev->asic_type) { 2858 case CHIP_BONAIRE: 2859 case CHIP_HAWAII: 2860 adev->mode_info.num_crtc = 6; 2861 adev->mode_info.num_hpd = 6; 2862 adev->mode_info.num_dig = 6; 2863 break; 2864 case CHIP_KAVERI: 2865 adev->mode_info.num_crtc = 4; 2866 adev->mode_info.num_hpd = 6; 2867 adev->mode_info.num_dig = 7; 2868 break; 2869 case CHIP_KABINI: 2870 case CHIP_MULLINS: 2871 adev->mode_info.num_crtc = 2; 2872 adev->mode_info.num_hpd = 6; 2873 adev->mode_info.num_dig = 6; /* ? */ 2874 break; 2875 default: 2876 /* FIXME: not supported yet */ 2877 return -EINVAL; 2878 } 2879 2880 return 0; 2881 } 2882 2883 static int dce_v8_0_sw_init(void *handle) 2884 { 2885 int r, i; 2886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2887 2888 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2889 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2890 if (r) 2891 return r; 2892 } 2893 2894 for (i = 8; i < 20; i += 2) { 2895 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2896 if (r) 2897 return r; 2898 } 2899 2900 /* HPD hotplug */ 2901 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2902 if (r) 2903 return r; 2904 2905 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2906 2907 adev->ddev->mode_config.async_page_flip = true; 2908 2909 adev->ddev->mode_config.max_width = 16384; 2910 adev->ddev->mode_config.max_height = 16384; 2911 2912 adev->ddev->mode_config.preferred_depth = 24; 2913 adev->ddev->mode_config.prefer_shadow = 1; 2914 2915 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2916 2917 r = amdgpu_modeset_create_props(adev); 2918 if (r) 2919 return r; 2920 2921 adev->ddev->mode_config.max_width = 16384; 2922 adev->ddev->mode_config.max_height = 16384; 2923 2924 /* allocate crtcs */ 2925 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2926 r = dce_v8_0_crtc_init(adev, i); 2927 if (r) 2928 return r; 2929 } 2930 2931 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2932 amdgpu_print_display_setup(adev->ddev); 2933 else 2934 return -EINVAL; 2935 2936 /* setup afmt */ 2937 r = dce_v8_0_afmt_init(adev); 2938 if (r) 2939 return r; 2940 2941 r = dce_v8_0_audio_init(adev); 2942 if (r) 2943 return r; 2944 2945 drm_kms_helper_poll_init(adev->ddev); 2946 2947 adev->mode_info.mode_config_initialized = true; 2948 return 0; 2949 } 2950 2951 static int dce_v8_0_sw_fini(void *handle) 2952 { 2953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2954 2955 kfree(adev->mode_info.bios_hardcoded_edid); 2956 2957 drm_kms_helper_poll_fini(adev->ddev); 2958 2959 dce_v8_0_audio_fini(adev); 2960 2961 dce_v8_0_afmt_fini(adev); 2962 2963 drm_mode_config_cleanup(adev->ddev); 2964 adev->mode_info.mode_config_initialized = false; 2965 2966 return 0; 2967 } 2968 2969 static int dce_v8_0_hw_init(void *handle) 2970 { 2971 int i; 2972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2973 2974 /* init dig PHYs, disp eng pll */ 2975 amdgpu_atombios_encoder_init_dig(adev); 2976 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2977 2978 /* initialize hpd */ 2979 dce_v8_0_hpd_init(adev); 2980 2981 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2982 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2983 } 2984 2985 dce_v8_0_pageflip_interrupt_init(adev); 2986 2987 return 0; 2988 } 2989 2990 static int dce_v8_0_hw_fini(void *handle) 2991 { 2992 int i; 2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2994 2995 dce_v8_0_hpd_fini(adev); 2996 2997 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2998 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2999 } 3000 3001 dce_v8_0_pageflip_interrupt_fini(adev); 3002 3003 return 0; 3004 } 3005 3006 static int dce_v8_0_suspend(void *handle) 3007 { 3008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3009 3010 amdgpu_atombios_scratch_regs_save(adev); 3011 3012 return dce_v8_0_hw_fini(handle); 3013 } 3014 3015 static int dce_v8_0_resume(void *handle) 3016 { 3017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3018 int ret; 3019 3020 ret = dce_v8_0_hw_init(handle); 3021 3022 amdgpu_atombios_scratch_regs_restore(adev); 3023 3024 /* turn on the BL */ 3025 if (adev->mode_info.bl_encoder) { 3026 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3027 adev->mode_info.bl_encoder); 3028 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3029 bl_level); 3030 } 3031 3032 return ret; 3033 } 3034 3035 static bool dce_v8_0_is_idle(void *handle) 3036 { 3037 return true; 3038 } 3039 3040 static int dce_v8_0_wait_for_idle(void *handle) 3041 { 3042 return 0; 3043 } 3044 3045 static int dce_v8_0_soft_reset(void *handle) 3046 { 3047 u32 srbm_soft_reset = 0, tmp; 3048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3049 3050 if (dce_v8_0_is_display_hung(adev)) 3051 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3052 3053 if (srbm_soft_reset) { 3054 tmp = RREG32(mmSRBM_SOFT_RESET); 3055 tmp |= srbm_soft_reset; 3056 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3057 WREG32(mmSRBM_SOFT_RESET, tmp); 3058 tmp = RREG32(mmSRBM_SOFT_RESET); 3059 3060 udelay(50); 3061 3062 tmp &= ~srbm_soft_reset; 3063 WREG32(mmSRBM_SOFT_RESET, tmp); 3064 tmp = RREG32(mmSRBM_SOFT_RESET); 3065 3066 /* Wait a little for things to settle down */ 3067 udelay(50); 3068 } 3069 return 0; 3070 } 3071 3072 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3073 int crtc, 3074 enum amdgpu_interrupt_state state) 3075 { 3076 u32 reg_block, lb_interrupt_mask; 3077 3078 if (crtc >= adev->mode_info.num_crtc) { 3079 DRM_DEBUG("invalid crtc %d\n", crtc); 3080 return; 3081 } 3082 3083 switch (crtc) { 3084 case 0: 3085 reg_block = CRTC0_REGISTER_OFFSET; 3086 break; 3087 case 1: 3088 reg_block = CRTC1_REGISTER_OFFSET; 3089 break; 3090 case 2: 3091 reg_block = CRTC2_REGISTER_OFFSET; 3092 break; 3093 case 3: 3094 reg_block = CRTC3_REGISTER_OFFSET; 3095 break; 3096 case 4: 3097 reg_block = CRTC4_REGISTER_OFFSET; 3098 break; 3099 case 5: 3100 reg_block = CRTC5_REGISTER_OFFSET; 3101 break; 3102 default: 3103 DRM_DEBUG("invalid crtc %d\n", crtc); 3104 return; 3105 } 3106 3107 switch (state) { 3108 case AMDGPU_IRQ_STATE_DISABLE: 3109 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3110 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3111 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3112 break; 3113 case AMDGPU_IRQ_STATE_ENABLE: 3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3115 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3116 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3117 break; 3118 default: 3119 break; 3120 } 3121 } 3122 3123 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3124 int crtc, 3125 enum amdgpu_interrupt_state state) 3126 { 3127 u32 reg_block, lb_interrupt_mask; 3128 3129 if (crtc >= adev->mode_info.num_crtc) { 3130 DRM_DEBUG("invalid crtc %d\n", crtc); 3131 return; 3132 } 3133 3134 switch (crtc) { 3135 case 0: 3136 reg_block = CRTC0_REGISTER_OFFSET; 3137 break; 3138 case 1: 3139 reg_block = CRTC1_REGISTER_OFFSET; 3140 break; 3141 case 2: 3142 reg_block = CRTC2_REGISTER_OFFSET; 3143 break; 3144 case 3: 3145 reg_block = CRTC3_REGISTER_OFFSET; 3146 break; 3147 case 4: 3148 reg_block = CRTC4_REGISTER_OFFSET; 3149 break; 3150 case 5: 3151 reg_block = CRTC5_REGISTER_OFFSET; 3152 break; 3153 default: 3154 DRM_DEBUG("invalid crtc %d\n", crtc); 3155 return; 3156 } 3157 3158 switch (state) { 3159 case AMDGPU_IRQ_STATE_DISABLE: 3160 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3161 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3162 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3163 break; 3164 case AMDGPU_IRQ_STATE_ENABLE: 3165 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3166 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3167 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3168 break; 3169 default: 3170 break; 3171 } 3172 } 3173 3174 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3175 struct amdgpu_irq_src *src, 3176 unsigned type, 3177 enum amdgpu_interrupt_state state) 3178 { 3179 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 3180 3181 switch (type) { 3182 case AMDGPU_HPD_1: 3183 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 3184 break; 3185 case AMDGPU_HPD_2: 3186 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 3187 break; 3188 case AMDGPU_HPD_3: 3189 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 3190 break; 3191 case AMDGPU_HPD_4: 3192 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 3193 break; 3194 case AMDGPU_HPD_5: 3195 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 3196 break; 3197 case AMDGPU_HPD_6: 3198 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 3199 break; 3200 default: 3201 DRM_DEBUG("invalid hdp %d\n", type); 3202 return 0; 3203 } 3204 3205 switch (state) { 3206 case AMDGPU_IRQ_STATE_DISABLE: 3207 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3208 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3209 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3210 break; 3211 case AMDGPU_IRQ_STATE_ENABLE: 3212 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3213 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3214 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3215 break; 3216 default: 3217 break; 3218 } 3219 3220 return 0; 3221 } 3222 3223 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3224 struct amdgpu_irq_src *src, 3225 unsigned type, 3226 enum amdgpu_interrupt_state state) 3227 { 3228 switch (type) { 3229 case AMDGPU_CRTC_IRQ_VBLANK1: 3230 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3231 break; 3232 case AMDGPU_CRTC_IRQ_VBLANK2: 3233 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3234 break; 3235 case AMDGPU_CRTC_IRQ_VBLANK3: 3236 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3237 break; 3238 case AMDGPU_CRTC_IRQ_VBLANK4: 3239 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3240 break; 3241 case AMDGPU_CRTC_IRQ_VBLANK5: 3242 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3243 break; 3244 case AMDGPU_CRTC_IRQ_VBLANK6: 3245 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3246 break; 3247 case AMDGPU_CRTC_IRQ_VLINE1: 3248 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); 3249 break; 3250 case AMDGPU_CRTC_IRQ_VLINE2: 3251 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); 3252 break; 3253 case AMDGPU_CRTC_IRQ_VLINE3: 3254 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); 3255 break; 3256 case AMDGPU_CRTC_IRQ_VLINE4: 3257 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); 3258 break; 3259 case AMDGPU_CRTC_IRQ_VLINE5: 3260 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); 3261 break; 3262 case AMDGPU_CRTC_IRQ_VLINE6: 3263 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); 3264 break; 3265 default: 3266 break; 3267 } 3268 return 0; 3269 } 3270 3271 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 3272 struct amdgpu_irq_src *source, 3273 struct amdgpu_iv_entry *entry) 3274 { 3275 unsigned crtc = entry->src_id - 1; 3276 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3277 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3278 3279 switch (entry->src_data) { 3280 case 0: /* vblank */ 3281 if (disp_int & interrupt_status_offsets[crtc].vblank) 3282 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3283 else 3284 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3285 3286 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3287 drm_handle_vblank(adev->ddev, crtc); 3288 } 3289 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3290 3291 break; 3292 case 1: /* vline */ 3293 if (disp_int & interrupt_status_offsets[crtc].vline) 3294 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3295 else 3296 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3297 3298 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3299 3300 break; 3301 default: 3302 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3303 break; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3310 struct amdgpu_irq_src *src, 3311 unsigned type, 3312 enum amdgpu_interrupt_state state) 3313 { 3314 u32 reg; 3315 3316 if (type >= adev->mode_info.num_crtc) { 3317 DRM_ERROR("invalid pageflip crtc %d\n", type); 3318 return -EINVAL; 3319 } 3320 3321 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3322 if (state == AMDGPU_IRQ_STATE_DISABLE) 3323 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3324 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3325 else 3326 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3327 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3328 3329 return 0; 3330 } 3331 3332 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, 3333 struct amdgpu_irq_src *source, 3334 struct amdgpu_iv_entry *entry) 3335 { 3336 unsigned long flags; 3337 unsigned crtc_id; 3338 struct amdgpu_crtc *amdgpu_crtc; 3339 struct amdgpu_flip_work *works; 3340 3341 crtc_id = (entry->src_id - 8) >> 1; 3342 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3343 3344 if (crtc_id >= adev->mode_info.num_crtc) { 3345 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3346 return -EINVAL; 3347 } 3348 3349 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3350 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3351 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3352 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3353 3354 /* IRQ could occur when in initial stage */ 3355 if (amdgpu_crtc == NULL) 3356 return 0; 3357 3358 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3359 works = amdgpu_crtc->pflip_works; 3360 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3361 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3362 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3363 amdgpu_crtc->pflip_status, 3364 AMDGPU_FLIP_SUBMITTED); 3365 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3366 return 0; 3367 } 3368 3369 /* page flip completed. clean up */ 3370 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3371 amdgpu_crtc->pflip_works = NULL; 3372 3373 /* wakeup usersapce */ 3374 if (works->event) 3375 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3376 3377 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3378 3379 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3380 schedule_work(&works->unpin_work); 3381 3382 return 0; 3383 } 3384 3385 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, 3386 struct amdgpu_irq_src *source, 3387 struct amdgpu_iv_entry *entry) 3388 { 3389 uint32_t disp_int, mask, int_control, tmp; 3390 unsigned hpd; 3391 3392 if (entry->src_data >= adev->mode_info.num_hpd) { 3393 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3394 return 0; 3395 } 3396 3397 hpd = entry->src_data; 3398 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3399 mask = interrupt_status_offsets[hpd].hpd; 3400 int_control = hpd_int_control_offsets[hpd]; 3401 3402 if (disp_int & mask) { 3403 tmp = RREG32(int_control); 3404 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3405 WREG32(int_control, tmp); 3406 schedule_work(&adev->hotplug_work); 3407 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3408 } 3409 3410 return 0; 3411 3412 } 3413 3414 static int dce_v8_0_set_clockgating_state(void *handle, 3415 enum amd_clockgating_state state) 3416 { 3417 return 0; 3418 } 3419 3420 static int dce_v8_0_set_powergating_state(void *handle, 3421 enum amd_powergating_state state) 3422 { 3423 return 0; 3424 } 3425 3426 const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3427 .name = "dce_v8_0", 3428 .early_init = dce_v8_0_early_init, 3429 .late_init = NULL, 3430 .sw_init = dce_v8_0_sw_init, 3431 .sw_fini = dce_v8_0_sw_fini, 3432 .hw_init = dce_v8_0_hw_init, 3433 .hw_fini = dce_v8_0_hw_fini, 3434 .suspend = dce_v8_0_suspend, 3435 .resume = dce_v8_0_resume, 3436 .is_idle = dce_v8_0_is_idle, 3437 .wait_for_idle = dce_v8_0_wait_for_idle, 3438 .soft_reset = dce_v8_0_soft_reset, 3439 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3440 .set_powergating_state = dce_v8_0_set_powergating_state, 3441 }; 3442 3443 static void 3444 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder, 3445 struct drm_display_mode *mode, 3446 struct drm_display_mode *adjusted_mode) 3447 { 3448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3449 3450 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3451 3452 /* need to call this here rather than in prepare() since we need some crtc info */ 3453 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3454 3455 /* set scaler clears this on some chips */ 3456 dce_v8_0_set_interleave(encoder->crtc, mode); 3457 3458 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3459 dce_v8_0_afmt_enable(encoder, true); 3460 dce_v8_0_afmt_setmode(encoder, adjusted_mode); 3461 } 3462 } 3463 3464 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) 3465 { 3466 struct amdgpu_device *adev = encoder->dev->dev_private; 3467 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3468 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3469 3470 if ((amdgpu_encoder->active_device & 3471 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3472 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3473 ENCODER_OBJECT_ID_NONE)) { 3474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3475 if (dig) { 3476 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); 3477 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3478 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3479 } 3480 } 3481 3482 amdgpu_atombios_scratch_regs_lock(adev, true); 3483 3484 if (connector) { 3485 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3486 3487 /* select the clock/data port if it uses a router */ 3488 if (amdgpu_connector->router.cd_valid) 3489 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3490 3491 /* turn eDP panel on for mode set */ 3492 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3493 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3494 ATOM_TRANSMITTER_ACTION_POWER_ON); 3495 } 3496 3497 /* this is needed for the pll/ss setup to work correctly in some cases */ 3498 amdgpu_atombios_encoder_set_crtc_source(encoder); 3499 /* set up the FMT blocks */ 3500 dce_v8_0_program_fmt(encoder); 3501 } 3502 3503 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder) 3504 { 3505 struct drm_device *dev = encoder->dev; 3506 struct amdgpu_device *adev = dev->dev_private; 3507 3508 /* need to call this here as we need the crtc set up */ 3509 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3510 amdgpu_atombios_scratch_regs_lock(adev, false); 3511 } 3512 3513 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder) 3514 { 3515 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3516 struct amdgpu_encoder_atom_dig *dig; 3517 3518 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3519 3520 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3521 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3522 dce_v8_0_afmt_enable(encoder, false); 3523 dig = amdgpu_encoder->enc_priv; 3524 dig->dig_encoder = -1; 3525 } 3526 amdgpu_encoder->active_device = 0; 3527 } 3528 3529 /* these are handled by the primary encoders */ 3530 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder) 3531 { 3532 3533 } 3534 3535 static void dce_v8_0_ext_commit(struct drm_encoder *encoder) 3536 { 3537 3538 } 3539 3540 static void 3541 dce_v8_0_ext_mode_set(struct drm_encoder *encoder, 3542 struct drm_display_mode *mode, 3543 struct drm_display_mode *adjusted_mode) 3544 { 3545 3546 } 3547 3548 static void dce_v8_0_ext_disable(struct drm_encoder *encoder) 3549 { 3550 3551 } 3552 3553 static void 3554 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode) 3555 { 3556 3557 } 3558 3559 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = { 3560 .dpms = dce_v8_0_ext_dpms, 3561 .prepare = dce_v8_0_ext_prepare, 3562 .mode_set = dce_v8_0_ext_mode_set, 3563 .commit = dce_v8_0_ext_commit, 3564 .disable = dce_v8_0_ext_disable, 3565 /* no detect for TMDS/LVDS yet */ 3566 }; 3567 3568 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = { 3569 .dpms = amdgpu_atombios_encoder_dpms, 3570 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3571 .prepare = dce_v8_0_encoder_prepare, 3572 .mode_set = dce_v8_0_encoder_mode_set, 3573 .commit = dce_v8_0_encoder_commit, 3574 .disable = dce_v8_0_encoder_disable, 3575 .detect = amdgpu_atombios_encoder_dig_detect, 3576 }; 3577 3578 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = { 3579 .dpms = amdgpu_atombios_encoder_dpms, 3580 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3581 .prepare = dce_v8_0_encoder_prepare, 3582 .mode_set = dce_v8_0_encoder_mode_set, 3583 .commit = dce_v8_0_encoder_commit, 3584 .detect = amdgpu_atombios_encoder_dac_detect, 3585 }; 3586 3587 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder) 3588 { 3589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3590 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3591 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3592 kfree(amdgpu_encoder->enc_priv); 3593 drm_encoder_cleanup(encoder); 3594 kfree(amdgpu_encoder); 3595 } 3596 3597 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { 3598 .destroy = dce_v8_0_encoder_destroy, 3599 }; 3600 3601 static void dce_v8_0_encoder_add(struct amdgpu_device *adev, 3602 uint32_t encoder_enum, 3603 uint32_t supported_device, 3604 u16 caps) 3605 { 3606 struct drm_device *dev = adev->ddev; 3607 struct drm_encoder *encoder; 3608 struct amdgpu_encoder *amdgpu_encoder; 3609 3610 /* see if we already added it */ 3611 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3612 amdgpu_encoder = to_amdgpu_encoder(encoder); 3613 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3614 amdgpu_encoder->devices |= supported_device; 3615 return; 3616 } 3617 3618 } 3619 3620 /* add a new one */ 3621 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3622 if (!amdgpu_encoder) 3623 return; 3624 3625 encoder = &amdgpu_encoder->base; 3626 switch (adev->mode_info.num_crtc) { 3627 case 1: 3628 encoder->possible_crtcs = 0x1; 3629 break; 3630 case 2: 3631 default: 3632 encoder->possible_crtcs = 0x3; 3633 break; 3634 case 4: 3635 encoder->possible_crtcs = 0xf; 3636 break; 3637 case 6: 3638 encoder->possible_crtcs = 0x3f; 3639 break; 3640 } 3641 3642 amdgpu_encoder->enc_priv = NULL; 3643 3644 amdgpu_encoder->encoder_enum = encoder_enum; 3645 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3646 amdgpu_encoder->devices = supported_device; 3647 amdgpu_encoder->rmx_type = RMX_OFF; 3648 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3649 amdgpu_encoder->is_ext_encoder = false; 3650 amdgpu_encoder->caps = caps; 3651 3652 switch (amdgpu_encoder->encoder_id) { 3653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3655 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3656 DRM_MODE_ENCODER_DAC, NULL); 3657 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); 3658 break; 3659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3660 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3664 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3665 amdgpu_encoder->rmx_type = RMX_FULL; 3666 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3667 DRM_MODE_ENCODER_LVDS, NULL); 3668 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3669 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3670 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3671 DRM_MODE_ENCODER_DAC, NULL); 3672 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3673 } else { 3674 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3675 DRM_MODE_ENCODER_TMDS, NULL); 3676 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3677 } 3678 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); 3679 break; 3680 case ENCODER_OBJECT_ID_SI170B: 3681 case ENCODER_OBJECT_ID_CH7303: 3682 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3683 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3684 case ENCODER_OBJECT_ID_TITFP513: 3685 case ENCODER_OBJECT_ID_VT1623: 3686 case ENCODER_OBJECT_ID_HDMI_SI1930: 3687 case ENCODER_OBJECT_ID_TRAVIS: 3688 case ENCODER_OBJECT_ID_NUTMEG: 3689 /* these are handled by the primary encoders */ 3690 amdgpu_encoder->is_ext_encoder = true; 3691 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3692 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3693 DRM_MODE_ENCODER_LVDS, NULL); 3694 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3695 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3696 DRM_MODE_ENCODER_DAC, NULL); 3697 else 3698 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3699 DRM_MODE_ENCODER_TMDS, NULL); 3700 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs); 3701 break; 3702 } 3703 } 3704 3705 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { 3706 .set_vga_render_state = &dce_v8_0_set_vga_render_state, 3707 .bandwidth_update = &dce_v8_0_bandwidth_update, 3708 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3709 .vblank_wait = &dce_v8_0_vblank_wait, 3710 .is_display_hung = &dce_v8_0_is_display_hung, 3711 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3712 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3713 .hpd_sense = &dce_v8_0_hpd_sense, 3714 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity, 3715 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg, 3716 .page_flip = &dce_v8_0_page_flip, 3717 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos, 3718 .add_encoder = &dce_v8_0_encoder_add, 3719 .add_connector = &amdgpu_connector_add, 3720 .stop_mc_access = &dce_v8_0_stop_mc_access, 3721 .resume_mc_access = &dce_v8_0_resume_mc_access, 3722 }; 3723 3724 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) 3725 { 3726 if (adev->mode_info.funcs == NULL) 3727 adev->mode_info.funcs = &dce_v8_0_display_funcs; 3728 } 3729 3730 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = { 3731 .set = dce_v8_0_set_crtc_interrupt_state, 3732 .process = dce_v8_0_crtc_irq, 3733 }; 3734 3735 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = { 3736 .set = dce_v8_0_set_pageflip_interrupt_state, 3737 .process = dce_v8_0_pageflip_irq, 3738 }; 3739 3740 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { 3741 .set = dce_v8_0_set_hpd_interrupt_state, 3742 .process = dce_v8_0_hpd_irq, 3743 }; 3744 3745 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) 3746 { 3747 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3748 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; 3749 3750 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3751 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; 3752 3753 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3754 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; 3755 } 3756