1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "cikd.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_8_0_d.h" 36 #include "dce/dce_8_0_sh_mask.h" 37 38 #include "gca/gfx_7_2_enum.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); 47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); 48 49 static const u32 crtc_offsets[6] = 50 { 51 CRTC0_REGISTER_OFFSET, 52 CRTC1_REGISTER_OFFSET, 53 CRTC2_REGISTER_OFFSET, 54 CRTC3_REGISTER_OFFSET, 55 CRTC4_REGISTER_OFFSET, 56 CRTC5_REGISTER_OFFSET 57 }; 58 59 static const uint32_t dig_offsets[] = { 60 CRTC0_REGISTER_OFFSET, 61 CRTC1_REGISTER_OFFSET, 62 CRTC2_REGISTER_OFFSET, 63 CRTC3_REGISTER_OFFSET, 64 CRTC4_REGISTER_OFFSET, 65 CRTC5_REGISTER_OFFSET, 66 (0x13830 - 0x7030) >> 2, 67 }; 68 69 static const struct { 70 uint32_t reg; 71 uint32_t vblank; 72 uint32_t vline; 73 uint32_t hpd; 74 75 } interrupt_status_offsets[6] = { { 76 .reg = mmDISP_INTERRUPT_STATUS, 77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 80 }, { 81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 85 }, { 86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 105 } }; 106 107 static const uint32_t hpd_int_control_offsets[6] = { 108 mmDC_HPD1_INT_CONTROL, 109 mmDC_HPD2_INT_CONTROL, 110 mmDC_HPD3_INT_CONTROL, 111 mmDC_HPD4_INT_CONTROL, 112 mmDC_HPD5_INT_CONTROL, 113 mmDC_HPD6_INT_CONTROL, 114 }; 115 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, 117 u32 block_offset, u32 reg) 118 { 119 unsigned long flags; 120 u32 r; 121 122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 126 127 return r; 128 } 129 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, 131 u32 block_offset, u32 reg, u32 v) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 139 } 140 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 142 { 143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 145 return true; 146 else 147 return false; 148 } 149 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 151 { 152 u32 pos1, pos2; 153 154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 156 157 if (pos1 != pos2) 158 return true; 159 else 160 return false; 161 } 162 163 /** 164 * dce_v8_0_vblank_wait - vblank wait asic callback. 165 * 166 * @adev: amdgpu_device pointer 167 * @crtc: crtc to wait for vblank on 168 * 169 * Wait for vblank on the requested crtc (evergreen+). 170 */ 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) 172 { 173 unsigned i = 0; 174 175 if (crtc >= adev->mode_info.num_crtc) 176 return; 177 178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 179 return; 180 181 /* depending on when we hit vblank, we may be close to active; if so, 182 * wait for another frame. 183 */ 184 while (dce_v8_0_is_in_vblank(adev, crtc)) { 185 if (i++ % 100 == 0) { 186 if (!dce_v8_0_is_counter_moving(adev, crtc)) 187 break; 188 } 189 } 190 191 while (!dce_v8_0_is_in_vblank(adev, crtc)) { 192 if (i++ % 100 == 0) { 193 if (!dce_v8_0_is_counter_moving(adev, crtc)) 194 break; 195 } 196 } 197 } 198 199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 200 { 201 if (crtc >= adev->mode_info.num_crtc) 202 return 0; 203 else 204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 205 } 206 207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) 208 { 209 unsigned i; 210 211 /* Enable pflip interrupts */ 212 for (i = 0; i < adev->mode_info.num_crtc; i++) 213 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 214 } 215 216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 217 { 218 unsigned i; 219 220 /* Disable pflip interrupts */ 221 for (i = 0; i < adev->mode_info.num_crtc; i++) 222 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 223 } 224 225 /** 226 * dce_v8_0_page_flip - pageflip callback. 227 * 228 * @adev: amdgpu_device pointer 229 * @crtc_id: crtc to cleanup pageflip on 230 * @crtc_base: new address of the crtc (GPU MC address) 231 * 232 * Triggers the actual pageflip by updating the primary 233 * surface base address. 234 */ 235 static void dce_v8_0_page_flip(struct amdgpu_device *adev, 236 int crtc_id, u64 crtc_base, bool async) 237 { 238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 239 240 /* flip at hsync for async, default is vsync */ 241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 243 /* update the primary scanout addresses */ 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 245 upper_32_bits(crtc_base)); 246 /* writing to the low address triggers the update */ 247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 248 lower_32_bits(crtc_base)); 249 /* post the write */ 250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 251 } 252 253 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 254 u32 *vbl, u32 *position) 255 { 256 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 257 return -EINVAL; 258 259 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 260 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 261 262 return 0; 263 } 264 265 /** 266 * dce_v8_0_hpd_sense - hpd sense callback. 267 * 268 * @adev: amdgpu_device pointer 269 * @hpd: hpd (hotplug detect) pin 270 * 271 * Checks if a digital monitor is connected (evergreen+). 272 * Returns true if connected, false if not connected. 273 */ 274 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, 275 enum amdgpu_hpd_id hpd) 276 { 277 bool connected = false; 278 279 switch (hpd) { 280 case AMDGPU_HPD_1: 281 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 282 connected = true; 283 break; 284 case AMDGPU_HPD_2: 285 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) 286 connected = true; 287 break; 288 case AMDGPU_HPD_3: 289 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) 290 connected = true; 291 break; 292 case AMDGPU_HPD_4: 293 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) 294 connected = true; 295 break; 296 case AMDGPU_HPD_5: 297 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) 298 connected = true; 299 break; 300 case AMDGPU_HPD_6: 301 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) 302 connected = true; 303 break; 304 default: 305 break; 306 } 307 308 return connected; 309 } 310 311 /** 312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback. 313 * 314 * @adev: amdgpu_device pointer 315 * @hpd: hpd (hotplug detect) pin 316 * 317 * Set the polarity of the hpd pin (evergreen+). 318 */ 319 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, 320 enum amdgpu_hpd_id hpd) 321 { 322 u32 tmp; 323 bool connected = dce_v8_0_hpd_sense(adev, hpd); 324 325 switch (hpd) { 326 case AMDGPU_HPD_1: 327 tmp = RREG32(mmDC_HPD1_INT_CONTROL); 328 if (connected) 329 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 330 else 331 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 332 WREG32(mmDC_HPD1_INT_CONTROL, tmp); 333 break; 334 case AMDGPU_HPD_2: 335 tmp = RREG32(mmDC_HPD2_INT_CONTROL); 336 if (connected) 337 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 338 else 339 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 340 WREG32(mmDC_HPD2_INT_CONTROL, tmp); 341 break; 342 case AMDGPU_HPD_3: 343 tmp = RREG32(mmDC_HPD3_INT_CONTROL); 344 if (connected) 345 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 346 else 347 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 348 WREG32(mmDC_HPD3_INT_CONTROL, tmp); 349 break; 350 case AMDGPU_HPD_4: 351 tmp = RREG32(mmDC_HPD4_INT_CONTROL); 352 if (connected) 353 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 354 else 355 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 356 WREG32(mmDC_HPD4_INT_CONTROL, tmp); 357 break; 358 case AMDGPU_HPD_5: 359 tmp = RREG32(mmDC_HPD5_INT_CONTROL); 360 if (connected) 361 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 362 else 363 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 364 WREG32(mmDC_HPD5_INT_CONTROL, tmp); 365 break; 366 case AMDGPU_HPD_6: 367 tmp = RREG32(mmDC_HPD6_INT_CONTROL); 368 if (connected) 369 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 370 else 371 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 372 WREG32(mmDC_HPD6_INT_CONTROL, tmp); 373 break; 374 default: 375 break; 376 } 377 } 378 379 /** 380 * dce_v8_0_hpd_init - hpd setup callback. 381 * 382 * @adev: amdgpu_device pointer 383 * 384 * Setup the hpd pins used by the card (evergreen+). 385 * Enable the pin, set the polarity, and enable the hpd interrupts. 386 */ 387 static void dce_v8_0_hpd_init(struct amdgpu_device *adev) 388 { 389 struct drm_device *dev = adev->ddev; 390 struct drm_connector *connector; 391 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) | 392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) | 393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 394 395 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 396 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 397 398 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 399 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 400 /* don't try to enable hpd on eDP or LVDS avoid breaking the 401 * aux dp channel on imac and help (but not completely fix) 402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 403 * also avoid interrupt storms during dpms. 404 */ 405 continue; 406 } 407 switch (amdgpu_connector->hpd.hpd) { 408 case AMDGPU_HPD_1: 409 WREG32(mmDC_HPD1_CONTROL, tmp); 410 break; 411 case AMDGPU_HPD_2: 412 WREG32(mmDC_HPD2_CONTROL, tmp); 413 break; 414 case AMDGPU_HPD_3: 415 WREG32(mmDC_HPD3_CONTROL, tmp); 416 break; 417 case AMDGPU_HPD_4: 418 WREG32(mmDC_HPD4_CONTROL, tmp); 419 break; 420 case AMDGPU_HPD_5: 421 WREG32(mmDC_HPD5_CONTROL, tmp); 422 break; 423 case AMDGPU_HPD_6: 424 WREG32(mmDC_HPD6_CONTROL, tmp); 425 break; 426 default: 427 break; 428 } 429 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 430 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 431 } 432 } 433 434 /** 435 * dce_v8_0_hpd_fini - hpd tear down callback. 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Tear down the hpd pins used by the card (evergreen+). 440 * Disable the hpd interrupts. 441 */ 442 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) 443 { 444 struct drm_device *dev = adev->ddev; 445 struct drm_connector *connector; 446 447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 448 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 449 450 switch (amdgpu_connector->hpd.hpd) { 451 case AMDGPU_HPD_1: 452 WREG32(mmDC_HPD1_CONTROL, 0); 453 break; 454 case AMDGPU_HPD_2: 455 WREG32(mmDC_HPD2_CONTROL, 0); 456 break; 457 case AMDGPU_HPD_3: 458 WREG32(mmDC_HPD3_CONTROL, 0); 459 break; 460 case AMDGPU_HPD_4: 461 WREG32(mmDC_HPD4_CONTROL, 0); 462 break; 463 case AMDGPU_HPD_5: 464 WREG32(mmDC_HPD5_CONTROL, 0); 465 break; 466 case AMDGPU_HPD_6: 467 WREG32(mmDC_HPD6_CONTROL, 0); 468 break; 469 default: 470 break; 471 } 472 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 473 } 474 } 475 476 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 477 { 478 return mmDC_GPIO_HPD_A; 479 } 480 481 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) 482 { 483 u32 crtc_hung = 0; 484 u32 crtc_status[6]; 485 u32 i, j, tmp; 486 487 for (i = 0; i < adev->mode_info.num_crtc; i++) { 488 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 489 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 490 crtc_hung |= (1 << i); 491 } 492 } 493 494 for (j = 0; j < 10; j++) { 495 for (i = 0; i < adev->mode_info.num_crtc; i++) { 496 if (crtc_hung & (1 << i)) { 497 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 498 if (tmp != crtc_status[i]) 499 crtc_hung &= ~(1 << i); 500 } 501 } 502 if (crtc_hung == 0) 503 return false; 504 udelay(100); 505 } 506 507 return true; 508 } 509 510 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 511 struct amdgpu_mode_mc_save *save) 512 { 513 u32 crtc_enabled, tmp; 514 int i; 515 516 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 517 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 518 519 /* disable VGA render */ 520 tmp = RREG32(mmVGA_RENDER_CONTROL); 521 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 522 WREG32(mmVGA_RENDER_CONTROL, tmp); 523 524 /* blank the display controllers */ 525 for (i = 0; i < adev->mode_info.num_crtc; i++) { 526 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 527 CRTC_CONTROL, CRTC_MASTER_EN); 528 if (crtc_enabled) { 529 #if 1 530 save->crtc_enabled[i] = true; 531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 532 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 533 /*it is correct only for RGB ; black is 0*/ 534 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 535 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 537 } 538 mdelay(20); 539 #else 540 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 541 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 542 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 543 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 544 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 545 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 546 save->crtc_enabled[i] = false; 547 /* ***** */ 548 #endif 549 } else { 550 save->crtc_enabled[i] = false; 551 } 552 } 553 } 554 555 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, 556 struct amdgpu_mode_mc_save *save) 557 { 558 u32 tmp; 559 int i; 560 561 /* update crtc base addresses */ 562 for (i = 0; i < adev->mode_info.num_crtc; i++) { 563 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 564 upper_32_bits(adev->mc.vram_start)); 565 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 566 (u32)adev->mc.vram_start); 567 568 if (save->crtc_enabled[i]) { 569 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 570 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 571 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 572 } 573 mdelay(20); 574 } 575 576 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 577 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 578 579 /* Unlock vga access */ 580 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 581 mdelay(1); 582 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 583 } 584 585 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, 586 bool render) 587 { 588 u32 tmp; 589 590 /* Lockout access through VGA aperture*/ 591 tmp = RREG32(mmVGA_HDP_CONTROL); 592 if (render) 593 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 594 else 595 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 596 WREG32(mmVGA_HDP_CONTROL, tmp); 597 598 /* disable VGA render */ 599 tmp = RREG32(mmVGA_RENDER_CONTROL); 600 if (render) 601 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 602 else 603 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 604 WREG32(mmVGA_RENDER_CONTROL, tmp); 605 } 606 607 static void dce_v8_0_program_fmt(struct drm_encoder *encoder) 608 { 609 struct drm_device *dev = encoder->dev; 610 struct amdgpu_device *adev = dev->dev_private; 611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 612 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 613 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 614 int bpc = 0; 615 u32 tmp = 0; 616 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 617 618 if (connector) { 619 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 620 bpc = amdgpu_connector_get_monitor_bpc(connector); 621 dither = amdgpu_connector->dither; 622 } 623 624 /* LVDS/eDP FMT is set up by atom */ 625 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 626 return; 627 628 /* not needed for analog */ 629 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 630 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 631 return; 632 633 if (bpc == 0) 634 return; 635 636 switch (bpc) { 637 case 6: 638 if (dither == AMDGPU_FMT_DITHER_ENABLE) 639 /* XXX sort out optimal dither settings */ 640 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 641 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 642 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 643 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 644 else 645 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 646 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 647 break; 648 case 8: 649 if (dither == AMDGPU_FMT_DITHER_ENABLE) 650 /* XXX sort out optimal dither settings */ 651 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 652 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 653 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 654 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 655 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 656 else 657 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 658 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 659 break; 660 case 10: 661 if (dither == AMDGPU_FMT_DITHER_ENABLE) 662 /* XXX sort out optimal dither settings */ 663 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 664 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 665 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 666 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 667 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 668 else 669 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 670 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 671 break; 672 default: 673 /* not needed */ 674 break; 675 } 676 677 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 678 } 679 680 681 /* display watermark setup */ 682 /** 683 * dce_v8_0_line_buffer_adjust - Set up the line buffer 684 * 685 * @adev: amdgpu_device pointer 686 * @amdgpu_crtc: the selected display controller 687 * @mode: the current display mode on the selected display 688 * controller 689 * 690 * Setup up the line buffer allocation for 691 * the selected display controller (CIK). 692 * Returns the line buffer size in pixels. 693 */ 694 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, 695 struct amdgpu_crtc *amdgpu_crtc, 696 struct drm_display_mode *mode) 697 { 698 u32 tmp, buffer_alloc, i; 699 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 700 /* 701 * Line Buffer Setup 702 * There are 6 line buffers, one for each display controllers. 703 * There are 3 partitions per LB. Select the number of partitions 704 * to enable based on the display width. For display widths larger 705 * than 4096, you need use to use 2 display controllers and combine 706 * them using the stereo blender. 707 */ 708 if (amdgpu_crtc->base.enabled && mode) { 709 if (mode->crtc_hdisplay < 1920) { 710 tmp = 1; 711 buffer_alloc = 2; 712 } else if (mode->crtc_hdisplay < 2560) { 713 tmp = 2; 714 buffer_alloc = 2; 715 } else if (mode->crtc_hdisplay < 4096) { 716 tmp = 0; 717 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 718 } else { 719 DRM_DEBUG_KMS("Mode too big for LB!\n"); 720 tmp = 0; 721 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 722 } 723 } else { 724 tmp = 1; 725 buffer_alloc = 0; 726 } 727 728 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, 729 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) | 730 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT)); 731 732 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 733 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 734 for (i = 0; i < adev->usec_timeout; i++) { 735 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 736 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 737 break; 738 udelay(1); 739 } 740 741 if (amdgpu_crtc->base.enabled && mode) { 742 switch (tmp) { 743 case 0: 744 default: 745 return 4096 * 2; 746 case 1: 747 return 1920 * 2; 748 case 2: 749 return 2560 * 2; 750 } 751 } 752 753 /* controller not enabled, so no lb used */ 754 return 0; 755 } 756 757 /** 758 * cik_get_number_of_dram_channels - get the number of dram channels 759 * 760 * @adev: amdgpu_device pointer 761 * 762 * Look up the number of video ram channels (CIK). 763 * Used for display watermark bandwidth calculations 764 * Returns the number of dram channels 765 */ 766 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 767 { 768 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 769 770 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 771 case 0: 772 default: 773 return 1; 774 case 1: 775 return 2; 776 case 2: 777 return 4; 778 case 3: 779 return 8; 780 case 4: 781 return 3; 782 case 5: 783 return 6; 784 case 6: 785 return 10; 786 case 7: 787 return 12; 788 case 8: 789 return 16; 790 } 791 } 792 793 struct dce8_wm_params { 794 u32 dram_channels; /* number of dram channels */ 795 u32 yclk; /* bandwidth per dram data pin in kHz */ 796 u32 sclk; /* engine clock in kHz */ 797 u32 disp_clk; /* display clock in kHz */ 798 u32 src_width; /* viewport width */ 799 u32 active_time; /* active display time in ns */ 800 u32 blank_time; /* blank time in ns */ 801 bool interlaced; /* mode is interlaced */ 802 fixed20_12 vsc; /* vertical scale ratio */ 803 u32 num_heads; /* number of active crtcs */ 804 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 805 u32 lb_size; /* line buffer allocated to pipe */ 806 u32 vtaps; /* vertical scaler taps */ 807 }; 808 809 /** 810 * dce_v8_0_dram_bandwidth - get the dram bandwidth 811 * 812 * @wm: watermark calculation data 813 * 814 * Calculate the raw dram bandwidth (CIK). 815 * Used for display watermark bandwidth calculations 816 * Returns the dram bandwidth in MBytes/s 817 */ 818 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) 819 { 820 /* Calculate raw DRAM Bandwidth */ 821 fixed20_12 dram_efficiency; /* 0.7 */ 822 fixed20_12 yclk, dram_channels, bandwidth; 823 fixed20_12 a; 824 825 a.full = dfixed_const(1000); 826 yclk.full = dfixed_const(wm->yclk); 827 yclk.full = dfixed_div(yclk, a); 828 dram_channels.full = dfixed_const(wm->dram_channels * 4); 829 a.full = dfixed_const(10); 830 dram_efficiency.full = dfixed_const(7); 831 dram_efficiency.full = dfixed_div(dram_efficiency, a); 832 bandwidth.full = dfixed_mul(dram_channels, yclk); 833 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 834 835 return dfixed_trunc(bandwidth); 836 } 837 838 /** 839 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display 840 * 841 * @wm: watermark calculation data 842 * 843 * Calculate the dram bandwidth used for display (CIK). 844 * Used for display watermark bandwidth calculations 845 * Returns the dram bandwidth for display in MBytes/s 846 */ 847 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) 848 { 849 /* Calculate DRAM Bandwidth and the part allocated to display. */ 850 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 851 fixed20_12 yclk, dram_channels, bandwidth; 852 fixed20_12 a; 853 854 a.full = dfixed_const(1000); 855 yclk.full = dfixed_const(wm->yclk); 856 yclk.full = dfixed_div(yclk, a); 857 dram_channels.full = dfixed_const(wm->dram_channels * 4); 858 a.full = dfixed_const(10); 859 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 860 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 861 bandwidth.full = dfixed_mul(dram_channels, yclk); 862 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 863 864 return dfixed_trunc(bandwidth); 865 } 866 867 /** 868 * dce_v8_0_data_return_bandwidth - get the data return bandwidth 869 * 870 * @wm: watermark calculation data 871 * 872 * Calculate the data return bandwidth used for display (CIK). 873 * Used for display watermark bandwidth calculations 874 * Returns the data return bandwidth in MBytes/s 875 */ 876 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) 877 { 878 /* Calculate the display Data return Bandwidth */ 879 fixed20_12 return_efficiency; /* 0.8 */ 880 fixed20_12 sclk, bandwidth; 881 fixed20_12 a; 882 883 a.full = dfixed_const(1000); 884 sclk.full = dfixed_const(wm->sclk); 885 sclk.full = dfixed_div(sclk, a); 886 a.full = dfixed_const(10); 887 return_efficiency.full = dfixed_const(8); 888 return_efficiency.full = dfixed_div(return_efficiency, a); 889 a.full = dfixed_const(32); 890 bandwidth.full = dfixed_mul(a, sclk); 891 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 892 893 return dfixed_trunc(bandwidth); 894 } 895 896 /** 897 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth 898 * 899 * @wm: watermark calculation data 900 * 901 * Calculate the dmif bandwidth used for display (CIK). 902 * Used for display watermark bandwidth calculations 903 * Returns the dmif bandwidth in MBytes/s 904 */ 905 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) 906 { 907 /* Calculate the DMIF Request Bandwidth */ 908 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 909 fixed20_12 disp_clk, bandwidth; 910 fixed20_12 a, b; 911 912 a.full = dfixed_const(1000); 913 disp_clk.full = dfixed_const(wm->disp_clk); 914 disp_clk.full = dfixed_div(disp_clk, a); 915 a.full = dfixed_const(32); 916 b.full = dfixed_mul(a, disp_clk); 917 918 a.full = dfixed_const(10); 919 disp_clk_request_efficiency.full = dfixed_const(8); 920 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 921 922 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 923 924 return dfixed_trunc(bandwidth); 925 } 926 927 /** 928 * dce_v8_0_available_bandwidth - get the min available bandwidth 929 * 930 * @wm: watermark calculation data 931 * 932 * Calculate the min available bandwidth used for display (CIK). 933 * Used for display watermark bandwidth calculations 934 * Returns the min available bandwidth in MBytes/s 935 */ 936 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) 937 { 938 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 939 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); 940 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); 941 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); 942 943 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 944 } 945 946 /** 947 * dce_v8_0_average_bandwidth - get the average available bandwidth 948 * 949 * @wm: watermark calculation data 950 * 951 * Calculate the average available bandwidth used for display (CIK). 952 * Used for display watermark bandwidth calculations 953 * Returns the average available bandwidth in MBytes/s 954 */ 955 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) 956 { 957 /* Calculate the display mode Average Bandwidth 958 * DisplayMode should contain the source and destination dimensions, 959 * timing, etc. 960 */ 961 fixed20_12 bpp; 962 fixed20_12 line_time; 963 fixed20_12 src_width; 964 fixed20_12 bandwidth; 965 fixed20_12 a; 966 967 a.full = dfixed_const(1000); 968 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 969 line_time.full = dfixed_div(line_time, a); 970 bpp.full = dfixed_const(wm->bytes_per_pixel); 971 src_width.full = dfixed_const(wm->src_width); 972 bandwidth.full = dfixed_mul(src_width, bpp); 973 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 974 bandwidth.full = dfixed_div(bandwidth, line_time); 975 976 return dfixed_trunc(bandwidth); 977 } 978 979 /** 980 * dce_v8_0_latency_watermark - get the latency watermark 981 * 982 * @wm: watermark calculation data 983 * 984 * Calculate the latency watermark (CIK). 985 * Used for display watermark bandwidth calculations 986 * Returns the latency watermark in ns 987 */ 988 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) 989 { 990 /* First calculate the latency in ns */ 991 u32 mc_latency = 2000; /* 2000 ns. */ 992 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); 993 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 994 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 995 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 996 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 997 (wm->num_heads * cursor_line_pair_return_time); 998 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 999 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1000 u32 tmp, dmif_size = 12288; 1001 fixed20_12 a, b, c; 1002 1003 if (wm->num_heads == 0) 1004 return 0; 1005 1006 a.full = dfixed_const(2); 1007 b.full = dfixed_const(1); 1008 if ((wm->vsc.full > a.full) || 1009 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1010 (wm->vtaps >= 5) || 1011 ((wm->vsc.full >= a.full) && wm->interlaced)) 1012 max_src_lines_per_dst_line = 4; 1013 else 1014 max_src_lines_per_dst_line = 2; 1015 1016 a.full = dfixed_const(available_bandwidth); 1017 b.full = dfixed_const(wm->num_heads); 1018 a.full = dfixed_div(a, b); 1019 1020 b.full = dfixed_const(mc_latency + 512); 1021 c.full = dfixed_const(wm->disp_clk); 1022 b.full = dfixed_div(b, c); 1023 1024 c.full = dfixed_const(dmif_size); 1025 b.full = dfixed_div(c, b); 1026 1027 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1028 1029 b.full = dfixed_const(1000); 1030 c.full = dfixed_const(wm->disp_clk); 1031 b.full = dfixed_div(c, b); 1032 c.full = dfixed_const(wm->bytes_per_pixel); 1033 b.full = dfixed_mul(b, c); 1034 1035 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1036 1037 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1038 b.full = dfixed_const(1000); 1039 c.full = dfixed_const(lb_fill_bw); 1040 b.full = dfixed_div(c, b); 1041 a.full = dfixed_div(a, b); 1042 line_fill_time = dfixed_trunc(a); 1043 1044 if (line_fill_time < wm->active_time) 1045 return latency; 1046 else 1047 return latency + (line_fill_time - wm->active_time); 1048 1049 } 1050 1051 /** 1052 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1053 * average and available dram bandwidth 1054 * 1055 * @wm: watermark calculation data 1056 * 1057 * Check if the display average bandwidth fits in the display 1058 * dram bandwidth (CIK). 1059 * Used for display watermark bandwidth calculations 1060 * Returns true if the display fits, false if not. 1061 */ 1062 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) 1063 { 1064 if (dce_v8_0_average_bandwidth(wm) <= 1065 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1066 return true; 1067 else 1068 return false; 1069 } 1070 1071 /** 1072 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check 1073 * average and available bandwidth 1074 * 1075 * @wm: watermark calculation data 1076 * 1077 * Check if the display average bandwidth fits in the display 1078 * available bandwidth (CIK). 1079 * Used for display watermark bandwidth calculations 1080 * Returns true if the display fits, false if not. 1081 */ 1082 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) 1083 { 1084 if (dce_v8_0_average_bandwidth(wm) <= 1085 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) 1086 return true; 1087 else 1088 return false; 1089 } 1090 1091 /** 1092 * dce_v8_0_check_latency_hiding - check latency hiding 1093 * 1094 * @wm: watermark calculation data 1095 * 1096 * Check latency hiding (CIK). 1097 * Used for display watermark bandwidth calculations 1098 * Returns true if the display fits, false if not. 1099 */ 1100 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) 1101 { 1102 u32 lb_partitions = wm->lb_size / wm->src_width; 1103 u32 line_time = wm->active_time + wm->blank_time; 1104 u32 latency_tolerant_lines; 1105 u32 latency_hiding; 1106 fixed20_12 a; 1107 1108 a.full = dfixed_const(1); 1109 if (wm->vsc.full > a.full) 1110 latency_tolerant_lines = 1; 1111 else { 1112 if (lb_partitions <= (wm->vtaps + 1)) 1113 latency_tolerant_lines = 1; 1114 else 1115 latency_tolerant_lines = 2; 1116 } 1117 1118 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1119 1120 if (dce_v8_0_latency_watermark(wm) <= latency_hiding) 1121 return true; 1122 else 1123 return false; 1124 } 1125 1126 /** 1127 * dce_v8_0_program_watermarks - program display watermarks 1128 * 1129 * @adev: amdgpu_device pointer 1130 * @amdgpu_crtc: the selected display controller 1131 * @lb_size: line buffer size 1132 * @num_heads: number of display controllers in use 1133 * 1134 * Calculate and program the display watermarks for the 1135 * selected display controller (CIK). 1136 */ 1137 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, 1138 struct amdgpu_crtc *amdgpu_crtc, 1139 u32 lb_size, u32 num_heads) 1140 { 1141 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1142 struct dce8_wm_params wm_low, wm_high; 1143 u32 pixel_period; 1144 u32 line_time = 0; 1145 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1146 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1147 1148 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1149 pixel_period = 1000000 / (u32)mode->clock; 1150 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1151 1152 /* watermark for high clocks */ 1153 if (adev->pm.dpm_enabled) { 1154 wm_high.yclk = 1155 amdgpu_dpm_get_mclk(adev, false) * 10; 1156 wm_high.sclk = 1157 amdgpu_dpm_get_sclk(adev, false) * 10; 1158 } else { 1159 wm_high.yclk = adev->pm.current_mclk * 10; 1160 wm_high.sclk = adev->pm.current_sclk * 10; 1161 } 1162 1163 wm_high.disp_clk = mode->clock; 1164 wm_high.src_width = mode->crtc_hdisplay; 1165 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1166 wm_high.blank_time = line_time - wm_high.active_time; 1167 wm_high.interlaced = false; 1168 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1169 wm_high.interlaced = true; 1170 wm_high.vsc = amdgpu_crtc->vsc; 1171 wm_high.vtaps = 1; 1172 if (amdgpu_crtc->rmx_type != RMX_OFF) 1173 wm_high.vtaps = 2; 1174 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1175 wm_high.lb_size = lb_size; 1176 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1177 wm_high.num_heads = num_heads; 1178 1179 /* set for high clocks */ 1180 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535); 1181 1182 /* possibly force display priority to high */ 1183 /* should really do this at mode validation time... */ 1184 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1185 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1186 !dce_v8_0_check_latency_hiding(&wm_high) || 1187 (adev->mode_info.disp_priority == 2)) { 1188 DRM_DEBUG_KMS("force priority to high\n"); 1189 } 1190 1191 /* watermark for low clocks */ 1192 if (adev->pm.dpm_enabled) { 1193 wm_low.yclk = 1194 amdgpu_dpm_get_mclk(adev, true) * 10; 1195 wm_low.sclk = 1196 amdgpu_dpm_get_sclk(adev, true) * 10; 1197 } else { 1198 wm_low.yclk = adev->pm.current_mclk * 10; 1199 wm_low.sclk = adev->pm.current_sclk * 10; 1200 } 1201 1202 wm_low.disp_clk = mode->clock; 1203 wm_low.src_width = mode->crtc_hdisplay; 1204 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1205 wm_low.blank_time = line_time - wm_low.active_time; 1206 wm_low.interlaced = false; 1207 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1208 wm_low.interlaced = true; 1209 wm_low.vsc = amdgpu_crtc->vsc; 1210 wm_low.vtaps = 1; 1211 if (amdgpu_crtc->rmx_type != RMX_OFF) 1212 wm_low.vtaps = 2; 1213 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1214 wm_low.lb_size = lb_size; 1215 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1216 wm_low.num_heads = num_heads; 1217 1218 /* set for low clocks */ 1219 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535); 1220 1221 /* possibly force display priority to high */ 1222 /* should really do this at mode validation time... */ 1223 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1224 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1225 !dce_v8_0_check_latency_hiding(&wm_low) || 1226 (adev->mode_info.disp_priority == 2)) { 1227 DRM_DEBUG_KMS("force priority to high\n"); 1228 } 1229 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1230 } 1231 1232 /* select wm A */ 1233 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1234 tmp = wm_mask; 1235 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1236 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1237 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1238 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1239 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1240 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1241 /* select wm B */ 1242 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1243 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1244 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1245 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1246 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1247 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1248 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1249 /* restore original selection */ 1250 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1251 1252 /* save values for DPM */ 1253 amdgpu_crtc->line_time = line_time; 1254 amdgpu_crtc->wm_high = latency_watermark_a; 1255 amdgpu_crtc->wm_low = latency_watermark_b; 1256 /* Save number of lines the linebuffer leads before the scanout */ 1257 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1258 } 1259 1260 /** 1261 * dce_v8_0_bandwidth_update - program display watermarks 1262 * 1263 * @adev: amdgpu_device pointer 1264 * 1265 * Calculate and program the display watermarks and line 1266 * buffer allocation (CIK). 1267 */ 1268 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) 1269 { 1270 struct drm_display_mode *mode = NULL; 1271 u32 num_heads = 0, lb_size; 1272 int i; 1273 1274 amdgpu_update_display_priority(adev); 1275 1276 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1277 if (adev->mode_info.crtcs[i]->base.enabled) 1278 num_heads++; 1279 } 1280 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1281 mode = &adev->mode_info.crtcs[i]->base.mode; 1282 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1283 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1284 lb_size, num_heads); 1285 } 1286 } 1287 1288 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) 1289 { 1290 int i; 1291 u32 offset, tmp; 1292 1293 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1294 offset = adev->mode_info.audio.pin[i].offset; 1295 tmp = RREG32_AUDIO_ENDPT(offset, 1296 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1297 if (((tmp & 1298 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1299 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1300 adev->mode_info.audio.pin[i].connected = false; 1301 else 1302 adev->mode_info.audio.pin[i].connected = true; 1303 } 1304 } 1305 1306 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) 1307 { 1308 int i; 1309 1310 dce_v8_0_audio_get_connected_pins(adev); 1311 1312 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1313 if (adev->mode_info.audio.pin[i].connected) 1314 return &adev->mode_info.audio.pin[i]; 1315 } 1316 DRM_ERROR("No connected audio pins found!\n"); 1317 return NULL; 1318 } 1319 1320 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1321 { 1322 struct amdgpu_device *adev = encoder->dev->dev_private; 1323 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1324 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1325 u32 offset; 1326 1327 if (!dig || !dig->afmt || !dig->afmt->pin) 1328 return; 1329 1330 offset = dig->afmt->offset; 1331 1332 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, 1333 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT)); 1334 } 1335 1336 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, 1337 struct drm_display_mode *mode) 1338 { 1339 struct amdgpu_device *adev = encoder->dev->dev_private; 1340 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1341 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1342 struct drm_connector *connector; 1343 struct amdgpu_connector *amdgpu_connector = NULL; 1344 u32 tmp = 0, offset; 1345 1346 if (!dig || !dig->afmt || !dig->afmt->pin) 1347 return; 1348 1349 offset = dig->afmt->pin->offset; 1350 1351 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1352 if (connector->encoder == encoder) { 1353 amdgpu_connector = to_amdgpu_connector(connector); 1354 break; 1355 } 1356 } 1357 1358 if (!amdgpu_connector) { 1359 DRM_ERROR("Couldn't find encoder's connector\n"); 1360 return; 1361 } 1362 1363 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1364 if (connector->latency_present[1]) 1365 tmp = 1366 (connector->video_latency[1] << 1367 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1368 (connector->audio_latency[1] << 1369 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1370 else 1371 tmp = 1372 (0 << 1373 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1374 (0 << 1375 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1376 } else { 1377 if (connector->latency_present[0]) 1378 tmp = 1379 (connector->video_latency[0] << 1380 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1381 (connector->audio_latency[0] << 1382 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1383 else 1384 tmp = 1385 (0 << 1386 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1387 (0 << 1388 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1389 1390 } 1391 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1392 } 1393 1394 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1395 { 1396 struct amdgpu_device *adev = encoder->dev->dev_private; 1397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1398 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1399 struct drm_connector *connector; 1400 struct amdgpu_connector *amdgpu_connector = NULL; 1401 u32 offset, tmp; 1402 u8 *sadb = NULL; 1403 int sad_count; 1404 1405 if (!dig || !dig->afmt || !dig->afmt->pin) 1406 return; 1407 1408 offset = dig->afmt->pin->offset; 1409 1410 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1411 if (connector->encoder == encoder) { 1412 amdgpu_connector = to_amdgpu_connector(connector); 1413 break; 1414 } 1415 } 1416 1417 if (!amdgpu_connector) { 1418 DRM_ERROR("Couldn't find encoder's connector\n"); 1419 return; 1420 } 1421 1422 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1423 if (sad_count < 0) { 1424 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1425 sad_count = 0; 1426 } 1427 1428 /* program the speaker allocation */ 1429 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1430 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK | 1431 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK); 1432 /* set HDMI mode */ 1433 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK; 1434 if (sad_count) 1435 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); 1436 else 1437 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */ 1438 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1439 1440 kfree(sadb); 1441 } 1442 1443 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) 1444 { 1445 struct amdgpu_device *adev = encoder->dev->dev_private; 1446 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1447 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1448 u32 offset; 1449 struct drm_connector *connector; 1450 struct amdgpu_connector *amdgpu_connector = NULL; 1451 struct cea_sad *sads; 1452 int i, sad_count; 1453 1454 static const u16 eld_reg_to_type[][2] = { 1455 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1456 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1457 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1458 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1459 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1460 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1461 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1462 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1463 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1464 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1465 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1466 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1467 }; 1468 1469 if (!dig || !dig->afmt || !dig->afmt->pin) 1470 return; 1471 1472 offset = dig->afmt->pin->offset; 1473 1474 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1475 if (connector->encoder == encoder) { 1476 amdgpu_connector = to_amdgpu_connector(connector); 1477 break; 1478 } 1479 } 1480 1481 if (!amdgpu_connector) { 1482 DRM_ERROR("Couldn't find encoder's connector\n"); 1483 return; 1484 } 1485 1486 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1487 if (sad_count <= 0) { 1488 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1489 return; 1490 } 1491 BUG_ON(!sads); 1492 1493 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1494 u32 value = 0; 1495 u8 stereo_freqs = 0; 1496 int max_channels = -1; 1497 int j; 1498 1499 for (j = 0; j < sad_count; j++) { 1500 struct cea_sad *sad = &sads[j]; 1501 1502 if (sad->format == eld_reg_to_type[i][1]) { 1503 if (sad->channels > max_channels) { 1504 value = (sad->channels << 1505 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1506 (sad->byte2 << 1507 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1508 (sad->freq << 1509 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1510 max_channels = sad->channels; 1511 } 1512 1513 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1514 stereo_freqs |= sad->freq; 1515 else 1516 break; 1517 } 1518 } 1519 1520 value |= (stereo_freqs << 1521 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1522 1523 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1524 } 1525 1526 kfree(sads); 1527 } 1528 1529 static void dce_v8_0_audio_enable(struct amdgpu_device *adev, 1530 struct amdgpu_audio_pin *pin, 1531 bool enable) 1532 { 1533 if (!pin) 1534 return; 1535 1536 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1537 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1538 } 1539 1540 static const u32 pin_offsets[7] = 1541 { 1542 (0x1780 - 0x1780), 1543 (0x1786 - 0x1780), 1544 (0x178c - 0x1780), 1545 (0x1792 - 0x1780), 1546 (0x1798 - 0x1780), 1547 (0x179d - 0x1780), 1548 (0x17a4 - 0x1780), 1549 }; 1550 1551 static int dce_v8_0_audio_init(struct amdgpu_device *adev) 1552 { 1553 int i; 1554 1555 if (!amdgpu_audio) 1556 return 0; 1557 1558 adev->mode_info.audio.enabled = true; 1559 1560 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ 1561 adev->mode_info.audio.num_pins = 7; 1562 else if ((adev->asic_type == CHIP_KABINI) || 1563 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ 1564 adev->mode_info.audio.num_pins = 3; 1565 else if ((adev->asic_type == CHIP_BONAIRE) || 1566 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ 1567 adev->mode_info.audio.num_pins = 7; 1568 else 1569 adev->mode_info.audio.num_pins = 3; 1570 1571 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1572 adev->mode_info.audio.pin[i].channels = -1; 1573 adev->mode_info.audio.pin[i].rate = -1; 1574 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1575 adev->mode_info.audio.pin[i].status_bits = 0; 1576 adev->mode_info.audio.pin[i].category_code = 0; 1577 adev->mode_info.audio.pin[i].connected = false; 1578 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1579 adev->mode_info.audio.pin[i].id = i; 1580 /* disable audio. it will be set up later */ 1581 /* XXX remove once we switch to ip funcs */ 1582 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1583 } 1584 1585 return 0; 1586 } 1587 1588 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) 1589 { 1590 int i; 1591 1592 if (!amdgpu_audio) 1593 return; 1594 1595 if (!adev->mode_info.audio.enabled) 1596 return; 1597 1598 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1599 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1600 1601 adev->mode_info.audio.enabled = false; 1602 } 1603 1604 /* 1605 * update the N and CTS parameters for a given pixel clock rate 1606 */ 1607 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1608 { 1609 struct drm_device *dev = encoder->dev; 1610 struct amdgpu_device *adev = dev->dev_private; 1611 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1613 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1614 uint32_t offset = dig->afmt->offset; 1615 1616 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1617 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); 1618 1619 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1620 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); 1621 1622 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); 1623 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); 1624 } 1625 1626 /* 1627 * build a HDMI Video Info Frame 1628 */ 1629 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1630 void *buffer, size_t size) 1631 { 1632 struct drm_device *dev = encoder->dev; 1633 struct amdgpu_device *adev = dev->dev_private; 1634 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1635 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1636 uint32_t offset = dig->afmt->offset; 1637 uint8_t *frame = buffer + 3; 1638 uint8_t *header = buffer; 1639 1640 WREG32(mmAFMT_AVI_INFO0 + offset, 1641 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1642 WREG32(mmAFMT_AVI_INFO1 + offset, 1643 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1644 WREG32(mmAFMT_AVI_INFO2 + offset, 1645 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1646 WREG32(mmAFMT_AVI_INFO3 + offset, 1647 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1648 } 1649 1650 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1651 { 1652 struct drm_device *dev = encoder->dev; 1653 struct amdgpu_device *adev = dev->dev_private; 1654 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1655 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1657 u32 dto_phase = 24 * 1000; 1658 u32 dto_modulo = clock; 1659 1660 if (!dig || !dig->afmt) 1661 return; 1662 1663 /* XXX two dtos; generally use dto0 for hdmi */ 1664 /* Express [24MHz / target pixel clock] as an exact rational 1665 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1666 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1667 */ 1668 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); 1669 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1670 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1671 } 1672 1673 /* 1674 * update the info frames with the data from the current display mode 1675 */ 1676 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, 1677 struct drm_display_mode *mode) 1678 { 1679 struct drm_device *dev = encoder->dev; 1680 struct amdgpu_device *adev = dev->dev_private; 1681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1682 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1683 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1684 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1685 struct hdmi_avi_infoframe frame; 1686 uint32_t offset, val; 1687 ssize_t err; 1688 int bpc = 8; 1689 1690 if (!dig || !dig->afmt) 1691 return; 1692 1693 /* Silent, r600_hdmi_enable will raise WARN for us */ 1694 if (!dig->afmt->enabled) 1695 return; 1696 offset = dig->afmt->offset; 1697 1698 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1699 if (encoder->crtc) { 1700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1701 bpc = amdgpu_crtc->bpc; 1702 } 1703 1704 /* disable audio prior to setting up hw */ 1705 dig->afmt->pin = dce_v8_0_audio_get_pin(adev); 1706 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1707 1708 dce_v8_0_audio_set_dto(encoder, mode->clock); 1709 1710 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1711 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */ 1712 1713 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 1714 1715 val = RREG32(mmHDMI_CONTROL + offset); 1716 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1717 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; 1718 1719 switch (bpc) { 1720 case 0: 1721 case 6: 1722 case 8: 1723 case 16: 1724 default: 1725 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1726 connector->name, bpc); 1727 break; 1728 case 10: 1729 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1730 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1731 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1732 connector->name); 1733 break; 1734 case 12: 1735 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1736 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1737 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1738 connector->name); 1739 break; 1740 } 1741 1742 WREG32(mmHDMI_CONTROL + offset, val); 1743 1744 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1745 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */ 1746 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */ 1747 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */ 1748 1749 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, 1750 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */ 1751 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */ 1752 1753 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, 1754 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */ 1755 1756 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, 1757 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */ 1758 1759 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 1760 1761 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, 1762 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */ 1763 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */ 1764 1765 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1766 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */ 1767 1768 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 1769 1770 if (bpc > 8) 1771 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1772 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1773 else 1774 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1775 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */ 1776 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1777 1778 dce_v8_0_afmt_update_ACR(encoder, mode->clock); 1779 1780 WREG32(mmAFMT_60958_0 + offset, 1781 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT)); 1782 1783 WREG32(mmAFMT_60958_1 + offset, 1784 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT)); 1785 1786 WREG32(mmAFMT_60958_2 + offset, 1787 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) | 1788 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) | 1789 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) | 1790 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) | 1791 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) | 1792 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT)); 1793 1794 dce_v8_0_audio_write_speaker_allocation(encoder); 1795 1796 1797 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, 1798 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1799 1800 dce_v8_0_afmt_audio_select_pin(encoder); 1801 dce_v8_0_audio_write_sad_regs(encoder); 1802 dce_v8_0_audio_write_latency_fields(encoder, mode); 1803 1804 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1805 if (err < 0) { 1806 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1807 return; 1808 } 1809 1810 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1811 if (err < 0) { 1812 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1813 return; 1814 } 1815 1816 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1817 1818 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, 1819 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ 1820 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */ 1821 1822 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, 1823 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ 1824 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK); 1825 1826 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1827 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ 1828 1829 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 1830 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 1831 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 1832 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); 1833 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); 1834 1835 /* enable audio after to setting up hw */ 1836 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); 1837 } 1838 1839 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1840 { 1841 struct drm_device *dev = encoder->dev; 1842 struct amdgpu_device *adev = dev->dev_private; 1843 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1844 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1845 1846 if (!dig || !dig->afmt) 1847 return; 1848 1849 /* Silent, r600_hdmi_enable will raise WARN for us */ 1850 if (enable && dig->afmt->enabled) 1851 return; 1852 if (!enable && !dig->afmt->enabled) 1853 return; 1854 1855 if (!enable && dig->afmt->pin) { 1856 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1857 dig->afmt->pin = NULL; 1858 } 1859 1860 dig->afmt->enabled = enable; 1861 1862 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1863 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1864 } 1865 1866 static int dce_v8_0_afmt_init(struct amdgpu_device *adev) 1867 { 1868 int i; 1869 1870 for (i = 0; i < adev->mode_info.num_dig; i++) 1871 adev->mode_info.afmt[i] = NULL; 1872 1873 /* DCE8 has audio blocks tied to DIG encoders */ 1874 for (i = 0; i < adev->mode_info.num_dig; i++) { 1875 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1876 if (adev->mode_info.afmt[i]) { 1877 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1878 adev->mode_info.afmt[i]->id = i; 1879 } else { 1880 int j; 1881 for (j = 0; j < i; j++) { 1882 kfree(adev->mode_info.afmt[j]); 1883 adev->mode_info.afmt[j] = NULL; 1884 } 1885 return -ENOMEM; 1886 } 1887 } 1888 return 0; 1889 } 1890 1891 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) 1892 { 1893 int i; 1894 1895 for (i = 0; i < adev->mode_info.num_dig; i++) { 1896 kfree(adev->mode_info.afmt[i]); 1897 adev->mode_info.afmt[i] = NULL; 1898 } 1899 } 1900 1901 static const u32 vga_control_regs[6] = 1902 { 1903 mmD1VGA_CONTROL, 1904 mmD2VGA_CONTROL, 1905 mmD3VGA_CONTROL, 1906 mmD4VGA_CONTROL, 1907 mmD5VGA_CONTROL, 1908 mmD6VGA_CONTROL, 1909 }; 1910 1911 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) 1912 { 1913 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1914 struct drm_device *dev = crtc->dev; 1915 struct amdgpu_device *adev = dev->dev_private; 1916 u32 vga_control; 1917 1918 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1919 if (enable) 1920 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1921 else 1922 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1923 } 1924 1925 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) 1926 { 1927 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1928 struct drm_device *dev = crtc->dev; 1929 struct amdgpu_device *adev = dev->dev_private; 1930 1931 if (enable) 1932 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1933 else 1934 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1935 } 1936 1937 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 1938 struct drm_framebuffer *fb, 1939 int x, int y, int atomic) 1940 { 1941 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1942 struct drm_device *dev = crtc->dev; 1943 struct amdgpu_device *adev = dev->dev_private; 1944 struct amdgpu_framebuffer *amdgpu_fb; 1945 struct drm_framebuffer *target_fb; 1946 struct drm_gem_object *obj; 1947 struct amdgpu_bo *rbo; 1948 uint64_t fb_location, tiling_flags; 1949 uint32_t fb_format, fb_pitch_pixels; 1950 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1951 u32 pipe_config; 1952 u32 viewport_w, viewport_h; 1953 int r; 1954 bool bypass_lut = false; 1955 1956 /* no fb bound */ 1957 if (!atomic && !crtc->primary->fb) { 1958 DRM_DEBUG_KMS("No FB bound\n"); 1959 return 0; 1960 } 1961 1962 if (atomic) { 1963 amdgpu_fb = to_amdgpu_framebuffer(fb); 1964 target_fb = fb; 1965 } else { 1966 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 1967 target_fb = crtc->primary->fb; 1968 } 1969 1970 /* If atomic, assume fb object is pinned & idle & fenced and 1971 * just update base pointers 1972 */ 1973 obj = amdgpu_fb->obj; 1974 rbo = gem_to_amdgpu_bo(obj); 1975 r = amdgpu_bo_reserve(rbo, false); 1976 if (unlikely(r != 0)) 1977 return r; 1978 1979 if (atomic) { 1980 fb_location = amdgpu_bo_gpu_offset(rbo); 1981 } else { 1982 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1983 if (unlikely(r != 0)) { 1984 amdgpu_bo_unreserve(rbo); 1985 return -EINVAL; 1986 } 1987 } 1988 1989 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 1990 amdgpu_bo_unreserve(rbo); 1991 1992 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1993 1994 switch (target_fb->pixel_format) { 1995 case DRM_FORMAT_C8: 1996 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1997 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1998 break; 1999 case DRM_FORMAT_XRGB4444: 2000 case DRM_FORMAT_ARGB4444: 2001 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2002 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2003 #ifdef __BIG_ENDIAN 2004 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2005 #endif 2006 break; 2007 case DRM_FORMAT_XRGB1555: 2008 case DRM_FORMAT_ARGB1555: 2009 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2010 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2011 #ifdef __BIG_ENDIAN 2012 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2013 #endif 2014 break; 2015 case DRM_FORMAT_BGRX5551: 2016 case DRM_FORMAT_BGRA5551: 2017 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2018 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2019 #ifdef __BIG_ENDIAN 2020 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2021 #endif 2022 break; 2023 case DRM_FORMAT_RGB565: 2024 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2025 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2026 #ifdef __BIG_ENDIAN 2027 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2028 #endif 2029 break; 2030 case DRM_FORMAT_XRGB8888: 2031 case DRM_FORMAT_ARGB8888: 2032 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2033 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2034 #ifdef __BIG_ENDIAN 2035 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2036 #endif 2037 break; 2038 case DRM_FORMAT_XRGB2101010: 2039 case DRM_FORMAT_ARGB2101010: 2040 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2041 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2042 #ifdef __BIG_ENDIAN 2043 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2044 #endif 2045 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2046 bypass_lut = true; 2047 break; 2048 case DRM_FORMAT_BGRX1010102: 2049 case DRM_FORMAT_BGRA1010102: 2050 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2051 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2052 #ifdef __BIG_ENDIAN 2053 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2054 #endif 2055 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2056 bypass_lut = true; 2057 break; 2058 default: 2059 DRM_ERROR("Unsupported screen format %s\n", 2060 drm_get_format_name(target_fb->pixel_format)); 2061 return -EINVAL; 2062 } 2063 2064 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2065 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2066 2067 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2068 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2069 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2070 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2071 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2072 2073 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 2074 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2075 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 2076 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 2077 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 2078 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 2079 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); 2080 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2081 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2082 } 2083 2084 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 2085 2086 dce_v8_0_vga_enable(crtc, false); 2087 2088 /* Make sure surface address is updated at vertical blank rather than 2089 * horizontal blank 2090 */ 2091 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2092 2093 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2094 upper_32_bits(fb_location)); 2095 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2096 upper_32_bits(fb_location)); 2097 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2098 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2099 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2100 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2101 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2102 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2103 2104 /* 2105 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2106 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2107 * retain the full precision throughout the pipeline. 2108 */ 2109 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 2110 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0), 2111 ~LUT_10BIT_BYPASS_EN); 2112 2113 if (bypass_lut) 2114 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2115 2116 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2117 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2118 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2119 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2120 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2121 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2122 2123 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2124 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2125 2126 dce_v8_0_grph_enable(crtc, true); 2127 2128 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2129 target_fb->height); 2130 2131 x &= ~3; 2132 y &= ~1; 2133 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2134 (x << 16) | y); 2135 viewport_w = crtc->mode.hdisplay; 2136 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2137 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2138 (viewport_w << 16) | viewport_h); 2139 2140 /* set pageflip to happen only at start of vblank interval (front porch) */ 2141 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2142 2143 if (!atomic && fb && fb != crtc->primary->fb) { 2144 amdgpu_fb = to_amdgpu_framebuffer(fb); 2145 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2146 r = amdgpu_bo_reserve(rbo, false); 2147 if (unlikely(r != 0)) 2148 return r; 2149 amdgpu_bo_unpin(rbo); 2150 amdgpu_bo_unreserve(rbo); 2151 } 2152 2153 /* Bytes per pixel may have changed */ 2154 dce_v8_0_bandwidth_update(adev); 2155 2156 return 0; 2157 } 2158 2159 static void dce_v8_0_set_interleave(struct drm_crtc *crtc, 2160 struct drm_display_mode *mode) 2161 { 2162 struct drm_device *dev = crtc->dev; 2163 struct amdgpu_device *adev = dev->dev_private; 2164 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2165 2166 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2167 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 2168 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT); 2169 else 2170 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2171 } 2172 2173 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) 2174 { 2175 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2176 struct drm_device *dev = crtc->dev; 2177 struct amdgpu_device *adev = dev->dev_private; 2178 int i; 2179 2180 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2181 2182 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2183 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2184 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2185 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2186 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2187 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2188 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2189 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2190 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2191 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2192 2193 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2194 2195 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2196 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2197 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2198 2199 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2200 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2201 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2202 2203 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2204 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2205 2206 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2207 for (i = 0; i < 256; i++) { 2208 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2209 (amdgpu_crtc->lut_r[i] << 20) | 2210 (amdgpu_crtc->lut_g[i] << 10) | 2211 (amdgpu_crtc->lut_b[i] << 0)); 2212 } 2213 2214 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2215 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2216 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2217 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2218 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2219 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2220 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2221 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2222 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2223 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2224 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2225 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2226 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2227 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2228 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2229 /* XXX this only needs to be programmed once per crtc at startup, 2230 * not sure where the best place for it is 2231 */ 2232 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, 2233 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK); 2234 } 2235 2236 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) 2237 { 2238 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2239 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2240 2241 switch (amdgpu_encoder->encoder_id) { 2242 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2243 if (dig->linkb) 2244 return 1; 2245 else 2246 return 0; 2247 break; 2248 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2249 if (dig->linkb) 2250 return 3; 2251 else 2252 return 2; 2253 break; 2254 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2255 if (dig->linkb) 2256 return 5; 2257 else 2258 return 4; 2259 break; 2260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2261 return 6; 2262 break; 2263 default: 2264 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2265 return 0; 2266 } 2267 } 2268 2269 /** 2270 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc. 2271 * 2272 * @crtc: drm crtc 2273 * 2274 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2275 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2276 * monitors a dedicated PPLL must be used. If a particular board has 2277 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2278 * as there is no need to program the PLL itself. If we are not able to 2279 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2280 * avoid messing up an existing monitor. 2281 * 2282 * Asic specific PLL information 2283 * 2284 * DCE 8.x 2285 * KB/KV 2286 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2287 * CI 2288 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2289 * 2290 */ 2291 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc) 2292 { 2293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2294 struct drm_device *dev = crtc->dev; 2295 struct amdgpu_device *adev = dev->dev_private; 2296 u32 pll_in_use; 2297 int pll; 2298 2299 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2300 if (adev->clock.dp_extclk) 2301 /* skip PPLL programming if using ext clock */ 2302 return ATOM_PPLL_INVALID; 2303 else { 2304 /* use the same PPLL for all DP monitors */ 2305 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2306 if (pll != ATOM_PPLL_INVALID) 2307 return pll; 2308 } 2309 } else { 2310 /* use the same PPLL for all monitors with the same clock */ 2311 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2312 if (pll != ATOM_PPLL_INVALID) 2313 return pll; 2314 } 2315 /* otherwise, pick one of the plls */ 2316 if ((adev->asic_type == CHIP_KABINI) || 2317 (adev->asic_type == CHIP_MULLINS)) { 2318 /* KB/ML has PPLL1 and PPLL2 */ 2319 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2320 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2321 return ATOM_PPLL2; 2322 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2323 return ATOM_PPLL1; 2324 DRM_ERROR("unable to allocate a PPLL\n"); 2325 return ATOM_PPLL_INVALID; 2326 } else { 2327 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 2328 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2329 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2330 return ATOM_PPLL2; 2331 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2332 return ATOM_PPLL1; 2333 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2334 return ATOM_PPLL0; 2335 DRM_ERROR("unable to allocate a PPLL\n"); 2336 return ATOM_PPLL_INVALID; 2337 } 2338 return ATOM_PPLL_INVALID; 2339 } 2340 2341 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2342 { 2343 struct amdgpu_device *adev = crtc->dev->dev_private; 2344 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2345 uint32_t cur_lock; 2346 2347 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2348 if (lock) 2349 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2350 else 2351 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2352 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2353 } 2354 2355 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) 2356 { 2357 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2358 struct amdgpu_device *adev = crtc->dev->dev_private; 2359 2360 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2361 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2362 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2363 } 2364 2365 static void dce_v8_0_show_cursor(struct drm_crtc *crtc) 2366 { 2367 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2368 struct amdgpu_device *adev = crtc->dev->dev_private; 2369 2370 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2371 upper_32_bits(amdgpu_crtc->cursor_addr)); 2372 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2373 lower_32_bits(amdgpu_crtc->cursor_addr)); 2374 2375 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2376 CUR_CONTROL__CURSOR_EN_MASK | 2377 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2378 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2379 } 2380 2381 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 2382 int x, int y) 2383 { 2384 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2385 struct amdgpu_device *adev = crtc->dev->dev_private; 2386 int xorigin = 0, yorigin = 0; 2387 2388 /* avivo cursor are offset into the total surface */ 2389 x += crtc->x; 2390 y += crtc->y; 2391 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2392 2393 if (x < 0) { 2394 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2395 x = 0; 2396 } 2397 if (y < 0) { 2398 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2399 y = 0; 2400 } 2401 2402 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2403 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2404 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2405 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2406 2407 amdgpu_crtc->cursor_x = x; 2408 amdgpu_crtc->cursor_y = y; 2409 2410 return 0; 2411 } 2412 2413 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, 2414 int x, int y) 2415 { 2416 int ret; 2417 2418 dce_v8_0_lock_cursor(crtc, true); 2419 ret = dce_v8_0_cursor_move_locked(crtc, x, y); 2420 dce_v8_0_lock_cursor(crtc, false); 2421 2422 return ret; 2423 } 2424 2425 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 2426 struct drm_file *file_priv, 2427 uint32_t handle, 2428 uint32_t width, 2429 uint32_t height, 2430 int32_t hot_x, 2431 int32_t hot_y) 2432 { 2433 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2434 struct drm_gem_object *obj; 2435 struct amdgpu_bo *aobj; 2436 int ret; 2437 2438 if (!handle) { 2439 /* turn off cursor */ 2440 dce_v8_0_hide_cursor(crtc); 2441 obj = NULL; 2442 goto unpin; 2443 } 2444 2445 if ((width > amdgpu_crtc->max_cursor_width) || 2446 (height > amdgpu_crtc->max_cursor_height)) { 2447 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2448 return -EINVAL; 2449 } 2450 2451 obj = drm_gem_object_lookup(file_priv, handle); 2452 if (!obj) { 2453 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2454 return -ENOENT; 2455 } 2456 2457 aobj = gem_to_amdgpu_bo(obj); 2458 ret = amdgpu_bo_reserve(aobj, false); 2459 if (ret != 0) { 2460 drm_gem_object_unreference_unlocked(obj); 2461 return ret; 2462 } 2463 2464 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2465 amdgpu_bo_unreserve(aobj); 2466 if (ret) { 2467 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2468 drm_gem_object_unreference_unlocked(obj); 2469 return ret; 2470 } 2471 2472 amdgpu_crtc->cursor_width = width; 2473 amdgpu_crtc->cursor_height = height; 2474 2475 dce_v8_0_lock_cursor(crtc, true); 2476 2477 if (hot_x != amdgpu_crtc->cursor_hot_x || 2478 hot_y != amdgpu_crtc->cursor_hot_y) { 2479 int x, y; 2480 2481 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2482 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2483 2484 dce_v8_0_cursor_move_locked(crtc, x, y); 2485 2486 amdgpu_crtc->cursor_hot_x = hot_x; 2487 amdgpu_crtc->cursor_hot_y = hot_y; 2488 } 2489 2490 dce_v8_0_show_cursor(crtc); 2491 dce_v8_0_lock_cursor(crtc, false); 2492 2493 unpin: 2494 if (amdgpu_crtc->cursor_bo) { 2495 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2496 ret = amdgpu_bo_reserve(aobj, false); 2497 if (likely(ret == 0)) { 2498 amdgpu_bo_unpin(aobj); 2499 amdgpu_bo_unreserve(aobj); 2500 } 2501 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2502 } 2503 2504 amdgpu_crtc->cursor_bo = obj; 2505 return 0; 2506 } 2507 2508 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 2509 { 2510 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2511 2512 if (amdgpu_crtc->cursor_bo) { 2513 dce_v8_0_lock_cursor(crtc, true); 2514 2515 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2516 amdgpu_crtc->cursor_y); 2517 2518 dce_v8_0_show_cursor(crtc); 2519 2520 dce_v8_0_lock_cursor(crtc, false); 2521 } 2522 } 2523 2524 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2525 u16 *blue, uint32_t size) 2526 { 2527 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2528 int i; 2529 2530 /* userspace palettes are always correct as is */ 2531 for (i = 0; i < size; i++) { 2532 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2533 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2534 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2535 } 2536 dce_v8_0_crtc_load_lut(crtc); 2537 2538 return 0; 2539 } 2540 2541 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) 2542 { 2543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2544 2545 drm_crtc_cleanup(crtc); 2546 kfree(amdgpu_crtc); 2547 } 2548 2549 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { 2550 .cursor_set2 = dce_v8_0_crtc_cursor_set2, 2551 .cursor_move = dce_v8_0_crtc_cursor_move, 2552 .gamma_set = dce_v8_0_crtc_gamma_set, 2553 .set_config = amdgpu_crtc_set_config, 2554 .destroy = dce_v8_0_crtc_destroy, 2555 .page_flip = amdgpu_crtc_page_flip, 2556 }; 2557 2558 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2559 { 2560 struct drm_device *dev = crtc->dev; 2561 struct amdgpu_device *adev = dev->dev_private; 2562 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2563 unsigned type; 2564 2565 switch (mode) { 2566 case DRM_MODE_DPMS_ON: 2567 amdgpu_crtc->enabled = true; 2568 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2569 dce_v8_0_vga_enable(crtc, true); 2570 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2571 dce_v8_0_vga_enable(crtc, false); 2572 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2573 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2574 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2575 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2576 drm_crtc_vblank_on(crtc); 2577 dce_v8_0_crtc_load_lut(crtc); 2578 break; 2579 case DRM_MODE_DPMS_STANDBY: 2580 case DRM_MODE_DPMS_SUSPEND: 2581 case DRM_MODE_DPMS_OFF: 2582 drm_crtc_vblank_off(crtc); 2583 if (amdgpu_crtc->enabled) { 2584 dce_v8_0_vga_enable(crtc, true); 2585 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2586 dce_v8_0_vga_enable(crtc, false); 2587 } 2588 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2589 amdgpu_crtc->enabled = false; 2590 break; 2591 } 2592 /* adjust pm to dpms */ 2593 amdgpu_pm_compute_clocks(adev); 2594 } 2595 2596 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc) 2597 { 2598 /* disable crtc pair power gating before programming */ 2599 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2600 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2601 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2602 } 2603 2604 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc) 2605 { 2606 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2607 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2608 } 2609 2610 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) 2611 { 2612 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2613 struct drm_device *dev = crtc->dev; 2614 struct amdgpu_device *adev = dev->dev_private; 2615 struct amdgpu_atom_ss ss; 2616 int i; 2617 2618 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2619 if (crtc->primary->fb) { 2620 int r; 2621 struct amdgpu_framebuffer *amdgpu_fb; 2622 struct amdgpu_bo *rbo; 2623 2624 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2625 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2626 r = amdgpu_bo_reserve(rbo, false); 2627 if (unlikely(r)) 2628 DRM_ERROR("failed to reserve rbo before unpin\n"); 2629 else { 2630 amdgpu_bo_unpin(rbo); 2631 amdgpu_bo_unreserve(rbo); 2632 } 2633 } 2634 /* disable the GRPH */ 2635 dce_v8_0_grph_enable(crtc, false); 2636 2637 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2638 2639 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2640 if (adev->mode_info.crtcs[i] && 2641 adev->mode_info.crtcs[i]->enabled && 2642 i != amdgpu_crtc->crtc_id && 2643 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2644 /* one other crtc is using this pll don't turn 2645 * off the pll 2646 */ 2647 goto done; 2648 } 2649 } 2650 2651 switch (amdgpu_crtc->pll_id) { 2652 case ATOM_PPLL1: 2653 case ATOM_PPLL2: 2654 /* disable the ppll */ 2655 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2656 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2657 break; 2658 case ATOM_PPLL0: 2659 /* disable the ppll */ 2660 if ((adev->asic_type == CHIP_KAVERI) || 2661 (adev->asic_type == CHIP_BONAIRE) || 2662 (adev->asic_type == CHIP_HAWAII)) 2663 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2664 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2665 break; 2666 default: 2667 break; 2668 } 2669 done: 2670 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2671 amdgpu_crtc->adjusted_clock = 0; 2672 amdgpu_crtc->encoder = NULL; 2673 amdgpu_crtc->connector = NULL; 2674 } 2675 2676 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, 2677 struct drm_display_mode *mode, 2678 struct drm_display_mode *adjusted_mode, 2679 int x, int y, struct drm_framebuffer *old_fb) 2680 { 2681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2682 2683 if (!amdgpu_crtc->adjusted_clock) 2684 return -EINVAL; 2685 2686 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2687 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2688 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2689 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2690 amdgpu_atombios_crtc_scaler_setup(crtc); 2691 dce_v8_0_cursor_reset(crtc); 2692 /* update the hw version fpr dpm */ 2693 amdgpu_crtc->hw_mode = *adjusted_mode; 2694 2695 return 0; 2696 } 2697 2698 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, 2699 const struct drm_display_mode *mode, 2700 struct drm_display_mode *adjusted_mode) 2701 { 2702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2703 struct drm_device *dev = crtc->dev; 2704 struct drm_encoder *encoder; 2705 2706 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2707 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2708 if (encoder->crtc == crtc) { 2709 amdgpu_crtc->encoder = encoder; 2710 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2711 break; 2712 } 2713 } 2714 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2715 amdgpu_crtc->encoder = NULL; 2716 amdgpu_crtc->connector = NULL; 2717 return false; 2718 } 2719 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2720 return false; 2721 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2722 return false; 2723 /* pick pll */ 2724 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc); 2725 /* if we can't get a PPLL for a non-DP encoder, fail */ 2726 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2727 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2728 return false; 2729 2730 return true; 2731 } 2732 2733 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2734 struct drm_framebuffer *old_fb) 2735 { 2736 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2737 } 2738 2739 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2740 struct drm_framebuffer *fb, 2741 int x, int y, enum mode_set_atomic state) 2742 { 2743 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); 2744 } 2745 2746 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { 2747 .dpms = dce_v8_0_crtc_dpms, 2748 .mode_fixup = dce_v8_0_crtc_mode_fixup, 2749 .mode_set = dce_v8_0_crtc_mode_set, 2750 .mode_set_base = dce_v8_0_crtc_set_base, 2751 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, 2752 .prepare = dce_v8_0_crtc_prepare, 2753 .commit = dce_v8_0_crtc_commit, 2754 .load_lut = dce_v8_0_crtc_load_lut, 2755 .disable = dce_v8_0_crtc_disable, 2756 }; 2757 2758 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) 2759 { 2760 struct amdgpu_crtc *amdgpu_crtc; 2761 int i; 2762 2763 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2764 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2765 if (amdgpu_crtc == NULL) 2766 return -ENOMEM; 2767 2768 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); 2769 2770 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2771 amdgpu_crtc->crtc_id = index; 2772 adev->mode_info.crtcs[index] = amdgpu_crtc; 2773 2774 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 2775 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 2776 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2777 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2778 2779 for (i = 0; i < 256; i++) { 2780 amdgpu_crtc->lut_r[i] = i << 2; 2781 amdgpu_crtc->lut_g[i] = i << 2; 2782 amdgpu_crtc->lut_b[i] = i << 2; 2783 } 2784 2785 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2786 2787 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2788 amdgpu_crtc->adjusted_clock = 0; 2789 amdgpu_crtc->encoder = NULL; 2790 amdgpu_crtc->connector = NULL; 2791 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); 2792 2793 return 0; 2794 } 2795 2796 static int dce_v8_0_early_init(void *handle) 2797 { 2798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2799 2800 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2801 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2802 2803 dce_v8_0_set_display_funcs(adev); 2804 dce_v8_0_set_irq_funcs(adev); 2805 2806 switch (adev->asic_type) { 2807 case CHIP_BONAIRE: 2808 case CHIP_HAWAII: 2809 adev->mode_info.num_crtc = 6; 2810 adev->mode_info.num_hpd = 6; 2811 adev->mode_info.num_dig = 6; 2812 break; 2813 case CHIP_KAVERI: 2814 adev->mode_info.num_crtc = 4; 2815 adev->mode_info.num_hpd = 6; 2816 adev->mode_info.num_dig = 7; 2817 break; 2818 case CHIP_KABINI: 2819 case CHIP_MULLINS: 2820 adev->mode_info.num_crtc = 2; 2821 adev->mode_info.num_hpd = 6; 2822 adev->mode_info.num_dig = 6; /* ? */ 2823 break; 2824 default: 2825 /* FIXME: not supported yet */ 2826 return -EINVAL; 2827 } 2828 2829 return 0; 2830 } 2831 2832 static int dce_v8_0_sw_init(void *handle) 2833 { 2834 int r, i; 2835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2836 2837 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2838 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2839 if (r) 2840 return r; 2841 } 2842 2843 for (i = 8; i < 20; i += 2) { 2844 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2845 if (r) 2846 return r; 2847 } 2848 2849 /* HPD hotplug */ 2850 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2851 if (r) 2852 return r; 2853 2854 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2855 2856 adev->ddev->mode_config.async_page_flip = true; 2857 2858 adev->ddev->mode_config.max_width = 16384; 2859 adev->ddev->mode_config.max_height = 16384; 2860 2861 adev->ddev->mode_config.preferred_depth = 24; 2862 adev->ddev->mode_config.prefer_shadow = 1; 2863 2864 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2865 2866 r = amdgpu_modeset_create_props(adev); 2867 if (r) 2868 return r; 2869 2870 adev->ddev->mode_config.max_width = 16384; 2871 adev->ddev->mode_config.max_height = 16384; 2872 2873 /* allocate crtcs */ 2874 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2875 r = dce_v8_0_crtc_init(adev, i); 2876 if (r) 2877 return r; 2878 } 2879 2880 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2881 amdgpu_print_display_setup(adev->ddev); 2882 else 2883 return -EINVAL; 2884 2885 /* setup afmt */ 2886 r = dce_v8_0_afmt_init(adev); 2887 if (r) 2888 return r; 2889 2890 r = dce_v8_0_audio_init(adev); 2891 if (r) 2892 return r; 2893 2894 drm_kms_helper_poll_init(adev->ddev); 2895 2896 adev->mode_info.mode_config_initialized = true; 2897 return 0; 2898 } 2899 2900 static int dce_v8_0_sw_fini(void *handle) 2901 { 2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2903 2904 kfree(adev->mode_info.bios_hardcoded_edid); 2905 2906 drm_kms_helper_poll_fini(adev->ddev); 2907 2908 dce_v8_0_audio_fini(adev); 2909 2910 dce_v8_0_afmt_fini(adev); 2911 2912 drm_mode_config_cleanup(adev->ddev); 2913 adev->mode_info.mode_config_initialized = false; 2914 2915 return 0; 2916 } 2917 2918 static int dce_v8_0_hw_init(void *handle) 2919 { 2920 int i; 2921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2922 2923 /* init dig PHYs, disp eng pll */ 2924 amdgpu_atombios_encoder_init_dig(adev); 2925 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2926 2927 /* initialize hpd */ 2928 dce_v8_0_hpd_init(adev); 2929 2930 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2931 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2932 } 2933 2934 dce_v8_0_pageflip_interrupt_init(adev); 2935 2936 return 0; 2937 } 2938 2939 static int dce_v8_0_hw_fini(void *handle) 2940 { 2941 int i; 2942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2943 2944 dce_v8_0_hpd_fini(adev); 2945 2946 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2947 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2948 } 2949 2950 dce_v8_0_pageflip_interrupt_fini(adev); 2951 2952 return 0; 2953 } 2954 2955 static int dce_v8_0_suspend(void *handle) 2956 { 2957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2958 2959 amdgpu_atombios_scratch_regs_save(adev); 2960 2961 return dce_v8_0_hw_fini(handle); 2962 } 2963 2964 static int dce_v8_0_resume(void *handle) 2965 { 2966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2967 int ret; 2968 2969 ret = dce_v8_0_hw_init(handle); 2970 2971 amdgpu_atombios_scratch_regs_restore(adev); 2972 2973 /* turn on the BL */ 2974 if (adev->mode_info.bl_encoder) { 2975 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2976 adev->mode_info.bl_encoder); 2977 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2978 bl_level); 2979 } 2980 2981 return ret; 2982 } 2983 2984 static bool dce_v8_0_is_idle(void *handle) 2985 { 2986 return true; 2987 } 2988 2989 static int dce_v8_0_wait_for_idle(void *handle) 2990 { 2991 return 0; 2992 } 2993 2994 static int dce_v8_0_soft_reset(void *handle) 2995 { 2996 u32 srbm_soft_reset = 0, tmp; 2997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2998 2999 if (dce_v8_0_is_display_hung(adev)) 3000 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3001 3002 if (srbm_soft_reset) { 3003 tmp = RREG32(mmSRBM_SOFT_RESET); 3004 tmp |= srbm_soft_reset; 3005 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3006 WREG32(mmSRBM_SOFT_RESET, tmp); 3007 tmp = RREG32(mmSRBM_SOFT_RESET); 3008 3009 udelay(50); 3010 3011 tmp &= ~srbm_soft_reset; 3012 WREG32(mmSRBM_SOFT_RESET, tmp); 3013 tmp = RREG32(mmSRBM_SOFT_RESET); 3014 3015 /* Wait a little for things to settle down */ 3016 udelay(50); 3017 } 3018 return 0; 3019 } 3020 3021 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3022 int crtc, 3023 enum amdgpu_interrupt_state state) 3024 { 3025 u32 reg_block, lb_interrupt_mask; 3026 3027 if (crtc >= adev->mode_info.num_crtc) { 3028 DRM_DEBUG("invalid crtc %d\n", crtc); 3029 return; 3030 } 3031 3032 switch (crtc) { 3033 case 0: 3034 reg_block = CRTC0_REGISTER_OFFSET; 3035 break; 3036 case 1: 3037 reg_block = CRTC1_REGISTER_OFFSET; 3038 break; 3039 case 2: 3040 reg_block = CRTC2_REGISTER_OFFSET; 3041 break; 3042 case 3: 3043 reg_block = CRTC3_REGISTER_OFFSET; 3044 break; 3045 case 4: 3046 reg_block = CRTC4_REGISTER_OFFSET; 3047 break; 3048 case 5: 3049 reg_block = CRTC5_REGISTER_OFFSET; 3050 break; 3051 default: 3052 DRM_DEBUG("invalid crtc %d\n", crtc); 3053 return; 3054 } 3055 3056 switch (state) { 3057 case AMDGPU_IRQ_STATE_DISABLE: 3058 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3059 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3060 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3061 break; 3062 case AMDGPU_IRQ_STATE_ENABLE: 3063 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3064 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3065 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3066 break; 3067 default: 3068 break; 3069 } 3070 } 3071 3072 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3073 int crtc, 3074 enum amdgpu_interrupt_state state) 3075 { 3076 u32 reg_block, lb_interrupt_mask; 3077 3078 if (crtc >= adev->mode_info.num_crtc) { 3079 DRM_DEBUG("invalid crtc %d\n", crtc); 3080 return; 3081 } 3082 3083 switch (crtc) { 3084 case 0: 3085 reg_block = CRTC0_REGISTER_OFFSET; 3086 break; 3087 case 1: 3088 reg_block = CRTC1_REGISTER_OFFSET; 3089 break; 3090 case 2: 3091 reg_block = CRTC2_REGISTER_OFFSET; 3092 break; 3093 case 3: 3094 reg_block = CRTC3_REGISTER_OFFSET; 3095 break; 3096 case 4: 3097 reg_block = CRTC4_REGISTER_OFFSET; 3098 break; 3099 case 5: 3100 reg_block = CRTC5_REGISTER_OFFSET; 3101 break; 3102 default: 3103 DRM_DEBUG("invalid crtc %d\n", crtc); 3104 return; 3105 } 3106 3107 switch (state) { 3108 case AMDGPU_IRQ_STATE_DISABLE: 3109 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3110 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3111 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3112 break; 3113 case AMDGPU_IRQ_STATE_ENABLE: 3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3115 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3116 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3117 break; 3118 default: 3119 break; 3120 } 3121 } 3122 3123 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3124 struct amdgpu_irq_src *src, 3125 unsigned type, 3126 enum amdgpu_interrupt_state state) 3127 { 3128 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 3129 3130 switch (type) { 3131 case AMDGPU_HPD_1: 3132 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 3133 break; 3134 case AMDGPU_HPD_2: 3135 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 3136 break; 3137 case AMDGPU_HPD_3: 3138 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 3139 break; 3140 case AMDGPU_HPD_4: 3141 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 3142 break; 3143 case AMDGPU_HPD_5: 3144 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 3145 break; 3146 case AMDGPU_HPD_6: 3147 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 3148 break; 3149 default: 3150 DRM_DEBUG("invalid hdp %d\n", type); 3151 return 0; 3152 } 3153 3154 switch (state) { 3155 case AMDGPU_IRQ_STATE_DISABLE: 3156 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3157 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3158 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3159 break; 3160 case AMDGPU_IRQ_STATE_ENABLE: 3161 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3162 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3163 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3164 break; 3165 default: 3166 break; 3167 } 3168 3169 return 0; 3170 } 3171 3172 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3173 struct amdgpu_irq_src *src, 3174 unsigned type, 3175 enum amdgpu_interrupt_state state) 3176 { 3177 switch (type) { 3178 case AMDGPU_CRTC_IRQ_VBLANK1: 3179 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3180 break; 3181 case AMDGPU_CRTC_IRQ_VBLANK2: 3182 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3183 break; 3184 case AMDGPU_CRTC_IRQ_VBLANK3: 3185 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3186 break; 3187 case AMDGPU_CRTC_IRQ_VBLANK4: 3188 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3189 break; 3190 case AMDGPU_CRTC_IRQ_VBLANK5: 3191 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3192 break; 3193 case AMDGPU_CRTC_IRQ_VBLANK6: 3194 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3195 break; 3196 case AMDGPU_CRTC_IRQ_VLINE1: 3197 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); 3198 break; 3199 case AMDGPU_CRTC_IRQ_VLINE2: 3200 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); 3201 break; 3202 case AMDGPU_CRTC_IRQ_VLINE3: 3203 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); 3204 break; 3205 case AMDGPU_CRTC_IRQ_VLINE4: 3206 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); 3207 break; 3208 case AMDGPU_CRTC_IRQ_VLINE5: 3209 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); 3210 break; 3211 case AMDGPU_CRTC_IRQ_VLINE6: 3212 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); 3213 break; 3214 default: 3215 break; 3216 } 3217 return 0; 3218 } 3219 3220 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 3221 struct amdgpu_irq_src *source, 3222 struct amdgpu_iv_entry *entry) 3223 { 3224 unsigned crtc = entry->src_id - 1; 3225 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3226 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3227 3228 switch (entry->src_data) { 3229 case 0: /* vblank */ 3230 if (disp_int & interrupt_status_offsets[crtc].vblank) 3231 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3232 else 3233 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3234 3235 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3236 drm_handle_vblank(adev->ddev, crtc); 3237 } 3238 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3239 3240 break; 3241 case 1: /* vline */ 3242 if (disp_int & interrupt_status_offsets[crtc].vline) 3243 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3244 else 3245 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3246 3247 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3248 3249 break; 3250 default: 3251 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3252 break; 3253 } 3254 3255 return 0; 3256 } 3257 3258 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3259 struct amdgpu_irq_src *src, 3260 unsigned type, 3261 enum amdgpu_interrupt_state state) 3262 { 3263 u32 reg; 3264 3265 if (type >= adev->mode_info.num_crtc) { 3266 DRM_ERROR("invalid pageflip crtc %d\n", type); 3267 return -EINVAL; 3268 } 3269 3270 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3271 if (state == AMDGPU_IRQ_STATE_DISABLE) 3272 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3273 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3274 else 3275 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3276 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3277 3278 return 0; 3279 } 3280 3281 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, 3282 struct amdgpu_irq_src *source, 3283 struct amdgpu_iv_entry *entry) 3284 { 3285 unsigned long flags; 3286 unsigned crtc_id; 3287 struct amdgpu_crtc *amdgpu_crtc; 3288 struct amdgpu_flip_work *works; 3289 3290 crtc_id = (entry->src_id - 8) >> 1; 3291 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3292 3293 if (crtc_id >= adev->mode_info.num_crtc) { 3294 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3295 return -EINVAL; 3296 } 3297 3298 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3299 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3300 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3301 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3302 3303 /* IRQ could occur when in initial stage */ 3304 if (amdgpu_crtc == NULL) 3305 return 0; 3306 3307 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3308 works = amdgpu_crtc->pflip_works; 3309 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3310 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3311 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3312 amdgpu_crtc->pflip_status, 3313 AMDGPU_FLIP_SUBMITTED); 3314 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3315 return 0; 3316 } 3317 3318 /* page flip completed. clean up */ 3319 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3320 amdgpu_crtc->pflip_works = NULL; 3321 3322 /* wakeup usersapce */ 3323 if (works->event) 3324 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3325 3326 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3327 3328 drm_crtc_vblank_put(&amdgpu_crtc->base); 3329 schedule_work(&works->unpin_work); 3330 3331 return 0; 3332 } 3333 3334 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, 3335 struct amdgpu_irq_src *source, 3336 struct amdgpu_iv_entry *entry) 3337 { 3338 uint32_t disp_int, mask, int_control, tmp; 3339 unsigned hpd; 3340 3341 if (entry->src_data >= adev->mode_info.num_hpd) { 3342 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3343 return 0; 3344 } 3345 3346 hpd = entry->src_data; 3347 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3348 mask = interrupt_status_offsets[hpd].hpd; 3349 int_control = hpd_int_control_offsets[hpd]; 3350 3351 if (disp_int & mask) { 3352 tmp = RREG32(int_control); 3353 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3354 WREG32(int_control, tmp); 3355 schedule_work(&adev->hotplug_work); 3356 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3357 } 3358 3359 return 0; 3360 3361 } 3362 3363 static int dce_v8_0_set_clockgating_state(void *handle, 3364 enum amd_clockgating_state state) 3365 { 3366 return 0; 3367 } 3368 3369 static int dce_v8_0_set_powergating_state(void *handle, 3370 enum amd_powergating_state state) 3371 { 3372 return 0; 3373 } 3374 3375 const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3376 .name = "dce_v8_0", 3377 .early_init = dce_v8_0_early_init, 3378 .late_init = NULL, 3379 .sw_init = dce_v8_0_sw_init, 3380 .sw_fini = dce_v8_0_sw_fini, 3381 .hw_init = dce_v8_0_hw_init, 3382 .hw_fini = dce_v8_0_hw_fini, 3383 .suspend = dce_v8_0_suspend, 3384 .resume = dce_v8_0_resume, 3385 .is_idle = dce_v8_0_is_idle, 3386 .wait_for_idle = dce_v8_0_wait_for_idle, 3387 .soft_reset = dce_v8_0_soft_reset, 3388 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3389 .set_powergating_state = dce_v8_0_set_powergating_state, 3390 }; 3391 3392 static void 3393 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder, 3394 struct drm_display_mode *mode, 3395 struct drm_display_mode *adjusted_mode) 3396 { 3397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3398 3399 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3400 3401 /* need to call this here rather than in prepare() since we need some crtc info */ 3402 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3403 3404 /* set scaler clears this on some chips */ 3405 dce_v8_0_set_interleave(encoder->crtc, mode); 3406 3407 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3408 dce_v8_0_afmt_enable(encoder, true); 3409 dce_v8_0_afmt_setmode(encoder, adjusted_mode); 3410 } 3411 } 3412 3413 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) 3414 { 3415 struct amdgpu_device *adev = encoder->dev->dev_private; 3416 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3417 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3418 3419 if ((amdgpu_encoder->active_device & 3420 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3421 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3422 ENCODER_OBJECT_ID_NONE)) { 3423 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3424 if (dig) { 3425 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); 3426 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3427 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3428 } 3429 } 3430 3431 amdgpu_atombios_scratch_regs_lock(adev, true); 3432 3433 if (connector) { 3434 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3435 3436 /* select the clock/data port if it uses a router */ 3437 if (amdgpu_connector->router.cd_valid) 3438 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3439 3440 /* turn eDP panel on for mode set */ 3441 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3442 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3443 ATOM_TRANSMITTER_ACTION_POWER_ON); 3444 } 3445 3446 /* this is needed for the pll/ss setup to work correctly in some cases */ 3447 amdgpu_atombios_encoder_set_crtc_source(encoder); 3448 /* set up the FMT blocks */ 3449 dce_v8_0_program_fmt(encoder); 3450 } 3451 3452 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder) 3453 { 3454 struct drm_device *dev = encoder->dev; 3455 struct amdgpu_device *adev = dev->dev_private; 3456 3457 /* need to call this here as we need the crtc set up */ 3458 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3459 amdgpu_atombios_scratch_regs_lock(adev, false); 3460 } 3461 3462 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder) 3463 { 3464 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3465 struct amdgpu_encoder_atom_dig *dig; 3466 3467 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3468 3469 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3470 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3471 dce_v8_0_afmt_enable(encoder, false); 3472 dig = amdgpu_encoder->enc_priv; 3473 dig->dig_encoder = -1; 3474 } 3475 amdgpu_encoder->active_device = 0; 3476 } 3477 3478 /* these are handled by the primary encoders */ 3479 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder) 3480 { 3481 3482 } 3483 3484 static void dce_v8_0_ext_commit(struct drm_encoder *encoder) 3485 { 3486 3487 } 3488 3489 static void 3490 dce_v8_0_ext_mode_set(struct drm_encoder *encoder, 3491 struct drm_display_mode *mode, 3492 struct drm_display_mode *adjusted_mode) 3493 { 3494 3495 } 3496 3497 static void dce_v8_0_ext_disable(struct drm_encoder *encoder) 3498 { 3499 3500 } 3501 3502 static void 3503 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode) 3504 { 3505 3506 } 3507 3508 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = { 3509 .dpms = dce_v8_0_ext_dpms, 3510 .prepare = dce_v8_0_ext_prepare, 3511 .mode_set = dce_v8_0_ext_mode_set, 3512 .commit = dce_v8_0_ext_commit, 3513 .disable = dce_v8_0_ext_disable, 3514 /* no detect for TMDS/LVDS yet */ 3515 }; 3516 3517 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = { 3518 .dpms = amdgpu_atombios_encoder_dpms, 3519 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3520 .prepare = dce_v8_0_encoder_prepare, 3521 .mode_set = dce_v8_0_encoder_mode_set, 3522 .commit = dce_v8_0_encoder_commit, 3523 .disable = dce_v8_0_encoder_disable, 3524 .detect = amdgpu_atombios_encoder_dig_detect, 3525 }; 3526 3527 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = { 3528 .dpms = amdgpu_atombios_encoder_dpms, 3529 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3530 .prepare = dce_v8_0_encoder_prepare, 3531 .mode_set = dce_v8_0_encoder_mode_set, 3532 .commit = dce_v8_0_encoder_commit, 3533 .detect = amdgpu_atombios_encoder_dac_detect, 3534 }; 3535 3536 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder) 3537 { 3538 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3539 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3540 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3541 kfree(amdgpu_encoder->enc_priv); 3542 drm_encoder_cleanup(encoder); 3543 kfree(amdgpu_encoder); 3544 } 3545 3546 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { 3547 .destroy = dce_v8_0_encoder_destroy, 3548 }; 3549 3550 static void dce_v8_0_encoder_add(struct amdgpu_device *adev, 3551 uint32_t encoder_enum, 3552 uint32_t supported_device, 3553 u16 caps) 3554 { 3555 struct drm_device *dev = adev->ddev; 3556 struct drm_encoder *encoder; 3557 struct amdgpu_encoder *amdgpu_encoder; 3558 3559 /* see if we already added it */ 3560 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3561 amdgpu_encoder = to_amdgpu_encoder(encoder); 3562 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3563 amdgpu_encoder->devices |= supported_device; 3564 return; 3565 } 3566 3567 } 3568 3569 /* add a new one */ 3570 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3571 if (!amdgpu_encoder) 3572 return; 3573 3574 encoder = &amdgpu_encoder->base; 3575 switch (adev->mode_info.num_crtc) { 3576 case 1: 3577 encoder->possible_crtcs = 0x1; 3578 break; 3579 case 2: 3580 default: 3581 encoder->possible_crtcs = 0x3; 3582 break; 3583 case 4: 3584 encoder->possible_crtcs = 0xf; 3585 break; 3586 case 6: 3587 encoder->possible_crtcs = 0x3f; 3588 break; 3589 } 3590 3591 amdgpu_encoder->enc_priv = NULL; 3592 3593 amdgpu_encoder->encoder_enum = encoder_enum; 3594 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3595 amdgpu_encoder->devices = supported_device; 3596 amdgpu_encoder->rmx_type = RMX_OFF; 3597 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3598 amdgpu_encoder->is_ext_encoder = false; 3599 amdgpu_encoder->caps = caps; 3600 3601 switch (amdgpu_encoder->encoder_id) { 3602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3604 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3605 DRM_MODE_ENCODER_DAC, NULL); 3606 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); 3607 break; 3608 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3610 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3611 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3613 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3614 amdgpu_encoder->rmx_type = RMX_FULL; 3615 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3616 DRM_MODE_ENCODER_LVDS, NULL); 3617 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3618 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3619 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3620 DRM_MODE_ENCODER_DAC, NULL); 3621 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3622 } else { 3623 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3624 DRM_MODE_ENCODER_TMDS, NULL); 3625 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3626 } 3627 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); 3628 break; 3629 case ENCODER_OBJECT_ID_SI170B: 3630 case ENCODER_OBJECT_ID_CH7303: 3631 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3632 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3633 case ENCODER_OBJECT_ID_TITFP513: 3634 case ENCODER_OBJECT_ID_VT1623: 3635 case ENCODER_OBJECT_ID_HDMI_SI1930: 3636 case ENCODER_OBJECT_ID_TRAVIS: 3637 case ENCODER_OBJECT_ID_NUTMEG: 3638 /* these are handled by the primary encoders */ 3639 amdgpu_encoder->is_ext_encoder = true; 3640 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3641 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3642 DRM_MODE_ENCODER_LVDS, NULL); 3643 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3644 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3645 DRM_MODE_ENCODER_DAC, NULL); 3646 else 3647 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3648 DRM_MODE_ENCODER_TMDS, NULL); 3649 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs); 3650 break; 3651 } 3652 } 3653 3654 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { 3655 .set_vga_render_state = &dce_v8_0_set_vga_render_state, 3656 .bandwidth_update = &dce_v8_0_bandwidth_update, 3657 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3658 .vblank_wait = &dce_v8_0_vblank_wait, 3659 .is_display_hung = &dce_v8_0_is_display_hung, 3660 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3661 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3662 .hpd_sense = &dce_v8_0_hpd_sense, 3663 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity, 3664 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg, 3665 .page_flip = &dce_v8_0_page_flip, 3666 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos, 3667 .add_encoder = &dce_v8_0_encoder_add, 3668 .add_connector = &amdgpu_connector_add, 3669 .stop_mc_access = &dce_v8_0_stop_mc_access, 3670 .resume_mc_access = &dce_v8_0_resume_mc_access, 3671 }; 3672 3673 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) 3674 { 3675 if (adev->mode_info.funcs == NULL) 3676 adev->mode_info.funcs = &dce_v8_0_display_funcs; 3677 } 3678 3679 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = { 3680 .set = dce_v8_0_set_crtc_interrupt_state, 3681 .process = dce_v8_0_crtc_irq, 3682 }; 3683 3684 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = { 3685 .set = dce_v8_0_set_pageflip_interrupt_state, 3686 .process = dce_v8_0_pageflip_irq, 3687 }; 3688 3689 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { 3690 .set = dce_v8_0_set_hpd_interrupt_state, 3691 .process = dce_v8_0_hpd_irq, 3692 }; 3693 3694 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) 3695 { 3696 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3697 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; 3698 3699 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3700 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; 3701 3702 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3703 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; 3704 } 3705