1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "dce_v6_0.h" 44 #include "sid.h" 45 46 #include "bif/bif_3_0_d.h" 47 #include "bif/bif_3_0_sh_mask.h" 48 49 #include "oss/oss_1_0_d.h" 50 #include "oss/oss_1_0_sh_mask.h" 51 52 #include "gca/gfx_6_0_d.h" 53 #include "gca/gfx_6_0_sh_mask.h" 54 #include "gca/gfx_7_2_enum.h" 55 56 #include "gmc/gmc_6_0_d.h" 57 #include "gmc/gmc_6_0_sh_mask.h" 58 59 #include "dce/dce_6_0_d.h" 60 #include "dce/dce_6_0_sh_mask.h" 61 62 #include "si_enums.h" 63 64 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 65 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const u32 crtc_offsets[6] = 68 { 69 CRTC0_REGISTER_OFFSET, 70 CRTC1_REGISTER_OFFSET, 71 CRTC2_REGISTER_OFFSET, 72 CRTC3_REGISTER_OFFSET, 73 CRTC4_REGISTER_OFFSET, 74 CRTC5_REGISTER_OFFSET 75 }; 76 77 static const u32 hpd_offsets[] = 78 { 79 HPD0_REGISTER_OFFSET, 80 HPD1_REGISTER_OFFSET, 81 HPD2_REGISTER_OFFSET, 82 HPD3_REGISTER_OFFSET, 83 HPD4_REGISTER_OFFSET, 84 HPD5_REGISTER_OFFSET 85 }; 86 87 static const uint32_t dig_offsets[] = { 88 CRTC0_REGISTER_OFFSET, 89 CRTC1_REGISTER_OFFSET, 90 CRTC2_REGISTER_OFFSET, 91 CRTC3_REGISTER_OFFSET, 92 CRTC4_REGISTER_OFFSET, 93 CRTC5_REGISTER_OFFSET, 94 (0x13830 - 0x7030) >> 2, 95 }; 96 97 static const struct { 98 uint32_t reg; 99 uint32_t vblank; 100 uint32_t vline; 101 uint32_t hpd; 102 103 } interrupt_status_offsets[6] = { { 104 .reg = mmDISP_INTERRUPT_STATUS, 105 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 113 }, { 114 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 116 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 118 }, { 119 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 120 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 121 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 123 }, { 124 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 125 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 126 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 128 }, { 129 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 130 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 131 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 132 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 133 } }; 134 135 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 136 u32 block_offset, u32 reg) 137 { 138 unsigned long flags; 139 u32 r; 140 141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 143 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 145 146 return r; 147 } 148 149 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 150 u32 block_offset, u32 reg, u32 v) 151 { 152 unsigned long flags; 153 154 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 155 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 156 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 157 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 158 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 159 } 160 161 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 162 { 163 if (crtc >= adev->mode_info.num_crtc) 164 return 0; 165 else 166 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 167 } 168 169 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 170 { 171 unsigned i; 172 173 /* Enable pflip interrupts */ 174 for (i = 0; i < adev->mode_info.num_crtc; i++) 175 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 176 } 177 178 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 179 { 180 unsigned i; 181 182 /* Disable pflip interrupts */ 183 for (i = 0; i < adev->mode_info.num_crtc; i++) 184 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 185 } 186 187 /** 188 * dce_v6_0_page_flip - pageflip callback. 189 * 190 * @adev: amdgpu_device pointer 191 * @crtc_id: crtc to cleanup pageflip on 192 * @crtc_base: new address of the crtc (GPU MC address) 193 * @async: asynchronous flip 194 * 195 * Does the actual pageflip (evergreen+). 196 * During vblank we take the crtc lock and wait for the update_pending 197 * bit to go high, when it does, we release the lock, and allow the 198 * double buffered update to take place. 199 * Returns the current update pending status. 200 */ 201 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 202 int crtc_id, u64 crtc_base, bool async) 203 { 204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 205 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 206 207 /* flip at hsync for async, default is vsync */ 208 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 209 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 210 /* update pitch */ 211 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 212 fb->pitches[0] / fb->format->cpp[0]); 213 /* update the scanout addresses */ 214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 215 upper_32_bits(crtc_base)); 216 /* writing to the low address triggers the update */ 217 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 218 (u32)crtc_base); 219 /* post the write */ 220 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 221 } 222 223 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 224 u32 *vbl, u32 *position) 225 { 226 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 227 return -EINVAL; 228 229 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 230 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 231 232 return 0; 233 } 234 235 /** 236 * dce_v6_0_hpd_sense - hpd sense callback. 237 * 238 * @adev: amdgpu_device pointer 239 * @hpd: hpd (hotplug detect) pin 240 * 241 * Checks if a digital monitor is connected (evergreen+). 242 * Returns true if connected, false if not connected. 243 */ 244 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 245 enum amdgpu_hpd_id hpd) 246 { 247 bool connected = false; 248 249 if (hpd >= adev->mode_info.num_hpd) 250 return connected; 251 252 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 253 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 254 connected = true; 255 256 return connected; 257 } 258 259 /** 260 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 261 * 262 * @adev: amdgpu_device pointer 263 * @hpd: hpd (hotplug detect) pin 264 * 265 * Set the polarity of the hpd pin (evergreen+). 266 */ 267 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 268 enum amdgpu_hpd_id hpd) 269 { 270 u32 tmp; 271 bool connected = dce_v6_0_hpd_sense(adev, hpd); 272 273 if (hpd >= adev->mode_info.num_hpd) 274 return; 275 276 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 277 if (connected) 278 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 279 else 280 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 281 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 282 } 283 284 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 285 int hpd) 286 { 287 u32 tmp; 288 289 if (hpd >= adev->mode_info.num_hpd) { 290 DRM_DEBUG("invalid hpd %d\n", hpd); 291 return; 292 } 293 294 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 295 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 296 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 297 } 298 299 /** 300 * dce_v6_0_hpd_init - hpd setup callback. 301 * 302 * @adev: amdgpu_device pointer 303 * 304 * Setup the hpd pins used by the card (evergreen+). 305 * Enable the pin, set the polarity, and enable the hpd interrupts. 306 */ 307 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 308 { 309 struct drm_device *dev = adev_to_drm(adev); 310 struct drm_connector *connector; 311 struct drm_connector_list_iter iter; 312 u32 tmp; 313 314 drm_connector_list_iter_begin(dev, &iter); 315 drm_for_each_connector_iter(connector, &iter) { 316 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 317 318 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 319 continue; 320 321 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 322 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 323 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 324 325 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 326 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 327 /* don't try to enable hpd on eDP or LVDS avoid breaking the 328 * aux dp channel on imac and help (but not completely fix) 329 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 330 * also avoid interrupt storms during dpms. 331 */ 332 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 333 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 334 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 335 continue; 336 } 337 338 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 339 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 340 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 341 } 342 drm_connector_list_iter_end(&iter); 343 } 344 345 /** 346 * dce_v6_0_hpd_fini - hpd tear down callback. 347 * 348 * @adev: amdgpu_device pointer 349 * 350 * Tear down the hpd pins used by the card (evergreen+). 351 * Disable the hpd interrupts. 352 */ 353 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 354 { 355 struct drm_device *dev = adev_to_drm(adev); 356 struct drm_connector *connector; 357 struct drm_connector_list_iter iter; 358 u32 tmp; 359 360 drm_connector_list_iter_begin(dev, &iter); 361 drm_for_each_connector_iter(connector, &iter) { 362 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 363 364 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 365 continue; 366 367 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 368 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 369 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 370 371 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 372 } 373 drm_connector_list_iter_end(&iter); 374 } 375 376 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 377 { 378 return mmDC_GPIO_HPD_A; 379 } 380 381 static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) 382 { 383 u32 crtc_hung = 0; 384 u32 crtc_status[6]; 385 u32 i, j, tmp; 386 387 for (i = 0; i < adev->mode_info.num_crtc; i++) { 388 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 389 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 390 crtc_hung |= (1 << i); 391 } 392 } 393 394 for (j = 0; j < 10; j++) { 395 for (i = 0; i < adev->mode_info.num_crtc; i++) { 396 if (crtc_hung & (1 << i)) { 397 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 398 if (tmp != crtc_status[i]) 399 crtc_hung &= ~(1 << i); 400 } 401 } 402 if (crtc_hung == 0) 403 return false; 404 udelay(100); 405 } 406 407 return true; 408 } 409 410 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 411 bool render) 412 { 413 if (!render) 414 WREG32(mmVGA_RENDER_CONTROL, 415 RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK); 416 } 417 418 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 419 { 420 switch (adev->asic_type) { 421 case CHIP_TAHITI: 422 case CHIP_PITCAIRN: 423 case CHIP_VERDE: 424 return 6; 425 case CHIP_OLAND: 426 return 2; 427 default: 428 return 0; 429 } 430 } 431 432 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 433 { 434 /*Disable VGA render and enabled crtc, if has DCE engine*/ 435 if (amdgpu_atombios_has_dce_engine_info(adev)) { 436 u32 tmp; 437 int crtc_enabled, i; 438 439 dce_v6_0_set_vga_render_state(adev, false); 440 441 /*Disable crtc*/ 442 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 443 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 444 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 445 if (crtc_enabled) { 446 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 447 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 448 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 449 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 450 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 451 } 452 } 453 } 454 } 455 456 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 457 { 458 struct drm_device *dev = encoder->dev; 459 struct amdgpu_device *adev = drm_to_adev(dev); 460 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 461 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 462 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 463 int bpc = 0; 464 u32 tmp = 0; 465 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 466 467 if (connector) { 468 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 469 bpc = amdgpu_connector_get_monitor_bpc(connector); 470 dither = amdgpu_connector->dither; 471 } 472 473 /* LVDS FMT is set up by atom */ 474 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 475 return; 476 477 if (bpc == 0) 478 return; 479 480 481 switch (bpc) { 482 case 6: 483 if (dither == AMDGPU_FMT_DITHER_ENABLE) 484 /* XXX sort out optimal dither settings */ 485 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 486 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 487 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 488 else 489 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 490 break; 491 case 8: 492 if (dither == AMDGPU_FMT_DITHER_ENABLE) 493 /* XXX sort out optimal dither settings */ 494 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 495 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 496 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 497 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 498 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 499 else 500 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 501 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 502 break; 503 case 10: 504 default: 505 /* not needed */ 506 break; 507 } 508 509 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 510 } 511 512 /** 513 * si_get_number_of_dram_channels - get the number of dram channels 514 * 515 * @adev: amdgpu_device pointer 516 * 517 * Look up the number of video ram channels (CIK). 518 * Used for display watermark bandwidth calculations 519 * Returns the number of dram channels 520 */ 521 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 522 { 523 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 524 525 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 526 case 0: 527 default: 528 return 1; 529 case 1: 530 return 2; 531 case 2: 532 return 4; 533 case 3: 534 return 8; 535 case 4: 536 return 3; 537 case 5: 538 return 6; 539 case 6: 540 return 10; 541 case 7: 542 return 12; 543 case 8: 544 return 16; 545 } 546 } 547 548 struct dce6_wm_params { 549 u32 dram_channels; /* number of dram channels */ 550 u32 yclk; /* bandwidth per dram data pin in kHz */ 551 u32 sclk; /* engine clock in kHz */ 552 u32 disp_clk; /* display clock in kHz */ 553 u32 src_width; /* viewport width */ 554 u32 active_time; /* active display time in ns */ 555 u32 blank_time; /* blank time in ns */ 556 bool interlaced; /* mode is interlaced */ 557 fixed20_12 vsc; /* vertical scale ratio */ 558 u32 num_heads; /* number of active crtcs */ 559 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 560 u32 lb_size; /* line buffer allocated to pipe */ 561 u32 vtaps; /* vertical scaler taps */ 562 }; 563 564 /** 565 * dce_v6_0_dram_bandwidth - get the dram bandwidth 566 * 567 * @wm: watermark calculation data 568 * 569 * Calculate the raw dram bandwidth (CIK). 570 * Used for display watermark bandwidth calculations 571 * Returns the dram bandwidth in MBytes/s 572 */ 573 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 574 { 575 /* Calculate raw DRAM Bandwidth */ 576 fixed20_12 dram_efficiency; /* 0.7 */ 577 fixed20_12 yclk, dram_channels, bandwidth; 578 fixed20_12 a; 579 580 a.full = dfixed_const(1000); 581 yclk.full = dfixed_const(wm->yclk); 582 yclk.full = dfixed_div(yclk, a); 583 dram_channels.full = dfixed_const(wm->dram_channels * 4); 584 a.full = dfixed_const(10); 585 dram_efficiency.full = dfixed_const(7); 586 dram_efficiency.full = dfixed_div(dram_efficiency, a); 587 bandwidth.full = dfixed_mul(dram_channels, yclk); 588 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 589 590 return dfixed_trunc(bandwidth); 591 } 592 593 /** 594 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 595 * 596 * @wm: watermark calculation data 597 * 598 * Calculate the dram bandwidth used for display (CIK). 599 * Used for display watermark bandwidth calculations 600 * Returns the dram bandwidth for display in MBytes/s 601 */ 602 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 603 { 604 /* Calculate DRAM Bandwidth and the part allocated to display. */ 605 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 606 fixed20_12 yclk, dram_channels, bandwidth; 607 fixed20_12 a; 608 609 a.full = dfixed_const(1000); 610 yclk.full = dfixed_const(wm->yclk); 611 yclk.full = dfixed_div(yclk, a); 612 dram_channels.full = dfixed_const(wm->dram_channels * 4); 613 a.full = dfixed_const(10); 614 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 615 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 616 bandwidth.full = dfixed_mul(dram_channels, yclk); 617 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 618 619 return dfixed_trunc(bandwidth); 620 } 621 622 /** 623 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 624 * 625 * @wm: watermark calculation data 626 * 627 * Calculate the data return bandwidth used for display (CIK). 628 * Used for display watermark bandwidth calculations 629 * Returns the data return bandwidth in MBytes/s 630 */ 631 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 632 { 633 /* Calculate the display Data return Bandwidth */ 634 fixed20_12 return_efficiency; /* 0.8 */ 635 fixed20_12 sclk, bandwidth; 636 fixed20_12 a; 637 638 a.full = dfixed_const(1000); 639 sclk.full = dfixed_const(wm->sclk); 640 sclk.full = dfixed_div(sclk, a); 641 a.full = dfixed_const(10); 642 return_efficiency.full = dfixed_const(8); 643 return_efficiency.full = dfixed_div(return_efficiency, a); 644 a.full = dfixed_const(32); 645 bandwidth.full = dfixed_mul(a, sclk); 646 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 647 648 return dfixed_trunc(bandwidth); 649 } 650 651 /** 652 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 653 * 654 * @wm: watermark calculation data 655 * 656 * Calculate the dmif bandwidth used for display (CIK). 657 * Used for display watermark bandwidth calculations 658 * Returns the dmif bandwidth in MBytes/s 659 */ 660 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 661 { 662 /* Calculate the DMIF Request Bandwidth */ 663 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 664 fixed20_12 disp_clk, bandwidth; 665 fixed20_12 a, b; 666 667 a.full = dfixed_const(1000); 668 disp_clk.full = dfixed_const(wm->disp_clk); 669 disp_clk.full = dfixed_div(disp_clk, a); 670 a.full = dfixed_const(32); 671 b.full = dfixed_mul(a, disp_clk); 672 673 a.full = dfixed_const(10); 674 disp_clk_request_efficiency.full = dfixed_const(8); 675 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 676 677 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 678 679 return dfixed_trunc(bandwidth); 680 } 681 682 /** 683 * dce_v6_0_available_bandwidth - get the min available bandwidth 684 * 685 * @wm: watermark calculation data 686 * 687 * Calculate the min available bandwidth used for display (CIK). 688 * Used for display watermark bandwidth calculations 689 * Returns the min available bandwidth in MBytes/s 690 */ 691 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 692 { 693 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 694 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 695 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 696 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 697 698 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 699 } 700 701 /** 702 * dce_v6_0_average_bandwidth - get the average available bandwidth 703 * 704 * @wm: watermark calculation data 705 * 706 * Calculate the average available bandwidth used for display (CIK). 707 * Used for display watermark bandwidth calculations 708 * Returns the average available bandwidth in MBytes/s 709 */ 710 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 711 { 712 /* Calculate the display mode Average Bandwidth 713 * DisplayMode should contain the source and destination dimensions, 714 * timing, etc. 715 */ 716 fixed20_12 bpp; 717 fixed20_12 line_time; 718 fixed20_12 src_width; 719 fixed20_12 bandwidth; 720 fixed20_12 a; 721 722 a.full = dfixed_const(1000); 723 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 724 line_time.full = dfixed_div(line_time, a); 725 bpp.full = dfixed_const(wm->bytes_per_pixel); 726 src_width.full = dfixed_const(wm->src_width); 727 bandwidth.full = dfixed_mul(src_width, bpp); 728 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 729 bandwidth.full = dfixed_div(bandwidth, line_time); 730 731 return dfixed_trunc(bandwidth); 732 } 733 734 /** 735 * dce_v6_0_latency_watermark - get the latency watermark 736 * 737 * @wm: watermark calculation data 738 * 739 * Calculate the latency watermark (CIK). 740 * Used for display watermark bandwidth calculations 741 * Returns the latency watermark in ns 742 */ 743 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 744 { 745 /* First calculate the latency in ns */ 746 u32 mc_latency = 2000; /* 2000 ns. */ 747 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 748 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 749 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 750 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 751 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 752 (wm->num_heads * cursor_line_pair_return_time); 753 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 754 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 755 u32 tmp, dmif_size = 12288; 756 fixed20_12 a, b, c; 757 758 if (wm->num_heads == 0) 759 return 0; 760 761 a.full = dfixed_const(2); 762 b.full = dfixed_const(1); 763 if ((wm->vsc.full > a.full) || 764 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 765 (wm->vtaps >= 5) || 766 ((wm->vsc.full >= a.full) && wm->interlaced)) 767 max_src_lines_per_dst_line = 4; 768 else 769 max_src_lines_per_dst_line = 2; 770 771 a.full = dfixed_const(available_bandwidth); 772 b.full = dfixed_const(wm->num_heads); 773 a.full = dfixed_div(a, b); 774 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 775 tmp = min(dfixed_trunc(a), tmp); 776 777 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 778 779 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 780 b.full = dfixed_const(1000); 781 c.full = dfixed_const(lb_fill_bw); 782 b.full = dfixed_div(c, b); 783 a.full = dfixed_div(a, b); 784 line_fill_time = dfixed_trunc(a); 785 786 if (line_fill_time < wm->active_time) 787 return latency; 788 else 789 return latency + (line_fill_time - wm->active_time); 790 791 } 792 793 /** 794 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 795 * average and available dram bandwidth 796 * 797 * @wm: watermark calculation data 798 * 799 * Check if the display average bandwidth fits in the display 800 * dram bandwidth (CIK). 801 * Used for display watermark bandwidth calculations 802 * Returns true if the display fits, false if not. 803 */ 804 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 805 { 806 if (dce_v6_0_average_bandwidth(wm) <= 807 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 808 return true; 809 else 810 return false; 811 } 812 813 /** 814 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 815 * average and available bandwidth 816 * 817 * @wm: watermark calculation data 818 * 819 * Check if the display average bandwidth fits in the display 820 * available bandwidth (CIK). 821 * Used for display watermark bandwidth calculations 822 * Returns true if the display fits, false if not. 823 */ 824 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 825 { 826 if (dce_v6_0_average_bandwidth(wm) <= 827 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 828 return true; 829 else 830 return false; 831 } 832 833 /** 834 * dce_v6_0_check_latency_hiding - check latency hiding 835 * 836 * @wm: watermark calculation data 837 * 838 * Check latency hiding (CIK). 839 * Used for display watermark bandwidth calculations 840 * Returns true if the display fits, false if not. 841 */ 842 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 843 { 844 u32 lb_partitions = wm->lb_size / wm->src_width; 845 u32 line_time = wm->active_time + wm->blank_time; 846 u32 latency_tolerant_lines; 847 u32 latency_hiding; 848 fixed20_12 a; 849 850 a.full = dfixed_const(1); 851 if (wm->vsc.full > a.full) 852 latency_tolerant_lines = 1; 853 else { 854 if (lb_partitions <= (wm->vtaps + 1)) 855 latency_tolerant_lines = 1; 856 else 857 latency_tolerant_lines = 2; 858 } 859 860 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 861 862 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 863 return true; 864 else 865 return false; 866 } 867 868 /** 869 * dce_v6_0_program_watermarks - program display watermarks 870 * 871 * @adev: amdgpu_device pointer 872 * @amdgpu_crtc: the selected display controller 873 * @lb_size: line buffer size 874 * @num_heads: number of display controllers in use 875 * 876 * Calculate and program the display watermarks for the 877 * selected display controller (CIK). 878 */ 879 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 880 struct amdgpu_crtc *amdgpu_crtc, 881 u32 lb_size, u32 num_heads) 882 { 883 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 884 struct dce6_wm_params wm_low, wm_high; 885 u32 dram_channels; 886 u32 active_time; 887 u32 line_time = 0; 888 u32 latency_watermark_a = 0, latency_watermark_b = 0; 889 u32 priority_a_mark = 0, priority_b_mark = 0; 890 u32 priority_a_cnt = PRIORITY_OFF; 891 u32 priority_b_cnt = PRIORITY_OFF; 892 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 893 fixed20_12 a, b, c; 894 895 if (amdgpu_crtc->base.enabled && num_heads && mode) { 896 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 897 (u32)mode->clock); 898 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 899 (u32)mode->clock); 900 line_time = min_t(u32, line_time, 65535); 901 priority_a_cnt = 0; 902 priority_b_cnt = 0; 903 904 dram_channels = si_get_number_of_dram_channels(adev); 905 906 /* watermark for high clocks */ 907 if (adev->pm.dpm_enabled) { 908 wm_high.yclk = 909 amdgpu_dpm_get_mclk(adev, false) * 10; 910 wm_high.sclk = 911 amdgpu_dpm_get_sclk(adev, false) * 10; 912 } else { 913 wm_high.yclk = adev->pm.current_mclk * 10; 914 wm_high.sclk = adev->pm.current_sclk * 10; 915 } 916 917 wm_high.disp_clk = mode->clock; 918 wm_high.src_width = mode->crtc_hdisplay; 919 wm_high.active_time = active_time; 920 wm_high.blank_time = line_time - wm_high.active_time; 921 wm_high.interlaced = false; 922 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 923 wm_high.interlaced = true; 924 wm_high.vsc = amdgpu_crtc->vsc; 925 wm_high.vtaps = 1; 926 if (amdgpu_crtc->rmx_type != RMX_OFF) 927 wm_high.vtaps = 2; 928 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 929 wm_high.lb_size = lb_size; 930 wm_high.dram_channels = dram_channels; 931 wm_high.num_heads = num_heads; 932 933 /* watermark for low clocks */ 934 if (adev->pm.dpm_enabled) { 935 wm_low.yclk = 936 amdgpu_dpm_get_mclk(adev, true) * 10; 937 wm_low.sclk = 938 amdgpu_dpm_get_sclk(adev, true) * 10; 939 } else { 940 wm_low.yclk = adev->pm.current_mclk * 10; 941 wm_low.sclk = adev->pm.current_sclk * 10; 942 } 943 944 wm_low.disp_clk = mode->clock; 945 wm_low.src_width = mode->crtc_hdisplay; 946 wm_low.active_time = active_time; 947 wm_low.blank_time = line_time - wm_low.active_time; 948 wm_low.interlaced = false; 949 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 950 wm_low.interlaced = true; 951 wm_low.vsc = amdgpu_crtc->vsc; 952 wm_low.vtaps = 1; 953 if (amdgpu_crtc->rmx_type != RMX_OFF) 954 wm_low.vtaps = 2; 955 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 956 wm_low.lb_size = lb_size; 957 wm_low.dram_channels = dram_channels; 958 wm_low.num_heads = num_heads; 959 960 /* set for high clocks */ 961 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 962 /* set for low clocks */ 963 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 964 965 /* possibly force display priority to high */ 966 /* should really do this at mode validation time... */ 967 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 968 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 969 !dce_v6_0_check_latency_hiding(&wm_high) || 970 (adev->mode_info.disp_priority == 2)) { 971 DRM_DEBUG_KMS("force priority to high\n"); 972 priority_a_cnt |= PRIORITY_ALWAYS_ON; 973 priority_b_cnt |= PRIORITY_ALWAYS_ON; 974 } 975 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 976 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 977 !dce_v6_0_check_latency_hiding(&wm_low) || 978 (adev->mode_info.disp_priority == 2)) { 979 DRM_DEBUG_KMS("force priority to high\n"); 980 priority_a_cnt |= PRIORITY_ALWAYS_ON; 981 priority_b_cnt |= PRIORITY_ALWAYS_ON; 982 } 983 984 a.full = dfixed_const(1000); 985 b.full = dfixed_const(mode->clock); 986 b.full = dfixed_div(b, a); 987 c.full = dfixed_const(latency_watermark_a); 988 c.full = dfixed_mul(c, b); 989 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 990 c.full = dfixed_div(c, a); 991 a.full = dfixed_const(16); 992 c.full = dfixed_div(c, a); 993 priority_a_mark = dfixed_trunc(c); 994 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 995 996 a.full = dfixed_const(1000); 997 b.full = dfixed_const(mode->clock); 998 b.full = dfixed_div(b, a); 999 c.full = dfixed_const(latency_watermark_b); 1000 c.full = dfixed_mul(c, b); 1001 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1002 c.full = dfixed_div(c, a); 1003 a.full = dfixed_const(16); 1004 c.full = dfixed_div(c, a); 1005 priority_b_mark = dfixed_trunc(c); 1006 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1007 1008 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1009 } 1010 1011 /* select wm A */ 1012 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1013 tmp = arb_control3; 1014 tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 1015 tmp |= (1 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 1016 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1017 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1018 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1019 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1020 /* select wm B */ 1021 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1022 tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 1023 tmp |= (2 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 1024 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1025 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1026 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1027 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1028 /* restore original selection */ 1029 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1030 1031 /* write the priority marks */ 1032 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1033 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1034 1035 /* save values for DPM */ 1036 amdgpu_crtc->line_time = line_time; 1037 amdgpu_crtc->wm_high = latency_watermark_a; 1038 1039 /* Save number of lines the linebuffer leads before the scanout */ 1040 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1041 } 1042 1043 /* watermark setup */ 1044 /** 1045 * dce_v6_0_line_buffer_adjust - Set up the line buffer 1046 * 1047 * @adev: amdgpu_device pointer 1048 * @amdgpu_crtc: the selected display controller 1049 * @mode: the current display mode on the selected display 1050 * controller 1051 * @other_mode: the display mode of another display controller 1052 * that may be sharing the line buffer 1053 * 1054 * Setup up the line buffer allocation for 1055 * the selected display controller (CIK). 1056 * Returns the line buffer size in pixels. 1057 */ 1058 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1059 struct amdgpu_crtc *amdgpu_crtc, 1060 struct drm_display_mode *mode, 1061 struct drm_display_mode *other_mode) 1062 { 1063 u32 tmp, buffer_alloc, i; 1064 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1065 /* 1066 * Line Buffer Setup 1067 * There are 3 line buffers, each one shared by 2 display controllers. 1068 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1069 * the display controllers. The paritioning is done via one of four 1070 * preset allocations specified in bits 21:20: 1071 * 0 - half lb 1072 * 2 - whole lb, other crtc must be disabled 1073 */ 1074 /* this can get tricky if we have two large displays on a paired group 1075 * of crtcs. Ideally for multiple large displays we'd assign them to 1076 * non-linked crtcs for maximum line buffer allocation. 1077 */ 1078 if (amdgpu_crtc->base.enabled && mode) { 1079 if (other_mode) { 1080 tmp = 0; /* 1/2 */ 1081 buffer_alloc = 1; 1082 } else { 1083 tmp = 2; /* whole */ 1084 buffer_alloc = 2; 1085 } 1086 } else { 1087 tmp = 0; 1088 buffer_alloc = 0; 1089 } 1090 1091 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1092 (tmp << DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT)); 1093 1094 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1095 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1096 for (i = 0; i < adev->usec_timeout; i++) { 1097 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1098 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1099 break; 1100 udelay(1); 1101 } 1102 1103 if (amdgpu_crtc->base.enabled && mode) { 1104 switch (tmp) { 1105 case 0: 1106 default: 1107 return 4096 * 2; 1108 case 2: 1109 return 8192 * 2; 1110 } 1111 } 1112 1113 /* controller not enabled, so no lb used */ 1114 return 0; 1115 } 1116 1117 1118 /** 1119 * dce_v6_0_bandwidth_update - program display watermarks 1120 * 1121 * @adev: amdgpu_device pointer 1122 * 1123 * Calculate and program the display watermarks and line 1124 * buffer allocation (CIK). 1125 */ 1126 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1127 { 1128 struct drm_display_mode *mode0 = NULL; 1129 struct drm_display_mode *mode1 = NULL; 1130 u32 num_heads = 0, lb_size; 1131 int i; 1132 1133 if (!adev->mode_info.mode_config_initialized) 1134 return; 1135 1136 amdgpu_display_update_priority(adev); 1137 1138 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1139 if (adev->mode_info.crtcs[i]->base.enabled) 1140 num_heads++; 1141 } 1142 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1143 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1144 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1145 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1146 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1147 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1148 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1149 } 1150 } 1151 1152 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1153 { 1154 int i; 1155 u32 tmp; 1156 1157 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1158 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1159 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1160 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1161 PORT_CONNECTIVITY)) 1162 adev->mode_info.audio.pin[i].connected = false; 1163 else 1164 adev->mode_info.audio.pin[i].connected = true; 1165 } 1166 1167 } 1168 1169 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1170 { 1171 int i; 1172 1173 dce_v6_0_audio_get_connected_pins(adev); 1174 1175 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1176 if (adev->mode_info.audio.pin[i].connected) 1177 return &adev->mode_info.audio.pin[i]; 1178 } 1179 DRM_ERROR("No connected audio pins found!\n"); 1180 return NULL; 1181 } 1182 1183 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1184 { 1185 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1186 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1187 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1188 1189 if (!dig || !dig->afmt || !dig->afmt->pin) 1190 return; 1191 1192 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1193 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1194 dig->afmt->pin->id)); 1195 } 1196 1197 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1198 struct drm_display_mode *mode) 1199 { 1200 struct drm_device *dev = encoder->dev; 1201 struct amdgpu_device *adev = drm_to_adev(dev); 1202 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1203 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1204 struct drm_connector *connector; 1205 struct drm_connector_list_iter iter; 1206 struct amdgpu_connector *amdgpu_connector = NULL; 1207 int interlace = 0; 1208 u32 tmp; 1209 1210 drm_connector_list_iter_begin(dev, &iter); 1211 drm_for_each_connector_iter(connector, &iter) { 1212 if (connector->encoder == encoder) { 1213 amdgpu_connector = to_amdgpu_connector(connector); 1214 break; 1215 } 1216 } 1217 drm_connector_list_iter_end(&iter); 1218 1219 if (!amdgpu_connector) { 1220 DRM_ERROR("Couldn't find encoder's connector\n"); 1221 return; 1222 } 1223 1224 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1225 interlace = 1; 1226 1227 if (connector->latency_present[interlace]) { 1228 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1229 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1230 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1231 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1232 } else { 1233 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1234 VIDEO_LIPSYNC, 0); 1235 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1236 AUDIO_LIPSYNC, 0); 1237 } 1238 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1239 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1240 } 1241 1242 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1243 { 1244 struct drm_device *dev = encoder->dev; 1245 struct amdgpu_device *adev = drm_to_adev(dev); 1246 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1247 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1248 struct drm_connector *connector; 1249 struct drm_connector_list_iter iter; 1250 struct amdgpu_connector *amdgpu_connector = NULL; 1251 u8 *sadb = NULL; 1252 int sad_count; 1253 u32 tmp; 1254 1255 drm_connector_list_iter_begin(dev, &iter); 1256 drm_for_each_connector_iter(connector, &iter) { 1257 if (connector->encoder == encoder) { 1258 amdgpu_connector = to_amdgpu_connector(connector); 1259 break; 1260 } 1261 } 1262 drm_connector_list_iter_end(&iter); 1263 1264 if (!amdgpu_connector) { 1265 DRM_ERROR("Couldn't find encoder's connector\n"); 1266 return; 1267 } 1268 1269 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); 1270 if (sad_count < 0) { 1271 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1272 sad_count = 0; 1273 } 1274 1275 /* program the speaker allocation */ 1276 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1277 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1278 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1279 HDMI_CONNECTION, 0); 1280 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1281 DP_CONNECTION, 0); 1282 1283 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1284 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1285 DP_CONNECTION, 1); 1286 else 1287 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1288 HDMI_CONNECTION, 1); 1289 1290 if (sad_count) 1291 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1292 SPEAKER_ALLOCATION, sadb[0]); 1293 else 1294 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1295 SPEAKER_ALLOCATION, 5); /* stereo */ 1296 1297 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1298 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1299 1300 kfree(sadb); 1301 } 1302 1303 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1304 { 1305 struct drm_device *dev = encoder->dev; 1306 struct amdgpu_device *adev = drm_to_adev(dev); 1307 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1308 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1309 u32 offset; 1310 struct drm_connector *connector; 1311 struct drm_connector_list_iter iter; 1312 struct amdgpu_connector *amdgpu_connector = NULL; 1313 struct cea_sad *sads; 1314 int i, sad_count; 1315 1316 static const u16 eld_reg_to_type[][2] = { 1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1319 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1320 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1321 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1322 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1323 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1324 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1325 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1326 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1327 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1328 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1329 }; 1330 1331 if (!dig || !dig->afmt || !dig->afmt->pin) 1332 return; 1333 1334 offset = dig->afmt->pin->offset; 1335 1336 drm_connector_list_iter_begin(dev, &iter); 1337 drm_for_each_connector_iter(connector, &iter) { 1338 if (connector->encoder == encoder) { 1339 amdgpu_connector = to_amdgpu_connector(connector); 1340 break; 1341 } 1342 } 1343 drm_connector_list_iter_end(&iter); 1344 1345 if (!amdgpu_connector) { 1346 DRM_ERROR("Couldn't find encoder's connector\n"); 1347 return; 1348 } 1349 1350 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); 1351 if (sad_count < 0) 1352 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1353 if (sad_count <= 0) 1354 return; 1355 1356 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1357 u32 value = 0; 1358 u8 stereo_freqs = 0; 1359 int max_channels = -1; 1360 int j; 1361 1362 for (j = 0; j < sad_count; j++) { 1363 struct cea_sad *sad = &sads[j]; 1364 1365 if (sad->format == eld_reg_to_type[i][1]) { 1366 if (sad->channels > max_channels) { 1367 value = (sad->channels << 1368 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1369 (sad->byte2 << 1370 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1371 (sad->freq << 1372 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1373 max_channels = sad->channels; 1374 } 1375 1376 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1377 stereo_freqs |= sad->freq; 1378 else 1379 break; 1380 } 1381 } 1382 1383 value |= (stereo_freqs << 1384 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1385 1386 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1387 } 1388 1389 kfree(sads); 1390 } 1391 1392 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1393 struct amdgpu_audio_pin *pin, 1394 bool enable) 1395 { 1396 if (!pin) 1397 return; 1398 1399 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1400 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1401 } 1402 1403 static const u32 pin_offsets[7] = 1404 { 1405 AUD0_REGISTER_OFFSET, 1406 AUD1_REGISTER_OFFSET, 1407 AUD2_REGISTER_OFFSET, 1408 AUD3_REGISTER_OFFSET, 1409 AUD4_REGISTER_OFFSET, 1410 AUD5_REGISTER_OFFSET, 1411 AUD6_REGISTER_OFFSET, 1412 }; 1413 1414 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1415 { 1416 int i; 1417 1418 if (!amdgpu_audio) 1419 return 0; 1420 1421 adev->mode_info.audio.enabled = true; 1422 1423 switch (adev->asic_type) { 1424 case CHIP_TAHITI: 1425 case CHIP_PITCAIRN: 1426 case CHIP_VERDE: 1427 default: 1428 adev->mode_info.audio.num_pins = 6; 1429 break; 1430 case CHIP_OLAND: 1431 adev->mode_info.audio.num_pins = 2; 1432 break; 1433 } 1434 1435 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1436 adev->mode_info.audio.pin[i].channels = -1; 1437 adev->mode_info.audio.pin[i].rate = -1; 1438 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1439 adev->mode_info.audio.pin[i].status_bits = 0; 1440 adev->mode_info.audio.pin[i].category_code = 0; 1441 adev->mode_info.audio.pin[i].connected = false; 1442 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1443 adev->mode_info.audio.pin[i].id = i; 1444 /* disable audio. it will be set up later */ 1445 /* XXX remove once we switch to ip funcs */ 1446 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1447 } 1448 1449 return 0; 1450 } 1451 1452 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1453 { 1454 if (!amdgpu_audio) 1455 return; 1456 1457 if (!adev->mode_info.audio.enabled) 1458 return; 1459 1460 adev->mode_info.audio.enabled = false; 1461 } 1462 1463 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1464 { 1465 struct drm_device *dev = encoder->dev; 1466 struct amdgpu_device *adev = drm_to_adev(dev); 1467 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1468 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1469 u32 tmp; 1470 1471 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1472 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1473 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1474 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1475 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1476 } 1477 1478 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1479 uint32_t clock, int bpc) 1480 { 1481 struct drm_device *dev = encoder->dev; 1482 struct amdgpu_device *adev = drm_to_adev(dev); 1483 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1484 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1485 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1486 u32 tmp; 1487 1488 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1489 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1490 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1491 bpc > 8 ? 0 : 1); 1492 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1493 1494 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1496 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1497 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1498 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1499 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1500 1501 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1503 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1504 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1505 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1506 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1507 1508 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1510 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1511 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1513 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1514 } 1515 1516 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1517 struct drm_display_mode *mode) 1518 { 1519 struct drm_device *dev = encoder->dev; 1520 struct amdgpu_device *adev = drm_to_adev(dev); 1521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1522 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1523 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1524 struct hdmi_avi_infoframe frame; 1525 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1526 uint8_t *payload = buffer + 3; 1527 uint8_t *header = buffer; 1528 ssize_t err; 1529 u32 tmp; 1530 1531 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1532 if (err < 0) { 1533 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1534 return; 1535 } 1536 1537 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1538 if (err < 0) { 1539 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1540 return; 1541 } 1542 1543 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1544 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1545 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1546 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1547 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1548 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1549 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1550 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1551 1552 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1553 /* anything other than 0 */ 1554 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1555 HDMI_AUDIO_INFO_LINE, 2); 1556 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1557 } 1558 1559 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1560 { 1561 struct drm_device *dev = encoder->dev; 1562 struct amdgpu_device *adev = drm_to_adev(dev); 1563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1564 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1565 u32 tmp; 1566 1567 /* 1568 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1569 * Express [24MHz / target pixel clock] as an exact rational 1570 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1571 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1572 */ 1573 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1574 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1575 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1576 if (em == ATOM_ENCODER_MODE_HDMI) { 1577 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1578 DCCG_AUDIO_DTO_SEL, 0); 1579 } else if (ENCODER_MODE_IS_DP(em)) { 1580 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1581 DCCG_AUDIO_DTO_SEL, 1); 1582 } 1583 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1584 if (em == ATOM_ENCODER_MODE_HDMI) { 1585 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1586 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1587 } else if (ENCODER_MODE_IS_DP(em)) { 1588 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1589 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1590 } 1591 } 1592 1593 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1594 { 1595 struct drm_device *dev = encoder->dev; 1596 struct amdgpu_device *adev = drm_to_adev(dev); 1597 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1598 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1599 u32 tmp; 1600 1601 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1602 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1603 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1604 1605 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1606 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1607 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1608 1609 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1610 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1611 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1612 1613 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1614 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1615 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1616 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1617 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1618 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1619 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1620 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1621 1622 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1623 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1624 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1625 1626 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1627 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1628 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1629 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1630 1631 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1632 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1633 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1634 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1635 } 1636 1637 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1638 { 1639 struct drm_device *dev = encoder->dev; 1640 struct amdgpu_device *adev = drm_to_adev(dev); 1641 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1642 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1643 u32 tmp; 1644 1645 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1646 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1647 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1648 } 1649 1650 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1651 { 1652 struct drm_device *dev = encoder->dev; 1653 struct amdgpu_device *adev = drm_to_adev(dev); 1654 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1655 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1656 u32 tmp; 1657 1658 if (enable) { 1659 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1660 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1661 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1662 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1663 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1664 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1665 1666 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1667 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1668 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1669 1670 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1671 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1672 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1673 } else { 1674 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1675 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1676 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1677 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1678 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1679 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1680 1681 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1682 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1683 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1684 } 1685 } 1686 1687 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1688 { 1689 struct drm_device *dev = encoder->dev; 1690 struct amdgpu_device *adev = drm_to_adev(dev); 1691 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1692 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1693 u32 tmp; 1694 1695 if (enable) { 1696 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1697 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1698 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1699 1700 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1701 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1702 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1703 1704 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1705 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1706 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1707 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1708 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1709 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1710 } else { 1711 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1712 } 1713 } 1714 1715 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1716 struct drm_display_mode *mode) 1717 { 1718 struct drm_device *dev = encoder->dev; 1719 struct amdgpu_device *adev = drm_to_adev(dev); 1720 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1721 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1722 struct drm_connector *connector; 1723 struct drm_connector_list_iter iter; 1724 struct amdgpu_connector *amdgpu_connector = NULL; 1725 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1726 int bpc = 8; 1727 1728 if (!dig || !dig->afmt) 1729 return; 1730 1731 drm_connector_list_iter_begin(dev, &iter); 1732 drm_for_each_connector_iter(connector, &iter) { 1733 if (connector->encoder == encoder) { 1734 amdgpu_connector = to_amdgpu_connector(connector); 1735 break; 1736 } 1737 } 1738 drm_connector_list_iter_end(&iter); 1739 1740 if (!amdgpu_connector) { 1741 DRM_ERROR("Couldn't find encoder's connector\n"); 1742 return; 1743 } 1744 1745 if (!dig->afmt->enabled) 1746 return; 1747 1748 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1749 if (!dig->afmt->pin) 1750 return; 1751 1752 if (encoder->crtc) { 1753 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1754 bpc = amdgpu_crtc->bpc; 1755 } 1756 1757 /* disable audio before setting up hw */ 1758 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1759 1760 dce_v6_0_audio_set_mute(encoder, true); 1761 dce_v6_0_audio_write_speaker_allocation(encoder); 1762 dce_v6_0_audio_write_sad_regs(encoder); 1763 dce_v6_0_audio_write_latency_fields(encoder, mode); 1764 if (em == ATOM_ENCODER_MODE_HDMI) { 1765 dce_v6_0_audio_set_dto(encoder, mode->clock); 1766 dce_v6_0_audio_set_vbi_packet(encoder); 1767 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1768 } else if (ENCODER_MODE_IS_DP(em)) { 1769 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1770 } 1771 dce_v6_0_audio_set_packet(encoder); 1772 dce_v6_0_audio_select_pin(encoder); 1773 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1774 dce_v6_0_audio_set_mute(encoder, false); 1775 if (em == ATOM_ENCODER_MODE_HDMI) { 1776 dce_v6_0_audio_hdmi_enable(encoder, 1); 1777 } else if (ENCODER_MODE_IS_DP(em)) { 1778 dce_v6_0_audio_dp_enable(encoder, 1); 1779 } 1780 1781 /* enable audio after setting up hw */ 1782 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1783 } 1784 1785 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1786 { 1787 struct drm_device *dev = encoder->dev; 1788 struct amdgpu_device *adev = drm_to_adev(dev); 1789 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1790 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1791 1792 if (!dig || !dig->afmt) 1793 return; 1794 1795 /* Silent, r600_hdmi_enable will raise WARN for us */ 1796 if (enable && dig->afmt->enabled) 1797 return; 1798 1799 if (!enable && !dig->afmt->enabled) 1800 return; 1801 1802 if (!enable && dig->afmt->pin) { 1803 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1804 dig->afmt->pin = NULL; 1805 } 1806 1807 dig->afmt->enabled = enable; 1808 1809 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1810 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1811 } 1812 1813 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1814 { 1815 int i, j; 1816 1817 for (i = 0; i < adev->mode_info.num_dig; i++) 1818 adev->mode_info.afmt[i] = NULL; 1819 1820 /* DCE6 has audio blocks tied to DIG encoders */ 1821 for (i = 0; i < adev->mode_info.num_dig; i++) { 1822 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1823 if (adev->mode_info.afmt[i]) { 1824 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1825 adev->mode_info.afmt[i]->id = i; 1826 } else { 1827 for (j = 0; j < i; j++) { 1828 kfree(adev->mode_info.afmt[j]); 1829 adev->mode_info.afmt[j] = NULL; 1830 } 1831 DRM_ERROR("Out of memory allocating afmt table\n"); 1832 return -ENOMEM; 1833 } 1834 } 1835 return 0; 1836 } 1837 1838 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1839 { 1840 int i; 1841 1842 for (i = 0; i < adev->mode_info.num_dig; i++) { 1843 kfree(adev->mode_info.afmt[i]); 1844 adev->mode_info.afmt[i] = NULL; 1845 } 1846 } 1847 1848 static const u32 vga_control_regs[6] = 1849 { 1850 mmD1VGA_CONTROL, 1851 mmD2VGA_CONTROL, 1852 mmD3VGA_CONTROL, 1853 mmD4VGA_CONTROL, 1854 mmD5VGA_CONTROL, 1855 mmD6VGA_CONTROL, 1856 }; 1857 1858 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1859 { 1860 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1861 struct drm_device *dev = crtc->dev; 1862 struct amdgpu_device *adev = drm_to_adev(dev); 1863 u32 vga_control; 1864 1865 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1866 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1867 } 1868 1869 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1870 { 1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1872 struct drm_device *dev = crtc->dev; 1873 struct amdgpu_device *adev = drm_to_adev(dev); 1874 1875 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1876 } 1877 1878 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1879 struct drm_framebuffer *fb, 1880 int x, int y, int atomic) 1881 { 1882 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1883 struct drm_device *dev = crtc->dev; 1884 struct amdgpu_device *adev = drm_to_adev(dev); 1885 struct drm_framebuffer *target_fb; 1886 struct drm_gem_object *obj; 1887 struct amdgpu_bo *abo; 1888 uint64_t fb_location, tiling_flags; 1889 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1890 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1891 u32 viewport_w, viewport_h; 1892 int r; 1893 bool bypass_lut = false; 1894 1895 /* no fb bound */ 1896 if (!atomic && !crtc->primary->fb) { 1897 DRM_DEBUG_KMS("No FB bound\n"); 1898 return 0; 1899 } 1900 1901 if (atomic) 1902 target_fb = fb; 1903 else 1904 target_fb = crtc->primary->fb; 1905 1906 /* If atomic, assume fb object is pinned & idle & fenced and 1907 * just update base pointers 1908 */ 1909 obj = target_fb->obj[0]; 1910 abo = gem_to_amdgpu_bo(obj); 1911 r = amdgpu_bo_reserve(abo, false); 1912 if (unlikely(r != 0)) 1913 return r; 1914 1915 if (!atomic) { 1916 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1917 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1918 if (unlikely(r != 0)) { 1919 amdgpu_bo_unreserve(abo); 1920 return -EINVAL; 1921 } 1922 } 1923 fb_location = amdgpu_bo_gpu_offset(abo); 1924 1925 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1926 amdgpu_bo_unreserve(abo); 1927 1928 switch (target_fb->format->format) { 1929 case DRM_FORMAT_C8: 1930 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1931 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1932 break; 1933 case DRM_FORMAT_XRGB4444: 1934 case DRM_FORMAT_ARGB4444: 1935 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1936 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1937 #ifdef __BIG_ENDIAN 1938 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1939 #endif 1940 break; 1941 case DRM_FORMAT_XRGB1555: 1942 case DRM_FORMAT_ARGB1555: 1943 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1944 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1945 #ifdef __BIG_ENDIAN 1946 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1947 #endif 1948 break; 1949 case DRM_FORMAT_BGRX5551: 1950 case DRM_FORMAT_BGRA5551: 1951 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1952 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1953 #ifdef __BIG_ENDIAN 1954 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1955 #endif 1956 break; 1957 case DRM_FORMAT_RGB565: 1958 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1959 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1960 #ifdef __BIG_ENDIAN 1961 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1962 #endif 1963 break; 1964 case DRM_FORMAT_XRGB8888: 1965 case DRM_FORMAT_ARGB8888: 1966 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1967 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1968 #ifdef __BIG_ENDIAN 1969 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1970 #endif 1971 break; 1972 case DRM_FORMAT_XRGB2101010: 1973 case DRM_FORMAT_ARGB2101010: 1974 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1975 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1976 #ifdef __BIG_ENDIAN 1977 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1978 #endif 1979 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1980 bypass_lut = true; 1981 break; 1982 case DRM_FORMAT_BGRX1010102: 1983 case DRM_FORMAT_BGRA1010102: 1984 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1985 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1986 #ifdef __BIG_ENDIAN 1987 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1988 #endif 1989 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1990 bypass_lut = true; 1991 break; 1992 case DRM_FORMAT_XBGR8888: 1993 case DRM_FORMAT_ABGR8888: 1994 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1995 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1996 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) | 1997 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT)); 1998 #ifdef __BIG_ENDIAN 1999 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2000 #endif 2001 break; 2002 default: 2003 DRM_ERROR("Unsupported screen format %p4cc\n", 2004 &target_fb->format->format); 2005 return -EINVAL; 2006 } 2007 2008 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2009 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2010 2011 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2012 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2013 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2014 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2015 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2016 2017 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 2018 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2019 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 2020 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 2021 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 2022 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 2023 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2024 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2025 } 2026 2027 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2028 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 2029 2030 dce_v6_0_vga_enable(crtc, false); 2031 2032 /* Make sure surface address is updated at vertical blank rather than 2033 * horizontal blank 2034 */ 2035 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2036 2037 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2038 upper_32_bits(fb_location)); 2039 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2040 upper_32_bits(fb_location)); 2041 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2042 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2043 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2044 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2045 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2046 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2047 2048 /* 2049 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2050 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2051 * retain the full precision throughout the pipeline. 2052 */ 2053 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2054 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2055 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2056 2057 if (bypass_lut) 2058 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2059 2060 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2061 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2062 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2063 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2064 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2065 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2066 2067 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2068 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2069 2070 dce_v6_0_grph_enable(crtc, true); 2071 2072 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2073 target_fb->height); 2074 x &= ~3; 2075 y &= ~1; 2076 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2077 (x << 16) | y); 2078 viewport_w = crtc->mode.hdisplay; 2079 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2080 2081 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2082 (viewport_w << 16) | viewport_h); 2083 2084 /* set pageflip to happen anywhere in vblank interval */ 2085 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2086 2087 if (!atomic && fb && fb != crtc->primary->fb) { 2088 abo = gem_to_amdgpu_bo(fb->obj[0]); 2089 r = amdgpu_bo_reserve(abo, true); 2090 if (unlikely(r != 0)) 2091 return r; 2092 amdgpu_bo_unpin(abo); 2093 amdgpu_bo_unreserve(abo); 2094 } 2095 2096 /* Bytes per pixel may have changed */ 2097 dce_v6_0_bandwidth_update(adev); 2098 2099 return 0; 2100 2101 } 2102 2103 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2104 struct drm_display_mode *mode) 2105 { 2106 struct drm_device *dev = crtc->dev; 2107 struct amdgpu_device *adev = drm_to_adev(dev); 2108 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2109 2110 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2111 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2112 DATA_FORMAT__INTERLEAVE_EN_MASK); 2113 else 2114 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2115 } 2116 2117 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2118 { 2119 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2120 struct drm_device *dev = crtc->dev; 2121 struct amdgpu_device *adev = drm_to_adev(dev); 2122 u16 *r, *g, *b; 2123 int i; 2124 2125 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2126 2127 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2128 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2129 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2130 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2131 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2132 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2133 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2134 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2135 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2136 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2137 2138 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2139 2140 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2141 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2142 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2143 2144 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2145 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2146 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2147 2148 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2149 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2150 2151 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2152 r = crtc->gamma_store; 2153 g = r + crtc->gamma_size; 2154 b = g + crtc->gamma_size; 2155 for (i = 0; i < 256; i++) { 2156 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2157 ((*r++ & 0xffc0) << 14) | 2158 ((*g++ & 0xffc0) << 4) | 2159 (*b++ >> 6)); 2160 } 2161 2162 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2163 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2164 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2165 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT) | 2166 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2167 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2168 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2169 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2170 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2171 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2172 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2173 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2174 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2175 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2176 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2177 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2178 2179 2180 } 2181 2182 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2183 { 2184 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2185 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2186 2187 switch (amdgpu_encoder->encoder_id) { 2188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2189 return dig->linkb ? 1 : 0; 2190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2191 return dig->linkb ? 3 : 2; 2192 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2193 return dig->linkb ? 5 : 4; 2194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2195 return 6; 2196 default: 2197 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2198 return 0; 2199 } 2200 } 2201 2202 /** 2203 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2204 * 2205 * @crtc: drm crtc 2206 * 2207 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2208 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2209 * monitors a dedicated PPLL must be used. If a particular board has 2210 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2211 * as there is no need to program the PLL itself. If we are not able to 2212 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2213 * avoid messing up an existing monitor. 2214 * 2215 * 2216 */ 2217 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2218 { 2219 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2220 struct drm_device *dev = crtc->dev; 2221 struct amdgpu_device *adev = drm_to_adev(dev); 2222 u32 pll_in_use; 2223 int pll; 2224 2225 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2226 if (adev->clock.dp_extclk) 2227 /* skip PPLL programming if using ext clock */ 2228 return ATOM_PPLL_INVALID; 2229 else 2230 return ATOM_PPLL0; 2231 } else { 2232 /* use the same PPLL for all monitors with the same clock */ 2233 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2234 if (pll != ATOM_PPLL_INVALID) 2235 return pll; 2236 } 2237 2238 /* PPLL1, and PPLL2 */ 2239 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2240 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2241 return ATOM_PPLL2; 2242 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2243 return ATOM_PPLL1; 2244 DRM_ERROR("unable to allocate a PPLL\n"); 2245 return ATOM_PPLL_INVALID; 2246 } 2247 2248 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2249 { 2250 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2251 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2252 uint32_t cur_lock; 2253 2254 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2255 if (lock) 2256 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2257 else 2258 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2259 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2260 } 2261 2262 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2263 { 2264 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2265 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2266 2267 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2268 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2269 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2270 } 2271 2272 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2273 { 2274 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2275 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2276 2277 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2278 upper_32_bits(amdgpu_crtc->cursor_addr)); 2279 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2280 lower_32_bits(amdgpu_crtc->cursor_addr)); 2281 2282 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2283 CUR_CONTROL__CURSOR_EN_MASK | 2284 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2285 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2286 } 2287 2288 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2289 int x, int y) 2290 { 2291 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2292 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2293 int xorigin = 0, yorigin = 0; 2294 2295 int w = amdgpu_crtc->cursor_width; 2296 2297 amdgpu_crtc->cursor_x = x; 2298 amdgpu_crtc->cursor_y = y; 2299 2300 /* avivo cursor are offset into the total surface */ 2301 x += crtc->x; 2302 y += crtc->y; 2303 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2304 2305 if (x < 0) { 2306 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2307 x = 0; 2308 } 2309 if (y < 0) { 2310 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2311 y = 0; 2312 } 2313 2314 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2315 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2316 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2317 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2318 2319 return 0; 2320 } 2321 2322 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2323 int x, int y) 2324 { 2325 int ret; 2326 2327 dce_v6_0_lock_cursor(crtc, true); 2328 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2329 dce_v6_0_lock_cursor(crtc, false); 2330 2331 return ret; 2332 } 2333 2334 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2335 struct drm_file *file_priv, 2336 uint32_t handle, 2337 uint32_t width, 2338 uint32_t height, 2339 int32_t hot_x, 2340 int32_t hot_y) 2341 { 2342 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2343 struct drm_gem_object *obj; 2344 struct amdgpu_bo *aobj; 2345 int ret; 2346 2347 if (!handle) { 2348 /* turn off cursor */ 2349 dce_v6_0_hide_cursor(crtc); 2350 obj = NULL; 2351 goto unpin; 2352 } 2353 2354 if ((width > amdgpu_crtc->max_cursor_width) || 2355 (height > amdgpu_crtc->max_cursor_height)) { 2356 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2357 return -EINVAL; 2358 } 2359 2360 obj = drm_gem_object_lookup(file_priv, handle); 2361 if (!obj) { 2362 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2363 return -ENOENT; 2364 } 2365 2366 aobj = gem_to_amdgpu_bo(obj); 2367 ret = amdgpu_bo_reserve(aobj, false); 2368 if (ret != 0) { 2369 drm_gem_object_put(obj); 2370 return ret; 2371 } 2372 2373 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2374 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2375 amdgpu_bo_unreserve(aobj); 2376 if (ret) { 2377 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2378 drm_gem_object_put(obj); 2379 return ret; 2380 } 2381 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2382 2383 dce_v6_0_lock_cursor(crtc, true); 2384 2385 if (width != amdgpu_crtc->cursor_width || 2386 height != amdgpu_crtc->cursor_height || 2387 hot_x != amdgpu_crtc->cursor_hot_x || 2388 hot_y != amdgpu_crtc->cursor_hot_y) { 2389 int x, y; 2390 2391 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2392 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2393 2394 dce_v6_0_cursor_move_locked(crtc, x, y); 2395 2396 amdgpu_crtc->cursor_width = width; 2397 amdgpu_crtc->cursor_height = height; 2398 amdgpu_crtc->cursor_hot_x = hot_x; 2399 amdgpu_crtc->cursor_hot_y = hot_y; 2400 } 2401 2402 dce_v6_0_show_cursor(crtc); 2403 dce_v6_0_lock_cursor(crtc, false); 2404 2405 unpin: 2406 if (amdgpu_crtc->cursor_bo) { 2407 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2408 ret = amdgpu_bo_reserve(aobj, true); 2409 if (likely(ret == 0)) { 2410 amdgpu_bo_unpin(aobj); 2411 amdgpu_bo_unreserve(aobj); 2412 } 2413 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2414 } 2415 2416 amdgpu_crtc->cursor_bo = obj; 2417 return 0; 2418 } 2419 2420 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2421 { 2422 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2423 2424 if (amdgpu_crtc->cursor_bo) { 2425 dce_v6_0_lock_cursor(crtc, true); 2426 2427 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2428 amdgpu_crtc->cursor_y); 2429 2430 dce_v6_0_show_cursor(crtc); 2431 dce_v6_0_lock_cursor(crtc, false); 2432 } 2433 } 2434 2435 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2436 u16 *blue, uint32_t size, 2437 struct drm_modeset_acquire_ctx *ctx) 2438 { 2439 dce_v6_0_crtc_load_lut(crtc); 2440 2441 return 0; 2442 } 2443 2444 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2445 { 2446 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2447 2448 drm_crtc_cleanup(crtc); 2449 kfree(amdgpu_crtc); 2450 } 2451 2452 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2453 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2454 .cursor_move = dce_v6_0_crtc_cursor_move, 2455 .gamma_set = dce_v6_0_crtc_gamma_set, 2456 .set_config = amdgpu_display_crtc_set_config, 2457 .destroy = dce_v6_0_crtc_destroy, 2458 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2459 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2460 .enable_vblank = amdgpu_enable_vblank_kms, 2461 .disable_vblank = amdgpu_disable_vblank_kms, 2462 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2463 }; 2464 2465 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2466 { 2467 struct drm_device *dev = crtc->dev; 2468 struct amdgpu_device *adev = drm_to_adev(dev); 2469 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2470 unsigned type; 2471 2472 switch (mode) { 2473 case DRM_MODE_DPMS_ON: 2474 amdgpu_crtc->enabled = true; 2475 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2476 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2477 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2478 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2479 amdgpu_crtc->crtc_id); 2480 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2481 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2482 drm_crtc_vblank_on(crtc); 2483 dce_v6_0_crtc_load_lut(crtc); 2484 break; 2485 case DRM_MODE_DPMS_STANDBY: 2486 case DRM_MODE_DPMS_SUSPEND: 2487 case DRM_MODE_DPMS_OFF: 2488 drm_crtc_vblank_off(crtc); 2489 if (amdgpu_crtc->enabled) 2490 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2491 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2492 amdgpu_crtc->enabled = false; 2493 break; 2494 } 2495 /* adjust pm to dpms */ 2496 amdgpu_dpm_compute_clocks(adev); 2497 } 2498 2499 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2500 { 2501 /* disable crtc pair power gating before programming */ 2502 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2503 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2504 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2505 } 2506 2507 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2508 { 2509 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2510 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2511 } 2512 2513 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2514 { 2515 2516 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2517 struct drm_device *dev = crtc->dev; 2518 struct amdgpu_device *adev = drm_to_adev(dev); 2519 struct amdgpu_atom_ss ss; 2520 int i; 2521 2522 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2523 if (crtc->primary->fb) { 2524 int r; 2525 struct amdgpu_bo *abo; 2526 2527 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2528 r = amdgpu_bo_reserve(abo, true); 2529 if (unlikely(r)) 2530 DRM_ERROR("failed to reserve abo before unpin\n"); 2531 else { 2532 amdgpu_bo_unpin(abo); 2533 amdgpu_bo_unreserve(abo); 2534 } 2535 } 2536 /* disable the GRPH */ 2537 dce_v6_0_grph_enable(crtc, false); 2538 2539 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2540 2541 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2542 if (adev->mode_info.crtcs[i] && 2543 adev->mode_info.crtcs[i]->enabled && 2544 i != amdgpu_crtc->crtc_id && 2545 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2546 /* one other crtc is using this pll don't turn 2547 * off the pll 2548 */ 2549 goto done; 2550 } 2551 } 2552 2553 switch (amdgpu_crtc->pll_id) { 2554 case ATOM_PPLL1: 2555 case ATOM_PPLL2: 2556 /* disable the ppll */ 2557 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2558 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2559 break; 2560 default: 2561 break; 2562 } 2563 done: 2564 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2565 amdgpu_crtc->adjusted_clock = 0; 2566 amdgpu_crtc->encoder = NULL; 2567 amdgpu_crtc->connector = NULL; 2568 } 2569 2570 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2571 struct drm_display_mode *mode, 2572 struct drm_display_mode *adjusted_mode, 2573 int x, int y, struct drm_framebuffer *old_fb) 2574 { 2575 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2576 2577 if (!amdgpu_crtc->adjusted_clock) 2578 return -EINVAL; 2579 2580 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2581 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2582 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2583 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2584 amdgpu_atombios_crtc_scaler_setup(crtc); 2585 dce_v6_0_cursor_reset(crtc); 2586 /* update the hw version fpr dpm */ 2587 amdgpu_crtc->hw_mode = *adjusted_mode; 2588 2589 return 0; 2590 } 2591 2592 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2593 const struct drm_display_mode *mode, 2594 struct drm_display_mode *adjusted_mode) 2595 { 2596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2597 struct drm_device *dev = crtc->dev; 2598 struct drm_encoder *encoder; 2599 2600 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2601 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2602 if (encoder->crtc == crtc) { 2603 amdgpu_crtc->encoder = encoder; 2604 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2605 break; 2606 } 2607 } 2608 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2609 amdgpu_crtc->encoder = NULL; 2610 amdgpu_crtc->connector = NULL; 2611 return false; 2612 } 2613 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2614 return false; 2615 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2616 return false; 2617 /* pick pll */ 2618 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2619 /* if we can't get a PPLL for a non-DP encoder, fail */ 2620 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2621 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2622 return false; 2623 2624 return true; 2625 } 2626 2627 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2628 struct drm_framebuffer *old_fb) 2629 { 2630 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2631 } 2632 2633 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2634 struct drm_framebuffer *fb, 2635 int x, int y, enum mode_set_atomic state) 2636 { 2637 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2638 } 2639 2640 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2641 .dpms = dce_v6_0_crtc_dpms, 2642 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2643 .mode_set = dce_v6_0_crtc_mode_set, 2644 .mode_set_base = dce_v6_0_crtc_set_base, 2645 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2646 .prepare = dce_v6_0_crtc_prepare, 2647 .commit = dce_v6_0_crtc_commit, 2648 .disable = dce_v6_0_crtc_disable, 2649 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2650 }; 2651 2652 static void dce_v6_0_panic_flush(struct drm_plane *plane) 2653 { 2654 struct drm_framebuffer *fb; 2655 struct amdgpu_crtc *amdgpu_crtc; 2656 struct amdgpu_device *adev; 2657 uint32_t fb_format; 2658 2659 if (!plane->fb) 2660 return; 2661 2662 fb = plane->fb; 2663 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2664 adev = drm_to_adev(fb->dev); 2665 2666 /* Disable DC tiling */ 2667 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2668 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; 2669 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2670 2671 } 2672 2673 static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { 2674 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2675 .panic_flush = dce_v6_0_panic_flush, 2676 }; 2677 2678 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2679 { 2680 struct amdgpu_crtc *amdgpu_crtc; 2681 2682 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2683 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2684 if (amdgpu_crtc == NULL) 2685 return -ENOMEM; 2686 2687 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2688 2689 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2690 amdgpu_crtc->crtc_id = index; 2691 adev->mode_info.crtcs[index] = amdgpu_crtc; 2692 2693 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2694 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2695 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2696 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2697 2698 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2699 2700 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2701 amdgpu_crtc->adjusted_clock = 0; 2702 amdgpu_crtc->encoder = NULL; 2703 amdgpu_crtc->connector = NULL; 2704 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2705 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); 2706 2707 return 0; 2708 } 2709 2710 static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) 2711 { 2712 struct amdgpu_device *adev = ip_block->adev; 2713 2714 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2715 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2716 2717 dce_v6_0_set_display_funcs(adev); 2718 2719 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2720 2721 switch (adev->asic_type) { 2722 case CHIP_TAHITI: 2723 case CHIP_PITCAIRN: 2724 case CHIP_VERDE: 2725 adev->mode_info.num_hpd = 6; 2726 adev->mode_info.num_dig = 6; 2727 break; 2728 case CHIP_OLAND: 2729 adev->mode_info.num_hpd = 2; 2730 adev->mode_info.num_dig = 2; 2731 break; 2732 default: 2733 return -EINVAL; 2734 } 2735 2736 dce_v6_0_set_irq_funcs(adev); 2737 2738 return 0; 2739 } 2740 2741 static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 2742 { 2743 int r, i; 2744 struct amdgpu_device *adev = ip_block->adev; 2745 2746 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2747 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2748 if (r) 2749 return r; 2750 } 2751 2752 for (i = 8; i < 20; i += 2) { 2753 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2754 if (r) 2755 return r; 2756 } 2757 2758 /* HPD hotplug */ 2759 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2760 if (r) 2761 return r; 2762 2763 adev->mode_info.mode_config_initialized = true; 2764 2765 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2766 adev_to_drm(adev)->mode_config.async_page_flip = true; 2767 adev_to_drm(adev)->mode_config.max_width = 16384; 2768 adev_to_drm(adev)->mode_config.max_height = 16384; 2769 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2770 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2771 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2772 2773 r = amdgpu_display_modeset_create_props(adev); 2774 if (r) 2775 return r; 2776 2777 adev_to_drm(adev)->mode_config.max_width = 16384; 2778 adev_to_drm(adev)->mode_config.max_height = 16384; 2779 2780 /* allocate crtcs */ 2781 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2782 r = dce_v6_0_crtc_init(adev, i); 2783 if (r) 2784 return r; 2785 } 2786 2787 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2788 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2789 else 2790 return -EINVAL; 2791 2792 /* setup afmt */ 2793 r = dce_v6_0_afmt_init(adev); 2794 if (r) 2795 return r; 2796 2797 r = dce_v6_0_audio_init(adev); 2798 if (r) 2799 return r; 2800 2801 /* Disable vblank IRQs aggressively for power-saving */ 2802 /* XXX: can this be enabled for DC? */ 2803 adev_to_drm(adev)->vblank_disable_immediate = true; 2804 2805 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2806 if (r) 2807 return r; 2808 2809 /* Pre-DCE11 */ 2810 INIT_DELAYED_WORK(&adev->hotplug_work, 2811 amdgpu_display_hotplug_work_func); 2812 2813 drm_kms_helper_poll_init(adev_to_drm(adev)); 2814 2815 return r; 2816 } 2817 2818 static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 2819 { 2820 struct amdgpu_device *adev = ip_block->adev; 2821 2822 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2823 2824 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2825 2826 dce_v6_0_audio_fini(adev); 2827 dce_v6_0_afmt_fini(adev); 2828 2829 drm_mode_config_cleanup(adev_to_drm(adev)); 2830 adev->mode_info.mode_config_initialized = false; 2831 2832 return 0; 2833 } 2834 2835 static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 2836 { 2837 int i; 2838 struct amdgpu_device *adev = ip_block->adev; 2839 2840 /* disable vga render */ 2841 dce_v6_0_set_vga_render_state(adev, false); 2842 /* init dig PHYs, disp eng pll */ 2843 amdgpu_atombios_encoder_init_dig(adev); 2844 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2845 2846 /* initialize hpd */ 2847 dce_v6_0_hpd_init(adev); 2848 2849 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2850 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2851 } 2852 2853 dce_v6_0_pageflip_interrupt_init(adev); 2854 2855 return 0; 2856 } 2857 2858 static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 2859 { 2860 int i; 2861 struct amdgpu_device *adev = ip_block->adev; 2862 2863 dce_v6_0_hpd_fini(adev); 2864 2865 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2866 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2867 } 2868 2869 dce_v6_0_pageflip_interrupt_fini(adev); 2870 2871 flush_delayed_work(&adev->hotplug_work); 2872 2873 return 0; 2874 } 2875 2876 static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) 2877 { 2878 struct amdgpu_device *adev = ip_block->adev; 2879 int r; 2880 2881 r = amdgpu_display_suspend_helper(adev); 2882 if (r) 2883 return r; 2884 adev->mode_info.bl_level = 2885 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2886 2887 return dce_v6_0_hw_fini(ip_block); 2888 } 2889 2890 static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) 2891 { 2892 struct amdgpu_device *adev = ip_block->adev; 2893 int ret; 2894 2895 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2896 adev->mode_info.bl_level); 2897 2898 ret = dce_v6_0_hw_init(ip_block); 2899 2900 /* turn on the BL */ 2901 if (adev->mode_info.bl_encoder) { 2902 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2903 adev->mode_info.bl_encoder); 2904 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2905 bl_level); 2906 } 2907 if (ret) 2908 return ret; 2909 2910 return amdgpu_display_resume_helper(adev); 2911 } 2912 2913 static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 2914 { 2915 return true; 2916 } 2917 2918 static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 2919 { 2920 u32 srbm_soft_reset = 0, tmp; 2921 struct amdgpu_device *adev = ip_block->adev; 2922 2923 if (dce_v6_0_is_display_hung(adev)) 2924 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2925 2926 if (srbm_soft_reset) { 2927 tmp = RREG32(mmSRBM_SOFT_RESET); 2928 tmp |= srbm_soft_reset; 2929 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2930 WREG32(mmSRBM_SOFT_RESET, tmp); 2931 tmp = RREG32(mmSRBM_SOFT_RESET); 2932 2933 udelay(50); 2934 2935 tmp &= ~srbm_soft_reset; 2936 WREG32(mmSRBM_SOFT_RESET, tmp); 2937 tmp = RREG32(mmSRBM_SOFT_RESET); 2938 2939 /* Wait a little for things to settle down */ 2940 udelay(50); 2941 } 2942 return 0; 2943 } 2944 2945 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2946 int crtc, 2947 enum amdgpu_interrupt_state state) 2948 { 2949 u32 reg_block, interrupt_mask; 2950 2951 if (crtc >= adev->mode_info.num_crtc) { 2952 DRM_DEBUG("invalid crtc %d\n", crtc); 2953 return; 2954 } 2955 2956 switch (crtc) { 2957 case 0: 2958 reg_block = CRTC0_REGISTER_OFFSET; 2959 break; 2960 case 1: 2961 reg_block = CRTC1_REGISTER_OFFSET; 2962 break; 2963 case 2: 2964 reg_block = CRTC2_REGISTER_OFFSET; 2965 break; 2966 case 3: 2967 reg_block = CRTC3_REGISTER_OFFSET; 2968 break; 2969 case 4: 2970 reg_block = CRTC4_REGISTER_OFFSET; 2971 break; 2972 case 5: 2973 reg_block = CRTC5_REGISTER_OFFSET; 2974 break; 2975 default: 2976 DRM_DEBUG("invalid crtc %d\n", crtc); 2977 return; 2978 } 2979 2980 switch (state) { 2981 case AMDGPU_IRQ_STATE_DISABLE: 2982 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2983 interrupt_mask &= ~INT_MASK__VBLANK_INT_MASK; 2984 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2985 break; 2986 case AMDGPU_IRQ_STATE_ENABLE: 2987 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2988 interrupt_mask |= INT_MASK__VBLANK_INT_MASK; 2989 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2990 break; 2991 default: 2992 break; 2993 } 2994 } 2995 2996 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2997 int crtc, 2998 enum amdgpu_interrupt_state state) 2999 { 3000 3001 } 3002 3003 static int dce_v6_0_set_hpd_irq_state(struct amdgpu_device *adev, 3004 struct amdgpu_irq_src *src, 3005 unsigned hpd, 3006 enum amdgpu_interrupt_state state) 3007 { 3008 u32 dc_hpd_int_cntl; 3009 3010 if (hpd >= adev->mode_info.num_hpd) { 3011 DRM_DEBUG("invalid hpd %d\n", hpd); 3012 return 0; 3013 } 3014 3015 switch (state) { 3016 case AMDGPU_IRQ_STATE_DISABLE: 3017 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3018 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3019 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); 3020 break; 3021 case AMDGPU_IRQ_STATE_ENABLE: 3022 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3023 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3024 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); 3025 break; 3026 default: 3027 break; 3028 } 3029 3030 return 0; 3031 } 3032 3033 static int dce_v6_0_set_crtc_irq_state(struct amdgpu_device *adev, 3034 struct amdgpu_irq_src *src, 3035 unsigned type, 3036 enum amdgpu_interrupt_state state) 3037 { 3038 switch (type) { 3039 case AMDGPU_CRTC_IRQ_VBLANK1: 3040 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3041 break; 3042 case AMDGPU_CRTC_IRQ_VBLANK2: 3043 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3044 break; 3045 case AMDGPU_CRTC_IRQ_VBLANK3: 3046 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3047 break; 3048 case AMDGPU_CRTC_IRQ_VBLANK4: 3049 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3050 break; 3051 case AMDGPU_CRTC_IRQ_VBLANK5: 3052 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3053 break; 3054 case AMDGPU_CRTC_IRQ_VBLANK6: 3055 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3056 break; 3057 case AMDGPU_CRTC_IRQ_VLINE1: 3058 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 3059 break; 3060 case AMDGPU_CRTC_IRQ_VLINE2: 3061 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 3062 break; 3063 case AMDGPU_CRTC_IRQ_VLINE3: 3064 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 3065 break; 3066 case AMDGPU_CRTC_IRQ_VLINE4: 3067 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 3068 break; 3069 case AMDGPU_CRTC_IRQ_VLINE5: 3070 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3071 break; 3072 case AMDGPU_CRTC_IRQ_VLINE6: 3073 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3074 break; 3075 default: 3076 break; 3077 } 3078 return 0; 3079 } 3080 3081 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3082 struct amdgpu_irq_src *source, 3083 struct amdgpu_iv_entry *entry) 3084 { 3085 unsigned crtc = entry->src_id - 1; 3086 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3087 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3088 crtc); 3089 3090 switch (entry->src_data[0]) { 3091 case 0: /* vblank */ 3092 if (disp_int & interrupt_status_offsets[crtc].vblank) 3093 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_STATUS__VBLANK_ACK_MASK); 3094 else 3095 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3096 3097 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3098 drm_handle_vblank(adev_to_drm(adev), crtc); 3099 } 3100 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3101 break; 3102 case 1: /* vline */ 3103 if (disp_int & interrupt_status_offsets[crtc].vline) 3104 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_STATUS__VLINE_ACK_MASK); 3105 else 3106 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3107 3108 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3109 break; 3110 default: 3111 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3112 break; 3113 } 3114 3115 return 0; 3116 } 3117 3118 static int dce_v6_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3119 struct amdgpu_irq_src *src, 3120 unsigned type, 3121 enum amdgpu_interrupt_state state) 3122 { 3123 u32 reg; 3124 3125 if (type >= adev->mode_info.num_crtc) { 3126 DRM_ERROR("invalid pageflip crtc %d\n", type); 3127 return -EINVAL; 3128 } 3129 3130 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3131 if (state == AMDGPU_IRQ_STATE_DISABLE) 3132 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3133 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3134 else 3135 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3136 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3137 3138 return 0; 3139 } 3140 3141 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3142 struct amdgpu_irq_src *source, 3143 struct amdgpu_iv_entry *entry) 3144 { 3145 unsigned long flags; 3146 unsigned crtc_id; 3147 struct amdgpu_crtc *amdgpu_crtc; 3148 struct amdgpu_flip_work *works; 3149 3150 crtc_id = (entry->src_id - 8) >> 1; 3151 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3152 3153 if (crtc_id >= adev->mode_info.num_crtc) { 3154 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3155 return -EINVAL; 3156 } 3157 3158 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3159 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3160 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3161 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3162 3163 /* IRQ could occur when in initial stage */ 3164 if (amdgpu_crtc == NULL) 3165 return 0; 3166 3167 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3168 works = amdgpu_crtc->pflip_works; 3169 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3170 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3171 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3172 amdgpu_crtc->pflip_status, 3173 AMDGPU_FLIP_SUBMITTED); 3174 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3175 return 0; 3176 } 3177 3178 /* page flip completed. clean up */ 3179 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3180 amdgpu_crtc->pflip_works = NULL; 3181 3182 /* wakeup usersapce */ 3183 if (works->event) 3184 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3185 3186 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3187 3188 drm_crtc_vblank_put(&amdgpu_crtc->base); 3189 schedule_work(&works->unpin_work); 3190 3191 return 0; 3192 } 3193 3194 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3195 struct amdgpu_irq_src *source, 3196 struct amdgpu_iv_entry *entry) 3197 { 3198 uint32_t disp_int, mask; 3199 unsigned hpd; 3200 3201 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3202 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3203 return 0; 3204 } 3205 3206 hpd = entry->src_data[0]; 3207 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3208 mask = interrupt_status_offsets[hpd].hpd; 3209 3210 if (disp_int & mask) { 3211 dce_v6_0_hpd_int_ack(adev, hpd); 3212 schedule_delayed_work(&adev->hotplug_work, 0); 3213 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3214 } 3215 3216 return 0; 3217 } 3218 3219 static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3220 enum amd_clockgating_state state) 3221 { 3222 return 0; 3223 } 3224 3225 static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3226 enum amd_powergating_state state) 3227 { 3228 return 0; 3229 } 3230 3231 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3232 .name = "dce_v6_0", 3233 .early_init = dce_v6_0_early_init, 3234 .sw_init = dce_v6_0_sw_init, 3235 .sw_fini = dce_v6_0_sw_fini, 3236 .hw_init = dce_v6_0_hw_init, 3237 .hw_fini = dce_v6_0_hw_fini, 3238 .suspend = dce_v6_0_suspend, 3239 .resume = dce_v6_0_resume, 3240 .is_idle = dce_v6_0_is_idle, 3241 .soft_reset = dce_v6_0_soft_reset, 3242 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3243 .set_powergating_state = dce_v6_0_set_powergating_state, 3244 }; 3245 3246 static void dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3247 struct drm_display_mode *mode, 3248 struct drm_display_mode *adjusted_mode) 3249 { 3250 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3251 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3252 3253 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3254 3255 /* need to call this here rather than in prepare() since we need some crtc info */ 3256 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3257 3258 /* set scaler clears this on some chips */ 3259 dce_v6_0_set_interleave(encoder->crtc, mode); 3260 3261 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3262 dce_v6_0_afmt_enable(encoder, true); 3263 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3264 } 3265 } 3266 3267 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3268 { 3269 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3270 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3271 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3272 3273 if ((amdgpu_encoder->active_device & 3274 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3275 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3276 ENCODER_OBJECT_ID_NONE)) { 3277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3278 if (dig) { 3279 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3280 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3281 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3282 } 3283 } 3284 3285 amdgpu_atombios_scratch_regs_lock(adev, true); 3286 3287 if (connector) { 3288 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3289 3290 /* select the clock/data port if it uses a router */ 3291 if (amdgpu_connector->router.cd_valid) 3292 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3293 3294 /* turn eDP panel on for mode set */ 3295 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3296 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3297 ATOM_TRANSMITTER_ACTION_POWER_ON); 3298 } 3299 3300 /* this is needed for the pll/ss setup to work correctly in some cases */ 3301 amdgpu_atombios_encoder_set_crtc_source(encoder); 3302 /* set up the FMT blocks */ 3303 dce_v6_0_program_fmt(encoder); 3304 } 3305 3306 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3307 { 3308 struct drm_device *dev = encoder->dev; 3309 struct amdgpu_device *adev = drm_to_adev(dev); 3310 3311 /* need to call this here as we need the crtc set up */ 3312 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3313 amdgpu_atombios_scratch_regs_lock(adev, false); 3314 } 3315 3316 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3317 { 3318 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3319 struct amdgpu_encoder_atom_dig *dig; 3320 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3321 3322 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3323 3324 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3325 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3326 dce_v6_0_afmt_enable(encoder, false); 3327 dig = amdgpu_encoder->enc_priv; 3328 dig->dig_encoder = -1; 3329 } 3330 amdgpu_encoder->active_device = 0; 3331 } 3332 3333 /* these are handled by the primary encoders */ 3334 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3335 { 3336 3337 } 3338 3339 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3340 { 3341 3342 } 3343 3344 static void dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3345 struct drm_display_mode *mode, 3346 struct drm_display_mode *adjusted_mode) 3347 { 3348 3349 } 3350 3351 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3352 { 3353 3354 } 3355 3356 static void dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3357 { 3358 3359 } 3360 3361 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3362 const struct drm_display_mode *mode, 3363 struct drm_display_mode *adjusted_mode) 3364 { 3365 return true; 3366 } 3367 3368 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3369 .dpms = dce_v6_0_ext_dpms, 3370 .mode_fixup = dce_v6_0_ext_mode_fixup, 3371 .prepare = dce_v6_0_ext_prepare, 3372 .mode_set = dce_v6_0_ext_mode_set, 3373 .commit = dce_v6_0_ext_commit, 3374 .disable = dce_v6_0_ext_disable, 3375 /* no detect for TMDS/LVDS yet */ 3376 }; 3377 3378 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3379 .dpms = amdgpu_atombios_encoder_dpms, 3380 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3381 .prepare = dce_v6_0_encoder_prepare, 3382 .mode_set = dce_v6_0_encoder_mode_set, 3383 .commit = dce_v6_0_encoder_commit, 3384 .disable = dce_v6_0_encoder_disable, 3385 .detect = amdgpu_atombios_encoder_dig_detect, 3386 }; 3387 3388 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3389 .dpms = amdgpu_atombios_encoder_dpms, 3390 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3391 .prepare = dce_v6_0_encoder_prepare, 3392 .mode_set = dce_v6_0_encoder_mode_set, 3393 .commit = dce_v6_0_encoder_commit, 3394 .detect = amdgpu_atombios_encoder_dac_detect, 3395 }; 3396 3397 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3398 { 3399 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3400 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3401 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3402 kfree(amdgpu_encoder->enc_priv); 3403 drm_encoder_cleanup(encoder); 3404 kfree(amdgpu_encoder); 3405 } 3406 3407 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3408 .destroy = dce_v6_0_encoder_destroy, 3409 }; 3410 3411 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3412 uint32_t encoder_enum, 3413 uint32_t supported_device, 3414 u16 caps) 3415 { 3416 struct drm_device *dev = adev_to_drm(adev); 3417 struct drm_encoder *encoder; 3418 struct amdgpu_encoder *amdgpu_encoder; 3419 3420 /* see if we already added it */ 3421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3422 amdgpu_encoder = to_amdgpu_encoder(encoder); 3423 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3424 amdgpu_encoder->devices |= supported_device; 3425 return; 3426 } 3427 } 3428 3429 /* add a new one */ 3430 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3431 if (!amdgpu_encoder) 3432 return; 3433 3434 encoder = &amdgpu_encoder->base; 3435 switch (adev->mode_info.num_crtc) { 3436 case 1: 3437 encoder->possible_crtcs = 0x1; 3438 break; 3439 case 2: 3440 default: 3441 encoder->possible_crtcs = 0x3; 3442 break; 3443 case 4: 3444 encoder->possible_crtcs = 0xf; 3445 break; 3446 case 6: 3447 encoder->possible_crtcs = 0x3f; 3448 break; 3449 } 3450 3451 amdgpu_encoder->enc_priv = NULL; 3452 amdgpu_encoder->encoder_enum = encoder_enum; 3453 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3454 amdgpu_encoder->devices = supported_device; 3455 amdgpu_encoder->rmx_type = RMX_OFF; 3456 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3457 amdgpu_encoder->is_ext_encoder = false; 3458 amdgpu_encoder->caps = caps; 3459 3460 switch (amdgpu_encoder->encoder_id) { 3461 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3462 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3463 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3464 DRM_MODE_ENCODER_DAC, NULL); 3465 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3466 break; 3467 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3468 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3469 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3470 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3471 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3472 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3473 amdgpu_encoder->rmx_type = RMX_FULL; 3474 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3475 DRM_MODE_ENCODER_LVDS, NULL); 3476 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3477 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3478 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3479 DRM_MODE_ENCODER_DAC, NULL); 3480 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3481 } else { 3482 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3483 DRM_MODE_ENCODER_TMDS, NULL); 3484 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3485 } 3486 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3487 break; 3488 case ENCODER_OBJECT_ID_SI170B: 3489 case ENCODER_OBJECT_ID_CH7303: 3490 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3491 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3492 case ENCODER_OBJECT_ID_TITFP513: 3493 case ENCODER_OBJECT_ID_VT1623: 3494 case ENCODER_OBJECT_ID_HDMI_SI1930: 3495 case ENCODER_OBJECT_ID_TRAVIS: 3496 case ENCODER_OBJECT_ID_NUTMEG: 3497 /* these are handled by the primary encoders */ 3498 amdgpu_encoder->is_ext_encoder = true; 3499 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3500 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3501 DRM_MODE_ENCODER_LVDS, NULL); 3502 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3503 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3504 DRM_MODE_ENCODER_DAC, NULL); 3505 else 3506 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3507 DRM_MODE_ENCODER_TMDS, NULL); 3508 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3509 break; 3510 } 3511 } 3512 3513 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3514 .bandwidth_update = &dce_v6_0_bandwidth_update, 3515 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3516 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3517 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3518 .hpd_sense = &dce_v6_0_hpd_sense, 3519 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3520 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3521 .page_flip = &dce_v6_0_page_flip, 3522 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3523 .add_encoder = &dce_v6_0_encoder_add, 3524 .add_connector = &amdgpu_connector_add, 3525 }; 3526 3527 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3528 { 3529 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3530 } 3531 3532 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3533 .set = dce_v6_0_set_crtc_irq_state, 3534 .process = dce_v6_0_crtc_irq, 3535 }; 3536 3537 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3538 .set = dce_v6_0_set_pageflip_irq_state, 3539 .process = dce_v6_0_pageflip_irq, 3540 }; 3541 3542 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3543 .set = dce_v6_0_set_hpd_irq_state, 3544 .process = dce_v6_0_hpd_irq, 3545 }; 3546 3547 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3548 { 3549 if (adev->mode_info.num_crtc > 0) 3550 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3551 else 3552 adev->crtc_irq.num_types = 0; 3553 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3554 3555 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3556 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3557 3558 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3559 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3560 } 3561 3562 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3563 { 3564 .type = AMD_IP_BLOCK_TYPE_DCE, 3565 .major = 6, 3566 .minor = 0, 3567 .rev = 0, 3568 .funcs = &dce_v6_0_ip_funcs, 3569 }; 3570 3571 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3572 { 3573 .type = AMD_IP_BLOCK_TYPE_DCE, 3574 .major = 6, 3575 .minor = 4, 3576 .rev = 0, 3577 .funcs = &dce_v6_0_ip_funcs, 3578 }; 3579