1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_modeset_helper.h> 29 #include <drm/drm_modeset_helper_vtables.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_atombios.h" 37 #include "atombios_crtc.h" 38 #include "atombios_encoders.h" 39 #include "amdgpu_pll.h" 40 #include "amdgpu_connectors.h" 41 #include "amdgpu_display.h" 42 43 #include "dce_v6_0.h" 44 #include "sid.h" 45 46 #include "bif/bif_3_0_d.h" 47 #include "bif/bif_3_0_sh_mask.h" 48 49 #include "oss/oss_1_0_d.h" 50 #include "oss/oss_1_0_sh_mask.h" 51 52 #include "gca/gfx_6_0_d.h" 53 #include "gca/gfx_6_0_sh_mask.h" 54 #include "gca/gfx_7_2_enum.h" 55 56 #include "gmc/gmc_6_0_d.h" 57 #include "gmc/gmc_6_0_sh_mask.h" 58 59 #include "dce/dce_6_0_d.h" 60 #include "dce/dce_6_0_sh_mask.h" 61 62 #include "si_enums.h" 63 64 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 65 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const u32 crtc_offsets[6] = 68 { 69 CRTC0_REGISTER_OFFSET, 70 CRTC1_REGISTER_OFFSET, 71 CRTC2_REGISTER_OFFSET, 72 CRTC3_REGISTER_OFFSET, 73 CRTC4_REGISTER_OFFSET, 74 CRTC5_REGISTER_OFFSET 75 }; 76 77 static const u32 hpd_offsets[] = 78 { 79 HPD0_REGISTER_OFFSET, 80 HPD1_REGISTER_OFFSET, 81 HPD2_REGISTER_OFFSET, 82 HPD3_REGISTER_OFFSET, 83 HPD4_REGISTER_OFFSET, 84 HPD5_REGISTER_OFFSET 85 }; 86 87 static const uint32_t dig_offsets[] = { 88 CRTC0_REGISTER_OFFSET, 89 CRTC1_REGISTER_OFFSET, 90 CRTC2_REGISTER_OFFSET, 91 CRTC3_REGISTER_OFFSET, 92 CRTC4_REGISTER_OFFSET, 93 CRTC5_REGISTER_OFFSET, 94 (0x13830 - 0x7030) >> 2, 95 }; 96 97 static const struct { 98 uint32_t reg; 99 uint32_t vblank; 100 uint32_t vline; 101 uint32_t hpd; 102 103 } interrupt_status_offsets[6] = { { 104 .reg = mmDISP_INTERRUPT_STATUS, 105 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 113 }, { 114 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 116 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 118 }, { 119 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 120 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 121 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 123 }, { 124 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 125 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 126 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 128 }, { 129 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 130 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 131 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 132 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 133 } }; 134 135 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 136 u32 block_offset, u32 reg) 137 { 138 unsigned long flags; 139 u32 r; 140 141 spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 143 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 144 spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 145 146 return r; 147 } 148 149 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 150 u32 block_offset, u32 reg, u32 v) 151 { 152 unsigned long flags; 153 154 spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 155 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 156 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 157 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 158 spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 159 } 160 161 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 162 { 163 if (crtc >= adev->mode_info.num_crtc) 164 return 0; 165 else 166 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 167 } 168 169 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 170 { 171 unsigned i; 172 173 /* Enable pflip interrupts */ 174 for (i = 0; i < adev->mode_info.num_crtc; i++) 175 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 176 } 177 178 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 179 { 180 unsigned i; 181 182 /* Disable pflip interrupts */ 183 for (i = 0; i < adev->mode_info.num_crtc; i++) 184 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 185 } 186 187 /** 188 * dce_v6_0_page_flip - pageflip callback. 189 * 190 * @adev: amdgpu_device pointer 191 * @crtc_id: crtc to cleanup pageflip on 192 * @crtc_base: new address of the crtc (GPU MC address) 193 * @async: asynchronous flip 194 * 195 * Does the actual pageflip (evergreen+). 196 * During vblank we take the crtc lock and wait for the update_pending 197 * bit to go high, when it does, we release the lock, and allow the 198 * double buffered update to take place. 199 * Returns the current update pending status. 200 */ 201 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 202 int crtc_id, u64 crtc_base, bool async) 203 { 204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 205 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 206 207 /* flip at hsync for async, default is vsync */ 208 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 209 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 210 /* update pitch */ 211 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 212 fb->pitches[0] / fb->format->cpp[0]); 213 /* update the scanout addresses */ 214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 215 upper_32_bits(crtc_base)); 216 /* writing to the low address triggers the update */ 217 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 218 (u32)crtc_base); 219 /* post the write */ 220 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 221 } 222 223 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 224 u32 *vbl, u32 *position) 225 { 226 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 227 return -EINVAL; 228 229 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 230 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 231 232 return 0; 233 } 234 235 /** 236 * dce_v6_0_hpd_sense - hpd sense callback. 237 * 238 * @adev: amdgpu_device pointer 239 * @hpd: hpd (hotplug detect) pin 240 * 241 * Checks if a digital monitor is connected (evergreen+). 242 * Returns true if connected, false if not connected. 243 */ 244 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 245 enum amdgpu_hpd_id hpd) 246 { 247 bool connected = false; 248 249 if (hpd >= adev->mode_info.num_hpd) 250 return connected; 251 252 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 253 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 254 connected = true; 255 256 return connected; 257 } 258 259 /** 260 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 261 * 262 * @adev: amdgpu_device pointer 263 * @hpd: hpd (hotplug detect) pin 264 * 265 * Set the polarity of the hpd pin (evergreen+). 266 */ 267 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 268 enum amdgpu_hpd_id hpd) 269 { 270 u32 tmp; 271 bool connected = dce_v6_0_hpd_sense(adev, hpd); 272 273 if (hpd >= adev->mode_info.num_hpd) 274 return; 275 276 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 277 if (connected) 278 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 279 else 280 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 281 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 282 } 283 284 static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, 285 int hpd) 286 { 287 u32 tmp; 288 289 if (hpd >= adev->mode_info.num_hpd) { 290 DRM_DEBUG("invalid hpd %d\n", hpd); 291 return; 292 } 293 294 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 295 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 296 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 297 } 298 299 /** 300 * dce_v6_0_hpd_init - hpd setup callback. 301 * 302 * @adev: amdgpu_device pointer 303 * 304 * Setup the hpd pins used by the card (evergreen+). 305 * Enable the pin, set the polarity, and enable the hpd interrupts. 306 */ 307 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 308 { 309 struct drm_device *dev = adev_to_drm(adev); 310 struct drm_connector *connector; 311 struct drm_connector_list_iter iter; 312 u32 tmp; 313 314 drm_connector_list_iter_begin(dev, &iter); 315 drm_for_each_connector_iter(connector, &iter) { 316 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 317 318 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 319 continue; 320 321 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 322 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 323 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 324 325 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 326 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 327 /* don't try to enable hpd on eDP or LVDS avoid breaking the 328 * aux dp channel on imac and help (but not completely fix) 329 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 330 * also avoid interrupt storms during dpms. 331 */ 332 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 333 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 334 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 335 continue; 336 } 337 338 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 339 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 340 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 341 } 342 drm_connector_list_iter_end(&iter); 343 } 344 345 /** 346 * dce_v6_0_hpd_fini - hpd tear down callback. 347 * 348 * @adev: amdgpu_device pointer 349 * 350 * Tear down the hpd pins used by the card (evergreen+). 351 * Disable the hpd interrupts. 352 */ 353 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 354 { 355 struct drm_device *dev = adev_to_drm(adev); 356 struct drm_connector *connector; 357 struct drm_connector_list_iter iter; 358 u32 tmp; 359 360 drm_connector_list_iter_begin(dev, &iter); 361 drm_for_each_connector_iter(connector, &iter) { 362 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 363 364 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 365 continue; 366 367 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 368 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 369 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 370 371 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 372 } 373 drm_connector_list_iter_end(&iter); 374 } 375 376 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 377 { 378 return mmDC_GPIO_HPD_A; 379 } 380 381 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 382 bool render) 383 { 384 if (!render) 385 WREG32(mmVGA_RENDER_CONTROL, 386 RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK); 387 } 388 389 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 390 { 391 switch (adev->asic_type) { 392 case CHIP_TAHITI: 393 case CHIP_PITCAIRN: 394 case CHIP_VERDE: 395 return 6; 396 case CHIP_OLAND: 397 return 2; 398 default: 399 return 0; 400 } 401 } 402 403 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 404 { 405 /*Disable VGA render and enabled crtc, if has DCE engine*/ 406 if (amdgpu_atombios_has_dce_engine_info(adev)) { 407 u32 tmp; 408 int crtc_enabled, i; 409 410 dce_v6_0_set_vga_render_state(adev, false); 411 412 /*Disable crtc*/ 413 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 414 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 415 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 416 if (crtc_enabled) { 417 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 418 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 419 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 420 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 421 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 422 } 423 } 424 } 425 } 426 427 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 428 { 429 struct drm_device *dev = encoder->dev; 430 struct amdgpu_device *adev = drm_to_adev(dev); 431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 432 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 433 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 434 int bpc = 0; 435 u32 tmp = 0; 436 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 437 438 if (connector) { 439 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 440 bpc = amdgpu_connector_get_monitor_bpc(connector); 441 dither = amdgpu_connector->dither; 442 } 443 444 /* LVDS FMT is set up by atom */ 445 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 446 return; 447 448 if (bpc == 0) 449 return; 450 451 452 switch (bpc) { 453 case 6: 454 if (dither == AMDGPU_FMT_DITHER_ENABLE) 455 /* XXX sort out optimal dither settings */ 456 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 457 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 458 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 459 else 460 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 461 break; 462 case 8: 463 if (dither == AMDGPU_FMT_DITHER_ENABLE) 464 /* XXX sort out optimal dither settings */ 465 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 466 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 467 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 468 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 469 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 470 else 471 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 472 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 473 break; 474 case 10: 475 default: 476 /* not needed */ 477 break; 478 } 479 480 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 481 } 482 483 /** 484 * si_get_number_of_dram_channels - get the number of dram channels 485 * 486 * @adev: amdgpu_device pointer 487 * 488 * Look up the number of video ram channels (CIK). 489 * Used for display watermark bandwidth calculations 490 * Returns the number of dram channels 491 */ 492 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 493 { 494 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 495 496 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 497 case 0: 498 default: 499 return 1; 500 case 1: 501 return 2; 502 case 2: 503 return 4; 504 case 3: 505 return 8; 506 case 4: 507 return 3; 508 case 5: 509 return 6; 510 case 6: 511 return 10; 512 case 7: 513 return 12; 514 case 8: 515 return 16; 516 } 517 } 518 519 struct dce6_wm_params { 520 u32 dram_channels; /* number of dram channels */ 521 u32 yclk; /* bandwidth per dram data pin in kHz */ 522 u32 sclk; /* engine clock in kHz */ 523 u32 disp_clk; /* display clock in kHz */ 524 u32 src_width; /* viewport width */ 525 u32 active_time; /* active display time in ns */ 526 u32 blank_time; /* blank time in ns */ 527 bool interlaced; /* mode is interlaced */ 528 fixed20_12 vsc; /* vertical scale ratio */ 529 u32 num_heads; /* number of active crtcs */ 530 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 531 u32 lb_size; /* line buffer allocated to pipe */ 532 u32 vtaps; /* vertical scaler taps */ 533 }; 534 535 /** 536 * dce_v6_0_dram_bandwidth - get the dram bandwidth 537 * 538 * @wm: watermark calculation data 539 * 540 * Calculate the raw dram bandwidth (CIK). 541 * Used for display watermark bandwidth calculations 542 * Returns the dram bandwidth in MBytes/s 543 */ 544 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 545 { 546 /* Calculate raw DRAM Bandwidth */ 547 fixed20_12 dram_efficiency; /* 0.7 */ 548 fixed20_12 yclk, dram_channels, bandwidth; 549 fixed20_12 a; 550 551 a.full = dfixed_const(1000); 552 yclk.full = dfixed_const(wm->yclk); 553 yclk.full = dfixed_div(yclk, a); 554 dram_channels.full = dfixed_const(wm->dram_channels * 4); 555 a.full = dfixed_const(10); 556 dram_efficiency.full = dfixed_const(7); 557 dram_efficiency.full = dfixed_div(dram_efficiency, a); 558 bandwidth.full = dfixed_mul(dram_channels, yclk); 559 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 560 561 return dfixed_trunc(bandwidth); 562 } 563 564 /** 565 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 566 * 567 * @wm: watermark calculation data 568 * 569 * Calculate the dram bandwidth used for display (CIK). 570 * Used for display watermark bandwidth calculations 571 * Returns the dram bandwidth for display in MBytes/s 572 */ 573 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 574 { 575 /* Calculate DRAM Bandwidth and the part allocated to display. */ 576 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 577 fixed20_12 yclk, dram_channels, bandwidth; 578 fixed20_12 a; 579 580 a.full = dfixed_const(1000); 581 yclk.full = dfixed_const(wm->yclk); 582 yclk.full = dfixed_div(yclk, a); 583 dram_channels.full = dfixed_const(wm->dram_channels * 4); 584 a.full = dfixed_const(10); 585 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 586 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 587 bandwidth.full = dfixed_mul(dram_channels, yclk); 588 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 589 590 return dfixed_trunc(bandwidth); 591 } 592 593 /** 594 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 595 * 596 * @wm: watermark calculation data 597 * 598 * Calculate the data return bandwidth used for display (CIK). 599 * Used for display watermark bandwidth calculations 600 * Returns the data return bandwidth in MBytes/s 601 */ 602 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 603 { 604 /* Calculate the display Data return Bandwidth */ 605 fixed20_12 return_efficiency; /* 0.8 */ 606 fixed20_12 sclk, bandwidth; 607 fixed20_12 a; 608 609 a.full = dfixed_const(1000); 610 sclk.full = dfixed_const(wm->sclk); 611 sclk.full = dfixed_div(sclk, a); 612 a.full = dfixed_const(10); 613 return_efficiency.full = dfixed_const(8); 614 return_efficiency.full = dfixed_div(return_efficiency, a); 615 a.full = dfixed_const(32); 616 bandwidth.full = dfixed_mul(a, sclk); 617 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 618 619 return dfixed_trunc(bandwidth); 620 } 621 622 /** 623 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 624 * 625 * @wm: watermark calculation data 626 * 627 * Calculate the dmif bandwidth used for display (CIK). 628 * Used for display watermark bandwidth calculations 629 * Returns the dmif bandwidth in MBytes/s 630 */ 631 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 632 { 633 /* Calculate the DMIF Request Bandwidth */ 634 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 635 fixed20_12 disp_clk, bandwidth; 636 fixed20_12 a, b; 637 638 a.full = dfixed_const(1000); 639 disp_clk.full = dfixed_const(wm->disp_clk); 640 disp_clk.full = dfixed_div(disp_clk, a); 641 a.full = dfixed_const(32); 642 b.full = dfixed_mul(a, disp_clk); 643 644 a.full = dfixed_const(10); 645 disp_clk_request_efficiency.full = dfixed_const(8); 646 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 647 648 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 649 650 return dfixed_trunc(bandwidth); 651 } 652 653 /** 654 * dce_v6_0_available_bandwidth - get the min available bandwidth 655 * 656 * @wm: watermark calculation data 657 * 658 * Calculate the min available bandwidth used for display (CIK). 659 * Used for display watermark bandwidth calculations 660 * Returns the min available bandwidth in MBytes/s 661 */ 662 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 663 { 664 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 665 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 666 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 667 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 668 669 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 670 } 671 672 /** 673 * dce_v6_0_average_bandwidth - get the average available bandwidth 674 * 675 * @wm: watermark calculation data 676 * 677 * Calculate the average available bandwidth used for display (CIK). 678 * Used for display watermark bandwidth calculations 679 * Returns the average available bandwidth in MBytes/s 680 */ 681 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 682 { 683 /* Calculate the display mode Average Bandwidth 684 * DisplayMode should contain the source and destination dimensions, 685 * timing, etc. 686 */ 687 fixed20_12 bpp; 688 fixed20_12 line_time; 689 fixed20_12 src_width; 690 fixed20_12 bandwidth; 691 fixed20_12 a; 692 693 a.full = dfixed_const(1000); 694 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 695 line_time.full = dfixed_div(line_time, a); 696 bpp.full = dfixed_const(wm->bytes_per_pixel); 697 src_width.full = dfixed_const(wm->src_width); 698 bandwidth.full = dfixed_mul(src_width, bpp); 699 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 700 bandwidth.full = dfixed_div(bandwidth, line_time); 701 702 return dfixed_trunc(bandwidth); 703 } 704 705 /** 706 * dce_v6_0_latency_watermark - get the latency watermark 707 * 708 * @wm: watermark calculation data 709 * 710 * Calculate the latency watermark (CIK). 711 * Used for display watermark bandwidth calculations 712 * Returns the latency watermark in ns 713 */ 714 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 715 { 716 /* First calculate the latency in ns */ 717 u32 mc_latency = 2000; /* 2000 ns. */ 718 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 719 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 720 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 721 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 722 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 723 (wm->num_heads * cursor_line_pair_return_time); 724 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 725 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 726 u32 tmp, dmif_size = 12288; 727 fixed20_12 a, b, c; 728 729 if (wm->num_heads == 0) 730 return 0; 731 732 a.full = dfixed_const(2); 733 b.full = dfixed_const(1); 734 if ((wm->vsc.full > a.full) || 735 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 736 (wm->vtaps >= 5) || 737 ((wm->vsc.full >= a.full) && wm->interlaced)) 738 max_src_lines_per_dst_line = 4; 739 else 740 max_src_lines_per_dst_line = 2; 741 742 a.full = dfixed_const(available_bandwidth); 743 b.full = dfixed_const(wm->num_heads); 744 a.full = dfixed_div(a, b); 745 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 746 tmp = min(dfixed_trunc(a), tmp); 747 748 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 749 750 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 751 b.full = dfixed_const(1000); 752 c.full = dfixed_const(lb_fill_bw); 753 b.full = dfixed_div(c, b); 754 a.full = dfixed_div(a, b); 755 line_fill_time = dfixed_trunc(a); 756 757 if (line_fill_time < wm->active_time) 758 return latency; 759 else 760 return latency + (line_fill_time - wm->active_time); 761 762 } 763 764 /** 765 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 766 * average and available dram bandwidth 767 * 768 * @wm: watermark calculation data 769 * 770 * Check if the display average bandwidth fits in the display 771 * dram bandwidth (CIK). 772 * Used for display watermark bandwidth calculations 773 * Returns true if the display fits, false if not. 774 */ 775 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 776 { 777 if (dce_v6_0_average_bandwidth(wm) <= 778 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 779 return true; 780 else 781 return false; 782 } 783 784 /** 785 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 786 * average and available bandwidth 787 * 788 * @wm: watermark calculation data 789 * 790 * Check if the display average bandwidth fits in the display 791 * available bandwidth (CIK). 792 * Used for display watermark bandwidth calculations 793 * Returns true if the display fits, false if not. 794 */ 795 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 796 { 797 if (dce_v6_0_average_bandwidth(wm) <= 798 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 799 return true; 800 else 801 return false; 802 } 803 804 /** 805 * dce_v6_0_check_latency_hiding - check latency hiding 806 * 807 * @wm: watermark calculation data 808 * 809 * Check latency hiding (CIK). 810 * Used for display watermark bandwidth calculations 811 * Returns true if the display fits, false if not. 812 */ 813 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 814 { 815 u32 lb_partitions = wm->lb_size / wm->src_width; 816 u32 line_time = wm->active_time + wm->blank_time; 817 u32 latency_tolerant_lines; 818 u32 latency_hiding; 819 fixed20_12 a; 820 821 a.full = dfixed_const(1); 822 if (wm->vsc.full > a.full) 823 latency_tolerant_lines = 1; 824 else { 825 if (lb_partitions <= (wm->vtaps + 1)) 826 latency_tolerant_lines = 1; 827 else 828 latency_tolerant_lines = 2; 829 } 830 831 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 832 833 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 834 return true; 835 else 836 return false; 837 } 838 839 /** 840 * dce_v6_0_program_watermarks - program display watermarks 841 * 842 * @adev: amdgpu_device pointer 843 * @amdgpu_crtc: the selected display controller 844 * @lb_size: line buffer size 845 * @num_heads: number of display controllers in use 846 * 847 * Calculate and program the display watermarks for the 848 * selected display controller (CIK). 849 */ 850 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 851 struct amdgpu_crtc *amdgpu_crtc, 852 u32 lb_size, u32 num_heads) 853 { 854 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 855 struct dce6_wm_params wm_low, wm_high; 856 u32 dram_channels; 857 u32 active_time; 858 u32 line_time = 0; 859 u32 latency_watermark_a = 0, latency_watermark_b = 0; 860 u32 priority_a_mark = 0, priority_b_mark = 0; 861 u32 priority_a_cnt = PRIORITY_OFF; 862 u32 priority_b_cnt = PRIORITY_OFF; 863 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 864 fixed20_12 a, b, c; 865 866 if (amdgpu_crtc->base.enabled && num_heads && mode) { 867 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 868 (u32)mode->clock); 869 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 870 (u32)mode->clock); 871 line_time = min_t(u32, line_time, 65535); 872 priority_a_cnt = 0; 873 priority_b_cnt = 0; 874 875 dram_channels = si_get_number_of_dram_channels(adev); 876 877 /* watermark for high clocks */ 878 if (adev->pm.dpm_enabled) { 879 wm_high.yclk = 880 amdgpu_dpm_get_mclk(adev, false) * 10; 881 wm_high.sclk = 882 amdgpu_dpm_get_sclk(adev, false) * 10; 883 } else { 884 wm_high.yclk = adev->pm.current_mclk * 10; 885 wm_high.sclk = adev->pm.current_sclk * 10; 886 } 887 888 wm_high.disp_clk = mode->clock; 889 wm_high.src_width = mode->crtc_hdisplay; 890 wm_high.active_time = active_time; 891 wm_high.blank_time = line_time - wm_high.active_time; 892 wm_high.interlaced = false; 893 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 894 wm_high.interlaced = true; 895 wm_high.vsc = amdgpu_crtc->vsc; 896 wm_high.vtaps = 1; 897 if (amdgpu_crtc->rmx_type != RMX_OFF) 898 wm_high.vtaps = 2; 899 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 900 wm_high.lb_size = lb_size; 901 wm_high.dram_channels = dram_channels; 902 wm_high.num_heads = num_heads; 903 904 /* watermark for low clocks */ 905 if (adev->pm.dpm_enabled) { 906 wm_low.yclk = 907 amdgpu_dpm_get_mclk(adev, true) * 10; 908 wm_low.sclk = 909 amdgpu_dpm_get_sclk(adev, true) * 10; 910 } else { 911 wm_low.yclk = adev->pm.current_mclk * 10; 912 wm_low.sclk = adev->pm.current_sclk * 10; 913 } 914 915 wm_low.disp_clk = mode->clock; 916 wm_low.src_width = mode->crtc_hdisplay; 917 wm_low.active_time = active_time; 918 wm_low.blank_time = line_time - wm_low.active_time; 919 wm_low.interlaced = false; 920 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 921 wm_low.interlaced = true; 922 wm_low.vsc = amdgpu_crtc->vsc; 923 wm_low.vtaps = 1; 924 if (amdgpu_crtc->rmx_type != RMX_OFF) 925 wm_low.vtaps = 2; 926 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 927 wm_low.lb_size = lb_size; 928 wm_low.dram_channels = dram_channels; 929 wm_low.num_heads = num_heads; 930 931 /* set for high clocks */ 932 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535); 933 /* set for low clocks */ 934 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535); 935 936 /* possibly force display priority to high */ 937 /* should really do this at mode validation time... */ 938 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 939 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 940 !dce_v6_0_check_latency_hiding(&wm_high) || 941 (adev->mode_info.disp_priority == 2)) { 942 DRM_DEBUG_KMS("force priority to high\n"); 943 priority_a_cnt |= PRIORITY_ALWAYS_ON; 944 priority_b_cnt |= PRIORITY_ALWAYS_ON; 945 } 946 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 947 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 948 !dce_v6_0_check_latency_hiding(&wm_low) || 949 (adev->mode_info.disp_priority == 2)) { 950 DRM_DEBUG_KMS("force priority to high\n"); 951 priority_a_cnt |= PRIORITY_ALWAYS_ON; 952 priority_b_cnt |= PRIORITY_ALWAYS_ON; 953 } 954 955 a.full = dfixed_const(1000); 956 b.full = dfixed_const(mode->clock); 957 b.full = dfixed_div(b, a); 958 c.full = dfixed_const(latency_watermark_a); 959 c.full = dfixed_mul(c, b); 960 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 961 c.full = dfixed_div(c, a); 962 a.full = dfixed_const(16); 963 c.full = dfixed_div(c, a); 964 priority_a_mark = dfixed_trunc(c); 965 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 966 967 a.full = dfixed_const(1000); 968 b.full = dfixed_const(mode->clock); 969 b.full = dfixed_div(b, a); 970 c.full = dfixed_const(latency_watermark_b); 971 c.full = dfixed_mul(c, b); 972 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 973 c.full = dfixed_div(c, a); 974 a.full = dfixed_const(16); 975 c.full = dfixed_div(c, a); 976 priority_b_mark = dfixed_trunc(c); 977 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 978 979 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 980 } 981 982 /* select wm A */ 983 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 984 tmp = arb_control3; 985 tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 986 tmp |= (1 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 987 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 988 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 989 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 990 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 991 /* select wm B */ 992 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 993 tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 994 tmp |= (2 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT); 995 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 996 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 997 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 998 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 999 /* restore original selection */ 1000 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1001 1002 /* write the priority marks */ 1003 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1004 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1005 1006 /* save values for DPM */ 1007 amdgpu_crtc->line_time = line_time; 1008 1009 /* Save number of lines the linebuffer leads before the scanout */ 1010 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1011 } 1012 1013 /* watermark setup */ 1014 /** 1015 * dce_v6_0_line_buffer_adjust - Set up the line buffer 1016 * 1017 * @adev: amdgpu_device pointer 1018 * @amdgpu_crtc: the selected display controller 1019 * @mode: the current display mode on the selected display 1020 * controller 1021 * @other_mode: the display mode of another display controller 1022 * that may be sharing the line buffer 1023 * 1024 * Setup up the line buffer allocation for 1025 * the selected display controller (CIK). 1026 * Returns the line buffer size in pixels. 1027 */ 1028 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1029 struct amdgpu_crtc *amdgpu_crtc, 1030 struct drm_display_mode *mode, 1031 struct drm_display_mode *other_mode) 1032 { 1033 u32 tmp, buffer_alloc, i; 1034 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1035 /* 1036 * Line Buffer Setup 1037 * There are 3 line buffers, each one shared by 2 display controllers. 1038 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1039 * the display controllers. The paritioning is done via one of four 1040 * preset allocations specified in bits 21:20: 1041 * 0 - half lb 1042 * 2 - whole lb, other crtc must be disabled 1043 */ 1044 /* this can get tricky if we have two large displays on a paired group 1045 * of crtcs. Ideally for multiple large displays we'd assign them to 1046 * non-linked crtcs for maximum line buffer allocation. 1047 */ 1048 if (amdgpu_crtc->base.enabled && mode) { 1049 if (other_mode) { 1050 tmp = 0; /* 1/2 */ 1051 buffer_alloc = 1; 1052 } else { 1053 tmp = 2; /* whole */ 1054 buffer_alloc = 2; 1055 } 1056 } else { 1057 tmp = 0; 1058 buffer_alloc = 0; 1059 } 1060 1061 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1062 (tmp << DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT)); 1063 1064 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1065 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1066 for (i = 0; i < adev->usec_timeout; i++) { 1067 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1068 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1069 break; 1070 udelay(1); 1071 } 1072 1073 if (amdgpu_crtc->base.enabled && mode) { 1074 switch (tmp) { 1075 case 0: 1076 default: 1077 return 4096 * 2; 1078 case 2: 1079 return 8192 * 2; 1080 } 1081 } 1082 1083 /* controller not enabled, so no lb used */ 1084 return 0; 1085 } 1086 1087 1088 /** 1089 * dce_v6_0_bandwidth_update - program display watermarks 1090 * 1091 * @adev: amdgpu_device pointer 1092 * 1093 * Calculate and program the display watermarks and line 1094 * buffer allocation (CIK). 1095 */ 1096 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1097 { 1098 struct drm_display_mode *mode0 = NULL; 1099 struct drm_display_mode *mode1 = NULL; 1100 u32 num_heads = 0, lb_size; 1101 int i; 1102 1103 if (!adev->mode_info.mode_config_initialized) 1104 return; 1105 1106 amdgpu_display_update_priority(adev); 1107 1108 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1109 if (adev->mode_info.crtcs[i]->base.enabled) 1110 num_heads++; 1111 } 1112 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1113 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1114 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1115 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1116 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1117 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1118 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1119 } 1120 } 1121 1122 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1123 { 1124 int i; 1125 u32 tmp; 1126 1127 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1128 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1129 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1130 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1131 PORT_CONNECTIVITY)) 1132 adev->mode_info.audio.pin[i].connected = false; 1133 else 1134 adev->mode_info.audio.pin[i].connected = true; 1135 } 1136 1137 } 1138 1139 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1140 { 1141 int i; 1142 1143 dce_v6_0_audio_get_connected_pins(adev); 1144 1145 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1146 if (adev->mode_info.audio.pin[i].connected) 1147 return &adev->mode_info.audio.pin[i]; 1148 } 1149 DRM_ERROR("No connected audio pins found!\n"); 1150 return NULL; 1151 } 1152 1153 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1154 { 1155 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1156 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1157 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1158 1159 if (!dig || !dig->afmt || !dig->afmt->pin) 1160 return; 1161 1162 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1163 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1164 dig->afmt->pin->id)); 1165 } 1166 1167 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1168 struct drm_display_mode *mode) 1169 { 1170 struct drm_device *dev = encoder->dev; 1171 struct amdgpu_device *adev = drm_to_adev(dev); 1172 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1173 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1174 struct drm_connector *connector; 1175 struct drm_connector_list_iter iter; 1176 struct amdgpu_connector *amdgpu_connector = NULL; 1177 int interlace = 0; 1178 u32 tmp; 1179 1180 drm_connector_list_iter_begin(dev, &iter); 1181 drm_for_each_connector_iter(connector, &iter) { 1182 if (connector->encoder == encoder) { 1183 amdgpu_connector = to_amdgpu_connector(connector); 1184 break; 1185 } 1186 } 1187 drm_connector_list_iter_end(&iter); 1188 1189 if (!amdgpu_connector) { 1190 DRM_ERROR("Couldn't find encoder's connector\n"); 1191 return; 1192 } 1193 1194 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1195 interlace = 1; 1196 1197 if (connector->latency_present[interlace]) { 1198 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1199 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1200 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1201 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1202 } else { 1203 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1204 VIDEO_LIPSYNC, 0); 1205 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1206 AUDIO_LIPSYNC, 0); 1207 } 1208 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1209 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1210 } 1211 1212 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1213 { 1214 struct drm_device *dev = encoder->dev; 1215 struct amdgpu_device *adev = drm_to_adev(dev); 1216 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1217 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1218 struct drm_connector *connector; 1219 struct drm_connector_list_iter iter; 1220 struct amdgpu_connector *amdgpu_connector = NULL; 1221 u8 *sadb = NULL; 1222 int sad_count; 1223 u32 tmp; 1224 1225 drm_connector_list_iter_begin(dev, &iter); 1226 drm_for_each_connector_iter(connector, &iter) { 1227 if (connector->encoder == encoder) { 1228 amdgpu_connector = to_amdgpu_connector(connector); 1229 break; 1230 } 1231 } 1232 drm_connector_list_iter_end(&iter); 1233 1234 if (!amdgpu_connector) { 1235 DRM_ERROR("Couldn't find encoder's connector\n"); 1236 return; 1237 } 1238 1239 sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); 1240 if (sad_count < 0) { 1241 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1242 sad_count = 0; 1243 } 1244 1245 /* program the speaker allocation */ 1246 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1247 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1248 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1249 HDMI_CONNECTION, 0); 1250 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1251 DP_CONNECTION, 0); 1252 1253 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1254 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1255 DP_CONNECTION, 1); 1256 else 1257 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1258 HDMI_CONNECTION, 1); 1259 1260 if (sad_count) 1261 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1262 SPEAKER_ALLOCATION, sadb[0]); 1263 else 1264 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1265 SPEAKER_ALLOCATION, 5); /* stereo */ 1266 1267 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1268 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1269 1270 kfree(sadb); 1271 } 1272 1273 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1274 { 1275 struct drm_device *dev = encoder->dev; 1276 struct amdgpu_device *adev = drm_to_adev(dev); 1277 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1278 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1279 u32 offset; 1280 struct drm_connector *connector; 1281 struct drm_connector_list_iter iter; 1282 struct amdgpu_connector *amdgpu_connector = NULL; 1283 struct cea_sad *sads; 1284 int i, sad_count; 1285 1286 static const u16 eld_reg_to_type[][2] = { 1287 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1288 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1289 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1290 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1291 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1292 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1293 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1294 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1295 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1296 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1297 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1298 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1299 }; 1300 1301 if (!dig || !dig->afmt || !dig->afmt->pin) 1302 return; 1303 1304 offset = dig->afmt->pin->offset; 1305 1306 drm_connector_list_iter_begin(dev, &iter); 1307 drm_for_each_connector_iter(connector, &iter) { 1308 if (connector->encoder == encoder) { 1309 amdgpu_connector = to_amdgpu_connector(connector); 1310 break; 1311 } 1312 } 1313 drm_connector_list_iter_end(&iter); 1314 1315 if (!amdgpu_connector) { 1316 DRM_ERROR("Couldn't find encoder's connector\n"); 1317 return; 1318 } 1319 1320 sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); 1321 if (sad_count < 0) 1322 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1323 if (sad_count <= 0) 1324 return; 1325 1326 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1327 u32 value = 0; 1328 u8 stereo_freqs = 0; 1329 int max_channels = -1; 1330 int j; 1331 1332 for (j = 0; j < sad_count; j++) { 1333 struct cea_sad *sad = &sads[j]; 1334 1335 if (sad->format == eld_reg_to_type[i][1]) { 1336 if (sad->channels > max_channels) { 1337 value = (sad->channels << 1338 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1339 (sad->byte2 << 1340 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1341 (sad->freq << 1342 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1343 max_channels = sad->channels; 1344 } 1345 1346 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1347 stereo_freqs |= sad->freq; 1348 else 1349 break; 1350 } 1351 } 1352 1353 value |= (stereo_freqs << 1354 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1355 1356 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1357 } 1358 1359 kfree(sads); 1360 } 1361 1362 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1363 struct amdgpu_audio_pin *pin, 1364 bool enable) 1365 { 1366 if (!pin) 1367 return; 1368 1369 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1370 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1371 } 1372 1373 static const u32 pin_offsets[7] = 1374 { 1375 AUD0_REGISTER_OFFSET, 1376 AUD1_REGISTER_OFFSET, 1377 AUD2_REGISTER_OFFSET, 1378 AUD3_REGISTER_OFFSET, 1379 AUD4_REGISTER_OFFSET, 1380 AUD5_REGISTER_OFFSET, 1381 AUD6_REGISTER_OFFSET, 1382 }; 1383 1384 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1385 { 1386 int i; 1387 1388 if (!amdgpu_audio) 1389 return 0; 1390 1391 adev->mode_info.audio.enabled = true; 1392 1393 switch (adev->asic_type) { 1394 case CHIP_TAHITI: 1395 case CHIP_PITCAIRN: 1396 case CHIP_VERDE: 1397 default: 1398 adev->mode_info.audio.num_pins = 6; 1399 break; 1400 case CHIP_OLAND: 1401 adev->mode_info.audio.num_pins = 2; 1402 break; 1403 } 1404 1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1406 adev->mode_info.audio.pin[i].channels = -1; 1407 adev->mode_info.audio.pin[i].rate = -1; 1408 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1409 adev->mode_info.audio.pin[i].status_bits = 0; 1410 adev->mode_info.audio.pin[i].category_code = 0; 1411 adev->mode_info.audio.pin[i].connected = false; 1412 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1413 adev->mode_info.audio.pin[i].id = i; 1414 /* disable audio. it will be set up later */ 1415 /* XXX remove once we switch to ip funcs */ 1416 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1417 } 1418 1419 return 0; 1420 } 1421 1422 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1423 { 1424 if (!amdgpu_audio) 1425 return; 1426 1427 if (!adev->mode_info.audio.enabled) 1428 return; 1429 1430 adev->mode_info.audio.enabled = false; 1431 } 1432 1433 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1434 { 1435 struct drm_device *dev = encoder->dev; 1436 struct amdgpu_device *adev = drm_to_adev(dev); 1437 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1438 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1439 u32 tmp; 1440 1441 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1442 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1443 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1444 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1445 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1446 } 1447 1448 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1449 uint32_t clock, int bpc) 1450 { 1451 struct drm_device *dev = encoder->dev; 1452 struct amdgpu_device *adev = drm_to_adev(dev); 1453 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1454 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1455 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1456 u32 tmp; 1457 1458 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1459 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1461 bpc > 8 ? 0 : 1); 1462 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1463 1464 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1465 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1466 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1467 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1468 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1469 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1470 1471 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1472 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1473 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1474 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1475 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1476 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1477 1478 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1479 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1480 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1481 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1482 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1483 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1484 } 1485 1486 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1487 struct drm_display_mode *mode) 1488 { 1489 struct drm_device *dev = encoder->dev; 1490 struct amdgpu_device *adev = drm_to_adev(dev); 1491 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1492 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1493 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1494 struct hdmi_avi_infoframe frame; 1495 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1496 uint8_t *payload = buffer + 3; 1497 uint8_t *header = buffer; 1498 ssize_t err; 1499 u32 tmp; 1500 1501 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1502 if (err < 0) { 1503 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1504 return; 1505 } 1506 1507 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1508 if (err < 0) { 1509 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1510 return; 1511 } 1512 1513 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1514 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1515 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1516 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1517 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1518 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1519 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1520 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1521 1522 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1523 /* anything other than 0 */ 1524 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1525 HDMI_AUDIO_INFO_LINE, 2); 1526 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1527 } 1528 1529 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1530 { 1531 struct drm_device *dev = encoder->dev; 1532 struct amdgpu_device *adev = drm_to_adev(dev); 1533 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1534 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1535 u32 tmp; 1536 1537 /* 1538 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1539 * Express [24MHz / target pixel clock] as an exact rational 1540 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1541 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1542 */ 1543 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1544 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1545 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1546 if (em == ATOM_ENCODER_MODE_HDMI) { 1547 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1548 DCCG_AUDIO_DTO_SEL, 0); 1549 } else if (ENCODER_MODE_IS_DP(em)) { 1550 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1551 DCCG_AUDIO_DTO_SEL, 1); 1552 } 1553 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1554 if (em == ATOM_ENCODER_MODE_HDMI) { 1555 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1556 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1557 } else if (ENCODER_MODE_IS_DP(em)) { 1558 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1559 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1560 } 1561 } 1562 1563 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1564 { 1565 struct drm_device *dev = encoder->dev; 1566 struct amdgpu_device *adev = drm_to_adev(dev); 1567 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1568 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1569 u32 tmp; 1570 1571 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1572 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1573 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1574 1575 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1576 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1577 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1578 1579 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1580 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1581 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1582 1583 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1584 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1585 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1586 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1587 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1588 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1589 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1590 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1591 1592 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1593 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1594 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1595 1596 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1597 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1598 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1599 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1600 1601 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1602 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1603 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1604 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1605 } 1606 1607 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1608 { 1609 struct drm_device *dev = encoder->dev; 1610 struct amdgpu_device *adev = drm_to_adev(dev); 1611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1612 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1613 u32 tmp; 1614 1615 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1616 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1617 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1618 } 1619 1620 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1621 { 1622 struct drm_device *dev = encoder->dev; 1623 struct amdgpu_device *adev = drm_to_adev(dev); 1624 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1625 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1626 u32 tmp; 1627 1628 if (enable) { 1629 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1630 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1631 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1632 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1633 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1634 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1635 1636 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1637 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1638 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1639 1640 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1641 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1642 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1643 } else { 1644 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1645 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1646 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1647 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1648 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1649 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1650 1651 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1652 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1653 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1654 } 1655 } 1656 1657 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1658 { 1659 struct drm_device *dev = encoder->dev; 1660 struct amdgpu_device *adev = drm_to_adev(dev); 1661 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1662 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1663 u32 tmp; 1664 1665 if (enable) { 1666 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1667 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1668 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1669 1670 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1671 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1672 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1673 1674 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1675 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1676 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1677 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1678 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1679 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1680 } else { 1681 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1682 } 1683 } 1684 1685 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1686 struct drm_display_mode *mode) 1687 { 1688 struct drm_device *dev = encoder->dev; 1689 struct amdgpu_device *adev = drm_to_adev(dev); 1690 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1691 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1692 struct drm_connector *connector; 1693 struct drm_connector_list_iter iter; 1694 struct amdgpu_connector *amdgpu_connector = NULL; 1695 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1696 int bpc = 8; 1697 1698 if (!dig || !dig->afmt) 1699 return; 1700 1701 drm_connector_list_iter_begin(dev, &iter); 1702 drm_for_each_connector_iter(connector, &iter) { 1703 if (connector->encoder == encoder) { 1704 amdgpu_connector = to_amdgpu_connector(connector); 1705 break; 1706 } 1707 } 1708 drm_connector_list_iter_end(&iter); 1709 1710 if (!amdgpu_connector) { 1711 DRM_ERROR("Couldn't find encoder's connector\n"); 1712 return; 1713 } 1714 1715 if (!dig->afmt->enabled) 1716 return; 1717 1718 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1719 if (!dig->afmt->pin) 1720 return; 1721 1722 if (encoder->crtc) { 1723 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1724 bpc = amdgpu_crtc->bpc; 1725 } 1726 1727 /* disable audio before setting up hw */ 1728 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1729 1730 dce_v6_0_audio_set_mute(encoder, true); 1731 dce_v6_0_audio_write_speaker_allocation(encoder); 1732 dce_v6_0_audio_write_sad_regs(encoder); 1733 dce_v6_0_audio_write_latency_fields(encoder, mode); 1734 if (em == ATOM_ENCODER_MODE_HDMI) { 1735 dce_v6_0_audio_set_dto(encoder, mode->clock); 1736 dce_v6_0_audio_set_vbi_packet(encoder); 1737 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1738 } else if (ENCODER_MODE_IS_DP(em)) { 1739 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1740 } 1741 dce_v6_0_audio_set_packet(encoder); 1742 dce_v6_0_audio_select_pin(encoder); 1743 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1744 dce_v6_0_audio_set_mute(encoder, false); 1745 if (em == ATOM_ENCODER_MODE_HDMI) { 1746 dce_v6_0_audio_hdmi_enable(encoder, 1); 1747 } else if (ENCODER_MODE_IS_DP(em)) { 1748 dce_v6_0_audio_dp_enable(encoder, 1); 1749 } 1750 1751 /* enable audio after setting up hw */ 1752 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1753 } 1754 1755 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1756 { 1757 struct drm_device *dev = encoder->dev; 1758 struct amdgpu_device *adev = drm_to_adev(dev); 1759 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1760 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1761 1762 if (!dig || !dig->afmt) 1763 return; 1764 1765 /* Silent, r600_hdmi_enable will raise WARN for us */ 1766 if (enable && dig->afmt->enabled) 1767 return; 1768 1769 if (!enable && !dig->afmt->enabled) 1770 return; 1771 1772 if (!enable && dig->afmt->pin) { 1773 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1774 dig->afmt->pin = NULL; 1775 } 1776 1777 dig->afmt->enabled = enable; 1778 1779 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1780 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1781 } 1782 1783 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1784 { 1785 int i, j; 1786 1787 for (i = 0; i < adev->mode_info.num_dig; i++) 1788 adev->mode_info.afmt[i] = NULL; 1789 1790 /* DCE6 has audio blocks tied to DIG encoders */ 1791 for (i = 0; i < adev->mode_info.num_dig; i++) { 1792 adev->mode_info.afmt[i] = kzalloc_obj(struct amdgpu_afmt); 1793 if (adev->mode_info.afmt[i]) { 1794 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1795 adev->mode_info.afmt[i]->id = i; 1796 } else { 1797 for (j = 0; j < i; j++) { 1798 kfree(adev->mode_info.afmt[j]); 1799 adev->mode_info.afmt[j] = NULL; 1800 } 1801 DRM_ERROR("Out of memory allocating afmt table\n"); 1802 return -ENOMEM; 1803 } 1804 } 1805 return 0; 1806 } 1807 1808 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1809 { 1810 int i; 1811 1812 for (i = 0; i < adev->mode_info.num_dig; i++) { 1813 kfree(adev->mode_info.afmt[i]); 1814 adev->mode_info.afmt[i] = NULL; 1815 } 1816 } 1817 1818 static const u32 vga_control_regs[6] = 1819 { 1820 mmD1VGA_CONTROL, 1821 mmD2VGA_CONTROL, 1822 mmD3VGA_CONTROL, 1823 mmD4VGA_CONTROL, 1824 mmD5VGA_CONTROL, 1825 mmD6VGA_CONTROL, 1826 }; 1827 1828 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1829 { 1830 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1831 struct drm_device *dev = crtc->dev; 1832 struct amdgpu_device *adev = drm_to_adev(dev); 1833 u32 vga_control; 1834 1835 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1836 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1837 } 1838 1839 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1840 { 1841 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1842 struct drm_device *dev = crtc->dev; 1843 struct amdgpu_device *adev = drm_to_adev(dev); 1844 1845 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1846 } 1847 1848 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1849 struct drm_framebuffer *fb, 1850 int x, int y) 1851 { 1852 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1853 struct drm_device *dev = crtc->dev; 1854 struct amdgpu_device *adev = drm_to_adev(dev); 1855 struct drm_framebuffer *target_fb; 1856 struct drm_gem_object *obj; 1857 struct amdgpu_bo *abo; 1858 uint64_t fb_location, tiling_flags; 1859 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1860 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1861 u32 viewport_w, viewport_h; 1862 int r; 1863 bool bypass_lut = false; 1864 1865 /* no fb bound */ 1866 if (!crtc->primary->fb) { 1867 DRM_DEBUG_KMS("No FB bound\n"); 1868 return 0; 1869 } 1870 1871 target_fb = crtc->primary->fb; 1872 1873 /* If atomic, assume fb object is pinned & idle & fenced and 1874 * just update base pointers 1875 */ 1876 obj = target_fb->obj[0]; 1877 abo = gem_to_amdgpu_bo(obj); 1878 r = amdgpu_bo_reserve(abo, false); 1879 if (unlikely(r != 0)) 1880 return r; 1881 1882 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1883 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1884 if (unlikely(r != 0)) { 1885 amdgpu_bo_unreserve(abo); 1886 return -EINVAL; 1887 } 1888 fb_location = amdgpu_bo_gpu_offset(abo); 1889 1890 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1891 amdgpu_bo_unreserve(abo); 1892 1893 switch (target_fb->format->format) { 1894 case DRM_FORMAT_C8: 1895 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1896 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1897 break; 1898 case DRM_FORMAT_XRGB4444: 1899 case DRM_FORMAT_ARGB4444: 1900 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1901 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1902 #ifdef __BIG_ENDIAN 1903 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1904 #endif 1905 break; 1906 case DRM_FORMAT_XRGB1555: 1907 case DRM_FORMAT_ARGB1555: 1908 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1909 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1910 #ifdef __BIG_ENDIAN 1911 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1912 #endif 1913 break; 1914 case DRM_FORMAT_BGRX5551: 1915 case DRM_FORMAT_BGRA5551: 1916 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1917 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1918 #ifdef __BIG_ENDIAN 1919 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1920 #endif 1921 break; 1922 case DRM_FORMAT_RGB565: 1923 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1924 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1925 #ifdef __BIG_ENDIAN 1926 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1927 #endif 1928 break; 1929 case DRM_FORMAT_XRGB8888: 1930 case DRM_FORMAT_ARGB8888: 1931 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1932 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1933 #ifdef __BIG_ENDIAN 1934 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1935 #endif 1936 break; 1937 case DRM_FORMAT_XRGB2101010: 1938 case DRM_FORMAT_ARGB2101010: 1939 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1940 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1941 #ifdef __BIG_ENDIAN 1942 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1943 #endif 1944 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1945 bypass_lut = true; 1946 break; 1947 case DRM_FORMAT_BGRX1010102: 1948 case DRM_FORMAT_BGRA1010102: 1949 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1950 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1951 #ifdef __BIG_ENDIAN 1952 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1953 #endif 1954 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1955 bypass_lut = true; 1956 break; 1957 case DRM_FORMAT_XBGR8888: 1958 case DRM_FORMAT_ABGR8888: 1959 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1960 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1961 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) | 1962 (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT)); 1963 #ifdef __BIG_ENDIAN 1964 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1965 #endif 1966 break; 1967 default: 1968 DRM_ERROR("Unsupported screen format %p4cc\n", 1969 &target_fb->format->format); 1970 return -EINVAL; 1971 } 1972 1973 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1974 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1975 1976 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1977 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1978 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1979 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1980 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1981 1982 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 1983 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 1984 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 1985 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 1986 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 1987 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 1988 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1989 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 1990 } 1991 1992 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1993 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 1994 1995 dce_v6_0_vga_enable(crtc, false); 1996 1997 /* Make sure surface address is updated at vertical blank rather than 1998 * horizontal blank 1999 */ 2000 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2001 2002 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2003 upper_32_bits(fb_location)); 2004 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2005 upper_32_bits(fb_location)); 2006 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2007 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2008 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2009 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2010 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2011 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2012 2013 /* 2014 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2015 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2016 * retain the full precision throughout the pipeline. 2017 */ 2018 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2019 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2020 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2021 2022 if (bypass_lut) 2023 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2024 2025 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2026 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2027 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2028 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2029 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2030 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2031 2032 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2033 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2034 2035 dce_v6_0_grph_enable(crtc, true); 2036 2037 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2038 target_fb->height); 2039 x &= ~3; 2040 y &= ~1; 2041 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2042 (x << 16) | y); 2043 viewport_w = crtc->mode.hdisplay; 2044 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2045 2046 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2047 (viewport_w << 16) | viewport_h); 2048 2049 /* set pageflip to happen anywhere in vblank interval */ 2050 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2051 2052 if (fb && fb != crtc->primary->fb) { 2053 abo = gem_to_amdgpu_bo(fb->obj[0]); 2054 r = amdgpu_bo_reserve(abo, true); 2055 if (unlikely(r != 0)) 2056 return r; 2057 amdgpu_bo_unpin(abo); 2058 amdgpu_bo_unreserve(abo); 2059 } 2060 2061 /* Bytes per pixel may have changed */ 2062 dce_v6_0_bandwidth_update(adev); 2063 2064 return 0; 2065 2066 } 2067 2068 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2069 struct drm_display_mode *mode) 2070 { 2071 struct drm_device *dev = crtc->dev; 2072 struct amdgpu_device *adev = drm_to_adev(dev); 2073 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2074 2075 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2076 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2077 DATA_FORMAT__INTERLEAVE_EN_MASK); 2078 else 2079 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2080 } 2081 2082 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2083 { 2084 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2085 struct drm_device *dev = crtc->dev; 2086 struct amdgpu_device *adev = drm_to_adev(dev); 2087 u16 *r, *g, *b; 2088 int i; 2089 2090 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2091 2092 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2093 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2094 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2095 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2096 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2097 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2098 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2099 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2100 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2101 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2102 2103 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2104 2105 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2106 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2107 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2108 2109 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2110 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2111 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2112 2113 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2114 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2115 2116 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2117 r = crtc->gamma_store; 2118 g = r + crtc->gamma_size; 2119 b = g + crtc->gamma_size; 2120 for (i = 0; i < 256; i++) { 2121 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2122 ((*r++ & 0xffc0) << 14) | 2123 ((*g++ & 0xffc0) << 4) | 2124 (*b++ >> 6)); 2125 } 2126 2127 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2128 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2129 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2130 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT) | 2131 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2132 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2133 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2134 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2135 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2136 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2137 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2138 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2139 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2140 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2141 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2142 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2143 2144 2145 } 2146 2147 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2148 { 2149 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2150 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2151 2152 switch (amdgpu_encoder->encoder_id) { 2153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2154 return dig->linkb ? 1 : 0; 2155 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2156 return dig->linkb ? 3 : 2; 2157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2158 return dig->linkb ? 5 : 4; 2159 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2160 return 6; 2161 default: 2162 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2163 return 0; 2164 } 2165 } 2166 2167 /** 2168 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2169 * 2170 * @crtc: drm crtc 2171 * 2172 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2173 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2174 * monitors a dedicated PPLL must be used. If a particular board has 2175 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2176 * as there is no need to program the PLL itself. If we are not able to 2177 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2178 * avoid messing up an existing monitor. 2179 * 2180 * 2181 */ 2182 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2183 { 2184 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2185 struct drm_device *dev = crtc->dev; 2186 struct amdgpu_device *adev = drm_to_adev(dev); 2187 u32 pll_in_use; 2188 int pll; 2189 2190 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2191 if (adev->clock.dp_extclk) 2192 /* skip PPLL programming if using ext clock */ 2193 return ATOM_PPLL_INVALID; 2194 else 2195 return ATOM_PPLL0; 2196 } else { 2197 /* use the same PPLL for all monitors with the same clock */ 2198 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2199 if (pll != ATOM_PPLL_INVALID) 2200 return pll; 2201 } 2202 2203 /* PPLL1, and PPLL2 */ 2204 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2205 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2206 return ATOM_PPLL2; 2207 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2208 return ATOM_PPLL1; 2209 DRM_ERROR("unable to allocate a PPLL\n"); 2210 return ATOM_PPLL_INVALID; 2211 } 2212 2213 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2214 { 2215 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2216 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2217 uint32_t cur_lock; 2218 2219 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2220 if (lock) 2221 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2222 else 2223 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2224 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2225 } 2226 2227 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2228 { 2229 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2230 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2231 2232 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2233 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2234 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2235 } 2236 2237 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2238 { 2239 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2240 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2241 2242 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2243 upper_32_bits(amdgpu_crtc->cursor_addr)); 2244 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2245 lower_32_bits(amdgpu_crtc->cursor_addr)); 2246 2247 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2248 CUR_CONTROL__CURSOR_EN_MASK | 2249 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2250 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2251 } 2252 2253 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2254 int x, int y) 2255 { 2256 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2257 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2258 int xorigin = 0, yorigin = 0; 2259 2260 int w = amdgpu_crtc->cursor_width; 2261 2262 amdgpu_crtc->cursor_x = x; 2263 amdgpu_crtc->cursor_y = y; 2264 2265 /* avivo cursor are offset into the total surface */ 2266 x += crtc->x; 2267 y += crtc->y; 2268 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2269 2270 if (x < 0) { 2271 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2272 x = 0; 2273 } 2274 if (y < 0) { 2275 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2276 y = 0; 2277 } 2278 2279 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2280 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2281 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2282 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2283 2284 return 0; 2285 } 2286 2287 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2288 int x, int y) 2289 { 2290 int ret; 2291 2292 dce_v6_0_lock_cursor(crtc, true); 2293 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2294 dce_v6_0_lock_cursor(crtc, false); 2295 2296 return ret; 2297 } 2298 2299 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2300 struct drm_file *file_priv, 2301 uint32_t handle, 2302 uint32_t width, 2303 uint32_t height, 2304 int32_t hot_x, 2305 int32_t hot_y) 2306 { 2307 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2308 struct drm_gem_object *obj; 2309 struct amdgpu_bo *aobj; 2310 int ret; 2311 2312 if (!handle) { 2313 /* turn off cursor */ 2314 dce_v6_0_hide_cursor(crtc); 2315 obj = NULL; 2316 goto unpin; 2317 } 2318 2319 if ((width > amdgpu_crtc->max_cursor_width) || 2320 (height > amdgpu_crtc->max_cursor_height)) { 2321 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2322 return -EINVAL; 2323 } 2324 2325 obj = drm_gem_object_lookup(file_priv, handle); 2326 if (!obj) { 2327 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2328 return -ENOENT; 2329 } 2330 2331 aobj = gem_to_amdgpu_bo(obj); 2332 ret = amdgpu_bo_reserve(aobj, false); 2333 if (ret != 0) { 2334 drm_gem_object_put(obj); 2335 return ret; 2336 } 2337 2338 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2339 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2340 amdgpu_bo_unreserve(aobj); 2341 if (ret) { 2342 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2343 drm_gem_object_put(obj); 2344 return ret; 2345 } 2346 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2347 2348 dce_v6_0_lock_cursor(crtc, true); 2349 2350 if (width != amdgpu_crtc->cursor_width || 2351 height != amdgpu_crtc->cursor_height || 2352 hot_x != amdgpu_crtc->cursor_hot_x || 2353 hot_y != amdgpu_crtc->cursor_hot_y) { 2354 int x, y; 2355 2356 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2357 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2358 2359 dce_v6_0_cursor_move_locked(crtc, x, y); 2360 2361 amdgpu_crtc->cursor_width = width; 2362 amdgpu_crtc->cursor_height = height; 2363 amdgpu_crtc->cursor_hot_x = hot_x; 2364 amdgpu_crtc->cursor_hot_y = hot_y; 2365 } 2366 2367 dce_v6_0_show_cursor(crtc); 2368 dce_v6_0_lock_cursor(crtc, false); 2369 2370 unpin: 2371 if (amdgpu_crtc->cursor_bo) { 2372 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2373 ret = amdgpu_bo_reserve(aobj, true); 2374 if (likely(ret == 0)) { 2375 amdgpu_bo_unpin(aobj); 2376 amdgpu_bo_unreserve(aobj); 2377 } 2378 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2379 } 2380 2381 amdgpu_crtc->cursor_bo = obj; 2382 return 0; 2383 } 2384 2385 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2386 { 2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2388 2389 if (amdgpu_crtc->cursor_bo) { 2390 dce_v6_0_lock_cursor(crtc, true); 2391 2392 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2393 amdgpu_crtc->cursor_y); 2394 2395 dce_v6_0_show_cursor(crtc); 2396 dce_v6_0_lock_cursor(crtc, false); 2397 } 2398 } 2399 2400 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2401 u16 *blue, uint32_t size, 2402 struct drm_modeset_acquire_ctx *ctx) 2403 { 2404 dce_v6_0_crtc_load_lut(crtc); 2405 2406 return 0; 2407 } 2408 2409 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2410 { 2411 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2412 2413 drm_crtc_cleanup(crtc); 2414 kfree(amdgpu_crtc); 2415 } 2416 2417 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2418 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2419 .cursor_move = dce_v6_0_crtc_cursor_move, 2420 .gamma_set = dce_v6_0_crtc_gamma_set, 2421 .set_config = amdgpu_display_crtc_set_config, 2422 .destroy = dce_v6_0_crtc_destroy, 2423 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2424 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2425 .enable_vblank = amdgpu_enable_vblank_kms, 2426 .disable_vblank = amdgpu_disable_vblank_kms, 2427 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2428 }; 2429 2430 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2431 { 2432 struct drm_device *dev = crtc->dev; 2433 struct amdgpu_device *adev = drm_to_adev(dev); 2434 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2435 unsigned type; 2436 2437 switch (mode) { 2438 case DRM_MODE_DPMS_ON: 2439 amdgpu_crtc->enabled = true; 2440 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2441 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2442 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2443 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2444 amdgpu_crtc->crtc_id); 2445 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2446 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2447 drm_crtc_vblank_on(crtc); 2448 dce_v6_0_crtc_load_lut(crtc); 2449 break; 2450 case DRM_MODE_DPMS_STANDBY: 2451 case DRM_MODE_DPMS_SUSPEND: 2452 case DRM_MODE_DPMS_OFF: 2453 drm_crtc_vblank_off(crtc); 2454 if (amdgpu_crtc->enabled) 2455 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2456 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2457 amdgpu_crtc->enabled = false; 2458 break; 2459 } 2460 /* adjust pm to dpms */ 2461 amdgpu_dpm_compute_clocks(adev); 2462 } 2463 2464 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2465 { 2466 /* disable crtc pair power gating before programming */ 2467 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2468 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2469 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2470 } 2471 2472 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2473 { 2474 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2475 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2476 } 2477 2478 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2479 { 2480 2481 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2482 struct drm_device *dev = crtc->dev; 2483 struct amdgpu_device *adev = drm_to_adev(dev); 2484 struct amdgpu_atom_ss ss; 2485 int i; 2486 2487 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2488 if (crtc->primary->fb) { 2489 int r; 2490 struct amdgpu_bo *abo; 2491 2492 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2493 r = amdgpu_bo_reserve(abo, true); 2494 if (unlikely(r)) 2495 DRM_ERROR("failed to reserve abo before unpin\n"); 2496 else { 2497 amdgpu_bo_unpin(abo); 2498 amdgpu_bo_unreserve(abo); 2499 } 2500 } 2501 /* disable the GRPH */ 2502 dce_v6_0_grph_enable(crtc, false); 2503 2504 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2505 2506 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2507 if (adev->mode_info.crtcs[i] && 2508 adev->mode_info.crtcs[i]->enabled && 2509 i != amdgpu_crtc->crtc_id && 2510 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2511 /* one other crtc is using this pll don't turn 2512 * off the pll 2513 */ 2514 goto done; 2515 } 2516 } 2517 2518 switch (amdgpu_crtc->pll_id) { 2519 case ATOM_PPLL1: 2520 case ATOM_PPLL2: 2521 /* disable the ppll */ 2522 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2523 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2524 break; 2525 default: 2526 break; 2527 } 2528 done: 2529 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2530 amdgpu_crtc->adjusted_clock = 0; 2531 amdgpu_crtc->encoder = NULL; 2532 amdgpu_crtc->connector = NULL; 2533 } 2534 2535 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2536 struct drm_display_mode *mode, 2537 struct drm_display_mode *adjusted_mode, 2538 int x, int y, struct drm_framebuffer *old_fb) 2539 { 2540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2541 2542 if (!amdgpu_crtc->adjusted_clock) 2543 return -EINVAL; 2544 2545 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2546 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2547 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); 2548 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2549 amdgpu_atombios_crtc_scaler_setup(crtc); 2550 dce_v6_0_cursor_reset(crtc); 2551 /* update the hw version fpr dpm */ 2552 amdgpu_crtc->hw_mode = *adjusted_mode; 2553 2554 return 0; 2555 } 2556 2557 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2558 const struct drm_display_mode *mode, 2559 struct drm_display_mode *adjusted_mode) 2560 { 2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2562 struct drm_device *dev = crtc->dev; 2563 struct drm_encoder *encoder; 2564 2565 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2567 if (encoder->crtc == crtc) { 2568 amdgpu_crtc->encoder = encoder; 2569 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2570 break; 2571 } 2572 } 2573 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2574 amdgpu_crtc->encoder = NULL; 2575 amdgpu_crtc->connector = NULL; 2576 return false; 2577 } 2578 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2579 return false; 2580 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2581 return false; 2582 /* pick pll */ 2583 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2584 /* if we can't get a PPLL for a non-DP encoder, fail */ 2585 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2586 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2587 return false; 2588 2589 return true; 2590 } 2591 2592 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2593 struct drm_framebuffer *old_fb) 2594 { 2595 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); 2596 } 2597 2598 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2599 .dpms = dce_v6_0_crtc_dpms, 2600 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2601 .mode_set = dce_v6_0_crtc_mode_set, 2602 .mode_set_base = dce_v6_0_crtc_set_base, 2603 .prepare = dce_v6_0_crtc_prepare, 2604 .commit = dce_v6_0_crtc_commit, 2605 .disable = dce_v6_0_crtc_disable, 2606 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2607 }; 2608 2609 static void dce_v6_0_panic_flush(struct drm_plane *plane) 2610 { 2611 struct drm_framebuffer *fb; 2612 struct amdgpu_crtc *amdgpu_crtc; 2613 struct amdgpu_device *adev; 2614 uint32_t fb_format; 2615 2616 if (!plane->fb) 2617 return; 2618 2619 fb = plane->fb; 2620 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2621 adev = drm_to_adev(fb->dev); 2622 2623 /* Disable DC tiling */ 2624 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2625 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; 2626 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2627 2628 } 2629 2630 static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { 2631 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2632 .panic_flush = dce_v6_0_panic_flush, 2633 }; 2634 2635 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2636 { 2637 struct amdgpu_crtc *amdgpu_crtc; 2638 2639 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2640 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2641 if (amdgpu_crtc == NULL) 2642 return -ENOMEM; 2643 2644 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2645 2646 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2647 amdgpu_crtc->crtc_id = index; 2648 adev->mode_info.crtcs[index] = amdgpu_crtc; 2649 2650 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2651 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2652 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2653 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2654 2655 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2656 2657 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2658 amdgpu_crtc->adjusted_clock = 0; 2659 amdgpu_crtc->encoder = NULL; 2660 amdgpu_crtc->connector = NULL; 2661 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2662 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); 2663 2664 return 0; 2665 } 2666 2667 static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) 2668 { 2669 struct amdgpu_device *adev = ip_block->adev; 2670 2671 adev->reg.audio_endpt.rreg = &dce_v6_0_audio_endpt_rreg; 2672 adev->reg.audio_endpt.wreg = &dce_v6_0_audio_endpt_wreg; 2673 2674 dce_v6_0_set_display_funcs(adev); 2675 2676 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2677 2678 switch (adev->asic_type) { 2679 case CHIP_TAHITI: 2680 case CHIP_PITCAIRN: 2681 case CHIP_VERDE: 2682 adev->mode_info.num_hpd = 6; 2683 adev->mode_info.num_dig = 6; 2684 break; 2685 case CHIP_OLAND: 2686 adev->mode_info.num_hpd = 2; 2687 adev->mode_info.num_dig = 2; 2688 break; 2689 default: 2690 return -EINVAL; 2691 } 2692 2693 dce_v6_0_set_irq_funcs(adev); 2694 2695 return 0; 2696 } 2697 2698 static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 2699 { 2700 int r, i; 2701 struct amdgpu_device *adev = ip_block->adev; 2702 2703 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2704 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2705 if (r) 2706 return r; 2707 } 2708 2709 for (i = 8; i < 20; i += 2) { 2710 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2711 if (r) 2712 return r; 2713 } 2714 2715 /* HPD hotplug */ 2716 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2717 if (r) 2718 return r; 2719 2720 adev->mode_info.mode_config_initialized = true; 2721 2722 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2723 adev_to_drm(adev)->mode_config.async_page_flip = true; 2724 adev_to_drm(adev)->mode_config.max_width = 16384; 2725 adev_to_drm(adev)->mode_config.max_height = 16384; 2726 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2727 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2728 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2729 2730 r = amdgpu_display_modeset_create_props(adev); 2731 if (r) 2732 return r; 2733 2734 adev_to_drm(adev)->mode_config.max_width = 16384; 2735 adev_to_drm(adev)->mode_config.max_height = 16384; 2736 2737 /* allocate crtcs */ 2738 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2739 r = dce_v6_0_crtc_init(adev, i); 2740 if (r) 2741 return r; 2742 } 2743 2744 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2745 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2746 else 2747 return -EINVAL; 2748 2749 /* setup afmt */ 2750 r = dce_v6_0_afmt_init(adev); 2751 if (r) 2752 return r; 2753 2754 r = dce_v6_0_audio_init(adev); 2755 if (r) 2756 return r; 2757 2758 /* Disable vblank IRQs aggressively for power-saving */ 2759 /* XXX: can this be enabled for DC? */ 2760 adev_to_drm(adev)->vblank_disable_immediate = true; 2761 2762 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2763 if (r) 2764 return r; 2765 2766 /* Pre-DCE11 */ 2767 INIT_DELAYED_WORK(&adev->hotplug_work, 2768 amdgpu_display_hotplug_work_func); 2769 2770 drm_kms_helper_poll_init(adev_to_drm(adev)); 2771 2772 return r; 2773 } 2774 2775 static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 2776 { 2777 struct amdgpu_device *adev = ip_block->adev; 2778 2779 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2780 2781 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2782 2783 dce_v6_0_audio_fini(adev); 2784 dce_v6_0_afmt_fini(adev); 2785 2786 drm_mode_config_cleanup(adev_to_drm(adev)); 2787 adev->mode_info.mode_config_initialized = false; 2788 2789 return 0; 2790 } 2791 2792 static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 2793 { 2794 int i; 2795 struct amdgpu_device *adev = ip_block->adev; 2796 2797 /* disable vga render */ 2798 dce_v6_0_set_vga_render_state(adev, false); 2799 /* init dig PHYs, disp eng pll */ 2800 amdgpu_atombios_encoder_init_dig(adev); 2801 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2802 2803 /* initialize hpd */ 2804 dce_v6_0_hpd_init(adev); 2805 2806 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2807 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2808 } 2809 2810 dce_v6_0_pageflip_interrupt_init(adev); 2811 2812 return 0; 2813 } 2814 2815 static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 2816 { 2817 int i; 2818 struct amdgpu_device *adev = ip_block->adev; 2819 2820 dce_v6_0_hpd_fini(adev); 2821 2822 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2823 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2824 } 2825 2826 dce_v6_0_pageflip_interrupt_fini(adev); 2827 2828 flush_delayed_work(&adev->hotplug_work); 2829 2830 return 0; 2831 } 2832 2833 static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) 2834 { 2835 struct amdgpu_device *adev = ip_block->adev; 2836 int r; 2837 2838 r = amdgpu_display_suspend_helper(adev); 2839 if (r) 2840 return r; 2841 adev->mode_info.bl_level = 2842 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2843 2844 return dce_v6_0_hw_fini(ip_block); 2845 } 2846 2847 static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) 2848 { 2849 struct amdgpu_device *adev = ip_block->adev; 2850 int ret; 2851 2852 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2853 adev->mode_info.bl_level); 2854 2855 ret = dce_v6_0_hw_init(ip_block); 2856 2857 /* turn on the BL */ 2858 if (adev->mode_info.bl_encoder) { 2859 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2860 adev->mode_info.bl_encoder); 2861 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2862 bl_level); 2863 } 2864 if (ret) 2865 return ret; 2866 2867 return amdgpu_display_resume_helper(adev); 2868 } 2869 2870 static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 2871 { 2872 return true; 2873 } 2874 2875 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2876 int crtc, 2877 enum amdgpu_interrupt_state state) 2878 { 2879 u32 reg_block, interrupt_mask; 2880 2881 if (crtc >= adev->mode_info.num_crtc) { 2882 DRM_DEBUG("invalid crtc %d\n", crtc); 2883 return; 2884 } 2885 2886 switch (crtc) { 2887 case 0: 2888 reg_block = CRTC0_REGISTER_OFFSET; 2889 break; 2890 case 1: 2891 reg_block = CRTC1_REGISTER_OFFSET; 2892 break; 2893 case 2: 2894 reg_block = CRTC2_REGISTER_OFFSET; 2895 break; 2896 case 3: 2897 reg_block = CRTC3_REGISTER_OFFSET; 2898 break; 2899 case 4: 2900 reg_block = CRTC4_REGISTER_OFFSET; 2901 break; 2902 case 5: 2903 reg_block = CRTC5_REGISTER_OFFSET; 2904 break; 2905 default: 2906 DRM_DEBUG("invalid crtc %d\n", crtc); 2907 return; 2908 } 2909 2910 switch (state) { 2911 case AMDGPU_IRQ_STATE_DISABLE: 2912 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2913 interrupt_mask &= ~INT_MASK__VBLANK_INT_MASK; 2914 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2915 break; 2916 case AMDGPU_IRQ_STATE_ENABLE: 2917 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2918 interrupt_mask |= INT_MASK__VBLANK_INT_MASK; 2919 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2920 break; 2921 default: 2922 break; 2923 } 2924 } 2925 2926 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2927 int crtc, 2928 enum amdgpu_interrupt_state state) 2929 { 2930 2931 } 2932 2933 static int dce_v6_0_set_hpd_irq_state(struct amdgpu_device *adev, 2934 struct amdgpu_irq_src *src, 2935 unsigned hpd, 2936 enum amdgpu_interrupt_state state) 2937 { 2938 u32 dc_hpd_int_cntl; 2939 2940 if (hpd >= adev->mode_info.num_hpd) { 2941 DRM_DEBUG("invalid hpd %d\n", hpd); 2942 return 0; 2943 } 2944 2945 switch (state) { 2946 case AMDGPU_IRQ_STATE_DISABLE: 2947 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 2948 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 2949 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); 2950 break; 2951 case AMDGPU_IRQ_STATE_ENABLE: 2952 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 2953 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 2954 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl); 2955 break; 2956 default: 2957 break; 2958 } 2959 2960 return 0; 2961 } 2962 2963 static int dce_v6_0_set_crtc_irq_state(struct amdgpu_device *adev, 2964 struct amdgpu_irq_src *src, 2965 unsigned type, 2966 enum amdgpu_interrupt_state state) 2967 { 2968 switch (type) { 2969 case AMDGPU_CRTC_IRQ_VBLANK1: 2970 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 2971 break; 2972 case AMDGPU_CRTC_IRQ_VBLANK2: 2973 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 2974 break; 2975 case AMDGPU_CRTC_IRQ_VBLANK3: 2976 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 2977 break; 2978 case AMDGPU_CRTC_IRQ_VBLANK4: 2979 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 2980 break; 2981 case AMDGPU_CRTC_IRQ_VBLANK5: 2982 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 2983 break; 2984 case AMDGPU_CRTC_IRQ_VBLANK6: 2985 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 2986 break; 2987 case AMDGPU_CRTC_IRQ_VLINE1: 2988 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 2989 break; 2990 case AMDGPU_CRTC_IRQ_VLINE2: 2991 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 2992 break; 2993 case AMDGPU_CRTC_IRQ_VLINE3: 2994 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 2995 break; 2996 case AMDGPU_CRTC_IRQ_VLINE4: 2997 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 2998 break; 2999 case AMDGPU_CRTC_IRQ_VLINE5: 3000 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3001 break; 3002 case AMDGPU_CRTC_IRQ_VLINE6: 3003 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3004 break; 3005 default: 3006 break; 3007 } 3008 return 0; 3009 } 3010 3011 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3012 struct amdgpu_irq_src *source, 3013 struct amdgpu_iv_entry *entry) 3014 { 3015 unsigned crtc = entry->src_id - 1; 3016 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3017 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3018 crtc); 3019 3020 switch (entry->src_data[0]) { 3021 case 0: /* vblank */ 3022 if (disp_int & interrupt_status_offsets[crtc].vblank) 3023 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_STATUS__VBLANK_ACK_MASK); 3024 else 3025 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3026 3027 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3028 drm_handle_vblank(adev_to_drm(adev), crtc); 3029 } 3030 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3031 break; 3032 case 1: /* vline */ 3033 if (disp_int & interrupt_status_offsets[crtc].vline) 3034 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_STATUS__VLINE_ACK_MASK); 3035 else 3036 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3037 3038 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3039 break; 3040 default: 3041 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3042 break; 3043 } 3044 3045 return 0; 3046 } 3047 3048 static int dce_v6_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3049 struct amdgpu_irq_src *src, 3050 unsigned type, 3051 enum amdgpu_interrupt_state state) 3052 { 3053 u32 reg; 3054 3055 if (type >= adev->mode_info.num_crtc) { 3056 DRM_ERROR("invalid pageflip crtc %d\n", type); 3057 return -EINVAL; 3058 } 3059 3060 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3061 if (state == AMDGPU_IRQ_STATE_DISABLE) 3062 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3063 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3064 else 3065 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3066 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3067 3068 return 0; 3069 } 3070 3071 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3072 struct amdgpu_irq_src *source, 3073 struct amdgpu_iv_entry *entry) 3074 { 3075 unsigned long flags; 3076 unsigned crtc_id; 3077 struct amdgpu_crtc *amdgpu_crtc; 3078 struct amdgpu_flip_work *works; 3079 3080 crtc_id = (entry->src_id - 8) >> 1; 3081 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3082 3083 if (crtc_id >= adev->mode_info.num_crtc) { 3084 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3085 return -EINVAL; 3086 } 3087 3088 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3089 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3090 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3091 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3092 3093 /* IRQ could occur when in initial stage */ 3094 if (amdgpu_crtc == NULL) 3095 return 0; 3096 3097 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3098 works = amdgpu_crtc->pflip_works; 3099 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3100 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3101 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3102 amdgpu_crtc->pflip_status, 3103 AMDGPU_FLIP_SUBMITTED); 3104 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3105 return 0; 3106 } 3107 3108 /* page flip completed. clean up */ 3109 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3110 amdgpu_crtc->pflip_works = NULL; 3111 3112 /* wakeup usersapce */ 3113 if (works->event) 3114 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3115 3116 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3117 3118 drm_crtc_vblank_put(&amdgpu_crtc->base); 3119 schedule_work(&works->unpin_work); 3120 3121 return 0; 3122 } 3123 3124 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3125 struct amdgpu_irq_src *source, 3126 struct amdgpu_iv_entry *entry) 3127 { 3128 uint32_t disp_int, mask; 3129 unsigned hpd; 3130 3131 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3132 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3133 return 0; 3134 } 3135 3136 hpd = entry->src_data[0]; 3137 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3138 mask = interrupt_status_offsets[hpd].hpd; 3139 3140 if (disp_int & mask) { 3141 dce_v6_0_hpd_int_ack(adev, hpd); 3142 schedule_delayed_work(&adev->hotplug_work, 0); 3143 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3144 } 3145 3146 return 0; 3147 } 3148 3149 static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3150 enum amd_clockgating_state state) 3151 { 3152 return 0; 3153 } 3154 3155 static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3156 enum amd_powergating_state state) 3157 { 3158 return 0; 3159 } 3160 3161 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3162 .name = "dce_v6_0", 3163 .early_init = dce_v6_0_early_init, 3164 .sw_init = dce_v6_0_sw_init, 3165 .sw_fini = dce_v6_0_sw_fini, 3166 .hw_init = dce_v6_0_hw_init, 3167 .hw_fini = dce_v6_0_hw_fini, 3168 .suspend = dce_v6_0_suspend, 3169 .resume = dce_v6_0_resume, 3170 .is_idle = dce_v6_0_is_idle, 3171 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3172 .set_powergating_state = dce_v6_0_set_powergating_state, 3173 }; 3174 3175 static void dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3176 struct drm_display_mode *mode, 3177 struct drm_display_mode *adjusted_mode) 3178 { 3179 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3180 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3181 3182 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3183 3184 /* need to call this here rather than in prepare() since we need some crtc info */ 3185 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3186 3187 /* set scaler clears this on some chips */ 3188 dce_v6_0_set_interleave(encoder->crtc, mode); 3189 3190 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3191 dce_v6_0_afmt_enable(encoder, true); 3192 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3193 } 3194 } 3195 3196 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3197 { 3198 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3199 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3200 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3201 3202 if ((amdgpu_encoder->active_device & 3203 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3204 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3205 ENCODER_OBJECT_ID_NONE)) { 3206 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3207 if (dig) { 3208 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3209 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3210 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3211 } 3212 } 3213 3214 amdgpu_atombios_scratch_regs_lock(adev, true); 3215 3216 if (connector) { 3217 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3218 3219 /* select the clock/data port if it uses a router */ 3220 if (amdgpu_connector->router.cd_valid) 3221 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3222 3223 /* turn eDP panel on for mode set */ 3224 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3225 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3226 ATOM_TRANSMITTER_ACTION_POWER_ON); 3227 } 3228 3229 /* this is needed for the pll/ss setup to work correctly in some cases */ 3230 amdgpu_atombios_encoder_set_crtc_source(encoder); 3231 /* set up the FMT blocks */ 3232 dce_v6_0_program_fmt(encoder); 3233 } 3234 3235 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3236 { 3237 struct drm_device *dev = encoder->dev; 3238 struct amdgpu_device *adev = drm_to_adev(dev); 3239 3240 /* need to call this here as we need the crtc set up */ 3241 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3242 amdgpu_atombios_scratch_regs_lock(adev, false); 3243 } 3244 3245 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3246 { 3247 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3248 struct amdgpu_encoder_atom_dig *dig; 3249 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3250 3251 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3252 3253 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3254 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3255 dce_v6_0_afmt_enable(encoder, false); 3256 dig = amdgpu_encoder->enc_priv; 3257 dig->dig_encoder = -1; 3258 } 3259 amdgpu_encoder->active_device = 0; 3260 } 3261 3262 /* these are handled by the primary encoders */ 3263 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3264 { 3265 3266 } 3267 3268 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3269 { 3270 3271 } 3272 3273 static void dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3274 struct drm_display_mode *mode, 3275 struct drm_display_mode *adjusted_mode) 3276 { 3277 3278 } 3279 3280 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3281 { 3282 3283 } 3284 3285 static void dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3286 { 3287 3288 } 3289 3290 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3291 const struct drm_display_mode *mode, 3292 struct drm_display_mode *adjusted_mode) 3293 { 3294 return true; 3295 } 3296 3297 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3298 .dpms = dce_v6_0_ext_dpms, 3299 .mode_fixup = dce_v6_0_ext_mode_fixup, 3300 .prepare = dce_v6_0_ext_prepare, 3301 .mode_set = dce_v6_0_ext_mode_set, 3302 .commit = dce_v6_0_ext_commit, 3303 .disable = dce_v6_0_ext_disable, 3304 /* no detect for TMDS/LVDS yet */ 3305 }; 3306 3307 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3308 .dpms = amdgpu_atombios_encoder_dpms, 3309 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3310 .prepare = dce_v6_0_encoder_prepare, 3311 .mode_set = dce_v6_0_encoder_mode_set, 3312 .commit = dce_v6_0_encoder_commit, 3313 .disable = dce_v6_0_encoder_disable, 3314 .detect = amdgpu_atombios_encoder_dig_detect, 3315 }; 3316 3317 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3318 .dpms = amdgpu_atombios_encoder_dpms, 3319 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3320 .prepare = dce_v6_0_encoder_prepare, 3321 .mode_set = dce_v6_0_encoder_mode_set, 3322 .commit = dce_v6_0_encoder_commit, 3323 .detect = amdgpu_atombios_encoder_dac_detect, 3324 }; 3325 3326 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3327 { 3328 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3329 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3330 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3331 kfree(amdgpu_encoder->enc_priv); 3332 drm_encoder_cleanup(encoder); 3333 kfree(amdgpu_encoder); 3334 } 3335 3336 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3337 .destroy = dce_v6_0_encoder_destroy, 3338 }; 3339 3340 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3341 uint32_t encoder_enum, 3342 uint32_t supported_device, 3343 u16 caps) 3344 { 3345 struct drm_device *dev = adev_to_drm(adev); 3346 struct drm_encoder *encoder; 3347 struct amdgpu_encoder *amdgpu_encoder; 3348 3349 /* see if we already added it */ 3350 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3351 amdgpu_encoder = to_amdgpu_encoder(encoder); 3352 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3353 amdgpu_encoder->devices |= supported_device; 3354 return; 3355 } 3356 } 3357 3358 /* add a new one */ 3359 amdgpu_encoder = kzalloc_obj(struct amdgpu_encoder); 3360 if (!amdgpu_encoder) 3361 return; 3362 3363 encoder = &amdgpu_encoder->base; 3364 switch (adev->mode_info.num_crtc) { 3365 case 1: 3366 encoder->possible_crtcs = 0x1; 3367 break; 3368 case 2: 3369 default: 3370 encoder->possible_crtcs = 0x3; 3371 break; 3372 case 4: 3373 encoder->possible_crtcs = 0xf; 3374 break; 3375 case 6: 3376 encoder->possible_crtcs = 0x3f; 3377 break; 3378 } 3379 3380 amdgpu_encoder->enc_priv = NULL; 3381 amdgpu_encoder->encoder_enum = encoder_enum; 3382 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3383 amdgpu_encoder->devices = supported_device; 3384 amdgpu_encoder->rmx_type = RMX_OFF; 3385 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3386 amdgpu_encoder->is_ext_encoder = false; 3387 amdgpu_encoder->caps = caps; 3388 3389 switch (amdgpu_encoder->encoder_id) { 3390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3392 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3393 DRM_MODE_ENCODER_DAC, NULL); 3394 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3395 break; 3396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3398 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3399 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3400 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3401 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3402 amdgpu_encoder->rmx_type = RMX_FULL; 3403 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3404 DRM_MODE_ENCODER_LVDS, NULL); 3405 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3406 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3407 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3408 DRM_MODE_ENCODER_DAC, NULL); 3409 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3410 } else { 3411 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3412 DRM_MODE_ENCODER_TMDS, NULL); 3413 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3414 } 3415 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3416 break; 3417 case ENCODER_OBJECT_ID_SI170B: 3418 case ENCODER_OBJECT_ID_CH7303: 3419 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3420 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3421 case ENCODER_OBJECT_ID_TITFP513: 3422 case ENCODER_OBJECT_ID_VT1623: 3423 case ENCODER_OBJECT_ID_HDMI_SI1930: 3424 case ENCODER_OBJECT_ID_TRAVIS: 3425 case ENCODER_OBJECT_ID_NUTMEG: 3426 /* these are handled by the primary encoders */ 3427 amdgpu_encoder->is_ext_encoder = true; 3428 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3429 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3430 DRM_MODE_ENCODER_LVDS, NULL); 3431 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3432 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3433 DRM_MODE_ENCODER_DAC, NULL); 3434 else 3435 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3436 DRM_MODE_ENCODER_TMDS, NULL); 3437 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3438 break; 3439 } 3440 } 3441 3442 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3443 .bandwidth_update = &dce_v6_0_bandwidth_update, 3444 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3445 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3446 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3447 .hpd_sense = &dce_v6_0_hpd_sense, 3448 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3449 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3450 .page_flip = &dce_v6_0_page_flip, 3451 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3452 .add_encoder = &dce_v6_0_encoder_add, 3453 .add_connector = &amdgpu_connector_add, 3454 }; 3455 3456 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3457 { 3458 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3459 } 3460 3461 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3462 .set = dce_v6_0_set_crtc_irq_state, 3463 .process = dce_v6_0_crtc_irq, 3464 }; 3465 3466 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3467 .set = dce_v6_0_set_pageflip_irq_state, 3468 .process = dce_v6_0_pageflip_irq, 3469 }; 3470 3471 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3472 .set = dce_v6_0_set_hpd_irq_state, 3473 .process = dce_v6_0_hpd_irq, 3474 }; 3475 3476 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3477 { 3478 if (adev->mode_info.num_crtc > 0) 3479 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3480 else 3481 adev->crtc_irq.num_types = 0; 3482 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3483 3484 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3485 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3486 3487 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3488 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3489 } 3490 3491 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3492 { 3493 .type = AMD_IP_BLOCK_TYPE_DCE, 3494 .major = 6, 3495 .minor = 0, 3496 .rev = 0, 3497 .funcs = &dce_v6_0_ip_funcs, 3498 }; 3499 3500 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3501 { 3502 .type = AMD_IP_BLOCK_TYPE_DCE, 3503 .major = 6, 3504 .minor = 4, 3505 .rev = 0, 3506 .funcs = &dce_v6_0_ip_funcs, 3507 }; 3508