1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drm_edid.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_modeset_helper.h> 27 #include <drm/drm_modeset_helper_vtables.h> 28 #include <drm/drm_vblank.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_i2c.h" 33 #include "vid.h" 34 #include "atom.h" 35 #include "amdgpu_atombios.h" 36 #include "atombios_crtc.h" 37 #include "atombios_encoders.h" 38 #include "amdgpu_pll.h" 39 #include "amdgpu_connectors.h" 40 #include "amdgpu_display.h" 41 #include "dce_v11_0.h" 42 43 #include "dce/dce_11_0_d.h" 44 #include "dce/dce_11_0_sh_mask.h" 45 #include "dce/dce_11_0_enum.h" 46 #include "oss/oss_3_0_d.h" 47 #include "oss/oss_3_0_sh_mask.h" 48 #include "gmc/gmc_8_1_d.h" 49 #include "gmc/gmc_8_1_sh_mask.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 54 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 55 56 static const u32 crtc_offsets[] = 57 { 58 CRTC0_REGISTER_OFFSET, 59 CRTC1_REGISTER_OFFSET, 60 CRTC2_REGISTER_OFFSET, 61 CRTC3_REGISTER_OFFSET, 62 CRTC4_REGISTER_OFFSET, 63 CRTC5_REGISTER_OFFSET, 64 CRTC6_REGISTER_OFFSET 65 }; 66 67 static const u32 hpd_offsets[] = 68 { 69 HPD0_REGISTER_OFFSET, 70 HPD1_REGISTER_OFFSET, 71 HPD2_REGISTER_OFFSET, 72 HPD3_REGISTER_OFFSET, 73 HPD4_REGISTER_OFFSET, 74 HPD5_REGISTER_OFFSET 75 }; 76 77 static const uint32_t dig_offsets[] = { 78 DIG0_REGISTER_OFFSET, 79 DIG1_REGISTER_OFFSET, 80 DIG2_REGISTER_OFFSET, 81 DIG3_REGISTER_OFFSET, 82 DIG4_REGISTER_OFFSET, 83 DIG5_REGISTER_OFFSET, 84 DIG6_REGISTER_OFFSET, 85 DIG7_REGISTER_OFFSET, 86 DIG8_REGISTER_OFFSET 87 }; 88 89 static const struct { 90 uint32_t reg; 91 uint32_t vblank; 92 uint32_t vline; 93 uint32_t hpd; 94 95 } interrupt_status_offsets[] = { { 96 .reg = mmDISP_INTERRUPT_STATUS, 97 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 115 }, { 116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 120 }, { 121 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 122 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 124 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 125 } }; 126 127 static const u32 cz_golden_settings_a11[] = 128 { 129 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 130 mmFBC_MISC, 0x1f311fff, 0x14300000, 131 }; 132 133 static const u32 cz_mgcg_cgcg_init[] = 134 { 135 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 136 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 137 }; 138 139 static const u32 stoney_golden_settings_a11[] = 140 { 141 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 142 mmFBC_MISC, 0x1f311fff, 0x14302000, 143 }; 144 145 static const u32 polaris11_golden_settings_a11[] = 146 { 147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 149 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 150 mmFBC_MISC, 0x9f313fff, 0x14302008, 151 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 152 }; 153 154 static const u32 polaris10_golden_settings_a11[] = 155 { 156 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 157 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 158 mmFBC_MISC, 0x9f313fff, 0x14302008, 159 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 160 }; 161 162 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 163 { 164 switch (adev->asic_type) { 165 case CHIP_CARRIZO: 166 amdgpu_device_program_register_sequence(adev, 167 cz_mgcg_cgcg_init, 168 ARRAY_SIZE(cz_mgcg_cgcg_init)); 169 amdgpu_device_program_register_sequence(adev, 170 cz_golden_settings_a11, 171 ARRAY_SIZE(cz_golden_settings_a11)); 172 break; 173 case CHIP_STONEY: 174 amdgpu_device_program_register_sequence(adev, 175 stoney_golden_settings_a11, 176 ARRAY_SIZE(stoney_golden_settings_a11)); 177 break; 178 case CHIP_POLARIS11: 179 case CHIP_POLARIS12: 180 amdgpu_device_program_register_sequence(adev, 181 polaris11_golden_settings_a11, 182 ARRAY_SIZE(polaris11_golden_settings_a11)); 183 break; 184 case CHIP_POLARIS10: 185 case CHIP_VEGAM: 186 amdgpu_device_program_register_sequence(adev, 187 polaris10_golden_settings_a11, 188 ARRAY_SIZE(polaris10_golden_settings_a11)); 189 break; 190 default: 191 break; 192 } 193 } 194 195 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 196 u32 block_offset, u32 reg) 197 { 198 unsigned long flags; 199 u32 r; 200 201 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 202 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 203 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 204 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 205 206 return r; 207 } 208 209 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 210 u32 block_offset, u32 reg, u32 v) 211 { 212 unsigned long flags; 213 214 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 215 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 216 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 217 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 218 } 219 220 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 221 { 222 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 223 return 0; 224 else 225 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 226 } 227 228 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 229 { 230 unsigned i; 231 232 /* Enable pflip interrupts */ 233 for (i = 0; i < adev->mode_info.num_crtc; i++) 234 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 235 } 236 237 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 238 { 239 unsigned i; 240 241 /* Disable pflip interrupts */ 242 for (i = 0; i < adev->mode_info.num_crtc; i++) 243 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 244 } 245 246 /** 247 * dce_v11_0_page_flip - pageflip callback. 248 * 249 * @adev: amdgpu_device pointer 250 * @crtc_id: crtc to cleanup pageflip on 251 * @crtc_base: new address of the crtc (GPU MC address) 252 * @async: asynchronous flip 253 * 254 * Triggers the actual pageflip by updating the primary 255 * surface base address. 256 */ 257 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 258 int crtc_id, u64 crtc_base, bool async) 259 { 260 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 261 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 262 u32 tmp; 263 264 /* flip immediate for async, default is vsync */ 265 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 266 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 267 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 268 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 269 /* update pitch */ 270 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 271 fb->pitches[0] / fb->format->cpp[0]); 272 /* update the scanout addresses */ 273 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 274 upper_32_bits(crtc_base)); 275 /* writing to the low address triggers the update */ 276 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 277 lower_32_bits(crtc_base)); 278 /* post the write */ 279 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 280 } 281 282 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 283 u32 *vbl, u32 *position) 284 { 285 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 286 return -EINVAL; 287 288 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 289 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 290 291 return 0; 292 } 293 294 /** 295 * dce_v11_0_hpd_sense - hpd sense callback. 296 * 297 * @adev: amdgpu_device pointer 298 * @hpd: hpd (hotplug detect) pin 299 * 300 * Checks if a digital monitor is connected (evergreen+). 301 * Returns true if connected, false if not connected. 302 */ 303 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 304 enum amdgpu_hpd_id hpd) 305 { 306 bool connected = false; 307 308 if (hpd >= adev->mode_info.num_hpd) 309 return connected; 310 311 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 312 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 313 connected = true; 314 315 return connected; 316 } 317 318 /** 319 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 320 * 321 * @adev: amdgpu_device pointer 322 * @hpd: hpd (hotplug detect) pin 323 * 324 * Set the polarity of the hpd pin (evergreen+). 325 */ 326 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 327 enum amdgpu_hpd_id hpd) 328 { 329 u32 tmp; 330 bool connected = dce_v11_0_hpd_sense(adev, hpd); 331 332 if (hpd >= adev->mode_info.num_hpd) 333 return; 334 335 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 336 if (connected) 337 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 338 else 339 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 341 } 342 343 /** 344 * dce_v11_0_hpd_init - hpd setup callback. 345 * 346 * @adev: amdgpu_device pointer 347 * 348 * Setup the hpd pins used by the card (evergreen+). 349 * Enable the pin, set the polarity, and enable the hpd interrupts. 350 */ 351 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 352 { 353 struct drm_device *dev = adev_to_drm(adev); 354 struct drm_connector *connector; 355 struct drm_connector_list_iter iter; 356 u32 tmp; 357 358 drm_connector_list_iter_begin(dev, &iter); 359 drm_for_each_connector_iter(connector, &iter) { 360 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 361 362 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 363 continue; 364 365 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 366 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 367 /* don't try to enable hpd on eDP or LVDS avoid breaking the 368 * aux dp channel on imac and help (but not completely fix) 369 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 370 * also avoid interrupt storms during dpms. 371 */ 372 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 373 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 374 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 375 continue; 376 } 377 378 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 379 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 380 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 381 382 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 383 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 384 DC_HPD_CONNECT_INT_DELAY, 385 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 386 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 387 DC_HPD_DISCONNECT_INT_DELAY, 388 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 389 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 390 391 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 392 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 393 } 394 drm_connector_list_iter_end(&iter); 395 } 396 397 /** 398 * dce_v11_0_hpd_fini - hpd tear down callback. 399 * 400 * @adev: amdgpu_device pointer 401 * 402 * Tear down the hpd pins used by the card (evergreen+). 403 * Disable the hpd interrupts. 404 */ 405 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 406 { 407 struct drm_device *dev = adev_to_drm(adev); 408 struct drm_connector *connector; 409 struct drm_connector_list_iter iter; 410 u32 tmp; 411 412 drm_connector_list_iter_begin(dev, &iter); 413 drm_for_each_connector_iter(connector, &iter) { 414 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 415 416 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 417 continue; 418 419 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 420 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 421 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 422 423 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 424 } 425 drm_connector_list_iter_end(&iter); 426 } 427 428 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 429 { 430 return mmDC_GPIO_HPD_A; 431 } 432 433 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 434 { 435 u32 crtc_hung = 0; 436 u32 crtc_status[6]; 437 u32 i, j, tmp; 438 439 for (i = 0; i < adev->mode_info.num_crtc; i++) { 440 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 441 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 442 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 443 crtc_hung |= (1 << i); 444 } 445 } 446 447 for (j = 0; j < 10; j++) { 448 for (i = 0; i < adev->mode_info.num_crtc; i++) { 449 if (crtc_hung & (1 << i)) { 450 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 451 if (tmp != crtc_status[i]) 452 crtc_hung &= ~(1 << i); 453 } 454 } 455 if (crtc_hung == 0) 456 return false; 457 udelay(100); 458 } 459 460 return true; 461 } 462 463 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 464 bool render) 465 { 466 u32 tmp; 467 468 /* Lockout access through VGA aperture*/ 469 tmp = RREG32(mmVGA_HDP_CONTROL); 470 if (render) 471 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 472 else 473 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 474 WREG32(mmVGA_HDP_CONTROL, tmp); 475 476 /* disable VGA render */ 477 tmp = RREG32(mmVGA_RENDER_CONTROL); 478 if (render) 479 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 480 else 481 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 482 WREG32(mmVGA_RENDER_CONTROL, tmp); 483 } 484 485 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 486 { 487 int num_crtc = 0; 488 489 switch (adev->asic_type) { 490 case CHIP_CARRIZO: 491 num_crtc = 3; 492 break; 493 case CHIP_STONEY: 494 num_crtc = 2; 495 break; 496 case CHIP_POLARIS10: 497 case CHIP_VEGAM: 498 num_crtc = 6; 499 break; 500 case CHIP_POLARIS11: 501 case CHIP_POLARIS12: 502 num_crtc = 5; 503 break; 504 default: 505 num_crtc = 0; 506 } 507 return num_crtc; 508 } 509 510 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 511 { 512 /*Disable VGA render and enabled crtc, if has DCE engine*/ 513 if (amdgpu_atombios_has_dce_engine_info(adev)) { 514 u32 tmp; 515 int crtc_enabled, i; 516 517 dce_v11_0_set_vga_render_state(adev, false); 518 519 /*Disable crtc*/ 520 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 521 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 522 CRTC_CONTROL, CRTC_MASTER_EN); 523 if (crtc_enabled) { 524 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 525 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 526 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 527 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 528 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 529 } 530 } 531 } 532 } 533 534 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 535 { 536 struct drm_device *dev = encoder->dev; 537 struct amdgpu_device *adev = drm_to_adev(dev); 538 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 539 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 540 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 541 int bpc = 0; 542 u32 tmp = 0; 543 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 544 545 if (connector) { 546 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 547 bpc = amdgpu_connector_get_monitor_bpc(connector); 548 dither = amdgpu_connector->dither; 549 } 550 551 /* LVDS/eDP FMT is set up by atom */ 552 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 553 return; 554 555 /* not needed for analog */ 556 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 557 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 558 return; 559 560 if (bpc == 0) 561 return; 562 563 switch (bpc) { 564 case 6: 565 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 566 /* XXX sort out optimal dither settings */ 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 571 } else { 572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 574 } 575 break; 576 case 8: 577 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 578 /* XXX sort out optimal dither settings */ 579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 584 } else { 585 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 586 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 587 } 588 break; 589 case 10: 590 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 591 /* XXX sort out optimal dither settings */ 592 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 593 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 597 } else { 598 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 599 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 600 } 601 break; 602 default: 603 /* not needed */ 604 break; 605 } 606 607 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 608 } 609 610 611 /* display watermark setup */ 612 /** 613 * dce_v11_0_line_buffer_adjust - Set up the line buffer 614 * 615 * @adev: amdgpu_device pointer 616 * @amdgpu_crtc: the selected display controller 617 * @mode: the current display mode on the selected display 618 * controller 619 * 620 * Setup up the line buffer allocation for 621 * the selected display controller (CIK). 622 * Returns the line buffer size in pixels. 623 */ 624 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 625 struct amdgpu_crtc *amdgpu_crtc, 626 struct drm_display_mode *mode) 627 { 628 u32 tmp, buffer_alloc, i, mem_cfg; 629 u32 pipe_offset = amdgpu_crtc->crtc_id; 630 /* 631 * Line Buffer Setup 632 * There are 6 line buffers, one for each display controllers. 633 * There are 3 partitions per LB. Select the number of partitions 634 * to enable based on the display width. For display widths larger 635 * than 4096, you need use to use 2 display controllers and combine 636 * them using the stereo blender. 637 */ 638 if (amdgpu_crtc->base.enabled && mode) { 639 if (mode->crtc_hdisplay < 1920) { 640 mem_cfg = 1; 641 buffer_alloc = 2; 642 } else if (mode->crtc_hdisplay < 2560) { 643 mem_cfg = 2; 644 buffer_alloc = 2; 645 } else if (mode->crtc_hdisplay < 4096) { 646 mem_cfg = 0; 647 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 648 } else { 649 DRM_DEBUG_KMS("Mode too big for LB!\n"); 650 mem_cfg = 0; 651 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 652 } 653 } else { 654 mem_cfg = 1; 655 buffer_alloc = 0; 656 } 657 658 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 659 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 660 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 661 662 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 663 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 664 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 665 666 for (i = 0; i < adev->usec_timeout; i++) { 667 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 668 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 669 break; 670 udelay(1); 671 } 672 673 if (amdgpu_crtc->base.enabled && mode) { 674 switch (mem_cfg) { 675 case 0: 676 default: 677 return 4096 * 2; 678 case 1: 679 return 1920 * 2; 680 case 2: 681 return 2560 * 2; 682 } 683 } 684 685 /* controller not enabled, so no lb used */ 686 return 0; 687 } 688 689 /** 690 * cik_get_number_of_dram_channels - get the number of dram channels 691 * 692 * @adev: amdgpu_device pointer 693 * 694 * Look up the number of video ram channels (CIK). 695 * Used for display watermark bandwidth calculations 696 * Returns the number of dram channels 697 */ 698 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 699 { 700 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 701 702 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 703 case 0: 704 default: 705 return 1; 706 case 1: 707 return 2; 708 case 2: 709 return 4; 710 case 3: 711 return 8; 712 case 4: 713 return 3; 714 case 5: 715 return 6; 716 case 6: 717 return 10; 718 case 7: 719 return 12; 720 case 8: 721 return 16; 722 } 723 } 724 725 struct dce10_wm_params { 726 u32 dram_channels; /* number of dram channels */ 727 u32 yclk; /* bandwidth per dram data pin in kHz */ 728 u32 sclk; /* engine clock in kHz */ 729 u32 disp_clk; /* display clock in kHz */ 730 u32 src_width; /* viewport width */ 731 u32 active_time; /* active display time in ns */ 732 u32 blank_time; /* blank time in ns */ 733 bool interlaced; /* mode is interlaced */ 734 fixed20_12 vsc; /* vertical scale ratio */ 735 u32 num_heads; /* number of active crtcs */ 736 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 737 u32 lb_size; /* line buffer allocated to pipe */ 738 u32 vtaps; /* vertical scaler taps */ 739 }; 740 741 /** 742 * dce_v11_0_dram_bandwidth - get the dram bandwidth 743 * 744 * @wm: watermark calculation data 745 * 746 * Calculate the raw dram bandwidth (CIK). 747 * Used for display watermark bandwidth calculations 748 * Returns the dram bandwidth in MBytes/s 749 */ 750 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 751 { 752 /* Calculate raw DRAM Bandwidth */ 753 fixed20_12 dram_efficiency; /* 0.7 */ 754 fixed20_12 yclk, dram_channels, bandwidth; 755 fixed20_12 a; 756 757 a.full = dfixed_const(1000); 758 yclk.full = dfixed_const(wm->yclk); 759 yclk.full = dfixed_div(yclk, a); 760 dram_channels.full = dfixed_const(wm->dram_channels * 4); 761 a.full = dfixed_const(10); 762 dram_efficiency.full = dfixed_const(7); 763 dram_efficiency.full = dfixed_div(dram_efficiency, a); 764 bandwidth.full = dfixed_mul(dram_channels, yclk); 765 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 766 767 return dfixed_trunc(bandwidth); 768 } 769 770 /** 771 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 772 * 773 * @wm: watermark calculation data 774 * 775 * Calculate the dram bandwidth used for display (CIK). 776 * Used for display watermark bandwidth calculations 777 * Returns the dram bandwidth for display in MBytes/s 778 */ 779 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 780 { 781 /* Calculate DRAM Bandwidth and the part allocated to display. */ 782 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 783 fixed20_12 yclk, dram_channels, bandwidth; 784 fixed20_12 a; 785 786 a.full = dfixed_const(1000); 787 yclk.full = dfixed_const(wm->yclk); 788 yclk.full = dfixed_div(yclk, a); 789 dram_channels.full = dfixed_const(wm->dram_channels * 4); 790 a.full = dfixed_const(10); 791 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 792 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 793 bandwidth.full = dfixed_mul(dram_channels, yclk); 794 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 795 796 return dfixed_trunc(bandwidth); 797 } 798 799 /** 800 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 801 * 802 * @wm: watermark calculation data 803 * 804 * Calculate the data return bandwidth used for display (CIK). 805 * Used for display watermark bandwidth calculations 806 * Returns the data return bandwidth in MBytes/s 807 */ 808 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 809 { 810 /* Calculate the display Data return Bandwidth */ 811 fixed20_12 return_efficiency; /* 0.8 */ 812 fixed20_12 sclk, bandwidth; 813 fixed20_12 a; 814 815 a.full = dfixed_const(1000); 816 sclk.full = dfixed_const(wm->sclk); 817 sclk.full = dfixed_div(sclk, a); 818 a.full = dfixed_const(10); 819 return_efficiency.full = dfixed_const(8); 820 return_efficiency.full = dfixed_div(return_efficiency, a); 821 a.full = dfixed_const(32); 822 bandwidth.full = dfixed_mul(a, sclk); 823 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 824 825 return dfixed_trunc(bandwidth); 826 } 827 828 /** 829 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 830 * 831 * @wm: watermark calculation data 832 * 833 * Calculate the dmif bandwidth used for display (CIK). 834 * Used for display watermark bandwidth calculations 835 * Returns the dmif bandwidth in MBytes/s 836 */ 837 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 838 { 839 /* Calculate the DMIF Request Bandwidth */ 840 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 841 fixed20_12 disp_clk, bandwidth; 842 fixed20_12 a, b; 843 844 a.full = dfixed_const(1000); 845 disp_clk.full = dfixed_const(wm->disp_clk); 846 disp_clk.full = dfixed_div(disp_clk, a); 847 a.full = dfixed_const(32); 848 b.full = dfixed_mul(a, disp_clk); 849 850 a.full = dfixed_const(10); 851 disp_clk_request_efficiency.full = dfixed_const(8); 852 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 853 854 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 855 856 return dfixed_trunc(bandwidth); 857 } 858 859 /** 860 * dce_v11_0_available_bandwidth - get the min available bandwidth 861 * 862 * @wm: watermark calculation data 863 * 864 * Calculate the min available bandwidth used for display (CIK). 865 * Used for display watermark bandwidth calculations 866 * Returns the min available bandwidth in MBytes/s 867 */ 868 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 869 { 870 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 871 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 872 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 873 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 874 875 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 876 } 877 878 /** 879 * dce_v11_0_average_bandwidth - get the average available bandwidth 880 * 881 * @wm: watermark calculation data 882 * 883 * Calculate the average available bandwidth used for display (CIK). 884 * Used for display watermark bandwidth calculations 885 * Returns the average available bandwidth in MBytes/s 886 */ 887 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 888 { 889 /* Calculate the display mode Average Bandwidth 890 * DisplayMode should contain the source and destination dimensions, 891 * timing, etc. 892 */ 893 fixed20_12 bpp; 894 fixed20_12 line_time; 895 fixed20_12 src_width; 896 fixed20_12 bandwidth; 897 fixed20_12 a; 898 899 a.full = dfixed_const(1000); 900 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 901 line_time.full = dfixed_div(line_time, a); 902 bpp.full = dfixed_const(wm->bytes_per_pixel); 903 src_width.full = dfixed_const(wm->src_width); 904 bandwidth.full = dfixed_mul(src_width, bpp); 905 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 906 bandwidth.full = dfixed_div(bandwidth, line_time); 907 908 return dfixed_trunc(bandwidth); 909 } 910 911 /** 912 * dce_v11_0_latency_watermark - get the latency watermark 913 * 914 * @wm: watermark calculation data 915 * 916 * Calculate the latency watermark (CIK). 917 * Used for display watermark bandwidth calculations 918 * Returns the latency watermark in ns 919 */ 920 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 921 { 922 /* First calculate the latency in ns */ 923 u32 mc_latency = 2000; /* 2000 ns. */ 924 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 925 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 926 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 927 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 928 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 929 (wm->num_heads * cursor_line_pair_return_time); 930 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 931 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 932 u32 tmp, dmif_size = 12288; 933 fixed20_12 a, b, c; 934 935 if (wm->num_heads == 0) 936 return 0; 937 938 a.full = dfixed_const(2); 939 b.full = dfixed_const(1); 940 if ((wm->vsc.full > a.full) || 941 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 942 (wm->vtaps >= 5) || 943 ((wm->vsc.full >= a.full) && wm->interlaced)) 944 max_src_lines_per_dst_line = 4; 945 else 946 max_src_lines_per_dst_line = 2; 947 948 a.full = dfixed_const(available_bandwidth); 949 b.full = dfixed_const(wm->num_heads); 950 a.full = dfixed_div(a, b); 951 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 952 tmp = min(dfixed_trunc(a), tmp); 953 954 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 955 956 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 957 b.full = dfixed_const(1000); 958 c.full = dfixed_const(lb_fill_bw); 959 b.full = dfixed_div(c, b); 960 a.full = dfixed_div(a, b); 961 line_fill_time = dfixed_trunc(a); 962 963 if (line_fill_time < wm->active_time) 964 return latency; 965 else 966 return latency + (line_fill_time - wm->active_time); 967 968 } 969 970 /** 971 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 972 * average and available dram bandwidth 973 * 974 * @wm: watermark calculation data 975 * 976 * Check if the display average bandwidth fits in the display 977 * dram bandwidth (CIK). 978 * Used for display watermark bandwidth calculations 979 * Returns true if the display fits, false if not. 980 */ 981 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 982 { 983 if (dce_v11_0_average_bandwidth(wm) <= 984 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 985 return true; 986 else 987 return false; 988 } 989 990 /** 991 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 992 * average and available bandwidth 993 * 994 * @wm: watermark calculation data 995 * 996 * Check if the display average bandwidth fits in the display 997 * available bandwidth (CIK). 998 * Used for display watermark bandwidth calculations 999 * Returns true if the display fits, false if not. 1000 */ 1001 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1002 { 1003 if (dce_v11_0_average_bandwidth(wm) <= 1004 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1005 return true; 1006 else 1007 return false; 1008 } 1009 1010 /** 1011 * dce_v11_0_check_latency_hiding - check latency hiding 1012 * 1013 * @wm: watermark calculation data 1014 * 1015 * Check latency hiding (CIK). 1016 * Used for display watermark bandwidth calculations 1017 * Returns true if the display fits, false if not. 1018 */ 1019 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1020 { 1021 u32 lb_partitions = wm->lb_size / wm->src_width; 1022 u32 line_time = wm->active_time + wm->blank_time; 1023 u32 latency_tolerant_lines; 1024 u32 latency_hiding; 1025 fixed20_12 a; 1026 1027 a.full = dfixed_const(1); 1028 if (wm->vsc.full > a.full) 1029 latency_tolerant_lines = 1; 1030 else { 1031 if (lb_partitions <= (wm->vtaps + 1)) 1032 latency_tolerant_lines = 1; 1033 else 1034 latency_tolerant_lines = 2; 1035 } 1036 1037 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1038 1039 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1040 return true; 1041 else 1042 return false; 1043 } 1044 1045 /** 1046 * dce_v11_0_program_watermarks - program display watermarks 1047 * 1048 * @adev: amdgpu_device pointer 1049 * @amdgpu_crtc: the selected display controller 1050 * @lb_size: line buffer size 1051 * @num_heads: number of display controllers in use 1052 * 1053 * Calculate and program the display watermarks for the 1054 * selected display controller (CIK). 1055 */ 1056 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1057 struct amdgpu_crtc *amdgpu_crtc, 1058 u32 lb_size, u32 num_heads) 1059 { 1060 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1061 struct dce10_wm_params wm_low, wm_high; 1062 u32 active_time; 1063 u32 line_time = 0; 1064 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1065 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1066 1067 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1068 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1069 (u32)mode->clock); 1070 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1071 (u32)mode->clock); 1072 line_time = min_t(u32, line_time, 65535); 1073 1074 /* watermark for high clocks */ 1075 if (adev->pm.dpm_enabled) { 1076 wm_high.yclk = 1077 amdgpu_dpm_get_mclk(adev, false) * 10; 1078 wm_high.sclk = 1079 amdgpu_dpm_get_sclk(adev, false) * 10; 1080 } else { 1081 wm_high.yclk = adev->pm.current_mclk * 10; 1082 wm_high.sclk = adev->pm.current_sclk * 10; 1083 } 1084 1085 wm_high.disp_clk = mode->clock; 1086 wm_high.src_width = mode->crtc_hdisplay; 1087 wm_high.active_time = active_time; 1088 wm_high.blank_time = line_time - wm_high.active_time; 1089 wm_high.interlaced = false; 1090 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1091 wm_high.interlaced = true; 1092 wm_high.vsc = amdgpu_crtc->vsc; 1093 wm_high.vtaps = 1; 1094 if (amdgpu_crtc->rmx_type != RMX_OFF) 1095 wm_high.vtaps = 2; 1096 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1097 wm_high.lb_size = lb_size; 1098 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1099 wm_high.num_heads = num_heads; 1100 1101 /* set for high clocks */ 1102 latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&wm_high), 65535); 1103 1104 /* possibly force display priority to high */ 1105 /* should really do this at mode validation time... */ 1106 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1107 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1108 !dce_v11_0_check_latency_hiding(&wm_high) || 1109 (adev->mode_info.disp_priority == 2)) { 1110 DRM_DEBUG_KMS("force priority to high\n"); 1111 } 1112 1113 /* watermark for low clocks */ 1114 if (adev->pm.dpm_enabled) { 1115 wm_low.yclk = 1116 amdgpu_dpm_get_mclk(adev, true) * 10; 1117 wm_low.sclk = 1118 amdgpu_dpm_get_sclk(adev, true) * 10; 1119 } else { 1120 wm_low.yclk = adev->pm.current_mclk * 10; 1121 wm_low.sclk = adev->pm.current_sclk * 10; 1122 } 1123 1124 wm_low.disp_clk = mode->clock; 1125 wm_low.src_width = mode->crtc_hdisplay; 1126 wm_low.active_time = active_time; 1127 wm_low.blank_time = line_time - wm_low.active_time; 1128 wm_low.interlaced = false; 1129 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1130 wm_low.interlaced = true; 1131 wm_low.vsc = amdgpu_crtc->vsc; 1132 wm_low.vtaps = 1; 1133 if (amdgpu_crtc->rmx_type != RMX_OFF) 1134 wm_low.vtaps = 2; 1135 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1136 wm_low.lb_size = lb_size; 1137 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1138 wm_low.num_heads = num_heads; 1139 1140 /* set for low clocks */ 1141 latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&wm_low), 65535); 1142 1143 /* possibly force display priority to high */ 1144 /* should really do this at mode validation time... */ 1145 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1146 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1147 !dce_v11_0_check_latency_hiding(&wm_low) || 1148 (adev->mode_info.disp_priority == 2)) { 1149 DRM_DEBUG_KMS("force priority to high\n"); 1150 } 1151 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1152 } 1153 1154 /* select wm A */ 1155 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1156 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1157 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1158 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1159 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1160 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1161 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1162 /* select wm B */ 1163 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1164 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1165 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1166 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1167 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1168 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1169 /* restore original selection */ 1170 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1171 1172 /* save values for DPM */ 1173 amdgpu_crtc->line_time = line_time; 1174 amdgpu_crtc->wm_high = latency_watermark_a; 1175 amdgpu_crtc->wm_low = latency_watermark_b; 1176 /* Save number of lines the linebuffer leads before the scanout */ 1177 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1178 } 1179 1180 /** 1181 * dce_v11_0_bandwidth_update - program display watermarks 1182 * 1183 * @adev: amdgpu_device pointer 1184 * 1185 * Calculate and program the display watermarks and line 1186 * buffer allocation (CIK). 1187 */ 1188 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1189 { 1190 struct drm_display_mode *mode = NULL; 1191 u32 num_heads = 0, lb_size; 1192 int i; 1193 1194 amdgpu_display_update_priority(adev); 1195 1196 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1197 if (adev->mode_info.crtcs[i]->base.enabled) 1198 num_heads++; 1199 } 1200 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1201 mode = &adev->mode_info.crtcs[i]->base.mode; 1202 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1203 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1204 lb_size, num_heads); 1205 } 1206 } 1207 1208 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1209 { 1210 int i; 1211 u32 offset, tmp; 1212 1213 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1214 offset = adev->mode_info.audio.pin[i].offset; 1215 tmp = RREG32_AUDIO_ENDPT(offset, 1216 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1217 if (((tmp & 1218 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1219 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1220 adev->mode_info.audio.pin[i].connected = false; 1221 else 1222 adev->mode_info.audio.pin[i].connected = true; 1223 } 1224 } 1225 1226 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1227 { 1228 int i; 1229 1230 dce_v11_0_audio_get_connected_pins(adev); 1231 1232 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1233 if (adev->mode_info.audio.pin[i].connected) 1234 return &adev->mode_info.audio.pin[i]; 1235 } 1236 DRM_ERROR("No connected audio pins found!\n"); 1237 return NULL; 1238 } 1239 1240 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1241 { 1242 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1243 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1244 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1245 u32 tmp; 1246 1247 if (!dig || !dig->afmt || !dig->afmt->pin) 1248 return; 1249 1250 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1251 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1252 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1253 } 1254 1255 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1256 struct drm_display_mode *mode) 1257 { 1258 struct drm_device *dev = encoder->dev; 1259 struct amdgpu_device *adev = drm_to_adev(dev); 1260 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1261 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1262 struct drm_connector *connector; 1263 struct drm_connector_list_iter iter; 1264 struct amdgpu_connector *amdgpu_connector = NULL; 1265 u32 tmp; 1266 int interlace = 0; 1267 1268 if (!dig || !dig->afmt || !dig->afmt->pin) 1269 return; 1270 1271 drm_connector_list_iter_begin(dev, &iter); 1272 drm_for_each_connector_iter(connector, &iter) { 1273 if (connector->encoder == encoder) { 1274 amdgpu_connector = to_amdgpu_connector(connector); 1275 break; 1276 } 1277 } 1278 drm_connector_list_iter_end(&iter); 1279 1280 if (!amdgpu_connector) { 1281 DRM_ERROR("Couldn't find encoder's connector\n"); 1282 return; 1283 } 1284 1285 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1286 interlace = 1; 1287 if (connector->latency_present[interlace]) { 1288 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1289 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1290 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1291 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1292 } else { 1293 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1294 VIDEO_LIPSYNC, 0); 1295 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1296 AUDIO_LIPSYNC, 0); 1297 } 1298 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1299 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1300 } 1301 1302 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1303 { 1304 struct drm_device *dev = encoder->dev; 1305 struct amdgpu_device *adev = drm_to_adev(dev); 1306 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1307 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1308 struct drm_connector *connector; 1309 struct drm_connector_list_iter iter; 1310 struct amdgpu_connector *amdgpu_connector = NULL; 1311 u32 tmp; 1312 u8 *sadb = NULL; 1313 int sad_count; 1314 1315 if (!dig || !dig->afmt || !dig->afmt->pin) 1316 return; 1317 1318 drm_connector_list_iter_begin(dev, &iter); 1319 drm_for_each_connector_iter(connector, &iter) { 1320 if (connector->encoder == encoder) { 1321 amdgpu_connector = to_amdgpu_connector(connector); 1322 break; 1323 } 1324 } 1325 drm_connector_list_iter_end(&iter); 1326 1327 if (!amdgpu_connector) { 1328 DRM_ERROR("Couldn't find encoder's connector\n"); 1329 return; 1330 } 1331 1332 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1333 if (sad_count < 0) { 1334 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1335 sad_count = 0; 1336 } 1337 1338 /* program the speaker allocation */ 1339 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1340 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1341 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1342 DP_CONNECTION, 0); 1343 /* set HDMI mode */ 1344 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1345 HDMI_CONNECTION, 1); 1346 if (sad_count) 1347 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1348 SPEAKER_ALLOCATION, sadb[0]); 1349 else 1350 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1351 SPEAKER_ALLOCATION, 5); /* stereo */ 1352 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1353 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1354 1355 kfree(sadb); 1356 } 1357 1358 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1359 { 1360 struct drm_device *dev = encoder->dev; 1361 struct amdgpu_device *adev = drm_to_adev(dev); 1362 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1363 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1364 struct drm_connector *connector; 1365 struct drm_connector_list_iter iter; 1366 struct amdgpu_connector *amdgpu_connector = NULL; 1367 struct cea_sad *sads; 1368 int i, sad_count; 1369 1370 static const u16 eld_reg_to_type[][2] = { 1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1379 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1380 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1381 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1382 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1383 }; 1384 1385 if (!dig || !dig->afmt || !dig->afmt->pin) 1386 return; 1387 1388 drm_connector_list_iter_begin(dev, &iter); 1389 drm_for_each_connector_iter(connector, &iter) { 1390 if (connector->encoder == encoder) { 1391 amdgpu_connector = to_amdgpu_connector(connector); 1392 break; 1393 } 1394 } 1395 drm_connector_list_iter_end(&iter); 1396 1397 if (!amdgpu_connector) { 1398 DRM_ERROR("Couldn't find encoder's connector\n"); 1399 return; 1400 } 1401 1402 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1403 if (sad_count < 0) 1404 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1405 if (sad_count <= 0) 1406 return; 1407 BUG_ON(!sads); 1408 1409 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1410 u32 tmp = 0; 1411 u8 stereo_freqs = 0; 1412 int max_channels = -1; 1413 int j; 1414 1415 for (j = 0; j < sad_count; j++) { 1416 struct cea_sad *sad = &sads[j]; 1417 1418 if (sad->format == eld_reg_to_type[i][1]) { 1419 if (sad->channels > max_channels) { 1420 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1421 MAX_CHANNELS, sad->channels); 1422 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1423 DESCRIPTOR_BYTE_2, sad->byte2); 1424 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1425 SUPPORTED_FREQUENCIES, sad->freq); 1426 max_channels = sad->channels; 1427 } 1428 1429 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1430 stereo_freqs |= sad->freq; 1431 else 1432 break; 1433 } 1434 } 1435 1436 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1437 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1438 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1439 } 1440 1441 kfree(sads); 1442 } 1443 1444 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1445 struct amdgpu_audio_pin *pin, 1446 bool enable) 1447 { 1448 if (!pin) 1449 return; 1450 1451 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1452 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1453 } 1454 1455 static const u32 pin_offsets[] = 1456 { 1457 AUD0_REGISTER_OFFSET, 1458 AUD1_REGISTER_OFFSET, 1459 AUD2_REGISTER_OFFSET, 1460 AUD3_REGISTER_OFFSET, 1461 AUD4_REGISTER_OFFSET, 1462 AUD5_REGISTER_OFFSET, 1463 AUD6_REGISTER_OFFSET, 1464 AUD7_REGISTER_OFFSET, 1465 }; 1466 1467 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1468 { 1469 int i; 1470 1471 if (!amdgpu_audio) 1472 return 0; 1473 1474 adev->mode_info.audio.enabled = true; 1475 1476 switch (adev->asic_type) { 1477 case CHIP_CARRIZO: 1478 case CHIP_STONEY: 1479 adev->mode_info.audio.num_pins = 7; 1480 break; 1481 case CHIP_POLARIS10: 1482 case CHIP_VEGAM: 1483 adev->mode_info.audio.num_pins = 8; 1484 break; 1485 case CHIP_POLARIS11: 1486 case CHIP_POLARIS12: 1487 adev->mode_info.audio.num_pins = 6; 1488 break; 1489 default: 1490 return -EINVAL; 1491 } 1492 1493 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1494 adev->mode_info.audio.pin[i].channels = -1; 1495 adev->mode_info.audio.pin[i].rate = -1; 1496 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1497 adev->mode_info.audio.pin[i].status_bits = 0; 1498 adev->mode_info.audio.pin[i].category_code = 0; 1499 adev->mode_info.audio.pin[i].connected = false; 1500 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1501 adev->mode_info.audio.pin[i].id = i; 1502 /* disable audio. it will be set up later */ 1503 /* XXX remove once we switch to ip funcs */ 1504 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1505 } 1506 1507 return 0; 1508 } 1509 1510 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1511 { 1512 int i; 1513 1514 if (!amdgpu_audio) 1515 return; 1516 1517 if (!adev->mode_info.audio.enabled) 1518 return; 1519 1520 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1521 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1522 1523 adev->mode_info.audio.enabled = false; 1524 } 1525 1526 /* 1527 * update the N and CTS parameters for a given pixel clock rate 1528 */ 1529 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1530 { 1531 struct drm_device *dev = encoder->dev; 1532 struct amdgpu_device *adev = drm_to_adev(dev); 1533 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1535 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1536 u32 tmp; 1537 1538 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1539 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1540 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1541 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1542 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1543 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1544 1545 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1546 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1547 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1548 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1549 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1550 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1551 1552 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1553 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1554 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1555 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1556 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1557 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1558 1559 } 1560 1561 /* 1562 * build a HDMI Video Info Frame 1563 */ 1564 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1565 void *buffer, size_t size) 1566 { 1567 struct drm_device *dev = encoder->dev; 1568 struct amdgpu_device *adev = drm_to_adev(dev); 1569 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1570 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1571 uint8_t *frame = buffer + 3; 1572 uint8_t *header = buffer; 1573 1574 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1575 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1576 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1577 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1578 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1579 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1580 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1581 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1582 } 1583 1584 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1585 { 1586 struct drm_device *dev = encoder->dev; 1587 struct amdgpu_device *adev = drm_to_adev(dev); 1588 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1589 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1591 u32 dto_phase = 24 * 1000; 1592 u32 dto_modulo = clock; 1593 u32 tmp; 1594 1595 if (!dig || !dig->afmt) 1596 return; 1597 1598 /* XXX two dtos; generally use dto0 for hdmi */ 1599 /* Express [24MHz / target pixel clock] as an exact rational 1600 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1601 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1602 */ 1603 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1604 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1605 amdgpu_crtc->crtc_id); 1606 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1607 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1608 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1609 } 1610 1611 /* 1612 * update the info frames with the data from the current display mode 1613 */ 1614 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1615 struct drm_display_mode *mode) 1616 { 1617 struct drm_device *dev = encoder->dev; 1618 struct amdgpu_device *adev = drm_to_adev(dev); 1619 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1620 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1621 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1622 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1623 struct hdmi_avi_infoframe frame; 1624 ssize_t err; 1625 u32 tmp; 1626 int bpc = 8; 1627 1628 if (!dig || !dig->afmt) 1629 return; 1630 1631 /* Silent, r600_hdmi_enable will raise WARN for us */ 1632 if (!dig->afmt->enabled) 1633 return; 1634 1635 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1636 if (encoder->crtc) { 1637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1638 bpc = amdgpu_crtc->bpc; 1639 } 1640 1641 /* disable audio prior to setting up hw */ 1642 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1643 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1644 1645 dce_v11_0_audio_set_dto(encoder, mode->clock); 1646 1647 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1648 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1649 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1650 1651 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1652 1653 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1654 switch (bpc) { 1655 case 0: 1656 case 6: 1657 case 8: 1658 case 16: 1659 default: 1660 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1661 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1662 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1663 connector->name, bpc); 1664 break; 1665 case 10: 1666 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1667 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1668 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1669 connector->name); 1670 break; 1671 case 12: 1672 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1673 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1674 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1675 connector->name); 1676 break; 1677 } 1678 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1679 1680 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1681 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1682 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1683 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1684 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1685 1686 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1687 /* enable audio info frames (frames won't be set until audio is enabled) */ 1688 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1689 /* required for audio info values to be updated */ 1690 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1691 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1692 1693 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1694 /* required for audio info values to be updated */ 1695 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1696 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1697 1698 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1699 /* anything other than 0 */ 1700 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1701 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1702 1703 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1704 1705 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1706 /* set the default audio delay */ 1707 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1708 /* should be suffient for all audio modes and small enough for all hblanks */ 1709 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1710 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1711 1712 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1713 /* allow 60958 channel status fields to be updated */ 1714 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1715 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1716 1717 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1718 if (bpc > 8) 1719 /* clear SW CTS value */ 1720 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1721 else 1722 /* select SW CTS value */ 1723 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1724 /* allow hw to sent ACR packets when required */ 1725 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1726 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1727 1728 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1729 1730 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1731 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1732 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1733 1734 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1735 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1736 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1737 1738 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1741 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1742 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1743 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1744 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1745 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1746 1747 dce_v11_0_audio_write_speaker_allocation(encoder); 1748 1749 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1750 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1751 1752 dce_v11_0_afmt_audio_select_pin(encoder); 1753 dce_v11_0_audio_write_sad_regs(encoder); 1754 dce_v11_0_audio_write_latency_fields(encoder, mode); 1755 1756 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1757 if (err < 0) { 1758 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1759 return; 1760 } 1761 1762 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1763 if (err < 0) { 1764 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1765 return; 1766 } 1767 1768 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1769 1770 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1771 /* enable AVI info frames */ 1772 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1773 /* required for audio info values to be updated */ 1774 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1775 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1776 1777 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1778 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1779 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1780 1781 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1782 /* send audio packets */ 1783 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1784 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1785 1786 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1787 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1788 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1789 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1790 1791 /* enable audio after to setting up hw */ 1792 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1793 } 1794 1795 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1796 { 1797 struct drm_device *dev = encoder->dev; 1798 struct amdgpu_device *adev = drm_to_adev(dev); 1799 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1800 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1801 1802 if (!dig || !dig->afmt) 1803 return; 1804 1805 /* Silent, r600_hdmi_enable will raise WARN for us */ 1806 if (enable && dig->afmt->enabled) 1807 return; 1808 if (!enable && !dig->afmt->enabled) 1809 return; 1810 1811 if (!enable && dig->afmt->pin) { 1812 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1813 dig->afmt->pin = NULL; 1814 } 1815 1816 dig->afmt->enabled = enable; 1817 1818 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1819 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1820 } 1821 1822 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1823 { 1824 int i; 1825 1826 for (i = 0; i < adev->mode_info.num_dig; i++) 1827 adev->mode_info.afmt[i] = NULL; 1828 1829 /* DCE11 has audio blocks tied to DIG encoders */ 1830 for (i = 0; i < adev->mode_info.num_dig; i++) { 1831 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1832 if (adev->mode_info.afmt[i]) { 1833 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1834 adev->mode_info.afmt[i]->id = i; 1835 } else { 1836 int j; 1837 for (j = 0; j < i; j++) { 1838 kfree(adev->mode_info.afmt[j]); 1839 adev->mode_info.afmt[j] = NULL; 1840 } 1841 return -ENOMEM; 1842 } 1843 } 1844 return 0; 1845 } 1846 1847 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1848 { 1849 int i; 1850 1851 for (i = 0; i < adev->mode_info.num_dig; i++) { 1852 kfree(adev->mode_info.afmt[i]); 1853 adev->mode_info.afmt[i] = NULL; 1854 } 1855 } 1856 1857 static const u32 vga_control_regs[6] = 1858 { 1859 mmD1VGA_CONTROL, 1860 mmD2VGA_CONTROL, 1861 mmD3VGA_CONTROL, 1862 mmD4VGA_CONTROL, 1863 mmD5VGA_CONTROL, 1864 mmD6VGA_CONTROL, 1865 }; 1866 1867 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1868 { 1869 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1870 struct drm_device *dev = crtc->dev; 1871 struct amdgpu_device *adev = drm_to_adev(dev); 1872 u32 vga_control; 1873 1874 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1875 if (enable) 1876 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1877 else 1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1879 } 1880 1881 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1882 { 1883 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1884 struct drm_device *dev = crtc->dev; 1885 struct amdgpu_device *adev = drm_to_adev(dev); 1886 1887 if (enable) 1888 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1889 else 1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1891 } 1892 1893 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1894 struct drm_framebuffer *fb, 1895 int x, int y, int atomic) 1896 { 1897 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1898 struct drm_device *dev = crtc->dev; 1899 struct amdgpu_device *adev = drm_to_adev(dev); 1900 struct drm_framebuffer *target_fb; 1901 struct drm_gem_object *obj; 1902 struct amdgpu_bo *abo; 1903 uint64_t fb_location, tiling_flags; 1904 uint32_t fb_format, fb_pitch_pixels; 1905 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1906 u32 pipe_config; 1907 u32 tmp, viewport_w, viewport_h; 1908 int r; 1909 bool bypass_lut = false; 1910 1911 /* no fb bound */ 1912 if (!atomic && !crtc->primary->fb) { 1913 DRM_DEBUG_KMS("No FB bound\n"); 1914 return 0; 1915 } 1916 1917 if (atomic) 1918 target_fb = fb; 1919 else 1920 target_fb = crtc->primary->fb; 1921 1922 /* If atomic, assume fb object is pinned & idle & fenced and 1923 * just update base pointers 1924 */ 1925 obj = target_fb->obj[0]; 1926 abo = gem_to_amdgpu_bo(obj); 1927 r = amdgpu_bo_reserve(abo, false); 1928 if (unlikely(r != 0)) 1929 return r; 1930 1931 if (!atomic) { 1932 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1933 if (unlikely(r != 0)) { 1934 amdgpu_bo_unreserve(abo); 1935 return -EINVAL; 1936 } 1937 } 1938 fb_location = amdgpu_bo_gpu_offset(abo); 1939 1940 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1941 amdgpu_bo_unreserve(abo); 1942 1943 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1944 1945 switch (target_fb->format->format) { 1946 case DRM_FORMAT_C8: 1947 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1948 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1949 break; 1950 case DRM_FORMAT_XRGB4444: 1951 case DRM_FORMAT_ARGB4444: 1952 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1953 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1954 #ifdef __BIG_ENDIAN 1955 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1956 ENDIAN_8IN16); 1957 #endif 1958 break; 1959 case DRM_FORMAT_XRGB1555: 1960 case DRM_FORMAT_ARGB1555: 1961 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1962 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1963 #ifdef __BIG_ENDIAN 1964 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1965 ENDIAN_8IN16); 1966 #endif 1967 break; 1968 case DRM_FORMAT_BGRX5551: 1969 case DRM_FORMAT_BGRA5551: 1970 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1971 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1972 #ifdef __BIG_ENDIAN 1973 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1974 ENDIAN_8IN16); 1975 #endif 1976 break; 1977 case DRM_FORMAT_RGB565: 1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1980 #ifdef __BIG_ENDIAN 1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1982 ENDIAN_8IN16); 1983 #endif 1984 break; 1985 case DRM_FORMAT_XRGB8888: 1986 case DRM_FORMAT_ARGB8888: 1987 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1988 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1989 #ifdef __BIG_ENDIAN 1990 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1991 ENDIAN_8IN32); 1992 #endif 1993 break; 1994 case DRM_FORMAT_XRGB2101010: 1995 case DRM_FORMAT_ARGB2101010: 1996 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1997 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1998 #ifdef __BIG_ENDIAN 1999 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2000 ENDIAN_8IN32); 2001 #endif 2002 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2003 bypass_lut = true; 2004 break; 2005 case DRM_FORMAT_BGRX1010102: 2006 case DRM_FORMAT_BGRA1010102: 2007 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2009 #ifdef __BIG_ENDIAN 2010 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2011 ENDIAN_8IN32); 2012 #endif 2013 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2014 bypass_lut = true; 2015 break; 2016 case DRM_FORMAT_XBGR8888: 2017 case DRM_FORMAT_ABGR8888: 2018 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2019 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2020 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); 2021 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); 2022 #ifdef __BIG_ENDIAN 2023 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2024 ENDIAN_8IN32); 2025 #endif 2026 break; 2027 default: 2028 DRM_ERROR("Unsupported screen format %p4cc\n", 2029 &target_fb->format->format); 2030 return -EINVAL; 2031 } 2032 2033 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2034 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2035 2036 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2037 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2038 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2039 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2040 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2041 2042 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2043 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2044 ARRAY_2D_TILED_THIN1); 2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2046 tile_split); 2047 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2048 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2050 mtaspect); 2051 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2052 ADDR_SURF_MICRO_TILING_DISPLAY); 2053 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2054 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2055 ARRAY_1D_TILED_THIN1); 2056 } 2057 2058 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2059 pipe_config); 2060 2061 dce_v11_0_vga_enable(crtc, false); 2062 2063 /* Make sure surface address is updated at vertical blank rather than 2064 * horizontal blank 2065 */ 2066 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2067 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2068 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2069 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2070 2071 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2072 upper_32_bits(fb_location)); 2073 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2074 upper_32_bits(fb_location)); 2075 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2076 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2077 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2078 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2079 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2080 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2081 2082 /* 2083 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2084 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2085 * retain the full precision throughout the pipeline. 2086 */ 2087 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2088 if (bypass_lut) 2089 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2090 else 2091 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2092 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2093 2094 if (bypass_lut) 2095 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2096 2097 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2098 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2099 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2100 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2101 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2102 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2103 2104 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2105 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2106 2107 dce_v11_0_grph_enable(crtc, true); 2108 2109 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2110 target_fb->height); 2111 2112 x &= ~3; 2113 y &= ~1; 2114 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2115 (x << 16) | y); 2116 viewport_w = crtc->mode.hdisplay; 2117 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2118 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2119 (viewport_w << 16) | viewport_h); 2120 2121 /* set pageflip to happen anywhere in vblank interval */ 2122 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2123 2124 if (!atomic && fb && fb != crtc->primary->fb) { 2125 abo = gem_to_amdgpu_bo(fb->obj[0]); 2126 r = amdgpu_bo_reserve(abo, true); 2127 if (unlikely(r != 0)) 2128 return r; 2129 amdgpu_bo_unpin(abo); 2130 amdgpu_bo_unreserve(abo); 2131 } 2132 2133 /* Bytes per pixel may have changed */ 2134 dce_v11_0_bandwidth_update(adev); 2135 2136 return 0; 2137 } 2138 2139 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2140 struct drm_display_mode *mode) 2141 { 2142 struct drm_device *dev = crtc->dev; 2143 struct amdgpu_device *adev = drm_to_adev(dev); 2144 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2145 u32 tmp; 2146 2147 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2148 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2149 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2150 else 2151 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2152 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2153 } 2154 2155 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2156 { 2157 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2158 struct drm_device *dev = crtc->dev; 2159 struct amdgpu_device *adev = drm_to_adev(dev); 2160 u16 *r, *g, *b; 2161 int i; 2162 u32 tmp; 2163 2164 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2165 2166 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2167 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2168 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2169 2170 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2171 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2172 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2173 2174 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2175 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2176 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2177 2178 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2179 2180 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2181 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2182 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2183 2184 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2185 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2186 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2187 2188 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2189 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2190 2191 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2192 r = crtc->gamma_store; 2193 g = r + crtc->gamma_size; 2194 b = g + crtc->gamma_size; 2195 for (i = 0; i < 256; i++) { 2196 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2197 ((*r++ & 0xffc0) << 14) | 2198 ((*g++ & 0xffc0) << 4) | 2199 (*b++ >> 6)); 2200 } 2201 2202 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2203 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2204 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2205 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2206 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2207 2208 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2209 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2210 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2211 2212 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2213 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2214 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2215 2216 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2217 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2218 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2219 2220 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2221 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2222 /* XXX this only needs to be programmed once per crtc at startup, 2223 * not sure where the best place for it is 2224 */ 2225 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2226 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2227 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2228 } 2229 2230 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2231 { 2232 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2233 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2234 2235 switch (amdgpu_encoder->encoder_id) { 2236 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2237 if (dig->linkb) 2238 return 1; 2239 else 2240 return 0; 2241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2242 if (dig->linkb) 2243 return 3; 2244 else 2245 return 2; 2246 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2247 if (dig->linkb) 2248 return 5; 2249 else 2250 return 4; 2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2252 return 6; 2253 default: 2254 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2255 return 0; 2256 } 2257 } 2258 2259 /** 2260 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2261 * 2262 * @crtc: drm crtc 2263 * 2264 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2265 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2266 * monitors a dedicated PPLL must be used. If a particular board has 2267 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2268 * as there is no need to program the PLL itself. If we are not able to 2269 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2270 * avoid messing up an existing monitor. 2271 * 2272 * Asic specific PLL information 2273 * 2274 * DCE 10.x 2275 * Tonga 2276 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2277 * CI 2278 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2279 * 2280 */ 2281 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2282 { 2283 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2284 struct drm_device *dev = crtc->dev; 2285 struct amdgpu_device *adev = drm_to_adev(dev); 2286 u32 pll_in_use; 2287 int pll; 2288 2289 if ((adev->asic_type == CHIP_POLARIS10) || 2290 (adev->asic_type == CHIP_POLARIS11) || 2291 (adev->asic_type == CHIP_POLARIS12) || 2292 (adev->asic_type == CHIP_VEGAM)) { 2293 struct amdgpu_encoder *amdgpu_encoder = 2294 to_amdgpu_encoder(amdgpu_crtc->encoder); 2295 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2296 2297 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2298 return ATOM_DP_DTO; 2299 2300 switch (amdgpu_encoder->encoder_id) { 2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2302 if (dig->linkb) 2303 return ATOM_COMBOPHY_PLL1; 2304 else 2305 return ATOM_COMBOPHY_PLL0; 2306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2307 if (dig->linkb) 2308 return ATOM_COMBOPHY_PLL3; 2309 else 2310 return ATOM_COMBOPHY_PLL2; 2311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2312 if (dig->linkb) 2313 return ATOM_COMBOPHY_PLL5; 2314 else 2315 return ATOM_COMBOPHY_PLL4; 2316 default: 2317 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2318 return ATOM_PPLL_INVALID; 2319 } 2320 } 2321 2322 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2323 if (adev->clock.dp_extclk) 2324 /* skip PPLL programming if using ext clock */ 2325 return ATOM_PPLL_INVALID; 2326 else { 2327 /* use the same PPLL for all DP monitors */ 2328 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2329 if (pll != ATOM_PPLL_INVALID) 2330 return pll; 2331 } 2332 } else { 2333 /* use the same PPLL for all monitors with the same clock */ 2334 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2335 if (pll != ATOM_PPLL_INVALID) 2336 return pll; 2337 } 2338 2339 /* XXX need to determine what plls are available on each DCE11 part */ 2340 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2341 if (adev->flags & AMD_IS_APU) { 2342 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2343 return ATOM_PPLL1; 2344 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2345 return ATOM_PPLL0; 2346 DRM_ERROR("unable to allocate a PPLL\n"); 2347 return ATOM_PPLL_INVALID; 2348 } else { 2349 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2350 return ATOM_PPLL2; 2351 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2352 return ATOM_PPLL1; 2353 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2354 return ATOM_PPLL0; 2355 DRM_ERROR("unable to allocate a PPLL\n"); 2356 return ATOM_PPLL_INVALID; 2357 } 2358 return ATOM_PPLL_INVALID; 2359 } 2360 2361 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2362 { 2363 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2364 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2365 uint32_t cur_lock; 2366 2367 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2368 if (lock) 2369 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2370 else 2371 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2372 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2373 } 2374 2375 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2376 { 2377 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2378 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2379 u32 tmp; 2380 2381 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2382 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2383 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2384 } 2385 2386 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2387 { 2388 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2389 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2390 u32 tmp; 2391 2392 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2393 upper_32_bits(amdgpu_crtc->cursor_addr)); 2394 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2395 lower_32_bits(amdgpu_crtc->cursor_addr)); 2396 2397 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2398 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2399 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2400 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2401 } 2402 2403 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2404 int x, int y) 2405 { 2406 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2407 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2408 int xorigin = 0, yorigin = 0; 2409 2410 amdgpu_crtc->cursor_x = x; 2411 amdgpu_crtc->cursor_y = y; 2412 2413 /* avivo cursor are offset into the total surface */ 2414 x += crtc->x; 2415 y += crtc->y; 2416 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2417 2418 if (x < 0) { 2419 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2420 x = 0; 2421 } 2422 if (y < 0) { 2423 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2424 y = 0; 2425 } 2426 2427 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2428 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2429 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2430 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2431 2432 return 0; 2433 } 2434 2435 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2436 int x, int y) 2437 { 2438 int ret; 2439 2440 dce_v11_0_lock_cursor(crtc, true); 2441 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2442 dce_v11_0_lock_cursor(crtc, false); 2443 2444 return ret; 2445 } 2446 2447 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2448 struct drm_file *file_priv, 2449 uint32_t handle, 2450 uint32_t width, 2451 uint32_t height, 2452 int32_t hot_x, 2453 int32_t hot_y) 2454 { 2455 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2456 struct drm_gem_object *obj; 2457 struct amdgpu_bo *aobj; 2458 int ret; 2459 2460 if (!handle) { 2461 /* turn off cursor */ 2462 dce_v11_0_hide_cursor(crtc); 2463 obj = NULL; 2464 goto unpin; 2465 } 2466 2467 if ((width > amdgpu_crtc->max_cursor_width) || 2468 (height > amdgpu_crtc->max_cursor_height)) { 2469 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2470 return -EINVAL; 2471 } 2472 2473 obj = drm_gem_object_lookup(file_priv, handle); 2474 if (!obj) { 2475 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2476 return -ENOENT; 2477 } 2478 2479 aobj = gem_to_amdgpu_bo(obj); 2480 ret = amdgpu_bo_reserve(aobj, false); 2481 if (ret != 0) { 2482 drm_gem_object_put(obj); 2483 return ret; 2484 } 2485 2486 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2487 amdgpu_bo_unreserve(aobj); 2488 if (ret) { 2489 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2490 drm_gem_object_put(obj); 2491 return ret; 2492 } 2493 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2494 2495 dce_v11_0_lock_cursor(crtc, true); 2496 2497 if (width != amdgpu_crtc->cursor_width || 2498 height != amdgpu_crtc->cursor_height || 2499 hot_x != amdgpu_crtc->cursor_hot_x || 2500 hot_y != amdgpu_crtc->cursor_hot_y) { 2501 int x, y; 2502 2503 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2504 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2505 2506 dce_v11_0_cursor_move_locked(crtc, x, y); 2507 2508 amdgpu_crtc->cursor_width = width; 2509 amdgpu_crtc->cursor_height = height; 2510 amdgpu_crtc->cursor_hot_x = hot_x; 2511 amdgpu_crtc->cursor_hot_y = hot_y; 2512 } 2513 2514 dce_v11_0_show_cursor(crtc); 2515 dce_v11_0_lock_cursor(crtc, false); 2516 2517 unpin: 2518 if (amdgpu_crtc->cursor_bo) { 2519 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2520 ret = amdgpu_bo_reserve(aobj, true); 2521 if (likely(ret == 0)) { 2522 amdgpu_bo_unpin(aobj); 2523 amdgpu_bo_unreserve(aobj); 2524 } 2525 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2526 } 2527 2528 amdgpu_crtc->cursor_bo = obj; 2529 return 0; 2530 } 2531 2532 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2533 { 2534 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2535 2536 if (amdgpu_crtc->cursor_bo) { 2537 dce_v11_0_lock_cursor(crtc, true); 2538 2539 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2540 amdgpu_crtc->cursor_y); 2541 2542 dce_v11_0_show_cursor(crtc); 2543 2544 dce_v11_0_lock_cursor(crtc, false); 2545 } 2546 } 2547 2548 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2549 u16 *blue, uint32_t size, 2550 struct drm_modeset_acquire_ctx *ctx) 2551 { 2552 dce_v11_0_crtc_load_lut(crtc); 2553 2554 return 0; 2555 } 2556 2557 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2558 { 2559 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2560 2561 drm_crtc_cleanup(crtc); 2562 kfree(amdgpu_crtc); 2563 } 2564 2565 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2566 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2567 .cursor_move = dce_v11_0_crtc_cursor_move, 2568 .gamma_set = dce_v11_0_crtc_gamma_set, 2569 .set_config = amdgpu_display_crtc_set_config, 2570 .destroy = dce_v11_0_crtc_destroy, 2571 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2572 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2573 .enable_vblank = amdgpu_enable_vblank_kms, 2574 .disable_vblank = amdgpu_disable_vblank_kms, 2575 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2576 }; 2577 2578 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2579 { 2580 struct drm_device *dev = crtc->dev; 2581 struct amdgpu_device *adev = drm_to_adev(dev); 2582 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2583 unsigned type; 2584 2585 switch (mode) { 2586 case DRM_MODE_DPMS_ON: 2587 amdgpu_crtc->enabled = true; 2588 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2589 dce_v11_0_vga_enable(crtc, true); 2590 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2591 dce_v11_0_vga_enable(crtc, false); 2592 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2593 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2594 amdgpu_crtc->crtc_id); 2595 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2596 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2597 drm_crtc_vblank_on(crtc); 2598 dce_v11_0_crtc_load_lut(crtc); 2599 break; 2600 case DRM_MODE_DPMS_STANDBY: 2601 case DRM_MODE_DPMS_SUSPEND: 2602 case DRM_MODE_DPMS_OFF: 2603 drm_crtc_vblank_off(crtc); 2604 if (amdgpu_crtc->enabled) { 2605 dce_v11_0_vga_enable(crtc, true); 2606 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2607 dce_v11_0_vga_enable(crtc, false); 2608 } 2609 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2610 amdgpu_crtc->enabled = false; 2611 break; 2612 } 2613 /* adjust pm to dpms */ 2614 amdgpu_dpm_compute_clocks(adev); 2615 } 2616 2617 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2618 { 2619 /* disable crtc pair power gating before programming */ 2620 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2621 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2622 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2623 } 2624 2625 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2626 { 2627 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2628 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2629 } 2630 2631 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2632 { 2633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2634 struct drm_device *dev = crtc->dev; 2635 struct amdgpu_device *adev = drm_to_adev(dev); 2636 struct amdgpu_atom_ss ss; 2637 int i; 2638 2639 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2640 if (crtc->primary->fb) { 2641 int r; 2642 struct amdgpu_bo *abo; 2643 2644 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2645 r = amdgpu_bo_reserve(abo, true); 2646 if (unlikely(r)) 2647 DRM_ERROR("failed to reserve abo before unpin\n"); 2648 else { 2649 amdgpu_bo_unpin(abo); 2650 amdgpu_bo_unreserve(abo); 2651 } 2652 } 2653 /* disable the GRPH */ 2654 dce_v11_0_grph_enable(crtc, false); 2655 2656 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2657 2658 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2659 if (adev->mode_info.crtcs[i] && 2660 adev->mode_info.crtcs[i]->enabled && 2661 i != amdgpu_crtc->crtc_id && 2662 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2663 /* one other crtc is using this pll don't turn 2664 * off the pll 2665 */ 2666 goto done; 2667 } 2668 } 2669 2670 switch (amdgpu_crtc->pll_id) { 2671 case ATOM_PPLL0: 2672 case ATOM_PPLL1: 2673 case ATOM_PPLL2: 2674 /* disable the ppll */ 2675 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2676 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2677 break; 2678 case ATOM_COMBOPHY_PLL0: 2679 case ATOM_COMBOPHY_PLL1: 2680 case ATOM_COMBOPHY_PLL2: 2681 case ATOM_COMBOPHY_PLL3: 2682 case ATOM_COMBOPHY_PLL4: 2683 case ATOM_COMBOPHY_PLL5: 2684 /* disable the ppll */ 2685 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2686 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2687 break; 2688 default: 2689 break; 2690 } 2691 done: 2692 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2693 amdgpu_crtc->adjusted_clock = 0; 2694 amdgpu_crtc->encoder = NULL; 2695 amdgpu_crtc->connector = NULL; 2696 } 2697 2698 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2699 struct drm_display_mode *mode, 2700 struct drm_display_mode *adjusted_mode, 2701 int x, int y, struct drm_framebuffer *old_fb) 2702 { 2703 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2704 struct drm_device *dev = crtc->dev; 2705 struct amdgpu_device *adev = drm_to_adev(dev); 2706 2707 if (!amdgpu_crtc->adjusted_clock) 2708 return -EINVAL; 2709 2710 if ((adev->asic_type == CHIP_POLARIS10) || 2711 (adev->asic_type == CHIP_POLARIS11) || 2712 (adev->asic_type == CHIP_POLARIS12) || 2713 (adev->asic_type == CHIP_VEGAM)) { 2714 struct amdgpu_encoder *amdgpu_encoder = 2715 to_amdgpu_encoder(amdgpu_crtc->encoder); 2716 int encoder_mode = 2717 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2718 2719 /* SetPixelClock calculates the plls and ss values now */ 2720 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2721 amdgpu_crtc->pll_id, 2722 encoder_mode, amdgpu_encoder->encoder_id, 2723 adjusted_mode->clock, 0, 0, 0, 0, 2724 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2725 } else { 2726 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2727 } 2728 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2729 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2730 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2731 amdgpu_atombios_crtc_scaler_setup(crtc); 2732 dce_v11_0_cursor_reset(crtc); 2733 /* update the hw version fpr dpm */ 2734 amdgpu_crtc->hw_mode = *adjusted_mode; 2735 2736 return 0; 2737 } 2738 2739 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2740 const struct drm_display_mode *mode, 2741 struct drm_display_mode *adjusted_mode) 2742 { 2743 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2744 struct drm_device *dev = crtc->dev; 2745 struct drm_encoder *encoder; 2746 2747 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2749 if (encoder->crtc == crtc) { 2750 amdgpu_crtc->encoder = encoder; 2751 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2752 break; 2753 } 2754 } 2755 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2756 amdgpu_crtc->encoder = NULL; 2757 amdgpu_crtc->connector = NULL; 2758 return false; 2759 } 2760 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2761 return false; 2762 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2763 return false; 2764 /* pick pll */ 2765 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2766 /* if we can't get a PPLL for a non-DP encoder, fail */ 2767 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2768 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2769 return false; 2770 2771 return true; 2772 } 2773 2774 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2775 struct drm_framebuffer *old_fb) 2776 { 2777 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2778 } 2779 2780 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2781 struct drm_framebuffer *fb, 2782 int x, int y, enum mode_set_atomic state) 2783 { 2784 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2785 } 2786 2787 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2788 .dpms = dce_v11_0_crtc_dpms, 2789 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2790 .mode_set = dce_v11_0_crtc_mode_set, 2791 .mode_set_base = dce_v11_0_crtc_set_base, 2792 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2793 .prepare = dce_v11_0_crtc_prepare, 2794 .commit = dce_v11_0_crtc_commit, 2795 .disable = dce_v11_0_crtc_disable, 2796 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2797 }; 2798 2799 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2800 { 2801 struct amdgpu_crtc *amdgpu_crtc; 2802 2803 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2804 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2805 if (amdgpu_crtc == NULL) 2806 return -ENOMEM; 2807 2808 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2809 2810 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2811 amdgpu_crtc->crtc_id = index; 2812 adev->mode_info.crtcs[index] = amdgpu_crtc; 2813 2814 amdgpu_crtc->max_cursor_width = 128; 2815 amdgpu_crtc->max_cursor_height = 128; 2816 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2817 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2818 2819 switch (amdgpu_crtc->crtc_id) { 2820 case 0: 2821 default: 2822 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2823 break; 2824 case 1: 2825 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2826 break; 2827 case 2: 2828 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2829 break; 2830 case 3: 2831 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2832 break; 2833 case 4: 2834 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2835 break; 2836 case 5: 2837 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2838 break; 2839 } 2840 2841 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2842 amdgpu_crtc->adjusted_clock = 0; 2843 amdgpu_crtc->encoder = NULL; 2844 amdgpu_crtc->connector = NULL; 2845 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2846 2847 return 0; 2848 } 2849 2850 static int dce_v11_0_early_init(void *handle) 2851 { 2852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2853 2854 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2855 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2856 2857 dce_v11_0_set_display_funcs(adev); 2858 2859 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 2860 2861 switch (adev->asic_type) { 2862 case CHIP_CARRIZO: 2863 adev->mode_info.num_hpd = 6; 2864 adev->mode_info.num_dig = 9; 2865 break; 2866 case CHIP_STONEY: 2867 adev->mode_info.num_hpd = 6; 2868 adev->mode_info.num_dig = 9; 2869 break; 2870 case CHIP_POLARIS10: 2871 case CHIP_VEGAM: 2872 adev->mode_info.num_hpd = 6; 2873 adev->mode_info.num_dig = 6; 2874 break; 2875 case CHIP_POLARIS11: 2876 case CHIP_POLARIS12: 2877 adev->mode_info.num_hpd = 5; 2878 adev->mode_info.num_dig = 5; 2879 break; 2880 default: 2881 /* FIXME: not supported yet */ 2882 return -EINVAL; 2883 } 2884 2885 dce_v11_0_set_irq_funcs(adev); 2886 2887 return 0; 2888 } 2889 2890 static int dce_v11_0_sw_init(void *handle) 2891 { 2892 int r, i; 2893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2894 2895 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2896 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2897 if (r) 2898 return r; 2899 } 2900 2901 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2902 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2903 if (r) 2904 return r; 2905 } 2906 2907 /* HPD hotplug */ 2908 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2909 if (r) 2910 return r; 2911 2912 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2913 2914 adev_to_drm(adev)->mode_config.async_page_flip = true; 2915 2916 adev_to_drm(adev)->mode_config.max_width = 16384; 2917 adev_to_drm(adev)->mode_config.max_height = 16384; 2918 2919 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2920 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2921 2922 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2923 2924 r = amdgpu_display_modeset_create_props(adev); 2925 if (r) 2926 return r; 2927 2928 adev_to_drm(adev)->mode_config.max_width = 16384; 2929 adev_to_drm(adev)->mode_config.max_height = 16384; 2930 2931 2932 /* allocate crtcs */ 2933 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2934 r = dce_v11_0_crtc_init(adev, i); 2935 if (r) 2936 return r; 2937 } 2938 2939 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2940 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2941 else 2942 return -EINVAL; 2943 2944 /* setup afmt */ 2945 r = dce_v11_0_afmt_init(adev); 2946 if (r) 2947 return r; 2948 2949 r = dce_v11_0_audio_init(adev); 2950 if (r) 2951 return r; 2952 2953 /* Disable vblank IRQs aggressively for power-saving */ 2954 /* XXX: can this be enabled for DC? */ 2955 adev_to_drm(adev)->vblank_disable_immediate = true; 2956 2957 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2958 if (r) 2959 return r; 2960 2961 INIT_DELAYED_WORK(&adev->hotplug_work, 2962 amdgpu_display_hotplug_work_func); 2963 2964 drm_kms_helper_poll_init(adev_to_drm(adev)); 2965 2966 adev->mode_info.mode_config_initialized = true; 2967 return 0; 2968 } 2969 2970 static int dce_v11_0_sw_fini(void *handle) 2971 { 2972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2973 2974 kfree(adev->mode_info.bios_hardcoded_edid); 2975 2976 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2977 2978 dce_v11_0_audio_fini(adev); 2979 2980 dce_v11_0_afmt_fini(adev); 2981 2982 drm_mode_config_cleanup(adev_to_drm(adev)); 2983 adev->mode_info.mode_config_initialized = false; 2984 2985 return 0; 2986 } 2987 2988 static int dce_v11_0_hw_init(void *handle) 2989 { 2990 int i; 2991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2992 2993 dce_v11_0_init_golden_registers(adev); 2994 2995 /* disable vga render */ 2996 dce_v11_0_set_vga_render_state(adev, false); 2997 /* init dig PHYs, disp eng pll */ 2998 amdgpu_atombios_crtc_powergate_init(adev); 2999 amdgpu_atombios_encoder_init_dig(adev); 3000 if ((adev->asic_type == CHIP_POLARIS10) || 3001 (adev->asic_type == CHIP_POLARIS11) || 3002 (adev->asic_type == CHIP_POLARIS12) || 3003 (adev->asic_type == CHIP_VEGAM)) { 3004 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 3005 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 3006 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 3007 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 3008 } else { 3009 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3010 } 3011 3012 /* initialize hpd */ 3013 dce_v11_0_hpd_init(adev); 3014 3015 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3016 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3017 } 3018 3019 dce_v11_0_pageflip_interrupt_init(adev); 3020 3021 return 0; 3022 } 3023 3024 static int dce_v11_0_hw_fini(void *handle) 3025 { 3026 int i; 3027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3028 3029 dce_v11_0_hpd_fini(adev); 3030 3031 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3032 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3033 } 3034 3035 dce_v11_0_pageflip_interrupt_fini(adev); 3036 3037 flush_delayed_work(&adev->hotplug_work); 3038 3039 return 0; 3040 } 3041 3042 static int dce_v11_0_suspend(void *handle) 3043 { 3044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3045 int r; 3046 3047 r = amdgpu_display_suspend_helper(adev); 3048 if (r) 3049 return r; 3050 3051 adev->mode_info.bl_level = 3052 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 3053 3054 return dce_v11_0_hw_fini(handle); 3055 } 3056 3057 static int dce_v11_0_resume(void *handle) 3058 { 3059 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3060 int ret; 3061 3062 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 3063 adev->mode_info.bl_level); 3064 3065 ret = dce_v11_0_hw_init(handle); 3066 3067 /* turn on the BL */ 3068 if (adev->mode_info.bl_encoder) { 3069 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3070 adev->mode_info.bl_encoder); 3071 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3072 bl_level); 3073 } 3074 if (ret) 3075 return ret; 3076 3077 return amdgpu_display_resume_helper(adev); 3078 } 3079 3080 static bool dce_v11_0_is_idle(void *handle) 3081 { 3082 return true; 3083 } 3084 3085 static int dce_v11_0_wait_for_idle(void *handle) 3086 { 3087 return 0; 3088 } 3089 3090 static int dce_v11_0_soft_reset(void *handle) 3091 { 3092 u32 srbm_soft_reset = 0, tmp; 3093 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3094 3095 if (dce_v11_0_is_display_hung(adev)) 3096 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3097 3098 if (srbm_soft_reset) { 3099 tmp = RREG32(mmSRBM_SOFT_RESET); 3100 tmp |= srbm_soft_reset; 3101 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3102 WREG32(mmSRBM_SOFT_RESET, tmp); 3103 tmp = RREG32(mmSRBM_SOFT_RESET); 3104 3105 udelay(50); 3106 3107 tmp &= ~srbm_soft_reset; 3108 WREG32(mmSRBM_SOFT_RESET, tmp); 3109 tmp = RREG32(mmSRBM_SOFT_RESET); 3110 3111 /* Wait a little for things to settle down */ 3112 udelay(50); 3113 } 3114 return 0; 3115 } 3116 3117 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3118 int crtc, 3119 enum amdgpu_interrupt_state state) 3120 { 3121 u32 lb_interrupt_mask; 3122 3123 if (crtc >= adev->mode_info.num_crtc) { 3124 DRM_DEBUG("invalid crtc %d\n", crtc); 3125 return; 3126 } 3127 3128 switch (state) { 3129 case AMDGPU_IRQ_STATE_DISABLE: 3130 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3131 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3132 VBLANK_INTERRUPT_MASK, 0); 3133 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3134 break; 3135 case AMDGPU_IRQ_STATE_ENABLE: 3136 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3137 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3138 VBLANK_INTERRUPT_MASK, 1); 3139 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3140 break; 3141 default: 3142 break; 3143 } 3144 } 3145 3146 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3147 int crtc, 3148 enum amdgpu_interrupt_state state) 3149 { 3150 u32 lb_interrupt_mask; 3151 3152 if (crtc >= adev->mode_info.num_crtc) { 3153 DRM_DEBUG("invalid crtc %d\n", crtc); 3154 return; 3155 } 3156 3157 switch (state) { 3158 case AMDGPU_IRQ_STATE_DISABLE: 3159 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3160 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3161 VLINE_INTERRUPT_MASK, 0); 3162 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3163 break; 3164 case AMDGPU_IRQ_STATE_ENABLE: 3165 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3166 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3167 VLINE_INTERRUPT_MASK, 1); 3168 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3169 break; 3170 default: 3171 break; 3172 } 3173 } 3174 3175 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3176 struct amdgpu_irq_src *source, 3177 unsigned hpd, 3178 enum amdgpu_interrupt_state state) 3179 { 3180 u32 tmp; 3181 3182 if (hpd >= adev->mode_info.num_hpd) { 3183 DRM_DEBUG("invalid hdp %d\n", hpd); 3184 return 0; 3185 } 3186 3187 switch (state) { 3188 case AMDGPU_IRQ_STATE_DISABLE: 3189 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3190 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3191 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3192 break; 3193 case AMDGPU_IRQ_STATE_ENABLE: 3194 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3195 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3196 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3197 break; 3198 default: 3199 break; 3200 } 3201 3202 return 0; 3203 } 3204 3205 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3206 struct amdgpu_irq_src *source, 3207 unsigned type, 3208 enum amdgpu_interrupt_state state) 3209 { 3210 switch (type) { 3211 case AMDGPU_CRTC_IRQ_VBLANK1: 3212 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3213 break; 3214 case AMDGPU_CRTC_IRQ_VBLANK2: 3215 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3216 break; 3217 case AMDGPU_CRTC_IRQ_VBLANK3: 3218 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3219 break; 3220 case AMDGPU_CRTC_IRQ_VBLANK4: 3221 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3222 break; 3223 case AMDGPU_CRTC_IRQ_VBLANK5: 3224 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3225 break; 3226 case AMDGPU_CRTC_IRQ_VBLANK6: 3227 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3228 break; 3229 case AMDGPU_CRTC_IRQ_VLINE1: 3230 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3231 break; 3232 case AMDGPU_CRTC_IRQ_VLINE2: 3233 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3234 break; 3235 case AMDGPU_CRTC_IRQ_VLINE3: 3236 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3237 break; 3238 case AMDGPU_CRTC_IRQ_VLINE4: 3239 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3240 break; 3241 case AMDGPU_CRTC_IRQ_VLINE5: 3242 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3243 break; 3244 case AMDGPU_CRTC_IRQ_VLINE6: 3245 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3246 break; 3247 default: 3248 break; 3249 } 3250 return 0; 3251 } 3252 3253 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3254 struct amdgpu_irq_src *src, 3255 unsigned type, 3256 enum amdgpu_interrupt_state state) 3257 { 3258 u32 reg; 3259 3260 if (type >= adev->mode_info.num_crtc) { 3261 DRM_ERROR("invalid pageflip crtc %d\n", type); 3262 return -EINVAL; 3263 } 3264 3265 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3266 if (state == AMDGPU_IRQ_STATE_DISABLE) 3267 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3268 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3269 else 3270 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3271 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3272 3273 return 0; 3274 } 3275 3276 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3277 struct amdgpu_irq_src *source, 3278 struct amdgpu_iv_entry *entry) 3279 { 3280 unsigned long flags; 3281 unsigned crtc_id; 3282 struct amdgpu_crtc *amdgpu_crtc; 3283 struct amdgpu_flip_work *works; 3284 3285 crtc_id = (entry->src_id - 8) >> 1; 3286 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3287 3288 if (crtc_id >= adev->mode_info.num_crtc) { 3289 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3290 return -EINVAL; 3291 } 3292 3293 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3294 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3295 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3296 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3297 3298 /* IRQ could occur when in initial stage */ 3299 if(amdgpu_crtc == NULL) 3300 return 0; 3301 3302 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3303 works = amdgpu_crtc->pflip_works; 3304 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3305 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3306 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3307 amdgpu_crtc->pflip_status, 3308 AMDGPU_FLIP_SUBMITTED); 3309 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3310 return 0; 3311 } 3312 3313 /* page flip completed. clean up */ 3314 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3315 amdgpu_crtc->pflip_works = NULL; 3316 3317 /* wakeup usersapce */ 3318 if(works->event) 3319 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3320 3321 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3322 3323 drm_crtc_vblank_put(&amdgpu_crtc->base); 3324 schedule_work(&works->unpin_work); 3325 3326 return 0; 3327 } 3328 3329 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3330 int hpd) 3331 { 3332 u32 tmp; 3333 3334 if (hpd >= adev->mode_info.num_hpd) { 3335 DRM_DEBUG("invalid hdp %d\n", hpd); 3336 return; 3337 } 3338 3339 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3340 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3342 } 3343 3344 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3345 int crtc) 3346 { 3347 u32 tmp; 3348 3349 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3350 DRM_DEBUG("invalid crtc %d\n", crtc); 3351 return; 3352 } 3353 3354 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3355 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3356 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3357 } 3358 3359 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3360 int crtc) 3361 { 3362 u32 tmp; 3363 3364 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3365 DRM_DEBUG("invalid crtc %d\n", crtc); 3366 return; 3367 } 3368 3369 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3370 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3371 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3372 } 3373 3374 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3375 struct amdgpu_irq_src *source, 3376 struct amdgpu_iv_entry *entry) 3377 { 3378 unsigned crtc = entry->src_id - 1; 3379 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3380 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3381 crtc); 3382 3383 switch (entry->src_data[0]) { 3384 case 0: /* vblank */ 3385 if (disp_int & interrupt_status_offsets[crtc].vblank) 3386 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3387 else 3388 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3389 3390 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3391 drm_handle_vblank(adev_to_drm(adev), crtc); 3392 } 3393 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3394 3395 break; 3396 case 1: /* vline */ 3397 if (disp_int & interrupt_status_offsets[crtc].vline) 3398 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3399 else 3400 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3401 3402 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3403 3404 break; 3405 default: 3406 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3407 break; 3408 } 3409 3410 return 0; 3411 } 3412 3413 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3414 struct amdgpu_irq_src *source, 3415 struct amdgpu_iv_entry *entry) 3416 { 3417 uint32_t disp_int, mask; 3418 unsigned hpd; 3419 3420 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3421 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3422 return 0; 3423 } 3424 3425 hpd = entry->src_data[0]; 3426 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3427 mask = interrupt_status_offsets[hpd].hpd; 3428 3429 if (disp_int & mask) { 3430 dce_v11_0_hpd_int_ack(adev, hpd); 3431 schedule_delayed_work(&adev->hotplug_work, 0); 3432 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3433 } 3434 3435 return 0; 3436 } 3437 3438 static int dce_v11_0_set_clockgating_state(void *handle, 3439 enum amd_clockgating_state state) 3440 { 3441 return 0; 3442 } 3443 3444 static int dce_v11_0_set_powergating_state(void *handle, 3445 enum amd_powergating_state state) 3446 { 3447 return 0; 3448 } 3449 3450 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3451 .name = "dce_v11_0", 3452 .early_init = dce_v11_0_early_init, 3453 .late_init = NULL, 3454 .sw_init = dce_v11_0_sw_init, 3455 .sw_fini = dce_v11_0_sw_fini, 3456 .hw_init = dce_v11_0_hw_init, 3457 .hw_fini = dce_v11_0_hw_fini, 3458 .suspend = dce_v11_0_suspend, 3459 .resume = dce_v11_0_resume, 3460 .is_idle = dce_v11_0_is_idle, 3461 .wait_for_idle = dce_v11_0_wait_for_idle, 3462 .soft_reset = dce_v11_0_soft_reset, 3463 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3464 .set_powergating_state = dce_v11_0_set_powergating_state, 3465 }; 3466 3467 static void 3468 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3469 struct drm_display_mode *mode, 3470 struct drm_display_mode *adjusted_mode) 3471 { 3472 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3473 3474 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3475 3476 /* need to call this here rather than in prepare() since we need some crtc info */ 3477 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3478 3479 /* set scaler clears this on some chips */ 3480 dce_v11_0_set_interleave(encoder->crtc, mode); 3481 3482 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3483 dce_v11_0_afmt_enable(encoder, true); 3484 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3485 } 3486 } 3487 3488 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3489 { 3490 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3491 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3492 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3493 3494 if ((amdgpu_encoder->active_device & 3495 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3496 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3497 ENCODER_OBJECT_ID_NONE)) { 3498 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3499 if (dig) { 3500 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3501 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3502 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3503 } 3504 } 3505 3506 amdgpu_atombios_scratch_regs_lock(adev, true); 3507 3508 if (connector) { 3509 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3510 3511 /* select the clock/data port if it uses a router */ 3512 if (amdgpu_connector->router.cd_valid) 3513 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3514 3515 /* turn eDP panel on for mode set */ 3516 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3517 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3518 ATOM_TRANSMITTER_ACTION_POWER_ON); 3519 } 3520 3521 /* this is needed for the pll/ss setup to work correctly in some cases */ 3522 amdgpu_atombios_encoder_set_crtc_source(encoder); 3523 /* set up the FMT blocks */ 3524 dce_v11_0_program_fmt(encoder); 3525 } 3526 3527 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3528 { 3529 struct drm_device *dev = encoder->dev; 3530 struct amdgpu_device *adev = drm_to_adev(dev); 3531 3532 /* need to call this here as we need the crtc set up */ 3533 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3534 amdgpu_atombios_scratch_regs_lock(adev, false); 3535 } 3536 3537 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3538 { 3539 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3540 struct amdgpu_encoder_atom_dig *dig; 3541 3542 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3543 3544 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3545 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3546 dce_v11_0_afmt_enable(encoder, false); 3547 dig = amdgpu_encoder->enc_priv; 3548 dig->dig_encoder = -1; 3549 } 3550 amdgpu_encoder->active_device = 0; 3551 } 3552 3553 /* these are handled by the primary encoders */ 3554 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3555 { 3556 3557 } 3558 3559 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3560 { 3561 3562 } 3563 3564 static void 3565 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3566 struct drm_display_mode *mode, 3567 struct drm_display_mode *adjusted_mode) 3568 { 3569 3570 } 3571 3572 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3573 { 3574 3575 } 3576 3577 static void 3578 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3579 { 3580 3581 } 3582 3583 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3584 .dpms = dce_v11_0_ext_dpms, 3585 .prepare = dce_v11_0_ext_prepare, 3586 .mode_set = dce_v11_0_ext_mode_set, 3587 .commit = dce_v11_0_ext_commit, 3588 .disable = dce_v11_0_ext_disable, 3589 /* no detect for TMDS/LVDS yet */ 3590 }; 3591 3592 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3593 .dpms = amdgpu_atombios_encoder_dpms, 3594 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3595 .prepare = dce_v11_0_encoder_prepare, 3596 .mode_set = dce_v11_0_encoder_mode_set, 3597 .commit = dce_v11_0_encoder_commit, 3598 .disable = dce_v11_0_encoder_disable, 3599 .detect = amdgpu_atombios_encoder_dig_detect, 3600 }; 3601 3602 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3603 .dpms = amdgpu_atombios_encoder_dpms, 3604 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3605 .prepare = dce_v11_0_encoder_prepare, 3606 .mode_set = dce_v11_0_encoder_mode_set, 3607 .commit = dce_v11_0_encoder_commit, 3608 .detect = amdgpu_atombios_encoder_dac_detect, 3609 }; 3610 3611 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3612 { 3613 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3614 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3615 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3616 kfree(amdgpu_encoder->enc_priv); 3617 drm_encoder_cleanup(encoder); 3618 kfree(amdgpu_encoder); 3619 } 3620 3621 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3622 .destroy = dce_v11_0_encoder_destroy, 3623 }; 3624 3625 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3626 uint32_t encoder_enum, 3627 uint32_t supported_device, 3628 u16 caps) 3629 { 3630 struct drm_device *dev = adev_to_drm(adev); 3631 struct drm_encoder *encoder; 3632 struct amdgpu_encoder *amdgpu_encoder; 3633 3634 /* see if we already added it */ 3635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3636 amdgpu_encoder = to_amdgpu_encoder(encoder); 3637 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3638 amdgpu_encoder->devices |= supported_device; 3639 return; 3640 } 3641 3642 } 3643 3644 /* add a new one */ 3645 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3646 if (!amdgpu_encoder) 3647 return; 3648 3649 encoder = &amdgpu_encoder->base; 3650 switch (adev->mode_info.num_crtc) { 3651 case 1: 3652 encoder->possible_crtcs = 0x1; 3653 break; 3654 case 2: 3655 default: 3656 encoder->possible_crtcs = 0x3; 3657 break; 3658 case 3: 3659 encoder->possible_crtcs = 0x7; 3660 break; 3661 case 4: 3662 encoder->possible_crtcs = 0xf; 3663 break; 3664 case 5: 3665 encoder->possible_crtcs = 0x1f; 3666 break; 3667 case 6: 3668 encoder->possible_crtcs = 0x3f; 3669 break; 3670 } 3671 3672 amdgpu_encoder->enc_priv = NULL; 3673 3674 amdgpu_encoder->encoder_enum = encoder_enum; 3675 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3676 amdgpu_encoder->devices = supported_device; 3677 amdgpu_encoder->rmx_type = RMX_OFF; 3678 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3679 amdgpu_encoder->is_ext_encoder = false; 3680 amdgpu_encoder->caps = caps; 3681 3682 switch (amdgpu_encoder->encoder_id) { 3683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3684 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3685 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3686 DRM_MODE_ENCODER_DAC, NULL); 3687 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3688 break; 3689 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3690 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3691 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3692 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3693 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3694 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3695 amdgpu_encoder->rmx_type = RMX_FULL; 3696 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3697 DRM_MODE_ENCODER_LVDS, NULL); 3698 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3699 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3700 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3701 DRM_MODE_ENCODER_DAC, NULL); 3702 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3703 } else { 3704 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3705 DRM_MODE_ENCODER_TMDS, NULL); 3706 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3707 } 3708 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3709 break; 3710 case ENCODER_OBJECT_ID_SI170B: 3711 case ENCODER_OBJECT_ID_CH7303: 3712 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3713 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3714 case ENCODER_OBJECT_ID_TITFP513: 3715 case ENCODER_OBJECT_ID_VT1623: 3716 case ENCODER_OBJECT_ID_HDMI_SI1930: 3717 case ENCODER_OBJECT_ID_TRAVIS: 3718 case ENCODER_OBJECT_ID_NUTMEG: 3719 /* these are handled by the primary encoders */ 3720 amdgpu_encoder->is_ext_encoder = true; 3721 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3722 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3723 DRM_MODE_ENCODER_LVDS, NULL); 3724 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3725 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3726 DRM_MODE_ENCODER_DAC, NULL); 3727 else 3728 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3729 DRM_MODE_ENCODER_TMDS, NULL); 3730 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3731 break; 3732 } 3733 } 3734 3735 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3736 .bandwidth_update = &dce_v11_0_bandwidth_update, 3737 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3738 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3739 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3740 .hpd_sense = &dce_v11_0_hpd_sense, 3741 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3742 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3743 .page_flip = &dce_v11_0_page_flip, 3744 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3745 .add_encoder = &dce_v11_0_encoder_add, 3746 .add_connector = &amdgpu_connector_add, 3747 }; 3748 3749 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3750 { 3751 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3752 } 3753 3754 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3755 .set = dce_v11_0_set_crtc_irq_state, 3756 .process = dce_v11_0_crtc_irq, 3757 }; 3758 3759 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3760 .set = dce_v11_0_set_pageflip_irq_state, 3761 .process = dce_v11_0_pageflip_irq, 3762 }; 3763 3764 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3765 .set = dce_v11_0_set_hpd_irq_state, 3766 .process = dce_v11_0_hpd_irq, 3767 }; 3768 3769 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3770 { 3771 if (adev->mode_info.num_crtc > 0) 3772 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3773 else 3774 adev->crtc_irq.num_types = 0; 3775 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3776 3777 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3778 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3779 3780 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3781 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3782 } 3783 3784 const struct amdgpu_ip_block_version dce_v11_0_ip_block = 3785 { 3786 .type = AMD_IP_BLOCK_TYPE_DCE, 3787 .major = 11, 3788 .minor = 0, 3789 .rev = 0, 3790 .funcs = &dce_v11_0_ip_funcs, 3791 }; 3792 3793 const struct amdgpu_ip_block_version dce_v11_2_ip_block = 3794 { 3795 .type = AMD_IP_BLOCK_TYPE_DCE, 3796 .major = 11, 3797 .minor = 2, 3798 .rev = 0, 3799 .funcs = &dce_v11_0_ip_funcs, 3800 }; 3801