1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static const u32 cz_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 stoney_golden_settings_a11[] = 130 { 131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 132 mmFBC_MISC, 0x1f311fff, 0x14302000, 133 }; 134 135 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 137 { 138 switch (adev->asic_type) { 139 case CHIP_CARRIZO: 140 amdgpu_program_register_sequence(adev, 141 cz_mgcg_cgcg_init, 142 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 143 amdgpu_program_register_sequence(adev, 144 cz_golden_settings_a11, 145 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 146 break; 147 case CHIP_STONEY: 148 amdgpu_program_register_sequence(adev, 149 stoney_golden_settings_a11, 150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 151 break; 152 default: 153 break; 154 } 155 } 156 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 158 u32 block_offset, u32 reg) 159 { 160 unsigned long flags; 161 u32 r; 162 163 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 166 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 167 168 return r; 169 } 170 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 172 u32 block_offset, u32 reg, u32 v) 173 { 174 unsigned long flags; 175 176 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 179 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 180 } 181 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 183 { 184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 186 return true; 187 else 188 return false; 189 } 190 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 192 { 193 u32 pos1, pos2; 194 195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 197 198 if (pos1 != pos2) 199 return true; 200 else 201 return false; 202 } 203 204 /** 205 * dce_v11_0_vblank_wait - vblank wait asic callback. 206 * 207 * @adev: amdgpu_device pointer 208 * @crtc: crtc to wait for vblank on 209 * 210 * Wait for vblank on the requested crtc (evergreen+). 211 */ 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 213 { 214 unsigned i = 100; 215 216 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 217 return; 218 219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 220 return; 221 222 /* depending on when we hit vblank, we may be close to active; if so, 223 * wait for another frame. 224 */ 225 while (dce_v11_0_is_in_vblank(adev, crtc)) { 226 if (i++ == 100) { 227 i = 0; 228 if (!dce_v11_0_is_counter_moving(adev, crtc)) 229 break; 230 } 231 } 232 233 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 234 if (i++ == 100) { 235 i = 0; 236 if (!dce_v11_0_is_counter_moving(adev, crtc)) 237 break; 238 } 239 } 240 } 241 242 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 243 { 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 245 return 0; 246 else 247 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 248 } 249 250 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 251 { 252 unsigned i; 253 254 /* Enable pflip interrupts */ 255 for (i = 0; i < adev->mode_info.num_crtc; i++) 256 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 257 } 258 259 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 260 { 261 unsigned i; 262 263 /* Disable pflip interrupts */ 264 for (i = 0; i < adev->mode_info.num_crtc; i++) 265 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 266 } 267 268 /** 269 * dce_v11_0_page_flip - pageflip callback. 270 * 271 * @adev: amdgpu_device pointer 272 * @crtc_id: crtc to cleanup pageflip on 273 * @crtc_base: new address of the crtc (GPU MC address) 274 * 275 * Triggers the actual pageflip by updating the primary 276 * surface base address. 277 */ 278 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 279 int crtc_id, u64 crtc_base) 280 { 281 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 282 283 /* update the scanout addresses */ 284 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 285 upper_32_bits(crtc_base)); 286 /* writing to the low address triggers the update */ 287 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 288 lower_32_bits(crtc_base)); 289 /* post the write */ 290 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 291 } 292 293 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 294 u32 *vbl, u32 *position) 295 { 296 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 297 return -EINVAL; 298 299 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 300 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 301 302 return 0; 303 } 304 305 /** 306 * dce_v11_0_hpd_sense - hpd sense callback. 307 * 308 * @adev: amdgpu_device pointer 309 * @hpd: hpd (hotplug detect) pin 310 * 311 * Checks if a digital monitor is connected (evergreen+). 312 * Returns true if connected, false if not connected. 313 */ 314 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 315 enum amdgpu_hpd_id hpd) 316 { 317 int idx; 318 bool connected = false; 319 320 switch (hpd) { 321 case AMDGPU_HPD_1: 322 idx = 0; 323 break; 324 case AMDGPU_HPD_2: 325 idx = 1; 326 break; 327 case AMDGPU_HPD_3: 328 idx = 2; 329 break; 330 case AMDGPU_HPD_4: 331 idx = 3; 332 break; 333 case AMDGPU_HPD_5: 334 idx = 4; 335 break; 336 case AMDGPU_HPD_6: 337 idx = 5; 338 break; 339 default: 340 return connected; 341 } 342 343 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 344 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 345 connected = true; 346 347 return connected; 348 } 349 350 /** 351 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 352 * 353 * @adev: amdgpu_device pointer 354 * @hpd: hpd (hotplug detect) pin 355 * 356 * Set the polarity of the hpd pin (evergreen+). 357 */ 358 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 359 enum amdgpu_hpd_id hpd) 360 { 361 u32 tmp; 362 bool connected = dce_v11_0_hpd_sense(adev, hpd); 363 int idx; 364 365 switch (hpd) { 366 case AMDGPU_HPD_1: 367 idx = 0; 368 break; 369 case AMDGPU_HPD_2: 370 idx = 1; 371 break; 372 case AMDGPU_HPD_3: 373 idx = 2; 374 break; 375 case AMDGPU_HPD_4: 376 idx = 3; 377 break; 378 case AMDGPU_HPD_5: 379 idx = 4; 380 break; 381 case AMDGPU_HPD_6: 382 idx = 5; 383 break; 384 default: 385 return; 386 } 387 388 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 389 if (connected) 390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 391 else 392 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 393 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 394 } 395 396 /** 397 * dce_v11_0_hpd_init - hpd setup callback. 398 * 399 * @adev: amdgpu_device pointer 400 * 401 * Setup the hpd pins used by the card (evergreen+). 402 * Enable the pin, set the polarity, and enable the hpd interrupts. 403 */ 404 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 405 { 406 struct drm_device *dev = adev->ddev; 407 struct drm_connector *connector; 408 u32 tmp; 409 int idx; 410 411 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 412 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 413 414 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 415 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 416 /* don't try to enable hpd on eDP or LVDS avoid breaking the 417 * aux dp channel on imac and help (but not completely fix) 418 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 419 * also avoid interrupt storms during dpms. 420 */ 421 continue; 422 } 423 424 switch (amdgpu_connector->hpd.hpd) { 425 case AMDGPU_HPD_1: 426 idx = 0; 427 break; 428 case AMDGPU_HPD_2: 429 idx = 1; 430 break; 431 case AMDGPU_HPD_3: 432 idx = 2; 433 break; 434 case AMDGPU_HPD_4: 435 idx = 3; 436 break; 437 case AMDGPU_HPD_5: 438 idx = 4; 439 break; 440 case AMDGPU_HPD_6: 441 idx = 5; 442 break; 443 default: 444 continue; 445 } 446 447 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 448 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 449 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 450 451 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 452 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 453 DC_HPD_CONNECT_INT_DELAY, 454 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 455 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 456 DC_HPD_DISCONNECT_INT_DELAY, 457 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 458 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 459 460 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 461 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 462 } 463 } 464 465 /** 466 * dce_v11_0_hpd_fini - hpd tear down callback. 467 * 468 * @adev: amdgpu_device pointer 469 * 470 * Tear down the hpd pins used by the card (evergreen+). 471 * Disable the hpd interrupts. 472 */ 473 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 474 { 475 struct drm_device *dev = adev->ddev; 476 struct drm_connector *connector; 477 u32 tmp; 478 int idx; 479 480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 481 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 482 483 switch (amdgpu_connector->hpd.hpd) { 484 case AMDGPU_HPD_1: 485 idx = 0; 486 break; 487 case AMDGPU_HPD_2: 488 idx = 1; 489 break; 490 case AMDGPU_HPD_3: 491 idx = 2; 492 break; 493 case AMDGPU_HPD_4: 494 idx = 3; 495 break; 496 case AMDGPU_HPD_5: 497 idx = 4; 498 break; 499 case AMDGPU_HPD_6: 500 idx = 5; 501 break; 502 default: 503 continue; 504 } 505 506 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 507 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 508 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 509 510 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 511 } 512 } 513 514 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 515 { 516 return mmDC_GPIO_HPD_A; 517 } 518 519 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 520 { 521 u32 crtc_hung = 0; 522 u32 crtc_status[6]; 523 u32 i, j, tmp; 524 525 for (i = 0; i < adev->mode_info.num_crtc; i++) { 526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 527 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 528 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 529 crtc_hung |= (1 << i); 530 } 531 } 532 533 for (j = 0; j < 10; j++) { 534 for (i = 0; i < adev->mode_info.num_crtc; i++) { 535 if (crtc_hung & (1 << i)) { 536 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 537 if (tmp != crtc_status[i]) 538 crtc_hung &= ~(1 << i); 539 } 540 } 541 if (crtc_hung == 0) 542 return false; 543 udelay(100); 544 } 545 546 return true; 547 } 548 549 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 550 struct amdgpu_mode_mc_save *save) 551 { 552 u32 crtc_enabled, tmp; 553 int i; 554 555 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 556 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 557 558 /* disable VGA render */ 559 tmp = RREG32(mmVGA_RENDER_CONTROL); 560 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 561 WREG32(mmVGA_RENDER_CONTROL, tmp); 562 563 /* blank the display controllers */ 564 for (i = 0; i < adev->mode_info.num_crtc; i++) { 565 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 566 CRTC_CONTROL, CRTC_MASTER_EN); 567 if (crtc_enabled) { 568 #if 1 569 save->crtc_enabled[i] = true; 570 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 571 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 572 /*it is correct only for RGB ; black is 0*/ 573 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 574 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 575 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 576 } 577 #else 578 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 579 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 580 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 581 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 582 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 583 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 584 save->crtc_enabled[i] = false; 585 /* ***** */ 586 #endif 587 } else { 588 save->crtc_enabled[i] = false; 589 } 590 } 591 } 592 593 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 594 struct amdgpu_mode_mc_save *save) 595 { 596 u32 tmp; 597 int i; 598 599 /* update crtc base addresses */ 600 for (i = 0; i < adev->mode_info.num_crtc; i++) { 601 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 602 upper_32_bits(adev->mc.vram_start)); 603 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 604 (u32)adev->mc.vram_start); 605 606 if (save->crtc_enabled[i]) { 607 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 608 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 609 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 610 } 611 } 612 613 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 614 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 615 616 /* Unlock vga access */ 617 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 618 mdelay(1); 619 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 620 } 621 622 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 623 bool render) 624 { 625 u32 tmp; 626 627 /* Lockout access through VGA aperture*/ 628 tmp = RREG32(mmVGA_HDP_CONTROL); 629 if (render) 630 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 631 else 632 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 633 WREG32(mmVGA_HDP_CONTROL, tmp); 634 635 /* disable VGA render */ 636 tmp = RREG32(mmVGA_RENDER_CONTROL); 637 if (render) 638 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 639 else 640 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 641 WREG32(mmVGA_RENDER_CONTROL, tmp); 642 } 643 644 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 645 { 646 struct drm_device *dev = encoder->dev; 647 struct amdgpu_device *adev = dev->dev_private; 648 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 649 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 650 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 651 int bpc = 0; 652 u32 tmp = 0; 653 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 654 655 if (connector) { 656 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 657 bpc = amdgpu_connector_get_monitor_bpc(connector); 658 dither = amdgpu_connector->dither; 659 } 660 661 /* LVDS/eDP FMT is set up by atom */ 662 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 663 return; 664 665 /* not needed for analog */ 666 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 667 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 668 return; 669 670 if (bpc == 0) 671 return; 672 673 switch (bpc) { 674 case 6: 675 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 676 /* XXX sort out optimal dither settings */ 677 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 681 } else { 682 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 684 } 685 break; 686 case 8: 687 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 688 /* XXX sort out optimal dither settings */ 689 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 694 } else { 695 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 697 } 698 break; 699 case 10: 700 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 701 /* XXX sort out optimal dither settings */ 702 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 707 } else { 708 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 710 } 711 break; 712 default: 713 /* not needed */ 714 break; 715 } 716 717 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 718 } 719 720 721 /* display watermark setup */ 722 /** 723 * dce_v11_0_line_buffer_adjust - Set up the line buffer 724 * 725 * @adev: amdgpu_device pointer 726 * @amdgpu_crtc: the selected display controller 727 * @mode: the current display mode on the selected display 728 * controller 729 * 730 * Setup up the line buffer allocation for 731 * the selected display controller (CIK). 732 * Returns the line buffer size in pixels. 733 */ 734 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 735 struct amdgpu_crtc *amdgpu_crtc, 736 struct drm_display_mode *mode) 737 { 738 u32 tmp, buffer_alloc, i, mem_cfg; 739 u32 pipe_offset = amdgpu_crtc->crtc_id; 740 /* 741 * Line Buffer Setup 742 * There are 6 line buffers, one for each display controllers. 743 * There are 3 partitions per LB. Select the number of partitions 744 * to enable based on the display width. For display widths larger 745 * than 4096, you need use to use 2 display controllers and combine 746 * them using the stereo blender. 747 */ 748 if (amdgpu_crtc->base.enabled && mode) { 749 if (mode->crtc_hdisplay < 1920) { 750 mem_cfg = 1; 751 buffer_alloc = 2; 752 } else if (mode->crtc_hdisplay < 2560) { 753 mem_cfg = 2; 754 buffer_alloc = 2; 755 } else if (mode->crtc_hdisplay < 4096) { 756 mem_cfg = 0; 757 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 758 } else { 759 DRM_DEBUG_KMS("Mode too big for LB!\n"); 760 mem_cfg = 0; 761 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 762 } 763 } else { 764 mem_cfg = 1; 765 buffer_alloc = 0; 766 } 767 768 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 769 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 770 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 771 772 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 773 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 774 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 775 776 for (i = 0; i < adev->usec_timeout; i++) { 777 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 778 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 779 break; 780 udelay(1); 781 } 782 783 if (amdgpu_crtc->base.enabled && mode) { 784 switch (mem_cfg) { 785 case 0: 786 default: 787 return 4096 * 2; 788 case 1: 789 return 1920 * 2; 790 case 2: 791 return 2560 * 2; 792 } 793 } 794 795 /* controller not enabled, so no lb used */ 796 return 0; 797 } 798 799 /** 800 * cik_get_number_of_dram_channels - get the number of dram channels 801 * 802 * @adev: amdgpu_device pointer 803 * 804 * Look up the number of video ram channels (CIK). 805 * Used for display watermark bandwidth calculations 806 * Returns the number of dram channels 807 */ 808 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 809 { 810 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 811 812 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 813 case 0: 814 default: 815 return 1; 816 case 1: 817 return 2; 818 case 2: 819 return 4; 820 case 3: 821 return 8; 822 case 4: 823 return 3; 824 case 5: 825 return 6; 826 case 6: 827 return 10; 828 case 7: 829 return 12; 830 case 8: 831 return 16; 832 } 833 } 834 835 struct dce10_wm_params { 836 u32 dram_channels; /* number of dram channels */ 837 u32 yclk; /* bandwidth per dram data pin in kHz */ 838 u32 sclk; /* engine clock in kHz */ 839 u32 disp_clk; /* display clock in kHz */ 840 u32 src_width; /* viewport width */ 841 u32 active_time; /* active display time in ns */ 842 u32 blank_time; /* blank time in ns */ 843 bool interlaced; /* mode is interlaced */ 844 fixed20_12 vsc; /* vertical scale ratio */ 845 u32 num_heads; /* number of active crtcs */ 846 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 847 u32 lb_size; /* line buffer allocated to pipe */ 848 u32 vtaps; /* vertical scaler taps */ 849 }; 850 851 /** 852 * dce_v11_0_dram_bandwidth - get the dram bandwidth 853 * 854 * @wm: watermark calculation data 855 * 856 * Calculate the raw dram bandwidth (CIK). 857 * Used for display watermark bandwidth calculations 858 * Returns the dram bandwidth in MBytes/s 859 */ 860 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 861 { 862 /* Calculate raw DRAM Bandwidth */ 863 fixed20_12 dram_efficiency; /* 0.7 */ 864 fixed20_12 yclk, dram_channels, bandwidth; 865 fixed20_12 a; 866 867 a.full = dfixed_const(1000); 868 yclk.full = dfixed_const(wm->yclk); 869 yclk.full = dfixed_div(yclk, a); 870 dram_channels.full = dfixed_const(wm->dram_channels * 4); 871 a.full = dfixed_const(10); 872 dram_efficiency.full = dfixed_const(7); 873 dram_efficiency.full = dfixed_div(dram_efficiency, a); 874 bandwidth.full = dfixed_mul(dram_channels, yclk); 875 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 876 877 return dfixed_trunc(bandwidth); 878 } 879 880 /** 881 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 882 * 883 * @wm: watermark calculation data 884 * 885 * Calculate the dram bandwidth used for display (CIK). 886 * Used for display watermark bandwidth calculations 887 * Returns the dram bandwidth for display in MBytes/s 888 */ 889 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 890 { 891 /* Calculate DRAM Bandwidth and the part allocated to display. */ 892 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 893 fixed20_12 yclk, dram_channels, bandwidth; 894 fixed20_12 a; 895 896 a.full = dfixed_const(1000); 897 yclk.full = dfixed_const(wm->yclk); 898 yclk.full = dfixed_div(yclk, a); 899 dram_channels.full = dfixed_const(wm->dram_channels * 4); 900 a.full = dfixed_const(10); 901 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 902 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 903 bandwidth.full = dfixed_mul(dram_channels, yclk); 904 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 905 906 return dfixed_trunc(bandwidth); 907 } 908 909 /** 910 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 911 * 912 * @wm: watermark calculation data 913 * 914 * Calculate the data return bandwidth used for display (CIK). 915 * Used for display watermark bandwidth calculations 916 * Returns the data return bandwidth in MBytes/s 917 */ 918 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 919 { 920 /* Calculate the display Data return Bandwidth */ 921 fixed20_12 return_efficiency; /* 0.8 */ 922 fixed20_12 sclk, bandwidth; 923 fixed20_12 a; 924 925 a.full = dfixed_const(1000); 926 sclk.full = dfixed_const(wm->sclk); 927 sclk.full = dfixed_div(sclk, a); 928 a.full = dfixed_const(10); 929 return_efficiency.full = dfixed_const(8); 930 return_efficiency.full = dfixed_div(return_efficiency, a); 931 a.full = dfixed_const(32); 932 bandwidth.full = dfixed_mul(a, sclk); 933 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 934 935 return dfixed_trunc(bandwidth); 936 } 937 938 /** 939 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 940 * 941 * @wm: watermark calculation data 942 * 943 * Calculate the dmif bandwidth used for display (CIK). 944 * Used for display watermark bandwidth calculations 945 * Returns the dmif bandwidth in MBytes/s 946 */ 947 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 948 { 949 /* Calculate the DMIF Request Bandwidth */ 950 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 951 fixed20_12 disp_clk, bandwidth; 952 fixed20_12 a, b; 953 954 a.full = dfixed_const(1000); 955 disp_clk.full = dfixed_const(wm->disp_clk); 956 disp_clk.full = dfixed_div(disp_clk, a); 957 a.full = dfixed_const(32); 958 b.full = dfixed_mul(a, disp_clk); 959 960 a.full = dfixed_const(10); 961 disp_clk_request_efficiency.full = dfixed_const(8); 962 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 963 964 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 965 966 return dfixed_trunc(bandwidth); 967 } 968 969 /** 970 * dce_v11_0_available_bandwidth - get the min available bandwidth 971 * 972 * @wm: watermark calculation data 973 * 974 * Calculate the min available bandwidth used for display (CIK). 975 * Used for display watermark bandwidth calculations 976 * Returns the min available bandwidth in MBytes/s 977 */ 978 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 979 { 980 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 981 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 982 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 983 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 984 985 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 986 } 987 988 /** 989 * dce_v11_0_average_bandwidth - get the average available bandwidth 990 * 991 * @wm: watermark calculation data 992 * 993 * Calculate the average available bandwidth used for display (CIK). 994 * Used for display watermark bandwidth calculations 995 * Returns the average available bandwidth in MBytes/s 996 */ 997 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 998 { 999 /* Calculate the display mode Average Bandwidth 1000 * DisplayMode should contain the source and destination dimensions, 1001 * timing, etc. 1002 */ 1003 fixed20_12 bpp; 1004 fixed20_12 line_time; 1005 fixed20_12 src_width; 1006 fixed20_12 bandwidth; 1007 fixed20_12 a; 1008 1009 a.full = dfixed_const(1000); 1010 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1011 line_time.full = dfixed_div(line_time, a); 1012 bpp.full = dfixed_const(wm->bytes_per_pixel); 1013 src_width.full = dfixed_const(wm->src_width); 1014 bandwidth.full = dfixed_mul(src_width, bpp); 1015 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1016 bandwidth.full = dfixed_div(bandwidth, line_time); 1017 1018 return dfixed_trunc(bandwidth); 1019 } 1020 1021 /** 1022 * dce_v11_0_latency_watermark - get the latency watermark 1023 * 1024 * @wm: watermark calculation data 1025 * 1026 * Calculate the latency watermark (CIK). 1027 * Used for display watermark bandwidth calculations 1028 * Returns the latency watermark in ns 1029 */ 1030 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1031 { 1032 /* First calculate the latency in ns */ 1033 u32 mc_latency = 2000; /* 2000 ns. */ 1034 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1035 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1036 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1037 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1038 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1039 (wm->num_heads * cursor_line_pair_return_time); 1040 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1041 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1042 u32 tmp, dmif_size = 12288; 1043 fixed20_12 a, b, c; 1044 1045 if (wm->num_heads == 0) 1046 return 0; 1047 1048 a.full = dfixed_const(2); 1049 b.full = dfixed_const(1); 1050 if ((wm->vsc.full > a.full) || 1051 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1052 (wm->vtaps >= 5) || 1053 ((wm->vsc.full >= a.full) && wm->interlaced)) 1054 max_src_lines_per_dst_line = 4; 1055 else 1056 max_src_lines_per_dst_line = 2; 1057 1058 a.full = dfixed_const(available_bandwidth); 1059 b.full = dfixed_const(wm->num_heads); 1060 a.full = dfixed_div(a, b); 1061 1062 b.full = dfixed_const(mc_latency + 512); 1063 c.full = dfixed_const(wm->disp_clk); 1064 b.full = dfixed_div(b, c); 1065 1066 c.full = dfixed_const(dmif_size); 1067 b.full = dfixed_div(c, b); 1068 1069 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1070 1071 b.full = dfixed_const(1000); 1072 c.full = dfixed_const(wm->disp_clk); 1073 b.full = dfixed_div(c, b); 1074 c.full = dfixed_const(wm->bytes_per_pixel); 1075 b.full = dfixed_mul(b, c); 1076 1077 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1078 1079 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1080 b.full = dfixed_const(1000); 1081 c.full = dfixed_const(lb_fill_bw); 1082 b.full = dfixed_div(c, b); 1083 a.full = dfixed_div(a, b); 1084 line_fill_time = dfixed_trunc(a); 1085 1086 if (line_fill_time < wm->active_time) 1087 return latency; 1088 else 1089 return latency + (line_fill_time - wm->active_time); 1090 1091 } 1092 1093 /** 1094 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1095 * average and available dram bandwidth 1096 * 1097 * @wm: watermark calculation data 1098 * 1099 * Check if the display average bandwidth fits in the display 1100 * dram bandwidth (CIK). 1101 * Used for display watermark bandwidth calculations 1102 * Returns true if the display fits, false if not. 1103 */ 1104 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1105 { 1106 if (dce_v11_0_average_bandwidth(wm) <= 1107 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1108 return true; 1109 else 1110 return false; 1111 } 1112 1113 /** 1114 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1115 * average and available bandwidth 1116 * 1117 * @wm: watermark calculation data 1118 * 1119 * Check if the display average bandwidth fits in the display 1120 * available bandwidth (CIK). 1121 * Used for display watermark bandwidth calculations 1122 * Returns true if the display fits, false if not. 1123 */ 1124 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1125 { 1126 if (dce_v11_0_average_bandwidth(wm) <= 1127 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1128 return true; 1129 else 1130 return false; 1131 } 1132 1133 /** 1134 * dce_v11_0_check_latency_hiding - check latency hiding 1135 * 1136 * @wm: watermark calculation data 1137 * 1138 * Check latency hiding (CIK). 1139 * Used for display watermark bandwidth calculations 1140 * Returns true if the display fits, false if not. 1141 */ 1142 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1143 { 1144 u32 lb_partitions = wm->lb_size / wm->src_width; 1145 u32 line_time = wm->active_time + wm->blank_time; 1146 u32 latency_tolerant_lines; 1147 u32 latency_hiding; 1148 fixed20_12 a; 1149 1150 a.full = dfixed_const(1); 1151 if (wm->vsc.full > a.full) 1152 latency_tolerant_lines = 1; 1153 else { 1154 if (lb_partitions <= (wm->vtaps + 1)) 1155 latency_tolerant_lines = 1; 1156 else 1157 latency_tolerant_lines = 2; 1158 } 1159 1160 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1161 1162 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1163 return true; 1164 else 1165 return false; 1166 } 1167 1168 /** 1169 * dce_v11_0_program_watermarks - program display watermarks 1170 * 1171 * @adev: amdgpu_device pointer 1172 * @amdgpu_crtc: the selected display controller 1173 * @lb_size: line buffer size 1174 * @num_heads: number of display controllers in use 1175 * 1176 * Calculate and program the display watermarks for the 1177 * selected display controller (CIK). 1178 */ 1179 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1180 struct amdgpu_crtc *amdgpu_crtc, 1181 u32 lb_size, u32 num_heads) 1182 { 1183 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1184 struct dce10_wm_params wm_low, wm_high; 1185 u32 pixel_period; 1186 u32 line_time = 0; 1187 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1188 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1189 1190 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1191 pixel_period = 1000000 / (u32)mode->clock; 1192 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1193 1194 /* watermark for high clocks */ 1195 if (adev->pm.dpm_enabled) { 1196 wm_high.yclk = 1197 amdgpu_dpm_get_mclk(adev, false) * 10; 1198 wm_high.sclk = 1199 amdgpu_dpm_get_sclk(adev, false) * 10; 1200 } else { 1201 wm_high.yclk = adev->pm.current_mclk * 10; 1202 wm_high.sclk = adev->pm.current_sclk * 10; 1203 } 1204 1205 wm_high.disp_clk = mode->clock; 1206 wm_high.src_width = mode->crtc_hdisplay; 1207 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1208 wm_high.blank_time = line_time - wm_high.active_time; 1209 wm_high.interlaced = false; 1210 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1211 wm_high.interlaced = true; 1212 wm_high.vsc = amdgpu_crtc->vsc; 1213 wm_high.vtaps = 1; 1214 if (amdgpu_crtc->rmx_type != RMX_OFF) 1215 wm_high.vtaps = 2; 1216 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1217 wm_high.lb_size = lb_size; 1218 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1219 wm_high.num_heads = num_heads; 1220 1221 /* set for high clocks */ 1222 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1223 1224 /* possibly force display priority to high */ 1225 /* should really do this at mode validation time... */ 1226 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1227 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1228 !dce_v11_0_check_latency_hiding(&wm_high) || 1229 (adev->mode_info.disp_priority == 2)) { 1230 DRM_DEBUG_KMS("force priority to high\n"); 1231 } 1232 1233 /* watermark for low clocks */ 1234 if (adev->pm.dpm_enabled) { 1235 wm_low.yclk = 1236 amdgpu_dpm_get_mclk(adev, true) * 10; 1237 wm_low.sclk = 1238 amdgpu_dpm_get_sclk(adev, true) * 10; 1239 } else { 1240 wm_low.yclk = adev->pm.current_mclk * 10; 1241 wm_low.sclk = adev->pm.current_sclk * 10; 1242 } 1243 1244 wm_low.disp_clk = mode->clock; 1245 wm_low.src_width = mode->crtc_hdisplay; 1246 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1247 wm_low.blank_time = line_time - wm_low.active_time; 1248 wm_low.interlaced = false; 1249 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1250 wm_low.interlaced = true; 1251 wm_low.vsc = amdgpu_crtc->vsc; 1252 wm_low.vtaps = 1; 1253 if (amdgpu_crtc->rmx_type != RMX_OFF) 1254 wm_low.vtaps = 2; 1255 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1256 wm_low.lb_size = lb_size; 1257 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1258 wm_low.num_heads = num_heads; 1259 1260 /* set for low clocks */ 1261 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1262 1263 /* possibly force display priority to high */ 1264 /* should really do this at mode validation time... */ 1265 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1266 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1267 !dce_v11_0_check_latency_hiding(&wm_low) || 1268 (adev->mode_info.disp_priority == 2)) { 1269 DRM_DEBUG_KMS("force priority to high\n"); 1270 } 1271 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1272 } 1273 1274 /* select wm A */ 1275 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1276 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1277 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1278 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1279 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1280 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1281 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1282 /* select wm B */ 1283 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1284 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1285 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1286 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1287 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1288 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1289 /* restore original selection */ 1290 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1291 1292 /* save values for DPM */ 1293 amdgpu_crtc->line_time = line_time; 1294 amdgpu_crtc->wm_high = latency_watermark_a; 1295 amdgpu_crtc->wm_low = latency_watermark_b; 1296 /* Save number of lines the linebuffer leads before the scanout */ 1297 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1298 } 1299 1300 /** 1301 * dce_v11_0_bandwidth_update - program display watermarks 1302 * 1303 * @adev: amdgpu_device pointer 1304 * 1305 * Calculate and program the display watermarks and line 1306 * buffer allocation (CIK). 1307 */ 1308 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1309 { 1310 struct drm_display_mode *mode = NULL; 1311 u32 num_heads = 0, lb_size; 1312 int i; 1313 1314 amdgpu_update_display_priority(adev); 1315 1316 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1317 if (adev->mode_info.crtcs[i]->base.enabled) 1318 num_heads++; 1319 } 1320 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1321 mode = &adev->mode_info.crtcs[i]->base.mode; 1322 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1323 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1324 lb_size, num_heads); 1325 } 1326 } 1327 1328 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1329 { 1330 int i; 1331 u32 offset, tmp; 1332 1333 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1334 offset = adev->mode_info.audio.pin[i].offset; 1335 tmp = RREG32_AUDIO_ENDPT(offset, 1336 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1337 if (((tmp & 1338 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1340 adev->mode_info.audio.pin[i].connected = false; 1341 else 1342 adev->mode_info.audio.pin[i].connected = true; 1343 } 1344 } 1345 1346 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1347 { 1348 int i; 1349 1350 dce_v11_0_audio_get_connected_pins(adev); 1351 1352 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1353 if (adev->mode_info.audio.pin[i].connected) 1354 return &adev->mode_info.audio.pin[i]; 1355 } 1356 DRM_ERROR("No connected audio pins found!\n"); 1357 return NULL; 1358 } 1359 1360 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1361 { 1362 struct amdgpu_device *adev = encoder->dev->dev_private; 1363 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1364 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1365 u32 tmp; 1366 1367 if (!dig || !dig->afmt || !dig->afmt->pin) 1368 return; 1369 1370 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1371 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1372 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1373 } 1374 1375 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1376 struct drm_display_mode *mode) 1377 { 1378 struct amdgpu_device *adev = encoder->dev->dev_private; 1379 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1380 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1381 struct drm_connector *connector; 1382 struct amdgpu_connector *amdgpu_connector = NULL; 1383 u32 tmp; 1384 int interlace = 0; 1385 1386 if (!dig || !dig->afmt || !dig->afmt->pin) 1387 return; 1388 1389 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1390 if (connector->encoder == encoder) { 1391 amdgpu_connector = to_amdgpu_connector(connector); 1392 break; 1393 } 1394 } 1395 1396 if (!amdgpu_connector) { 1397 DRM_ERROR("Couldn't find encoder's connector\n"); 1398 return; 1399 } 1400 1401 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1402 interlace = 1; 1403 if (connector->latency_present[interlace]) { 1404 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1405 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1406 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1407 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1408 } else { 1409 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1410 VIDEO_LIPSYNC, 0); 1411 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1412 AUDIO_LIPSYNC, 0); 1413 } 1414 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1415 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1416 } 1417 1418 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1419 { 1420 struct amdgpu_device *adev = encoder->dev->dev_private; 1421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1422 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1423 struct drm_connector *connector; 1424 struct amdgpu_connector *amdgpu_connector = NULL; 1425 u32 tmp; 1426 u8 *sadb = NULL; 1427 int sad_count; 1428 1429 if (!dig || !dig->afmt || !dig->afmt->pin) 1430 return; 1431 1432 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1433 if (connector->encoder == encoder) { 1434 amdgpu_connector = to_amdgpu_connector(connector); 1435 break; 1436 } 1437 } 1438 1439 if (!amdgpu_connector) { 1440 DRM_ERROR("Couldn't find encoder's connector\n"); 1441 return; 1442 } 1443 1444 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1445 if (sad_count < 0) { 1446 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1447 sad_count = 0; 1448 } 1449 1450 /* program the speaker allocation */ 1451 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1452 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1453 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1454 DP_CONNECTION, 0); 1455 /* set HDMI mode */ 1456 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1457 HDMI_CONNECTION, 1); 1458 if (sad_count) 1459 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1460 SPEAKER_ALLOCATION, sadb[0]); 1461 else 1462 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1463 SPEAKER_ALLOCATION, 5); /* stereo */ 1464 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1465 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1466 1467 kfree(sadb); 1468 } 1469 1470 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1471 { 1472 struct amdgpu_device *adev = encoder->dev->dev_private; 1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1475 struct drm_connector *connector; 1476 struct amdgpu_connector *amdgpu_connector = NULL; 1477 struct cea_sad *sads; 1478 int i, sad_count; 1479 1480 static const u16 eld_reg_to_type[][2] = { 1481 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1493 }; 1494 1495 if (!dig || !dig->afmt || !dig->afmt->pin) 1496 return; 1497 1498 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1499 if (connector->encoder == encoder) { 1500 amdgpu_connector = to_amdgpu_connector(connector); 1501 break; 1502 } 1503 } 1504 1505 if (!amdgpu_connector) { 1506 DRM_ERROR("Couldn't find encoder's connector\n"); 1507 return; 1508 } 1509 1510 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1511 if (sad_count <= 0) { 1512 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1513 return; 1514 } 1515 BUG_ON(!sads); 1516 1517 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1518 u32 tmp = 0; 1519 u8 stereo_freqs = 0; 1520 int max_channels = -1; 1521 int j; 1522 1523 for (j = 0; j < sad_count; j++) { 1524 struct cea_sad *sad = &sads[j]; 1525 1526 if (sad->format == eld_reg_to_type[i][1]) { 1527 if (sad->channels > max_channels) { 1528 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1529 MAX_CHANNELS, sad->channels); 1530 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1531 DESCRIPTOR_BYTE_2, sad->byte2); 1532 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1533 SUPPORTED_FREQUENCIES, sad->freq); 1534 max_channels = sad->channels; 1535 } 1536 1537 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1538 stereo_freqs |= sad->freq; 1539 else 1540 break; 1541 } 1542 } 1543 1544 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1545 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1546 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1547 } 1548 1549 kfree(sads); 1550 } 1551 1552 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1553 struct amdgpu_audio_pin *pin, 1554 bool enable) 1555 { 1556 if (!pin) 1557 return; 1558 1559 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1560 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1561 } 1562 1563 static const u32 pin_offsets[] = 1564 { 1565 AUD0_REGISTER_OFFSET, 1566 AUD1_REGISTER_OFFSET, 1567 AUD2_REGISTER_OFFSET, 1568 AUD3_REGISTER_OFFSET, 1569 AUD4_REGISTER_OFFSET, 1570 AUD5_REGISTER_OFFSET, 1571 AUD6_REGISTER_OFFSET, 1572 }; 1573 1574 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1575 { 1576 int i; 1577 1578 if (!amdgpu_audio) 1579 return 0; 1580 1581 adev->mode_info.audio.enabled = true; 1582 1583 adev->mode_info.audio.num_pins = 7; 1584 1585 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1586 adev->mode_info.audio.pin[i].channels = -1; 1587 adev->mode_info.audio.pin[i].rate = -1; 1588 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1589 adev->mode_info.audio.pin[i].status_bits = 0; 1590 adev->mode_info.audio.pin[i].category_code = 0; 1591 adev->mode_info.audio.pin[i].connected = false; 1592 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1593 adev->mode_info.audio.pin[i].id = i; 1594 /* disable audio. it will be set up later */ 1595 /* XXX remove once we switch to ip funcs */ 1596 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1597 } 1598 1599 return 0; 1600 } 1601 1602 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1603 { 1604 int i; 1605 1606 if (!amdgpu_audio) 1607 return; 1608 1609 if (!adev->mode_info.audio.enabled) 1610 return; 1611 1612 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1613 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1614 1615 adev->mode_info.audio.enabled = false; 1616 } 1617 1618 /* 1619 * update the N and CTS parameters for a given pixel clock rate 1620 */ 1621 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1622 { 1623 struct drm_device *dev = encoder->dev; 1624 struct amdgpu_device *adev = dev->dev_private; 1625 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1626 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1627 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1628 u32 tmp; 1629 1630 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1631 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1632 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1633 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1634 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1635 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1636 1637 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1638 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1639 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1640 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1641 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1642 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1643 1644 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1645 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1646 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1647 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1648 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1649 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1650 1651 } 1652 1653 /* 1654 * build a HDMI Video Info Frame 1655 */ 1656 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1657 void *buffer, size_t size) 1658 { 1659 struct drm_device *dev = encoder->dev; 1660 struct amdgpu_device *adev = dev->dev_private; 1661 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1662 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1663 uint8_t *frame = buffer + 3; 1664 uint8_t *header = buffer; 1665 1666 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1667 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1668 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1669 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1670 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1671 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1672 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1673 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1674 } 1675 1676 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1677 { 1678 struct drm_device *dev = encoder->dev; 1679 struct amdgpu_device *adev = dev->dev_private; 1680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1681 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1683 u32 dto_phase = 24 * 1000; 1684 u32 dto_modulo = clock; 1685 u32 tmp; 1686 1687 if (!dig || !dig->afmt) 1688 return; 1689 1690 /* XXX two dtos; generally use dto0 for hdmi */ 1691 /* Express [24MHz / target pixel clock] as an exact rational 1692 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1693 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1694 */ 1695 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1696 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1697 amdgpu_crtc->crtc_id); 1698 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1699 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1700 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1701 } 1702 1703 /* 1704 * update the info frames with the data from the current display mode 1705 */ 1706 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1707 struct drm_display_mode *mode) 1708 { 1709 struct drm_device *dev = encoder->dev; 1710 struct amdgpu_device *adev = dev->dev_private; 1711 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1712 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1713 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1714 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1715 struct hdmi_avi_infoframe frame; 1716 ssize_t err; 1717 u32 tmp; 1718 int bpc = 8; 1719 1720 if (!dig || !dig->afmt) 1721 return; 1722 1723 /* Silent, r600_hdmi_enable will raise WARN for us */ 1724 if (!dig->afmt->enabled) 1725 return; 1726 1727 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1728 if (encoder->crtc) { 1729 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1730 bpc = amdgpu_crtc->bpc; 1731 } 1732 1733 /* disable audio prior to setting up hw */ 1734 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1735 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1736 1737 dce_v11_0_audio_set_dto(encoder, mode->clock); 1738 1739 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1740 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1741 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1742 1743 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1744 1745 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1746 switch (bpc) { 1747 case 0: 1748 case 6: 1749 case 8: 1750 case 16: 1751 default: 1752 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1753 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1754 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1755 connector->name, bpc); 1756 break; 1757 case 10: 1758 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1759 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1760 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1761 connector->name); 1762 break; 1763 case 12: 1764 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1765 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1766 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1767 connector->name); 1768 break; 1769 } 1770 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1771 1772 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1773 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1774 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1775 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1776 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1777 1778 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1779 /* enable audio info frames (frames won't be set until audio is enabled) */ 1780 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1781 /* required for audio info values to be updated */ 1782 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1783 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1784 1785 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1786 /* required for audio info values to be updated */ 1787 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1788 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1789 1790 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1791 /* anything other than 0 */ 1792 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1793 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1794 1795 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1796 1797 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1798 /* set the default audio delay */ 1799 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1800 /* should be suffient for all audio modes and small enough for all hblanks */ 1801 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1802 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1803 1804 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1805 /* allow 60958 channel status fields to be updated */ 1806 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1807 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1808 1809 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1810 if (bpc > 8) 1811 /* clear SW CTS value */ 1812 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1813 else 1814 /* select SW CTS value */ 1815 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1816 /* allow hw to sent ACR packets when required */ 1817 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1818 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1819 1820 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1821 1822 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1823 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1824 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1825 1826 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1827 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1828 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1829 1830 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1831 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1832 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1833 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1834 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1835 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1836 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1837 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1838 1839 dce_v11_0_audio_write_speaker_allocation(encoder); 1840 1841 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1842 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1843 1844 dce_v11_0_afmt_audio_select_pin(encoder); 1845 dce_v11_0_audio_write_sad_regs(encoder); 1846 dce_v11_0_audio_write_latency_fields(encoder, mode); 1847 1848 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1849 if (err < 0) { 1850 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1851 return; 1852 } 1853 1854 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1855 if (err < 0) { 1856 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1857 return; 1858 } 1859 1860 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1861 1862 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1863 /* enable AVI info frames */ 1864 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1865 /* required for audio info values to be updated */ 1866 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1867 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1868 1869 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1870 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1871 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1872 1873 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1874 /* send audio packets */ 1875 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1876 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1877 1878 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1879 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1880 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1881 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1882 1883 /* enable audio after to setting up hw */ 1884 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1885 } 1886 1887 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1888 { 1889 struct drm_device *dev = encoder->dev; 1890 struct amdgpu_device *adev = dev->dev_private; 1891 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1892 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1893 1894 if (!dig || !dig->afmt) 1895 return; 1896 1897 /* Silent, r600_hdmi_enable will raise WARN for us */ 1898 if (enable && dig->afmt->enabled) 1899 return; 1900 if (!enable && !dig->afmt->enabled) 1901 return; 1902 1903 if (!enable && dig->afmt->pin) { 1904 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1905 dig->afmt->pin = NULL; 1906 } 1907 1908 dig->afmt->enabled = enable; 1909 1910 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1911 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1912 } 1913 1914 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1915 { 1916 int i; 1917 1918 for (i = 0; i < adev->mode_info.num_dig; i++) 1919 adev->mode_info.afmt[i] = NULL; 1920 1921 /* DCE11 has audio blocks tied to DIG encoders */ 1922 for (i = 0; i < adev->mode_info.num_dig; i++) { 1923 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1924 if (adev->mode_info.afmt[i]) { 1925 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1926 adev->mode_info.afmt[i]->id = i; 1927 } else { 1928 int j; 1929 for (j = 0; j < i; j++) { 1930 kfree(adev->mode_info.afmt[j]); 1931 adev->mode_info.afmt[j] = NULL; 1932 } 1933 return -ENOMEM; 1934 } 1935 } 1936 return 0; 1937 } 1938 1939 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1940 { 1941 int i; 1942 1943 for (i = 0; i < adev->mode_info.num_dig; i++) { 1944 kfree(adev->mode_info.afmt[i]); 1945 adev->mode_info.afmt[i] = NULL; 1946 } 1947 } 1948 1949 static const u32 vga_control_regs[6] = 1950 { 1951 mmD1VGA_CONTROL, 1952 mmD2VGA_CONTROL, 1953 mmD3VGA_CONTROL, 1954 mmD4VGA_CONTROL, 1955 mmD5VGA_CONTROL, 1956 mmD6VGA_CONTROL, 1957 }; 1958 1959 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1960 { 1961 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1962 struct drm_device *dev = crtc->dev; 1963 struct amdgpu_device *adev = dev->dev_private; 1964 u32 vga_control; 1965 1966 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1967 if (enable) 1968 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1969 else 1970 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1971 } 1972 1973 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1974 { 1975 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1976 struct drm_device *dev = crtc->dev; 1977 struct amdgpu_device *adev = dev->dev_private; 1978 1979 if (enable) 1980 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1981 else 1982 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1983 } 1984 1985 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1986 struct drm_framebuffer *fb, 1987 int x, int y, int atomic) 1988 { 1989 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1990 struct drm_device *dev = crtc->dev; 1991 struct amdgpu_device *adev = dev->dev_private; 1992 struct amdgpu_framebuffer *amdgpu_fb; 1993 struct drm_framebuffer *target_fb; 1994 struct drm_gem_object *obj; 1995 struct amdgpu_bo *rbo; 1996 uint64_t fb_location, tiling_flags; 1997 uint32_t fb_format, fb_pitch_pixels; 1998 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1999 u32 pipe_config; 2000 u32 tmp, viewport_w, viewport_h; 2001 int r; 2002 bool bypass_lut = false; 2003 2004 /* no fb bound */ 2005 if (!atomic && !crtc->primary->fb) { 2006 DRM_DEBUG_KMS("No FB bound\n"); 2007 return 0; 2008 } 2009 2010 if (atomic) { 2011 amdgpu_fb = to_amdgpu_framebuffer(fb); 2012 target_fb = fb; 2013 } else { 2014 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2015 target_fb = crtc->primary->fb; 2016 } 2017 2018 /* If atomic, assume fb object is pinned & idle & fenced and 2019 * just update base pointers 2020 */ 2021 obj = amdgpu_fb->obj; 2022 rbo = gem_to_amdgpu_bo(obj); 2023 r = amdgpu_bo_reserve(rbo, false); 2024 if (unlikely(r != 0)) 2025 return r; 2026 2027 if (atomic) { 2028 fb_location = amdgpu_bo_gpu_offset(rbo); 2029 } else { 2030 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2031 if (unlikely(r != 0)) { 2032 amdgpu_bo_unreserve(rbo); 2033 return -EINVAL; 2034 } 2035 } 2036 2037 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2038 amdgpu_bo_unreserve(rbo); 2039 2040 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2041 2042 switch (target_fb->pixel_format) { 2043 case DRM_FORMAT_C8: 2044 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2046 break; 2047 case DRM_FORMAT_XRGB4444: 2048 case DRM_FORMAT_ARGB4444: 2049 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2050 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2051 #ifdef __BIG_ENDIAN 2052 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2053 ENDIAN_8IN16); 2054 #endif 2055 break; 2056 case DRM_FORMAT_XRGB1555: 2057 case DRM_FORMAT_ARGB1555: 2058 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2059 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2060 #ifdef __BIG_ENDIAN 2061 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2062 ENDIAN_8IN16); 2063 #endif 2064 break; 2065 case DRM_FORMAT_BGRX5551: 2066 case DRM_FORMAT_BGRA5551: 2067 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2068 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2069 #ifdef __BIG_ENDIAN 2070 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2071 ENDIAN_8IN16); 2072 #endif 2073 break; 2074 case DRM_FORMAT_RGB565: 2075 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2076 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2077 #ifdef __BIG_ENDIAN 2078 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2079 ENDIAN_8IN16); 2080 #endif 2081 break; 2082 case DRM_FORMAT_XRGB8888: 2083 case DRM_FORMAT_ARGB8888: 2084 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2085 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2086 #ifdef __BIG_ENDIAN 2087 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2088 ENDIAN_8IN32); 2089 #endif 2090 break; 2091 case DRM_FORMAT_XRGB2101010: 2092 case DRM_FORMAT_ARGB2101010: 2093 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2094 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2095 #ifdef __BIG_ENDIAN 2096 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2097 ENDIAN_8IN32); 2098 #endif 2099 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2100 bypass_lut = true; 2101 break; 2102 case DRM_FORMAT_BGRX1010102: 2103 case DRM_FORMAT_BGRA1010102: 2104 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2105 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2106 #ifdef __BIG_ENDIAN 2107 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2108 ENDIAN_8IN32); 2109 #endif 2110 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2111 bypass_lut = true; 2112 break; 2113 default: 2114 DRM_ERROR("Unsupported screen format %s\n", 2115 drm_get_format_name(target_fb->pixel_format)); 2116 return -EINVAL; 2117 } 2118 2119 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2120 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2121 2122 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2123 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2124 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2125 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2126 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2127 2128 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2129 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2130 ARRAY_2D_TILED_THIN1); 2131 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2132 tile_split); 2133 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2134 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2135 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2136 mtaspect); 2137 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2138 ADDR_SURF_MICRO_TILING_DISPLAY); 2139 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2140 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2141 ARRAY_1D_TILED_THIN1); 2142 } 2143 2144 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2145 pipe_config); 2146 2147 dce_v11_0_vga_enable(crtc, false); 2148 2149 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2150 upper_32_bits(fb_location)); 2151 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2152 upper_32_bits(fb_location)); 2153 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2154 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2155 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2156 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2157 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2158 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2159 2160 /* 2161 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2162 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2163 * retain the full precision throughout the pipeline. 2164 */ 2165 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2166 if (bypass_lut) 2167 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2168 else 2169 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2170 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2171 2172 if (bypass_lut) 2173 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2174 2175 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2176 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2177 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2178 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2179 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2180 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2181 2182 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2183 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2184 2185 dce_v11_0_grph_enable(crtc, true); 2186 2187 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2188 target_fb->height); 2189 2190 x &= ~3; 2191 y &= ~1; 2192 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2193 (x << 16) | y); 2194 viewport_w = crtc->mode.hdisplay; 2195 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2196 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2197 (viewport_w << 16) | viewport_h); 2198 2199 /* pageflip setup */ 2200 /* make sure flip is at vb rather than hb */ 2201 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2202 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2203 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2204 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2205 2206 /* set pageflip to happen only at start of vblank interval (front porch) */ 2207 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2208 2209 if (!atomic && fb && fb != crtc->primary->fb) { 2210 amdgpu_fb = to_amdgpu_framebuffer(fb); 2211 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2212 r = amdgpu_bo_reserve(rbo, false); 2213 if (unlikely(r != 0)) 2214 return r; 2215 amdgpu_bo_unpin(rbo); 2216 amdgpu_bo_unreserve(rbo); 2217 } 2218 2219 /* Bytes per pixel may have changed */ 2220 dce_v11_0_bandwidth_update(adev); 2221 2222 return 0; 2223 } 2224 2225 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2226 struct drm_display_mode *mode) 2227 { 2228 struct drm_device *dev = crtc->dev; 2229 struct amdgpu_device *adev = dev->dev_private; 2230 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2231 u32 tmp; 2232 2233 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2234 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2235 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2236 else 2237 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2238 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2239 } 2240 2241 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2242 { 2243 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2244 struct drm_device *dev = crtc->dev; 2245 struct amdgpu_device *adev = dev->dev_private; 2246 int i; 2247 u32 tmp; 2248 2249 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2250 2251 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2252 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2253 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2254 2255 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2256 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2257 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2258 2259 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2260 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2261 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2262 2263 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2264 2265 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2266 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2267 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2268 2269 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2270 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2271 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2272 2273 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2274 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2275 2276 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2277 for (i = 0; i < 256; i++) { 2278 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2279 (amdgpu_crtc->lut_r[i] << 20) | 2280 (amdgpu_crtc->lut_g[i] << 10) | 2281 (amdgpu_crtc->lut_b[i] << 0)); 2282 } 2283 2284 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2285 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2286 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2287 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2288 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2289 2290 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2291 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2292 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2293 2294 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2295 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2296 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2297 2298 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2299 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2300 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2301 2302 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2303 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2304 /* XXX this only needs to be programmed once per crtc at startup, 2305 * not sure where the best place for it is 2306 */ 2307 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2308 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2309 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2310 } 2311 2312 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2313 { 2314 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2315 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2316 2317 switch (amdgpu_encoder->encoder_id) { 2318 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2319 if (dig->linkb) 2320 return 1; 2321 else 2322 return 0; 2323 break; 2324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2325 if (dig->linkb) 2326 return 3; 2327 else 2328 return 2; 2329 break; 2330 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2331 if (dig->linkb) 2332 return 5; 2333 else 2334 return 4; 2335 break; 2336 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2337 return 6; 2338 break; 2339 default: 2340 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2341 return 0; 2342 } 2343 } 2344 2345 /** 2346 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2347 * 2348 * @crtc: drm crtc 2349 * 2350 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2351 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2352 * monitors a dedicated PPLL must be used. If a particular board has 2353 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2354 * as there is no need to program the PLL itself. If we are not able to 2355 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2356 * avoid messing up an existing monitor. 2357 * 2358 * Asic specific PLL information 2359 * 2360 * DCE 10.x 2361 * Tonga 2362 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2363 * CI 2364 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2365 * 2366 */ 2367 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2368 { 2369 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2370 struct drm_device *dev = crtc->dev; 2371 struct amdgpu_device *adev = dev->dev_private; 2372 u32 pll_in_use; 2373 int pll; 2374 2375 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2376 if (adev->clock.dp_extclk) 2377 /* skip PPLL programming if using ext clock */ 2378 return ATOM_PPLL_INVALID; 2379 else { 2380 /* use the same PPLL for all DP monitors */ 2381 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2382 if (pll != ATOM_PPLL_INVALID) 2383 return pll; 2384 } 2385 } else { 2386 /* use the same PPLL for all monitors with the same clock */ 2387 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2388 if (pll != ATOM_PPLL_INVALID) 2389 return pll; 2390 } 2391 2392 /* XXX need to determine what plls are available on each DCE11 part */ 2393 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2394 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2395 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2396 return ATOM_PPLL1; 2397 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2398 return ATOM_PPLL0; 2399 DRM_ERROR("unable to allocate a PPLL\n"); 2400 return ATOM_PPLL_INVALID; 2401 } else { 2402 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2403 return ATOM_PPLL2; 2404 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2405 return ATOM_PPLL1; 2406 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2407 return ATOM_PPLL0; 2408 DRM_ERROR("unable to allocate a PPLL\n"); 2409 return ATOM_PPLL_INVALID; 2410 } 2411 return ATOM_PPLL_INVALID; 2412 } 2413 2414 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2415 { 2416 struct amdgpu_device *adev = crtc->dev->dev_private; 2417 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2418 uint32_t cur_lock; 2419 2420 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2421 if (lock) 2422 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2423 else 2424 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2425 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2426 } 2427 2428 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2429 { 2430 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2431 struct amdgpu_device *adev = crtc->dev->dev_private; 2432 u32 tmp; 2433 2434 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2435 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2436 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2437 } 2438 2439 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2440 { 2441 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2442 struct amdgpu_device *adev = crtc->dev->dev_private; 2443 u32 tmp; 2444 2445 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2446 upper_32_bits(amdgpu_crtc->cursor_addr)); 2447 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2448 lower_32_bits(amdgpu_crtc->cursor_addr)); 2449 2450 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2451 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2452 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2453 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2454 } 2455 2456 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2457 int x, int y) 2458 { 2459 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2460 struct amdgpu_device *adev = crtc->dev->dev_private; 2461 int xorigin = 0, yorigin = 0; 2462 2463 /* avivo cursor are offset into the total surface */ 2464 x += crtc->x; 2465 y += crtc->y; 2466 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2467 2468 if (x < 0) { 2469 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2470 x = 0; 2471 } 2472 if (y < 0) { 2473 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2474 y = 0; 2475 } 2476 2477 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2478 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2479 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2480 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2481 2482 amdgpu_crtc->cursor_x = x; 2483 amdgpu_crtc->cursor_y = y; 2484 2485 return 0; 2486 } 2487 2488 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2489 int x, int y) 2490 { 2491 int ret; 2492 2493 dce_v11_0_lock_cursor(crtc, true); 2494 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2495 dce_v11_0_lock_cursor(crtc, false); 2496 2497 return ret; 2498 } 2499 2500 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2501 struct drm_file *file_priv, 2502 uint32_t handle, 2503 uint32_t width, 2504 uint32_t height, 2505 int32_t hot_x, 2506 int32_t hot_y) 2507 { 2508 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2509 struct drm_gem_object *obj; 2510 struct amdgpu_bo *aobj; 2511 int ret; 2512 2513 if (!handle) { 2514 /* turn off cursor */ 2515 dce_v11_0_hide_cursor(crtc); 2516 obj = NULL; 2517 goto unpin; 2518 } 2519 2520 if ((width > amdgpu_crtc->max_cursor_width) || 2521 (height > amdgpu_crtc->max_cursor_height)) { 2522 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2523 return -EINVAL; 2524 } 2525 2526 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2527 if (!obj) { 2528 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2529 return -ENOENT; 2530 } 2531 2532 aobj = gem_to_amdgpu_bo(obj); 2533 ret = amdgpu_bo_reserve(aobj, false); 2534 if (ret != 0) { 2535 drm_gem_object_unreference_unlocked(obj); 2536 return ret; 2537 } 2538 2539 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2540 amdgpu_bo_unreserve(aobj); 2541 if (ret) { 2542 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2543 drm_gem_object_unreference_unlocked(obj); 2544 return ret; 2545 } 2546 2547 amdgpu_crtc->cursor_width = width; 2548 amdgpu_crtc->cursor_height = height; 2549 2550 dce_v11_0_lock_cursor(crtc, true); 2551 2552 if (hot_x != amdgpu_crtc->cursor_hot_x || 2553 hot_y != amdgpu_crtc->cursor_hot_y) { 2554 int x, y; 2555 2556 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2557 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2558 2559 dce_v11_0_cursor_move_locked(crtc, x, y); 2560 2561 amdgpu_crtc->cursor_hot_x = hot_x; 2562 amdgpu_crtc->cursor_hot_y = hot_y; 2563 } 2564 2565 dce_v11_0_show_cursor(crtc); 2566 dce_v11_0_lock_cursor(crtc, false); 2567 2568 unpin: 2569 if (amdgpu_crtc->cursor_bo) { 2570 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2571 ret = amdgpu_bo_reserve(aobj, false); 2572 if (likely(ret == 0)) { 2573 amdgpu_bo_unpin(aobj); 2574 amdgpu_bo_unreserve(aobj); 2575 } 2576 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2577 } 2578 2579 amdgpu_crtc->cursor_bo = obj; 2580 return 0; 2581 } 2582 2583 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2584 { 2585 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2586 2587 if (amdgpu_crtc->cursor_bo) { 2588 dce_v11_0_lock_cursor(crtc, true); 2589 2590 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2591 amdgpu_crtc->cursor_y); 2592 2593 dce_v11_0_show_cursor(crtc); 2594 2595 dce_v11_0_lock_cursor(crtc, false); 2596 } 2597 } 2598 2599 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2600 u16 *blue, uint32_t start, uint32_t size) 2601 { 2602 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2603 int end = (start + size > 256) ? 256 : start + size, i; 2604 2605 /* userspace palettes are always correct as is */ 2606 for (i = start; i < end; i++) { 2607 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2608 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2609 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2610 } 2611 dce_v11_0_crtc_load_lut(crtc); 2612 } 2613 2614 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2615 { 2616 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2617 2618 drm_crtc_cleanup(crtc); 2619 kfree(amdgpu_crtc); 2620 } 2621 2622 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2623 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2624 .cursor_move = dce_v11_0_crtc_cursor_move, 2625 .gamma_set = dce_v11_0_crtc_gamma_set, 2626 .set_config = amdgpu_crtc_set_config, 2627 .destroy = dce_v11_0_crtc_destroy, 2628 .page_flip = amdgpu_crtc_page_flip, 2629 }; 2630 2631 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2632 { 2633 struct drm_device *dev = crtc->dev; 2634 struct amdgpu_device *adev = dev->dev_private; 2635 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2636 unsigned type; 2637 2638 switch (mode) { 2639 case DRM_MODE_DPMS_ON: 2640 amdgpu_crtc->enabled = true; 2641 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2642 dce_v11_0_vga_enable(crtc, true); 2643 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2644 dce_v11_0_vga_enable(crtc, false); 2645 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2646 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2647 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2648 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2649 drm_vblank_on(dev, amdgpu_crtc->crtc_id); 2650 dce_v11_0_crtc_load_lut(crtc); 2651 break; 2652 case DRM_MODE_DPMS_STANDBY: 2653 case DRM_MODE_DPMS_SUSPEND: 2654 case DRM_MODE_DPMS_OFF: 2655 drm_vblank_off(dev, amdgpu_crtc->crtc_id); 2656 if (amdgpu_crtc->enabled) { 2657 dce_v11_0_vga_enable(crtc, true); 2658 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2659 dce_v11_0_vga_enable(crtc, false); 2660 } 2661 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2662 amdgpu_crtc->enabled = false; 2663 break; 2664 } 2665 /* adjust pm to dpms */ 2666 amdgpu_pm_compute_clocks(adev); 2667 } 2668 2669 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2670 { 2671 /* disable crtc pair power gating before programming */ 2672 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2673 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2674 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2675 } 2676 2677 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2678 { 2679 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2680 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2681 } 2682 2683 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2684 { 2685 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2686 struct drm_device *dev = crtc->dev; 2687 struct amdgpu_device *adev = dev->dev_private; 2688 struct amdgpu_atom_ss ss; 2689 int i; 2690 2691 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2692 if (crtc->primary->fb) { 2693 int r; 2694 struct amdgpu_framebuffer *amdgpu_fb; 2695 struct amdgpu_bo *rbo; 2696 2697 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2698 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2699 r = amdgpu_bo_reserve(rbo, false); 2700 if (unlikely(r)) 2701 DRM_ERROR("failed to reserve rbo before unpin\n"); 2702 else { 2703 amdgpu_bo_unpin(rbo); 2704 amdgpu_bo_unreserve(rbo); 2705 } 2706 } 2707 /* disable the GRPH */ 2708 dce_v11_0_grph_enable(crtc, false); 2709 2710 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2711 2712 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2713 if (adev->mode_info.crtcs[i] && 2714 adev->mode_info.crtcs[i]->enabled && 2715 i != amdgpu_crtc->crtc_id && 2716 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2717 /* one other crtc is using this pll don't turn 2718 * off the pll 2719 */ 2720 goto done; 2721 } 2722 } 2723 2724 switch (amdgpu_crtc->pll_id) { 2725 case ATOM_PPLL0: 2726 case ATOM_PPLL1: 2727 case ATOM_PPLL2: 2728 /* disable the ppll */ 2729 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2730 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2731 break; 2732 default: 2733 break; 2734 } 2735 done: 2736 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2737 amdgpu_crtc->adjusted_clock = 0; 2738 amdgpu_crtc->encoder = NULL; 2739 amdgpu_crtc->connector = NULL; 2740 } 2741 2742 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2743 struct drm_display_mode *mode, 2744 struct drm_display_mode *adjusted_mode, 2745 int x, int y, struct drm_framebuffer *old_fb) 2746 { 2747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2748 2749 if (!amdgpu_crtc->adjusted_clock) 2750 return -EINVAL; 2751 2752 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2753 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2754 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2755 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2756 amdgpu_atombios_crtc_scaler_setup(crtc); 2757 dce_v11_0_cursor_reset(crtc); 2758 /* update the hw version fpr dpm */ 2759 amdgpu_crtc->hw_mode = *adjusted_mode; 2760 2761 return 0; 2762 } 2763 2764 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2765 const struct drm_display_mode *mode, 2766 struct drm_display_mode *adjusted_mode) 2767 { 2768 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2769 struct drm_device *dev = crtc->dev; 2770 struct drm_encoder *encoder; 2771 2772 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2773 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2774 if (encoder->crtc == crtc) { 2775 amdgpu_crtc->encoder = encoder; 2776 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2777 break; 2778 } 2779 } 2780 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2781 amdgpu_crtc->encoder = NULL; 2782 amdgpu_crtc->connector = NULL; 2783 return false; 2784 } 2785 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2786 return false; 2787 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2788 return false; 2789 /* pick pll */ 2790 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2791 /* if we can't get a PPLL for a non-DP encoder, fail */ 2792 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2793 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2794 return false; 2795 2796 return true; 2797 } 2798 2799 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2800 struct drm_framebuffer *old_fb) 2801 { 2802 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2803 } 2804 2805 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2806 struct drm_framebuffer *fb, 2807 int x, int y, enum mode_set_atomic state) 2808 { 2809 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2810 } 2811 2812 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2813 .dpms = dce_v11_0_crtc_dpms, 2814 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2815 .mode_set = dce_v11_0_crtc_mode_set, 2816 .mode_set_base = dce_v11_0_crtc_set_base, 2817 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2818 .prepare = dce_v11_0_crtc_prepare, 2819 .commit = dce_v11_0_crtc_commit, 2820 .load_lut = dce_v11_0_crtc_load_lut, 2821 .disable = dce_v11_0_crtc_disable, 2822 }; 2823 2824 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2825 { 2826 struct amdgpu_crtc *amdgpu_crtc; 2827 int i; 2828 2829 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2830 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2831 if (amdgpu_crtc == NULL) 2832 return -ENOMEM; 2833 2834 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2835 2836 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2837 amdgpu_crtc->crtc_id = index; 2838 adev->mode_info.crtcs[index] = amdgpu_crtc; 2839 2840 amdgpu_crtc->max_cursor_width = 128; 2841 amdgpu_crtc->max_cursor_height = 128; 2842 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2843 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2844 2845 for (i = 0; i < 256; i++) { 2846 amdgpu_crtc->lut_r[i] = i << 2; 2847 amdgpu_crtc->lut_g[i] = i << 2; 2848 amdgpu_crtc->lut_b[i] = i << 2; 2849 } 2850 2851 switch (amdgpu_crtc->crtc_id) { 2852 case 0: 2853 default: 2854 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2855 break; 2856 case 1: 2857 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2858 break; 2859 case 2: 2860 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2861 break; 2862 case 3: 2863 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2864 break; 2865 case 4: 2866 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2867 break; 2868 case 5: 2869 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2870 break; 2871 } 2872 2873 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2874 amdgpu_crtc->adjusted_clock = 0; 2875 amdgpu_crtc->encoder = NULL; 2876 amdgpu_crtc->connector = NULL; 2877 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2878 2879 return 0; 2880 } 2881 2882 static int dce_v11_0_early_init(void *handle) 2883 { 2884 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2885 2886 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2887 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2888 2889 dce_v11_0_set_display_funcs(adev); 2890 dce_v11_0_set_irq_funcs(adev); 2891 2892 switch (adev->asic_type) { 2893 case CHIP_CARRIZO: 2894 adev->mode_info.num_crtc = 3; 2895 adev->mode_info.num_hpd = 6; 2896 adev->mode_info.num_dig = 9; 2897 break; 2898 case CHIP_STONEY: 2899 adev->mode_info.num_crtc = 2; 2900 adev->mode_info.num_hpd = 6; 2901 adev->mode_info.num_dig = 9; 2902 break; 2903 default: 2904 /* FIXME: not supported yet */ 2905 return -EINVAL; 2906 } 2907 2908 return 0; 2909 } 2910 2911 static int dce_v11_0_sw_init(void *handle) 2912 { 2913 int r, i; 2914 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2915 2916 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2917 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2918 if (r) 2919 return r; 2920 } 2921 2922 for (i = 8; i < 20; i += 2) { 2923 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2924 if (r) 2925 return r; 2926 } 2927 2928 /* HPD hotplug */ 2929 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2930 if (r) 2931 return r; 2932 2933 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2934 2935 adev->ddev->mode_config.max_width = 16384; 2936 adev->ddev->mode_config.max_height = 16384; 2937 2938 adev->ddev->mode_config.preferred_depth = 24; 2939 adev->ddev->mode_config.prefer_shadow = 1; 2940 2941 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2942 2943 r = amdgpu_modeset_create_props(adev); 2944 if (r) 2945 return r; 2946 2947 adev->ddev->mode_config.max_width = 16384; 2948 adev->ddev->mode_config.max_height = 16384; 2949 2950 2951 /* allocate crtcs */ 2952 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2953 r = dce_v11_0_crtc_init(adev, i); 2954 if (r) 2955 return r; 2956 } 2957 2958 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2959 amdgpu_print_display_setup(adev->ddev); 2960 else 2961 return -EINVAL; 2962 2963 /* setup afmt */ 2964 r = dce_v11_0_afmt_init(adev); 2965 if (r) 2966 return r; 2967 2968 r = dce_v11_0_audio_init(adev); 2969 if (r) 2970 return r; 2971 2972 drm_kms_helper_poll_init(adev->ddev); 2973 2974 adev->mode_info.mode_config_initialized = true; 2975 return 0; 2976 } 2977 2978 static int dce_v11_0_sw_fini(void *handle) 2979 { 2980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2981 2982 kfree(adev->mode_info.bios_hardcoded_edid); 2983 2984 drm_kms_helper_poll_fini(adev->ddev); 2985 2986 dce_v11_0_audio_fini(adev); 2987 2988 dce_v11_0_afmt_fini(adev); 2989 2990 adev->mode_info.mode_config_initialized = false; 2991 2992 return 0; 2993 } 2994 2995 static int dce_v11_0_hw_init(void *handle) 2996 { 2997 int i; 2998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2999 3000 dce_v11_0_init_golden_registers(adev); 3001 3002 /* init dig PHYs, disp eng pll */ 3003 amdgpu_atombios_crtc_powergate_init(adev); 3004 amdgpu_atombios_encoder_init_dig(adev); 3005 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3006 3007 /* initialize hpd */ 3008 dce_v11_0_hpd_init(adev); 3009 3010 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3011 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3012 } 3013 3014 dce_v11_0_pageflip_interrupt_init(adev); 3015 3016 return 0; 3017 } 3018 3019 static int dce_v11_0_hw_fini(void *handle) 3020 { 3021 int i; 3022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3023 3024 dce_v11_0_hpd_fini(adev); 3025 3026 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3027 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3028 } 3029 3030 dce_v11_0_pageflip_interrupt_fini(adev); 3031 3032 return 0; 3033 } 3034 3035 static int dce_v11_0_suspend(void *handle) 3036 { 3037 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3038 3039 amdgpu_atombios_scratch_regs_save(adev); 3040 3041 return dce_v11_0_hw_fini(handle); 3042 } 3043 3044 static int dce_v11_0_resume(void *handle) 3045 { 3046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3047 int ret; 3048 3049 ret = dce_v11_0_hw_init(handle); 3050 3051 amdgpu_atombios_scratch_regs_restore(adev); 3052 3053 /* turn on the BL */ 3054 if (adev->mode_info.bl_encoder) { 3055 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3056 adev->mode_info.bl_encoder); 3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3058 bl_level); 3059 } 3060 3061 return ret; 3062 } 3063 3064 static bool dce_v11_0_is_idle(void *handle) 3065 { 3066 return true; 3067 } 3068 3069 static int dce_v11_0_wait_for_idle(void *handle) 3070 { 3071 return 0; 3072 } 3073 3074 static void dce_v11_0_print_status(void *handle) 3075 { 3076 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3077 3078 dev_info(adev->dev, "DCE 10.x registers\n"); 3079 /* XXX todo */ 3080 } 3081 3082 static int dce_v11_0_soft_reset(void *handle) 3083 { 3084 u32 srbm_soft_reset = 0, tmp; 3085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3086 3087 if (dce_v11_0_is_display_hung(adev)) 3088 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3089 3090 if (srbm_soft_reset) { 3091 dce_v11_0_print_status((void *)adev); 3092 3093 tmp = RREG32(mmSRBM_SOFT_RESET); 3094 tmp |= srbm_soft_reset; 3095 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3096 WREG32(mmSRBM_SOFT_RESET, tmp); 3097 tmp = RREG32(mmSRBM_SOFT_RESET); 3098 3099 udelay(50); 3100 3101 tmp &= ~srbm_soft_reset; 3102 WREG32(mmSRBM_SOFT_RESET, tmp); 3103 tmp = RREG32(mmSRBM_SOFT_RESET); 3104 3105 /* Wait a little for things to settle down */ 3106 udelay(50); 3107 dce_v11_0_print_status((void *)adev); 3108 } 3109 return 0; 3110 } 3111 3112 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3113 int crtc, 3114 enum amdgpu_interrupt_state state) 3115 { 3116 u32 lb_interrupt_mask; 3117 3118 if (crtc >= adev->mode_info.num_crtc) { 3119 DRM_DEBUG("invalid crtc %d\n", crtc); 3120 return; 3121 } 3122 3123 switch (state) { 3124 case AMDGPU_IRQ_STATE_DISABLE: 3125 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3126 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3127 VBLANK_INTERRUPT_MASK, 0); 3128 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3129 break; 3130 case AMDGPU_IRQ_STATE_ENABLE: 3131 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3132 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3133 VBLANK_INTERRUPT_MASK, 1); 3134 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3135 break; 3136 default: 3137 break; 3138 } 3139 } 3140 3141 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3142 int crtc, 3143 enum amdgpu_interrupt_state state) 3144 { 3145 u32 lb_interrupt_mask; 3146 3147 if (crtc >= adev->mode_info.num_crtc) { 3148 DRM_DEBUG("invalid crtc %d\n", crtc); 3149 return; 3150 } 3151 3152 switch (state) { 3153 case AMDGPU_IRQ_STATE_DISABLE: 3154 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3155 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3156 VLINE_INTERRUPT_MASK, 0); 3157 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3158 break; 3159 case AMDGPU_IRQ_STATE_ENABLE: 3160 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3161 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3162 VLINE_INTERRUPT_MASK, 1); 3163 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3164 break; 3165 default: 3166 break; 3167 } 3168 } 3169 3170 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3171 struct amdgpu_irq_src *source, 3172 unsigned hpd, 3173 enum amdgpu_interrupt_state state) 3174 { 3175 u32 tmp; 3176 3177 if (hpd >= adev->mode_info.num_hpd) { 3178 DRM_DEBUG("invalid hdp %d\n", hpd); 3179 return 0; 3180 } 3181 3182 switch (state) { 3183 case AMDGPU_IRQ_STATE_DISABLE: 3184 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3185 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3186 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3187 break; 3188 case AMDGPU_IRQ_STATE_ENABLE: 3189 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3190 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3191 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3192 break; 3193 default: 3194 break; 3195 } 3196 3197 return 0; 3198 } 3199 3200 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3201 struct amdgpu_irq_src *source, 3202 unsigned type, 3203 enum amdgpu_interrupt_state state) 3204 { 3205 switch (type) { 3206 case AMDGPU_CRTC_IRQ_VBLANK1: 3207 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3208 break; 3209 case AMDGPU_CRTC_IRQ_VBLANK2: 3210 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3211 break; 3212 case AMDGPU_CRTC_IRQ_VBLANK3: 3213 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3214 break; 3215 case AMDGPU_CRTC_IRQ_VBLANK4: 3216 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3217 break; 3218 case AMDGPU_CRTC_IRQ_VBLANK5: 3219 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3220 break; 3221 case AMDGPU_CRTC_IRQ_VBLANK6: 3222 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3223 break; 3224 case AMDGPU_CRTC_IRQ_VLINE1: 3225 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3226 break; 3227 case AMDGPU_CRTC_IRQ_VLINE2: 3228 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3229 break; 3230 case AMDGPU_CRTC_IRQ_VLINE3: 3231 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3232 break; 3233 case AMDGPU_CRTC_IRQ_VLINE4: 3234 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3235 break; 3236 case AMDGPU_CRTC_IRQ_VLINE5: 3237 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3238 break; 3239 case AMDGPU_CRTC_IRQ_VLINE6: 3240 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3241 break; 3242 default: 3243 break; 3244 } 3245 return 0; 3246 } 3247 3248 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3249 struct amdgpu_irq_src *src, 3250 unsigned type, 3251 enum amdgpu_interrupt_state state) 3252 { 3253 u32 reg; 3254 3255 if (type >= adev->mode_info.num_crtc) { 3256 DRM_ERROR("invalid pageflip crtc %d\n", type); 3257 return -EINVAL; 3258 } 3259 3260 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3261 if (state == AMDGPU_IRQ_STATE_DISABLE) 3262 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3263 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3264 else 3265 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3266 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3267 3268 return 0; 3269 } 3270 3271 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3272 struct amdgpu_irq_src *source, 3273 struct amdgpu_iv_entry *entry) 3274 { 3275 unsigned long flags; 3276 unsigned crtc_id; 3277 struct amdgpu_crtc *amdgpu_crtc; 3278 struct amdgpu_flip_work *works; 3279 3280 crtc_id = (entry->src_id - 8) >> 1; 3281 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3282 3283 if (crtc_id >= adev->mode_info.num_crtc) { 3284 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3285 return -EINVAL; 3286 } 3287 3288 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3289 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3290 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3291 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3292 3293 /* IRQ could occur when in initial stage */ 3294 if(amdgpu_crtc == NULL) 3295 return 0; 3296 3297 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3298 works = amdgpu_crtc->pflip_works; 3299 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3300 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3301 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3302 amdgpu_crtc->pflip_status, 3303 AMDGPU_FLIP_SUBMITTED); 3304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3305 return 0; 3306 } 3307 3308 /* page flip completed. clean up */ 3309 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3310 amdgpu_crtc->pflip_works = NULL; 3311 3312 /* wakeup usersapce */ 3313 if(works->event) 3314 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3315 3316 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3317 3318 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3319 schedule_work(&works->unpin_work); 3320 3321 return 0; 3322 } 3323 3324 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3325 int hpd) 3326 { 3327 u32 tmp; 3328 3329 if (hpd >= adev->mode_info.num_hpd) { 3330 DRM_DEBUG("invalid hdp %d\n", hpd); 3331 return; 3332 } 3333 3334 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3335 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3336 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3337 } 3338 3339 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3340 int crtc) 3341 { 3342 u32 tmp; 3343 3344 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3345 DRM_DEBUG("invalid crtc %d\n", crtc); 3346 return; 3347 } 3348 3349 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3350 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3351 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3352 } 3353 3354 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3355 int crtc) 3356 { 3357 u32 tmp; 3358 3359 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3360 DRM_DEBUG("invalid crtc %d\n", crtc); 3361 return; 3362 } 3363 3364 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3365 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3366 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3367 } 3368 3369 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3370 struct amdgpu_irq_src *source, 3371 struct amdgpu_iv_entry *entry) 3372 { 3373 unsigned crtc = entry->src_id - 1; 3374 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3375 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3376 3377 switch (entry->src_data) { 3378 case 0: /* vblank */ 3379 if (disp_int & interrupt_status_offsets[crtc].vblank) 3380 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3381 else 3382 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3383 3384 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3385 drm_handle_vblank(adev->ddev, crtc); 3386 } 3387 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3388 3389 break; 3390 case 1: /* vline */ 3391 if (disp_int & interrupt_status_offsets[crtc].vline) 3392 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3393 else 3394 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3395 3396 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3397 3398 break; 3399 default: 3400 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3401 break; 3402 } 3403 3404 return 0; 3405 } 3406 3407 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3408 struct amdgpu_irq_src *source, 3409 struct amdgpu_iv_entry *entry) 3410 { 3411 uint32_t disp_int, mask; 3412 unsigned hpd; 3413 3414 if (entry->src_data >= adev->mode_info.num_hpd) { 3415 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3416 return 0; 3417 } 3418 3419 hpd = entry->src_data; 3420 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3421 mask = interrupt_status_offsets[hpd].hpd; 3422 3423 if (disp_int & mask) { 3424 dce_v11_0_hpd_int_ack(adev, hpd); 3425 schedule_work(&adev->hotplug_work); 3426 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3427 } 3428 3429 return 0; 3430 } 3431 3432 static int dce_v11_0_set_clockgating_state(void *handle, 3433 enum amd_clockgating_state state) 3434 { 3435 return 0; 3436 } 3437 3438 static int dce_v11_0_set_powergating_state(void *handle, 3439 enum amd_powergating_state state) 3440 { 3441 return 0; 3442 } 3443 3444 const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3445 .early_init = dce_v11_0_early_init, 3446 .late_init = NULL, 3447 .sw_init = dce_v11_0_sw_init, 3448 .sw_fini = dce_v11_0_sw_fini, 3449 .hw_init = dce_v11_0_hw_init, 3450 .hw_fini = dce_v11_0_hw_fini, 3451 .suspend = dce_v11_0_suspend, 3452 .resume = dce_v11_0_resume, 3453 .is_idle = dce_v11_0_is_idle, 3454 .wait_for_idle = dce_v11_0_wait_for_idle, 3455 .soft_reset = dce_v11_0_soft_reset, 3456 .print_status = dce_v11_0_print_status, 3457 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3458 .set_powergating_state = dce_v11_0_set_powergating_state, 3459 }; 3460 3461 static void 3462 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3463 struct drm_display_mode *mode, 3464 struct drm_display_mode *adjusted_mode) 3465 { 3466 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3467 3468 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3469 3470 /* need to call this here rather than in prepare() since we need some crtc info */ 3471 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3472 3473 /* set scaler clears this on some chips */ 3474 dce_v11_0_set_interleave(encoder->crtc, mode); 3475 3476 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3477 dce_v11_0_afmt_enable(encoder, true); 3478 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3479 } 3480 } 3481 3482 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3483 { 3484 struct amdgpu_device *adev = encoder->dev->dev_private; 3485 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3486 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3487 3488 if ((amdgpu_encoder->active_device & 3489 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3490 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3491 ENCODER_OBJECT_ID_NONE)) { 3492 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3493 if (dig) { 3494 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3495 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3496 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3497 } 3498 } 3499 3500 amdgpu_atombios_scratch_regs_lock(adev, true); 3501 3502 if (connector) { 3503 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3504 3505 /* select the clock/data port if it uses a router */ 3506 if (amdgpu_connector->router.cd_valid) 3507 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3508 3509 /* turn eDP panel on for mode set */ 3510 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3511 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3512 ATOM_TRANSMITTER_ACTION_POWER_ON); 3513 } 3514 3515 /* this is needed for the pll/ss setup to work correctly in some cases */ 3516 amdgpu_atombios_encoder_set_crtc_source(encoder); 3517 /* set up the FMT blocks */ 3518 dce_v11_0_program_fmt(encoder); 3519 } 3520 3521 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3522 { 3523 struct drm_device *dev = encoder->dev; 3524 struct amdgpu_device *adev = dev->dev_private; 3525 3526 /* need to call this here as we need the crtc set up */ 3527 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3528 amdgpu_atombios_scratch_regs_lock(adev, false); 3529 } 3530 3531 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3532 { 3533 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3534 struct amdgpu_encoder_atom_dig *dig; 3535 3536 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3537 3538 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3539 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3540 dce_v11_0_afmt_enable(encoder, false); 3541 dig = amdgpu_encoder->enc_priv; 3542 dig->dig_encoder = -1; 3543 } 3544 amdgpu_encoder->active_device = 0; 3545 } 3546 3547 /* these are handled by the primary encoders */ 3548 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3549 { 3550 3551 } 3552 3553 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3554 { 3555 3556 } 3557 3558 static void 3559 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3560 struct drm_display_mode *mode, 3561 struct drm_display_mode *adjusted_mode) 3562 { 3563 3564 } 3565 3566 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3567 { 3568 3569 } 3570 3571 static void 3572 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3573 { 3574 3575 } 3576 3577 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3578 .dpms = dce_v11_0_ext_dpms, 3579 .prepare = dce_v11_0_ext_prepare, 3580 .mode_set = dce_v11_0_ext_mode_set, 3581 .commit = dce_v11_0_ext_commit, 3582 .disable = dce_v11_0_ext_disable, 3583 /* no detect for TMDS/LVDS yet */ 3584 }; 3585 3586 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3587 .dpms = amdgpu_atombios_encoder_dpms, 3588 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3589 .prepare = dce_v11_0_encoder_prepare, 3590 .mode_set = dce_v11_0_encoder_mode_set, 3591 .commit = dce_v11_0_encoder_commit, 3592 .disable = dce_v11_0_encoder_disable, 3593 .detect = amdgpu_atombios_encoder_dig_detect, 3594 }; 3595 3596 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3597 .dpms = amdgpu_atombios_encoder_dpms, 3598 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3599 .prepare = dce_v11_0_encoder_prepare, 3600 .mode_set = dce_v11_0_encoder_mode_set, 3601 .commit = dce_v11_0_encoder_commit, 3602 .detect = amdgpu_atombios_encoder_dac_detect, 3603 }; 3604 3605 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3606 { 3607 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3608 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3609 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3610 kfree(amdgpu_encoder->enc_priv); 3611 drm_encoder_cleanup(encoder); 3612 kfree(amdgpu_encoder); 3613 } 3614 3615 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3616 .destroy = dce_v11_0_encoder_destroy, 3617 }; 3618 3619 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3620 uint32_t encoder_enum, 3621 uint32_t supported_device, 3622 u16 caps) 3623 { 3624 struct drm_device *dev = adev->ddev; 3625 struct drm_encoder *encoder; 3626 struct amdgpu_encoder *amdgpu_encoder; 3627 3628 /* see if we already added it */ 3629 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3630 amdgpu_encoder = to_amdgpu_encoder(encoder); 3631 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3632 amdgpu_encoder->devices |= supported_device; 3633 return; 3634 } 3635 3636 } 3637 3638 /* add a new one */ 3639 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3640 if (!amdgpu_encoder) 3641 return; 3642 3643 encoder = &amdgpu_encoder->base; 3644 switch (adev->mode_info.num_crtc) { 3645 case 1: 3646 encoder->possible_crtcs = 0x1; 3647 break; 3648 case 2: 3649 default: 3650 encoder->possible_crtcs = 0x3; 3651 break; 3652 case 4: 3653 encoder->possible_crtcs = 0xf; 3654 break; 3655 case 6: 3656 encoder->possible_crtcs = 0x3f; 3657 break; 3658 } 3659 3660 amdgpu_encoder->enc_priv = NULL; 3661 3662 amdgpu_encoder->encoder_enum = encoder_enum; 3663 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3664 amdgpu_encoder->devices = supported_device; 3665 amdgpu_encoder->rmx_type = RMX_OFF; 3666 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3667 amdgpu_encoder->is_ext_encoder = false; 3668 amdgpu_encoder->caps = caps; 3669 3670 switch (amdgpu_encoder->encoder_id) { 3671 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3673 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3674 DRM_MODE_ENCODER_DAC, NULL); 3675 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3676 break; 3677 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3678 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3680 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3682 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3683 amdgpu_encoder->rmx_type = RMX_FULL; 3684 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3685 DRM_MODE_ENCODER_LVDS, NULL); 3686 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3687 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3688 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3689 DRM_MODE_ENCODER_DAC, NULL); 3690 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3691 } else { 3692 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3693 DRM_MODE_ENCODER_TMDS, NULL); 3694 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3695 } 3696 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3697 break; 3698 case ENCODER_OBJECT_ID_SI170B: 3699 case ENCODER_OBJECT_ID_CH7303: 3700 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3701 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3702 case ENCODER_OBJECT_ID_TITFP513: 3703 case ENCODER_OBJECT_ID_VT1623: 3704 case ENCODER_OBJECT_ID_HDMI_SI1930: 3705 case ENCODER_OBJECT_ID_TRAVIS: 3706 case ENCODER_OBJECT_ID_NUTMEG: 3707 /* these are handled by the primary encoders */ 3708 amdgpu_encoder->is_ext_encoder = true; 3709 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3710 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3711 DRM_MODE_ENCODER_LVDS, NULL); 3712 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3713 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3714 DRM_MODE_ENCODER_DAC, NULL); 3715 else 3716 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3717 DRM_MODE_ENCODER_TMDS, NULL); 3718 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3719 break; 3720 } 3721 } 3722 3723 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3724 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3725 .bandwidth_update = &dce_v11_0_bandwidth_update, 3726 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3727 .vblank_wait = &dce_v11_0_vblank_wait, 3728 .is_display_hung = &dce_v11_0_is_display_hung, 3729 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3730 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3731 .hpd_sense = &dce_v11_0_hpd_sense, 3732 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3733 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3734 .page_flip = &dce_v11_0_page_flip, 3735 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3736 .add_encoder = &dce_v11_0_encoder_add, 3737 .add_connector = &amdgpu_connector_add, 3738 .stop_mc_access = &dce_v11_0_stop_mc_access, 3739 .resume_mc_access = &dce_v11_0_resume_mc_access, 3740 }; 3741 3742 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3743 { 3744 if (adev->mode_info.funcs == NULL) 3745 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3746 } 3747 3748 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3749 .set = dce_v11_0_set_crtc_irq_state, 3750 .process = dce_v11_0_crtc_irq, 3751 }; 3752 3753 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3754 .set = dce_v11_0_set_pageflip_irq_state, 3755 .process = dce_v11_0_pageflip_irq, 3756 }; 3757 3758 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3759 .set = dce_v11_0_set_hpd_irq_state, 3760 .process = dce_v11_0_hpd_irq, 3761 }; 3762 3763 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3764 { 3765 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3766 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3767 3768 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3769 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3770 3771 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3772 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3773 } 3774