1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_10_0_d.h" 36 #include "dce/dce_10_0_sh_mask.h" 37 #include "dce/dce_10_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET 75 }; 76 77 static const struct { 78 uint32_t reg; 79 uint32_t vblank; 80 uint32_t vline; 81 uint32_t hpd; 82 83 } interrupt_status_offsets[] = { { 84 .reg = mmDISP_INTERRUPT_STATUS, 85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 88 }, { 89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 93 }, { 94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 98 }, { 99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 103 }, { 104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 113 } }; 114 115 static const u32 golden_settings_tonga_a11[] = 116 { 117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 119 mmFBC_MISC, 0x1f311fff, 0x12300000, 120 mmHDMI_CONTROL, 0x31000111, 0x00000011, 121 }; 122 123 static const u32 tonga_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 130 { 131 switch (adev->asic_type) { 132 case CHIP_TONGA: 133 amdgpu_program_register_sequence(adev, 134 tonga_mgcg_cgcg_init, 135 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 136 amdgpu_program_register_sequence(adev, 137 golden_settings_tonga_a11, 138 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 139 break; 140 default: 141 break; 142 } 143 } 144 145 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 146 u32 block_offset, u32 reg) 147 { 148 unsigned long flags; 149 u32 r; 150 151 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 152 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 153 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 154 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 155 156 return r; 157 } 158 159 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 160 u32 block_offset, u32 reg, u32 v) 161 { 162 unsigned long flags; 163 164 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 165 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 166 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 167 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 168 } 169 170 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 171 { 172 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 173 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 174 return true; 175 else 176 return false; 177 } 178 179 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 180 { 181 u32 pos1, pos2; 182 183 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 184 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 185 186 if (pos1 != pos2) 187 return true; 188 else 189 return false; 190 } 191 192 /** 193 * dce_v10_0_vblank_wait - vblank wait asic callback. 194 * 195 * @adev: amdgpu_device pointer 196 * @crtc: crtc to wait for vblank on 197 * 198 * Wait for vblank on the requested crtc (evergreen+). 199 */ 200 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) 201 { 202 unsigned i = 0; 203 204 if (crtc >= adev->mode_info.num_crtc) 205 return; 206 207 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 208 return; 209 210 /* depending on when we hit vblank, we may be close to active; if so, 211 * wait for another frame. 212 */ 213 while (dce_v10_0_is_in_vblank(adev, crtc)) { 214 if (i++ % 100 == 0) { 215 if (!dce_v10_0_is_counter_moving(adev, crtc)) 216 break; 217 } 218 } 219 220 while (!dce_v10_0_is_in_vblank(adev, crtc)) { 221 if (i++ % 100 == 0) { 222 if (!dce_v10_0_is_counter_moving(adev, crtc)) 223 break; 224 } 225 } 226 } 227 228 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 229 { 230 if (crtc >= adev->mode_info.num_crtc) 231 return 0; 232 else 233 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 234 } 235 236 /** 237 * dce_v10_0_page_flip - pageflip callback. 238 * 239 * @adev: amdgpu_device pointer 240 * @crtc_id: crtc to cleanup pageflip on 241 * @crtc_base: new address of the crtc (GPU MC address) 242 * 243 * Does the actual pageflip (evergreen+). 244 * During vblank we take the crtc lock and wait for the update_pending 245 * bit to go high, when it does, we release the lock, and allow the 246 * double buffered update to take place. 247 * Returns the current update pending status. 248 */ 249 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 250 int crtc_id, u64 crtc_base) 251 { 252 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 253 u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); 254 int i; 255 256 /* Lock the graphics update lock */ 257 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 258 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); 259 260 /* update the scanout addresses */ 261 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 262 upper_32_bits(crtc_base)); 263 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 264 lower_32_bits(crtc_base)); 265 266 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 267 upper_32_bits(crtc_base)); 268 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 269 lower_32_bits(crtc_base)); 270 271 /* Wait for update_pending to go high. */ 272 for (i = 0; i < adev->usec_timeout; i++) { 273 if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & 274 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) 275 break; 276 udelay(1); 277 } 278 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 279 280 /* Unlock the lock, so double-buffering can take place inside vblank */ 281 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 282 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); 283 } 284 285 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 286 u32 *vbl, u32 *position) 287 { 288 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 289 return -EINVAL; 290 291 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 292 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 293 294 return 0; 295 } 296 297 /** 298 * dce_v10_0_hpd_sense - hpd sense callback. 299 * 300 * @adev: amdgpu_device pointer 301 * @hpd: hpd (hotplug detect) pin 302 * 303 * Checks if a digital monitor is connected (evergreen+). 304 * Returns true if connected, false if not connected. 305 */ 306 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 307 enum amdgpu_hpd_id hpd) 308 { 309 int idx; 310 bool connected = false; 311 312 switch (hpd) { 313 case AMDGPU_HPD_1: 314 idx = 0; 315 break; 316 case AMDGPU_HPD_2: 317 idx = 1; 318 break; 319 case AMDGPU_HPD_3: 320 idx = 2; 321 break; 322 case AMDGPU_HPD_4: 323 idx = 3; 324 break; 325 case AMDGPU_HPD_5: 326 idx = 4; 327 break; 328 case AMDGPU_HPD_6: 329 idx = 5; 330 break; 331 default: 332 return connected; 333 } 334 335 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 336 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 337 connected = true; 338 339 return connected; 340 } 341 342 /** 343 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 344 * 345 * @adev: amdgpu_device pointer 346 * @hpd: hpd (hotplug detect) pin 347 * 348 * Set the polarity of the hpd pin (evergreen+). 349 */ 350 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 351 enum amdgpu_hpd_id hpd) 352 { 353 u32 tmp; 354 bool connected = dce_v10_0_hpd_sense(adev, hpd); 355 int idx; 356 357 switch (hpd) { 358 case AMDGPU_HPD_1: 359 idx = 0; 360 break; 361 case AMDGPU_HPD_2: 362 idx = 1; 363 break; 364 case AMDGPU_HPD_3: 365 idx = 2; 366 break; 367 case AMDGPU_HPD_4: 368 idx = 3; 369 break; 370 case AMDGPU_HPD_5: 371 idx = 4; 372 break; 373 case AMDGPU_HPD_6: 374 idx = 5; 375 break; 376 default: 377 return; 378 } 379 380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 381 if (connected) 382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 383 else 384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 386 } 387 388 /** 389 * dce_v10_0_hpd_init - hpd setup callback. 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * Setup the hpd pins used by the card (evergreen+). 394 * Enable the pin, set the polarity, and enable the hpd interrupts. 395 */ 396 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 397 { 398 struct drm_device *dev = adev->ddev; 399 struct drm_connector *connector; 400 u32 tmp; 401 int idx; 402 403 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 404 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 405 406 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 407 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 408 /* don't try to enable hpd on eDP or LVDS avoid breaking the 409 * aux dp channel on imac and help (but not completely fix) 410 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 411 * also avoid interrupt storms during dpms. 412 */ 413 continue; 414 } 415 416 switch (amdgpu_connector->hpd.hpd) { 417 case AMDGPU_HPD_1: 418 idx = 0; 419 break; 420 case AMDGPU_HPD_2: 421 idx = 1; 422 break; 423 case AMDGPU_HPD_3: 424 idx = 2; 425 break; 426 case AMDGPU_HPD_4: 427 idx = 3; 428 break; 429 case AMDGPU_HPD_5: 430 idx = 4; 431 break; 432 case AMDGPU_HPD_6: 433 idx = 5; 434 break; 435 default: 436 continue; 437 } 438 439 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 440 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 441 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 442 443 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 444 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 445 DC_HPD_CONNECT_INT_DELAY, 446 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 447 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 448 DC_HPD_DISCONNECT_INT_DELAY, 449 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 450 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 451 452 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 453 amdgpu_irq_get(adev, &adev->hpd_irq, 454 amdgpu_connector->hpd.hpd); 455 } 456 } 457 458 /** 459 * dce_v10_0_hpd_fini - hpd tear down callback. 460 * 461 * @adev: amdgpu_device pointer 462 * 463 * Tear down the hpd pins used by the card (evergreen+). 464 * Disable the hpd interrupts. 465 */ 466 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 467 { 468 struct drm_device *dev = adev->ddev; 469 struct drm_connector *connector; 470 u32 tmp; 471 int idx; 472 473 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 474 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 475 476 switch (amdgpu_connector->hpd.hpd) { 477 case AMDGPU_HPD_1: 478 idx = 0; 479 break; 480 case AMDGPU_HPD_2: 481 idx = 1; 482 break; 483 case AMDGPU_HPD_3: 484 idx = 2; 485 break; 486 case AMDGPU_HPD_4: 487 idx = 3; 488 break; 489 case AMDGPU_HPD_5: 490 idx = 4; 491 break; 492 case AMDGPU_HPD_6: 493 idx = 5; 494 break; 495 default: 496 continue; 497 } 498 499 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 500 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 501 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 502 503 amdgpu_irq_put(adev, &adev->hpd_irq, 504 amdgpu_connector->hpd.hpd); 505 } 506 } 507 508 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 509 { 510 return mmDC_GPIO_HPD_A; 511 } 512 513 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 514 { 515 u32 crtc_hung = 0; 516 u32 crtc_status[6]; 517 u32 i, j, tmp; 518 519 for (i = 0; i < adev->mode_info.num_crtc; i++) { 520 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 521 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 522 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 523 crtc_hung |= (1 << i); 524 } 525 } 526 527 for (j = 0; j < 10; j++) { 528 for (i = 0; i < adev->mode_info.num_crtc; i++) { 529 if (crtc_hung & (1 << i)) { 530 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 531 if (tmp != crtc_status[i]) 532 crtc_hung &= ~(1 << i); 533 } 534 } 535 if (crtc_hung == 0) 536 return false; 537 udelay(100); 538 } 539 540 return true; 541 } 542 543 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, 544 struct amdgpu_mode_mc_save *save) 545 { 546 u32 crtc_enabled, tmp; 547 int i; 548 549 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 550 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 551 552 /* disable VGA render */ 553 tmp = RREG32(mmVGA_RENDER_CONTROL); 554 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 555 WREG32(mmVGA_RENDER_CONTROL, tmp); 556 557 /* blank the display controllers */ 558 for (i = 0; i < adev->mode_info.num_crtc; i++) { 559 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 560 CRTC_CONTROL, CRTC_MASTER_EN); 561 if (crtc_enabled) { 562 #if 0 563 u32 frame_count; 564 int j; 565 566 save->crtc_enabled[i] = true; 567 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 568 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 569 amdgpu_display_vblank_wait(adev, i); 570 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 571 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 572 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 573 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 574 } 575 /* wait for the next frame */ 576 frame_count = amdgpu_display_vblank_get_counter(adev, i); 577 for (j = 0; j < adev->usec_timeout; j++) { 578 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 579 break; 580 udelay(1); 581 } 582 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 583 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 584 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 585 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 586 } 587 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 588 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 589 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 590 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 591 } 592 #else 593 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 594 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 595 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 596 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 597 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 598 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 599 save->crtc_enabled[i] = false; 600 /* ***** */ 601 #endif 602 } else { 603 save->crtc_enabled[i] = false; 604 } 605 } 606 } 607 608 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, 609 struct amdgpu_mode_mc_save *save) 610 { 611 u32 tmp, frame_count; 612 int i, j; 613 614 /* update crtc base addresses */ 615 for (i = 0; i < adev->mode_info.num_crtc; i++) { 616 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 617 upper_32_bits(adev->mc.vram_start)); 618 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 619 upper_32_bits(adev->mc.vram_start)); 620 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 621 (u32)adev->mc.vram_start); 622 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 623 (u32)adev->mc.vram_start); 624 625 if (save->crtc_enabled[i]) { 626 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 627 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 628 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 629 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 630 } 631 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 632 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 633 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 634 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 635 } 636 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 637 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 638 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 639 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 640 } 641 for (j = 0; j < adev->usec_timeout; j++) { 642 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 643 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 644 break; 645 udelay(1); 646 } 647 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 648 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 649 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 650 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 651 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 652 /* wait for the next frame */ 653 frame_count = amdgpu_display_vblank_get_counter(adev, i); 654 for (j = 0; j < adev->usec_timeout; j++) { 655 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 656 break; 657 udelay(1); 658 } 659 } 660 } 661 662 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 663 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 664 665 /* Unlock vga access */ 666 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 667 mdelay(1); 668 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 669 } 670 671 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 672 bool render) 673 { 674 u32 tmp; 675 676 /* Lockout access through VGA aperture*/ 677 tmp = RREG32(mmVGA_HDP_CONTROL); 678 if (render) 679 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 680 else 681 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 682 WREG32(mmVGA_HDP_CONTROL, tmp); 683 684 /* disable VGA render */ 685 tmp = RREG32(mmVGA_RENDER_CONTROL); 686 if (render) 687 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 688 else 689 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 690 WREG32(mmVGA_RENDER_CONTROL, tmp); 691 } 692 693 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 694 { 695 struct drm_device *dev = encoder->dev; 696 struct amdgpu_device *adev = dev->dev_private; 697 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 699 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 700 int bpc = 0; 701 u32 tmp = 0; 702 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 703 704 if (connector) { 705 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 706 bpc = amdgpu_connector_get_monitor_bpc(connector); 707 dither = amdgpu_connector->dither; 708 } 709 710 /* LVDS/eDP FMT is set up by atom */ 711 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 712 return; 713 714 /* not needed for analog */ 715 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 716 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 717 return; 718 719 if (bpc == 0) 720 return; 721 722 switch (bpc) { 723 case 6: 724 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 725 /* XXX sort out optimal dither settings */ 726 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 727 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 729 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 730 } else { 731 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 733 } 734 break; 735 case 8: 736 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 737 /* XXX sort out optimal dither settings */ 738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 739 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 740 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 743 } else { 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 746 } 747 break; 748 case 10: 749 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 750 /* XXX sort out optimal dither settings */ 751 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 752 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 753 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 756 } else { 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 759 } 760 break; 761 default: 762 /* not needed */ 763 break; 764 } 765 766 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 767 } 768 769 770 /* display watermark setup */ 771 /** 772 * dce_v10_0_line_buffer_adjust - Set up the line buffer 773 * 774 * @adev: amdgpu_device pointer 775 * @amdgpu_crtc: the selected display controller 776 * @mode: the current display mode on the selected display 777 * controller 778 * 779 * Setup up the line buffer allocation for 780 * the selected display controller (CIK). 781 * Returns the line buffer size in pixels. 782 */ 783 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 784 struct amdgpu_crtc *amdgpu_crtc, 785 struct drm_display_mode *mode) 786 { 787 u32 tmp, buffer_alloc, i, mem_cfg; 788 u32 pipe_offset = amdgpu_crtc->crtc_id; 789 /* 790 * Line Buffer Setup 791 * There are 6 line buffers, one for each display controllers. 792 * There are 3 partitions per LB. Select the number of partitions 793 * to enable based on the display width. For display widths larger 794 * than 4096, you need use to use 2 display controllers and combine 795 * them using the stereo blender. 796 */ 797 if (amdgpu_crtc->base.enabled && mode) { 798 if (mode->crtc_hdisplay < 1920) { 799 mem_cfg = 1; 800 buffer_alloc = 2; 801 } else if (mode->crtc_hdisplay < 2560) { 802 mem_cfg = 2; 803 buffer_alloc = 2; 804 } else if (mode->crtc_hdisplay < 4096) { 805 mem_cfg = 0; 806 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 807 } else { 808 DRM_DEBUG_KMS("Mode too big for LB!\n"); 809 mem_cfg = 0; 810 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 811 } 812 } else { 813 mem_cfg = 1; 814 buffer_alloc = 0; 815 } 816 817 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 818 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 819 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 820 821 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 822 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 823 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 824 825 for (i = 0; i < adev->usec_timeout; i++) { 826 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 827 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 828 break; 829 udelay(1); 830 } 831 832 if (amdgpu_crtc->base.enabled && mode) { 833 switch (mem_cfg) { 834 case 0: 835 default: 836 return 4096 * 2; 837 case 1: 838 return 1920 * 2; 839 case 2: 840 return 2560 * 2; 841 } 842 } 843 844 /* controller not enabled, so no lb used */ 845 return 0; 846 } 847 848 /** 849 * cik_get_number_of_dram_channels - get the number of dram channels 850 * 851 * @adev: amdgpu_device pointer 852 * 853 * Look up the number of video ram channels (CIK). 854 * Used for display watermark bandwidth calculations 855 * Returns the number of dram channels 856 */ 857 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 858 { 859 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 860 861 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 862 case 0: 863 default: 864 return 1; 865 case 1: 866 return 2; 867 case 2: 868 return 4; 869 case 3: 870 return 8; 871 case 4: 872 return 3; 873 case 5: 874 return 6; 875 case 6: 876 return 10; 877 case 7: 878 return 12; 879 case 8: 880 return 16; 881 } 882 } 883 884 struct dce10_wm_params { 885 u32 dram_channels; /* number of dram channels */ 886 u32 yclk; /* bandwidth per dram data pin in kHz */ 887 u32 sclk; /* engine clock in kHz */ 888 u32 disp_clk; /* display clock in kHz */ 889 u32 src_width; /* viewport width */ 890 u32 active_time; /* active display time in ns */ 891 u32 blank_time; /* blank time in ns */ 892 bool interlaced; /* mode is interlaced */ 893 fixed20_12 vsc; /* vertical scale ratio */ 894 u32 num_heads; /* number of active crtcs */ 895 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 896 u32 lb_size; /* line buffer allocated to pipe */ 897 u32 vtaps; /* vertical scaler taps */ 898 }; 899 900 /** 901 * dce_v10_0_dram_bandwidth - get the dram bandwidth 902 * 903 * @wm: watermark calculation data 904 * 905 * Calculate the raw dram bandwidth (CIK). 906 * Used for display watermark bandwidth calculations 907 * Returns the dram bandwidth in MBytes/s 908 */ 909 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 910 { 911 /* Calculate raw DRAM Bandwidth */ 912 fixed20_12 dram_efficiency; /* 0.7 */ 913 fixed20_12 yclk, dram_channels, bandwidth; 914 fixed20_12 a; 915 916 a.full = dfixed_const(1000); 917 yclk.full = dfixed_const(wm->yclk); 918 yclk.full = dfixed_div(yclk, a); 919 dram_channels.full = dfixed_const(wm->dram_channels * 4); 920 a.full = dfixed_const(10); 921 dram_efficiency.full = dfixed_const(7); 922 dram_efficiency.full = dfixed_div(dram_efficiency, a); 923 bandwidth.full = dfixed_mul(dram_channels, yclk); 924 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 925 926 return dfixed_trunc(bandwidth); 927 } 928 929 /** 930 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 931 * 932 * @wm: watermark calculation data 933 * 934 * Calculate the dram bandwidth used for display (CIK). 935 * Used for display watermark bandwidth calculations 936 * Returns the dram bandwidth for display in MBytes/s 937 */ 938 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 939 { 940 /* Calculate DRAM Bandwidth and the part allocated to display. */ 941 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 942 fixed20_12 yclk, dram_channels, bandwidth; 943 fixed20_12 a; 944 945 a.full = dfixed_const(1000); 946 yclk.full = dfixed_const(wm->yclk); 947 yclk.full = dfixed_div(yclk, a); 948 dram_channels.full = dfixed_const(wm->dram_channels * 4); 949 a.full = dfixed_const(10); 950 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 951 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 952 bandwidth.full = dfixed_mul(dram_channels, yclk); 953 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 954 955 return dfixed_trunc(bandwidth); 956 } 957 958 /** 959 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 960 * 961 * @wm: watermark calculation data 962 * 963 * Calculate the data return bandwidth used for display (CIK). 964 * Used for display watermark bandwidth calculations 965 * Returns the data return bandwidth in MBytes/s 966 */ 967 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 968 { 969 /* Calculate the display Data return Bandwidth */ 970 fixed20_12 return_efficiency; /* 0.8 */ 971 fixed20_12 sclk, bandwidth; 972 fixed20_12 a; 973 974 a.full = dfixed_const(1000); 975 sclk.full = dfixed_const(wm->sclk); 976 sclk.full = dfixed_div(sclk, a); 977 a.full = dfixed_const(10); 978 return_efficiency.full = dfixed_const(8); 979 return_efficiency.full = dfixed_div(return_efficiency, a); 980 a.full = dfixed_const(32); 981 bandwidth.full = dfixed_mul(a, sclk); 982 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 983 984 return dfixed_trunc(bandwidth); 985 } 986 987 /** 988 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 989 * 990 * @wm: watermark calculation data 991 * 992 * Calculate the dmif bandwidth used for display (CIK). 993 * Used for display watermark bandwidth calculations 994 * Returns the dmif bandwidth in MBytes/s 995 */ 996 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 997 { 998 /* Calculate the DMIF Request Bandwidth */ 999 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1000 fixed20_12 disp_clk, bandwidth; 1001 fixed20_12 a, b; 1002 1003 a.full = dfixed_const(1000); 1004 disp_clk.full = dfixed_const(wm->disp_clk); 1005 disp_clk.full = dfixed_div(disp_clk, a); 1006 a.full = dfixed_const(32); 1007 b.full = dfixed_mul(a, disp_clk); 1008 1009 a.full = dfixed_const(10); 1010 disp_clk_request_efficiency.full = dfixed_const(8); 1011 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1012 1013 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1014 1015 return dfixed_trunc(bandwidth); 1016 } 1017 1018 /** 1019 * dce_v10_0_available_bandwidth - get the min available bandwidth 1020 * 1021 * @wm: watermark calculation data 1022 * 1023 * Calculate the min available bandwidth used for display (CIK). 1024 * Used for display watermark bandwidth calculations 1025 * Returns the min available bandwidth in MBytes/s 1026 */ 1027 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 1028 { 1029 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1030 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 1031 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 1032 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 1033 1034 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1035 } 1036 1037 /** 1038 * dce_v10_0_average_bandwidth - get the average available bandwidth 1039 * 1040 * @wm: watermark calculation data 1041 * 1042 * Calculate the average available bandwidth used for display (CIK). 1043 * Used for display watermark bandwidth calculations 1044 * Returns the average available bandwidth in MBytes/s 1045 */ 1046 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 1047 { 1048 /* Calculate the display mode Average Bandwidth 1049 * DisplayMode should contain the source and destination dimensions, 1050 * timing, etc. 1051 */ 1052 fixed20_12 bpp; 1053 fixed20_12 line_time; 1054 fixed20_12 src_width; 1055 fixed20_12 bandwidth; 1056 fixed20_12 a; 1057 1058 a.full = dfixed_const(1000); 1059 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1060 line_time.full = dfixed_div(line_time, a); 1061 bpp.full = dfixed_const(wm->bytes_per_pixel); 1062 src_width.full = dfixed_const(wm->src_width); 1063 bandwidth.full = dfixed_mul(src_width, bpp); 1064 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1065 bandwidth.full = dfixed_div(bandwidth, line_time); 1066 1067 return dfixed_trunc(bandwidth); 1068 } 1069 1070 /** 1071 * dce_v10_0_latency_watermark - get the latency watermark 1072 * 1073 * @wm: watermark calculation data 1074 * 1075 * Calculate the latency watermark (CIK). 1076 * Used for display watermark bandwidth calculations 1077 * Returns the latency watermark in ns 1078 */ 1079 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 1080 { 1081 /* First calculate the latency in ns */ 1082 u32 mc_latency = 2000; /* 2000 ns. */ 1083 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 1084 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1085 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1086 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1087 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1088 (wm->num_heads * cursor_line_pair_return_time); 1089 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1090 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1091 u32 tmp, dmif_size = 12288; 1092 fixed20_12 a, b, c; 1093 1094 if (wm->num_heads == 0) 1095 return 0; 1096 1097 a.full = dfixed_const(2); 1098 b.full = dfixed_const(1); 1099 if ((wm->vsc.full > a.full) || 1100 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1101 (wm->vtaps >= 5) || 1102 ((wm->vsc.full >= a.full) && wm->interlaced)) 1103 max_src_lines_per_dst_line = 4; 1104 else 1105 max_src_lines_per_dst_line = 2; 1106 1107 a.full = dfixed_const(available_bandwidth); 1108 b.full = dfixed_const(wm->num_heads); 1109 a.full = dfixed_div(a, b); 1110 1111 b.full = dfixed_const(mc_latency + 512); 1112 c.full = dfixed_const(wm->disp_clk); 1113 b.full = dfixed_div(b, c); 1114 1115 c.full = dfixed_const(dmif_size); 1116 b.full = dfixed_div(c, b); 1117 1118 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1119 1120 b.full = dfixed_const(1000); 1121 c.full = dfixed_const(wm->disp_clk); 1122 b.full = dfixed_div(c, b); 1123 c.full = dfixed_const(wm->bytes_per_pixel); 1124 b.full = dfixed_mul(b, c); 1125 1126 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1127 1128 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1129 b.full = dfixed_const(1000); 1130 c.full = dfixed_const(lb_fill_bw); 1131 b.full = dfixed_div(c, b); 1132 a.full = dfixed_div(a, b); 1133 line_fill_time = dfixed_trunc(a); 1134 1135 if (line_fill_time < wm->active_time) 1136 return latency; 1137 else 1138 return latency + (line_fill_time - wm->active_time); 1139 1140 } 1141 1142 /** 1143 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1144 * average and available dram bandwidth 1145 * 1146 * @wm: watermark calculation data 1147 * 1148 * Check if the display average bandwidth fits in the display 1149 * dram bandwidth (CIK). 1150 * Used for display watermark bandwidth calculations 1151 * Returns true if the display fits, false if not. 1152 */ 1153 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1154 { 1155 if (dce_v10_0_average_bandwidth(wm) <= 1156 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1157 return true; 1158 else 1159 return false; 1160 } 1161 1162 /** 1163 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 1164 * average and available bandwidth 1165 * 1166 * @wm: watermark calculation data 1167 * 1168 * Check if the display average bandwidth fits in the display 1169 * available bandwidth (CIK). 1170 * Used for display watermark bandwidth calculations 1171 * Returns true if the display fits, false if not. 1172 */ 1173 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1174 { 1175 if (dce_v10_0_average_bandwidth(wm) <= 1176 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 1177 return true; 1178 else 1179 return false; 1180 } 1181 1182 /** 1183 * dce_v10_0_check_latency_hiding - check latency hiding 1184 * 1185 * @wm: watermark calculation data 1186 * 1187 * Check latency hiding (CIK). 1188 * Used for display watermark bandwidth calculations 1189 * Returns true if the display fits, false if not. 1190 */ 1191 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 1192 { 1193 u32 lb_partitions = wm->lb_size / wm->src_width; 1194 u32 line_time = wm->active_time + wm->blank_time; 1195 u32 latency_tolerant_lines; 1196 u32 latency_hiding; 1197 fixed20_12 a; 1198 1199 a.full = dfixed_const(1); 1200 if (wm->vsc.full > a.full) 1201 latency_tolerant_lines = 1; 1202 else { 1203 if (lb_partitions <= (wm->vtaps + 1)) 1204 latency_tolerant_lines = 1; 1205 else 1206 latency_tolerant_lines = 2; 1207 } 1208 1209 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1210 1211 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 1212 return true; 1213 else 1214 return false; 1215 } 1216 1217 /** 1218 * dce_v10_0_program_watermarks - program display watermarks 1219 * 1220 * @adev: amdgpu_device pointer 1221 * @amdgpu_crtc: the selected display controller 1222 * @lb_size: line buffer size 1223 * @num_heads: number of display controllers in use 1224 * 1225 * Calculate and program the display watermarks for the 1226 * selected display controller (CIK). 1227 */ 1228 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 1229 struct amdgpu_crtc *amdgpu_crtc, 1230 u32 lb_size, u32 num_heads) 1231 { 1232 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1233 struct dce10_wm_params wm_low, wm_high; 1234 u32 pixel_period; 1235 u32 line_time = 0; 1236 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1237 u32 tmp, wm_mask; 1238 1239 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1240 pixel_period = 1000000 / (u32)mode->clock; 1241 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1242 1243 /* watermark for high clocks */ 1244 if (adev->pm.dpm_enabled) { 1245 wm_high.yclk = 1246 amdgpu_dpm_get_mclk(adev, false) * 10; 1247 wm_high.sclk = 1248 amdgpu_dpm_get_sclk(adev, false) * 10; 1249 } else { 1250 wm_high.yclk = adev->pm.current_mclk * 10; 1251 wm_high.sclk = adev->pm.current_sclk * 10; 1252 } 1253 1254 wm_high.disp_clk = mode->clock; 1255 wm_high.src_width = mode->crtc_hdisplay; 1256 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1257 wm_high.blank_time = line_time - wm_high.active_time; 1258 wm_high.interlaced = false; 1259 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1260 wm_high.interlaced = true; 1261 wm_high.vsc = amdgpu_crtc->vsc; 1262 wm_high.vtaps = 1; 1263 if (amdgpu_crtc->rmx_type != RMX_OFF) 1264 wm_high.vtaps = 2; 1265 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1266 wm_high.lb_size = lb_size; 1267 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1268 wm_high.num_heads = num_heads; 1269 1270 /* set for high clocks */ 1271 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); 1272 1273 /* possibly force display priority to high */ 1274 /* should really do this at mode validation time... */ 1275 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1276 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1277 !dce_v10_0_check_latency_hiding(&wm_high) || 1278 (adev->mode_info.disp_priority == 2)) { 1279 DRM_DEBUG_KMS("force priority to high\n"); 1280 } 1281 1282 /* watermark for low clocks */ 1283 if (adev->pm.dpm_enabled) { 1284 wm_low.yclk = 1285 amdgpu_dpm_get_mclk(adev, true) * 10; 1286 wm_low.sclk = 1287 amdgpu_dpm_get_sclk(adev, true) * 10; 1288 } else { 1289 wm_low.yclk = adev->pm.current_mclk * 10; 1290 wm_low.sclk = adev->pm.current_sclk * 10; 1291 } 1292 1293 wm_low.disp_clk = mode->clock; 1294 wm_low.src_width = mode->crtc_hdisplay; 1295 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1296 wm_low.blank_time = line_time - wm_low.active_time; 1297 wm_low.interlaced = false; 1298 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1299 wm_low.interlaced = true; 1300 wm_low.vsc = amdgpu_crtc->vsc; 1301 wm_low.vtaps = 1; 1302 if (amdgpu_crtc->rmx_type != RMX_OFF) 1303 wm_low.vtaps = 2; 1304 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1305 wm_low.lb_size = lb_size; 1306 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1307 wm_low.num_heads = num_heads; 1308 1309 /* set for low clocks */ 1310 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); 1311 1312 /* possibly force display priority to high */ 1313 /* should really do this at mode validation time... */ 1314 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1315 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1316 !dce_v10_0_check_latency_hiding(&wm_low) || 1317 (adev->mode_info.disp_priority == 2)) { 1318 DRM_DEBUG_KMS("force priority to high\n"); 1319 } 1320 } 1321 1322 /* select wm A */ 1323 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1324 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1325 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1326 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1327 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1328 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1329 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1330 /* select wm B */ 1331 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1332 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1333 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1334 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1335 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1336 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1337 /* restore original selection */ 1338 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1339 1340 /* save values for DPM */ 1341 amdgpu_crtc->line_time = line_time; 1342 amdgpu_crtc->wm_high = latency_watermark_a; 1343 amdgpu_crtc->wm_low = latency_watermark_b; 1344 } 1345 1346 /** 1347 * dce_v10_0_bandwidth_update - program display watermarks 1348 * 1349 * @adev: amdgpu_device pointer 1350 * 1351 * Calculate and program the display watermarks and line 1352 * buffer allocation (CIK). 1353 */ 1354 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1355 { 1356 struct drm_display_mode *mode = NULL; 1357 u32 num_heads = 0, lb_size; 1358 int i; 1359 1360 amdgpu_update_display_priority(adev); 1361 1362 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1363 if (adev->mode_info.crtcs[i]->base.enabled) 1364 num_heads++; 1365 } 1366 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1367 mode = &adev->mode_info.crtcs[i]->base.mode; 1368 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1369 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1370 lb_size, num_heads); 1371 } 1372 } 1373 1374 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1375 { 1376 int i; 1377 u32 offset, tmp; 1378 1379 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1380 offset = adev->mode_info.audio.pin[i].offset; 1381 tmp = RREG32_AUDIO_ENDPT(offset, 1382 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1383 if (((tmp & 1384 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1385 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1386 adev->mode_info.audio.pin[i].connected = false; 1387 else 1388 adev->mode_info.audio.pin[i].connected = true; 1389 } 1390 } 1391 1392 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1393 { 1394 int i; 1395 1396 dce_v10_0_audio_get_connected_pins(adev); 1397 1398 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1399 if (adev->mode_info.audio.pin[i].connected) 1400 return &adev->mode_info.audio.pin[i]; 1401 } 1402 DRM_ERROR("No connected audio pins found!\n"); 1403 return NULL; 1404 } 1405 1406 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1407 { 1408 struct amdgpu_device *adev = encoder->dev->dev_private; 1409 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1410 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1411 u32 tmp; 1412 1413 if (!dig || !dig->afmt || !dig->afmt->pin) 1414 return; 1415 1416 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1417 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1418 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1419 } 1420 1421 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1422 struct drm_display_mode *mode) 1423 { 1424 struct amdgpu_device *adev = encoder->dev->dev_private; 1425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1426 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1427 struct drm_connector *connector; 1428 struct amdgpu_connector *amdgpu_connector = NULL; 1429 u32 tmp; 1430 int interlace = 0; 1431 1432 if (!dig || !dig->afmt || !dig->afmt->pin) 1433 return; 1434 1435 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1436 if (connector->encoder == encoder) { 1437 amdgpu_connector = to_amdgpu_connector(connector); 1438 break; 1439 } 1440 } 1441 1442 if (!amdgpu_connector) { 1443 DRM_ERROR("Couldn't find encoder's connector\n"); 1444 return; 1445 } 1446 1447 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1448 interlace = 1; 1449 if (connector->latency_present[interlace]) { 1450 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1451 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1452 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1453 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1454 } else { 1455 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1456 VIDEO_LIPSYNC, 0); 1457 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1458 AUDIO_LIPSYNC, 0); 1459 } 1460 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1461 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1462 } 1463 1464 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1465 { 1466 struct amdgpu_device *adev = encoder->dev->dev_private; 1467 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1468 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1469 struct drm_connector *connector; 1470 struct amdgpu_connector *amdgpu_connector = NULL; 1471 u32 tmp; 1472 u8 *sadb = NULL; 1473 int sad_count; 1474 1475 if (!dig || !dig->afmt || !dig->afmt->pin) 1476 return; 1477 1478 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1479 if (connector->encoder == encoder) { 1480 amdgpu_connector = to_amdgpu_connector(connector); 1481 break; 1482 } 1483 } 1484 1485 if (!amdgpu_connector) { 1486 DRM_ERROR("Couldn't find encoder's connector\n"); 1487 return; 1488 } 1489 1490 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1491 if (sad_count < 0) { 1492 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1493 sad_count = 0; 1494 } 1495 1496 /* program the speaker allocation */ 1497 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1498 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1499 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1500 DP_CONNECTION, 0); 1501 /* set HDMI mode */ 1502 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1503 HDMI_CONNECTION, 1); 1504 if (sad_count) 1505 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1506 SPEAKER_ALLOCATION, sadb[0]); 1507 else 1508 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1509 SPEAKER_ALLOCATION, 5); /* stereo */ 1510 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1511 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1512 1513 kfree(sadb); 1514 } 1515 1516 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1517 { 1518 struct amdgpu_device *adev = encoder->dev->dev_private; 1519 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1520 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1521 struct drm_connector *connector; 1522 struct amdgpu_connector *amdgpu_connector = NULL; 1523 struct cea_sad *sads; 1524 int i, sad_count; 1525 1526 static const u16 eld_reg_to_type[][2] = { 1527 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1528 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1529 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1530 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1531 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1532 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1533 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1534 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1535 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1539 }; 1540 1541 if (!dig || !dig->afmt || !dig->afmt->pin) 1542 return; 1543 1544 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1545 if (connector->encoder == encoder) { 1546 amdgpu_connector = to_amdgpu_connector(connector); 1547 break; 1548 } 1549 } 1550 1551 if (!amdgpu_connector) { 1552 DRM_ERROR("Couldn't find encoder's connector\n"); 1553 return; 1554 } 1555 1556 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1557 if (sad_count <= 0) { 1558 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1559 return; 1560 } 1561 BUG_ON(!sads); 1562 1563 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1564 u32 tmp = 0; 1565 u8 stereo_freqs = 0; 1566 int max_channels = -1; 1567 int j; 1568 1569 for (j = 0; j < sad_count; j++) { 1570 struct cea_sad *sad = &sads[j]; 1571 1572 if (sad->format == eld_reg_to_type[i][1]) { 1573 if (sad->channels > max_channels) { 1574 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1575 MAX_CHANNELS, sad->channels); 1576 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1577 DESCRIPTOR_BYTE_2, sad->byte2); 1578 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1579 SUPPORTED_FREQUENCIES, sad->freq); 1580 max_channels = sad->channels; 1581 } 1582 1583 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1584 stereo_freqs |= sad->freq; 1585 else 1586 break; 1587 } 1588 } 1589 1590 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1591 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1592 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1593 } 1594 1595 kfree(sads); 1596 } 1597 1598 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1599 struct amdgpu_audio_pin *pin, 1600 bool enable) 1601 { 1602 if (!pin) 1603 return; 1604 1605 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1606 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1607 } 1608 1609 static const u32 pin_offsets[] = 1610 { 1611 AUD0_REGISTER_OFFSET, 1612 AUD1_REGISTER_OFFSET, 1613 AUD2_REGISTER_OFFSET, 1614 AUD3_REGISTER_OFFSET, 1615 AUD4_REGISTER_OFFSET, 1616 AUD5_REGISTER_OFFSET, 1617 AUD6_REGISTER_OFFSET, 1618 }; 1619 1620 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1621 { 1622 int i; 1623 1624 if (!amdgpu_audio) 1625 return 0; 1626 1627 adev->mode_info.audio.enabled = true; 1628 1629 adev->mode_info.audio.num_pins = 7; 1630 1631 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1632 adev->mode_info.audio.pin[i].channels = -1; 1633 adev->mode_info.audio.pin[i].rate = -1; 1634 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1635 adev->mode_info.audio.pin[i].status_bits = 0; 1636 adev->mode_info.audio.pin[i].category_code = 0; 1637 adev->mode_info.audio.pin[i].connected = false; 1638 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1639 adev->mode_info.audio.pin[i].id = i; 1640 /* disable audio. it will be set up later */ 1641 /* XXX remove once we switch to ip funcs */ 1642 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1649 { 1650 int i; 1651 1652 if (!adev->mode_info.audio.enabled) 1653 return; 1654 1655 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1656 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1657 1658 adev->mode_info.audio.enabled = false; 1659 } 1660 1661 /* 1662 * update the N and CTS parameters for a given pixel clock rate 1663 */ 1664 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1665 { 1666 struct drm_device *dev = encoder->dev; 1667 struct amdgpu_device *adev = dev->dev_private; 1668 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1669 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1670 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1671 u32 tmp; 1672 1673 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1674 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1675 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1676 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1677 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1678 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1679 1680 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1682 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1683 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1685 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1686 1687 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1689 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1690 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1692 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1693 1694 } 1695 1696 /* 1697 * build a HDMI Video Info Frame 1698 */ 1699 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1700 void *buffer, size_t size) 1701 { 1702 struct drm_device *dev = encoder->dev; 1703 struct amdgpu_device *adev = dev->dev_private; 1704 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1705 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1706 uint8_t *frame = buffer + 3; 1707 uint8_t *header = buffer; 1708 1709 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1710 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1711 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1712 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1713 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1714 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1715 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1716 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1717 } 1718 1719 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1720 { 1721 struct drm_device *dev = encoder->dev; 1722 struct amdgpu_device *adev = dev->dev_private; 1723 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1724 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1725 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1726 u32 dto_phase = 24 * 1000; 1727 u32 dto_modulo = clock; 1728 u32 tmp; 1729 1730 if (!dig || !dig->afmt) 1731 return; 1732 1733 /* XXX two dtos; generally use dto0 for hdmi */ 1734 /* Express [24MHz / target pixel clock] as an exact rational 1735 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1736 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1737 */ 1738 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1739 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1740 amdgpu_crtc->crtc_id); 1741 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1742 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1743 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1744 } 1745 1746 /* 1747 * update the info frames with the data from the current display mode 1748 */ 1749 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1750 struct drm_display_mode *mode) 1751 { 1752 struct drm_device *dev = encoder->dev; 1753 struct amdgpu_device *adev = dev->dev_private; 1754 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1755 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1756 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1757 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1758 struct hdmi_avi_infoframe frame; 1759 ssize_t err; 1760 u32 tmp; 1761 int bpc = 8; 1762 1763 if (!dig || !dig->afmt) 1764 return; 1765 1766 /* Silent, r600_hdmi_enable will raise WARN for us */ 1767 if (!dig->afmt->enabled) 1768 return; 1769 1770 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1771 if (encoder->crtc) { 1772 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1773 bpc = amdgpu_crtc->bpc; 1774 } 1775 1776 /* disable audio prior to setting up hw */ 1777 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1778 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1779 1780 dce_v10_0_audio_set_dto(encoder, mode->clock); 1781 1782 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1783 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1784 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1785 1786 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1787 1788 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1789 switch (bpc) { 1790 case 0: 1791 case 6: 1792 case 8: 1793 case 16: 1794 default: 1795 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1796 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1797 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1798 connector->name, bpc); 1799 break; 1800 case 10: 1801 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1802 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1803 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1804 connector->name); 1805 break; 1806 case 12: 1807 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1809 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1810 connector->name); 1811 break; 1812 } 1813 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1814 1815 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1816 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1817 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1818 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1819 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1820 1821 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1822 /* enable audio info frames (frames won't be set until audio is enabled) */ 1823 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1824 /* required for audio info values to be updated */ 1825 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1826 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1827 1828 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1829 /* required for audio info values to be updated */ 1830 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1831 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1832 1833 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1834 /* anything other than 0 */ 1835 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1836 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1837 1838 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1839 1840 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1841 /* set the default audio delay */ 1842 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1843 /* should be suffient for all audio modes and small enough for all hblanks */ 1844 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1845 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1846 1847 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1848 /* allow 60958 channel status fields to be updated */ 1849 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1850 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1851 1852 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1853 if (bpc > 8) 1854 /* clear SW CTS value */ 1855 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1856 else 1857 /* select SW CTS value */ 1858 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1859 /* allow hw to sent ACR packets when required */ 1860 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1861 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1862 1863 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1864 1865 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1866 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1867 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1868 1869 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1870 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1871 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1872 1873 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1874 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1875 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1876 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1877 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1879 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1880 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1881 1882 dce_v10_0_audio_write_speaker_allocation(encoder); 1883 1884 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1885 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1886 1887 dce_v10_0_afmt_audio_select_pin(encoder); 1888 dce_v10_0_audio_write_sad_regs(encoder); 1889 dce_v10_0_audio_write_latency_fields(encoder, mode); 1890 1891 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1892 if (err < 0) { 1893 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1894 return; 1895 } 1896 1897 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1898 if (err < 0) { 1899 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1900 return; 1901 } 1902 1903 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1904 1905 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1906 /* enable AVI info frames */ 1907 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1908 /* required for audio info values to be updated */ 1909 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1910 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1911 1912 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1913 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1914 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1915 1916 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1917 /* send audio packets */ 1918 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1919 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1920 1921 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1922 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1923 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1924 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1925 1926 /* enable audio after to setting up hw */ 1927 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 1928 } 1929 1930 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1931 { 1932 struct drm_device *dev = encoder->dev; 1933 struct amdgpu_device *adev = dev->dev_private; 1934 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1935 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1936 1937 if (!dig || !dig->afmt) 1938 return; 1939 1940 /* Silent, r600_hdmi_enable will raise WARN for us */ 1941 if (enable && dig->afmt->enabled) 1942 return; 1943 if (!enable && !dig->afmt->enabled) 1944 return; 1945 1946 if (!enable && dig->afmt->pin) { 1947 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1948 dig->afmt->pin = NULL; 1949 } 1950 1951 dig->afmt->enabled = enable; 1952 1953 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1954 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1955 } 1956 1957 static void dce_v10_0_afmt_init(struct amdgpu_device *adev) 1958 { 1959 int i; 1960 1961 for (i = 0; i < adev->mode_info.num_dig; i++) 1962 adev->mode_info.afmt[i] = NULL; 1963 1964 /* DCE10 has audio blocks tied to DIG encoders */ 1965 for (i = 0; i < adev->mode_info.num_dig; i++) { 1966 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1967 if (adev->mode_info.afmt[i]) { 1968 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1969 adev->mode_info.afmt[i]->id = i; 1970 } 1971 } 1972 } 1973 1974 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 1975 { 1976 int i; 1977 1978 for (i = 0; i < adev->mode_info.num_dig; i++) { 1979 kfree(adev->mode_info.afmt[i]); 1980 adev->mode_info.afmt[i] = NULL; 1981 } 1982 } 1983 1984 static const u32 vga_control_regs[6] = 1985 { 1986 mmD1VGA_CONTROL, 1987 mmD2VGA_CONTROL, 1988 mmD3VGA_CONTROL, 1989 mmD4VGA_CONTROL, 1990 mmD5VGA_CONTROL, 1991 mmD6VGA_CONTROL, 1992 }; 1993 1994 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 1995 { 1996 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1997 struct drm_device *dev = crtc->dev; 1998 struct amdgpu_device *adev = dev->dev_private; 1999 u32 vga_control; 2000 2001 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2002 if (enable) 2003 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2004 else 2005 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2006 } 2007 2008 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 2009 { 2010 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2011 struct drm_device *dev = crtc->dev; 2012 struct amdgpu_device *adev = dev->dev_private; 2013 2014 if (enable) 2015 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2016 else 2017 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2018 } 2019 2020 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 2021 struct drm_framebuffer *fb, 2022 int x, int y, int atomic) 2023 { 2024 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2025 struct drm_device *dev = crtc->dev; 2026 struct amdgpu_device *adev = dev->dev_private; 2027 struct amdgpu_framebuffer *amdgpu_fb; 2028 struct drm_framebuffer *target_fb; 2029 struct drm_gem_object *obj; 2030 struct amdgpu_bo *rbo; 2031 uint64_t fb_location, tiling_flags; 2032 uint32_t fb_format, fb_pitch_pixels; 2033 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2034 u32 pipe_config; 2035 u32 tmp, viewport_w, viewport_h; 2036 int r; 2037 bool bypass_lut = false; 2038 2039 /* no fb bound */ 2040 if (!atomic && !crtc->primary->fb) { 2041 DRM_DEBUG_KMS("No FB bound\n"); 2042 return 0; 2043 } 2044 2045 if (atomic) { 2046 amdgpu_fb = to_amdgpu_framebuffer(fb); 2047 target_fb = fb; 2048 } 2049 else { 2050 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2051 target_fb = crtc->primary->fb; 2052 } 2053 2054 /* If atomic, assume fb object is pinned & idle & fenced and 2055 * just update base pointers 2056 */ 2057 obj = amdgpu_fb->obj; 2058 rbo = gem_to_amdgpu_bo(obj); 2059 r = amdgpu_bo_reserve(rbo, false); 2060 if (unlikely(r != 0)) 2061 return r; 2062 2063 if (atomic) 2064 fb_location = amdgpu_bo_gpu_offset(rbo); 2065 else { 2066 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2067 if (unlikely(r != 0)) { 2068 amdgpu_bo_unreserve(rbo); 2069 return -EINVAL; 2070 } 2071 } 2072 2073 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2074 amdgpu_bo_unreserve(rbo); 2075 2076 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2077 2078 switch (target_fb->pixel_format) { 2079 case DRM_FORMAT_C8: 2080 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2081 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2082 break; 2083 case DRM_FORMAT_XRGB4444: 2084 case DRM_FORMAT_ARGB4444: 2085 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2086 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2087 #ifdef __BIG_ENDIAN 2088 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2089 ENDIAN_8IN16); 2090 #endif 2091 break; 2092 case DRM_FORMAT_XRGB1555: 2093 case DRM_FORMAT_ARGB1555: 2094 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2095 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2096 #ifdef __BIG_ENDIAN 2097 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2098 ENDIAN_8IN16); 2099 #endif 2100 break; 2101 case DRM_FORMAT_BGRX5551: 2102 case DRM_FORMAT_BGRA5551: 2103 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2104 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2105 #ifdef __BIG_ENDIAN 2106 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2107 ENDIAN_8IN16); 2108 #endif 2109 break; 2110 case DRM_FORMAT_RGB565: 2111 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2112 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2113 #ifdef __BIG_ENDIAN 2114 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2115 ENDIAN_8IN16); 2116 #endif 2117 break; 2118 case DRM_FORMAT_XRGB8888: 2119 case DRM_FORMAT_ARGB8888: 2120 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2121 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2122 #ifdef __BIG_ENDIAN 2123 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2124 ENDIAN_8IN32); 2125 #endif 2126 break; 2127 case DRM_FORMAT_XRGB2101010: 2128 case DRM_FORMAT_ARGB2101010: 2129 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2130 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2131 #ifdef __BIG_ENDIAN 2132 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2133 ENDIAN_8IN32); 2134 #endif 2135 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2136 bypass_lut = true; 2137 break; 2138 case DRM_FORMAT_BGRX1010102: 2139 case DRM_FORMAT_BGRA1010102: 2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2142 #ifdef __BIG_ENDIAN 2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2144 ENDIAN_8IN32); 2145 #endif 2146 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2147 bypass_lut = true; 2148 break; 2149 default: 2150 DRM_ERROR("Unsupported screen format %s\n", 2151 drm_get_format_name(target_fb->pixel_format)); 2152 return -EINVAL; 2153 } 2154 2155 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2156 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2157 2158 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2159 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2160 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2161 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2162 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2163 2164 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2165 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2166 ARRAY_2D_TILED_THIN1); 2167 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2168 tile_split); 2169 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2170 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2171 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2172 mtaspect); 2173 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2174 ADDR_SURF_MICRO_TILING_DISPLAY); 2175 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2176 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2177 ARRAY_1D_TILED_THIN1); 2178 } 2179 2180 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2181 pipe_config); 2182 2183 dce_v10_0_vga_enable(crtc, false); 2184 2185 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2186 upper_32_bits(fb_location)); 2187 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2188 upper_32_bits(fb_location)); 2189 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2190 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2191 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2192 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2193 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2194 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2195 2196 /* 2197 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2198 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2199 * retain the full precision throughout the pipeline. 2200 */ 2201 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2202 if (bypass_lut) 2203 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2204 else 2205 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2206 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2207 2208 if (bypass_lut) 2209 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2210 2211 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2212 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2213 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2214 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2215 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2216 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2217 2218 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2219 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2220 2221 dce_v10_0_grph_enable(crtc, true); 2222 2223 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2224 target_fb->height); 2225 2226 x &= ~3; 2227 y &= ~1; 2228 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2229 (x << 16) | y); 2230 viewport_w = crtc->mode.hdisplay; 2231 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2232 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2233 (viewport_w << 16) | viewport_h); 2234 2235 /* pageflip setup */ 2236 /* make sure flip is at vb rather than hb */ 2237 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2238 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2239 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2240 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2241 2242 /* set pageflip to happen only at start of vblank interval (front porch) */ 2243 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2244 2245 if (!atomic && fb && fb != crtc->primary->fb) { 2246 amdgpu_fb = to_amdgpu_framebuffer(fb); 2247 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2248 r = amdgpu_bo_reserve(rbo, false); 2249 if (unlikely(r != 0)) 2250 return r; 2251 amdgpu_bo_unpin(rbo); 2252 amdgpu_bo_unreserve(rbo); 2253 } 2254 2255 /* Bytes per pixel may have changed */ 2256 dce_v10_0_bandwidth_update(adev); 2257 2258 return 0; 2259 } 2260 2261 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2262 struct drm_display_mode *mode) 2263 { 2264 struct drm_device *dev = crtc->dev; 2265 struct amdgpu_device *adev = dev->dev_private; 2266 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2267 u32 tmp; 2268 2269 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2270 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2271 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2272 else 2273 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2274 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2275 } 2276 2277 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2278 { 2279 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2280 struct drm_device *dev = crtc->dev; 2281 struct amdgpu_device *adev = dev->dev_private; 2282 int i; 2283 u32 tmp; 2284 2285 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2286 2287 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2288 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2289 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2290 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2291 2292 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2293 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2294 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2295 2296 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2297 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2298 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2299 2300 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2301 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2302 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2303 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2304 2305 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2306 2307 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2308 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2309 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2310 2311 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2312 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2313 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2314 2315 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2316 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2317 2318 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2319 for (i = 0; i < 256; i++) { 2320 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2321 (amdgpu_crtc->lut_r[i] << 20) | 2322 (amdgpu_crtc->lut_g[i] << 10) | 2323 (amdgpu_crtc->lut_b[i] << 0)); 2324 } 2325 2326 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2327 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2328 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2329 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2330 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2331 2332 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2333 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2334 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2335 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2336 2337 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2338 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2339 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2340 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2341 2342 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2343 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2344 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2345 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2346 2347 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2348 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2349 /* XXX this only needs to be programmed once per crtc at startup, 2350 * not sure where the best place for it is 2351 */ 2352 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2353 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2354 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2355 } 2356 2357 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2358 { 2359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2360 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2361 2362 switch (amdgpu_encoder->encoder_id) { 2363 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2364 if (dig->linkb) 2365 return 1; 2366 else 2367 return 0; 2368 break; 2369 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2370 if (dig->linkb) 2371 return 3; 2372 else 2373 return 2; 2374 break; 2375 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2376 if (dig->linkb) 2377 return 5; 2378 else 2379 return 4; 2380 break; 2381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2382 return 6; 2383 break; 2384 default: 2385 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2386 return 0; 2387 } 2388 } 2389 2390 /** 2391 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2392 * 2393 * @crtc: drm crtc 2394 * 2395 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2396 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2397 * monitors a dedicated PPLL must be used. If a particular board has 2398 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2399 * as there is no need to program the PLL itself. If we are not able to 2400 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2401 * avoid messing up an existing monitor. 2402 * 2403 * Asic specific PLL information 2404 * 2405 * DCE 10.x 2406 * Tonga 2407 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2408 * CI 2409 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2410 * 2411 */ 2412 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2413 { 2414 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2415 struct drm_device *dev = crtc->dev; 2416 struct amdgpu_device *adev = dev->dev_private; 2417 u32 pll_in_use; 2418 int pll; 2419 2420 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2421 if (adev->clock.dp_extclk) 2422 /* skip PPLL programming if using ext clock */ 2423 return ATOM_PPLL_INVALID; 2424 else { 2425 /* use the same PPLL for all DP monitors */ 2426 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2427 if (pll != ATOM_PPLL_INVALID) 2428 return pll; 2429 } 2430 } else { 2431 /* use the same PPLL for all monitors with the same clock */ 2432 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2433 if (pll != ATOM_PPLL_INVALID) 2434 return pll; 2435 } 2436 2437 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2438 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2439 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2440 return ATOM_PPLL2; 2441 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2442 return ATOM_PPLL1; 2443 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2444 return ATOM_PPLL0; 2445 DRM_ERROR("unable to allocate a PPLL\n"); 2446 return ATOM_PPLL_INVALID; 2447 } 2448 2449 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2450 { 2451 struct amdgpu_device *adev = crtc->dev->dev_private; 2452 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2453 uint32_t cur_lock; 2454 2455 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2456 if (lock) 2457 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2458 else 2459 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2460 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2461 } 2462 2463 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2464 { 2465 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2466 struct amdgpu_device *adev = crtc->dev->dev_private; 2467 u32 tmp; 2468 2469 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2470 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2471 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2472 } 2473 2474 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2475 { 2476 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2477 struct amdgpu_device *adev = crtc->dev->dev_private; 2478 u32 tmp; 2479 2480 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2481 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2482 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2483 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2484 } 2485 2486 static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 2487 uint64_t gpu_addr) 2488 { 2489 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2490 struct amdgpu_device *adev = crtc->dev->dev_private; 2491 2492 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2493 upper_32_bits(gpu_addr)); 2494 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2495 lower_32_bits(gpu_addr)); 2496 } 2497 2498 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2499 int x, int y) 2500 { 2501 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2502 struct amdgpu_device *adev = crtc->dev->dev_private; 2503 int xorigin = 0, yorigin = 0; 2504 2505 /* avivo cursor are offset into the total surface */ 2506 x += crtc->x; 2507 y += crtc->y; 2508 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2509 2510 if (x < 0) { 2511 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2512 x = 0; 2513 } 2514 if (y < 0) { 2515 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2516 y = 0; 2517 } 2518 2519 dce_v10_0_lock_cursor(crtc, true); 2520 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2521 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2522 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2523 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2524 dce_v10_0_lock_cursor(crtc, false); 2525 2526 return 0; 2527 } 2528 2529 static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, 2530 struct drm_file *file_priv, 2531 uint32_t handle, 2532 uint32_t width, 2533 uint32_t height) 2534 { 2535 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2536 struct drm_gem_object *obj; 2537 struct amdgpu_bo *robj; 2538 uint64_t gpu_addr; 2539 int ret; 2540 2541 if (!handle) { 2542 /* turn off cursor */ 2543 dce_v10_0_hide_cursor(crtc); 2544 obj = NULL; 2545 goto unpin; 2546 } 2547 2548 if ((width > amdgpu_crtc->max_cursor_width) || 2549 (height > amdgpu_crtc->max_cursor_height)) { 2550 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2551 return -EINVAL; 2552 } 2553 2554 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2555 if (!obj) { 2556 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2557 return -ENOENT; 2558 } 2559 2560 robj = gem_to_amdgpu_bo(obj); 2561 ret = amdgpu_bo_reserve(robj, false); 2562 if (unlikely(ret != 0)) 2563 goto fail; 2564 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 2565 0, 0, &gpu_addr); 2566 amdgpu_bo_unreserve(robj); 2567 if (ret) 2568 goto fail; 2569 2570 amdgpu_crtc->cursor_width = width; 2571 amdgpu_crtc->cursor_height = height; 2572 2573 dce_v10_0_lock_cursor(crtc, true); 2574 dce_v10_0_set_cursor(crtc, obj, gpu_addr); 2575 dce_v10_0_show_cursor(crtc); 2576 dce_v10_0_lock_cursor(crtc, false); 2577 2578 unpin: 2579 if (amdgpu_crtc->cursor_bo) { 2580 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2581 ret = amdgpu_bo_reserve(robj, false); 2582 if (likely(ret == 0)) { 2583 amdgpu_bo_unpin(robj); 2584 amdgpu_bo_unreserve(robj); 2585 } 2586 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2587 } 2588 2589 amdgpu_crtc->cursor_bo = obj; 2590 return 0; 2591 fail: 2592 drm_gem_object_unreference_unlocked(obj); 2593 2594 return ret; 2595 } 2596 2597 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2598 u16 *blue, uint32_t start, uint32_t size) 2599 { 2600 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2601 int end = (start + size > 256) ? 256 : start + size, i; 2602 2603 /* userspace palettes are always correct as is */ 2604 for (i = start; i < end; i++) { 2605 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2606 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2607 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2608 } 2609 dce_v10_0_crtc_load_lut(crtc); 2610 } 2611 2612 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2613 { 2614 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2615 2616 drm_crtc_cleanup(crtc); 2617 destroy_workqueue(amdgpu_crtc->pflip_queue); 2618 kfree(amdgpu_crtc); 2619 } 2620 2621 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2622 .cursor_set = dce_v10_0_crtc_cursor_set, 2623 .cursor_move = dce_v10_0_crtc_cursor_move, 2624 .gamma_set = dce_v10_0_crtc_gamma_set, 2625 .set_config = amdgpu_crtc_set_config, 2626 .destroy = dce_v10_0_crtc_destroy, 2627 .page_flip = amdgpu_crtc_page_flip, 2628 }; 2629 2630 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2631 { 2632 struct drm_device *dev = crtc->dev; 2633 struct amdgpu_device *adev = dev->dev_private; 2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2635 unsigned type; 2636 2637 switch (mode) { 2638 case DRM_MODE_DPMS_ON: 2639 amdgpu_crtc->enabled = true; 2640 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2641 dce_v10_0_vga_enable(crtc, true); 2642 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2643 dce_v10_0_vga_enable(crtc, false); 2644 /* Make sure VBLANK interrupt is still enabled */ 2645 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2646 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2647 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2648 dce_v10_0_crtc_load_lut(crtc); 2649 break; 2650 case DRM_MODE_DPMS_STANDBY: 2651 case DRM_MODE_DPMS_SUSPEND: 2652 case DRM_MODE_DPMS_OFF: 2653 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); 2654 if (amdgpu_crtc->enabled) { 2655 dce_v10_0_vga_enable(crtc, true); 2656 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2657 dce_v10_0_vga_enable(crtc, false); 2658 } 2659 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2660 amdgpu_crtc->enabled = false; 2661 break; 2662 } 2663 /* adjust pm to dpms */ 2664 amdgpu_pm_compute_clocks(adev); 2665 } 2666 2667 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2668 { 2669 /* disable crtc pair power gating before programming */ 2670 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2671 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2672 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2673 } 2674 2675 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2676 { 2677 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2678 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2679 } 2680 2681 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2682 { 2683 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2684 struct drm_device *dev = crtc->dev; 2685 struct amdgpu_device *adev = dev->dev_private; 2686 struct amdgpu_atom_ss ss; 2687 int i; 2688 2689 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2690 if (crtc->primary->fb) { 2691 int r; 2692 struct amdgpu_framebuffer *amdgpu_fb; 2693 struct amdgpu_bo *rbo; 2694 2695 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2696 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2697 r = amdgpu_bo_reserve(rbo, false); 2698 if (unlikely(r)) 2699 DRM_ERROR("failed to reserve rbo before unpin\n"); 2700 else { 2701 amdgpu_bo_unpin(rbo); 2702 amdgpu_bo_unreserve(rbo); 2703 } 2704 } 2705 /* disable the GRPH */ 2706 dce_v10_0_grph_enable(crtc, false); 2707 2708 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2709 2710 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2711 if (adev->mode_info.crtcs[i] && 2712 adev->mode_info.crtcs[i]->enabled && 2713 i != amdgpu_crtc->crtc_id && 2714 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2715 /* one other crtc is using this pll don't turn 2716 * off the pll 2717 */ 2718 goto done; 2719 } 2720 } 2721 2722 switch (amdgpu_crtc->pll_id) { 2723 case ATOM_PPLL0: 2724 case ATOM_PPLL1: 2725 case ATOM_PPLL2: 2726 /* disable the ppll */ 2727 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2728 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2729 break; 2730 default: 2731 break; 2732 } 2733 done: 2734 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2735 amdgpu_crtc->adjusted_clock = 0; 2736 amdgpu_crtc->encoder = NULL; 2737 amdgpu_crtc->connector = NULL; 2738 } 2739 2740 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2741 struct drm_display_mode *mode, 2742 struct drm_display_mode *adjusted_mode, 2743 int x, int y, struct drm_framebuffer *old_fb) 2744 { 2745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2746 2747 if (!amdgpu_crtc->adjusted_clock) 2748 return -EINVAL; 2749 2750 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2751 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2752 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2753 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2754 amdgpu_atombios_crtc_scaler_setup(crtc); 2755 /* update the hw version fpr dpm */ 2756 amdgpu_crtc->hw_mode = *adjusted_mode; 2757 2758 return 0; 2759 } 2760 2761 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2762 const struct drm_display_mode *mode, 2763 struct drm_display_mode *adjusted_mode) 2764 { 2765 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2766 struct drm_device *dev = crtc->dev; 2767 struct drm_encoder *encoder; 2768 2769 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2771 if (encoder->crtc == crtc) { 2772 amdgpu_crtc->encoder = encoder; 2773 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2774 break; 2775 } 2776 } 2777 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2778 amdgpu_crtc->encoder = NULL; 2779 amdgpu_crtc->connector = NULL; 2780 return false; 2781 } 2782 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2783 return false; 2784 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2785 return false; 2786 /* pick pll */ 2787 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2788 /* if we can't get a PPLL for a non-DP encoder, fail */ 2789 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2790 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2791 return false; 2792 2793 return true; 2794 } 2795 2796 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2797 struct drm_framebuffer *old_fb) 2798 { 2799 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2800 } 2801 2802 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2803 struct drm_framebuffer *fb, 2804 int x, int y, enum mode_set_atomic state) 2805 { 2806 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); 2807 } 2808 2809 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2810 .dpms = dce_v10_0_crtc_dpms, 2811 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2812 .mode_set = dce_v10_0_crtc_mode_set, 2813 .mode_set_base = dce_v10_0_crtc_set_base, 2814 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, 2815 .prepare = dce_v10_0_crtc_prepare, 2816 .commit = dce_v10_0_crtc_commit, 2817 .load_lut = dce_v10_0_crtc_load_lut, 2818 .disable = dce_v10_0_crtc_disable, 2819 }; 2820 2821 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2822 { 2823 struct amdgpu_crtc *amdgpu_crtc; 2824 int i; 2825 2826 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2827 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2828 if (amdgpu_crtc == NULL) 2829 return -ENOMEM; 2830 2831 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2832 2833 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2834 amdgpu_crtc->crtc_id = index; 2835 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); 2836 adev->mode_info.crtcs[index] = amdgpu_crtc; 2837 2838 amdgpu_crtc->max_cursor_width = 128; 2839 amdgpu_crtc->max_cursor_height = 128; 2840 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2841 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2842 2843 for (i = 0; i < 256; i++) { 2844 amdgpu_crtc->lut_r[i] = i << 2; 2845 amdgpu_crtc->lut_g[i] = i << 2; 2846 amdgpu_crtc->lut_b[i] = i << 2; 2847 } 2848 2849 switch (amdgpu_crtc->crtc_id) { 2850 case 0: 2851 default: 2852 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2853 break; 2854 case 1: 2855 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2856 break; 2857 case 2: 2858 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2859 break; 2860 case 3: 2861 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2862 break; 2863 case 4: 2864 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2865 break; 2866 case 5: 2867 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2868 break; 2869 } 2870 2871 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2872 amdgpu_crtc->adjusted_clock = 0; 2873 amdgpu_crtc->encoder = NULL; 2874 amdgpu_crtc->connector = NULL; 2875 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2876 2877 return 0; 2878 } 2879 2880 static int dce_v10_0_early_init(void *handle) 2881 { 2882 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2883 2884 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2885 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2886 2887 dce_v10_0_set_display_funcs(adev); 2888 dce_v10_0_set_irq_funcs(adev); 2889 2890 switch (adev->asic_type) { 2891 case CHIP_TONGA: 2892 adev->mode_info.num_crtc = 6; /* XXX 7??? */ 2893 adev->mode_info.num_hpd = 6; 2894 adev->mode_info.num_dig = 7; 2895 break; 2896 default: 2897 /* FIXME: not supported yet */ 2898 return -EINVAL; 2899 } 2900 2901 return 0; 2902 } 2903 2904 static int dce_v10_0_sw_init(void *handle) 2905 { 2906 int r, i; 2907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2908 2909 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2910 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2911 if (r) 2912 return r; 2913 } 2914 2915 for (i = 8; i < 20; i += 2) { 2916 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2917 if (r) 2918 return r; 2919 } 2920 2921 /* HPD hotplug */ 2922 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2923 if (r) 2924 return r; 2925 2926 adev->mode_info.mode_config_initialized = true; 2927 2928 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2929 2930 adev->ddev->mode_config.max_width = 16384; 2931 adev->ddev->mode_config.max_height = 16384; 2932 2933 adev->ddev->mode_config.preferred_depth = 24; 2934 adev->ddev->mode_config.prefer_shadow = 1; 2935 2936 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2937 2938 r = amdgpu_modeset_create_props(adev); 2939 if (r) 2940 return r; 2941 2942 adev->ddev->mode_config.max_width = 16384; 2943 adev->ddev->mode_config.max_height = 16384; 2944 2945 /* allocate crtcs */ 2946 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2947 r = dce_v10_0_crtc_init(adev, i); 2948 if (r) 2949 return r; 2950 } 2951 2952 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2953 amdgpu_print_display_setup(adev->ddev); 2954 else 2955 return -EINVAL; 2956 2957 /* setup afmt */ 2958 dce_v10_0_afmt_init(adev); 2959 2960 r = dce_v10_0_audio_init(adev); 2961 if (r) 2962 return r; 2963 2964 drm_kms_helper_poll_init(adev->ddev); 2965 2966 return r; 2967 } 2968 2969 static int dce_v10_0_sw_fini(void *handle) 2970 { 2971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2972 2973 kfree(adev->mode_info.bios_hardcoded_edid); 2974 2975 drm_kms_helper_poll_fini(adev->ddev); 2976 2977 dce_v10_0_audio_fini(adev); 2978 2979 dce_v10_0_afmt_fini(adev); 2980 2981 drm_mode_config_cleanup(adev->ddev); 2982 adev->mode_info.mode_config_initialized = false; 2983 2984 return 0; 2985 } 2986 2987 static int dce_v10_0_hw_init(void *handle) 2988 { 2989 int i; 2990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2991 2992 dce_v10_0_init_golden_registers(adev); 2993 2994 /* init dig PHYs, disp eng pll */ 2995 amdgpu_atombios_encoder_init_dig(adev); 2996 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2997 2998 /* initialize hpd */ 2999 dce_v10_0_hpd_init(adev); 3000 3001 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3002 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3003 } 3004 3005 return 0; 3006 } 3007 3008 static int dce_v10_0_hw_fini(void *handle) 3009 { 3010 int i; 3011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3012 3013 dce_v10_0_hpd_fini(adev); 3014 3015 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3016 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3017 } 3018 3019 return 0; 3020 } 3021 3022 static int dce_v10_0_suspend(void *handle) 3023 { 3024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3025 3026 amdgpu_atombios_scratch_regs_save(adev); 3027 3028 dce_v10_0_hpd_fini(adev); 3029 3030 return 0; 3031 } 3032 3033 static int dce_v10_0_resume(void *handle) 3034 { 3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3036 3037 dce_v10_0_init_golden_registers(adev); 3038 3039 amdgpu_atombios_scratch_regs_restore(adev); 3040 3041 /* init dig PHYs, disp eng pll */ 3042 amdgpu_atombios_encoder_init_dig(adev); 3043 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3044 /* turn on the BL */ 3045 if (adev->mode_info.bl_encoder) { 3046 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3047 adev->mode_info.bl_encoder); 3048 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3049 bl_level); 3050 } 3051 3052 /* initialize hpd */ 3053 dce_v10_0_hpd_init(adev); 3054 3055 return 0; 3056 } 3057 3058 static bool dce_v10_0_is_idle(void *handle) 3059 { 3060 return true; 3061 } 3062 3063 static int dce_v10_0_wait_for_idle(void *handle) 3064 { 3065 return 0; 3066 } 3067 3068 static void dce_v10_0_print_status(void *handle) 3069 { 3070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3071 3072 dev_info(adev->dev, "DCE 10.x registers\n"); 3073 /* XXX todo */ 3074 } 3075 3076 static int dce_v10_0_soft_reset(void *handle) 3077 { 3078 u32 srbm_soft_reset = 0, tmp; 3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3080 3081 if (dce_v10_0_is_display_hung(adev)) 3082 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3083 3084 if (srbm_soft_reset) { 3085 dce_v10_0_print_status((void *)adev); 3086 3087 tmp = RREG32(mmSRBM_SOFT_RESET); 3088 tmp |= srbm_soft_reset; 3089 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3090 WREG32(mmSRBM_SOFT_RESET, tmp); 3091 tmp = RREG32(mmSRBM_SOFT_RESET); 3092 3093 udelay(50); 3094 3095 tmp &= ~srbm_soft_reset; 3096 WREG32(mmSRBM_SOFT_RESET, tmp); 3097 tmp = RREG32(mmSRBM_SOFT_RESET); 3098 3099 /* Wait a little for things to settle down */ 3100 udelay(50); 3101 dce_v10_0_print_status((void *)adev); 3102 } 3103 return 0; 3104 } 3105 3106 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3107 int crtc, 3108 enum amdgpu_interrupt_state state) 3109 { 3110 u32 lb_interrupt_mask; 3111 3112 if (crtc >= adev->mode_info.num_crtc) { 3113 DRM_DEBUG("invalid crtc %d\n", crtc); 3114 return; 3115 } 3116 3117 switch (state) { 3118 case AMDGPU_IRQ_STATE_DISABLE: 3119 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3120 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3121 VBLANK_INTERRUPT_MASK, 0); 3122 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3123 break; 3124 case AMDGPU_IRQ_STATE_ENABLE: 3125 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3126 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3127 VBLANK_INTERRUPT_MASK, 1); 3128 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3129 break; 3130 default: 3131 break; 3132 } 3133 } 3134 3135 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3136 int crtc, 3137 enum amdgpu_interrupt_state state) 3138 { 3139 u32 lb_interrupt_mask; 3140 3141 if (crtc >= adev->mode_info.num_crtc) { 3142 DRM_DEBUG("invalid crtc %d\n", crtc); 3143 return; 3144 } 3145 3146 switch (state) { 3147 case AMDGPU_IRQ_STATE_DISABLE: 3148 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3149 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3150 VLINE_INTERRUPT_MASK, 0); 3151 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3152 break; 3153 case AMDGPU_IRQ_STATE_ENABLE: 3154 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3155 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3156 VLINE_INTERRUPT_MASK, 1); 3157 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3158 break; 3159 default: 3160 break; 3161 } 3162 } 3163 3164 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 3165 struct amdgpu_irq_src *source, 3166 unsigned hpd, 3167 enum amdgpu_interrupt_state state) 3168 { 3169 u32 tmp; 3170 3171 if (hpd >= adev->mode_info.num_hpd) { 3172 DRM_DEBUG("invalid hdp %d\n", hpd); 3173 return 0; 3174 } 3175 3176 switch (state) { 3177 case AMDGPU_IRQ_STATE_DISABLE: 3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3179 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3181 break; 3182 case AMDGPU_IRQ_STATE_ENABLE: 3183 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3184 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3185 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 return 0; 3192 } 3193 3194 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3195 struct amdgpu_irq_src *source, 3196 unsigned type, 3197 enum amdgpu_interrupt_state state) 3198 { 3199 switch (type) { 3200 case AMDGPU_CRTC_IRQ_VBLANK1: 3201 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3202 break; 3203 case AMDGPU_CRTC_IRQ_VBLANK2: 3204 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3205 break; 3206 case AMDGPU_CRTC_IRQ_VBLANK3: 3207 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3208 break; 3209 case AMDGPU_CRTC_IRQ_VBLANK4: 3210 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3211 break; 3212 case AMDGPU_CRTC_IRQ_VBLANK5: 3213 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3214 break; 3215 case AMDGPU_CRTC_IRQ_VBLANK6: 3216 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3217 break; 3218 case AMDGPU_CRTC_IRQ_VLINE1: 3219 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3220 break; 3221 case AMDGPU_CRTC_IRQ_VLINE2: 3222 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3223 break; 3224 case AMDGPU_CRTC_IRQ_VLINE3: 3225 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3226 break; 3227 case AMDGPU_CRTC_IRQ_VLINE4: 3228 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3229 break; 3230 case AMDGPU_CRTC_IRQ_VLINE5: 3231 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3232 break; 3233 case AMDGPU_CRTC_IRQ_VLINE6: 3234 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3235 break; 3236 default: 3237 break; 3238 } 3239 return 0; 3240 } 3241 3242 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3243 struct amdgpu_irq_src *src, 3244 unsigned type, 3245 enum amdgpu_interrupt_state state) 3246 { 3247 u32 reg, reg_block; 3248 /* now deal with page flip IRQ */ 3249 switch (type) { 3250 case AMDGPU_PAGEFLIP_IRQ_D1: 3251 reg_block = CRTC0_REGISTER_OFFSET; 3252 break; 3253 case AMDGPU_PAGEFLIP_IRQ_D2: 3254 reg_block = CRTC1_REGISTER_OFFSET; 3255 break; 3256 case AMDGPU_PAGEFLIP_IRQ_D3: 3257 reg_block = CRTC2_REGISTER_OFFSET; 3258 break; 3259 case AMDGPU_PAGEFLIP_IRQ_D4: 3260 reg_block = CRTC3_REGISTER_OFFSET; 3261 break; 3262 case AMDGPU_PAGEFLIP_IRQ_D5: 3263 reg_block = CRTC4_REGISTER_OFFSET; 3264 break; 3265 case AMDGPU_PAGEFLIP_IRQ_D6: 3266 reg_block = CRTC5_REGISTER_OFFSET; 3267 break; 3268 default: 3269 DRM_ERROR("invalid pageflip crtc %d\n", type); 3270 return -EINVAL; 3271 } 3272 3273 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); 3274 if (state == AMDGPU_IRQ_STATE_DISABLE) 3275 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3276 else 3277 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3278 3279 return 0; 3280 } 3281 3282 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3283 struct amdgpu_irq_src *source, 3284 struct amdgpu_iv_entry *entry) 3285 { 3286 int reg_block; 3287 unsigned long flags; 3288 unsigned crtc_id; 3289 struct amdgpu_crtc *amdgpu_crtc; 3290 struct amdgpu_flip_work *works; 3291 3292 crtc_id = (entry->src_id - 8) >> 1; 3293 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3294 3295 /* ack the interrupt */ 3296 switch(crtc_id){ 3297 case AMDGPU_PAGEFLIP_IRQ_D1: 3298 reg_block = CRTC0_REGISTER_OFFSET; 3299 break; 3300 case AMDGPU_PAGEFLIP_IRQ_D2: 3301 reg_block = CRTC1_REGISTER_OFFSET; 3302 break; 3303 case AMDGPU_PAGEFLIP_IRQ_D3: 3304 reg_block = CRTC2_REGISTER_OFFSET; 3305 break; 3306 case AMDGPU_PAGEFLIP_IRQ_D4: 3307 reg_block = CRTC3_REGISTER_OFFSET; 3308 break; 3309 case AMDGPU_PAGEFLIP_IRQ_D5: 3310 reg_block = CRTC4_REGISTER_OFFSET; 3311 break; 3312 case AMDGPU_PAGEFLIP_IRQ_D6: 3313 reg_block = CRTC5_REGISTER_OFFSET; 3314 break; 3315 default: 3316 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3317 return -EINVAL; 3318 } 3319 3320 if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3321 WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3322 3323 /* IRQ could occur when in initial stage */ 3324 if (amdgpu_crtc == NULL) 3325 return 0; 3326 3327 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3328 works = amdgpu_crtc->pflip_works; 3329 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3330 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3331 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3332 amdgpu_crtc->pflip_status, 3333 AMDGPU_FLIP_SUBMITTED); 3334 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3335 return 0; 3336 } 3337 3338 /* page flip completed. clean up */ 3339 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3340 amdgpu_crtc->pflip_works = NULL; 3341 3342 /* wakeup usersapce */ 3343 if (works->event) 3344 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3345 3346 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3347 3348 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3349 amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); 3350 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3351 3352 return 0; 3353 } 3354 3355 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3356 int hpd) 3357 { 3358 u32 tmp; 3359 3360 if (hpd >= adev->mode_info.num_hpd) { 3361 DRM_DEBUG("invalid hdp %d\n", hpd); 3362 return; 3363 } 3364 3365 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3366 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3367 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3368 } 3369 3370 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3371 int crtc) 3372 { 3373 u32 tmp; 3374 3375 if (crtc >= adev->mode_info.num_crtc) { 3376 DRM_DEBUG("invalid crtc %d\n", crtc); 3377 return; 3378 } 3379 3380 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3381 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3382 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3383 } 3384 3385 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3386 int crtc) 3387 { 3388 u32 tmp; 3389 3390 if (crtc >= adev->mode_info.num_crtc) { 3391 DRM_DEBUG("invalid crtc %d\n", crtc); 3392 return; 3393 } 3394 3395 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3396 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3397 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3398 } 3399 3400 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3401 struct amdgpu_irq_src *source, 3402 struct amdgpu_iv_entry *entry) 3403 { 3404 unsigned crtc = entry->src_id - 1; 3405 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3406 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3407 3408 switch (entry->src_data) { 3409 case 0: /* vblank */ 3410 if (disp_int & interrupt_status_offsets[crtc].vblank) 3411 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3412 else 3413 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3414 3415 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3416 drm_handle_vblank(adev->ddev, crtc); 3417 } 3418 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3419 3420 break; 3421 case 1: /* vline */ 3422 if (disp_int & interrupt_status_offsets[crtc].vline) 3423 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3424 else 3425 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3426 3427 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3428 3429 break; 3430 default: 3431 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3432 break; 3433 } 3434 3435 return 0; 3436 } 3437 3438 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3439 struct amdgpu_irq_src *source, 3440 struct amdgpu_iv_entry *entry) 3441 { 3442 uint32_t disp_int, mask; 3443 unsigned hpd; 3444 3445 if (entry->src_data >= adev->mode_info.num_hpd) { 3446 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3447 return 0; 3448 } 3449 3450 hpd = entry->src_data; 3451 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3452 mask = interrupt_status_offsets[hpd].hpd; 3453 3454 if (disp_int & mask) { 3455 dce_v10_0_hpd_int_ack(adev, hpd); 3456 schedule_work(&adev->hotplug_work); 3457 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3458 } 3459 3460 return 0; 3461 } 3462 3463 static int dce_v10_0_set_clockgating_state(void *handle, 3464 enum amd_clockgating_state state) 3465 { 3466 return 0; 3467 } 3468 3469 static int dce_v10_0_set_powergating_state(void *handle, 3470 enum amd_powergating_state state) 3471 { 3472 return 0; 3473 } 3474 3475 const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3476 .early_init = dce_v10_0_early_init, 3477 .late_init = NULL, 3478 .sw_init = dce_v10_0_sw_init, 3479 .sw_fini = dce_v10_0_sw_fini, 3480 .hw_init = dce_v10_0_hw_init, 3481 .hw_fini = dce_v10_0_hw_fini, 3482 .suspend = dce_v10_0_suspend, 3483 .resume = dce_v10_0_resume, 3484 .is_idle = dce_v10_0_is_idle, 3485 .wait_for_idle = dce_v10_0_wait_for_idle, 3486 .soft_reset = dce_v10_0_soft_reset, 3487 .print_status = dce_v10_0_print_status, 3488 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3489 .set_powergating_state = dce_v10_0_set_powergating_state, 3490 }; 3491 3492 static void 3493 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3494 struct drm_display_mode *mode, 3495 struct drm_display_mode *adjusted_mode) 3496 { 3497 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3498 3499 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3500 3501 /* need to call this here rather than in prepare() since we need some crtc info */ 3502 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3503 3504 /* set scaler clears this on some chips */ 3505 dce_v10_0_set_interleave(encoder->crtc, mode); 3506 3507 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3508 dce_v10_0_afmt_enable(encoder, true); 3509 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3510 } 3511 } 3512 3513 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3514 { 3515 struct amdgpu_device *adev = encoder->dev->dev_private; 3516 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3517 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3518 3519 if ((amdgpu_encoder->active_device & 3520 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3521 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3522 ENCODER_OBJECT_ID_NONE)) { 3523 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3524 if (dig) { 3525 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3526 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3527 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3528 } 3529 } 3530 3531 amdgpu_atombios_scratch_regs_lock(adev, true); 3532 3533 if (connector) { 3534 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3535 3536 /* select the clock/data port if it uses a router */ 3537 if (amdgpu_connector->router.cd_valid) 3538 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3539 3540 /* turn eDP panel on for mode set */ 3541 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3542 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3543 ATOM_TRANSMITTER_ACTION_POWER_ON); 3544 } 3545 3546 /* this is needed for the pll/ss setup to work correctly in some cases */ 3547 amdgpu_atombios_encoder_set_crtc_source(encoder); 3548 /* set up the FMT blocks */ 3549 dce_v10_0_program_fmt(encoder); 3550 } 3551 3552 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3553 { 3554 struct drm_device *dev = encoder->dev; 3555 struct amdgpu_device *adev = dev->dev_private; 3556 3557 /* need to call this here as we need the crtc set up */ 3558 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3559 amdgpu_atombios_scratch_regs_lock(adev, false); 3560 } 3561 3562 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3563 { 3564 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3565 struct amdgpu_encoder_atom_dig *dig; 3566 3567 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3568 3569 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3570 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3571 dce_v10_0_afmt_enable(encoder, false); 3572 dig = amdgpu_encoder->enc_priv; 3573 dig->dig_encoder = -1; 3574 } 3575 amdgpu_encoder->active_device = 0; 3576 } 3577 3578 /* these are handled by the primary encoders */ 3579 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3580 { 3581 3582 } 3583 3584 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3585 { 3586 3587 } 3588 3589 static void 3590 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3591 struct drm_display_mode *mode, 3592 struct drm_display_mode *adjusted_mode) 3593 { 3594 3595 } 3596 3597 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3598 { 3599 3600 } 3601 3602 static void 3603 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3604 { 3605 3606 } 3607 3608 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder, 3609 const struct drm_display_mode *mode, 3610 struct drm_display_mode *adjusted_mode) 3611 { 3612 return true; 3613 } 3614 3615 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3616 .dpms = dce_v10_0_ext_dpms, 3617 .mode_fixup = dce_v10_0_ext_mode_fixup, 3618 .prepare = dce_v10_0_ext_prepare, 3619 .mode_set = dce_v10_0_ext_mode_set, 3620 .commit = dce_v10_0_ext_commit, 3621 .disable = dce_v10_0_ext_disable, 3622 /* no detect for TMDS/LVDS yet */ 3623 }; 3624 3625 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3626 .dpms = amdgpu_atombios_encoder_dpms, 3627 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3628 .prepare = dce_v10_0_encoder_prepare, 3629 .mode_set = dce_v10_0_encoder_mode_set, 3630 .commit = dce_v10_0_encoder_commit, 3631 .disable = dce_v10_0_encoder_disable, 3632 .detect = amdgpu_atombios_encoder_dig_detect, 3633 }; 3634 3635 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3636 .dpms = amdgpu_atombios_encoder_dpms, 3637 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3638 .prepare = dce_v10_0_encoder_prepare, 3639 .mode_set = dce_v10_0_encoder_mode_set, 3640 .commit = dce_v10_0_encoder_commit, 3641 .detect = amdgpu_atombios_encoder_dac_detect, 3642 }; 3643 3644 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3645 { 3646 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3647 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3648 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3649 kfree(amdgpu_encoder->enc_priv); 3650 drm_encoder_cleanup(encoder); 3651 kfree(amdgpu_encoder); 3652 } 3653 3654 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3655 .destroy = dce_v10_0_encoder_destroy, 3656 }; 3657 3658 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3659 uint32_t encoder_enum, 3660 uint32_t supported_device, 3661 u16 caps) 3662 { 3663 struct drm_device *dev = adev->ddev; 3664 struct drm_encoder *encoder; 3665 struct amdgpu_encoder *amdgpu_encoder; 3666 3667 /* see if we already added it */ 3668 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3669 amdgpu_encoder = to_amdgpu_encoder(encoder); 3670 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3671 amdgpu_encoder->devices |= supported_device; 3672 return; 3673 } 3674 3675 } 3676 3677 /* add a new one */ 3678 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3679 if (!amdgpu_encoder) 3680 return; 3681 3682 encoder = &amdgpu_encoder->base; 3683 switch (adev->mode_info.num_crtc) { 3684 case 1: 3685 encoder->possible_crtcs = 0x1; 3686 break; 3687 case 2: 3688 default: 3689 encoder->possible_crtcs = 0x3; 3690 break; 3691 case 4: 3692 encoder->possible_crtcs = 0xf; 3693 break; 3694 case 6: 3695 encoder->possible_crtcs = 0x3f; 3696 break; 3697 } 3698 3699 amdgpu_encoder->enc_priv = NULL; 3700 3701 amdgpu_encoder->encoder_enum = encoder_enum; 3702 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3703 amdgpu_encoder->devices = supported_device; 3704 amdgpu_encoder->rmx_type = RMX_OFF; 3705 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3706 amdgpu_encoder->is_ext_encoder = false; 3707 amdgpu_encoder->caps = caps; 3708 3709 switch (amdgpu_encoder->encoder_id) { 3710 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3711 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3712 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3713 DRM_MODE_ENCODER_DAC); 3714 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3715 break; 3716 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3717 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3718 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3719 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3720 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3721 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3722 amdgpu_encoder->rmx_type = RMX_FULL; 3723 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3724 DRM_MODE_ENCODER_LVDS); 3725 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3726 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3727 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3728 DRM_MODE_ENCODER_DAC); 3729 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3730 } else { 3731 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3732 DRM_MODE_ENCODER_TMDS); 3733 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3734 } 3735 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3736 break; 3737 case ENCODER_OBJECT_ID_SI170B: 3738 case ENCODER_OBJECT_ID_CH7303: 3739 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3740 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3741 case ENCODER_OBJECT_ID_TITFP513: 3742 case ENCODER_OBJECT_ID_VT1623: 3743 case ENCODER_OBJECT_ID_HDMI_SI1930: 3744 case ENCODER_OBJECT_ID_TRAVIS: 3745 case ENCODER_OBJECT_ID_NUTMEG: 3746 /* these are handled by the primary encoders */ 3747 amdgpu_encoder->is_ext_encoder = true; 3748 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3749 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3750 DRM_MODE_ENCODER_LVDS); 3751 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3752 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3753 DRM_MODE_ENCODER_DAC); 3754 else 3755 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3756 DRM_MODE_ENCODER_TMDS); 3757 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3758 break; 3759 } 3760 } 3761 3762 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3763 .set_vga_render_state = &dce_v10_0_set_vga_render_state, 3764 .bandwidth_update = &dce_v10_0_bandwidth_update, 3765 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3766 .vblank_wait = &dce_v10_0_vblank_wait, 3767 .is_display_hung = &dce_v10_0_is_display_hung, 3768 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3769 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3770 .hpd_sense = &dce_v10_0_hpd_sense, 3771 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3772 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3773 .page_flip = &dce_v10_0_page_flip, 3774 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3775 .add_encoder = &dce_v10_0_encoder_add, 3776 .add_connector = &amdgpu_connector_add, 3777 .stop_mc_access = &dce_v10_0_stop_mc_access, 3778 .resume_mc_access = &dce_v10_0_resume_mc_access, 3779 }; 3780 3781 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3782 { 3783 if (adev->mode_info.funcs == NULL) 3784 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3785 } 3786 3787 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3788 .set = dce_v10_0_set_crtc_irq_state, 3789 .process = dce_v10_0_crtc_irq, 3790 }; 3791 3792 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3793 .set = dce_v10_0_set_pageflip_irq_state, 3794 .process = dce_v10_0_pageflip_irq, 3795 }; 3796 3797 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3798 .set = dce_v10_0_set_hpd_irq_state, 3799 .process = dce_v10_0_hpd_irq, 3800 }; 3801 3802 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3803 { 3804 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3805 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3806 3807 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3808 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3809 3810 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3811 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3812 } 3813