1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drm_edid.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_modeset_helper.h> 27 #include <drm/drm_modeset_helper_vtables.h> 28 #include <drm/drm_vblank.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_i2c.h" 33 #include "vid.h" 34 #include "atom.h" 35 #include "amdgpu_atombios.h" 36 #include "atombios_crtc.h" 37 #include "atombios_encoders.h" 38 #include "amdgpu_pll.h" 39 #include "amdgpu_connectors.h" 40 #include "amdgpu_display.h" 41 #include "dce_v10_0.h" 42 43 #include "dce/dce_10_0_d.h" 44 #include "dce/dce_10_0_sh_mask.h" 45 #include "dce/dce_10_0_enum.h" 46 #include "oss/oss_3_0_d.h" 47 #include "oss/oss_3_0_sh_mask.h" 48 #include "gmc/gmc_8_1_d.h" 49 #include "gmc/gmc_8_1_sh_mask.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 54 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); 56 57 static const u32 crtc_offsets[] = { 58 CRTC0_REGISTER_OFFSET, 59 CRTC1_REGISTER_OFFSET, 60 CRTC2_REGISTER_OFFSET, 61 CRTC3_REGISTER_OFFSET, 62 CRTC4_REGISTER_OFFSET, 63 CRTC5_REGISTER_OFFSET, 64 CRTC6_REGISTER_OFFSET 65 }; 66 67 static const u32 hpd_offsets[] = { 68 HPD0_REGISTER_OFFSET, 69 HPD1_REGISTER_OFFSET, 70 HPD2_REGISTER_OFFSET, 71 HPD3_REGISTER_OFFSET, 72 HPD4_REGISTER_OFFSET, 73 HPD5_REGISTER_OFFSET 74 }; 75 76 static const uint32_t dig_offsets[] = { 77 DIG0_REGISTER_OFFSET, 78 DIG1_REGISTER_OFFSET, 79 DIG2_REGISTER_OFFSET, 80 DIG3_REGISTER_OFFSET, 81 DIG4_REGISTER_OFFSET, 82 DIG5_REGISTER_OFFSET, 83 DIG6_REGISTER_OFFSET 84 }; 85 86 static const struct { 87 uint32_t reg; 88 uint32_t vblank; 89 uint32_t vline; 90 uint32_t hpd; 91 92 } interrupt_status_offsets[] = { { 93 .reg = mmDISP_INTERRUPT_STATUS, 94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 97 }, { 98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 102 }, { 103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 107 }, { 108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 112 }, { 113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 117 }, { 118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 122 } }; 123 124 static const u32 golden_settings_tonga_a11[] = { 125 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 127 mmFBC_MISC, 0x1f311fff, 0x12300000, 128 mmHDMI_CONTROL, 0x31000111, 0x00000011, 129 }; 130 131 static const u32 tonga_mgcg_cgcg_init[] = { 132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 134 }; 135 136 static const u32 golden_settings_fiji_a10[] = { 137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 139 mmFBC_MISC, 0x1f311fff, 0x12300000, 140 mmHDMI_CONTROL, 0x31000111, 0x00000011, 141 }; 142 143 static const u32 fiji_mgcg_cgcg_init[] = { 144 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 145 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 146 }; 147 148 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 149 { 150 switch (adev->asic_type) { 151 case CHIP_FIJI: 152 amdgpu_device_program_register_sequence(adev, 153 fiji_mgcg_cgcg_init, 154 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 155 amdgpu_device_program_register_sequence(adev, 156 golden_settings_fiji_a10, 157 ARRAY_SIZE(golden_settings_fiji_a10)); 158 break; 159 case CHIP_TONGA: 160 amdgpu_device_program_register_sequence(adev, 161 tonga_mgcg_cgcg_init, 162 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 163 amdgpu_device_program_register_sequence(adev, 164 golden_settings_tonga_a11, 165 ARRAY_SIZE(golden_settings_tonga_a11)); 166 break; 167 default: 168 break; 169 } 170 } 171 172 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 173 u32 block_offset, u32 reg) 174 { 175 unsigned long flags; 176 u32 r; 177 178 spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 179 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 180 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 181 spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 182 183 return r; 184 } 185 186 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 187 u32 block_offset, u32 reg, u32 v) 188 { 189 unsigned long flags; 190 191 spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); 192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 193 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 194 spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); 195 } 196 197 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 198 { 199 if (crtc >= adev->mode_info.num_crtc) 200 return 0; 201 else 202 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 203 } 204 205 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 206 { 207 unsigned i; 208 209 /* Enable pflip interrupts */ 210 for (i = 0; i < adev->mode_info.num_crtc; i++) 211 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 212 } 213 214 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 215 { 216 unsigned i; 217 218 /* Disable pflip interrupts */ 219 for (i = 0; i < adev->mode_info.num_crtc; i++) 220 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 221 } 222 223 /** 224 * dce_v10_0_page_flip - pageflip callback. 225 * 226 * @adev: amdgpu_device pointer 227 * @crtc_id: crtc to cleanup pageflip on 228 * @crtc_base: new address of the crtc (GPU MC address) 229 * @async: asynchronous flip 230 * 231 * Triggers the actual pageflip by updating the primary 232 * surface base address. 233 */ 234 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 235 int crtc_id, u64 crtc_base, bool async) 236 { 237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 239 u32 tmp; 240 241 /* flip at hsync for async, default is vsync */ 242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 243 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 244 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); 245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 246 /* update pitch */ 247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 248 fb->pitches[0] / fb->format->cpp[0]); 249 /* update the primary scanout address */ 250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 251 upper_32_bits(crtc_base)); 252 /* writing to the low address triggers the update */ 253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 254 lower_32_bits(crtc_base)); 255 /* post the write */ 256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 257 } 258 259 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 260 u32 *vbl, u32 *position) 261 { 262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 263 return -EINVAL; 264 265 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 266 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 267 268 return 0; 269 } 270 271 /** 272 * dce_v10_0_hpd_sense - hpd sense callback. 273 * 274 * @adev: amdgpu_device pointer 275 * @hpd: hpd (hotplug detect) pin 276 * 277 * Checks if a digital monitor is connected (evergreen+). 278 * Returns true if connected, false if not connected. 279 */ 280 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 281 enum amdgpu_hpd_id hpd) 282 { 283 bool connected = false; 284 285 if (hpd >= adev->mode_info.num_hpd) 286 return connected; 287 288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 289 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 290 connected = true; 291 292 return connected; 293 } 294 295 /** 296 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 297 * 298 * @adev: amdgpu_device pointer 299 * @hpd: hpd (hotplug detect) pin 300 * 301 * Set the polarity of the hpd pin (evergreen+). 302 */ 303 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 304 enum amdgpu_hpd_id hpd) 305 { 306 u32 tmp; 307 bool connected = dce_v10_0_hpd_sense(adev, hpd); 308 309 if (hpd >= adev->mode_info.num_hpd) 310 return; 311 312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 313 if (connected) 314 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 315 else 316 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 318 } 319 320 /** 321 * dce_v10_0_hpd_init - hpd setup callback. 322 * 323 * @adev: amdgpu_device pointer 324 * 325 * Setup the hpd pins used by the card (evergreen+). 326 * Enable the pin, set the polarity, and enable the hpd interrupts. 327 */ 328 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 329 { 330 struct drm_device *dev = adev_to_drm(adev); 331 struct drm_connector *connector; 332 struct drm_connector_list_iter iter; 333 u32 tmp; 334 335 drm_connector_list_iter_begin(dev, &iter); 336 drm_for_each_connector_iter(connector, &iter) { 337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 338 339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 340 continue; 341 342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 344 /* don't try to enable hpd on eDP or LVDS avoid breaking the 345 * aux dp channel on imac and help (but not completely fix) 346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 347 * also avoid interrupt storms during dpms. 348 */ 349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 350 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 352 continue; 353 } 354 355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 356 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 358 359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 360 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 361 DC_HPD_CONNECT_INT_DELAY, 362 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 363 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 364 DC_HPD_DISCONNECT_INT_DELAY, 365 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 367 368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); 369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 370 amdgpu_irq_get(adev, &adev->hpd_irq, 371 amdgpu_connector->hpd.hpd); 372 } 373 drm_connector_list_iter_end(&iter); 374 } 375 376 /** 377 * dce_v10_0_hpd_fini - hpd tear down callback. 378 * 379 * @adev: amdgpu_device pointer 380 * 381 * Tear down the hpd pins used by the card (evergreen+). 382 * Disable the hpd interrupts. 383 */ 384 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 385 { 386 struct drm_device *dev = adev_to_drm(adev); 387 struct drm_connector *connector; 388 struct drm_connector_list_iter iter; 389 u32 tmp; 390 391 drm_connector_list_iter_begin(dev, &iter); 392 drm_for_each_connector_iter(connector, &iter) { 393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 394 395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 396 continue; 397 398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 399 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 401 402 amdgpu_irq_put(adev, &adev->hpd_irq, 403 amdgpu_connector->hpd.hpd); 404 } 405 drm_connector_list_iter_end(&iter); 406 } 407 408 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 409 { 410 return mmDC_GPIO_HPD_A; 411 } 412 413 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 414 bool render) 415 { 416 u32 tmp; 417 418 /* Lockout access through VGA aperture*/ 419 tmp = RREG32(mmVGA_HDP_CONTROL); 420 if (render) 421 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 422 else 423 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 424 WREG32(mmVGA_HDP_CONTROL, tmp); 425 426 /* disable VGA render */ 427 tmp = RREG32(mmVGA_RENDER_CONTROL); 428 if (render) 429 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 430 else 431 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 432 WREG32(mmVGA_RENDER_CONTROL, tmp); 433 } 434 435 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev) 436 { 437 int num_crtc = 0; 438 439 switch (adev->asic_type) { 440 case CHIP_FIJI: 441 case CHIP_TONGA: 442 num_crtc = 6; 443 break; 444 default: 445 num_crtc = 0; 446 } 447 return num_crtc; 448 } 449 450 void dce_v10_0_disable_dce(struct amdgpu_device *adev) 451 { 452 /*Disable VGA render and enabled crtc, if has DCE engine*/ 453 if (amdgpu_atombios_has_dce_engine_info(adev)) { 454 u32 tmp; 455 int crtc_enabled, i; 456 457 dce_v10_0_set_vga_render_state(adev, false); 458 459 /*Disable crtc*/ 460 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) { 461 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 462 CRTC_CONTROL, CRTC_MASTER_EN); 463 if (crtc_enabled) { 464 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 465 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 466 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 467 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 468 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 469 } 470 } 471 } 472 } 473 474 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 475 { 476 struct drm_device *dev = encoder->dev; 477 struct amdgpu_device *adev = drm_to_adev(dev); 478 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 479 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 480 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 481 int bpc = 0; 482 u32 tmp = 0; 483 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 484 485 if (connector) { 486 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 487 bpc = amdgpu_connector_get_monitor_bpc(connector); 488 dither = amdgpu_connector->dither; 489 } 490 491 /* LVDS/eDP FMT is set up by atom */ 492 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 493 return; 494 495 /* not needed for analog */ 496 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 497 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 498 return; 499 500 if (bpc == 0) 501 return; 502 503 switch (bpc) { 504 case 6: 505 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 506 /* XXX sort out optimal dither settings */ 507 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 508 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 509 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 510 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 511 } else { 512 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 513 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 514 } 515 break; 516 case 8: 517 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 518 /* XXX sort out optimal dither settings */ 519 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 520 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 521 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 522 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 523 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 524 } else { 525 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 526 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 527 } 528 break; 529 case 10: 530 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 531 /* XXX sort out optimal dither settings */ 532 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 533 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 534 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 535 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 536 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 537 } else { 538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 540 } 541 break; 542 default: 543 /* not needed */ 544 break; 545 } 546 547 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 548 } 549 550 551 /* display watermark setup */ 552 /** 553 * dce_v10_0_line_buffer_adjust - Set up the line buffer 554 * 555 * @adev: amdgpu_device pointer 556 * @amdgpu_crtc: the selected display controller 557 * @mode: the current display mode on the selected display 558 * controller 559 * 560 * Setup up the line buffer allocation for 561 * the selected display controller (CIK). 562 * Returns the line buffer size in pixels. 563 */ 564 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 565 struct amdgpu_crtc *amdgpu_crtc, 566 struct drm_display_mode *mode) 567 { 568 u32 tmp, buffer_alloc, i, mem_cfg; 569 u32 pipe_offset = amdgpu_crtc->crtc_id; 570 /* 571 * Line Buffer Setup 572 * There are 6 line buffers, one for each display controllers. 573 * There are 3 partitions per LB. Select the number of partitions 574 * to enable based on the display width. For display widths larger 575 * than 4096, you need use to use 2 display controllers and combine 576 * them using the stereo blender. 577 */ 578 if (amdgpu_crtc->base.enabled && mode) { 579 if (mode->crtc_hdisplay < 1920) { 580 mem_cfg = 1; 581 buffer_alloc = 2; 582 } else if (mode->crtc_hdisplay < 2560) { 583 mem_cfg = 2; 584 buffer_alloc = 2; 585 } else if (mode->crtc_hdisplay < 4096) { 586 mem_cfg = 0; 587 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 588 } else { 589 DRM_DEBUG_KMS("Mode too big for LB!\n"); 590 mem_cfg = 0; 591 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 592 } 593 } else { 594 mem_cfg = 1; 595 buffer_alloc = 0; 596 } 597 598 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 599 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 600 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 601 602 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 603 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 604 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 605 606 for (i = 0; i < adev->usec_timeout; i++) { 607 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 608 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 609 break; 610 udelay(1); 611 } 612 613 if (amdgpu_crtc->base.enabled && mode) { 614 switch (mem_cfg) { 615 case 0: 616 default: 617 return 4096 * 2; 618 case 1: 619 return 1920 * 2; 620 case 2: 621 return 2560 * 2; 622 } 623 } 624 625 /* controller not enabled, so no lb used */ 626 return 0; 627 } 628 629 /** 630 * cik_get_number_of_dram_channels - get the number of dram channels 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Look up the number of video ram channels (CIK). 635 * Used for display watermark bandwidth calculations 636 * Returns the number of dram channels 637 */ 638 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 639 { 640 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 641 642 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 643 case 0: 644 default: 645 return 1; 646 case 1: 647 return 2; 648 case 2: 649 return 4; 650 case 3: 651 return 8; 652 case 4: 653 return 3; 654 case 5: 655 return 6; 656 case 6: 657 return 10; 658 case 7: 659 return 12; 660 case 8: 661 return 16; 662 } 663 } 664 665 struct dce10_wm_params { 666 u32 dram_channels; /* number of dram channels */ 667 u32 yclk; /* bandwidth per dram data pin in kHz */ 668 u32 sclk; /* engine clock in kHz */ 669 u32 disp_clk; /* display clock in kHz */ 670 u32 src_width; /* viewport width */ 671 u32 active_time; /* active display time in ns */ 672 u32 blank_time; /* blank time in ns */ 673 bool interlaced; /* mode is interlaced */ 674 fixed20_12 vsc; /* vertical scale ratio */ 675 u32 num_heads; /* number of active crtcs */ 676 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 677 u32 lb_size; /* line buffer allocated to pipe */ 678 u32 vtaps; /* vertical scaler taps */ 679 }; 680 681 /** 682 * dce_v10_0_dram_bandwidth - get the dram bandwidth 683 * 684 * @wm: watermark calculation data 685 * 686 * Calculate the raw dram bandwidth (CIK). 687 * Used for display watermark bandwidth calculations 688 * Returns the dram bandwidth in MBytes/s 689 */ 690 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 691 { 692 /* Calculate raw DRAM Bandwidth */ 693 fixed20_12 dram_efficiency; /* 0.7 */ 694 fixed20_12 yclk, dram_channels, bandwidth; 695 fixed20_12 a; 696 697 a.full = dfixed_const(1000); 698 yclk.full = dfixed_const(wm->yclk); 699 yclk.full = dfixed_div(yclk, a); 700 dram_channels.full = dfixed_const(wm->dram_channels * 4); 701 a.full = dfixed_const(10); 702 dram_efficiency.full = dfixed_const(7); 703 dram_efficiency.full = dfixed_div(dram_efficiency, a); 704 bandwidth.full = dfixed_mul(dram_channels, yclk); 705 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 706 707 return dfixed_trunc(bandwidth); 708 } 709 710 /** 711 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 712 * 713 * @wm: watermark calculation data 714 * 715 * Calculate the dram bandwidth used for display (CIK). 716 * Used for display watermark bandwidth calculations 717 * Returns the dram bandwidth for display in MBytes/s 718 */ 719 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 720 { 721 /* Calculate DRAM Bandwidth and the part allocated to display. */ 722 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 723 fixed20_12 yclk, dram_channels, bandwidth; 724 fixed20_12 a; 725 726 a.full = dfixed_const(1000); 727 yclk.full = dfixed_const(wm->yclk); 728 yclk.full = dfixed_div(yclk, a); 729 dram_channels.full = dfixed_const(wm->dram_channels * 4); 730 a.full = dfixed_const(10); 731 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 732 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 733 bandwidth.full = dfixed_mul(dram_channels, yclk); 734 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 735 736 return dfixed_trunc(bandwidth); 737 } 738 739 /** 740 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 741 * 742 * @wm: watermark calculation data 743 * 744 * Calculate the data return bandwidth used for display (CIK). 745 * Used for display watermark bandwidth calculations 746 * Returns the data return bandwidth in MBytes/s 747 */ 748 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 749 { 750 /* Calculate the display Data return Bandwidth */ 751 fixed20_12 return_efficiency; /* 0.8 */ 752 fixed20_12 sclk, bandwidth; 753 fixed20_12 a; 754 755 a.full = dfixed_const(1000); 756 sclk.full = dfixed_const(wm->sclk); 757 sclk.full = dfixed_div(sclk, a); 758 a.full = dfixed_const(10); 759 return_efficiency.full = dfixed_const(8); 760 return_efficiency.full = dfixed_div(return_efficiency, a); 761 a.full = dfixed_const(32); 762 bandwidth.full = dfixed_mul(a, sclk); 763 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 764 765 return dfixed_trunc(bandwidth); 766 } 767 768 /** 769 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 770 * 771 * @wm: watermark calculation data 772 * 773 * Calculate the dmif bandwidth used for display (CIK). 774 * Used for display watermark bandwidth calculations 775 * Returns the dmif bandwidth in MBytes/s 776 */ 777 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 778 { 779 /* Calculate the DMIF Request Bandwidth */ 780 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 781 fixed20_12 disp_clk, bandwidth; 782 fixed20_12 a, b; 783 784 a.full = dfixed_const(1000); 785 disp_clk.full = dfixed_const(wm->disp_clk); 786 disp_clk.full = dfixed_div(disp_clk, a); 787 a.full = dfixed_const(32); 788 b.full = dfixed_mul(a, disp_clk); 789 790 a.full = dfixed_const(10); 791 disp_clk_request_efficiency.full = dfixed_const(8); 792 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 793 794 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 795 796 return dfixed_trunc(bandwidth); 797 } 798 799 /** 800 * dce_v10_0_available_bandwidth - get the min available bandwidth 801 * 802 * @wm: watermark calculation data 803 * 804 * Calculate the min available bandwidth used for display (CIK). 805 * Used for display watermark bandwidth calculations 806 * Returns the min available bandwidth in MBytes/s 807 */ 808 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 809 { 810 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 811 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 812 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 813 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 814 815 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 816 } 817 818 /** 819 * dce_v10_0_average_bandwidth - get the average available bandwidth 820 * 821 * @wm: watermark calculation data 822 * 823 * Calculate the average available bandwidth used for display (CIK). 824 * Used for display watermark bandwidth calculations 825 * Returns the average available bandwidth in MBytes/s 826 */ 827 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 828 { 829 /* Calculate the display mode Average Bandwidth 830 * DisplayMode should contain the source and destination dimensions, 831 * timing, etc. 832 */ 833 fixed20_12 bpp; 834 fixed20_12 line_time; 835 fixed20_12 src_width; 836 fixed20_12 bandwidth; 837 fixed20_12 a; 838 839 a.full = dfixed_const(1000); 840 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 841 line_time.full = dfixed_div(line_time, a); 842 bpp.full = dfixed_const(wm->bytes_per_pixel); 843 src_width.full = dfixed_const(wm->src_width); 844 bandwidth.full = dfixed_mul(src_width, bpp); 845 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 846 bandwidth.full = dfixed_div(bandwidth, line_time); 847 848 return dfixed_trunc(bandwidth); 849 } 850 851 /** 852 * dce_v10_0_latency_watermark - get the latency watermark 853 * 854 * @wm: watermark calculation data 855 * 856 * Calculate the latency watermark (CIK). 857 * Used for display watermark bandwidth calculations 858 * Returns the latency watermark in ns 859 */ 860 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 861 { 862 /* First calculate the latency in ns */ 863 u32 mc_latency = 2000; /* 2000 ns. */ 864 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 865 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 866 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 867 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 868 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 869 (wm->num_heads * cursor_line_pair_return_time); 870 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 871 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 872 u32 tmp, dmif_size = 12288; 873 fixed20_12 a, b, c; 874 875 if (wm->num_heads == 0) 876 return 0; 877 878 a.full = dfixed_const(2); 879 b.full = dfixed_const(1); 880 if ((wm->vsc.full > a.full) || 881 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 882 (wm->vtaps >= 5) || 883 ((wm->vsc.full >= a.full) && wm->interlaced)) 884 max_src_lines_per_dst_line = 4; 885 else 886 max_src_lines_per_dst_line = 2; 887 888 a.full = dfixed_const(available_bandwidth); 889 b.full = dfixed_const(wm->num_heads); 890 a.full = dfixed_div(a, b); 891 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 892 tmp = min(dfixed_trunc(a), tmp); 893 894 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 895 896 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 897 b.full = dfixed_const(1000); 898 c.full = dfixed_const(lb_fill_bw); 899 b.full = dfixed_div(c, b); 900 a.full = dfixed_div(a, b); 901 line_fill_time = dfixed_trunc(a); 902 903 if (line_fill_time < wm->active_time) 904 return latency; 905 else 906 return latency + (line_fill_time - wm->active_time); 907 908 } 909 910 /** 911 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 912 * average and available dram bandwidth 913 * 914 * @wm: watermark calculation data 915 * 916 * Check if the display average bandwidth fits in the display 917 * dram bandwidth (CIK). 918 * Used for display watermark bandwidth calculations 919 * Returns true if the display fits, false if not. 920 */ 921 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 922 { 923 if (dce_v10_0_average_bandwidth(wm) <= 924 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 925 return true; 926 else 927 return false; 928 } 929 930 /** 931 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 932 * average and available bandwidth 933 * 934 * @wm: watermark calculation data 935 * 936 * Check if the display average bandwidth fits in the display 937 * available bandwidth (CIK). 938 * Used for display watermark bandwidth calculations 939 * Returns true if the display fits, false if not. 940 */ 941 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 942 { 943 if (dce_v10_0_average_bandwidth(wm) <= 944 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 945 return true; 946 else 947 return false; 948 } 949 950 /** 951 * dce_v10_0_check_latency_hiding - check latency hiding 952 * 953 * @wm: watermark calculation data 954 * 955 * Check latency hiding (CIK). 956 * Used for display watermark bandwidth calculations 957 * Returns true if the display fits, false if not. 958 */ 959 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 960 { 961 u32 lb_partitions = wm->lb_size / wm->src_width; 962 u32 line_time = wm->active_time + wm->blank_time; 963 u32 latency_tolerant_lines; 964 u32 latency_hiding; 965 fixed20_12 a; 966 967 a.full = dfixed_const(1); 968 if (wm->vsc.full > a.full) 969 latency_tolerant_lines = 1; 970 else { 971 if (lb_partitions <= (wm->vtaps + 1)) 972 latency_tolerant_lines = 1; 973 else 974 latency_tolerant_lines = 2; 975 } 976 977 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 978 979 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 980 return true; 981 else 982 return false; 983 } 984 985 /** 986 * dce_v10_0_program_watermarks - program display watermarks 987 * 988 * @adev: amdgpu_device pointer 989 * @amdgpu_crtc: the selected display controller 990 * @lb_size: line buffer size 991 * @num_heads: number of display controllers in use 992 * 993 * Calculate and program the display watermarks for the 994 * selected display controller (CIK). 995 */ 996 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 997 struct amdgpu_crtc *amdgpu_crtc, 998 u32 lb_size, u32 num_heads) 999 { 1000 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1001 struct dce10_wm_params wm_low, wm_high; 1002 u32 active_time; 1003 u32 line_time = 0; 1004 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1005 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1006 1007 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1008 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1009 (u32)mode->clock); 1010 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1011 (u32)mode->clock); 1012 line_time = min_t(u32, line_time, 65535); 1013 1014 /* watermark for high clocks */ 1015 if (adev->pm.dpm_enabled) { 1016 wm_high.yclk = 1017 amdgpu_dpm_get_mclk(adev, false) * 10; 1018 wm_high.sclk = 1019 amdgpu_dpm_get_sclk(adev, false) * 10; 1020 } else { 1021 wm_high.yclk = adev->pm.current_mclk * 10; 1022 wm_high.sclk = adev->pm.current_sclk * 10; 1023 } 1024 1025 wm_high.disp_clk = mode->clock; 1026 wm_high.src_width = mode->crtc_hdisplay; 1027 wm_high.active_time = active_time; 1028 wm_high.blank_time = line_time - wm_high.active_time; 1029 wm_high.interlaced = false; 1030 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1031 wm_high.interlaced = true; 1032 wm_high.vsc = amdgpu_crtc->vsc; 1033 wm_high.vtaps = 1; 1034 if (amdgpu_crtc->rmx_type != RMX_OFF) 1035 wm_high.vtaps = 2; 1036 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1037 wm_high.lb_size = lb_size; 1038 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1039 wm_high.num_heads = num_heads; 1040 1041 /* set for high clocks */ 1042 latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535); 1043 1044 /* possibly force display priority to high */ 1045 /* should really do this at mode validation time... */ 1046 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1047 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1048 !dce_v10_0_check_latency_hiding(&wm_high) || 1049 (adev->mode_info.disp_priority == 2)) { 1050 DRM_DEBUG_KMS("force priority to high\n"); 1051 } 1052 1053 /* watermark for low clocks */ 1054 if (adev->pm.dpm_enabled) { 1055 wm_low.yclk = 1056 amdgpu_dpm_get_mclk(adev, true) * 10; 1057 wm_low.sclk = 1058 amdgpu_dpm_get_sclk(adev, true) * 10; 1059 } else { 1060 wm_low.yclk = adev->pm.current_mclk * 10; 1061 wm_low.sclk = adev->pm.current_sclk * 10; 1062 } 1063 1064 wm_low.disp_clk = mode->clock; 1065 wm_low.src_width = mode->crtc_hdisplay; 1066 wm_low.active_time = active_time; 1067 wm_low.blank_time = line_time - wm_low.active_time; 1068 wm_low.interlaced = false; 1069 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1070 wm_low.interlaced = true; 1071 wm_low.vsc = amdgpu_crtc->vsc; 1072 wm_low.vtaps = 1; 1073 if (amdgpu_crtc->rmx_type != RMX_OFF) 1074 wm_low.vtaps = 2; 1075 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1076 wm_low.lb_size = lb_size; 1077 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1078 wm_low.num_heads = num_heads; 1079 1080 /* set for low clocks */ 1081 latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535); 1082 1083 /* possibly force display priority to high */ 1084 /* should really do this at mode validation time... */ 1085 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1086 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1087 !dce_v10_0_check_latency_hiding(&wm_low) || 1088 (adev->mode_info.disp_priority == 2)) { 1089 DRM_DEBUG_KMS("force priority to high\n"); 1090 } 1091 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1092 } 1093 1094 /* select wm A */ 1095 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1096 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1097 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1098 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1099 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1100 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1101 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1102 /* select wm B */ 1103 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1104 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1105 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1106 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1107 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1108 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1109 /* restore original selection */ 1110 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1111 1112 /* save values for DPM */ 1113 amdgpu_crtc->line_time = line_time; 1114 1115 /* Save number of lines the linebuffer leads before the scanout */ 1116 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1117 } 1118 1119 /** 1120 * dce_v10_0_bandwidth_update - program display watermarks 1121 * 1122 * @adev: amdgpu_device pointer 1123 * 1124 * Calculate and program the display watermarks and line 1125 * buffer allocation (CIK). 1126 */ 1127 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1128 { 1129 struct drm_display_mode *mode = NULL; 1130 u32 num_heads = 0, lb_size; 1131 int i; 1132 1133 amdgpu_display_update_priority(adev); 1134 1135 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1136 if (adev->mode_info.crtcs[i]->base.enabled) 1137 num_heads++; 1138 } 1139 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1140 mode = &adev->mode_info.crtcs[i]->base.mode; 1141 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1142 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1143 lb_size, num_heads); 1144 } 1145 } 1146 1147 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1148 { 1149 int i; 1150 u32 offset, tmp; 1151 1152 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1153 offset = adev->mode_info.audio.pin[i].offset; 1154 tmp = RREG32_AUDIO_ENDPT(offset, 1155 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1156 if (((tmp & 1157 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1158 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1159 adev->mode_info.audio.pin[i].connected = false; 1160 else 1161 adev->mode_info.audio.pin[i].connected = true; 1162 } 1163 } 1164 1165 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1166 { 1167 int i; 1168 1169 dce_v10_0_audio_get_connected_pins(adev); 1170 1171 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1172 if (adev->mode_info.audio.pin[i].connected) 1173 return &adev->mode_info.audio.pin[i]; 1174 } 1175 DRM_ERROR("No connected audio pins found!\n"); 1176 return NULL; 1177 } 1178 1179 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1180 { 1181 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1182 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1183 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1184 u32 tmp; 1185 1186 if (!dig || !dig->afmt || !dig->afmt->pin) 1187 return; 1188 1189 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1190 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1191 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1192 } 1193 1194 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1195 struct drm_display_mode *mode) 1196 { 1197 struct drm_device *dev = encoder->dev; 1198 struct amdgpu_device *adev = drm_to_adev(dev); 1199 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1200 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1201 struct drm_connector *connector; 1202 struct drm_connector_list_iter iter; 1203 struct amdgpu_connector *amdgpu_connector = NULL; 1204 u32 tmp; 1205 int interlace = 0; 1206 1207 if (!dig || !dig->afmt || !dig->afmt->pin) 1208 return; 1209 1210 drm_connector_list_iter_begin(dev, &iter); 1211 drm_for_each_connector_iter(connector, &iter) { 1212 if (connector->encoder == encoder) { 1213 amdgpu_connector = to_amdgpu_connector(connector); 1214 break; 1215 } 1216 } 1217 drm_connector_list_iter_end(&iter); 1218 1219 if (!amdgpu_connector) { 1220 DRM_ERROR("Couldn't find encoder's connector\n"); 1221 return; 1222 } 1223 1224 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1225 interlace = 1; 1226 if (connector->latency_present[interlace]) { 1227 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1228 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1229 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1230 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1231 } else { 1232 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1233 VIDEO_LIPSYNC, 0); 1234 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1235 AUDIO_LIPSYNC, 0); 1236 } 1237 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1238 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1239 } 1240 1241 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1242 { 1243 struct drm_device *dev = encoder->dev; 1244 struct amdgpu_device *adev = drm_to_adev(dev); 1245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1247 struct drm_connector *connector; 1248 struct drm_connector_list_iter iter; 1249 struct amdgpu_connector *amdgpu_connector = NULL; 1250 u32 tmp; 1251 u8 *sadb = NULL; 1252 int sad_count; 1253 1254 if (!dig || !dig->afmt || !dig->afmt->pin) 1255 return; 1256 1257 drm_connector_list_iter_begin(dev, &iter); 1258 drm_for_each_connector_iter(connector, &iter) { 1259 if (connector->encoder == encoder) { 1260 amdgpu_connector = to_amdgpu_connector(connector); 1261 break; 1262 } 1263 } 1264 drm_connector_list_iter_end(&iter); 1265 1266 if (!amdgpu_connector) { 1267 DRM_ERROR("Couldn't find encoder's connector\n"); 1268 return; 1269 } 1270 1271 sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); 1272 if (sad_count < 0) { 1273 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1274 sad_count = 0; 1275 } 1276 1277 /* program the speaker allocation */ 1278 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1279 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1280 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1281 DP_CONNECTION, 0); 1282 /* set HDMI mode */ 1283 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1284 HDMI_CONNECTION, 1); 1285 if (sad_count) 1286 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1287 SPEAKER_ALLOCATION, sadb[0]); 1288 else 1289 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1290 SPEAKER_ALLOCATION, 5); /* stereo */ 1291 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1292 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1293 1294 kfree(sadb); 1295 } 1296 1297 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1298 { 1299 struct drm_device *dev = encoder->dev; 1300 struct amdgpu_device *adev = drm_to_adev(dev); 1301 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1302 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1303 struct drm_connector *connector; 1304 struct drm_connector_list_iter iter; 1305 struct amdgpu_connector *amdgpu_connector = NULL; 1306 struct cea_sad *sads; 1307 int i, sad_count; 1308 1309 static const u16 eld_reg_to_type[][2] = { 1310 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1311 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1312 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1313 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1314 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1315 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1316 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1319 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1320 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1321 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1322 }; 1323 1324 if (!dig || !dig->afmt || !dig->afmt->pin) 1325 return; 1326 1327 drm_connector_list_iter_begin(dev, &iter); 1328 drm_for_each_connector_iter(connector, &iter) { 1329 if (connector->encoder == encoder) { 1330 amdgpu_connector = to_amdgpu_connector(connector); 1331 break; 1332 } 1333 } 1334 drm_connector_list_iter_end(&iter); 1335 1336 if (!amdgpu_connector) { 1337 DRM_ERROR("Couldn't find encoder's connector\n"); 1338 return; 1339 } 1340 1341 sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); 1342 if (sad_count < 0) 1343 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1344 if (sad_count <= 0) 1345 return; 1346 BUG_ON(!sads); 1347 1348 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1349 u32 tmp = 0; 1350 u8 stereo_freqs = 0; 1351 int max_channels = -1; 1352 int j; 1353 1354 for (j = 0; j < sad_count; j++) { 1355 struct cea_sad *sad = &sads[j]; 1356 1357 if (sad->format == eld_reg_to_type[i][1]) { 1358 if (sad->channels > max_channels) { 1359 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1360 MAX_CHANNELS, sad->channels); 1361 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1362 DESCRIPTOR_BYTE_2, sad->byte2); 1363 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1364 SUPPORTED_FREQUENCIES, sad->freq); 1365 max_channels = sad->channels; 1366 } 1367 1368 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1369 stereo_freqs |= sad->freq; 1370 else 1371 break; 1372 } 1373 } 1374 1375 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1376 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1377 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1378 } 1379 1380 kfree(sads); 1381 } 1382 1383 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1384 struct amdgpu_audio_pin *pin, 1385 bool enable) 1386 { 1387 if (!pin) 1388 return; 1389 1390 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1391 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1392 } 1393 1394 static const u32 pin_offsets[] = { 1395 AUD0_REGISTER_OFFSET, 1396 AUD1_REGISTER_OFFSET, 1397 AUD2_REGISTER_OFFSET, 1398 AUD3_REGISTER_OFFSET, 1399 AUD4_REGISTER_OFFSET, 1400 AUD5_REGISTER_OFFSET, 1401 AUD6_REGISTER_OFFSET, 1402 }; 1403 1404 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1405 { 1406 int i; 1407 1408 if (!amdgpu_audio) 1409 return 0; 1410 1411 adev->mode_info.audio.enabled = true; 1412 1413 adev->mode_info.audio.num_pins = 7; 1414 1415 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1416 adev->mode_info.audio.pin[i].channels = -1; 1417 adev->mode_info.audio.pin[i].rate = -1; 1418 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1419 adev->mode_info.audio.pin[i].status_bits = 0; 1420 adev->mode_info.audio.pin[i].category_code = 0; 1421 adev->mode_info.audio.pin[i].connected = false; 1422 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1423 adev->mode_info.audio.pin[i].id = i; 1424 /* disable audio. it will be set up later */ 1425 /* XXX remove once we switch to ip funcs */ 1426 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1427 } 1428 1429 return 0; 1430 } 1431 1432 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1433 { 1434 if (!amdgpu_audio) 1435 return; 1436 1437 if (!adev->mode_info.audio.enabled) 1438 return; 1439 1440 adev->mode_info.audio.enabled = false; 1441 } 1442 1443 /* 1444 * update the N and CTS parameters for a given pixel clock rate 1445 */ 1446 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1447 { 1448 struct drm_device *dev = encoder->dev; 1449 struct amdgpu_device *adev = drm_to_adev(dev); 1450 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1451 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1452 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1453 u32 tmp; 1454 1455 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1456 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1457 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1458 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1459 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1460 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1461 1462 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1463 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1464 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1465 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1466 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1467 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1468 1469 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1470 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1471 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1472 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1473 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1474 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1475 1476 } 1477 1478 /* 1479 * build a HDMI Video Info Frame 1480 */ 1481 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1482 void *buffer, size_t size) 1483 { 1484 struct drm_device *dev = encoder->dev; 1485 struct amdgpu_device *adev = drm_to_adev(dev); 1486 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1487 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1488 uint8_t *frame = buffer + 3; 1489 uint8_t *header = buffer; 1490 1491 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1492 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1493 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1494 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1495 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1496 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1497 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1498 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1499 } 1500 1501 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1502 { 1503 struct drm_device *dev = encoder->dev; 1504 struct amdgpu_device *adev = drm_to_adev(dev); 1505 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1506 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1507 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1508 u32 dto_phase = 24 * 1000; 1509 u32 dto_modulo = clock; 1510 u32 tmp; 1511 1512 if (!dig || !dig->afmt) 1513 return; 1514 1515 /* XXX two dtos; generally use dto0 for hdmi */ 1516 /* Express [24MHz / target pixel clock] as an exact rational 1517 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1518 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1519 */ 1520 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1521 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1522 amdgpu_crtc->crtc_id); 1523 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1524 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1525 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1526 } 1527 1528 /* 1529 * update the info frames with the data from the current display mode 1530 */ 1531 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1532 struct drm_display_mode *mode) 1533 { 1534 struct drm_device *dev = encoder->dev; 1535 struct amdgpu_device *adev = drm_to_adev(dev); 1536 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1537 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1538 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1539 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1540 struct hdmi_avi_infoframe frame; 1541 ssize_t err; 1542 u32 tmp; 1543 int bpc = 8; 1544 1545 if (!dig || !dig->afmt) 1546 return; 1547 1548 /* Silent, r600_hdmi_enable will raise WARN for us */ 1549 if (!dig->afmt->enabled) 1550 return; 1551 1552 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1553 if (encoder->crtc) { 1554 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1555 bpc = amdgpu_crtc->bpc; 1556 } 1557 1558 /* disable audio prior to setting up hw */ 1559 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1560 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1561 1562 dce_v10_0_audio_set_dto(encoder, mode->clock); 1563 1564 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1565 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1566 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1567 1568 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1569 1570 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1571 switch (bpc) { 1572 case 0: 1573 case 6: 1574 case 8: 1575 case 16: 1576 default: 1577 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1578 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1579 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1580 connector->name, bpc); 1581 break; 1582 case 10: 1583 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1584 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1585 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1586 connector->name); 1587 break; 1588 case 12: 1589 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1590 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1591 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1592 connector->name); 1593 break; 1594 } 1595 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1596 1597 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1598 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1599 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1600 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1601 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1602 1603 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1604 /* enable audio info frames (frames won't be set until audio is enabled) */ 1605 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1606 /* required for audio info values to be updated */ 1607 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1608 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1609 1610 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1611 /* required for audio info values to be updated */ 1612 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1613 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1614 1615 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1616 /* anything other than 0 */ 1617 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1618 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1619 1620 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1621 1622 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1623 /* set the default audio delay */ 1624 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1625 /* should be suffient for all audio modes and small enough for all hblanks */ 1626 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1627 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1628 1629 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1630 /* allow 60958 channel status fields to be updated */ 1631 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1632 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1633 1634 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1635 if (bpc > 8) 1636 /* clear SW CTS value */ 1637 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1638 else 1639 /* select SW CTS value */ 1640 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1641 /* allow hw to sent ACR packets when required */ 1642 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1643 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1644 1645 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1646 1647 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1648 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1649 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1650 1651 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1652 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1653 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1654 1655 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1656 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1657 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1658 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1659 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1660 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1661 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1662 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1663 1664 dce_v10_0_audio_write_speaker_allocation(encoder); 1665 1666 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1667 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1668 1669 dce_v10_0_afmt_audio_select_pin(encoder); 1670 dce_v10_0_audio_write_sad_regs(encoder); 1671 dce_v10_0_audio_write_latency_fields(encoder, mode); 1672 1673 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1674 if (err < 0) { 1675 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1676 return; 1677 } 1678 1679 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1680 if (err < 0) { 1681 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1682 return; 1683 } 1684 1685 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1686 1687 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1688 /* enable AVI info frames */ 1689 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1690 /* required for audio info values to be updated */ 1691 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1692 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1693 1694 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1695 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1696 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1697 1698 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1699 /* send audio packets */ 1700 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1701 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1702 1703 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1704 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1705 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1706 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1707 1708 /* enable audio after to setting up hw */ 1709 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 1710 } 1711 1712 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1713 { 1714 struct drm_device *dev = encoder->dev; 1715 struct amdgpu_device *adev = drm_to_adev(dev); 1716 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1717 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1718 1719 if (!dig || !dig->afmt) 1720 return; 1721 1722 /* Silent, r600_hdmi_enable will raise WARN for us */ 1723 if (enable && dig->afmt->enabled) 1724 return; 1725 if (!enable && !dig->afmt->enabled) 1726 return; 1727 1728 if (!enable && dig->afmt->pin) { 1729 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1730 dig->afmt->pin = NULL; 1731 } 1732 1733 dig->afmt->enabled = enable; 1734 1735 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1736 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1737 } 1738 1739 static int dce_v10_0_afmt_init(struct amdgpu_device *adev) 1740 { 1741 int i; 1742 1743 for (i = 0; i < adev->mode_info.num_dig; i++) 1744 adev->mode_info.afmt[i] = NULL; 1745 1746 /* DCE10 has audio blocks tied to DIG encoders */ 1747 for (i = 0; i < adev->mode_info.num_dig; i++) { 1748 adev->mode_info.afmt[i] = kzalloc_obj(struct amdgpu_afmt); 1749 if (adev->mode_info.afmt[i]) { 1750 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1751 adev->mode_info.afmt[i]->id = i; 1752 } else { 1753 int j; 1754 for (j = 0; j < i; j++) { 1755 kfree(adev->mode_info.afmt[j]); 1756 adev->mode_info.afmt[j] = NULL; 1757 } 1758 return -ENOMEM; 1759 } 1760 } 1761 return 0; 1762 } 1763 1764 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 1765 { 1766 int i; 1767 1768 for (i = 0; i < adev->mode_info.num_dig; i++) { 1769 kfree(adev->mode_info.afmt[i]); 1770 adev->mode_info.afmt[i] = NULL; 1771 } 1772 } 1773 1774 static const u32 vga_control_regs[6] = { 1775 mmD1VGA_CONTROL, 1776 mmD2VGA_CONTROL, 1777 mmD3VGA_CONTROL, 1778 mmD4VGA_CONTROL, 1779 mmD5VGA_CONTROL, 1780 mmD6VGA_CONTROL, 1781 }; 1782 1783 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 1784 { 1785 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1786 struct drm_device *dev = crtc->dev; 1787 struct amdgpu_device *adev = drm_to_adev(dev); 1788 u32 vga_control; 1789 1790 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1791 if (enable) 1792 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1793 else 1794 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1795 } 1796 1797 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 1798 { 1799 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1800 struct drm_device *dev = crtc->dev; 1801 struct amdgpu_device *adev = drm_to_adev(dev); 1802 1803 if (enable) 1804 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1805 else 1806 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1807 } 1808 1809 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 1810 struct drm_framebuffer *fb, 1811 int x, int y) 1812 { 1813 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1814 struct drm_device *dev = crtc->dev; 1815 struct amdgpu_device *adev = drm_to_adev(dev); 1816 struct drm_framebuffer *target_fb; 1817 struct drm_gem_object *obj; 1818 struct amdgpu_bo *abo; 1819 uint64_t fb_location, tiling_flags; 1820 uint32_t fb_format, fb_pitch_pixels; 1821 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1822 u32 pipe_config; 1823 u32 tmp, viewport_w, viewport_h; 1824 int r; 1825 bool bypass_lut = false; 1826 1827 /* no fb bound */ 1828 if (!crtc->primary->fb) { 1829 DRM_DEBUG_KMS("No FB bound\n"); 1830 return 0; 1831 } 1832 1833 target_fb = crtc->primary->fb; 1834 1835 /* If atomic, assume fb object is pinned & idle & fenced and 1836 * just update base pointers 1837 */ 1838 obj = target_fb->obj[0]; 1839 abo = gem_to_amdgpu_bo(obj); 1840 r = amdgpu_bo_reserve(abo, false); 1841 if (unlikely(r != 0)) 1842 return r; 1843 1844 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1845 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1846 if (unlikely(r != 0)) { 1847 amdgpu_bo_unreserve(abo); 1848 return -EINVAL; 1849 } 1850 fb_location = amdgpu_bo_gpu_offset(abo); 1851 1852 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1853 amdgpu_bo_unreserve(abo); 1854 1855 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1856 1857 switch (target_fb->format->format) { 1858 case DRM_FORMAT_C8: 1859 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1860 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1861 break; 1862 case DRM_FORMAT_XRGB4444: 1863 case DRM_FORMAT_ARGB4444: 1864 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1865 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1866 #ifdef __BIG_ENDIAN 1867 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1868 ENDIAN_8IN16); 1869 #endif 1870 break; 1871 case DRM_FORMAT_XRGB1555: 1872 case DRM_FORMAT_ARGB1555: 1873 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1874 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1875 #ifdef __BIG_ENDIAN 1876 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1877 ENDIAN_8IN16); 1878 #endif 1879 break; 1880 case DRM_FORMAT_BGRX5551: 1881 case DRM_FORMAT_BGRA5551: 1882 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1883 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1884 #ifdef __BIG_ENDIAN 1885 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1886 ENDIAN_8IN16); 1887 #endif 1888 break; 1889 case DRM_FORMAT_RGB565: 1890 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1891 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1892 #ifdef __BIG_ENDIAN 1893 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1894 ENDIAN_8IN16); 1895 #endif 1896 break; 1897 case DRM_FORMAT_XRGB8888: 1898 case DRM_FORMAT_ARGB8888: 1899 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1900 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1901 #ifdef __BIG_ENDIAN 1902 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1903 ENDIAN_8IN32); 1904 #endif 1905 break; 1906 case DRM_FORMAT_XRGB2101010: 1907 case DRM_FORMAT_ARGB2101010: 1908 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1909 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1910 #ifdef __BIG_ENDIAN 1911 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1912 ENDIAN_8IN32); 1913 #endif 1914 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1915 bypass_lut = true; 1916 break; 1917 case DRM_FORMAT_BGRX1010102: 1918 case DRM_FORMAT_BGRA1010102: 1919 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1920 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 1921 #ifdef __BIG_ENDIAN 1922 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1923 ENDIAN_8IN32); 1924 #endif 1925 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1926 bypass_lut = true; 1927 break; 1928 case DRM_FORMAT_XBGR8888: 1929 case DRM_FORMAT_ABGR8888: 1930 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1931 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1932 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); 1933 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); 1934 #ifdef __BIG_ENDIAN 1935 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1936 ENDIAN_8IN32); 1937 #endif 1938 break; 1939 default: 1940 DRM_ERROR("Unsupported screen format %p4cc\n", 1941 &target_fb->format->format); 1942 return -EINVAL; 1943 } 1944 1945 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1946 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1947 1948 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1949 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1950 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1951 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1952 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1953 1954 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 1955 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 1956 ARRAY_2D_TILED_THIN1); 1957 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 1958 tile_split); 1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 1960 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 1961 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 1962 mtaspect); 1963 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 1964 ADDR_SURF_MICRO_TILING_DISPLAY); 1965 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1966 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 1967 ARRAY_1D_TILED_THIN1); 1968 } 1969 1970 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 1971 pipe_config); 1972 1973 dce_v10_0_vga_enable(crtc, false); 1974 1975 /* Make sure surface address is updated at vertical blank rather than 1976 * horizontal blank 1977 */ 1978 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 1979 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 1980 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 1981 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1982 1983 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1984 upper_32_bits(fb_location)); 1985 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1986 upper_32_bits(fb_location)); 1987 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1988 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1989 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1990 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 1991 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1992 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 1993 1994 /* 1995 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1996 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1997 * retain the full precision throughout the pipeline. 1998 */ 1999 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2000 if (bypass_lut) 2001 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2002 else 2003 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2004 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2005 2006 if (bypass_lut) 2007 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2008 2009 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2010 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2011 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2012 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2013 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2014 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2015 2016 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2017 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2018 2019 dce_v10_0_grph_enable(crtc, true); 2020 2021 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2022 target_fb->height); 2023 2024 x &= ~3; 2025 y &= ~1; 2026 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2027 (x << 16) | y); 2028 viewport_w = crtc->mode.hdisplay; 2029 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2030 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2031 (viewport_w << 16) | viewport_h); 2032 2033 /* set pageflip to happen anywhere in vblank interval */ 2034 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2035 2036 if (fb && fb != crtc->primary->fb) { 2037 abo = gem_to_amdgpu_bo(fb->obj[0]); 2038 r = amdgpu_bo_reserve(abo, true); 2039 if (unlikely(r != 0)) 2040 return r; 2041 amdgpu_bo_unpin(abo); 2042 amdgpu_bo_unreserve(abo); 2043 } 2044 2045 /* Bytes per pixel may have changed */ 2046 dce_v10_0_bandwidth_update(adev); 2047 2048 return 0; 2049 } 2050 2051 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2052 struct drm_display_mode *mode) 2053 { 2054 struct drm_device *dev = crtc->dev; 2055 struct amdgpu_device *adev = drm_to_adev(dev); 2056 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2057 u32 tmp; 2058 2059 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2060 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2061 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2062 else 2063 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2064 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2065 } 2066 2067 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2068 { 2069 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2070 struct drm_device *dev = crtc->dev; 2071 struct amdgpu_device *adev = drm_to_adev(dev); 2072 u16 *r, *g, *b; 2073 int i; 2074 u32 tmp; 2075 2076 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2077 2078 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2079 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2080 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2081 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2082 2083 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2084 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2085 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2086 2087 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2088 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2089 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2090 2091 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2092 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2093 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2094 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2095 2096 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2097 2098 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2099 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2100 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2101 2102 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2103 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2104 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2105 2106 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2107 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2108 2109 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2110 r = crtc->gamma_store; 2111 g = r + crtc->gamma_size; 2112 b = g + crtc->gamma_size; 2113 for (i = 0; i < 256; i++) { 2114 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2115 ((*r++ & 0xffc0) << 14) | 2116 ((*g++ & 0xffc0) << 4) | 2117 (*b++ >> 6)); 2118 } 2119 2120 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2121 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2122 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2123 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2124 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2125 2126 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2127 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2128 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2129 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2130 2131 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2132 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2133 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2134 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2135 2136 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2137 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2138 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2139 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2140 2141 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2142 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2143 /* XXX this only needs to be programmed once per crtc at startup, 2144 * not sure where the best place for it is 2145 */ 2146 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2147 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2148 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2149 } 2150 2151 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2152 { 2153 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2154 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2155 2156 switch (amdgpu_encoder->encoder_id) { 2157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2158 if (dig->linkb) 2159 return 1; 2160 else 2161 return 0; 2162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2163 if (dig->linkb) 2164 return 3; 2165 else 2166 return 2; 2167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2168 if (dig->linkb) 2169 return 5; 2170 else 2171 return 4; 2172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2173 return 6; 2174 default: 2175 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2176 return 0; 2177 } 2178 } 2179 2180 /** 2181 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2182 * 2183 * @crtc: drm crtc 2184 * 2185 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2186 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2187 * monitors a dedicated PPLL must be used. If a particular board has 2188 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2189 * as there is no need to program the PLL itself. If we are not able to 2190 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2191 * avoid messing up an existing monitor. 2192 * 2193 * Asic specific PLL information 2194 * 2195 * DCE 10.x 2196 * Tonga 2197 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2198 * CI 2199 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2200 * 2201 */ 2202 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2203 { 2204 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2205 struct drm_device *dev = crtc->dev; 2206 struct amdgpu_device *adev = drm_to_adev(dev); 2207 u32 pll_in_use; 2208 int pll; 2209 2210 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2211 if (adev->clock.dp_extclk) 2212 /* skip PPLL programming if using ext clock */ 2213 return ATOM_PPLL_INVALID; 2214 else { 2215 /* use the same PPLL for all DP monitors */ 2216 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2217 if (pll != ATOM_PPLL_INVALID) 2218 return pll; 2219 } 2220 } else { 2221 /* use the same PPLL for all monitors with the same clock */ 2222 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2223 if (pll != ATOM_PPLL_INVALID) 2224 return pll; 2225 } 2226 2227 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2228 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2229 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2230 return ATOM_PPLL2; 2231 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2232 return ATOM_PPLL1; 2233 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2234 return ATOM_PPLL0; 2235 DRM_ERROR("unable to allocate a PPLL\n"); 2236 return ATOM_PPLL_INVALID; 2237 } 2238 2239 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2240 { 2241 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2242 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2243 uint32_t cur_lock; 2244 2245 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2246 if (lock) 2247 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2248 else 2249 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2250 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2251 } 2252 2253 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2254 { 2255 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2256 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2257 u32 tmp; 2258 2259 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2260 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2261 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2262 } 2263 2264 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2265 { 2266 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2267 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2268 u32 tmp; 2269 2270 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2271 upper_32_bits(amdgpu_crtc->cursor_addr)); 2272 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2273 lower_32_bits(amdgpu_crtc->cursor_addr)); 2274 2275 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2276 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2277 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2278 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2279 } 2280 2281 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 2282 int x, int y) 2283 { 2284 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2285 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2286 int xorigin = 0, yorigin = 0; 2287 2288 amdgpu_crtc->cursor_x = x; 2289 amdgpu_crtc->cursor_y = y; 2290 2291 /* avivo cursor are offset into the total surface */ 2292 x += crtc->x; 2293 y += crtc->y; 2294 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2295 2296 if (x < 0) { 2297 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2298 x = 0; 2299 } 2300 if (y < 0) { 2301 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2302 y = 0; 2303 } 2304 2305 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2306 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2307 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2308 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2309 2310 return 0; 2311 } 2312 2313 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2314 int x, int y) 2315 { 2316 int ret; 2317 2318 dce_v10_0_lock_cursor(crtc, true); 2319 ret = dce_v10_0_cursor_move_locked(crtc, x, y); 2320 dce_v10_0_lock_cursor(crtc, false); 2321 2322 return ret; 2323 } 2324 2325 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 2326 struct drm_file *file_priv, 2327 uint32_t handle, 2328 uint32_t width, 2329 uint32_t height, 2330 int32_t hot_x, 2331 int32_t hot_y) 2332 { 2333 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2334 struct drm_gem_object *obj; 2335 struct amdgpu_bo *aobj; 2336 int ret; 2337 2338 if (!handle) { 2339 /* turn off cursor */ 2340 dce_v10_0_hide_cursor(crtc); 2341 obj = NULL; 2342 goto unpin; 2343 } 2344 2345 if ((width > amdgpu_crtc->max_cursor_width) || 2346 (height > amdgpu_crtc->max_cursor_height)) { 2347 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2348 return -EINVAL; 2349 } 2350 2351 obj = drm_gem_object_lookup(file_priv, handle); 2352 if (!obj) { 2353 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2354 return -ENOENT; 2355 } 2356 2357 aobj = gem_to_amdgpu_bo(obj); 2358 ret = amdgpu_bo_reserve(aobj, false); 2359 if (ret != 0) { 2360 drm_gem_object_put(obj); 2361 return ret; 2362 } 2363 2364 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 2365 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2366 amdgpu_bo_unreserve(aobj); 2367 if (ret) { 2368 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2369 drm_gem_object_put(obj); 2370 return ret; 2371 } 2372 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2373 2374 dce_v10_0_lock_cursor(crtc, true); 2375 2376 if (width != amdgpu_crtc->cursor_width || 2377 height != amdgpu_crtc->cursor_height || 2378 hot_x != amdgpu_crtc->cursor_hot_x || 2379 hot_y != amdgpu_crtc->cursor_hot_y) { 2380 int x, y; 2381 2382 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2383 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2384 2385 dce_v10_0_cursor_move_locked(crtc, x, y); 2386 2387 amdgpu_crtc->cursor_width = width; 2388 amdgpu_crtc->cursor_height = height; 2389 amdgpu_crtc->cursor_hot_x = hot_x; 2390 amdgpu_crtc->cursor_hot_y = hot_y; 2391 } 2392 2393 dce_v10_0_show_cursor(crtc); 2394 dce_v10_0_lock_cursor(crtc, false); 2395 2396 unpin: 2397 if (amdgpu_crtc->cursor_bo) { 2398 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2399 ret = amdgpu_bo_reserve(aobj, true); 2400 if (likely(ret == 0)) { 2401 amdgpu_bo_unpin(aobj); 2402 amdgpu_bo_unreserve(aobj); 2403 } 2404 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2405 } 2406 2407 amdgpu_crtc->cursor_bo = obj; 2408 return 0; 2409 } 2410 2411 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2412 { 2413 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2414 2415 if (amdgpu_crtc->cursor_bo) { 2416 dce_v10_0_lock_cursor(crtc, true); 2417 2418 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2419 amdgpu_crtc->cursor_y); 2420 2421 dce_v10_0_show_cursor(crtc); 2422 2423 dce_v10_0_lock_cursor(crtc, false); 2424 } 2425 } 2426 2427 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2428 u16 *blue, uint32_t size, 2429 struct drm_modeset_acquire_ctx *ctx) 2430 { 2431 dce_v10_0_crtc_load_lut(crtc); 2432 2433 return 0; 2434 } 2435 2436 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2437 { 2438 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2439 2440 drm_crtc_cleanup(crtc); 2441 kfree(amdgpu_crtc); 2442 } 2443 2444 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2445 .cursor_set2 = dce_v10_0_crtc_cursor_set2, 2446 .cursor_move = dce_v10_0_crtc_cursor_move, 2447 .gamma_set = dce_v10_0_crtc_gamma_set, 2448 .set_config = amdgpu_display_crtc_set_config, 2449 .destroy = dce_v10_0_crtc_destroy, 2450 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2451 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2452 .enable_vblank = amdgpu_enable_vblank_kms, 2453 .disable_vblank = amdgpu_disable_vblank_kms, 2454 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2455 }; 2456 2457 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2458 { 2459 struct drm_device *dev = crtc->dev; 2460 struct amdgpu_device *adev = drm_to_adev(dev); 2461 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2462 unsigned type; 2463 2464 switch (mode) { 2465 case DRM_MODE_DPMS_ON: 2466 amdgpu_crtc->enabled = true; 2467 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2468 dce_v10_0_vga_enable(crtc, true); 2469 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2470 dce_v10_0_vga_enable(crtc, false); 2471 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2472 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2473 amdgpu_crtc->crtc_id); 2474 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2475 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2476 drm_crtc_vblank_on(crtc); 2477 dce_v10_0_crtc_load_lut(crtc); 2478 break; 2479 case DRM_MODE_DPMS_STANDBY: 2480 case DRM_MODE_DPMS_SUSPEND: 2481 case DRM_MODE_DPMS_OFF: 2482 drm_crtc_vblank_off(crtc); 2483 if (amdgpu_crtc->enabled) { 2484 dce_v10_0_vga_enable(crtc, true); 2485 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2486 dce_v10_0_vga_enable(crtc, false); 2487 } 2488 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2489 amdgpu_crtc->enabled = false; 2490 break; 2491 } 2492 /* adjust pm to dpms */ 2493 amdgpu_dpm_compute_clocks(adev); 2494 } 2495 2496 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2497 { 2498 /* disable crtc pair power gating before programming */ 2499 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2500 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2501 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2502 } 2503 2504 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2505 { 2506 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2507 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2508 } 2509 2510 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2511 { 2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2513 struct drm_device *dev = crtc->dev; 2514 struct amdgpu_device *adev = drm_to_adev(dev); 2515 struct amdgpu_atom_ss ss; 2516 int i; 2517 2518 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2519 if (crtc->primary->fb) { 2520 int r; 2521 struct amdgpu_bo *abo; 2522 2523 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2524 r = amdgpu_bo_reserve(abo, true); 2525 if (unlikely(r)) 2526 DRM_ERROR("failed to reserve abo before unpin\n"); 2527 else { 2528 amdgpu_bo_unpin(abo); 2529 amdgpu_bo_unreserve(abo); 2530 } 2531 } 2532 /* disable the GRPH */ 2533 dce_v10_0_grph_enable(crtc, false); 2534 2535 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2536 2537 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2538 if (adev->mode_info.crtcs[i] && 2539 adev->mode_info.crtcs[i]->enabled && 2540 i != amdgpu_crtc->crtc_id && 2541 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2542 /* one other crtc is using this pll don't turn 2543 * off the pll 2544 */ 2545 goto done; 2546 } 2547 } 2548 2549 switch (amdgpu_crtc->pll_id) { 2550 case ATOM_PPLL0: 2551 case ATOM_PPLL1: 2552 case ATOM_PPLL2: 2553 /* disable the ppll */ 2554 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2555 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2556 break; 2557 default: 2558 break; 2559 } 2560 done: 2561 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2562 amdgpu_crtc->adjusted_clock = 0; 2563 amdgpu_crtc->encoder = NULL; 2564 amdgpu_crtc->connector = NULL; 2565 } 2566 2567 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2568 struct drm_display_mode *mode, 2569 struct drm_display_mode *adjusted_mode, 2570 int x, int y, struct drm_framebuffer *old_fb) 2571 { 2572 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2573 2574 if (!amdgpu_crtc->adjusted_clock) 2575 return -EINVAL; 2576 2577 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2578 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2579 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); 2580 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2581 amdgpu_atombios_crtc_scaler_setup(crtc); 2582 dce_v10_0_cursor_reset(crtc); 2583 /* update the hw version fpr dpm */ 2584 amdgpu_crtc->hw_mode = *adjusted_mode; 2585 2586 return 0; 2587 } 2588 2589 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2590 const struct drm_display_mode *mode, 2591 struct drm_display_mode *adjusted_mode) 2592 { 2593 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2594 struct drm_device *dev = crtc->dev; 2595 struct drm_encoder *encoder; 2596 2597 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2598 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2599 if (encoder->crtc == crtc) { 2600 amdgpu_crtc->encoder = encoder; 2601 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2602 break; 2603 } 2604 } 2605 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2606 amdgpu_crtc->encoder = NULL; 2607 amdgpu_crtc->connector = NULL; 2608 return false; 2609 } 2610 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2611 return false; 2612 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2613 return false; 2614 /* pick pll */ 2615 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2616 /* if we can't get a PPLL for a non-DP encoder, fail */ 2617 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2618 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2619 return false; 2620 2621 return true; 2622 } 2623 2624 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2625 struct drm_framebuffer *old_fb) 2626 { 2627 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); 2628 } 2629 2630 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2631 .dpms = dce_v10_0_crtc_dpms, 2632 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2633 .mode_set = dce_v10_0_crtc_mode_set, 2634 .mode_set_base = dce_v10_0_crtc_set_base, 2635 .prepare = dce_v10_0_crtc_prepare, 2636 .commit = dce_v10_0_crtc_commit, 2637 .disable = dce_v10_0_crtc_disable, 2638 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2639 }; 2640 2641 static void dce_v10_0_panic_flush(struct drm_plane *plane) 2642 { 2643 struct drm_framebuffer *fb; 2644 struct amdgpu_crtc *amdgpu_crtc; 2645 struct amdgpu_device *adev; 2646 uint32_t fb_format; 2647 2648 if (!plane->fb) 2649 return; 2650 2651 fb = plane->fb; 2652 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); 2653 adev = drm_to_adev(fb->dev); 2654 2655 /* Disable DC tiling */ 2656 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); 2657 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; 2658 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2659 2660 } 2661 2662 static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_funcs = { 2663 .get_scanout_buffer = amdgpu_display_get_scanout_buffer, 2664 .panic_flush = dce_v10_0_panic_flush, 2665 }; 2666 2667 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2668 { 2669 struct amdgpu_crtc *amdgpu_crtc; 2670 2671 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2672 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2673 if (amdgpu_crtc == NULL) 2674 return -ENOMEM; 2675 2676 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2677 2678 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2679 amdgpu_crtc->crtc_id = index; 2680 adev->mode_info.crtcs[index] = amdgpu_crtc; 2681 2682 amdgpu_crtc->max_cursor_width = 128; 2683 amdgpu_crtc->max_cursor_height = 128; 2684 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2685 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2686 2687 switch (amdgpu_crtc->crtc_id) { 2688 case 0: 2689 default: 2690 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2691 break; 2692 case 1: 2693 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2694 break; 2695 case 2: 2696 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2697 break; 2698 case 3: 2699 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2700 break; 2701 case 4: 2702 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2703 break; 2704 case 5: 2705 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2706 break; 2707 } 2708 2709 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2710 amdgpu_crtc->adjusted_clock = 0; 2711 amdgpu_crtc->encoder = NULL; 2712 amdgpu_crtc->connector = NULL; 2713 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2714 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs); 2715 2716 return 0; 2717 } 2718 2719 static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block) 2720 { 2721 struct amdgpu_device *adev = ip_block->adev; 2722 2723 adev->reg.audio_endpt.rreg = &dce_v10_0_audio_endpt_rreg; 2724 adev->reg.audio_endpt.wreg = &dce_v10_0_audio_endpt_wreg; 2725 2726 dce_v10_0_set_display_funcs(adev); 2727 2728 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); 2729 2730 switch (adev->asic_type) { 2731 case CHIP_FIJI: 2732 case CHIP_TONGA: 2733 adev->mode_info.num_hpd = 6; 2734 adev->mode_info.num_dig = 7; 2735 break; 2736 default: 2737 /* FIXME: not supported yet */ 2738 return -EINVAL; 2739 } 2740 2741 dce_v10_0_set_irq_funcs(adev); 2742 2743 return 0; 2744 } 2745 2746 static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 2747 { 2748 int r, i; 2749 struct amdgpu_device *adev = ip_block->adev; 2750 2751 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2752 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2753 if (r) 2754 return r; 2755 } 2756 2757 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2758 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2759 if (r) 2760 return r; 2761 } 2762 2763 /* HPD hotplug */ 2764 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2765 if (r) 2766 return r; 2767 2768 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2769 2770 adev_to_drm(adev)->mode_config.async_page_flip = true; 2771 2772 adev_to_drm(adev)->mode_config.max_width = 16384; 2773 adev_to_drm(adev)->mode_config.max_height = 16384; 2774 2775 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2776 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2777 2778 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2779 2780 r = amdgpu_display_modeset_create_props(adev); 2781 if (r) 2782 return r; 2783 2784 adev_to_drm(adev)->mode_config.max_width = 16384; 2785 adev_to_drm(adev)->mode_config.max_height = 16384; 2786 2787 /* allocate crtcs */ 2788 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2789 r = dce_v10_0_crtc_init(adev, i); 2790 if (r) 2791 return r; 2792 } 2793 2794 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2795 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2796 else 2797 return -EINVAL; 2798 2799 /* setup afmt */ 2800 r = dce_v10_0_afmt_init(adev); 2801 if (r) 2802 return r; 2803 2804 r = dce_v10_0_audio_init(adev); 2805 if (r) 2806 return r; 2807 2808 /* Disable vblank IRQs aggressively for power-saving */ 2809 /* XXX: can this be enabled for DC? */ 2810 adev_to_drm(adev)->vblank_disable_immediate = true; 2811 2812 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2813 if (r) 2814 return r; 2815 2816 INIT_DELAYED_WORK(&adev->hotplug_work, 2817 amdgpu_display_hotplug_work_func); 2818 2819 drm_kms_helper_poll_init(adev_to_drm(adev)); 2820 2821 adev->mode_info.mode_config_initialized = true; 2822 return 0; 2823 } 2824 2825 static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 2826 { 2827 struct amdgpu_device *adev = ip_block->adev; 2828 2829 drm_edid_free(adev->mode_info.bios_hardcoded_edid); 2830 2831 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2832 2833 dce_v10_0_audio_fini(adev); 2834 2835 dce_v10_0_afmt_fini(adev); 2836 2837 drm_mode_config_cleanup(adev_to_drm(adev)); 2838 adev->mode_info.mode_config_initialized = false; 2839 2840 return 0; 2841 } 2842 2843 static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 2844 { 2845 int i; 2846 struct amdgpu_device *adev = ip_block->adev; 2847 2848 dce_v10_0_init_golden_registers(adev); 2849 2850 /* disable vga render */ 2851 dce_v10_0_set_vga_render_state(adev, false); 2852 /* init dig PHYs, disp eng pll */ 2853 amdgpu_atombios_encoder_init_dig(adev); 2854 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2855 2856 /* initialize hpd */ 2857 dce_v10_0_hpd_init(adev); 2858 2859 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2860 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2861 } 2862 2863 dce_v10_0_pageflip_interrupt_init(adev); 2864 2865 return 0; 2866 } 2867 2868 static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 2869 { 2870 int i; 2871 struct amdgpu_device *adev = ip_block->adev; 2872 2873 dce_v10_0_hpd_fini(adev); 2874 2875 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2876 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2877 } 2878 2879 dce_v10_0_pageflip_interrupt_fini(adev); 2880 2881 flush_delayed_work(&adev->hotplug_work); 2882 2883 return 0; 2884 } 2885 2886 static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block) 2887 { 2888 struct amdgpu_device *adev = ip_block->adev; 2889 int r; 2890 2891 r = amdgpu_display_suspend_helper(adev); 2892 if (r) 2893 return r; 2894 2895 adev->mode_info.bl_level = 2896 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2897 2898 return dce_v10_0_hw_fini(ip_block); 2899 } 2900 2901 static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block) 2902 { 2903 struct amdgpu_device *adev = ip_block->adev; 2904 int ret; 2905 2906 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2907 adev->mode_info.bl_level); 2908 2909 ret = dce_v10_0_hw_init(ip_block); 2910 2911 /* turn on the BL */ 2912 if (adev->mode_info.bl_encoder) { 2913 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2914 adev->mode_info.bl_encoder); 2915 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2916 bl_level); 2917 } 2918 if (ret) 2919 return ret; 2920 2921 return amdgpu_display_resume_helper(adev); 2922 } 2923 2924 static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 2925 { 2926 return true; 2927 } 2928 2929 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2930 int crtc, 2931 enum amdgpu_interrupt_state state) 2932 { 2933 u32 lb_interrupt_mask; 2934 2935 if (crtc >= adev->mode_info.num_crtc) { 2936 DRM_DEBUG("invalid crtc %d\n", crtc); 2937 return; 2938 } 2939 2940 switch (state) { 2941 case AMDGPU_IRQ_STATE_DISABLE: 2942 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2943 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2944 VBLANK_INTERRUPT_MASK, 0); 2945 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2946 break; 2947 case AMDGPU_IRQ_STATE_ENABLE: 2948 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2949 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2950 VBLANK_INTERRUPT_MASK, 1); 2951 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2952 break; 2953 default: 2954 break; 2955 } 2956 } 2957 2958 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2959 int crtc, 2960 enum amdgpu_interrupt_state state) 2961 { 2962 u32 lb_interrupt_mask; 2963 2964 if (crtc >= adev->mode_info.num_crtc) { 2965 DRM_DEBUG("invalid crtc %d\n", crtc); 2966 return; 2967 } 2968 2969 switch (state) { 2970 case AMDGPU_IRQ_STATE_DISABLE: 2971 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2972 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2973 VLINE_INTERRUPT_MASK, 0); 2974 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2975 break; 2976 case AMDGPU_IRQ_STATE_ENABLE: 2977 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2978 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2979 VLINE_INTERRUPT_MASK, 1); 2980 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2981 break; 2982 default: 2983 break; 2984 } 2985 } 2986 2987 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 2988 struct amdgpu_irq_src *source, 2989 unsigned hpd, 2990 enum amdgpu_interrupt_state state) 2991 { 2992 u32 tmp; 2993 2994 if (hpd >= adev->mode_info.num_hpd) { 2995 DRM_DEBUG("invalid hpd %d\n", hpd); 2996 return 0; 2997 } 2998 2999 switch (state) { 3000 case AMDGPU_IRQ_STATE_DISABLE: 3001 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3002 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3003 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3004 break; 3005 case AMDGPU_IRQ_STATE_ENABLE: 3006 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3007 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3008 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3009 break; 3010 default: 3011 break; 3012 } 3013 3014 return 0; 3015 } 3016 3017 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3018 struct amdgpu_irq_src *source, 3019 unsigned type, 3020 enum amdgpu_interrupt_state state) 3021 { 3022 switch (type) { 3023 case AMDGPU_CRTC_IRQ_VBLANK1: 3024 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3025 break; 3026 case AMDGPU_CRTC_IRQ_VBLANK2: 3027 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3028 break; 3029 case AMDGPU_CRTC_IRQ_VBLANK3: 3030 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3031 break; 3032 case AMDGPU_CRTC_IRQ_VBLANK4: 3033 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3034 break; 3035 case AMDGPU_CRTC_IRQ_VBLANK5: 3036 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3037 break; 3038 case AMDGPU_CRTC_IRQ_VBLANK6: 3039 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3040 break; 3041 case AMDGPU_CRTC_IRQ_VLINE1: 3042 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3043 break; 3044 case AMDGPU_CRTC_IRQ_VLINE2: 3045 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3046 break; 3047 case AMDGPU_CRTC_IRQ_VLINE3: 3048 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3049 break; 3050 case AMDGPU_CRTC_IRQ_VLINE4: 3051 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3052 break; 3053 case AMDGPU_CRTC_IRQ_VLINE5: 3054 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3055 break; 3056 case AMDGPU_CRTC_IRQ_VLINE6: 3057 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3058 break; 3059 default: 3060 break; 3061 } 3062 return 0; 3063 } 3064 3065 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3066 struct amdgpu_irq_src *src, 3067 unsigned type, 3068 enum amdgpu_interrupt_state state) 3069 { 3070 u32 reg; 3071 3072 if (type >= adev->mode_info.num_crtc) { 3073 DRM_ERROR("invalid pageflip crtc %d\n", type); 3074 return -EINVAL; 3075 } 3076 3077 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3078 if (state == AMDGPU_IRQ_STATE_DISABLE) 3079 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3080 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3081 else 3082 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3083 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3084 3085 return 0; 3086 } 3087 3088 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3089 struct amdgpu_irq_src *source, 3090 struct amdgpu_iv_entry *entry) 3091 { 3092 unsigned long flags; 3093 unsigned crtc_id; 3094 struct amdgpu_crtc *amdgpu_crtc; 3095 struct amdgpu_flip_work *works; 3096 3097 crtc_id = (entry->src_id - 8) >> 1; 3098 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3099 3100 if (crtc_id >= adev->mode_info.num_crtc) { 3101 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3102 return -EINVAL; 3103 } 3104 3105 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3106 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3107 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3108 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3109 3110 /* IRQ could occur when in initial stage */ 3111 if (amdgpu_crtc == NULL) 3112 return 0; 3113 3114 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3115 works = amdgpu_crtc->pflip_works; 3116 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3117 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3118 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3119 amdgpu_crtc->pflip_status, 3120 AMDGPU_FLIP_SUBMITTED); 3121 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3122 return 0; 3123 } 3124 3125 /* page flip completed. clean up */ 3126 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3127 amdgpu_crtc->pflip_works = NULL; 3128 3129 /* wakeup usersapce */ 3130 if (works->event) 3131 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3132 3133 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3134 3135 drm_crtc_vblank_put(&amdgpu_crtc->base); 3136 schedule_work(&works->unpin_work); 3137 3138 return 0; 3139 } 3140 3141 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3142 int hpd) 3143 { 3144 u32 tmp; 3145 3146 if (hpd >= adev->mode_info.num_hpd) { 3147 DRM_DEBUG("invalid hpd %d\n", hpd); 3148 return; 3149 } 3150 3151 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3152 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3153 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3154 } 3155 3156 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3157 int crtc) 3158 { 3159 u32 tmp; 3160 3161 if (crtc >= adev->mode_info.num_crtc) { 3162 DRM_DEBUG("invalid crtc %d\n", crtc); 3163 return; 3164 } 3165 3166 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3167 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3168 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3169 } 3170 3171 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3172 int crtc) 3173 { 3174 u32 tmp; 3175 3176 if (crtc >= adev->mode_info.num_crtc) { 3177 DRM_DEBUG("invalid crtc %d\n", crtc); 3178 return; 3179 } 3180 3181 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3182 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3183 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3184 } 3185 3186 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3187 struct amdgpu_irq_src *source, 3188 struct amdgpu_iv_entry *entry) 3189 { 3190 unsigned crtc = entry->src_id - 1; 3191 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3192 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc); 3193 3194 switch (entry->src_data[0]) { 3195 case 0: /* vblank */ 3196 if (disp_int & interrupt_status_offsets[crtc].vblank) 3197 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3198 else 3199 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3200 3201 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3202 drm_handle_vblank(adev_to_drm(adev), crtc); 3203 } 3204 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3205 3206 break; 3207 case 1: /* vline */ 3208 if (disp_int & interrupt_status_offsets[crtc].vline) 3209 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3210 else 3211 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3212 3213 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3214 3215 break; 3216 default: 3217 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3218 break; 3219 } 3220 3221 return 0; 3222 } 3223 3224 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3225 struct amdgpu_irq_src *source, 3226 struct amdgpu_iv_entry *entry) 3227 { 3228 uint32_t disp_int, mask; 3229 unsigned hpd; 3230 3231 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3232 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3233 return 0; 3234 } 3235 3236 hpd = entry->src_data[0]; 3237 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3238 mask = interrupt_status_offsets[hpd].hpd; 3239 3240 if (disp_int & mask) { 3241 dce_v10_0_hpd_int_ack(adev, hpd); 3242 schedule_delayed_work(&adev->hotplug_work, 0); 3243 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3244 } 3245 3246 return 0; 3247 } 3248 3249 static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3250 enum amd_clockgating_state state) 3251 { 3252 return 0; 3253 } 3254 3255 static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 3256 enum amd_powergating_state state) 3257 { 3258 return 0; 3259 } 3260 3261 static const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3262 .name = "dce_v10_0", 3263 .early_init = dce_v10_0_early_init, 3264 .sw_init = dce_v10_0_sw_init, 3265 .sw_fini = dce_v10_0_sw_fini, 3266 .hw_init = dce_v10_0_hw_init, 3267 .hw_fini = dce_v10_0_hw_fini, 3268 .suspend = dce_v10_0_suspend, 3269 .resume = dce_v10_0_resume, 3270 .is_idle = dce_v10_0_is_idle, 3271 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3272 .set_powergating_state = dce_v10_0_set_powergating_state, 3273 }; 3274 3275 static void 3276 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3277 struct drm_display_mode *mode, 3278 struct drm_display_mode *adjusted_mode) 3279 { 3280 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3281 3282 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3283 3284 /* need to call this here rather than in prepare() since we need some crtc info */ 3285 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3286 3287 /* set scaler clears this on some chips */ 3288 dce_v10_0_set_interleave(encoder->crtc, mode); 3289 3290 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3291 dce_v10_0_afmt_enable(encoder, true); 3292 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3293 } 3294 } 3295 3296 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3297 { 3298 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3299 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3300 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3301 3302 if ((amdgpu_encoder->active_device & 3303 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3304 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3305 ENCODER_OBJECT_ID_NONE)) { 3306 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3307 if (dig) { 3308 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3309 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3310 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3311 } 3312 } 3313 3314 amdgpu_atombios_scratch_regs_lock(adev, true); 3315 3316 if (connector) { 3317 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3318 3319 /* select the clock/data port if it uses a router */ 3320 if (amdgpu_connector->router.cd_valid) 3321 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3322 3323 /* turn eDP panel on for mode set */ 3324 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3325 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3326 ATOM_TRANSMITTER_ACTION_POWER_ON); 3327 } 3328 3329 /* this is needed for the pll/ss setup to work correctly in some cases */ 3330 amdgpu_atombios_encoder_set_crtc_source(encoder); 3331 /* set up the FMT blocks */ 3332 dce_v10_0_program_fmt(encoder); 3333 } 3334 3335 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3336 { 3337 struct drm_device *dev = encoder->dev; 3338 struct amdgpu_device *adev = drm_to_adev(dev); 3339 3340 /* need to call this here as we need the crtc set up */ 3341 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3342 amdgpu_atombios_scratch_regs_lock(adev, false); 3343 } 3344 3345 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3346 { 3347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3348 struct amdgpu_encoder_atom_dig *dig; 3349 3350 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3351 3352 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3353 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3354 dce_v10_0_afmt_enable(encoder, false); 3355 dig = amdgpu_encoder->enc_priv; 3356 dig->dig_encoder = -1; 3357 } 3358 amdgpu_encoder->active_device = 0; 3359 } 3360 3361 /* these are handled by the primary encoders */ 3362 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3363 { 3364 3365 } 3366 3367 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3368 { 3369 3370 } 3371 3372 static void 3373 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3374 struct drm_display_mode *mode, 3375 struct drm_display_mode *adjusted_mode) 3376 { 3377 3378 } 3379 3380 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3381 { 3382 3383 } 3384 3385 static void 3386 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3387 { 3388 3389 } 3390 3391 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3392 .dpms = dce_v10_0_ext_dpms, 3393 .prepare = dce_v10_0_ext_prepare, 3394 .mode_set = dce_v10_0_ext_mode_set, 3395 .commit = dce_v10_0_ext_commit, 3396 .disable = dce_v10_0_ext_disable, 3397 /* no detect for TMDS/LVDS yet */ 3398 }; 3399 3400 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3401 .dpms = amdgpu_atombios_encoder_dpms, 3402 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3403 .prepare = dce_v10_0_encoder_prepare, 3404 .mode_set = dce_v10_0_encoder_mode_set, 3405 .commit = dce_v10_0_encoder_commit, 3406 .disable = dce_v10_0_encoder_disable, 3407 .detect = amdgpu_atombios_encoder_dig_detect, 3408 }; 3409 3410 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3411 .dpms = amdgpu_atombios_encoder_dpms, 3412 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3413 .prepare = dce_v10_0_encoder_prepare, 3414 .mode_set = dce_v10_0_encoder_mode_set, 3415 .commit = dce_v10_0_encoder_commit, 3416 .detect = amdgpu_atombios_encoder_dac_detect, 3417 }; 3418 3419 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3420 { 3421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3422 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3423 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3424 kfree(amdgpu_encoder->enc_priv); 3425 drm_encoder_cleanup(encoder); 3426 kfree(amdgpu_encoder); 3427 } 3428 3429 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3430 .destroy = dce_v10_0_encoder_destroy, 3431 }; 3432 3433 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3434 uint32_t encoder_enum, 3435 uint32_t supported_device, 3436 u16 caps) 3437 { 3438 struct drm_device *dev = adev_to_drm(adev); 3439 struct drm_encoder *encoder; 3440 struct amdgpu_encoder *amdgpu_encoder; 3441 3442 /* see if we already added it */ 3443 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3444 amdgpu_encoder = to_amdgpu_encoder(encoder); 3445 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3446 amdgpu_encoder->devices |= supported_device; 3447 return; 3448 } 3449 3450 } 3451 3452 /* add a new one */ 3453 amdgpu_encoder = kzalloc_obj(struct amdgpu_encoder); 3454 if (!amdgpu_encoder) 3455 return; 3456 3457 encoder = &amdgpu_encoder->base; 3458 switch (adev->mode_info.num_crtc) { 3459 case 1: 3460 encoder->possible_crtcs = 0x1; 3461 break; 3462 case 2: 3463 default: 3464 encoder->possible_crtcs = 0x3; 3465 break; 3466 case 4: 3467 encoder->possible_crtcs = 0xf; 3468 break; 3469 case 6: 3470 encoder->possible_crtcs = 0x3f; 3471 break; 3472 } 3473 3474 amdgpu_encoder->enc_priv = NULL; 3475 3476 amdgpu_encoder->encoder_enum = encoder_enum; 3477 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3478 amdgpu_encoder->devices = supported_device; 3479 amdgpu_encoder->rmx_type = RMX_OFF; 3480 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3481 amdgpu_encoder->is_ext_encoder = false; 3482 amdgpu_encoder->caps = caps; 3483 3484 switch (amdgpu_encoder->encoder_id) { 3485 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3486 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3487 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3488 DRM_MODE_ENCODER_DAC, NULL); 3489 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3490 break; 3491 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3492 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3493 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3494 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3495 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3496 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3497 amdgpu_encoder->rmx_type = RMX_FULL; 3498 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3499 DRM_MODE_ENCODER_LVDS, NULL); 3500 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3501 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3502 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3503 DRM_MODE_ENCODER_DAC, NULL); 3504 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3505 } else { 3506 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3507 DRM_MODE_ENCODER_TMDS, NULL); 3508 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3509 } 3510 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3511 break; 3512 case ENCODER_OBJECT_ID_SI170B: 3513 case ENCODER_OBJECT_ID_CH7303: 3514 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3515 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3516 case ENCODER_OBJECT_ID_TITFP513: 3517 case ENCODER_OBJECT_ID_VT1623: 3518 case ENCODER_OBJECT_ID_HDMI_SI1930: 3519 case ENCODER_OBJECT_ID_TRAVIS: 3520 case ENCODER_OBJECT_ID_NUTMEG: 3521 /* these are handled by the primary encoders */ 3522 amdgpu_encoder->is_ext_encoder = true; 3523 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3524 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3525 DRM_MODE_ENCODER_LVDS, NULL); 3526 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3527 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3528 DRM_MODE_ENCODER_DAC, NULL); 3529 else 3530 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3531 DRM_MODE_ENCODER_TMDS, NULL); 3532 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3533 break; 3534 } 3535 } 3536 3537 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3538 .bandwidth_update = &dce_v10_0_bandwidth_update, 3539 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3540 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3541 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3542 .hpd_sense = &dce_v10_0_hpd_sense, 3543 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3544 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3545 .page_flip = &dce_v10_0_page_flip, 3546 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3547 .add_encoder = &dce_v10_0_encoder_add, 3548 .add_connector = &amdgpu_connector_add, 3549 }; 3550 3551 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3552 { 3553 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3554 } 3555 3556 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3557 .set = dce_v10_0_set_crtc_irq_state, 3558 .process = dce_v10_0_crtc_irq, 3559 }; 3560 3561 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3562 .set = dce_v10_0_set_pageflip_irq_state, 3563 .process = dce_v10_0_pageflip_irq, 3564 }; 3565 3566 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3567 .set = dce_v10_0_set_hpd_irq_state, 3568 .process = dce_v10_0_hpd_irq, 3569 }; 3570 3571 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3572 { 3573 if (adev->mode_info.num_crtc > 0) 3574 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3575 else 3576 adev->crtc_irq.num_types = 0; 3577 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3578 3579 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3580 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3581 3582 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3583 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3584 } 3585 3586 const struct amdgpu_ip_block_version dce_v10_0_ip_block = { 3587 .type = AMD_IP_BLOCK_TYPE_DCE, 3588 .major = 10, 3589 .minor = 0, 3590 .rev = 0, 3591 .funcs = &dce_v10_0_ip_funcs, 3592 }; 3593 3594 const struct amdgpu_ip_block_version dce_v10_1_ip_block = { 3595 .type = AMD_IP_BLOCK_TYPE_DCE, 3596 .major = 10, 3597 .minor = 1, 3598 .rev = 0, 3599 .funcs = &dce_v10_0_ip_funcs, 3600 }; 3601