1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_10_0_d.h" 36 #include "dce/dce_10_0_sh_mask.h" 37 #include "dce/dce_10_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET 75 }; 76 77 static const struct { 78 uint32_t reg; 79 uint32_t vblank; 80 uint32_t vline; 81 uint32_t hpd; 82 83 } interrupt_status_offsets[] = { { 84 .reg = mmDISP_INTERRUPT_STATUS, 85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 88 }, { 89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 93 }, { 94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 98 }, { 99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 103 }, { 104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 113 } }; 114 115 static const u32 golden_settings_tonga_a11[] = 116 { 117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 119 mmFBC_MISC, 0x1f311fff, 0x12300000, 120 mmHDMI_CONTROL, 0x31000111, 0x00000011, 121 }; 122 123 static const u32 tonga_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 golden_settings_fiji_a10[] = 130 { 131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 133 mmFBC_MISC, 0x1f311fff, 0x12300000, 134 mmHDMI_CONTROL, 0x31000111, 0x00000011, 135 }; 136 137 static const u32 fiji_mgcg_cgcg_init[] = 138 { 139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 141 }; 142 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 144 { 145 switch (adev->asic_type) { 146 case CHIP_FIJI: 147 amdgpu_program_register_sequence(adev, 148 fiji_mgcg_cgcg_init, 149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 150 amdgpu_program_register_sequence(adev, 151 golden_settings_fiji_a10, 152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 153 break; 154 case CHIP_TONGA: 155 amdgpu_program_register_sequence(adev, 156 tonga_mgcg_cgcg_init, 157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 158 amdgpu_program_register_sequence(adev, 159 golden_settings_tonga_a11, 160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 161 break; 162 default: 163 break; 164 } 165 } 166 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 168 u32 block_offset, u32 reg) 169 { 170 unsigned long flags; 171 u32 r; 172 173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 177 178 return r; 179 } 180 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 182 u32 block_offset, u32 reg, u32 v) 183 { 184 unsigned long flags; 185 186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 190 } 191 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 193 { 194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 196 return true; 197 else 198 return false; 199 } 200 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 202 { 203 u32 pos1, pos2; 204 205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 207 208 if (pos1 != pos2) 209 return true; 210 else 211 return false; 212 } 213 214 /** 215 * dce_v10_0_vblank_wait - vblank wait asic callback. 216 * 217 * @adev: amdgpu_device pointer 218 * @crtc: crtc to wait for vblank on 219 * 220 * Wait for vblank on the requested crtc (evergreen+). 221 */ 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) 223 { 224 unsigned i = 0; 225 226 if (crtc >= adev->mode_info.num_crtc) 227 return; 228 229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 230 return; 231 232 /* depending on when we hit vblank, we may be close to active; if so, 233 * wait for another frame. 234 */ 235 while (dce_v10_0_is_in_vblank(adev, crtc)) { 236 if (i++ % 100 == 0) { 237 if (!dce_v10_0_is_counter_moving(adev, crtc)) 238 break; 239 } 240 } 241 242 while (!dce_v10_0_is_in_vblank(adev, crtc)) { 243 if (i++ % 100 == 0) { 244 if (!dce_v10_0_is_counter_moving(adev, crtc)) 245 break; 246 } 247 } 248 } 249 250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 251 { 252 if (crtc >= adev->mode_info.num_crtc) 253 return 0; 254 else 255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 256 } 257 258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 259 { 260 unsigned i; 261 262 /* Enable pflip interrupts */ 263 for (i = 0; i < adev->mode_info.num_crtc; i++) 264 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 265 } 266 267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 268 { 269 unsigned i; 270 271 /* Disable pflip interrupts */ 272 for (i = 0; i < adev->mode_info.num_crtc; i++) 273 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 274 } 275 276 /** 277 * dce_v10_0_page_flip - pageflip callback. 278 * 279 * @adev: amdgpu_device pointer 280 * @crtc_id: crtc to cleanup pageflip on 281 * @crtc_base: new address of the crtc (GPU MC address) 282 * 283 * Triggers the actual pageflip by updating the primary 284 * surface base address. 285 */ 286 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 287 int crtc_id, u64 crtc_base) 288 { 289 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 290 291 /* update the primary scanout address */ 292 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 293 upper_32_bits(crtc_base)); 294 /* writing to the low address triggers the update */ 295 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 296 lower_32_bits(crtc_base)); 297 /* post the write */ 298 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 299 } 300 301 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 302 u32 *vbl, u32 *position) 303 { 304 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 305 return -EINVAL; 306 307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 308 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 309 310 return 0; 311 } 312 313 /** 314 * dce_v10_0_hpd_sense - hpd sense callback. 315 * 316 * @adev: amdgpu_device pointer 317 * @hpd: hpd (hotplug detect) pin 318 * 319 * Checks if a digital monitor is connected (evergreen+). 320 * Returns true if connected, false if not connected. 321 */ 322 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 323 enum amdgpu_hpd_id hpd) 324 { 325 int idx; 326 bool connected = false; 327 328 switch (hpd) { 329 case AMDGPU_HPD_1: 330 idx = 0; 331 break; 332 case AMDGPU_HPD_2: 333 idx = 1; 334 break; 335 case AMDGPU_HPD_3: 336 idx = 2; 337 break; 338 case AMDGPU_HPD_4: 339 idx = 3; 340 break; 341 case AMDGPU_HPD_5: 342 idx = 4; 343 break; 344 case AMDGPU_HPD_6: 345 idx = 5; 346 break; 347 default: 348 return connected; 349 } 350 351 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 352 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 353 connected = true; 354 355 return connected; 356 } 357 358 /** 359 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 360 * 361 * @adev: amdgpu_device pointer 362 * @hpd: hpd (hotplug detect) pin 363 * 364 * Set the polarity of the hpd pin (evergreen+). 365 */ 366 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 367 enum amdgpu_hpd_id hpd) 368 { 369 u32 tmp; 370 bool connected = dce_v10_0_hpd_sense(adev, hpd); 371 int idx; 372 373 switch (hpd) { 374 case AMDGPU_HPD_1: 375 idx = 0; 376 break; 377 case AMDGPU_HPD_2: 378 idx = 1; 379 break; 380 case AMDGPU_HPD_3: 381 idx = 2; 382 break; 383 case AMDGPU_HPD_4: 384 idx = 3; 385 break; 386 case AMDGPU_HPD_5: 387 idx = 4; 388 break; 389 case AMDGPU_HPD_6: 390 idx = 5; 391 break; 392 default: 393 return; 394 } 395 396 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 397 if (connected) 398 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 399 else 400 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 401 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 402 } 403 404 /** 405 * dce_v10_0_hpd_init - hpd setup callback. 406 * 407 * @adev: amdgpu_device pointer 408 * 409 * Setup the hpd pins used by the card (evergreen+). 410 * Enable the pin, set the polarity, and enable the hpd interrupts. 411 */ 412 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 413 { 414 struct drm_device *dev = adev->ddev; 415 struct drm_connector *connector; 416 u32 tmp; 417 int idx; 418 419 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 420 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 421 422 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 423 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 424 /* don't try to enable hpd on eDP or LVDS avoid breaking the 425 * aux dp channel on imac and help (but not completely fix) 426 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 427 * also avoid interrupt storms during dpms. 428 */ 429 continue; 430 } 431 432 switch (amdgpu_connector->hpd.hpd) { 433 case AMDGPU_HPD_1: 434 idx = 0; 435 break; 436 case AMDGPU_HPD_2: 437 idx = 1; 438 break; 439 case AMDGPU_HPD_3: 440 idx = 2; 441 break; 442 case AMDGPU_HPD_4: 443 idx = 3; 444 break; 445 case AMDGPU_HPD_5: 446 idx = 4; 447 break; 448 case AMDGPU_HPD_6: 449 idx = 5; 450 break; 451 default: 452 continue; 453 } 454 455 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 456 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 457 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 458 459 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 460 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 461 DC_HPD_CONNECT_INT_DELAY, 462 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 463 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 464 DC_HPD_DISCONNECT_INT_DELAY, 465 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 466 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 467 468 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 469 amdgpu_irq_get(adev, &adev->hpd_irq, 470 amdgpu_connector->hpd.hpd); 471 } 472 } 473 474 /** 475 * dce_v10_0_hpd_fini - hpd tear down callback. 476 * 477 * @adev: amdgpu_device pointer 478 * 479 * Tear down the hpd pins used by the card (evergreen+). 480 * Disable the hpd interrupts. 481 */ 482 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 483 { 484 struct drm_device *dev = adev->ddev; 485 struct drm_connector *connector; 486 u32 tmp; 487 int idx; 488 489 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 490 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 491 492 switch (amdgpu_connector->hpd.hpd) { 493 case AMDGPU_HPD_1: 494 idx = 0; 495 break; 496 case AMDGPU_HPD_2: 497 idx = 1; 498 break; 499 case AMDGPU_HPD_3: 500 idx = 2; 501 break; 502 case AMDGPU_HPD_4: 503 idx = 3; 504 break; 505 case AMDGPU_HPD_5: 506 idx = 4; 507 break; 508 case AMDGPU_HPD_6: 509 idx = 5; 510 break; 511 default: 512 continue; 513 } 514 515 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 516 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 517 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 518 519 amdgpu_irq_put(adev, &adev->hpd_irq, 520 amdgpu_connector->hpd.hpd); 521 } 522 } 523 524 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 525 { 526 return mmDC_GPIO_HPD_A; 527 } 528 529 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 530 { 531 u32 crtc_hung = 0; 532 u32 crtc_status[6]; 533 u32 i, j, tmp; 534 535 for (i = 0; i < adev->mode_info.num_crtc; i++) { 536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 537 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 538 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 539 crtc_hung |= (1 << i); 540 } 541 } 542 543 for (j = 0; j < 10; j++) { 544 for (i = 0; i < adev->mode_info.num_crtc; i++) { 545 if (crtc_hung & (1 << i)) { 546 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 547 if (tmp != crtc_status[i]) 548 crtc_hung &= ~(1 << i); 549 } 550 } 551 if (crtc_hung == 0) 552 return false; 553 udelay(100); 554 } 555 556 return true; 557 } 558 559 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, 560 struct amdgpu_mode_mc_save *save) 561 { 562 u32 crtc_enabled, tmp; 563 int i; 564 565 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 566 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 567 568 /* disable VGA render */ 569 tmp = RREG32(mmVGA_RENDER_CONTROL); 570 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 571 WREG32(mmVGA_RENDER_CONTROL, tmp); 572 573 /* blank the display controllers */ 574 for (i = 0; i < adev->mode_info.num_crtc; i++) { 575 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 576 CRTC_CONTROL, CRTC_MASTER_EN); 577 if (crtc_enabled) { 578 #if 0 579 u32 frame_count; 580 int j; 581 582 save->crtc_enabled[i] = true; 583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 584 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 585 amdgpu_display_vblank_wait(adev, i); 586 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 587 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 589 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 590 } 591 /* wait for the next frame */ 592 frame_count = amdgpu_display_vblank_get_counter(adev, i); 593 for (j = 0; j < adev->usec_timeout; j++) { 594 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 595 break; 596 udelay(1); 597 } 598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 602 } 603 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 604 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 605 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 606 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 607 } 608 #else 609 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 610 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 612 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 615 save->crtc_enabled[i] = false; 616 /* ***** */ 617 #endif 618 } else { 619 save->crtc_enabled[i] = false; 620 } 621 } 622 } 623 624 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, 625 struct amdgpu_mode_mc_save *save) 626 { 627 u32 tmp, frame_count; 628 int i, j; 629 630 /* update crtc base addresses */ 631 for (i = 0; i < adev->mode_info.num_crtc; i++) { 632 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 633 upper_32_bits(adev->mc.vram_start)); 634 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 635 upper_32_bits(adev->mc.vram_start)); 636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 637 (u32)adev->mc.vram_start); 638 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 639 (u32)adev->mc.vram_start); 640 641 if (save->crtc_enabled[i]) { 642 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 643 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 644 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 645 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 646 } 647 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 648 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 649 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 650 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 651 } 652 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 653 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 654 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 655 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 656 } 657 for (j = 0; j < adev->usec_timeout; j++) { 658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 660 break; 661 udelay(1); 662 } 663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 664 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 665 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 667 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 668 /* wait for the next frame */ 669 frame_count = amdgpu_display_vblank_get_counter(adev, i); 670 for (j = 0; j < adev->usec_timeout; j++) { 671 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 672 break; 673 udelay(1); 674 } 675 } 676 } 677 678 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 679 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 680 681 /* Unlock vga access */ 682 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 683 mdelay(1); 684 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 685 } 686 687 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 688 bool render) 689 { 690 u32 tmp; 691 692 /* Lockout access through VGA aperture*/ 693 tmp = RREG32(mmVGA_HDP_CONTROL); 694 if (render) 695 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 696 else 697 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 698 WREG32(mmVGA_HDP_CONTROL, tmp); 699 700 /* disable VGA render */ 701 tmp = RREG32(mmVGA_RENDER_CONTROL); 702 if (render) 703 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 704 else 705 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 706 WREG32(mmVGA_RENDER_CONTROL, tmp); 707 } 708 709 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 710 { 711 struct drm_device *dev = encoder->dev; 712 struct amdgpu_device *adev = dev->dev_private; 713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 715 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 716 int bpc = 0; 717 u32 tmp = 0; 718 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 719 720 if (connector) { 721 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 722 bpc = amdgpu_connector_get_monitor_bpc(connector); 723 dither = amdgpu_connector->dither; 724 } 725 726 /* LVDS/eDP FMT is set up by atom */ 727 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 728 return; 729 730 /* not needed for analog */ 731 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 732 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 733 return; 734 735 if (bpc == 0) 736 return; 737 738 switch (bpc) { 739 case 6: 740 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 741 /* XXX sort out optimal dither settings */ 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 746 } else { 747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 749 } 750 break; 751 case 8: 752 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 753 /* XXX sort out optimal dither settings */ 754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 759 } else { 760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 762 } 763 break; 764 case 10: 765 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 766 /* XXX sort out optimal dither settings */ 767 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 772 } else { 773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 775 } 776 break; 777 default: 778 /* not needed */ 779 break; 780 } 781 782 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 783 } 784 785 786 /* display watermark setup */ 787 /** 788 * dce_v10_0_line_buffer_adjust - Set up the line buffer 789 * 790 * @adev: amdgpu_device pointer 791 * @amdgpu_crtc: the selected display controller 792 * @mode: the current display mode on the selected display 793 * controller 794 * 795 * Setup up the line buffer allocation for 796 * the selected display controller (CIK). 797 * Returns the line buffer size in pixels. 798 */ 799 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 800 struct amdgpu_crtc *amdgpu_crtc, 801 struct drm_display_mode *mode) 802 { 803 u32 tmp, buffer_alloc, i, mem_cfg; 804 u32 pipe_offset = amdgpu_crtc->crtc_id; 805 /* 806 * Line Buffer Setup 807 * There are 6 line buffers, one for each display controllers. 808 * There are 3 partitions per LB. Select the number of partitions 809 * to enable based on the display width. For display widths larger 810 * than 4096, you need use to use 2 display controllers and combine 811 * them using the stereo blender. 812 */ 813 if (amdgpu_crtc->base.enabled && mode) { 814 if (mode->crtc_hdisplay < 1920) { 815 mem_cfg = 1; 816 buffer_alloc = 2; 817 } else if (mode->crtc_hdisplay < 2560) { 818 mem_cfg = 2; 819 buffer_alloc = 2; 820 } else if (mode->crtc_hdisplay < 4096) { 821 mem_cfg = 0; 822 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 823 } else { 824 DRM_DEBUG_KMS("Mode too big for LB!\n"); 825 mem_cfg = 0; 826 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 827 } 828 } else { 829 mem_cfg = 1; 830 buffer_alloc = 0; 831 } 832 833 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 834 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 835 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 836 837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 838 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 840 841 for (i = 0; i < adev->usec_timeout; i++) { 842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 843 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 844 break; 845 udelay(1); 846 } 847 848 if (amdgpu_crtc->base.enabled && mode) { 849 switch (mem_cfg) { 850 case 0: 851 default: 852 return 4096 * 2; 853 case 1: 854 return 1920 * 2; 855 case 2: 856 return 2560 * 2; 857 } 858 } 859 860 /* controller not enabled, so no lb used */ 861 return 0; 862 } 863 864 /** 865 * cik_get_number_of_dram_channels - get the number of dram channels 866 * 867 * @adev: amdgpu_device pointer 868 * 869 * Look up the number of video ram channels (CIK). 870 * Used for display watermark bandwidth calculations 871 * Returns the number of dram channels 872 */ 873 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 874 { 875 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 876 877 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 878 case 0: 879 default: 880 return 1; 881 case 1: 882 return 2; 883 case 2: 884 return 4; 885 case 3: 886 return 8; 887 case 4: 888 return 3; 889 case 5: 890 return 6; 891 case 6: 892 return 10; 893 case 7: 894 return 12; 895 case 8: 896 return 16; 897 } 898 } 899 900 struct dce10_wm_params { 901 u32 dram_channels; /* number of dram channels */ 902 u32 yclk; /* bandwidth per dram data pin in kHz */ 903 u32 sclk; /* engine clock in kHz */ 904 u32 disp_clk; /* display clock in kHz */ 905 u32 src_width; /* viewport width */ 906 u32 active_time; /* active display time in ns */ 907 u32 blank_time; /* blank time in ns */ 908 bool interlaced; /* mode is interlaced */ 909 fixed20_12 vsc; /* vertical scale ratio */ 910 u32 num_heads; /* number of active crtcs */ 911 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 912 u32 lb_size; /* line buffer allocated to pipe */ 913 u32 vtaps; /* vertical scaler taps */ 914 }; 915 916 /** 917 * dce_v10_0_dram_bandwidth - get the dram bandwidth 918 * 919 * @wm: watermark calculation data 920 * 921 * Calculate the raw dram bandwidth (CIK). 922 * Used for display watermark bandwidth calculations 923 * Returns the dram bandwidth in MBytes/s 924 */ 925 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 926 { 927 /* Calculate raw DRAM Bandwidth */ 928 fixed20_12 dram_efficiency; /* 0.7 */ 929 fixed20_12 yclk, dram_channels, bandwidth; 930 fixed20_12 a; 931 932 a.full = dfixed_const(1000); 933 yclk.full = dfixed_const(wm->yclk); 934 yclk.full = dfixed_div(yclk, a); 935 dram_channels.full = dfixed_const(wm->dram_channels * 4); 936 a.full = dfixed_const(10); 937 dram_efficiency.full = dfixed_const(7); 938 dram_efficiency.full = dfixed_div(dram_efficiency, a); 939 bandwidth.full = dfixed_mul(dram_channels, yclk); 940 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 941 942 return dfixed_trunc(bandwidth); 943 } 944 945 /** 946 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 947 * 948 * @wm: watermark calculation data 949 * 950 * Calculate the dram bandwidth used for display (CIK). 951 * Used for display watermark bandwidth calculations 952 * Returns the dram bandwidth for display in MBytes/s 953 */ 954 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 955 { 956 /* Calculate DRAM Bandwidth and the part allocated to display. */ 957 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 958 fixed20_12 yclk, dram_channels, bandwidth; 959 fixed20_12 a; 960 961 a.full = dfixed_const(1000); 962 yclk.full = dfixed_const(wm->yclk); 963 yclk.full = dfixed_div(yclk, a); 964 dram_channels.full = dfixed_const(wm->dram_channels * 4); 965 a.full = dfixed_const(10); 966 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 967 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 968 bandwidth.full = dfixed_mul(dram_channels, yclk); 969 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 970 971 return dfixed_trunc(bandwidth); 972 } 973 974 /** 975 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 976 * 977 * @wm: watermark calculation data 978 * 979 * Calculate the data return bandwidth used for display (CIK). 980 * Used for display watermark bandwidth calculations 981 * Returns the data return bandwidth in MBytes/s 982 */ 983 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 984 { 985 /* Calculate the display Data return Bandwidth */ 986 fixed20_12 return_efficiency; /* 0.8 */ 987 fixed20_12 sclk, bandwidth; 988 fixed20_12 a; 989 990 a.full = dfixed_const(1000); 991 sclk.full = dfixed_const(wm->sclk); 992 sclk.full = dfixed_div(sclk, a); 993 a.full = dfixed_const(10); 994 return_efficiency.full = dfixed_const(8); 995 return_efficiency.full = dfixed_div(return_efficiency, a); 996 a.full = dfixed_const(32); 997 bandwidth.full = dfixed_mul(a, sclk); 998 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 999 1000 return dfixed_trunc(bandwidth); 1001 } 1002 1003 /** 1004 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 1005 * 1006 * @wm: watermark calculation data 1007 * 1008 * Calculate the dmif bandwidth used for display (CIK). 1009 * Used for display watermark bandwidth calculations 1010 * Returns the dmif bandwidth in MBytes/s 1011 */ 1012 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 1013 { 1014 /* Calculate the DMIF Request Bandwidth */ 1015 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1016 fixed20_12 disp_clk, bandwidth; 1017 fixed20_12 a, b; 1018 1019 a.full = dfixed_const(1000); 1020 disp_clk.full = dfixed_const(wm->disp_clk); 1021 disp_clk.full = dfixed_div(disp_clk, a); 1022 a.full = dfixed_const(32); 1023 b.full = dfixed_mul(a, disp_clk); 1024 1025 a.full = dfixed_const(10); 1026 disp_clk_request_efficiency.full = dfixed_const(8); 1027 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1028 1029 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1030 1031 return dfixed_trunc(bandwidth); 1032 } 1033 1034 /** 1035 * dce_v10_0_available_bandwidth - get the min available bandwidth 1036 * 1037 * @wm: watermark calculation data 1038 * 1039 * Calculate the min available bandwidth used for display (CIK). 1040 * Used for display watermark bandwidth calculations 1041 * Returns the min available bandwidth in MBytes/s 1042 */ 1043 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 1044 { 1045 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1046 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 1047 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 1048 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 1049 1050 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1051 } 1052 1053 /** 1054 * dce_v10_0_average_bandwidth - get the average available bandwidth 1055 * 1056 * @wm: watermark calculation data 1057 * 1058 * Calculate the average available bandwidth used for display (CIK). 1059 * Used for display watermark bandwidth calculations 1060 * Returns the average available bandwidth in MBytes/s 1061 */ 1062 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 1063 { 1064 /* Calculate the display mode Average Bandwidth 1065 * DisplayMode should contain the source and destination dimensions, 1066 * timing, etc. 1067 */ 1068 fixed20_12 bpp; 1069 fixed20_12 line_time; 1070 fixed20_12 src_width; 1071 fixed20_12 bandwidth; 1072 fixed20_12 a; 1073 1074 a.full = dfixed_const(1000); 1075 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1076 line_time.full = dfixed_div(line_time, a); 1077 bpp.full = dfixed_const(wm->bytes_per_pixel); 1078 src_width.full = dfixed_const(wm->src_width); 1079 bandwidth.full = dfixed_mul(src_width, bpp); 1080 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1081 bandwidth.full = dfixed_div(bandwidth, line_time); 1082 1083 return dfixed_trunc(bandwidth); 1084 } 1085 1086 /** 1087 * dce_v10_0_latency_watermark - get the latency watermark 1088 * 1089 * @wm: watermark calculation data 1090 * 1091 * Calculate the latency watermark (CIK). 1092 * Used for display watermark bandwidth calculations 1093 * Returns the latency watermark in ns 1094 */ 1095 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 1096 { 1097 /* First calculate the latency in ns */ 1098 u32 mc_latency = 2000; /* 2000 ns. */ 1099 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 1100 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1101 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1102 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1103 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1104 (wm->num_heads * cursor_line_pair_return_time); 1105 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1106 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1107 u32 tmp, dmif_size = 12288; 1108 fixed20_12 a, b, c; 1109 1110 if (wm->num_heads == 0) 1111 return 0; 1112 1113 a.full = dfixed_const(2); 1114 b.full = dfixed_const(1); 1115 if ((wm->vsc.full > a.full) || 1116 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1117 (wm->vtaps >= 5) || 1118 ((wm->vsc.full >= a.full) && wm->interlaced)) 1119 max_src_lines_per_dst_line = 4; 1120 else 1121 max_src_lines_per_dst_line = 2; 1122 1123 a.full = dfixed_const(available_bandwidth); 1124 b.full = dfixed_const(wm->num_heads); 1125 a.full = dfixed_div(a, b); 1126 1127 b.full = dfixed_const(mc_latency + 512); 1128 c.full = dfixed_const(wm->disp_clk); 1129 b.full = dfixed_div(b, c); 1130 1131 c.full = dfixed_const(dmif_size); 1132 b.full = dfixed_div(c, b); 1133 1134 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1135 1136 b.full = dfixed_const(1000); 1137 c.full = dfixed_const(wm->disp_clk); 1138 b.full = dfixed_div(c, b); 1139 c.full = dfixed_const(wm->bytes_per_pixel); 1140 b.full = dfixed_mul(b, c); 1141 1142 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1143 1144 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1145 b.full = dfixed_const(1000); 1146 c.full = dfixed_const(lb_fill_bw); 1147 b.full = dfixed_div(c, b); 1148 a.full = dfixed_div(a, b); 1149 line_fill_time = dfixed_trunc(a); 1150 1151 if (line_fill_time < wm->active_time) 1152 return latency; 1153 else 1154 return latency + (line_fill_time - wm->active_time); 1155 1156 } 1157 1158 /** 1159 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1160 * average and available dram bandwidth 1161 * 1162 * @wm: watermark calculation data 1163 * 1164 * Check if the display average bandwidth fits in the display 1165 * dram bandwidth (CIK). 1166 * Used for display watermark bandwidth calculations 1167 * Returns true if the display fits, false if not. 1168 */ 1169 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1170 { 1171 if (dce_v10_0_average_bandwidth(wm) <= 1172 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1173 return true; 1174 else 1175 return false; 1176 } 1177 1178 /** 1179 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 1180 * average and available bandwidth 1181 * 1182 * @wm: watermark calculation data 1183 * 1184 * Check if the display average bandwidth fits in the display 1185 * available bandwidth (CIK). 1186 * Used for display watermark bandwidth calculations 1187 * Returns true if the display fits, false if not. 1188 */ 1189 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1190 { 1191 if (dce_v10_0_average_bandwidth(wm) <= 1192 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 1193 return true; 1194 else 1195 return false; 1196 } 1197 1198 /** 1199 * dce_v10_0_check_latency_hiding - check latency hiding 1200 * 1201 * @wm: watermark calculation data 1202 * 1203 * Check latency hiding (CIK). 1204 * Used for display watermark bandwidth calculations 1205 * Returns true if the display fits, false if not. 1206 */ 1207 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 1208 { 1209 u32 lb_partitions = wm->lb_size / wm->src_width; 1210 u32 line_time = wm->active_time + wm->blank_time; 1211 u32 latency_tolerant_lines; 1212 u32 latency_hiding; 1213 fixed20_12 a; 1214 1215 a.full = dfixed_const(1); 1216 if (wm->vsc.full > a.full) 1217 latency_tolerant_lines = 1; 1218 else { 1219 if (lb_partitions <= (wm->vtaps + 1)) 1220 latency_tolerant_lines = 1; 1221 else 1222 latency_tolerant_lines = 2; 1223 } 1224 1225 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1226 1227 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 1228 return true; 1229 else 1230 return false; 1231 } 1232 1233 /** 1234 * dce_v10_0_program_watermarks - program display watermarks 1235 * 1236 * @adev: amdgpu_device pointer 1237 * @amdgpu_crtc: the selected display controller 1238 * @lb_size: line buffer size 1239 * @num_heads: number of display controllers in use 1240 * 1241 * Calculate and program the display watermarks for the 1242 * selected display controller (CIK). 1243 */ 1244 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 1245 struct amdgpu_crtc *amdgpu_crtc, 1246 u32 lb_size, u32 num_heads) 1247 { 1248 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1249 struct dce10_wm_params wm_low, wm_high; 1250 u32 pixel_period; 1251 u32 line_time = 0; 1252 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1253 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1254 1255 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1256 pixel_period = 1000000 / (u32)mode->clock; 1257 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1258 1259 /* watermark for high clocks */ 1260 if (adev->pm.dpm_enabled) { 1261 wm_high.yclk = 1262 amdgpu_dpm_get_mclk(adev, false) * 10; 1263 wm_high.sclk = 1264 amdgpu_dpm_get_sclk(adev, false) * 10; 1265 } else { 1266 wm_high.yclk = adev->pm.current_mclk * 10; 1267 wm_high.sclk = adev->pm.current_sclk * 10; 1268 } 1269 1270 wm_high.disp_clk = mode->clock; 1271 wm_high.src_width = mode->crtc_hdisplay; 1272 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1273 wm_high.blank_time = line_time - wm_high.active_time; 1274 wm_high.interlaced = false; 1275 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1276 wm_high.interlaced = true; 1277 wm_high.vsc = amdgpu_crtc->vsc; 1278 wm_high.vtaps = 1; 1279 if (amdgpu_crtc->rmx_type != RMX_OFF) 1280 wm_high.vtaps = 2; 1281 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1282 wm_high.lb_size = lb_size; 1283 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1284 wm_high.num_heads = num_heads; 1285 1286 /* set for high clocks */ 1287 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); 1288 1289 /* possibly force display priority to high */ 1290 /* should really do this at mode validation time... */ 1291 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1292 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1293 !dce_v10_0_check_latency_hiding(&wm_high) || 1294 (adev->mode_info.disp_priority == 2)) { 1295 DRM_DEBUG_KMS("force priority to high\n"); 1296 } 1297 1298 /* watermark for low clocks */ 1299 if (adev->pm.dpm_enabled) { 1300 wm_low.yclk = 1301 amdgpu_dpm_get_mclk(adev, true) * 10; 1302 wm_low.sclk = 1303 amdgpu_dpm_get_sclk(adev, true) * 10; 1304 } else { 1305 wm_low.yclk = adev->pm.current_mclk * 10; 1306 wm_low.sclk = adev->pm.current_sclk * 10; 1307 } 1308 1309 wm_low.disp_clk = mode->clock; 1310 wm_low.src_width = mode->crtc_hdisplay; 1311 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1312 wm_low.blank_time = line_time - wm_low.active_time; 1313 wm_low.interlaced = false; 1314 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1315 wm_low.interlaced = true; 1316 wm_low.vsc = amdgpu_crtc->vsc; 1317 wm_low.vtaps = 1; 1318 if (amdgpu_crtc->rmx_type != RMX_OFF) 1319 wm_low.vtaps = 2; 1320 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1321 wm_low.lb_size = lb_size; 1322 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1323 wm_low.num_heads = num_heads; 1324 1325 /* set for low clocks */ 1326 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); 1327 1328 /* possibly force display priority to high */ 1329 /* should really do this at mode validation time... */ 1330 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1331 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1332 !dce_v10_0_check_latency_hiding(&wm_low) || 1333 (adev->mode_info.disp_priority == 2)) { 1334 DRM_DEBUG_KMS("force priority to high\n"); 1335 } 1336 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1337 } 1338 1339 /* select wm A */ 1340 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1341 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1342 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1343 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1344 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1345 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1346 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1347 /* select wm B */ 1348 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1349 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1350 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1352 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1353 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1354 /* restore original selection */ 1355 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1356 1357 /* save values for DPM */ 1358 amdgpu_crtc->line_time = line_time; 1359 amdgpu_crtc->wm_high = latency_watermark_a; 1360 amdgpu_crtc->wm_low = latency_watermark_b; 1361 /* Save number of lines the linebuffer leads before the scanout */ 1362 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1363 } 1364 1365 /** 1366 * dce_v10_0_bandwidth_update - program display watermarks 1367 * 1368 * @adev: amdgpu_device pointer 1369 * 1370 * Calculate and program the display watermarks and line 1371 * buffer allocation (CIK). 1372 */ 1373 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1374 { 1375 struct drm_display_mode *mode = NULL; 1376 u32 num_heads = 0, lb_size; 1377 int i; 1378 1379 amdgpu_update_display_priority(adev); 1380 1381 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1382 if (adev->mode_info.crtcs[i]->base.enabled) 1383 num_heads++; 1384 } 1385 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1386 mode = &adev->mode_info.crtcs[i]->base.mode; 1387 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1388 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1389 lb_size, num_heads); 1390 } 1391 } 1392 1393 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1394 { 1395 int i; 1396 u32 offset, tmp; 1397 1398 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1399 offset = adev->mode_info.audio.pin[i].offset; 1400 tmp = RREG32_AUDIO_ENDPT(offset, 1401 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1402 if (((tmp & 1403 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1404 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1405 adev->mode_info.audio.pin[i].connected = false; 1406 else 1407 adev->mode_info.audio.pin[i].connected = true; 1408 } 1409 } 1410 1411 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1412 { 1413 int i; 1414 1415 dce_v10_0_audio_get_connected_pins(adev); 1416 1417 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1418 if (adev->mode_info.audio.pin[i].connected) 1419 return &adev->mode_info.audio.pin[i]; 1420 } 1421 DRM_ERROR("No connected audio pins found!\n"); 1422 return NULL; 1423 } 1424 1425 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1426 { 1427 struct amdgpu_device *adev = encoder->dev->dev_private; 1428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1429 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1430 u32 tmp; 1431 1432 if (!dig || !dig->afmt || !dig->afmt->pin) 1433 return; 1434 1435 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1436 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1437 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1438 } 1439 1440 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1441 struct drm_display_mode *mode) 1442 { 1443 struct amdgpu_device *adev = encoder->dev->dev_private; 1444 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1445 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1446 struct drm_connector *connector; 1447 struct amdgpu_connector *amdgpu_connector = NULL; 1448 u32 tmp; 1449 int interlace = 0; 1450 1451 if (!dig || !dig->afmt || !dig->afmt->pin) 1452 return; 1453 1454 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1455 if (connector->encoder == encoder) { 1456 amdgpu_connector = to_amdgpu_connector(connector); 1457 break; 1458 } 1459 } 1460 1461 if (!amdgpu_connector) { 1462 DRM_ERROR("Couldn't find encoder's connector\n"); 1463 return; 1464 } 1465 1466 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1467 interlace = 1; 1468 if (connector->latency_present[interlace]) { 1469 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1470 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1471 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1472 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1473 } else { 1474 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1475 VIDEO_LIPSYNC, 0); 1476 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1477 AUDIO_LIPSYNC, 0); 1478 } 1479 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1480 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1481 } 1482 1483 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1484 { 1485 struct amdgpu_device *adev = encoder->dev->dev_private; 1486 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1487 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1488 struct drm_connector *connector; 1489 struct amdgpu_connector *amdgpu_connector = NULL; 1490 u32 tmp; 1491 u8 *sadb = NULL; 1492 int sad_count; 1493 1494 if (!dig || !dig->afmt || !dig->afmt->pin) 1495 return; 1496 1497 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1498 if (connector->encoder == encoder) { 1499 amdgpu_connector = to_amdgpu_connector(connector); 1500 break; 1501 } 1502 } 1503 1504 if (!amdgpu_connector) { 1505 DRM_ERROR("Couldn't find encoder's connector\n"); 1506 return; 1507 } 1508 1509 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1510 if (sad_count < 0) { 1511 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1512 sad_count = 0; 1513 } 1514 1515 /* program the speaker allocation */ 1516 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1517 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1519 DP_CONNECTION, 0); 1520 /* set HDMI mode */ 1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1522 HDMI_CONNECTION, 1); 1523 if (sad_count) 1524 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1525 SPEAKER_ALLOCATION, sadb[0]); 1526 else 1527 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1528 SPEAKER_ALLOCATION, 5); /* stereo */ 1529 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1530 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1531 1532 kfree(sadb); 1533 } 1534 1535 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1536 { 1537 struct amdgpu_device *adev = encoder->dev->dev_private; 1538 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1539 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1540 struct drm_connector *connector; 1541 struct amdgpu_connector *amdgpu_connector = NULL; 1542 struct cea_sad *sads; 1543 int i, sad_count; 1544 1545 static const u16 eld_reg_to_type[][2] = { 1546 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1547 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1548 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1549 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1550 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1551 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1552 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1553 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1554 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1555 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1556 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1557 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1558 }; 1559 1560 if (!dig || !dig->afmt || !dig->afmt->pin) 1561 return; 1562 1563 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1564 if (connector->encoder == encoder) { 1565 amdgpu_connector = to_amdgpu_connector(connector); 1566 break; 1567 } 1568 } 1569 1570 if (!amdgpu_connector) { 1571 DRM_ERROR("Couldn't find encoder's connector\n"); 1572 return; 1573 } 1574 1575 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1576 if (sad_count <= 0) { 1577 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1578 return; 1579 } 1580 BUG_ON(!sads); 1581 1582 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1583 u32 tmp = 0; 1584 u8 stereo_freqs = 0; 1585 int max_channels = -1; 1586 int j; 1587 1588 for (j = 0; j < sad_count; j++) { 1589 struct cea_sad *sad = &sads[j]; 1590 1591 if (sad->format == eld_reg_to_type[i][1]) { 1592 if (sad->channels > max_channels) { 1593 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1594 MAX_CHANNELS, sad->channels); 1595 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1596 DESCRIPTOR_BYTE_2, sad->byte2); 1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1598 SUPPORTED_FREQUENCIES, sad->freq); 1599 max_channels = sad->channels; 1600 } 1601 1602 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1603 stereo_freqs |= sad->freq; 1604 else 1605 break; 1606 } 1607 } 1608 1609 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1610 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1611 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1612 } 1613 1614 kfree(sads); 1615 } 1616 1617 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1618 struct amdgpu_audio_pin *pin, 1619 bool enable) 1620 { 1621 if (!pin) 1622 return; 1623 1624 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1625 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1626 } 1627 1628 static const u32 pin_offsets[] = 1629 { 1630 AUD0_REGISTER_OFFSET, 1631 AUD1_REGISTER_OFFSET, 1632 AUD2_REGISTER_OFFSET, 1633 AUD3_REGISTER_OFFSET, 1634 AUD4_REGISTER_OFFSET, 1635 AUD5_REGISTER_OFFSET, 1636 AUD6_REGISTER_OFFSET, 1637 }; 1638 1639 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1640 { 1641 int i; 1642 1643 if (!amdgpu_audio) 1644 return 0; 1645 1646 adev->mode_info.audio.enabled = true; 1647 1648 adev->mode_info.audio.num_pins = 7; 1649 1650 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1651 adev->mode_info.audio.pin[i].channels = -1; 1652 adev->mode_info.audio.pin[i].rate = -1; 1653 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1654 adev->mode_info.audio.pin[i].status_bits = 0; 1655 adev->mode_info.audio.pin[i].category_code = 0; 1656 adev->mode_info.audio.pin[i].connected = false; 1657 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1658 adev->mode_info.audio.pin[i].id = i; 1659 /* disable audio. it will be set up later */ 1660 /* XXX remove once we switch to ip funcs */ 1661 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1662 } 1663 1664 return 0; 1665 } 1666 1667 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1668 { 1669 int i; 1670 1671 if (!amdgpu_audio) 1672 return; 1673 1674 if (!adev->mode_info.audio.enabled) 1675 return; 1676 1677 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1678 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1679 1680 adev->mode_info.audio.enabled = false; 1681 } 1682 1683 /* 1684 * update the N and CTS parameters for a given pixel clock rate 1685 */ 1686 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1687 { 1688 struct drm_device *dev = encoder->dev; 1689 struct amdgpu_device *adev = dev->dev_private; 1690 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1691 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1692 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1693 u32 tmp; 1694 1695 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1697 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1698 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1699 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1700 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1701 1702 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1704 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1705 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1706 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1707 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1708 1709 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1710 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1711 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1712 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1713 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1714 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1715 1716 } 1717 1718 /* 1719 * build a HDMI Video Info Frame 1720 */ 1721 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1722 void *buffer, size_t size) 1723 { 1724 struct drm_device *dev = encoder->dev; 1725 struct amdgpu_device *adev = dev->dev_private; 1726 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1727 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1728 uint8_t *frame = buffer + 3; 1729 uint8_t *header = buffer; 1730 1731 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1732 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1733 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1734 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1735 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1736 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1737 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1738 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1739 } 1740 1741 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1742 { 1743 struct drm_device *dev = encoder->dev; 1744 struct amdgpu_device *adev = dev->dev_private; 1745 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1746 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1748 u32 dto_phase = 24 * 1000; 1749 u32 dto_modulo = clock; 1750 u32 tmp; 1751 1752 if (!dig || !dig->afmt) 1753 return; 1754 1755 /* XXX two dtos; generally use dto0 for hdmi */ 1756 /* Express [24MHz / target pixel clock] as an exact rational 1757 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1758 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1759 */ 1760 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1761 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1762 amdgpu_crtc->crtc_id); 1763 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1764 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1765 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1766 } 1767 1768 /* 1769 * update the info frames with the data from the current display mode 1770 */ 1771 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1772 struct drm_display_mode *mode) 1773 { 1774 struct drm_device *dev = encoder->dev; 1775 struct amdgpu_device *adev = dev->dev_private; 1776 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1777 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1778 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1779 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1780 struct hdmi_avi_infoframe frame; 1781 ssize_t err; 1782 u32 tmp; 1783 int bpc = 8; 1784 1785 if (!dig || !dig->afmt) 1786 return; 1787 1788 /* Silent, r600_hdmi_enable will raise WARN for us */ 1789 if (!dig->afmt->enabled) 1790 return; 1791 1792 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1793 if (encoder->crtc) { 1794 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1795 bpc = amdgpu_crtc->bpc; 1796 } 1797 1798 /* disable audio prior to setting up hw */ 1799 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1800 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1801 1802 dce_v10_0_audio_set_dto(encoder, mode->clock); 1803 1804 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1805 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1806 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1807 1808 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1809 1810 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1811 switch (bpc) { 1812 case 0: 1813 case 6: 1814 case 8: 1815 case 16: 1816 default: 1817 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1818 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1819 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1820 connector->name, bpc); 1821 break; 1822 case 10: 1823 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1824 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1825 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1826 connector->name); 1827 break; 1828 case 12: 1829 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1830 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1831 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1832 connector->name); 1833 break; 1834 } 1835 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1836 1837 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1838 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1839 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1840 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1841 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1842 1843 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1844 /* enable audio info frames (frames won't be set until audio is enabled) */ 1845 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1846 /* required for audio info values to be updated */ 1847 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1848 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1849 1850 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1851 /* required for audio info values to be updated */ 1852 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1853 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1854 1855 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1856 /* anything other than 0 */ 1857 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1858 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1859 1860 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1861 1862 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1863 /* set the default audio delay */ 1864 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1865 /* should be suffient for all audio modes and small enough for all hblanks */ 1866 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1867 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1868 1869 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1870 /* allow 60958 channel status fields to be updated */ 1871 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1872 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1873 1874 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1875 if (bpc > 8) 1876 /* clear SW CTS value */ 1877 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1878 else 1879 /* select SW CTS value */ 1880 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1881 /* allow hw to sent ACR packets when required */ 1882 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1883 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1884 1885 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1886 1887 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1888 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1889 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1890 1891 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1892 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1893 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1894 1895 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1896 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1897 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1898 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1899 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1900 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1901 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1902 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1903 1904 dce_v10_0_audio_write_speaker_allocation(encoder); 1905 1906 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1907 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1908 1909 dce_v10_0_afmt_audio_select_pin(encoder); 1910 dce_v10_0_audio_write_sad_regs(encoder); 1911 dce_v10_0_audio_write_latency_fields(encoder, mode); 1912 1913 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1914 if (err < 0) { 1915 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1916 return; 1917 } 1918 1919 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1920 if (err < 0) { 1921 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1922 return; 1923 } 1924 1925 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1926 1927 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1928 /* enable AVI info frames */ 1929 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1930 /* required for audio info values to be updated */ 1931 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1932 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1933 1934 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1935 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1936 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1937 1938 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1939 /* send audio packets */ 1940 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1941 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1942 1943 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1944 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1945 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1946 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1947 1948 /* enable audio after to setting up hw */ 1949 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 1950 } 1951 1952 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1953 { 1954 struct drm_device *dev = encoder->dev; 1955 struct amdgpu_device *adev = dev->dev_private; 1956 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1957 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1958 1959 if (!dig || !dig->afmt) 1960 return; 1961 1962 /* Silent, r600_hdmi_enable will raise WARN for us */ 1963 if (enable && dig->afmt->enabled) 1964 return; 1965 if (!enable && !dig->afmt->enabled) 1966 return; 1967 1968 if (!enable && dig->afmt->pin) { 1969 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1970 dig->afmt->pin = NULL; 1971 } 1972 1973 dig->afmt->enabled = enable; 1974 1975 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1976 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1977 } 1978 1979 static int dce_v10_0_afmt_init(struct amdgpu_device *adev) 1980 { 1981 int i; 1982 1983 for (i = 0; i < adev->mode_info.num_dig; i++) 1984 adev->mode_info.afmt[i] = NULL; 1985 1986 /* DCE10 has audio blocks tied to DIG encoders */ 1987 for (i = 0; i < adev->mode_info.num_dig; i++) { 1988 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1989 if (adev->mode_info.afmt[i]) { 1990 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1991 adev->mode_info.afmt[i]->id = i; 1992 } else { 1993 int j; 1994 for (j = 0; j < i; j++) { 1995 kfree(adev->mode_info.afmt[j]); 1996 adev->mode_info.afmt[j] = NULL; 1997 } 1998 return -ENOMEM; 1999 } 2000 } 2001 return 0; 2002 } 2003 2004 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 2005 { 2006 int i; 2007 2008 for (i = 0; i < adev->mode_info.num_dig; i++) { 2009 kfree(adev->mode_info.afmt[i]); 2010 adev->mode_info.afmt[i] = NULL; 2011 } 2012 } 2013 2014 static const u32 vga_control_regs[6] = 2015 { 2016 mmD1VGA_CONTROL, 2017 mmD2VGA_CONTROL, 2018 mmD3VGA_CONTROL, 2019 mmD4VGA_CONTROL, 2020 mmD5VGA_CONTROL, 2021 mmD6VGA_CONTROL, 2022 }; 2023 2024 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 2025 { 2026 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2027 struct drm_device *dev = crtc->dev; 2028 struct amdgpu_device *adev = dev->dev_private; 2029 u32 vga_control; 2030 2031 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2032 if (enable) 2033 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2034 else 2035 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2036 } 2037 2038 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 2039 { 2040 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2041 struct drm_device *dev = crtc->dev; 2042 struct amdgpu_device *adev = dev->dev_private; 2043 2044 if (enable) 2045 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2046 else 2047 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2048 } 2049 2050 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 2051 struct drm_framebuffer *fb, 2052 int x, int y, int atomic) 2053 { 2054 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2055 struct drm_device *dev = crtc->dev; 2056 struct amdgpu_device *adev = dev->dev_private; 2057 struct amdgpu_framebuffer *amdgpu_fb; 2058 struct drm_framebuffer *target_fb; 2059 struct drm_gem_object *obj; 2060 struct amdgpu_bo *rbo; 2061 uint64_t fb_location, tiling_flags; 2062 uint32_t fb_format, fb_pitch_pixels; 2063 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2064 u32 pipe_config; 2065 u32 tmp, viewport_w, viewport_h; 2066 int r; 2067 bool bypass_lut = false; 2068 2069 /* no fb bound */ 2070 if (!atomic && !crtc->primary->fb) { 2071 DRM_DEBUG_KMS("No FB bound\n"); 2072 return 0; 2073 } 2074 2075 if (atomic) { 2076 amdgpu_fb = to_amdgpu_framebuffer(fb); 2077 target_fb = fb; 2078 } else { 2079 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2080 target_fb = crtc->primary->fb; 2081 } 2082 2083 /* If atomic, assume fb object is pinned & idle & fenced and 2084 * just update base pointers 2085 */ 2086 obj = amdgpu_fb->obj; 2087 rbo = gem_to_amdgpu_bo(obj); 2088 r = amdgpu_bo_reserve(rbo, false); 2089 if (unlikely(r != 0)) 2090 return r; 2091 2092 if (atomic) { 2093 fb_location = amdgpu_bo_gpu_offset(rbo); 2094 } else { 2095 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2096 if (unlikely(r != 0)) { 2097 amdgpu_bo_unreserve(rbo); 2098 return -EINVAL; 2099 } 2100 } 2101 2102 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2103 amdgpu_bo_unreserve(rbo); 2104 2105 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2106 2107 switch (target_fb->pixel_format) { 2108 case DRM_FORMAT_C8: 2109 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2110 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2111 break; 2112 case DRM_FORMAT_XRGB4444: 2113 case DRM_FORMAT_ARGB4444: 2114 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2115 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2116 #ifdef __BIG_ENDIAN 2117 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2118 ENDIAN_8IN16); 2119 #endif 2120 break; 2121 case DRM_FORMAT_XRGB1555: 2122 case DRM_FORMAT_ARGB1555: 2123 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2124 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2125 #ifdef __BIG_ENDIAN 2126 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2127 ENDIAN_8IN16); 2128 #endif 2129 break; 2130 case DRM_FORMAT_BGRX5551: 2131 case DRM_FORMAT_BGRA5551: 2132 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2133 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2134 #ifdef __BIG_ENDIAN 2135 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2136 ENDIAN_8IN16); 2137 #endif 2138 break; 2139 case DRM_FORMAT_RGB565: 2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2142 #ifdef __BIG_ENDIAN 2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2144 ENDIAN_8IN16); 2145 #endif 2146 break; 2147 case DRM_FORMAT_XRGB8888: 2148 case DRM_FORMAT_ARGB8888: 2149 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2151 #ifdef __BIG_ENDIAN 2152 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2153 ENDIAN_8IN32); 2154 #endif 2155 break; 2156 case DRM_FORMAT_XRGB2101010: 2157 case DRM_FORMAT_ARGB2101010: 2158 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2159 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2160 #ifdef __BIG_ENDIAN 2161 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2162 ENDIAN_8IN32); 2163 #endif 2164 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2165 bypass_lut = true; 2166 break; 2167 case DRM_FORMAT_BGRX1010102: 2168 case DRM_FORMAT_BGRA1010102: 2169 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2170 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2171 #ifdef __BIG_ENDIAN 2172 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2173 ENDIAN_8IN32); 2174 #endif 2175 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2176 bypass_lut = true; 2177 break; 2178 default: 2179 DRM_ERROR("Unsupported screen format %s\n", 2180 drm_get_format_name(target_fb->pixel_format)); 2181 return -EINVAL; 2182 } 2183 2184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2185 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2186 2187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2192 2193 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2194 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2195 ARRAY_2D_TILED_THIN1); 2196 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2197 tile_split); 2198 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2199 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2200 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2201 mtaspect); 2202 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2203 ADDR_SURF_MICRO_TILING_DISPLAY); 2204 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2205 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2206 ARRAY_1D_TILED_THIN1); 2207 } 2208 2209 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2210 pipe_config); 2211 2212 dce_v10_0_vga_enable(crtc, false); 2213 2214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2215 upper_32_bits(fb_location)); 2216 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2217 upper_32_bits(fb_location)); 2218 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2219 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2220 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2221 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2222 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2223 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2224 2225 /* 2226 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2227 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2228 * retain the full precision throughout the pipeline. 2229 */ 2230 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2231 if (bypass_lut) 2232 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2233 else 2234 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2235 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2236 2237 if (bypass_lut) 2238 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2239 2240 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2241 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2242 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2243 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2244 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2245 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2246 2247 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2248 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2249 2250 dce_v10_0_grph_enable(crtc, true); 2251 2252 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2253 target_fb->height); 2254 2255 x &= ~3; 2256 y &= ~1; 2257 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2258 (x << 16) | y); 2259 viewport_w = crtc->mode.hdisplay; 2260 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2261 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2262 (viewport_w << 16) | viewport_h); 2263 2264 /* pageflip setup */ 2265 /* make sure flip is at vb rather than hb */ 2266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2267 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2268 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2270 2271 /* set pageflip to happen only at start of vblank interval (front porch) */ 2272 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2273 2274 if (!atomic && fb && fb != crtc->primary->fb) { 2275 amdgpu_fb = to_amdgpu_framebuffer(fb); 2276 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2277 r = amdgpu_bo_reserve(rbo, false); 2278 if (unlikely(r != 0)) 2279 return r; 2280 amdgpu_bo_unpin(rbo); 2281 amdgpu_bo_unreserve(rbo); 2282 } 2283 2284 /* Bytes per pixel may have changed */ 2285 dce_v10_0_bandwidth_update(adev); 2286 2287 return 0; 2288 } 2289 2290 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2291 struct drm_display_mode *mode) 2292 { 2293 struct drm_device *dev = crtc->dev; 2294 struct amdgpu_device *adev = dev->dev_private; 2295 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2296 u32 tmp; 2297 2298 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2299 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2300 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2301 else 2302 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2303 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2304 } 2305 2306 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2307 { 2308 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2309 struct drm_device *dev = crtc->dev; 2310 struct amdgpu_device *adev = dev->dev_private; 2311 int i; 2312 u32 tmp; 2313 2314 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2315 2316 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2317 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2318 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2319 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2320 2321 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2322 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2323 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2324 2325 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2326 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2327 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2328 2329 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2330 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2331 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2332 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2333 2334 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2335 2336 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2337 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2338 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2339 2340 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2341 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2342 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2343 2344 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2345 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2346 2347 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2348 for (i = 0; i < 256; i++) { 2349 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2350 (amdgpu_crtc->lut_r[i] << 20) | 2351 (amdgpu_crtc->lut_g[i] << 10) | 2352 (amdgpu_crtc->lut_b[i] << 0)); 2353 } 2354 2355 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2356 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2357 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2358 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2359 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2360 2361 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2362 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2363 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2364 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2365 2366 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2367 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2368 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2369 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2370 2371 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2372 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2373 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2374 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2375 2376 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2377 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2378 /* XXX this only needs to be programmed once per crtc at startup, 2379 * not sure where the best place for it is 2380 */ 2381 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2382 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2383 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2384 } 2385 2386 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2387 { 2388 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2389 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2390 2391 switch (amdgpu_encoder->encoder_id) { 2392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2393 if (dig->linkb) 2394 return 1; 2395 else 2396 return 0; 2397 break; 2398 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2399 if (dig->linkb) 2400 return 3; 2401 else 2402 return 2; 2403 break; 2404 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2405 if (dig->linkb) 2406 return 5; 2407 else 2408 return 4; 2409 break; 2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2411 return 6; 2412 break; 2413 default: 2414 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2415 return 0; 2416 } 2417 } 2418 2419 /** 2420 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2421 * 2422 * @crtc: drm crtc 2423 * 2424 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2425 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2426 * monitors a dedicated PPLL must be used. If a particular board has 2427 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2428 * as there is no need to program the PLL itself. If we are not able to 2429 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2430 * avoid messing up an existing monitor. 2431 * 2432 * Asic specific PLL information 2433 * 2434 * DCE 10.x 2435 * Tonga 2436 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2437 * CI 2438 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2439 * 2440 */ 2441 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2442 { 2443 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2444 struct drm_device *dev = crtc->dev; 2445 struct amdgpu_device *adev = dev->dev_private; 2446 u32 pll_in_use; 2447 int pll; 2448 2449 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2450 if (adev->clock.dp_extclk) 2451 /* skip PPLL programming if using ext clock */ 2452 return ATOM_PPLL_INVALID; 2453 else { 2454 /* use the same PPLL for all DP monitors */ 2455 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2456 if (pll != ATOM_PPLL_INVALID) 2457 return pll; 2458 } 2459 } else { 2460 /* use the same PPLL for all monitors with the same clock */ 2461 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2462 if (pll != ATOM_PPLL_INVALID) 2463 return pll; 2464 } 2465 2466 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2467 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2468 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2469 return ATOM_PPLL2; 2470 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2471 return ATOM_PPLL1; 2472 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2473 return ATOM_PPLL0; 2474 DRM_ERROR("unable to allocate a PPLL\n"); 2475 return ATOM_PPLL_INVALID; 2476 } 2477 2478 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2479 { 2480 struct amdgpu_device *adev = crtc->dev->dev_private; 2481 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2482 uint32_t cur_lock; 2483 2484 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2485 if (lock) 2486 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2487 else 2488 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2489 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2490 } 2491 2492 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2493 { 2494 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2495 struct amdgpu_device *adev = crtc->dev->dev_private; 2496 u32 tmp; 2497 2498 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2499 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2500 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2501 } 2502 2503 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2504 { 2505 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2506 struct amdgpu_device *adev = crtc->dev->dev_private; 2507 u32 tmp; 2508 2509 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2510 upper_32_bits(amdgpu_crtc->cursor_addr)); 2511 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2512 lower_32_bits(amdgpu_crtc->cursor_addr)); 2513 2514 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2515 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2516 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2517 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2518 } 2519 2520 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 2521 int x, int y) 2522 { 2523 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2524 struct amdgpu_device *adev = crtc->dev->dev_private; 2525 int xorigin = 0, yorigin = 0; 2526 2527 /* avivo cursor are offset into the total surface */ 2528 x += crtc->x; 2529 y += crtc->y; 2530 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2531 2532 if (x < 0) { 2533 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2534 x = 0; 2535 } 2536 if (y < 0) { 2537 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2538 y = 0; 2539 } 2540 2541 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2542 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2543 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2544 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2545 2546 amdgpu_crtc->cursor_x = x; 2547 amdgpu_crtc->cursor_y = y; 2548 2549 return 0; 2550 } 2551 2552 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2553 int x, int y) 2554 { 2555 int ret; 2556 2557 dce_v10_0_lock_cursor(crtc, true); 2558 ret = dce_v10_0_cursor_move_locked(crtc, x, y); 2559 dce_v10_0_lock_cursor(crtc, false); 2560 2561 return ret; 2562 } 2563 2564 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 2565 struct drm_file *file_priv, 2566 uint32_t handle, 2567 uint32_t width, 2568 uint32_t height, 2569 int32_t hot_x, 2570 int32_t hot_y) 2571 { 2572 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2573 struct drm_gem_object *obj; 2574 struct amdgpu_bo *aobj; 2575 int ret; 2576 2577 if (!handle) { 2578 /* turn off cursor */ 2579 dce_v10_0_hide_cursor(crtc); 2580 obj = NULL; 2581 goto unpin; 2582 } 2583 2584 if ((width > amdgpu_crtc->max_cursor_width) || 2585 (height > amdgpu_crtc->max_cursor_height)) { 2586 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2587 return -EINVAL; 2588 } 2589 2590 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2591 if (!obj) { 2592 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2593 return -ENOENT; 2594 } 2595 2596 aobj = gem_to_amdgpu_bo(obj); 2597 ret = amdgpu_bo_reserve(aobj, false); 2598 if (ret != 0) { 2599 drm_gem_object_unreference_unlocked(obj); 2600 return ret; 2601 } 2602 2603 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2604 amdgpu_bo_unreserve(aobj); 2605 if (ret) { 2606 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2607 drm_gem_object_unreference_unlocked(obj); 2608 return ret; 2609 } 2610 2611 amdgpu_crtc->cursor_width = width; 2612 amdgpu_crtc->cursor_height = height; 2613 2614 dce_v10_0_lock_cursor(crtc, true); 2615 2616 if (hot_x != amdgpu_crtc->cursor_hot_x || 2617 hot_y != amdgpu_crtc->cursor_hot_y) { 2618 int x, y; 2619 2620 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2621 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2622 2623 dce_v10_0_cursor_move_locked(crtc, x, y); 2624 2625 amdgpu_crtc->cursor_hot_x = hot_x; 2626 amdgpu_crtc->cursor_hot_y = hot_y; 2627 } 2628 2629 dce_v10_0_show_cursor(crtc); 2630 dce_v10_0_lock_cursor(crtc, false); 2631 2632 unpin: 2633 if (amdgpu_crtc->cursor_bo) { 2634 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2635 ret = amdgpu_bo_reserve(aobj, false); 2636 if (likely(ret == 0)) { 2637 amdgpu_bo_unpin(aobj); 2638 amdgpu_bo_unreserve(aobj); 2639 } 2640 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2641 } 2642 2643 amdgpu_crtc->cursor_bo = obj; 2644 return 0; 2645 } 2646 2647 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2648 { 2649 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2650 2651 if (amdgpu_crtc->cursor_bo) { 2652 dce_v10_0_lock_cursor(crtc, true); 2653 2654 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2655 amdgpu_crtc->cursor_y); 2656 2657 dce_v10_0_show_cursor(crtc); 2658 2659 dce_v10_0_lock_cursor(crtc, false); 2660 } 2661 } 2662 2663 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2664 u16 *blue, uint32_t start, uint32_t size) 2665 { 2666 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2667 int end = (start + size > 256) ? 256 : start + size, i; 2668 2669 /* userspace palettes are always correct as is */ 2670 for (i = start; i < end; i++) { 2671 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2672 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2673 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2674 } 2675 dce_v10_0_crtc_load_lut(crtc); 2676 } 2677 2678 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2679 { 2680 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2681 2682 drm_crtc_cleanup(crtc); 2683 kfree(amdgpu_crtc); 2684 } 2685 2686 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2687 .cursor_set2 = dce_v10_0_crtc_cursor_set2, 2688 .cursor_move = dce_v10_0_crtc_cursor_move, 2689 .gamma_set = dce_v10_0_crtc_gamma_set, 2690 .set_config = amdgpu_crtc_set_config, 2691 .destroy = dce_v10_0_crtc_destroy, 2692 .page_flip = amdgpu_crtc_page_flip, 2693 }; 2694 2695 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2696 { 2697 struct drm_device *dev = crtc->dev; 2698 struct amdgpu_device *adev = dev->dev_private; 2699 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2700 unsigned type; 2701 2702 switch (mode) { 2703 case DRM_MODE_DPMS_ON: 2704 amdgpu_crtc->enabled = true; 2705 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2706 dce_v10_0_vga_enable(crtc, true); 2707 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2708 dce_v10_0_vga_enable(crtc, false); 2709 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2710 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2711 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2712 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2713 drm_vblank_on(dev, amdgpu_crtc->crtc_id); 2714 dce_v10_0_crtc_load_lut(crtc); 2715 break; 2716 case DRM_MODE_DPMS_STANDBY: 2717 case DRM_MODE_DPMS_SUSPEND: 2718 case DRM_MODE_DPMS_OFF: 2719 drm_vblank_off(dev, amdgpu_crtc->crtc_id); 2720 if (amdgpu_crtc->enabled) { 2721 dce_v10_0_vga_enable(crtc, true); 2722 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2723 dce_v10_0_vga_enable(crtc, false); 2724 } 2725 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2726 amdgpu_crtc->enabled = false; 2727 break; 2728 } 2729 /* adjust pm to dpms */ 2730 amdgpu_pm_compute_clocks(adev); 2731 } 2732 2733 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2734 { 2735 /* disable crtc pair power gating before programming */ 2736 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2737 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2738 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2739 } 2740 2741 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2742 { 2743 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2744 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2745 } 2746 2747 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2748 { 2749 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2750 struct drm_device *dev = crtc->dev; 2751 struct amdgpu_device *adev = dev->dev_private; 2752 struct amdgpu_atom_ss ss; 2753 int i; 2754 2755 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2756 if (crtc->primary->fb) { 2757 int r; 2758 struct amdgpu_framebuffer *amdgpu_fb; 2759 struct amdgpu_bo *rbo; 2760 2761 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2762 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2763 r = amdgpu_bo_reserve(rbo, false); 2764 if (unlikely(r)) 2765 DRM_ERROR("failed to reserve rbo before unpin\n"); 2766 else { 2767 amdgpu_bo_unpin(rbo); 2768 amdgpu_bo_unreserve(rbo); 2769 } 2770 } 2771 /* disable the GRPH */ 2772 dce_v10_0_grph_enable(crtc, false); 2773 2774 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2775 2776 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2777 if (adev->mode_info.crtcs[i] && 2778 adev->mode_info.crtcs[i]->enabled && 2779 i != amdgpu_crtc->crtc_id && 2780 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2781 /* one other crtc is using this pll don't turn 2782 * off the pll 2783 */ 2784 goto done; 2785 } 2786 } 2787 2788 switch (amdgpu_crtc->pll_id) { 2789 case ATOM_PPLL0: 2790 case ATOM_PPLL1: 2791 case ATOM_PPLL2: 2792 /* disable the ppll */ 2793 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2794 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2795 break; 2796 default: 2797 break; 2798 } 2799 done: 2800 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2801 amdgpu_crtc->adjusted_clock = 0; 2802 amdgpu_crtc->encoder = NULL; 2803 amdgpu_crtc->connector = NULL; 2804 } 2805 2806 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2807 struct drm_display_mode *mode, 2808 struct drm_display_mode *adjusted_mode, 2809 int x, int y, struct drm_framebuffer *old_fb) 2810 { 2811 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2812 2813 if (!amdgpu_crtc->adjusted_clock) 2814 return -EINVAL; 2815 2816 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2817 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2818 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2819 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2820 amdgpu_atombios_crtc_scaler_setup(crtc); 2821 dce_v10_0_cursor_reset(crtc); 2822 /* update the hw version fpr dpm */ 2823 amdgpu_crtc->hw_mode = *adjusted_mode; 2824 2825 return 0; 2826 } 2827 2828 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2829 const struct drm_display_mode *mode, 2830 struct drm_display_mode *adjusted_mode) 2831 { 2832 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2833 struct drm_device *dev = crtc->dev; 2834 struct drm_encoder *encoder; 2835 2836 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2837 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2838 if (encoder->crtc == crtc) { 2839 amdgpu_crtc->encoder = encoder; 2840 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2841 break; 2842 } 2843 } 2844 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2845 amdgpu_crtc->encoder = NULL; 2846 amdgpu_crtc->connector = NULL; 2847 return false; 2848 } 2849 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2850 return false; 2851 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2852 return false; 2853 /* pick pll */ 2854 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2855 /* if we can't get a PPLL for a non-DP encoder, fail */ 2856 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2857 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2858 return false; 2859 2860 return true; 2861 } 2862 2863 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2864 struct drm_framebuffer *old_fb) 2865 { 2866 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2867 } 2868 2869 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2870 struct drm_framebuffer *fb, 2871 int x, int y, enum mode_set_atomic state) 2872 { 2873 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); 2874 } 2875 2876 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2877 .dpms = dce_v10_0_crtc_dpms, 2878 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2879 .mode_set = dce_v10_0_crtc_mode_set, 2880 .mode_set_base = dce_v10_0_crtc_set_base, 2881 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, 2882 .prepare = dce_v10_0_crtc_prepare, 2883 .commit = dce_v10_0_crtc_commit, 2884 .load_lut = dce_v10_0_crtc_load_lut, 2885 .disable = dce_v10_0_crtc_disable, 2886 }; 2887 2888 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2889 { 2890 struct amdgpu_crtc *amdgpu_crtc; 2891 int i; 2892 2893 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2894 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2895 if (amdgpu_crtc == NULL) 2896 return -ENOMEM; 2897 2898 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2899 2900 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2901 amdgpu_crtc->crtc_id = index; 2902 adev->mode_info.crtcs[index] = amdgpu_crtc; 2903 2904 amdgpu_crtc->max_cursor_width = 128; 2905 amdgpu_crtc->max_cursor_height = 128; 2906 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2907 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2908 2909 for (i = 0; i < 256; i++) { 2910 amdgpu_crtc->lut_r[i] = i << 2; 2911 amdgpu_crtc->lut_g[i] = i << 2; 2912 amdgpu_crtc->lut_b[i] = i << 2; 2913 } 2914 2915 switch (amdgpu_crtc->crtc_id) { 2916 case 0: 2917 default: 2918 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2919 break; 2920 case 1: 2921 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2922 break; 2923 case 2: 2924 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2925 break; 2926 case 3: 2927 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2928 break; 2929 case 4: 2930 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2931 break; 2932 case 5: 2933 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2934 break; 2935 } 2936 2937 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2938 amdgpu_crtc->adjusted_clock = 0; 2939 amdgpu_crtc->encoder = NULL; 2940 amdgpu_crtc->connector = NULL; 2941 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2942 2943 return 0; 2944 } 2945 2946 static int dce_v10_0_early_init(void *handle) 2947 { 2948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2949 2950 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2951 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2952 2953 dce_v10_0_set_display_funcs(adev); 2954 dce_v10_0_set_irq_funcs(adev); 2955 2956 switch (adev->asic_type) { 2957 case CHIP_FIJI: 2958 case CHIP_TONGA: 2959 adev->mode_info.num_crtc = 6; /* XXX 7??? */ 2960 adev->mode_info.num_hpd = 6; 2961 adev->mode_info.num_dig = 7; 2962 break; 2963 default: 2964 /* FIXME: not supported yet */ 2965 return -EINVAL; 2966 } 2967 2968 return 0; 2969 } 2970 2971 static int dce_v10_0_sw_init(void *handle) 2972 { 2973 int r, i; 2974 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2975 2976 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2977 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2978 if (r) 2979 return r; 2980 } 2981 2982 for (i = 8; i < 20; i += 2) { 2983 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2984 if (r) 2985 return r; 2986 } 2987 2988 /* HPD hotplug */ 2989 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2990 if (r) 2991 return r; 2992 2993 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2994 2995 adev->ddev->mode_config.max_width = 16384; 2996 adev->ddev->mode_config.max_height = 16384; 2997 2998 adev->ddev->mode_config.preferred_depth = 24; 2999 adev->ddev->mode_config.prefer_shadow = 1; 3000 3001 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 3002 3003 r = amdgpu_modeset_create_props(adev); 3004 if (r) 3005 return r; 3006 3007 adev->ddev->mode_config.max_width = 16384; 3008 adev->ddev->mode_config.max_height = 16384; 3009 3010 /* allocate crtcs */ 3011 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3012 r = dce_v10_0_crtc_init(adev, i); 3013 if (r) 3014 return r; 3015 } 3016 3017 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3018 amdgpu_print_display_setup(adev->ddev); 3019 else 3020 return -EINVAL; 3021 3022 /* setup afmt */ 3023 r = dce_v10_0_afmt_init(adev); 3024 if (r) 3025 return r; 3026 3027 r = dce_v10_0_audio_init(adev); 3028 if (r) 3029 return r; 3030 3031 drm_kms_helper_poll_init(adev->ddev); 3032 3033 adev->mode_info.mode_config_initialized = true; 3034 return 0; 3035 } 3036 3037 static int dce_v10_0_sw_fini(void *handle) 3038 { 3039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3040 3041 kfree(adev->mode_info.bios_hardcoded_edid); 3042 3043 drm_kms_helper_poll_fini(adev->ddev); 3044 3045 dce_v10_0_audio_fini(adev); 3046 3047 dce_v10_0_afmt_fini(adev); 3048 3049 drm_mode_config_cleanup(adev->ddev); 3050 adev->mode_info.mode_config_initialized = false; 3051 3052 return 0; 3053 } 3054 3055 static int dce_v10_0_hw_init(void *handle) 3056 { 3057 int i; 3058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3059 3060 dce_v10_0_init_golden_registers(adev); 3061 3062 /* init dig PHYs, disp eng pll */ 3063 amdgpu_atombios_encoder_init_dig(adev); 3064 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3065 3066 /* initialize hpd */ 3067 dce_v10_0_hpd_init(adev); 3068 3069 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3070 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3071 } 3072 3073 dce_v10_0_pageflip_interrupt_init(adev); 3074 3075 return 0; 3076 } 3077 3078 static int dce_v10_0_hw_fini(void *handle) 3079 { 3080 int i; 3081 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3082 3083 dce_v10_0_hpd_fini(adev); 3084 3085 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3086 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3087 } 3088 3089 dce_v10_0_pageflip_interrupt_fini(adev); 3090 3091 return 0; 3092 } 3093 3094 static int dce_v10_0_suspend(void *handle) 3095 { 3096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3097 3098 amdgpu_atombios_scratch_regs_save(adev); 3099 3100 return dce_v10_0_hw_fini(handle); 3101 } 3102 3103 static int dce_v10_0_resume(void *handle) 3104 { 3105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3106 int ret; 3107 3108 ret = dce_v10_0_hw_init(handle); 3109 3110 amdgpu_atombios_scratch_regs_restore(adev); 3111 3112 /* turn on the BL */ 3113 if (adev->mode_info.bl_encoder) { 3114 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3115 adev->mode_info.bl_encoder); 3116 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3117 bl_level); 3118 } 3119 3120 return ret; 3121 } 3122 3123 static bool dce_v10_0_is_idle(void *handle) 3124 { 3125 return true; 3126 } 3127 3128 static int dce_v10_0_wait_for_idle(void *handle) 3129 { 3130 return 0; 3131 } 3132 3133 static void dce_v10_0_print_status(void *handle) 3134 { 3135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3136 3137 dev_info(adev->dev, "DCE 10.x registers\n"); 3138 /* XXX todo */ 3139 } 3140 3141 static int dce_v10_0_soft_reset(void *handle) 3142 { 3143 u32 srbm_soft_reset = 0, tmp; 3144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3145 3146 if (dce_v10_0_is_display_hung(adev)) 3147 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3148 3149 if (srbm_soft_reset) { 3150 dce_v10_0_print_status((void *)adev); 3151 3152 tmp = RREG32(mmSRBM_SOFT_RESET); 3153 tmp |= srbm_soft_reset; 3154 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3155 WREG32(mmSRBM_SOFT_RESET, tmp); 3156 tmp = RREG32(mmSRBM_SOFT_RESET); 3157 3158 udelay(50); 3159 3160 tmp &= ~srbm_soft_reset; 3161 WREG32(mmSRBM_SOFT_RESET, tmp); 3162 tmp = RREG32(mmSRBM_SOFT_RESET); 3163 3164 /* Wait a little for things to settle down */ 3165 udelay(50); 3166 dce_v10_0_print_status((void *)adev); 3167 } 3168 return 0; 3169 } 3170 3171 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3172 int crtc, 3173 enum amdgpu_interrupt_state state) 3174 { 3175 u32 lb_interrupt_mask; 3176 3177 if (crtc >= adev->mode_info.num_crtc) { 3178 DRM_DEBUG("invalid crtc %d\n", crtc); 3179 return; 3180 } 3181 3182 switch (state) { 3183 case AMDGPU_IRQ_STATE_DISABLE: 3184 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3185 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3186 VBLANK_INTERRUPT_MASK, 0); 3187 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3188 break; 3189 case AMDGPU_IRQ_STATE_ENABLE: 3190 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3191 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3192 VBLANK_INTERRUPT_MASK, 1); 3193 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3194 break; 3195 default: 3196 break; 3197 } 3198 } 3199 3200 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3201 int crtc, 3202 enum amdgpu_interrupt_state state) 3203 { 3204 u32 lb_interrupt_mask; 3205 3206 if (crtc >= adev->mode_info.num_crtc) { 3207 DRM_DEBUG("invalid crtc %d\n", crtc); 3208 return; 3209 } 3210 3211 switch (state) { 3212 case AMDGPU_IRQ_STATE_DISABLE: 3213 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3214 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3215 VLINE_INTERRUPT_MASK, 0); 3216 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3217 break; 3218 case AMDGPU_IRQ_STATE_ENABLE: 3219 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3220 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3221 VLINE_INTERRUPT_MASK, 1); 3222 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3223 break; 3224 default: 3225 break; 3226 } 3227 } 3228 3229 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 3230 struct amdgpu_irq_src *source, 3231 unsigned hpd, 3232 enum amdgpu_interrupt_state state) 3233 { 3234 u32 tmp; 3235 3236 if (hpd >= adev->mode_info.num_hpd) { 3237 DRM_DEBUG("invalid hdp %d\n", hpd); 3238 return 0; 3239 } 3240 3241 switch (state) { 3242 case AMDGPU_IRQ_STATE_DISABLE: 3243 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3244 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3245 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3246 break; 3247 case AMDGPU_IRQ_STATE_ENABLE: 3248 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3249 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3250 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3251 break; 3252 default: 3253 break; 3254 } 3255 3256 return 0; 3257 } 3258 3259 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3260 struct amdgpu_irq_src *source, 3261 unsigned type, 3262 enum amdgpu_interrupt_state state) 3263 { 3264 switch (type) { 3265 case AMDGPU_CRTC_IRQ_VBLANK1: 3266 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3267 break; 3268 case AMDGPU_CRTC_IRQ_VBLANK2: 3269 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3270 break; 3271 case AMDGPU_CRTC_IRQ_VBLANK3: 3272 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3273 break; 3274 case AMDGPU_CRTC_IRQ_VBLANK4: 3275 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3276 break; 3277 case AMDGPU_CRTC_IRQ_VBLANK5: 3278 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3279 break; 3280 case AMDGPU_CRTC_IRQ_VBLANK6: 3281 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3282 break; 3283 case AMDGPU_CRTC_IRQ_VLINE1: 3284 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3285 break; 3286 case AMDGPU_CRTC_IRQ_VLINE2: 3287 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3288 break; 3289 case AMDGPU_CRTC_IRQ_VLINE3: 3290 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3291 break; 3292 case AMDGPU_CRTC_IRQ_VLINE4: 3293 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3294 break; 3295 case AMDGPU_CRTC_IRQ_VLINE5: 3296 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3297 break; 3298 case AMDGPU_CRTC_IRQ_VLINE6: 3299 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3300 break; 3301 default: 3302 break; 3303 } 3304 return 0; 3305 } 3306 3307 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3308 struct amdgpu_irq_src *src, 3309 unsigned type, 3310 enum amdgpu_interrupt_state state) 3311 { 3312 u32 reg; 3313 3314 if (type >= adev->mode_info.num_crtc) { 3315 DRM_ERROR("invalid pageflip crtc %d\n", type); 3316 return -EINVAL; 3317 } 3318 3319 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3320 if (state == AMDGPU_IRQ_STATE_DISABLE) 3321 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3322 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3323 else 3324 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3325 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3326 3327 return 0; 3328 } 3329 3330 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3331 struct amdgpu_irq_src *source, 3332 struct amdgpu_iv_entry *entry) 3333 { 3334 unsigned long flags; 3335 unsigned crtc_id; 3336 struct amdgpu_crtc *amdgpu_crtc; 3337 struct amdgpu_flip_work *works; 3338 3339 crtc_id = (entry->src_id - 8) >> 1; 3340 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3341 3342 if (crtc_id >= adev->mode_info.num_crtc) { 3343 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3344 return -EINVAL; 3345 } 3346 3347 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3348 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3349 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3350 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3351 3352 /* IRQ could occur when in initial stage */ 3353 if (amdgpu_crtc == NULL) 3354 return 0; 3355 3356 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3357 works = amdgpu_crtc->pflip_works; 3358 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3359 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3360 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3361 amdgpu_crtc->pflip_status, 3362 AMDGPU_FLIP_SUBMITTED); 3363 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3364 return 0; 3365 } 3366 3367 /* page flip completed. clean up */ 3368 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3369 amdgpu_crtc->pflip_works = NULL; 3370 3371 /* wakeup usersapce */ 3372 if (works->event) 3373 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3374 3375 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3376 3377 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3378 schedule_work(&works->unpin_work); 3379 3380 return 0; 3381 } 3382 3383 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3384 int hpd) 3385 { 3386 u32 tmp; 3387 3388 if (hpd >= adev->mode_info.num_hpd) { 3389 DRM_DEBUG("invalid hdp %d\n", hpd); 3390 return; 3391 } 3392 3393 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3394 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3395 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3396 } 3397 3398 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3399 int crtc) 3400 { 3401 u32 tmp; 3402 3403 if (crtc >= adev->mode_info.num_crtc) { 3404 DRM_DEBUG("invalid crtc %d\n", crtc); 3405 return; 3406 } 3407 3408 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3409 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3410 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3411 } 3412 3413 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3414 int crtc) 3415 { 3416 u32 tmp; 3417 3418 if (crtc >= adev->mode_info.num_crtc) { 3419 DRM_DEBUG("invalid crtc %d\n", crtc); 3420 return; 3421 } 3422 3423 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3424 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3425 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3426 } 3427 3428 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3429 struct amdgpu_irq_src *source, 3430 struct amdgpu_iv_entry *entry) 3431 { 3432 unsigned crtc = entry->src_id - 1; 3433 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3434 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3435 3436 switch (entry->src_data) { 3437 case 0: /* vblank */ 3438 if (disp_int & interrupt_status_offsets[crtc].vblank) 3439 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3440 else 3441 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3442 3443 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3444 drm_handle_vblank(adev->ddev, crtc); 3445 } 3446 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3447 3448 break; 3449 case 1: /* vline */ 3450 if (disp_int & interrupt_status_offsets[crtc].vline) 3451 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3452 else 3453 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3454 3455 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3456 3457 break; 3458 default: 3459 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3460 break; 3461 } 3462 3463 return 0; 3464 } 3465 3466 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3467 struct amdgpu_irq_src *source, 3468 struct amdgpu_iv_entry *entry) 3469 { 3470 uint32_t disp_int, mask; 3471 unsigned hpd; 3472 3473 if (entry->src_data >= adev->mode_info.num_hpd) { 3474 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3475 return 0; 3476 } 3477 3478 hpd = entry->src_data; 3479 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3480 mask = interrupt_status_offsets[hpd].hpd; 3481 3482 if (disp_int & mask) { 3483 dce_v10_0_hpd_int_ack(adev, hpd); 3484 schedule_work(&adev->hotplug_work); 3485 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3486 } 3487 3488 return 0; 3489 } 3490 3491 static int dce_v10_0_set_clockgating_state(void *handle, 3492 enum amd_clockgating_state state) 3493 { 3494 return 0; 3495 } 3496 3497 static int dce_v10_0_set_powergating_state(void *handle, 3498 enum amd_powergating_state state) 3499 { 3500 return 0; 3501 } 3502 3503 const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3504 .early_init = dce_v10_0_early_init, 3505 .late_init = NULL, 3506 .sw_init = dce_v10_0_sw_init, 3507 .sw_fini = dce_v10_0_sw_fini, 3508 .hw_init = dce_v10_0_hw_init, 3509 .hw_fini = dce_v10_0_hw_fini, 3510 .suspend = dce_v10_0_suspend, 3511 .resume = dce_v10_0_resume, 3512 .is_idle = dce_v10_0_is_idle, 3513 .wait_for_idle = dce_v10_0_wait_for_idle, 3514 .soft_reset = dce_v10_0_soft_reset, 3515 .print_status = dce_v10_0_print_status, 3516 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3517 .set_powergating_state = dce_v10_0_set_powergating_state, 3518 }; 3519 3520 static void 3521 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3522 struct drm_display_mode *mode, 3523 struct drm_display_mode *adjusted_mode) 3524 { 3525 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3526 3527 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3528 3529 /* need to call this here rather than in prepare() since we need some crtc info */ 3530 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3531 3532 /* set scaler clears this on some chips */ 3533 dce_v10_0_set_interleave(encoder->crtc, mode); 3534 3535 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3536 dce_v10_0_afmt_enable(encoder, true); 3537 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3538 } 3539 } 3540 3541 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3542 { 3543 struct amdgpu_device *adev = encoder->dev->dev_private; 3544 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3545 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3546 3547 if ((amdgpu_encoder->active_device & 3548 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3549 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3550 ENCODER_OBJECT_ID_NONE)) { 3551 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3552 if (dig) { 3553 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3554 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3555 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3556 } 3557 } 3558 3559 amdgpu_atombios_scratch_regs_lock(adev, true); 3560 3561 if (connector) { 3562 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3563 3564 /* select the clock/data port if it uses a router */ 3565 if (amdgpu_connector->router.cd_valid) 3566 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3567 3568 /* turn eDP panel on for mode set */ 3569 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3570 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3571 ATOM_TRANSMITTER_ACTION_POWER_ON); 3572 } 3573 3574 /* this is needed for the pll/ss setup to work correctly in some cases */ 3575 amdgpu_atombios_encoder_set_crtc_source(encoder); 3576 /* set up the FMT blocks */ 3577 dce_v10_0_program_fmt(encoder); 3578 } 3579 3580 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3581 { 3582 struct drm_device *dev = encoder->dev; 3583 struct amdgpu_device *adev = dev->dev_private; 3584 3585 /* need to call this here as we need the crtc set up */ 3586 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3587 amdgpu_atombios_scratch_regs_lock(adev, false); 3588 } 3589 3590 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3591 { 3592 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3593 struct amdgpu_encoder_atom_dig *dig; 3594 3595 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3596 3597 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3598 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3599 dce_v10_0_afmt_enable(encoder, false); 3600 dig = amdgpu_encoder->enc_priv; 3601 dig->dig_encoder = -1; 3602 } 3603 amdgpu_encoder->active_device = 0; 3604 } 3605 3606 /* these are handled by the primary encoders */ 3607 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3608 { 3609 3610 } 3611 3612 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3613 { 3614 3615 } 3616 3617 static void 3618 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3619 struct drm_display_mode *mode, 3620 struct drm_display_mode *adjusted_mode) 3621 { 3622 3623 } 3624 3625 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3626 { 3627 3628 } 3629 3630 static void 3631 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3632 { 3633 3634 } 3635 3636 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3637 .dpms = dce_v10_0_ext_dpms, 3638 .prepare = dce_v10_0_ext_prepare, 3639 .mode_set = dce_v10_0_ext_mode_set, 3640 .commit = dce_v10_0_ext_commit, 3641 .disable = dce_v10_0_ext_disable, 3642 /* no detect for TMDS/LVDS yet */ 3643 }; 3644 3645 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3646 .dpms = amdgpu_atombios_encoder_dpms, 3647 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3648 .prepare = dce_v10_0_encoder_prepare, 3649 .mode_set = dce_v10_0_encoder_mode_set, 3650 .commit = dce_v10_0_encoder_commit, 3651 .disable = dce_v10_0_encoder_disable, 3652 .detect = amdgpu_atombios_encoder_dig_detect, 3653 }; 3654 3655 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3656 .dpms = amdgpu_atombios_encoder_dpms, 3657 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3658 .prepare = dce_v10_0_encoder_prepare, 3659 .mode_set = dce_v10_0_encoder_mode_set, 3660 .commit = dce_v10_0_encoder_commit, 3661 .detect = amdgpu_atombios_encoder_dac_detect, 3662 }; 3663 3664 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3665 { 3666 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3667 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3668 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3669 kfree(amdgpu_encoder->enc_priv); 3670 drm_encoder_cleanup(encoder); 3671 kfree(amdgpu_encoder); 3672 } 3673 3674 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3675 .destroy = dce_v10_0_encoder_destroy, 3676 }; 3677 3678 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3679 uint32_t encoder_enum, 3680 uint32_t supported_device, 3681 u16 caps) 3682 { 3683 struct drm_device *dev = adev->ddev; 3684 struct drm_encoder *encoder; 3685 struct amdgpu_encoder *amdgpu_encoder; 3686 3687 /* see if we already added it */ 3688 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3689 amdgpu_encoder = to_amdgpu_encoder(encoder); 3690 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3691 amdgpu_encoder->devices |= supported_device; 3692 return; 3693 } 3694 3695 } 3696 3697 /* add a new one */ 3698 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3699 if (!amdgpu_encoder) 3700 return; 3701 3702 encoder = &amdgpu_encoder->base; 3703 switch (adev->mode_info.num_crtc) { 3704 case 1: 3705 encoder->possible_crtcs = 0x1; 3706 break; 3707 case 2: 3708 default: 3709 encoder->possible_crtcs = 0x3; 3710 break; 3711 case 4: 3712 encoder->possible_crtcs = 0xf; 3713 break; 3714 case 6: 3715 encoder->possible_crtcs = 0x3f; 3716 break; 3717 } 3718 3719 amdgpu_encoder->enc_priv = NULL; 3720 3721 amdgpu_encoder->encoder_enum = encoder_enum; 3722 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3723 amdgpu_encoder->devices = supported_device; 3724 amdgpu_encoder->rmx_type = RMX_OFF; 3725 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3726 amdgpu_encoder->is_ext_encoder = false; 3727 amdgpu_encoder->caps = caps; 3728 3729 switch (amdgpu_encoder->encoder_id) { 3730 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3731 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3732 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3733 DRM_MODE_ENCODER_DAC, NULL); 3734 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3735 break; 3736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3738 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3741 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3742 amdgpu_encoder->rmx_type = RMX_FULL; 3743 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3744 DRM_MODE_ENCODER_LVDS, NULL); 3745 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3746 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3747 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3748 DRM_MODE_ENCODER_DAC, NULL); 3749 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3750 } else { 3751 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3752 DRM_MODE_ENCODER_TMDS, NULL); 3753 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3754 } 3755 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3756 break; 3757 case ENCODER_OBJECT_ID_SI170B: 3758 case ENCODER_OBJECT_ID_CH7303: 3759 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3760 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3761 case ENCODER_OBJECT_ID_TITFP513: 3762 case ENCODER_OBJECT_ID_VT1623: 3763 case ENCODER_OBJECT_ID_HDMI_SI1930: 3764 case ENCODER_OBJECT_ID_TRAVIS: 3765 case ENCODER_OBJECT_ID_NUTMEG: 3766 /* these are handled by the primary encoders */ 3767 amdgpu_encoder->is_ext_encoder = true; 3768 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3769 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3770 DRM_MODE_ENCODER_LVDS, NULL); 3771 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3772 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3773 DRM_MODE_ENCODER_DAC, NULL); 3774 else 3775 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3776 DRM_MODE_ENCODER_TMDS, NULL); 3777 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3778 break; 3779 } 3780 } 3781 3782 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3783 .set_vga_render_state = &dce_v10_0_set_vga_render_state, 3784 .bandwidth_update = &dce_v10_0_bandwidth_update, 3785 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3786 .vblank_wait = &dce_v10_0_vblank_wait, 3787 .is_display_hung = &dce_v10_0_is_display_hung, 3788 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3789 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3790 .hpd_sense = &dce_v10_0_hpd_sense, 3791 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3792 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3793 .page_flip = &dce_v10_0_page_flip, 3794 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3795 .add_encoder = &dce_v10_0_encoder_add, 3796 .add_connector = &amdgpu_connector_add, 3797 .stop_mc_access = &dce_v10_0_stop_mc_access, 3798 .resume_mc_access = &dce_v10_0_resume_mc_access, 3799 }; 3800 3801 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3802 { 3803 if (adev->mode_info.funcs == NULL) 3804 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3805 } 3806 3807 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3808 .set = dce_v10_0_set_crtc_irq_state, 3809 .process = dce_v10_0_crtc_irq, 3810 }; 3811 3812 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3813 .set = dce_v10_0_set_pageflip_irq_state, 3814 .process = dce_v10_0_pageflip_irq, 3815 }; 3816 3817 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3818 .set = dce_v10_0_set_hpd_irq_state, 3819 .process = dce_v10_0_hpd_irq, 3820 }; 3821 3822 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3823 { 3824 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3825 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3826 3827 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3828 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3829 3830 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3831 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3832 } 3833