1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "vid.h" 29 30 #include "oss/oss_3_0_1_d.h" 31 #include "oss/oss_3_0_1_sh_mask.h" 32 33 #include "bif/bif_5_1_d.h" 34 #include "bif/bif_5_1_sh_mask.h" 35 36 /* 37 * Interrupts 38 * Starting with r6xx, interrupts are handled via a ring buffer. 39 * Ring buffers are areas of GPU accessible memory that the GPU 40 * writes interrupt vectors into and the host reads vectors out of. 41 * There is a rptr (read pointer) that determines where the 42 * host is currently reading, and a wptr (write pointer) 43 * which determines where the GPU has written. When the 44 * pointers are equal, the ring is idle. When the GPU 45 * writes vectors to the ring buffer, it increments the 46 * wptr. When there is an interrupt, the host then starts 47 * fetching commands and processing them until the pointers are 48 * equal again at which point it updates the rptr. 49 */ 50 51 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev); 52 53 /** 54 * cz_ih_enable_interrupts - Enable the interrupt ring buffer 55 * 56 * @adev: amdgpu_device pointer 57 * 58 * Enable the interrupt ring buffer (VI). 59 */ 60 static void cz_ih_enable_interrupts(struct amdgpu_device *adev) 61 { 62 u32 ih_cntl = RREG32(mmIH_CNTL); 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 64 65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 67 WREG32(mmIH_CNTL, ih_cntl); 68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 69 adev->irq.ih.enabled = true; 70 } 71 72 /** 73 * cz_ih_disable_interrupts - Disable the interrupt ring buffer 74 * 75 * @adev: amdgpu_device pointer 76 * 77 * Disable the interrupt ring buffer (VI). 78 */ 79 static void cz_ih_disable_interrupts(struct amdgpu_device *adev) 80 { 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 82 u32 ih_cntl = RREG32(mmIH_CNTL); 83 84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); 86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 87 WREG32(mmIH_CNTL, ih_cntl); 88 /* set rptr, wptr to 0 */ 89 WREG32(mmIH_RB_RPTR, 0); 90 WREG32(mmIH_RB_WPTR, 0); 91 adev->irq.ih.enabled = false; 92 adev->irq.ih.rptr = 0; 93 } 94 95 /** 96 * cz_ih_irq_init - init and enable the interrupt ring 97 * 98 * @adev: amdgpu_device pointer 99 * 100 * Allocate a ring buffer for the interrupt controller, 101 * enable the RLC, disable interrupts, enable the IH 102 * ring buffer and enable it (VI). 103 * Called at device load and reume. 104 * Returns 0 for success, errors for failure. 105 */ 106 static int cz_ih_irq_init(struct amdgpu_device *adev) 107 { 108 struct amdgpu_ih_ring *ih = &adev->irq.ih; 109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 110 int rb_bufsz; 111 112 /* disable irqs */ 113 cz_ih_disable_interrupts(adev); 114 115 /* setup interrupt control */ 116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 118 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 119 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 120 */ 121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 122 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 125 126 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 128 129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 133 134 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 136 137 /* set the writeback address whether it's enabled or not */ 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 140 141 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 142 143 /* set rptr, wptr to 0 */ 144 WREG32(mmIH_RB_RPTR, 0); 145 WREG32(mmIH_RB_WPTR, 0); 146 147 /* Default settings for IH_CNTL (disabled at first) */ 148 ih_cntl = RREG32(mmIH_CNTL); 149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); 150 151 if (adev->irq.msi_enabled) 152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); 153 WREG32(mmIH_CNTL, ih_cntl); 154 155 pci_set_master(adev->pdev); 156 157 /* enable interrupts */ 158 cz_ih_enable_interrupts(adev); 159 160 if (adev->irq.ih_soft.ring_size) 161 adev->irq.ih_soft.enabled = true; 162 163 return 0; 164 } 165 166 /** 167 * cz_ih_irq_disable - disable interrupts 168 * 169 * @adev: amdgpu_device pointer 170 * 171 * Disable interrupts on the hw (VI). 172 */ 173 static void cz_ih_irq_disable(struct amdgpu_device *adev) 174 { 175 cz_ih_disable_interrupts(adev); 176 177 /* Wait and acknowledge irq */ 178 mdelay(1); 179 } 180 181 /** 182 * cz_ih_get_wptr - get the IH ring buffer wptr 183 * 184 * @adev: amdgpu_device pointer 185 * @ih: IH ring buffer to fetch wptr 186 * 187 * Get the IH ring buffer wptr from either the register 188 * or the writeback memory buffer (VI). Also check for 189 * ring buffer overflow and deal with it. 190 * Used by cz_irq_process(VI). 191 * Returns the value of the wptr. 192 */ 193 static u32 cz_ih_get_wptr(struct amdgpu_device *adev, 194 struct amdgpu_ih_ring *ih) 195 { 196 u32 wptr, tmp; 197 198 wptr = le32_to_cpu(*ih->wptr_cpu); 199 200 if (ih == &adev->irq.ih_soft) 201 goto out; 202 203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 204 goto out; 205 206 /* Double check that the overflow wasn't already cleared. */ 207 wptr = RREG32(mmIH_RB_WPTR); 208 209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 210 goto out; 211 212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 213 214 /* When a ring buffer overflow happen start parsing interrupt 215 * from the last not overwritten vector (wptr + 16). Hopefully 216 * this should allow us to catchup. 217 */ 218 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 219 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 220 ih->rptr = (wptr + 16) & ih->ptr_mask; 221 tmp = RREG32(mmIH_RB_CNTL); 222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 223 WREG32(mmIH_RB_CNTL, tmp); 224 225 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 226 * can be detected. 227 */ 228 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 229 WREG32(mmIH_RB_CNTL, tmp); 230 231 out: 232 return (wptr & ih->ptr_mask); 233 } 234 235 /** 236 * cz_ih_decode_iv - decode an interrupt vector 237 * 238 * @adev: amdgpu_device pointer 239 * @ih: IH ring buffer to decode 240 * @entry: IV entry to place decoded information into 241 * 242 * Decodes the interrupt vector at the current rptr 243 * position and also advance the position. 244 */ 245 static void cz_ih_decode_iv(struct amdgpu_device *adev, 246 struct amdgpu_ih_ring *ih, 247 struct amdgpu_iv_entry *entry) 248 { 249 /* wptr/rptr are in bytes! */ 250 u32 ring_index = ih->rptr >> 2; 251 uint32_t dw[4]; 252 253 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 254 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 255 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 256 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 257 258 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 259 entry->src_id = dw[0] & 0xff; 260 entry->src_data[0] = dw[1] & 0xfffffff; 261 entry->ring_id = dw[2] & 0xff; 262 entry->vmid = (dw[2] >> 8) & 0xff; 263 entry->pasid = (dw[2] >> 16) & 0xffff; 264 265 /* wptr/rptr are in bytes! */ 266 ih->rptr += 16; 267 } 268 269 /** 270 * cz_ih_set_rptr - set the IH ring buffer rptr 271 * 272 * @adev: amdgpu_device pointer 273 * @ih: IH ring buffer to set rptr 274 * 275 * Set the IH ring buffer rptr. 276 */ 277 static void cz_ih_set_rptr(struct amdgpu_device *adev, 278 struct amdgpu_ih_ring *ih) 279 { 280 WREG32(mmIH_RB_RPTR, ih->rptr); 281 } 282 283 static int cz_ih_early_init(struct amdgpu_ip_block *ip_block) 284 { 285 struct amdgpu_device *adev = ip_block->adev; 286 int ret; 287 288 ret = amdgpu_irq_add_domain(adev); 289 if (ret) 290 return ret; 291 292 cz_ih_set_interrupt_funcs(adev); 293 294 return 0; 295 } 296 297 static int cz_ih_sw_init(struct amdgpu_ip_block *ip_block) 298 { 299 int r; 300 struct amdgpu_device *adev = ip_block->adev; 301 302 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 303 if (r) 304 return r; 305 306 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); 307 if (r) 308 return r; 309 310 r = amdgpu_irq_init(adev); 311 312 return r; 313 } 314 315 static int cz_ih_sw_fini(struct amdgpu_ip_block *ip_block) 316 { 317 struct amdgpu_device *adev = ip_block->adev; 318 319 amdgpu_irq_fini_sw(adev); 320 amdgpu_irq_remove_domain(adev); 321 322 return 0; 323 } 324 325 static int cz_ih_hw_init(struct amdgpu_ip_block *ip_block) 326 { 327 int r; 328 struct amdgpu_device *adev = ip_block->adev; 329 330 r = cz_ih_irq_init(adev); 331 if (r) 332 return r; 333 334 return 0; 335 } 336 337 static int cz_ih_hw_fini(struct amdgpu_ip_block *ip_block) 338 { 339 cz_ih_irq_disable(ip_block->adev); 340 341 return 0; 342 } 343 344 static int cz_ih_suspend(struct amdgpu_ip_block *ip_block) 345 { 346 return cz_ih_hw_fini(ip_block); 347 } 348 349 static int cz_ih_resume(struct amdgpu_ip_block *ip_block) 350 { 351 return cz_ih_hw_init(ip_block); 352 } 353 354 static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block) 355 { 356 struct amdgpu_device *adev = ip_block->adev; 357 u32 tmp = RREG32(mmSRBM_STATUS); 358 359 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 360 return false; 361 362 return true; 363 } 364 365 static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) 366 { 367 unsigned i; 368 u32 tmp; 369 struct amdgpu_device *adev = ip_block->adev; 370 371 for (i = 0; i < adev->usec_timeout; i++) { 372 /* read MC_STATUS */ 373 tmp = RREG32(mmSRBM_STATUS); 374 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 375 return 0; 376 udelay(1); 377 } 378 return -ETIMEDOUT; 379 } 380 381 static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block) 382 { 383 u32 srbm_soft_reset = 0; 384 struct amdgpu_device *adev = ip_block->adev; 385 u32 tmp = RREG32(mmSRBM_STATUS); 386 387 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 388 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 389 SOFT_RESET_IH, 1); 390 391 if (srbm_soft_reset) { 392 tmp = RREG32(mmSRBM_SOFT_RESET); 393 tmp |= srbm_soft_reset; 394 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 395 WREG32(mmSRBM_SOFT_RESET, tmp); 396 tmp = RREG32(mmSRBM_SOFT_RESET); 397 398 udelay(50); 399 400 tmp &= ~srbm_soft_reset; 401 WREG32(mmSRBM_SOFT_RESET, tmp); 402 tmp = RREG32(mmSRBM_SOFT_RESET); 403 404 /* Wait a little for things to settle down */ 405 udelay(50); 406 } 407 408 return 0; 409 } 410 411 static int cz_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block, 412 enum amd_clockgating_state state) 413 { 414 // TODO 415 return 0; 416 } 417 418 static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block, 419 enum amd_powergating_state state) 420 { 421 // TODO 422 return 0; 423 } 424 425 static const struct amd_ip_funcs cz_ih_ip_funcs = { 426 .name = "cz_ih", 427 .early_init = cz_ih_early_init, 428 .sw_init = cz_ih_sw_init, 429 .sw_fini = cz_ih_sw_fini, 430 .hw_init = cz_ih_hw_init, 431 .hw_fini = cz_ih_hw_fini, 432 .suspend = cz_ih_suspend, 433 .resume = cz_ih_resume, 434 .is_idle = cz_ih_is_idle, 435 .wait_for_idle = cz_ih_wait_for_idle, 436 .soft_reset = cz_ih_soft_reset, 437 .set_clockgating_state = cz_ih_set_clockgating_state, 438 .set_powergating_state = cz_ih_set_powergating_state, 439 }; 440 441 static const struct amdgpu_ih_funcs cz_ih_funcs = { 442 .get_wptr = cz_ih_get_wptr, 443 .decode_iv = cz_ih_decode_iv, 444 .set_rptr = cz_ih_set_rptr 445 }; 446 447 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) 448 { 449 adev->irq.ih_funcs = &cz_ih_funcs; 450 } 451 452 const struct amdgpu_ip_block_version cz_ih_ip_block = 453 { 454 .type = AMD_IP_BLOCK_TYPE_IH, 455 .major = 3, 456 .minor = 0, 457 .rev = 0, 458 .funcs = &cz_ih_ip_funcs, 459 }; 460