1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ucode.h" 30 #include "amdgpu_sdma.h" 31 #include "amdgpu_trace.h" 32 #include "cikd.h" 33 #include "cik.h" 34 35 #include "bif/bif_4_1_d.h" 36 #include "bif/bif_4_1_sh_mask.h" 37 38 #include "gca/gfx_7_2_d.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "gca/gfx_7_2_sh_mask.h" 41 42 #include "gmc/gmc_7_1_d.h" 43 #include "gmc/gmc_7_1_sh_mask.h" 44 45 #include "oss/oss_2_0_d.h" 46 #include "oss/oss_2_0_sh_mask.h" 47 48 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 49 { 50 SDMA0_REGISTER_OFFSET, 51 SDMA1_REGISTER_OFFSET 52 }; 53 54 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 55 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 56 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 57 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); 58 59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin"); 69 70 static void cik_sdma_free_microcode(struct amdgpu_device *adev) 71 { 72 int i; 73 74 for (i = 0; i < adev->sdma.num_instances; i++) 75 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 76 } 77 78 /* 79 * sDMA - System DMA 80 * Starting with CIK, the GPU has new asynchronous 81 * DMA engines. These engines are used for compute 82 * and gfx. There are two DMA engines (SDMA0, SDMA1) 83 * and each one supports 1 ring buffer used for gfx 84 * and 2 queues used for compute. 85 * 86 * The programming model is very similar to the CP 87 * (ring buffer, IBs, etc.), but sDMA has it's own 88 * packet format that is different from the PM4 format 89 * used by the CP. sDMA supports copying data, writing 90 * embedded data, solid fills, and a number of other 91 * things. It also has support for tiling/detiling of 92 * buffers. 93 */ 94 95 /** 96 * cik_sdma_init_microcode - load ucode images from disk 97 * 98 * @adev: amdgpu_device pointer 99 * 100 * Use the firmware interface to load the ucode images into 101 * the driver (not loaded into hw). 102 * Returns 0 on success, error on failure. 103 */ 104 static int cik_sdma_init_microcode(struct amdgpu_device *adev) 105 { 106 const char *chip_name; 107 int err = 0, i; 108 109 DRM_DEBUG("\n"); 110 111 switch (adev->asic_type) { 112 case CHIP_BONAIRE: 113 chip_name = "bonaire"; 114 break; 115 case CHIP_HAWAII: 116 chip_name = "hawaii"; 117 break; 118 case CHIP_KAVERI: 119 chip_name = "kaveri"; 120 break; 121 case CHIP_KABINI: 122 chip_name = "kabini"; 123 break; 124 case CHIP_MULLINS: 125 chip_name = "mullins"; 126 break; 127 default: 128 return -EINVAL; 129 } 130 131 for (i = 0; i < adev->sdma.num_instances; i++) { 132 if (i == 0) 133 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 134 AMDGPU_UCODE_REQUIRED, 135 "amdgpu/%s_sdma.bin", chip_name); 136 else 137 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 138 AMDGPU_UCODE_REQUIRED, 139 "amdgpu/%s_sdma1.bin", chip_name); 140 if (err) 141 goto out; 142 } 143 out: 144 if (err) { 145 pr_err("cik_sdma: Failed to load firmware \"%s_sdma%s.bin\"\n", 146 chip_name, i == 0 ? "" : "1"); 147 for (i = 0; i < adev->sdma.num_instances; i++) 148 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 149 } 150 return err; 151 } 152 153 /** 154 * cik_sdma_ring_get_rptr - get the current read pointer 155 * 156 * @ring: amdgpu ring pointer 157 * 158 * Get the current rptr from the hardware (CIK+). 159 */ 160 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 161 { 162 u32 rptr; 163 164 rptr = *ring->rptr_cpu_addr; 165 166 return (rptr & 0x3fffc) >> 2; 167 } 168 169 /** 170 * cik_sdma_ring_get_wptr - get the current write pointer 171 * 172 * @ring: amdgpu ring pointer 173 * 174 * Get the current wptr from the hardware (CIK+). 175 */ 176 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) 177 { 178 struct amdgpu_device *adev = ring->adev; 179 180 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; 181 } 182 183 /** 184 * cik_sdma_ring_set_wptr - commit the write pointer 185 * 186 * @ring: amdgpu ring pointer 187 * 188 * Write the wptr back to the hardware (CIK+). 189 */ 190 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 191 { 192 struct amdgpu_device *adev = ring->adev; 193 194 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], 195 (ring->wptr << 2) & 0x3fffc); 196 } 197 198 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 199 { 200 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 201 int i; 202 203 for (i = 0; i < count; i++) 204 if (sdma && sdma->burst_nop && (i == 0)) 205 amdgpu_ring_write(ring, ring->funcs->nop | 206 SDMA_NOP_COUNT(count - 1)); 207 else 208 amdgpu_ring_write(ring, ring->funcs->nop); 209 } 210 211 /** 212 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine 213 * 214 * @ring: amdgpu ring pointer 215 * @job: job to retrive vmid from 216 * @ib: IB object to schedule 217 * @flags: unused 218 * 219 * Schedule an IB in the DMA ring (CIK). 220 */ 221 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 222 struct amdgpu_job *job, 223 struct amdgpu_ib *ib, 224 uint32_t flags) 225 { 226 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 227 u32 extra_bits = vmid & 0xf; 228 229 /* IB packet must end on a 8 DW boundary */ 230 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); 231 232 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 233 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 234 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 235 amdgpu_ring_write(ring, ib->length_dw); 236 237 } 238 239 /** 240 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 241 * 242 * @ring: amdgpu ring pointer 243 * 244 * Emit an hdp flush packet on the requested DMA ring. 245 */ 246 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 247 { 248 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 249 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 250 u32 ref_and_mask; 251 252 if (ring->me == 0) 253 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; 254 else 255 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; 256 257 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 260 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 261 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 262 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 263 } 264 265 /** 266 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring 267 * 268 * @ring: amdgpu ring pointer 269 * @addr: address 270 * @seq: sequence number 271 * @flags: fence related flags 272 * 273 * Add a DMA fence packet to the ring to write 274 * the fence seq number and DMA trap packet to generate 275 * an interrupt if needed (CIK). 276 */ 277 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 278 unsigned flags) 279 { 280 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 281 /* write the fence */ 282 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 283 amdgpu_ring_write(ring, lower_32_bits(addr)); 284 amdgpu_ring_write(ring, upper_32_bits(addr)); 285 amdgpu_ring_write(ring, lower_32_bits(seq)); 286 287 /* optionally write high bits as well */ 288 if (write64bit) { 289 addr += 4; 290 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 291 amdgpu_ring_write(ring, lower_32_bits(addr)); 292 amdgpu_ring_write(ring, upper_32_bits(addr)); 293 amdgpu_ring_write(ring, upper_32_bits(seq)); 294 } 295 296 /* generate an interrupt */ 297 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 298 } 299 300 /** 301 * cik_sdma_gfx_stop - stop the gfx async dma engines 302 * 303 * @adev: amdgpu_device pointer 304 * 305 * Stop the gfx async dma ring buffers (CIK). 306 */ 307 static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 308 { 309 u32 rb_cntl; 310 int i; 311 312 for (i = 0; i < adev->sdma.num_instances; i++) { 313 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 314 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; 315 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 316 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); 317 } 318 } 319 320 /** 321 * cik_ctx_switch_enable - stop the async dma engines context switch 322 * 323 * @adev: amdgpu_device pointer 324 * @enable: enable/disable the DMA MEs context switch. 325 * 326 * Halt or unhalt the async dma engines context switch (VI). 327 */ 328 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 329 { 330 u32 f32_cntl, phase_quantum = 0; 331 int i; 332 333 if (amdgpu_sdma_phase_quantum) { 334 unsigned value = amdgpu_sdma_phase_quantum; 335 unsigned unit = 0; 336 337 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 338 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 339 value = (value + 1) >> 1; 340 unit++; 341 } 342 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 343 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 344 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 345 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 346 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 347 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 348 WARN_ONCE(1, 349 "clamping sdma_phase_quantum to %uK clock cycles\n", 350 value << unit); 351 } 352 phase_quantum = 353 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 354 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 355 } 356 357 for (i = 0; i < adev->sdma.num_instances; i++) { 358 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 359 if (enable) { 360 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 361 AUTO_CTXSW_ENABLE, 1); 362 if (amdgpu_sdma_phase_quantum) { 363 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 364 phase_quantum); 365 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 366 phase_quantum); 367 } 368 } else { 369 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 370 AUTO_CTXSW_ENABLE, 0); 371 } 372 373 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 374 } 375 } 376 377 /** 378 * cik_sdma_enable - stop the async dma engines 379 * 380 * @adev: amdgpu_device pointer 381 * @enable: enable/disable the DMA MEs. 382 * 383 * Halt or unhalt the async dma engines (CIK). 384 */ 385 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) 386 { 387 u32 me_cntl; 388 int i; 389 390 if (!enable) { 391 cik_sdma_gfx_stop(adev); 392 } 393 394 for (i = 0; i < adev->sdma.num_instances; i++) { 395 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 396 if (enable) 397 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; 398 else 399 me_cntl |= SDMA0_F32_CNTL__HALT_MASK; 400 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); 401 } 402 } 403 404 /** 405 * cik_sdma_gfx_resume - setup and start the async dma engines 406 * 407 * @adev: amdgpu_device pointer 408 * 409 * Set up the gfx DMA ring buffers and enable them (CIK). 410 * Returns 0 for success, error for failure. 411 */ 412 static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 413 { 414 struct amdgpu_ring *ring; 415 u32 rb_cntl, ib_cntl; 416 u32 rb_bufsz; 417 int i, j, r; 418 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 ring = &adev->sdma.instance[i].ring; 421 422 mutex_lock(&adev->srbm_mutex); 423 for (j = 0; j < 16; j++) { 424 cik_srbm_select(adev, 0, 0, 0, j); 425 /* SDMA GFX */ 426 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 427 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 428 /* XXX SDMA RLC - todo */ 429 } 430 cik_srbm_select(adev, 0, 0, 0, 0); 431 mutex_unlock(&adev->srbm_mutex); 432 433 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 434 adev->gfx.config.gb_addr_config & 0x70); 435 436 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 437 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 438 439 /* Set ring buffer size in dwords */ 440 rb_bufsz = order_base_2(ring->ring_size / 4); 441 rb_cntl = rb_bufsz << 1; 442 #ifdef __BIG_ENDIAN 443 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | 444 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; 445 #endif 446 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 447 448 /* Initialize the ring buffer's read and write pointers */ 449 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 450 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 451 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 452 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 453 454 /* set the wb address whether it's enabled or not */ 455 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 456 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 457 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 458 ((ring->rptr_gpu_addr) & 0xFFFFFFFC)); 459 460 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; 461 462 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 463 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 464 465 ring->wptr = 0; 466 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 467 468 /* enable DMA RB */ 469 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], 470 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); 471 472 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; 473 #ifdef __BIG_ENDIAN 474 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; 475 #endif 476 /* enable DMA IBs */ 477 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 478 } 479 480 cik_sdma_enable(adev, true); 481 482 for (i = 0; i < adev->sdma.num_instances; i++) { 483 ring = &adev->sdma.instance[i].ring; 484 r = amdgpu_ring_test_helper(ring); 485 if (r) 486 return r; 487 } 488 489 return 0; 490 } 491 492 /** 493 * cik_sdma_load_microcode - load the sDMA ME ucode 494 * 495 * @adev: amdgpu_device pointer 496 * 497 * Loads the sDMA0/1 ucode. 498 * Returns 0 for success, -EINVAL if the ucode is not available. 499 */ 500 static int cik_sdma_load_microcode(struct amdgpu_device *adev) 501 { 502 const struct sdma_firmware_header_v1_0 *hdr; 503 const __le32 *fw_data; 504 u32 fw_size; 505 int i, j; 506 507 /* halt the MEs */ 508 cik_sdma_enable(adev, false); 509 510 for (i = 0; i < adev->sdma.num_instances; i++) { 511 if (!adev->sdma.instance[i].fw) 512 return -EINVAL; 513 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 514 amdgpu_ucode_print_sdma_hdr(&hdr->header); 515 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 516 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 517 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 518 if (adev->sdma.instance[i].feature_version >= 20) 519 adev->sdma.instance[i].burst_nop = true; 520 fw_data = (const __le32 *) 521 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 522 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 523 for (j = 0; j < fw_size; j++) 524 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 525 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 526 } 527 528 return 0; 529 } 530 531 /** 532 * cik_sdma_start - setup and start the async dma engines 533 * 534 * @adev: amdgpu_device pointer 535 * 536 * Set up the DMA engines and enable them (CIK). 537 * Returns 0 for success, error for failure. 538 */ 539 static int cik_sdma_start(struct amdgpu_device *adev) 540 { 541 int r; 542 543 r = cik_sdma_load_microcode(adev); 544 if (r) 545 return r; 546 547 /* halt the engine before programing */ 548 cik_sdma_enable(adev, false); 549 /* enable sdma ring preemption */ 550 cik_ctx_switch_enable(adev, true); 551 552 /* start the gfx rings and rlc compute queues */ 553 r = cik_sdma_gfx_resume(adev); 554 if (r) 555 return r; 556 557 return 0; 558 } 559 560 /** 561 * cik_sdma_ring_test_ring - simple async dma engine test 562 * 563 * @ring: amdgpu_ring structure holding ring information 564 * 565 * Test the DMA engine by writing using it to write an 566 * value to memory. (CIK). 567 * Returns 0 for success, error for failure. 568 */ 569 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) 570 { 571 struct amdgpu_device *adev = ring->adev; 572 unsigned i; 573 unsigned index; 574 int r; 575 u32 tmp; 576 u64 gpu_addr; 577 578 r = amdgpu_wb_get(adev, &index); 579 if (r) 580 return r; 581 582 gpu_addr = adev->wb.gpu_addr + (index * 4); 583 tmp = 0xCAFEDEAD; 584 adev->wb.wb[index] = cpu_to_le32(tmp); 585 586 r = amdgpu_ring_alloc(ring, 5); 587 if (r) 588 goto error_free_wb; 589 590 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 591 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 592 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 593 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ 594 amdgpu_ring_write(ring, 0xDEADBEEF); 595 amdgpu_ring_commit(ring); 596 597 for (i = 0; i < adev->usec_timeout; i++) { 598 tmp = le32_to_cpu(adev->wb.wb[index]); 599 if (tmp == 0xDEADBEEF) 600 break; 601 udelay(1); 602 } 603 604 if (i >= adev->usec_timeout) 605 r = -ETIMEDOUT; 606 607 error_free_wb: 608 amdgpu_wb_free(adev, index); 609 return r; 610 } 611 612 /** 613 * cik_sdma_ring_test_ib - test an IB on the DMA engine 614 * 615 * @ring: amdgpu_ring structure holding ring information 616 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 617 * 618 * Test a simple IB in the DMA ring (CIK). 619 * Returns 0 on success, error on failure. 620 */ 621 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 622 { 623 struct amdgpu_device *adev = ring->adev; 624 struct amdgpu_job *job; 625 struct amdgpu_ib *ib; 626 struct dma_fence *f = NULL; 627 unsigned index; 628 u32 tmp = 0; 629 u64 gpu_addr; 630 long r; 631 632 r = amdgpu_wb_get(adev, &index); 633 if (r) 634 return r; 635 636 gpu_addr = adev->wb.gpu_addr + (index * 4); 637 tmp = 0xCAFEDEAD; 638 adev->wb.wb[index] = cpu_to_le32(tmp); 639 640 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256, 641 AMDGPU_IB_POOL_DIRECT, 642 AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST, 643 &job); 644 if (r) 645 goto err0; 646 ib = &job->ibs[0]; 647 648 ib->ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, 649 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 650 ib->ptr[1] = lower_32_bits(gpu_addr); 651 ib->ptr[2] = upper_32_bits(gpu_addr); 652 ib->ptr[3] = 1; 653 ib->ptr[4] = 0xDEADBEEF; 654 ib->length_dw = 5; 655 656 r = amdgpu_job_submit_direct(job, ring, &f); 657 if (r) { 658 amdgpu_job_free(job); 659 goto err1; 660 } 661 662 r = dma_fence_wait_timeout(f, false, timeout); 663 if (r == 0) { 664 r = -ETIMEDOUT; 665 goto err1; 666 } else if (r < 0) { 667 goto err1; 668 } 669 tmp = le32_to_cpu(adev->wb.wb[index]); 670 if (tmp == 0xDEADBEEF) 671 r = 0; 672 else 673 r = -EINVAL; 674 675 err1: 676 dma_fence_put(f); 677 err0: 678 amdgpu_wb_free(adev, index); 679 return r; 680 } 681 682 /** 683 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART 684 * 685 * @ib: indirect buffer to fill with commands 686 * @pe: addr of the page entry 687 * @src: src addr to copy from 688 * @count: number of page entries to update 689 * 690 * Update PTEs by copying them from the GART using sDMA (CIK). 691 */ 692 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, 693 uint64_t pe, uint64_t src, 694 unsigned count) 695 { 696 unsigned bytes = count * 8; 697 698 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 699 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 700 ib->ptr[ib->length_dw++] = bytes; 701 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 702 ib->ptr[ib->length_dw++] = lower_32_bits(src); 703 ib->ptr[ib->length_dw++] = upper_32_bits(src); 704 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 705 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 706 } 707 708 /** 709 * cik_sdma_vm_write_pte - update PTEs by writing them manually 710 * 711 * @ib: indirect buffer to fill with commands 712 * @pe: addr of the page entry 713 * @value: dst addr to write into pe 714 * @count: number of page entries to update 715 * @incr: increase next addr by incr bytes 716 * 717 * Update PTEs by writing them manually using sDMA (CIK). 718 */ 719 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 720 uint64_t value, unsigned count, 721 uint32_t incr) 722 { 723 unsigned ndw = count * 2; 724 725 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 726 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 727 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 728 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 729 ib->ptr[ib->length_dw++] = ndw; 730 for (; ndw > 0; ndw -= 2) { 731 ib->ptr[ib->length_dw++] = lower_32_bits(value); 732 ib->ptr[ib->length_dw++] = upper_32_bits(value); 733 value += incr; 734 } 735 } 736 737 /** 738 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA 739 * 740 * @ib: indirect buffer to fill with commands 741 * @pe: addr of the page entry 742 * @addr: dst addr to write into pe 743 * @count: number of page entries to update 744 * @incr: increase next addr by incr bytes 745 * @flags: access flags 746 * 747 * Update the page tables using sDMA (CIK). 748 */ 749 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 750 uint64_t addr, unsigned count, 751 uint32_t incr, uint64_t flags) 752 { 753 /* for physically contiguous pages (vram) */ 754 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 755 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 756 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 757 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 758 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 759 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 760 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 761 ib->ptr[ib->length_dw++] = incr; /* increment size */ 762 ib->ptr[ib->length_dw++] = 0; 763 ib->ptr[ib->length_dw++] = count; /* number of entries */ 764 } 765 766 /** 767 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw 768 * 769 * @ring: amdgpu_ring structure holding ring information 770 * @ib: indirect buffer to fill with padding 771 * 772 */ 773 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 774 { 775 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 776 u32 pad_count; 777 int i; 778 779 pad_count = (-ib->length_dw) & 7; 780 for (i = 0; i < pad_count; i++) 781 if (sdma && sdma->burst_nop && (i == 0)) 782 ib->ptr[ib->length_dw++] = 783 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | 784 SDMA_NOP_COUNT(pad_count - 1); 785 else 786 ib->ptr[ib->length_dw++] = 787 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 788 } 789 790 /** 791 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 792 * 793 * @ring: amdgpu_ring pointer 794 * 795 * Make sure all previous operations are completed (CIK). 796 */ 797 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 798 { 799 uint32_t seq = ring->fence_drv.sync_seq; 800 uint64_t addr = ring->fence_drv.gpu_addr; 801 802 /* wait for idle */ 803 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 804 SDMA_POLL_REG_MEM_EXTRA_OP(0) | 805 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ 806 SDMA_POLL_REG_MEM_EXTRA_M)); 807 amdgpu_ring_write(ring, addr & 0xfffffffc); 808 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 809 amdgpu_ring_write(ring, seq); /* reference */ 810 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 811 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ 812 } 813 814 /** 815 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA 816 * 817 * @ring: amdgpu_ring pointer 818 * @vmid: vmid number to use 819 * @pd_addr: address 820 * 821 * Update the page table base and flush the VM TLB 822 * using sDMA (CIK). 823 */ 824 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 825 unsigned vmid, uint64_t pd_addr) 826 { 827 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 828 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 829 830 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 831 832 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 833 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 834 amdgpu_ring_write(ring, 0); 835 amdgpu_ring_write(ring, 0); /* reference */ 836 amdgpu_ring_write(ring, 0); /* mask */ 837 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 838 } 839 840 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring, 841 uint32_t reg, uint32_t val) 842 { 843 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 844 amdgpu_ring_write(ring, reg); 845 amdgpu_ring_write(ring, val); 846 } 847 848 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 849 bool enable) 850 { 851 u32 orig, data; 852 853 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 854 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 855 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 856 } else { 857 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); 858 data |= 0xff000000; 859 if (data != orig) 860 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); 861 862 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); 863 data |= 0xff000000; 864 if (data != orig) 865 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); 866 } 867 } 868 869 static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 870 bool enable) 871 { 872 u32 orig, data; 873 874 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 875 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 876 data |= 0x100; 877 if (orig != data) 878 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 879 880 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 881 data |= 0x100; 882 if (orig != data) 883 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 884 } else { 885 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 886 data &= ~0x100; 887 if (orig != data) 888 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 889 890 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 891 data &= ~0x100; 892 if (orig != data) 893 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 894 } 895 } 896 897 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 898 .copy_pte_num_dw = 7, 899 .copy_pte = cik_sdma_vm_copy_pte, 900 901 .write_pte = cik_sdma_vm_write_pte, 902 .set_pte_pde = cik_sdma_vm_set_pte_pde, 903 }; 904 905 static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) 906 { 907 struct amdgpu_device *adev = ip_block->adev; 908 int r; 909 910 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 911 912 r = cik_sdma_init_microcode(adev); 913 if (r) 914 return r; 915 916 cik_sdma_set_ring_funcs(adev); 917 cik_sdma_set_irq_funcs(adev); 918 amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); 919 920 return 0; 921 } 922 923 static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block) 924 { 925 struct amdgpu_ring *ring; 926 struct amdgpu_device *adev = ip_block->adev; 927 int r, i; 928 929 /* SDMA trap event */ 930 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, 931 &adev->sdma.trap_irq); 932 if (r) 933 return r; 934 935 /* SDMA Privileged inst */ 936 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 937 &adev->sdma.illegal_inst_irq); 938 if (r) 939 return r; 940 941 /* SDMA Privileged inst */ 942 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247, 943 &adev->sdma.illegal_inst_irq); 944 if (r) 945 return r; 946 947 for (i = 0; i < adev->sdma.num_instances; i++) { 948 ring = &adev->sdma.instance[i].ring; 949 ring->ring_obj = NULL; 950 sprintf(ring->name, "sdma%d", i); 951 r = amdgpu_ring_init(adev, ring, 1024, 952 &adev->sdma.trap_irq, 953 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 954 AMDGPU_SDMA_IRQ_INSTANCE1, 955 AMDGPU_RING_PRIO_DEFAULT, NULL); 956 if (r) 957 return r; 958 } 959 960 return r; 961 } 962 963 static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block) 964 { 965 struct amdgpu_device *adev = ip_block->adev; 966 int i; 967 968 for (i = 0; i < adev->sdma.num_instances; i++) 969 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 970 971 cik_sdma_free_microcode(adev); 972 return 0; 973 } 974 975 static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block) 976 { 977 struct amdgpu_device *adev = ip_block->adev; 978 int r; 979 980 r = cik_sdma_start(adev); 981 if (r) 982 return r; 983 984 cik_sdma_set_buffer_funcs(adev); 985 986 return 0; 987 } 988 989 static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block) 990 { 991 struct amdgpu_device *adev = ip_block->adev; 992 993 cik_ctx_switch_enable(adev, false); 994 cik_sdma_enable(adev, false); 995 996 return 0; 997 } 998 999 static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block) 1000 { 1001 return cik_sdma_hw_fini(ip_block); 1002 } 1003 1004 static int cik_sdma_resume(struct amdgpu_ip_block *ip_block) 1005 { 1006 cik_sdma_soft_reset(ip_block); 1007 1008 return cik_sdma_hw_init(ip_block); 1009 } 1010 1011 static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block) 1012 { 1013 struct amdgpu_device *adev = ip_block->adev; 1014 u32 tmp = RREG32(mmSRBM_STATUS2); 1015 1016 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1017 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1018 return false; 1019 1020 return true; 1021 } 1022 1023 static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block) 1024 { 1025 unsigned i; 1026 struct amdgpu_device *adev = ip_block->adev; 1027 1028 for (i = 0; i < adev->usec_timeout; i++) { 1029 if (cik_sdma_is_idle(ip_block)) 1030 return 0; 1031 udelay(1); 1032 } 1033 return -ETIMEDOUT; 1034 } 1035 1036 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block) 1037 { 1038 u32 srbm_soft_reset = 0; 1039 struct amdgpu_device *adev = ip_block->adev; 1040 u32 tmp; 1041 1042 /* sdma0 */ 1043 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1044 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1045 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1046 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1047 1048 /* sdma1 */ 1049 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1050 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1051 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1052 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1053 1054 if (srbm_soft_reset) { 1055 tmp = RREG32(mmSRBM_SOFT_RESET); 1056 tmp |= srbm_soft_reset; 1057 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1058 WREG32(mmSRBM_SOFT_RESET, tmp); 1059 tmp = RREG32(mmSRBM_SOFT_RESET); 1060 1061 udelay(50); 1062 1063 tmp &= ~srbm_soft_reset; 1064 WREG32(mmSRBM_SOFT_RESET, tmp); 1065 tmp = RREG32(mmSRBM_SOFT_RESET); 1066 1067 /* Wait a little for things to settle down */ 1068 udelay(50); 1069 } 1070 1071 return 0; 1072 } 1073 1074 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, 1075 struct amdgpu_irq_src *src, 1076 unsigned type, 1077 enum amdgpu_interrupt_state state) 1078 { 1079 u32 sdma_cntl; 1080 1081 switch (type) { 1082 case AMDGPU_SDMA_IRQ_INSTANCE0: 1083 switch (state) { 1084 case AMDGPU_IRQ_STATE_DISABLE: 1085 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1086 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1087 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1088 break; 1089 case AMDGPU_IRQ_STATE_ENABLE: 1090 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1091 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1092 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1093 break; 1094 default: 1095 break; 1096 } 1097 break; 1098 case AMDGPU_SDMA_IRQ_INSTANCE1: 1099 switch (state) { 1100 case AMDGPU_IRQ_STATE_DISABLE: 1101 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1102 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1103 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1104 break; 1105 case AMDGPU_IRQ_STATE_ENABLE: 1106 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1107 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1108 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1109 break; 1110 default: 1111 break; 1112 } 1113 break; 1114 default: 1115 break; 1116 } 1117 return 0; 1118 } 1119 1120 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, 1121 struct amdgpu_irq_src *source, 1122 struct amdgpu_iv_entry *entry) 1123 { 1124 u8 instance_id, queue_id; 1125 1126 instance_id = (entry->ring_id & 0x3) >> 0; 1127 queue_id = (entry->ring_id & 0xc) >> 2; 1128 DRM_DEBUG("IH: SDMA trap\n"); 1129 switch (instance_id) { 1130 case 0: 1131 switch (queue_id) { 1132 case 0: 1133 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1134 break; 1135 case 1: 1136 /* XXX compute */ 1137 break; 1138 case 2: 1139 /* XXX compute */ 1140 break; 1141 } 1142 break; 1143 case 1: 1144 switch (queue_id) { 1145 case 0: 1146 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1147 break; 1148 case 1: 1149 /* XXX compute */ 1150 break; 1151 case 2: 1152 /* XXX compute */ 1153 break; 1154 } 1155 break; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, 1162 struct amdgpu_irq_src *source, 1163 struct amdgpu_iv_entry *entry) 1164 { 1165 u8 instance_id; 1166 1167 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1168 instance_id = (entry->ring_id & 0x3) >> 0; 1169 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1170 return 0; 1171 } 1172 1173 static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1174 enum amd_clockgating_state state) 1175 { 1176 bool gate = false; 1177 struct amdgpu_device *adev = ip_block->adev; 1178 1179 if (state == AMD_CG_STATE_GATE) 1180 gate = true; 1181 1182 cik_enable_sdma_mgcg(adev, gate); 1183 cik_enable_sdma_mgls(adev, gate); 1184 1185 return 0; 1186 } 1187 1188 static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block, 1189 enum amd_powergating_state state) 1190 { 1191 return 0; 1192 } 1193 1194 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1195 .name = "cik_sdma", 1196 .early_init = cik_sdma_early_init, 1197 .sw_init = cik_sdma_sw_init, 1198 .sw_fini = cik_sdma_sw_fini, 1199 .hw_init = cik_sdma_hw_init, 1200 .hw_fini = cik_sdma_hw_fini, 1201 .suspend = cik_sdma_suspend, 1202 .resume = cik_sdma_resume, 1203 .wait_for_idle = cik_sdma_wait_for_idle, 1204 .soft_reset = cik_sdma_soft_reset, 1205 .set_clockgating_state = cik_sdma_set_clockgating_state, 1206 .set_powergating_state = cik_sdma_set_powergating_state, 1207 }; 1208 1209 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1210 .type = AMDGPU_RING_TYPE_SDMA, 1211 .align_mask = 0xf, 1212 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 1213 .support_64bit_ptrs = false, 1214 .get_rptr = cik_sdma_ring_get_rptr, 1215 .get_wptr = cik_sdma_ring_get_wptr, 1216 .set_wptr = cik_sdma_ring_set_wptr, 1217 .emit_frame_size = 1218 6 + /* cik_sdma_ring_emit_hdp_flush */ 1219 3 + /* hdp invalidate */ 1220 6 + /* cik_sdma_ring_emit_pipeline_sync */ 1221 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ 1222 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ 1223 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ 1224 .emit_ib = cik_sdma_ring_emit_ib, 1225 .emit_fence = cik_sdma_ring_emit_fence, 1226 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, 1227 .emit_vm_flush = cik_sdma_ring_emit_vm_flush, 1228 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1229 .test_ring = cik_sdma_ring_test_ring, 1230 .test_ib = cik_sdma_ring_test_ib, 1231 .insert_nop = cik_sdma_ring_insert_nop, 1232 .pad_ib = cik_sdma_ring_pad_ib, 1233 .emit_wreg = cik_sdma_ring_emit_wreg, 1234 }; 1235 1236 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) 1237 { 1238 int i; 1239 1240 for (i = 0; i < adev->sdma.num_instances; i++) { 1241 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; 1242 adev->sdma.instance[i].ring.me = i; 1243 } 1244 } 1245 1246 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { 1247 .set = cik_sdma_set_trap_irq_state, 1248 .process = cik_sdma_process_trap_irq, 1249 }; 1250 1251 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { 1252 .process = cik_sdma_process_illegal_inst_irq, 1253 }; 1254 1255 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) 1256 { 1257 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1258 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; 1259 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; 1260 } 1261 1262 /** 1263 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine 1264 * 1265 * @ib: indirect buffer to copy to 1266 * @src_offset: src GPU address 1267 * @dst_offset: dst GPU address 1268 * @byte_count: number of bytes to xfer 1269 * @copy_flags: unused 1270 * 1271 * Copy GPU buffers using the DMA engine (CIK). 1272 * Used by the amdgpu ttm implementation to move pages if 1273 * registered as the asic copy callback. 1274 */ 1275 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, 1276 uint64_t src_offset, 1277 uint64_t dst_offset, 1278 uint32_t byte_count, 1279 uint32_t copy_flags) 1280 { 1281 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1282 ib->ptr[ib->length_dw++] = byte_count; 1283 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1284 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1285 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1286 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1287 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1288 } 1289 1290 /** 1291 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine 1292 * 1293 * @ib: indirect buffer to fill 1294 * @src_data: value to write to buffer 1295 * @dst_offset: dst GPU address 1296 * @byte_count: number of bytes to xfer 1297 * 1298 * Fill GPU buffers using the DMA engine (CIK). 1299 */ 1300 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, 1301 uint32_t src_data, 1302 uint64_t dst_offset, 1303 uint32_t byte_count) 1304 { 1305 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); 1306 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1307 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1308 ib->ptr[ib->length_dw++] = src_data; 1309 ib->ptr[ib->length_dw++] = byte_count; 1310 } 1311 1312 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { 1313 .copy_max_bytes = 0x1fffff, 1314 .copy_num_dw = 7, 1315 .emit_copy_buffer = cik_sdma_emit_copy_buffer, 1316 1317 .fill_max_bytes = 0x1fffff, 1318 .fill_num_dw = 5, 1319 .emit_fill_buffer = cik_sdma_emit_fill_buffer, 1320 }; 1321 1322 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) 1323 { 1324 amdgpu_sdma_set_buffer_funcs_scheds(adev, &cik_sdma_buffer_funcs); 1325 } 1326 1327 const struct amdgpu_ip_block_version cik_sdma_ip_block = 1328 { 1329 .type = AMD_IP_BLOCK_TYPE_SDMA, 1330 .major = 2, 1331 .minor = 0, 1332 .rev = 0, 1333 .funcs = &cik_sdma_ip_funcs, 1334 }; 1335