1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 #include "drmP.h" 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "cikd.h" 34 #include "atom.h" 35 36 #include "cik.h" 37 #include "gmc_v7_0.h" 38 #include "cik_ih.h" 39 #include "dce_v8_0.h" 40 #include "gfx_v7_0.h" 41 #include "cik_sdma.h" 42 #include "uvd_v4_2.h" 43 #include "vce_v2_0.h" 44 #include "cik_dpm.h" 45 46 #include "uvd/uvd_4_2_d.h" 47 48 #include "smu/smu_7_0_1_d.h" 49 #include "smu/smu_7_0_1_sh_mask.h" 50 51 #include "dce/dce_8_0_d.h" 52 #include "dce/dce_8_0_sh_mask.h" 53 54 #include "bif/bif_4_1_d.h" 55 #include "bif/bif_4_1_sh_mask.h" 56 57 #include "gca/gfx_7_2_d.h" 58 #include "gca/gfx_7_2_enum.h" 59 #include "gca/gfx_7_2_sh_mask.h" 60 61 #include "gmc/gmc_7_1_d.h" 62 #include "gmc/gmc_7_1_sh_mask.h" 63 64 #include "oss/oss_2_0_d.h" 65 #include "oss/oss_2_0_sh_mask.h" 66 67 /* 68 * Indirect registers accessor 69 */ 70 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71 { 72 unsigned long flags; 73 u32 r; 74 75 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 76 WREG32(mmPCIE_INDEX, reg); 77 (void)RREG32(mmPCIE_INDEX); 78 r = RREG32(mmPCIE_DATA); 79 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 80 return r; 81 } 82 83 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 84 { 85 unsigned long flags; 86 87 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 88 WREG32(mmPCIE_INDEX, reg); 89 (void)RREG32(mmPCIE_INDEX); 90 WREG32(mmPCIE_DATA, v); 91 (void)RREG32(mmPCIE_DATA); 92 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 93 } 94 95 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long flags; 98 u32 r; 99 100 spin_lock_irqsave(&adev->smc_idx_lock, flags); 101 WREG32(mmSMC_IND_INDEX_0, (reg)); 102 r = RREG32(mmSMC_IND_DATA_0); 103 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 104 return r; 105 } 106 107 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 108 { 109 unsigned long flags; 110 111 spin_lock_irqsave(&adev->smc_idx_lock, flags); 112 WREG32(mmSMC_IND_INDEX_0, (reg)); 113 WREG32(mmSMC_IND_DATA_0, (v)); 114 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 115 } 116 117 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 118 { 119 unsigned long flags; 120 u32 r; 121 122 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 123 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 124 r = RREG32(mmUVD_CTX_DATA); 125 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 126 return r; 127 } 128 129 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 130 { 131 unsigned long flags; 132 133 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 134 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 135 WREG32(mmUVD_CTX_DATA, (v)); 136 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 137 } 138 139 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) 140 { 141 unsigned long flags; 142 u32 r; 143 144 spin_lock_irqsave(&adev->didt_idx_lock, flags); 145 WREG32(mmDIDT_IND_INDEX, (reg)); 146 r = RREG32(mmDIDT_IND_DATA); 147 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 148 return r; 149 } 150 151 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 152 { 153 unsigned long flags; 154 155 spin_lock_irqsave(&adev->didt_idx_lock, flags); 156 WREG32(mmDIDT_IND_INDEX, (reg)); 157 WREG32(mmDIDT_IND_DATA, (v)); 158 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 159 } 160 161 static const u32 bonaire_golden_spm_registers[] = 162 { 163 0xc200, 0xe0ffffff, 0xe0000000 164 }; 165 166 static const u32 bonaire_golden_common_registers[] = 167 { 168 0x31dc, 0xffffffff, 0x00000800, 169 0x31dd, 0xffffffff, 0x00000800, 170 0x31e6, 0xffffffff, 0x00007fbf, 171 0x31e7, 0xffffffff, 0x00007faf 172 }; 173 174 static const u32 bonaire_golden_registers[] = 175 { 176 0xcd5, 0x00000333, 0x00000333, 177 0xcd4, 0x000c0fc0, 0x00040200, 178 0x2684, 0x00010000, 0x00058208, 179 0xf000, 0xffff1fff, 0x00140000, 180 0xf080, 0xfdfc0fff, 0x00000100, 181 0xf08d, 0x40000000, 0x40000200, 182 0x260c, 0xffffffff, 0x00000000, 183 0x260d, 0xf00fffff, 0x00000400, 184 0x260e, 0x0002021c, 0x00020200, 185 0x31e, 0x00000080, 0x00000000, 186 0x16ec, 0x000000f0, 0x00000070, 187 0x16f0, 0xf0311fff, 0x80300000, 188 0x263e, 0x73773777, 0x12010001, 189 0xd43, 0x00810000, 0x408af000, 190 0x1c0c, 0x31000111, 0x00000011, 191 0xbd2, 0x73773777, 0x12010001, 192 0x883, 0x00007fb6, 0x0021a1b1, 193 0x884, 0x00007fb6, 0x002021b1, 194 0x860, 0x00007fb6, 0x00002191, 195 0x886, 0x00007fb6, 0x002121b1, 196 0x887, 0x00007fb6, 0x002021b1, 197 0x877, 0x00007fb6, 0x00002191, 198 0x878, 0x00007fb6, 0x00002191, 199 0xd8a, 0x0000003f, 0x0000000a, 200 0xd8b, 0x0000003f, 0x0000000a, 201 0xab9, 0x00073ffe, 0x000022a2, 202 0x903, 0x000007ff, 0x00000000, 203 0x2285, 0xf000003f, 0x00000007, 204 0x22fc, 0x00002001, 0x00000001, 205 0x22c9, 0xffffffff, 0x00ffffff, 206 0xc281, 0x0000ff0f, 0x00000000, 207 0xa293, 0x07ffffff, 0x06000000, 208 0x136, 0x00000fff, 0x00000100, 209 0xf9e, 0x00000001, 0x00000002, 210 0x2440, 0x03000000, 0x0362c688, 211 0x2300, 0x000000ff, 0x00000001, 212 0x390, 0x00001fff, 0x00001fff, 213 0x2418, 0x0000007f, 0x00000020, 214 0x2542, 0x00010000, 0x00010000, 215 0x2b05, 0x000003ff, 0x000000f3, 216 0x2b03, 0xffffffff, 0x00001032 217 }; 218 219 static const u32 bonaire_mgcg_cgcg_init[] = 220 { 221 0x3108, 0xffffffff, 0xfffffffc, 222 0xc200, 0xffffffff, 0xe0000000, 223 0xf0a8, 0xffffffff, 0x00000100, 224 0xf082, 0xffffffff, 0x00000100, 225 0xf0b0, 0xffffffff, 0xc0000100, 226 0xf0b2, 0xffffffff, 0xc0000100, 227 0xf0b1, 0xffffffff, 0xc0000100, 228 0x1579, 0xffffffff, 0x00600100, 229 0xf0a0, 0xffffffff, 0x00000100, 230 0xf085, 0xffffffff, 0x06000100, 231 0xf088, 0xffffffff, 0x00000100, 232 0xf086, 0xffffffff, 0x06000100, 233 0xf081, 0xffffffff, 0x00000100, 234 0xf0b8, 0xffffffff, 0x00000100, 235 0xf089, 0xffffffff, 0x00000100, 236 0xf080, 0xffffffff, 0x00000100, 237 0xf08c, 0xffffffff, 0x00000100, 238 0xf08d, 0xffffffff, 0x00000100, 239 0xf094, 0xffffffff, 0x00000100, 240 0xf095, 0xffffffff, 0x00000100, 241 0xf096, 0xffffffff, 0x00000100, 242 0xf097, 0xffffffff, 0x00000100, 243 0xf098, 0xffffffff, 0x00000100, 244 0xf09f, 0xffffffff, 0x00000100, 245 0xf09e, 0xffffffff, 0x00000100, 246 0xf084, 0xffffffff, 0x06000100, 247 0xf0a4, 0xffffffff, 0x00000100, 248 0xf09d, 0xffffffff, 0x00000100, 249 0xf0ad, 0xffffffff, 0x00000100, 250 0xf0ac, 0xffffffff, 0x00000100, 251 0xf09c, 0xffffffff, 0x00000100, 252 0xc200, 0xffffffff, 0xe0000000, 253 0xf008, 0xffffffff, 0x00010000, 254 0xf009, 0xffffffff, 0x00030002, 255 0xf00a, 0xffffffff, 0x00040007, 256 0xf00b, 0xffffffff, 0x00060005, 257 0xf00c, 0xffffffff, 0x00090008, 258 0xf00d, 0xffffffff, 0x00010000, 259 0xf00e, 0xffffffff, 0x00030002, 260 0xf00f, 0xffffffff, 0x00040007, 261 0xf010, 0xffffffff, 0x00060005, 262 0xf011, 0xffffffff, 0x00090008, 263 0xf012, 0xffffffff, 0x00010000, 264 0xf013, 0xffffffff, 0x00030002, 265 0xf014, 0xffffffff, 0x00040007, 266 0xf015, 0xffffffff, 0x00060005, 267 0xf016, 0xffffffff, 0x00090008, 268 0xf017, 0xffffffff, 0x00010000, 269 0xf018, 0xffffffff, 0x00030002, 270 0xf019, 0xffffffff, 0x00040007, 271 0xf01a, 0xffffffff, 0x00060005, 272 0xf01b, 0xffffffff, 0x00090008, 273 0xf01c, 0xffffffff, 0x00010000, 274 0xf01d, 0xffffffff, 0x00030002, 275 0xf01e, 0xffffffff, 0x00040007, 276 0xf01f, 0xffffffff, 0x00060005, 277 0xf020, 0xffffffff, 0x00090008, 278 0xf021, 0xffffffff, 0x00010000, 279 0xf022, 0xffffffff, 0x00030002, 280 0xf023, 0xffffffff, 0x00040007, 281 0xf024, 0xffffffff, 0x00060005, 282 0xf025, 0xffffffff, 0x00090008, 283 0xf026, 0xffffffff, 0x00010000, 284 0xf027, 0xffffffff, 0x00030002, 285 0xf028, 0xffffffff, 0x00040007, 286 0xf029, 0xffffffff, 0x00060005, 287 0xf02a, 0xffffffff, 0x00090008, 288 0xf000, 0xffffffff, 0x96e00200, 289 0x21c2, 0xffffffff, 0x00900100, 290 0x3109, 0xffffffff, 0x0020003f, 291 0xe, 0xffffffff, 0x0140001c, 292 0xf, 0x000f0000, 0x000f0000, 293 0x88, 0xffffffff, 0xc060000c, 294 0x89, 0xc0000fff, 0x00000100, 295 0x3e4, 0xffffffff, 0x00000100, 296 0x3e6, 0x00000101, 0x00000000, 297 0x82a, 0xffffffff, 0x00000104, 298 0x1579, 0xff000fff, 0x00000100, 299 0xc33, 0xc0000fff, 0x00000104, 300 0x3079, 0x00000001, 0x00000001, 301 0x3403, 0xff000ff0, 0x00000100, 302 0x3603, 0xff000ff0, 0x00000100 303 }; 304 305 static const u32 spectre_golden_spm_registers[] = 306 { 307 0xc200, 0xe0ffffff, 0xe0000000 308 }; 309 310 static const u32 spectre_golden_common_registers[] = 311 { 312 0x31dc, 0xffffffff, 0x00000800, 313 0x31dd, 0xffffffff, 0x00000800, 314 0x31e6, 0xffffffff, 0x00007fbf, 315 0x31e7, 0xffffffff, 0x00007faf 316 }; 317 318 static const u32 spectre_golden_registers[] = 319 { 320 0xf000, 0xffff1fff, 0x96940200, 321 0xf003, 0xffff0001, 0xff000000, 322 0xf080, 0xfffc0fff, 0x00000100, 323 0x1bb6, 0x00010101, 0x00010000, 324 0x260d, 0xf00fffff, 0x00000400, 325 0x260e, 0xfffffffc, 0x00020200, 326 0x16ec, 0x000000f0, 0x00000070, 327 0x16f0, 0xf0311fff, 0x80300000, 328 0x263e, 0x73773777, 0x12010001, 329 0x26df, 0x00ff0000, 0x00fc0000, 330 0xbd2, 0x73773777, 0x12010001, 331 0x2285, 0xf000003f, 0x00000007, 332 0x22c9, 0xffffffff, 0x00ffffff, 333 0xa0d4, 0x3f3f3fff, 0x00000082, 334 0xa0d5, 0x0000003f, 0x00000000, 335 0xf9e, 0x00000001, 0x00000002, 336 0x244f, 0xffff03df, 0x00000004, 337 0x31da, 0x00000008, 0x00000008, 338 0x2300, 0x000008ff, 0x00000800, 339 0x2542, 0x00010000, 0x00010000, 340 0x2b03, 0xffffffff, 0x54763210, 341 0x853e, 0x01ff01ff, 0x00000002, 342 0x8526, 0x007ff800, 0x00200000, 343 0x8057, 0xffffffff, 0x00000f40, 344 0xc24d, 0xffffffff, 0x00000001 345 }; 346 347 static const u32 spectre_mgcg_cgcg_init[] = 348 { 349 0x3108, 0xffffffff, 0xfffffffc, 350 0xc200, 0xffffffff, 0xe0000000, 351 0xf0a8, 0xffffffff, 0x00000100, 352 0xf082, 0xffffffff, 0x00000100, 353 0xf0b0, 0xffffffff, 0x00000100, 354 0xf0b2, 0xffffffff, 0x00000100, 355 0xf0b1, 0xffffffff, 0x00000100, 356 0x1579, 0xffffffff, 0x00600100, 357 0xf0a0, 0xffffffff, 0x00000100, 358 0xf085, 0xffffffff, 0x06000100, 359 0xf088, 0xffffffff, 0x00000100, 360 0xf086, 0xffffffff, 0x06000100, 361 0xf081, 0xffffffff, 0x00000100, 362 0xf0b8, 0xffffffff, 0x00000100, 363 0xf089, 0xffffffff, 0x00000100, 364 0xf080, 0xffffffff, 0x00000100, 365 0xf08c, 0xffffffff, 0x00000100, 366 0xf08d, 0xffffffff, 0x00000100, 367 0xf094, 0xffffffff, 0x00000100, 368 0xf095, 0xffffffff, 0x00000100, 369 0xf096, 0xffffffff, 0x00000100, 370 0xf097, 0xffffffff, 0x00000100, 371 0xf098, 0xffffffff, 0x00000100, 372 0xf09f, 0xffffffff, 0x00000100, 373 0xf09e, 0xffffffff, 0x00000100, 374 0xf084, 0xffffffff, 0x06000100, 375 0xf0a4, 0xffffffff, 0x00000100, 376 0xf09d, 0xffffffff, 0x00000100, 377 0xf0ad, 0xffffffff, 0x00000100, 378 0xf0ac, 0xffffffff, 0x00000100, 379 0xf09c, 0xffffffff, 0x00000100, 380 0xc200, 0xffffffff, 0xe0000000, 381 0xf008, 0xffffffff, 0x00010000, 382 0xf009, 0xffffffff, 0x00030002, 383 0xf00a, 0xffffffff, 0x00040007, 384 0xf00b, 0xffffffff, 0x00060005, 385 0xf00c, 0xffffffff, 0x00090008, 386 0xf00d, 0xffffffff, 0x00010000, 387 0xf00e, 0xffffffff, 0x00030002, 388 0xf00f, 0xffffffff, 0x00040007, 389 0xf010, 0xffffffff, 0x00060005, 390 0xf011, 0xffffffff, 0x00090008, 391 0xf012, 0xffffffff, 0x00010000, 392 0xf013, 0xffffffff, 0x00030002, 393 0xf014, 0xffffffff, 0x00040007, 394 0xf015, 0xffffffff, 0x00060005, 395 0xf016, 0xffffffff, 0x00090008, 396 0xf017, 0xffffffff, 0x00010000, 397 0xf018, 0xffffffff, 0x00030002, 398 0xf019, 0xffffffff, 0x00040007, 399 0xf01a, 0xffffffff, 0x00060005, 400 0xf01b, 0xffffffff, 0x00090008, 401 0xf01c, 0xffffffff, 0x00010000, 402 0xf01d, 0xffffffff, 0x00030002, 403 0xf01e, 0xffffffff, 0x00040007, 404 0xf01f, 0xffffffff, 0x00060005, 405 0xf020, 0xffffffff, 0x00090008, 406 0xf021, 0xffffffff, 0x00010000, 407 0xf022, 0xffffffff, 0x00030002, 408 0xf023, 0xffffffff, 0x00040007, 409 0xf024, 0xffffffff, 0x00060005, 410 0xf025, 0xffffffff, 0x00090008, 411 0xf026, 0xffffffff, 0x00010000, 412 0xf027, 0xffffffff, 0x00030002, 413 0xf028, 0xffffffff, 0x00040007, 414 0xf029, 0xffffffff, 0x00060005, 415 0xf02a, 0xffffffff, 0x00090008, 416 0xf02b, 0xffffffff, 0x00010000, 417 0xf02c, 0xffffffff, 0x00030002, 418 0xf02d, 0xffffffff, 0x00040007, 419 0xf02e, 0xffffffff, 0x00060005, 420 0xf02f, 0xffffffff, 0x00090008, 421 0xf000, 0xffffffff, 0x96e00200, 422 0x21c2, 0xffffffff, 0x00900100, 423 0x3109, 0xffffffff, 0x0020003f, 424 0xe, 0xffffffff, 0x0140001c, 425 0xf, 0x000f0000, 0x000f0000, 426 0x88, 0xffffffff, 0xc060000c, 427 0x89, 0xc0000fff, 0x00000100, 428 0x3e4, 0xffffffff, 0x00000100, 429 0x3e6, 0x00000101, 0x00000000, 430 0x82a, 0xffffffff, 0x00000104, 431 0x1579, 0xff000fff, 0x00000100, 432 0xc33, 0xc0000fff, 0x00000104, 433 0x3079, 0x00000001, 0x00000001, 434 0x3403, 0xff000ff0, 0x00000100, 435 0x3603, 0xff000ff0, 0x00000100 436 }; 437 438 static const u32 kalindi_golden_spm_registers[] = 439 { 440 0xc200, 0xe0ffffff, 0xe0000000 441 }; 442 443 static const u32 kalindi_golden_common_registers[] = 444 { 445 0x31dc, 0xffffffff, 0x00000800, 446 0x31dd, 0xffffffff, 0x00000800, 447 0x31e6, 0xffffffff, 0x00007fbf, 448 0x31e7, 0xffffffff, 0x00007faf 449 }; 450 451 static const u32 kalindi_golden_registers[] = 452 { 453 0xf000, 0xffffdfff, 0x6e944040, 454 0x1579, 0xff607fff, 0xfc000100, 455 0xf088, 0xff000fff, 0x00000100, 456 0xf089, 0xff000fff, 0x00000100, 457 0xf080, 0xfffc0fff, 0x00000100, 458 0x1bb6, 0x00010101, 0x00010000, 459 0x260c, 0xffffffff, 0x00000000, 460 0x260d, 0xf00fffff, 0x00000400, 461 0x16ec, 0x000000f0, 0x00000070, 462 0x16f0, 0xf0311fff, 0x80300000, 463 0x263e, 0x73773777, 0x12010001, 464 0x263f, 0xffffffff, 0x00000010, 465 0x26df, 0x00ff0000, 0x00fc0000, 466 0x200c, 0x00001f0f, 0x0000100a, 467 0xbd2, 0x73773777, 0x12010001, 468 0x902, 0x000fffff, 0x000c007f, 469 0x2285, 0xf000003f, 0x00000007, 470 0x22c9, 0x3fff3fff, 0x00ffcfff, 471 0xc281, 0x0000ff0f, 0x00000000, 472 0xa293, 0x07ffffff, 0x06000000, 473 0x136, 0x00000fff, 0x00000100, 474 0xf9e, 0x00000001, 0x00000002, 475 0x31da, 0x00000008, 0x00000008, 476 0x2300, 0x000000ff, 0x00000003, 477 0x853e, 0x01ff01ff, 0x00000002, 478 0x8526, 0x007ff800, 0x00200000, 479 0x8057, 0xffffffff, 0x00000f40, 480 0x2231, 0x001f3ae3, 0x00000082, 481 0x2235, 0x0000001f, 0x00000010, 482 0xc24d, 0xffffffff, 0x00000000 483 }; 484 485 static const u32 kalindi_mgcg_cgcg_init[] = 486 { 487 0x3108, 0xffffffff, 0xfffffffc, 488 0xc200, 0xffffffff, 0xe0000000, 489 0xf0a8, 0xffffffff, 0x00000100, 490 0xf082, 0xffffffff, 0x00000100, 491 0xf0b0, 0xffffffff, 0x00000100, 492 0xf0b2, 0xffffffff, 0x00000100, 493 0xf0b1, 0xffffffff, 0x00000100, 494 0x1579, 0xffffffff, 0x00600100, 495 0xf0a0, 0xffffffff, 0x00000100, 496 0xf085, 0xffffffff, 0x06000100, 497 0xf088, 0xffffffff, 0x00000100, 498 0xf086, 0xffffffff, 0x06000100, 499 0xf081, 0xffffffff, 0x00000100, 500 0xf0b8, 0xffffffff, 0x00000100, 501 0xf089, 0xffffffff, 0x00000100, 502 0xf080, 0xffffffff, 0x00000100, 503 0xf08c, 0xffffffff, 0x00000100, 504 0xf08d, 0xffffffff, 0x00000100, 505 0xf094, 0xffffffff, 0x00000100, 506 0xf095, 0xffffffff, 0x00000100, 507 0xf096, 0xffffffff, 0x00000100, 508 0xf097, 0xffffffff, 0x00000100, 509 0xf098, 0xffffffff, 0x00000100, 510 0xf09f, 0xffffffff, 0x00000100, 511 0xf09e, 0xffffffff, 0x00000100, 512 0xf084, 0xffffffff, 0x06000100, 513 0xf0a4, 0xffffffff, 0x00000100, 514 0xf09d, 0xffffffff, 0x00000100, 515 0xf0ad, 0xffffffff, 0x00000100, 516 0xf0ac, 0xffffffff, 0x00000100, 517 0xf09c, 0xffffffff, 0x00000100, 518 0xc200, 0xffffffff, 0xe0000000, 519 0xf008, 0xffffffff, 0x00010000, 520 0xf009, 0xffffffff, 0x00030002, 521 0xf00a, 0xffffffff, 0x00040007, 522 0xf00b, 0xffffffff, 0x00060005, 523 0xf00c, 0xffffffff, 0x00090008, 524 0xf00d, 0xffffffff, 0x00010000, 525 0xf00e, 0xffffffff, 0x00030002, 526 0xf00f, 0xffffffff, 0x00040007, 527 0xf010, 0xffffffff, 0x00060005, 528 0xf011, 0xffffffff, 0x00090008, 529 0xf000, 0xffffffff, 0x96e00200, 530 0x21c2, 0xffffffff, 0x00900100, 531 0x3109, 0xffffffff, 0x0020003f, 532 0xe, 0xffffffff, 0x0140001c, 533 0xf, 0x000f0000, 0x000f0000, 534 0x88, 0xffffffff, 0xc060000c, 535 0x89, 0xc0000fff, 0x00000100, 536 0x82a, 0xffffffff, 0x00000104, 537 0x1579, 0xff000fff, 0x00000100, 538 0xc33, 0xc0000fff, 0x00000104, 539 0x3079, 0x00000001, 0x00000001, 540 0x3403, 0xff000ff0, 0x00000100, 541 0x3603, 0xff000ff0, 0x00000100 542 }; 543 544 static const u32 hawaii_golden_spm_registers[] = 545 { 546 0xc200, 0xe0ffffff, 0xe0000000 547 }; 548 549 static const u32 hawaii_golden_common_registers[] = 550 { 551 0xc200, 0xffffffff, 0xe0000000, 552 0xa0d4, 0xffffffff, 0x3a00161a, 553 0xa0d5, 0xffffffff, 0x0000002e, 554 0x2684, 0xffffffff, 0x00018208, 555 0x263e, 0xffffffff, 0x12011003 556 }; 557 558 static const u32 hawaii_golden_registers[] = 559 { 560 0xcd5, 0x00000333, 0x00000333, 561 0x2684, 0x00010000, 0x00058208, 562 0x260c, 0xffffffff, 0x00000000, 563 0x260d, 0xf00fffff, 0x00000400, 564 0x260e, 0x0002021c, 0x00020200, 565 0x31e, 0x00000080, 0x00000000, 566 0x16ec, 0x000000f0, 0x00000070, 567 0x16f0, 0xf0311fff, 0x80300000, 568 0xd43, 0x00810000, 0x408af000, 569 0x1c0c, 0x31000111, 0x00000011, 570 0xbd2, 0x73773777, 0x12010001, 571 0x848, 0x0000007f, 0x0000001b, 572 0x877, 0x00007fb6, 0x00002191, 573 0xd8a, 0x0000003f, 0x0000000a, 574 0xd8b, 0x0000003f, 0x0000000a, 575 0xab9, 0x00073ffe, 0x000022a2, 576 0x903, 0x000007ff, 0x00000000, 577 0x22fc, 0x00002001, 0x00000001, 578 0x22c9, 0xffffffff, 0x00ffffff, 579 0xc281, 0x0000ff0f, 0x00000000, 580 0xa293, 0x07ffffff, 0x06000000, 581 0xf9e, 0x00000001, 0x00000002, 582 0x31da, 0x00000008, 0x00000008, 583 0x31dc, 0x00000f00, 0x00000800, 584 0x31dd, 0x00000f00, 0x00000800, 585 0x31e6, 0x00ffffff, 0x00ff7fbf, 586 0x31e7, 0x00ffffff, 0x00ff7faf, 587 0x2300, 0x000000ff, 0x00000800, 588 0x390, 0x00001fff, 0x00001fff, 589 0x2418, 0x0000007f, 0x00000020, 590 0x2542, 0x00010000, 0x00010000, 591 0x2b80, 0x00100000, 0x000ff07c, 592 0x2b05, 0x000003ff, 0x0000000f, 593 0x2b04, 0xffffffff, 0x7564fdec, 594 0x2b03, 0xffffffff, 0x3120b9a8, 595 0x2b02, 0x20000000, 0x0f9c0000 596 }; 597 598 static const u32 hawaii_mgcg_cgcg_init[] = 599 { 600 0x3108, 0xffffffff, 0xfffffffd, 601 0xc200, 0xffffffff, 0xe0000000, 602 0xf0a8, 0xffffffff, 0x00000100, 603 0xf082, 0xffffffff, 0x00000100, 604 0xf0b0, 0xffffffff, 0x00000100, 605 0xf0b2, 0xffffffff, 0x00000100, 606 0xf0b1, 0xffffffff, 0x00000100, 607 0x1579, 0xffffffff, 0x00200100, 608 0xf0a0, 0xffffffff, 0x00000100, 609 0xf085, 0xffffffff, 0x06000100, 610 0xf088, 0xffffffff, 0x00000100, 611 0xf086, 0xffffffff, 0x06000100, 612 0xf081, 0xffffffff, 0x00000100, 613 0xf0b8, 0xffffffff, 0x00000100, 614 0xf089, 0xffffffff, 0x00000100, 615 0xf080, 0xffffffff, 0x00000100, 616 0xf08c, 0xffffffff, 0x00000100, 617 0xf08d, 0xffffffff, 0x00000100, 618 0xf094, 0xffffffff, 0x00000100, 619 0xf095, 0xffffffff, 0x00000100, 620 0xf096, 0xffffffff, 0x00000100, 621 0xf097, 0xffffffff, 0x00000100, 622 0xf098, 0xffffffff, 0x00000100, 623 0xf09f, 0xffffffff, 0x00000100, 624 0xf09e, 0xffffffff, 0x00000100, 625 0xf084, 0xffffffff, 0x06000100, 626 0xf0a4, 0xffffffff, 0x00000100, 627 0xf09d, 0xffffffff, 0x00000100, 628 0xf0ad, 0xffffffff, 0x00000100, 629 0xf0ac, 0xffffffff, 0x00000100, 630 0xf09c, 0xffffffff, 0x00000100, 631 0xc200, 0xffffffff, 0xe0000000, 632 0xf008, 0xffffffff, 0x00010000, 633 0xf009, 0xffffffff, 0x00030002, 634 0xf00a, 0xffffffff, 0x00040007, 635 0xf00b, 0xffffffff, 0x00060005, 636 0xf00c, 0xffffffff, 0x00090008, 637 0xf00d, 0xffffffff, 0x00010000, 638 0xf00e, 0xffffffff, 0x00030002, 639 0xf00f, 0xffffffff, 0x00040007, 640 0xf010, 0xffffffff, 0x00060005, 641 0xf011, 0xffffffff, 0x00090008, 642 0xf012, 0xffffffff, 0x00010000, 643 0xf013, 0xffffffff, 0x00030002, 644 0xf014, 0xffffffff, 0x00040007, 645 0xf015, 0xffffffff, 0x00060005, 646 0xf016, 0xffffffff, 0x00090008, 647 0xf017, 0xffffffff, 0x00010000, 648 0xf018, 0xffffffff, 0x00030002, 649 0xf019, 0xffffffff, 0x00040007, 650 0xf01a, 0xffffffff, 0x00060005, 651 0xf01b, 0xffffffff, 0x00090008, 652 0xf01c, 0xffffffff, 0x00010000, 653 0xf01d, 0xffffffff, 0x00030002, 654 0xf01e, 0xffffffff, 0x00040007, 655 0xf01f, 0xffffffff, 0x00060005, 656 0xf020, 0xffffffff, 0x00090008, 657 0xf021, 0xffffffff, 0x00010000, 658 0xf022, 0xffffffff, 0x00030002, 659 0xf023, 0xffffffff, 0x00040007, 660 0xf024, 0xffffffff, 0x00060005, 661 0xf025, 0xffffffff, 0x00090008, 662 0xf026, 0xffffffff, 0x00010000, 663 0xf027, 0xffffffff, 0x00030002, 664 0xf028, 0xffffffff, 0x00040007, 665 0xf029, 0xffffffff, 0x00060005, 666 0xf02a, 0xffffffff, 0x00090008, 667 0xf02b, 0xffffffff, 0x00010000, 668 0xf02c, 0xffffffff, 0x00030002, 669 0xf02d, 0xffffffff, 0x00040007, 670 0xf02e, 0xffffffff, 0x00060005, 671 0xf02f, 0xffffffff, 0x00090008, 672 0xf030, 0xffffffff, 0x00010000, 673 0xf031, 0xffffffff, 0x00030002, 674 0xf032, 0xffffffff, 0x00040007, 675 0xf033, 0xffffffff, 0x00060005, 676 0xf034, 0xffffffff, 0x00090008, 677 0xf035, 0xffffffff, 0x00010000, 678 0xf036, 0xffffffff, 0x00030002, 679 0xf037, 0xffffffff, 0x00040007, 680 0xf038, 0xffffffff, 0x00060005, 681 0xf039, 0xffffffff, 0x00090008, 682 0xf03a, 0xffffffff, 0x00010000, 683 0xf03b, 0xffffffff, 0x00030002, 684 0xf03c, 0xffffffff, 0x00040007, 685 0xf03d, 0xffffffff, 0x00060005, 686 0xf03e, 0xffffffff, 0x00090008, 687 0x30c6, 0xffffffff, 0x00020200, 688 0xcd4, 0xffffffff, 0x00000200, 689 0x570, 0xffffffff, 0x00000400, 690 0x157a, 0xffffffff, 0x00000000, 691 0xbd4, 0xffffffff, 0x00000902, 692 0xf000, 0xffffffff, 0x96940200, 693 0x21c2, 0xffffffff, 0x00900100, 694 0x3109, 0xffffffff, 0x0020003f, 695 0xe, 0xffffffff, 0x0140001c, 696 0xf, 0x000f0000, 0x000f0000, 697 0x88, 0xffffffff, 0xc060000c, 698 0x89, 0xc0000fff, 0x00000100, 699 0x3e4, 0xffffffff, 0x00000100, 700 0x3e6, 0x00000101, 0x00000000, 701 0x82a, 0xffffffff, 0x00000104, 702 0x1579, 0xff000fff, 0x00000100, 703 0xc33, 0xc0000fff, 0x00000104, 704 0x3079, 0x00000001, 0x00000001, 705 0x3403, 0xff000ff0, 0x00000100, 706 0x3603, 0xff000ff0, 0x00000100 707 }; 708 709 static const u32 godavari_golden_registers[] = 710 { 711 0x1579, 0xff607fff, 0xfc000100, 712 0x1bb6, 0x00010101, 0x00010000, 713 0x260c, 0xffffffff, 0x00000000, 714 0x260c0, 0xf00fffff, 0x00000400, 715 0x184c, 0xffffffff, 0x00010000, 716 0x16ec, 0x000000f0, 0x00000070, 717 0x16f0, 0xf0311fff, 0x80300000, 718 0x263e, 0x73773777, 0x12010001, 719 0x263f, 0xffffffff, 0x00000010, 720 0x200c, 0x00001f0f, 0x0000100a, 721 0xbd2, 0x73773777, 0x12010001, 722 0x902, 0x000fffff, 0x000c007f, 723 0x2285, 0xf000003f, 0x00000007, 724 0x22c9, 0xffffffff, 0x00ff0fff, 725 0xc281, 0x0000ff0f, 0x00000000, 726 0xa293, 0x07ffffff, 0x06000000, 727 0x136, 0x00000fff, 0x00000100, 728 0x3405, 0x00010000, 0x00810001, 729 0x3605, 0x00010000, 0x00810001, 730 0xf9e, 0x00000001, 0x00000002, 731 0x31da, 0x00000008, 0x00000008, 732 0x31dc, 0x00000f00, 0x00000800, 733 0x31dd, 0x00000f00, 0x00000800, 734 0x31e6, 0x00ffffff, 0x00ff7fbf, 735 0x31e7, 0x00ffffff, 0x00ff7faf, 736 0x2300, 0x000000ff, 0x00000001, 737 0x853e, 0x01ff01ff, 0x00000002, 738 0x8526, 0x007ff800, 0x00200000, 739 0x8057, 0xffffffff, 0x00000f40, 740 0x2231, 0x001f3ae3, 0x00000082, 741 0x2235, 0x0000001f, 0x00000010, 742 0xc24d, 0xffffffff, 0x00000000 743 }; 744 745 static void cik_init_golden_registers(struct amdgpu_device *adev) 746 { 747 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 748 mutex_lock(&adev->grbm_idx_mutex); 749 750 switch (adev->asic_type) { 751 case CHIP_BONAIRE: 752 amdgpu_program_register_sequence(adev, 753 bonaire_mgcg_cgcg_init, 754 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); 755 amdgpu_program_register_sequence(adev, 756 bonaire_golden_registers, 757 (const u32)ARRAY_SIZE(bonaire_golden_registers)); 758 amdgpu_program_register_sequence(adev, 759 bonaire_golden_common_registers, 760 (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); 761 amdgpu_program_register_sequence(adev, 762 bonaire_golden_spm_registers, 763 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); 764 break; 765 case CHIP_KABINI: 766 amdgpu_program_register_sequence(adev, 767 kalindi_mgcg_cgcg_init, 768 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 769 amdgpu_program_register_sequence(adev, 770 kalindi_golden_registers, 771 (const u32)ARRAY_SIZE(kalindi_golden_registers)); 772 amdgpu_program_register_sequence(adev, 773 kalindi_golden_common_registers, 774 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 775 amdgpu_program_register_sequence(adev, 776 kalindi_golden_spm_registers, 777 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 778 break; 779 case CHIP_MULLINS: 780 amdgpu_program_register_sequence(adev, 781 kalindi_mgcg_cgcg_init, 782 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 783 amdgpu_program_register_sequence(adev, 784 godavari_golden_registers, 785 (const u32)ARRAY_SIZE(godavari_golden_registers)); 786 amdgpu_program_register_sequence(adev, 787 kalindi_golden_common_registers, 788 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 789 amdgpu_program_register_sequence(adev, 790 kalindi_golden_spm_registers, 791 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 792 break; 793 case CHIP_KAVERI: 794 amdgpu_program_register_sequence(adev, 795 spectre_mgcg_cgcg_init, 796 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); 797 amdgpu_program_register_sequence(adev, 798 spectre_golden_registers, 799 (const u32)ARRAY_SIZE(spectre_golden_registers)); 800 amdgpu_program_register_sequence(adev, 801 spectre_golden_common_registers, 802 (const u32)ARRAY_SIZE(spectre_golden_common_registers)); 803 amdgpu_program_register_sequence(adev, 804 spectre_golden_spm_registers, 805 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 806 break; 807 case CHIP_HAWAII: 808 amdgpu_program_register_sequence(adev, 809 hawaii_mgcg_cgcg_init, 810 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 811 amdgpu_program_register_sequence(adev, 812 hawaii_golden_registers, 813 (const u32)ARRAY_SIZE(hawaii_golden_registers)); 814 amdgpu_program_register_sequence(adev, 815 hawaii_golden_common_registers, 816 (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); 817 amdgpu_program_register_sequence(adev, 818 hawaii_golden_spm_registers, 819 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); 820 break; 821 default: 822 break; 823 } 824 mutex_unlock(&adev->grbm_idx_mutex); 825 } 826 827 /** 828 * cik_get_xclk - get the xclk 829 * 830 * @adev: amdgpu_device pointer 831 * 832 * Returns the reference clock used by the gfx engine 833 * (CIK). 834 */ 835 static u32 cik_get_xclk(struct amdgpu_device *adev) 836 { 837 u32 reference_clock = adev->clock.spll.reference_freq; 838 839 if (adev->flags & AMDGPU_IS_APU) { 840 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) 841 return reference_clock / 2; 842 } else { 843 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 844 return reference_clock / 4; 845 } 846 return reference_clock; 847 } 848 849 /** 850 * cik_srbm_select - select specific register instances 851 * 852 * @adev: amdgpu_device pointer 853 * @me: selected ME (micro engine) 854 * @pipe: pipe 855 * @queue: queue 856 * @vmid: VMID 857 * 858 * Switches the currently active registers instances. Some 859 * registers are instanced per VMID, others are instanced per 860 * me/pipe/queue combination. 861 */ 862 void cik_srbm_select(struct amdgpu_device *adev, 863 u32 me, u32 pipe, u32 queue, u32 vmid) 864 { 865 u32 srbm_gfx_cntl = 866 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)| 867 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)| 868 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)| 869 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK)); 870 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 871 } 872 873 static void cik_vga_set_state(struct amdgpu_device *adev, bool state) 874 { 875 uint32_t tmp; 876 877 tmp = RREG32(mmCONFIG_CNTL); 878 if (state == false) 879 tmp |= CONFIG_CNTL__VGA_DIS_MASK; 880 else 881 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK; 882 WREG32(mmCONFIG_CNTL, tmp); 883 } 884 885 static bool cik_read_disabled_bios(struct amdgpu_device *adev) 886 { 887 u32 bus_cntl; 888 u32 d1vga_control = 0; 889 u32 d2vga_control = 0; 890 u32 vga_render_control = 0; 891 u32 rom_cntl; 892 bool r; 893 894 bus_cntl = RREG32(mmBUS_CNTL); 895 if (adev->mode_info.num_crtc) { 896 d1vga_control = RREG32(mmD1VGA_CONTROL); 897 d2vga_control = RREG32(mmD2VGA_CONTROL); 898 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 899 } 900 rom_cntl = RREG32_SMC(ixROM_CNTL); 901 902 /* enable the rom */ 903 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 904 if (adev->mode_info.num_crtc) { 905 /* Disable VGA mode */ 906 WREG32(mmD1VGA_CONTROL, 907 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 908 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 909 WREG32(mmD2VGA_CONTROL, 910 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 911 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 912 WREG32(mmVGA_RENDER_CONTROL, 913 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 914 } 915 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 916 917 r = amdgpu_read_bios(adev); 918 919 /* restore regs */ 920 WREG32(mmBUS_CNTL, bus_cntl); 921 if (adev->mode_info.num_crtc) { 922 WREG32(mmD1VGA_CONTROL, d1vga_control); 923 WREG32(mmD2VGA_CONTROL, d2vga_control); 924 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 925 } 926 WREG32_SMC(ixROM_CNTL, rom_cntl); 927 return r; 928 } 929 930 static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { 931 {mmGRBM_STATUS, false}, 932 {mmGB_ADDR_CONFIG, false}, 933 {mmMC_ARB_RAMCFG, false}, 934 {mmGB_TILE_MODE0, false}, 935 {mmGB_TILE_MODE1, false}, 936 {mmGB_TILE_MODE2, false}, 937 {mmGB_TILE_MODE3, false}, 938 {mmGB_TILE_MODE4, false}, 939 {mmGB_TILE_MODE5, false}, 940 {mmGB_TILE_MODE6, false}, 941 {mmGB_TILE_MODE7, false}, 942 {mmGB_TILE_MODE8, false}, 943 {mmGB_TILE_MODE9, false}, 944 {mmGB_TILE_MODE10, false}, 945 {mmGB_TILE_MODE11, false}, 946 {mmGB_TILE_MODE12, false}, 947 {mmGB_TILE_MODE13, false}, 948 {mmGB_TILE_MODE14, false}, 949 {mmGB_TILE_MODE15, false}, 950 {mmGB_TILE_MODE16, false}, 951 {mmGB_TILE_MODE17, false}, 952 {mmGB_TILE_MODE18, false}, 953 {mmGB_TILE_MODE19, false}, 954 {mmGB_TILE_MODE20, false}, 955 {mmGB_TILE_MODE21, false}, 956 {mmGB_TILE_MODE22, false}, 957 {mmGB_TILE_MODE23, false}, 958 {mmGB_TILE_MODE24, false}, 959 {mmGB_TILE_MODE25, false}, 960 {mmGB_TILE_MODE26, false}, 961 {mmGB_TILE_MODE27, false}, 962 {mmGB_TILE_MODE28, false}, 963 {mmGB_TILE_MODE29, false}, 964 {mmGB_TILE_MODE30, false}, 965 {mmGB_TILE_MODE31, false}, 966 {mmGB_MACROTILE_MODE0, false}, 967 {mmGB_MACROTILE_MODE1, false}, 968 {mmGB_MACROTILE_MODE2, false}, 969 {mmGB_MACROTILE_MODE3, false}, 970 {mmGB_MACROTILE_MODE4, false}, 971 {mmGB_MACROTILE_MODE5, false}, 972 {mmGB_MACROTILE_MODE6, false}, 973 {mmGB_MACROTILE_MODE7, false}, 974 {mmGB_MACROTILE_MODE8, false}, 975 {mmGB_MACROTILE_MODE9, false}, 976 {mmGB_MACROTILE_MODE10, false}, 977 {mmGB_MACROTILE_MODE11, false}, 978 {mmGB_MACROTILE_MODE12, false}, 979 {mmGB_MACROTILE_MODE13, false}, 980 {mmGB_MACROTILE_MODE14, false}, 981 {mmGB_MACROTILE_MODE15, false}, 982 {mmCC_RB_BACKEND_DISABLE, false, true}, 983 {mmGC_USER_RB_BACKEND_DISABLE, false, true}, 984 {mmGB_BACKEND_MAP, false, false}, 985 {mmPA_SC_RASTER_CONFIG, false, true}, 986 {mmPA_SC_RASTER_CONFIG_1, false, true}, 987 }; 988 989 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, 990 u32 se_num, u32 sh_num, 991 u32 reg_offset) 992 { 993 uint32_t val; 994 995 mutex_lock(&adev->grbm_idx_mutex); 996 if (se_num != 0xffffffff || sh_num != 0xffffffff) 997 gfx_v7_0_select_se_sh(adev, se_num, sh_num); 998 999 val = RREG32(reg_offset); 1000 1001 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1002 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1003 mutex_unlock(&adev->grbm_idx_mutex); 1004 return val; 1005 } 1006 1007 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, 1008 u32 sh_num, u32 reg_offset, u32 *value) 1009 { 1010 uint32_t i; 1011 1012 *value = 0; 1013 for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) { 1014 if (reg_offset != cik_allowed_read_registers[i].reg_offset) 1015 continue; 1016 1017 if (!cik_allowed_read_registers[i].untouched) 1018 *value = cik_allowed_read_registers[i].grbm_indexed ? 1019 cik_read_indexed_register(adev, se_num, 1020 sh_num, reg_offset) : 1021 RREG32(reg_offset); 1022 return 0; 1023 } 1024 return -EINVAL; 1025 } 1026 1027 static void cik_print_gpu_status_regs(struct amdgpu_device *adev) 1028 { 1029 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 1030 RREG32(mmGRBM_STATUS)); 1031 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 1032 RREG32(mmGRBM_STATUS2)); 1033 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1034 RREG32(mmGRBM_STATUS_SE0)); 1035 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1036 RREG32(mmGRBM_STATUS_SE1)); 1037 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 1038 RREG32(mmGRBM_STATUS_SE2)); 1039 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 1040 RREG32(mmGRBM_STATUS_SE3)); 1041 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1042 RREG32(mmSRBM_STATUS)); 1043 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1044 RREG32(mmSRBM_STATUS2)); 1045 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", 1046 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); 1047 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", 1048 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); 1049 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 1050 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 1051 RREG32(mmCP_STALLED_STAT1)); 1052 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 1053 RREG32(mmCP_STALLED_STAT2)); 1054 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 1055 RREG32(mmCP_STALLED_STAT3)); 1056 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 1057 RREG32(mmCP_CPF_BUSY_STAT)); 1058 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 1059 RREG32(mmCP_CPF_STALLED_STAT1)); 1060 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 1061 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 1062 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 1063 RREG32(mmCP_CPC_STALLED_STAT1)); 1064 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 1065 } 1066 1067 /** 1068 * cik_gpu_check_soft_reset - check which blocks are busy 1069 * 1070 * @adev: amdgpu_device pointer 1071 * 1072 * Check which blocks are busy and return the relevant reset 1073 * mask to be used by cik_gpu_soft_reset(). 1074 * Returns a mask of the blocks to be reset. 1075 */ 1076 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev) 1077 { 1078 u32 reset_mask = 0; 1079 u32 tmp; 1080 1081 /* GRBM_STATUS */ 1082 tmp = RREG32(mmGRBM_STATUS); 1083 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 1084 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 1085 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 1086 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 1087 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 1088 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 1089 reset_mask |= AMDGPU_RESET_GFX; 1090 1091 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) 1092 reset_mask |= AMDGPU_RESET_CP; 1093 1094 /* GRBM_STATUS2 */ 1095 tmp = RREG32(mmGRBM_STATUS2); 1096 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 1097 reset_mask |= AMDGPU_RESET_RLC; 1098 1099 /* SDMA0_STATUS_REG */ 1100 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); 1101 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1102 reset_mask |= AMDGPU_RESET_DMA; 1103 1104 /* SDMA1_STATUS_REG */ 1105 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); 1106 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1107 reset_mask |= AMDGPU_RESET_DMA1; 1108 1109 /* SRBM_STATUS2 */ 1110 tmp = RREG32(mmSRBM_STATUS2); 1111 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) 1112 reset_mask |= AMDGPU_RESET_DMA; 1113 1114 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) 1115 reset_mask |= AMDGPU_RESET_DMA1; 1116 1117 /* SRBM_STATUS */ 1118 tmp = RREG32(mmSRBM_STATUS); 1119 1120 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 1121 reset_mask |= AMDGPU_RESET_IH; 1122 1123 if (tmp & SRBM_STATUS__SEM_BUSY_MASK) 1124 reset_mask |= AMDGPU_RESET_SEM; 1125 1126 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 1127 reset_mask |= AMDGPU_RESET_GRBM; 1128 1129 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1130 reset_mask |= AMDGPU_RESET_VMC; 1131 1132 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1133 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) 1134 reset_mask |= AMDGPU_RESET_MC; 1135 1136 if (amdgpu_display_is_display_hung(adev)) 1137 reset_mask |= AMDGPU_RESET_DISPLAY; 1138 1139 /* Skip MC reset as it's mostly likely not hung, just busy */ 1140 if (reset_mask & AMDGPU_RESET_MC) { 1141 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1142 reset_mask &= ~AMDGPU_RESET_MC; 1143 } 1144 1145 return reset_mask; 1146 } 1147 1148 /** 1149 * cik_gpu_soft_reset - soft reset GPU 1150 * 1151 * @adev: amdgpu_device pointer 1152 * @reset_mask: mask of which blocks to reset 1153 * 1154 * Soft reset the blocks specified in @reset_mask. 1155 */ 1156 static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) 1157 { 1158 struct amdgpu_mode_mc_save save; 1159 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1160 u32 tmp; 1161 1162 if (reset_mask == 0) 1163 return; 1164 1165 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1166 1167 cik_print_gpu_status_regs(adev); 1168 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1169 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); 1170 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1171 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); 1172 1173 /* disable CG/PG */ 1174 1175 /* stop the rlc */ 1176 gfx_v7_0_rlc_stop(adev); 1177 1178 /* Disable GFX parsing/prefetching */ 1179 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1180 1181 /* Disable MEC parsing/prefetching */ 1182 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1183 1184 if (reset_mask & AMDGPU_RESET_DMA) { 1185 /* sdma0 */ 1186 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1187 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1188 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1189 } 1190 if (reset_mask & AMDGPU_RESET_DMA1) { 1191 /* sdma1 */ 1192 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1193 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1194 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1195 } 1196 1197 gmc_v7_0_mc_stop(adev, &save); 1198 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1199 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 1200 } 1201 1202 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) 1203 grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 1204 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 1205 1206 if (reset_mask & AMDGPU_RESET_CP) { 1207 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 1208 1209 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1210 } 1211 1212 if (reset_mask & AMDGPU_RESET_DMA) 1213 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1214 1215 if (reset_mask & AMDGPU_RESET_DMA1) 1216 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1217 1218 if (reset_mask & AMDGPU_RESET_DISPLAY) 1219 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 1220 1221 if (reset_mask & AMDGPU_RESET_RLC) 1222 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 1223 1224 if (reset_mask & AMDGPU_RESET_SEM) 1225 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK; 1226 1227 if (reset_mask & AMDGPU_RESET_IH) 1228 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 1229 1230 if (reset_mask & AMDGPU_RESET_GRBM) 1231 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1232 1233 if (reset_mask & AMDGPU_RESET_VMC) 1234 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; 1235 1236 if (!(adev->flags & AMDGPU_IS_APU)) { 1237 if (reset_mask & AMDGPU_RESET_MC) 1238 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; 1239 } 1240 1241 if (grbm_soft_reset) { 1242 tmp = RREG32(mmGRBM_SOFT_RESET); 1243 tmp |= grbm_soft_reset; 1244 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1245 WREG32(mmGRBM_SOFT_RESET, tmp); 1246 tmp = RREG32(mmGRBM_SOFT_RESET); 1247 1248 udelay(50); 1249 1250 tmp &= ~grbm_soft_reset; 1251 WREG32(mmGRBM_SOFT_RESET, tmp); 1252 tmp = RREG32(mmGRBM_SOFT_RESET); 1253 } 1254 1255 if (srbm_soft_reset) { 1256 tmp = RREG32(mmSRBM_SOFT_RESET); 1257 tmp |= srbm_soft_reset; 1258 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1259 WREG32(mmSRBM_SOFT_RESET, tmp); 1260 tmp = RREG32(mmSRBM_SOFT_RESET); 1261 1262 udelay(50); 1263 1264 tmp &= ~srbm_soft_reset; 1265 WREG32(mmSRBM_SOFT_RESET, tmp); 1266 tmp = RREG32(mmSRBM_SOFT_RESET); 1267 } 1268 1269 /* Wait a little for things to settle down */ 1270 udelay(50); 1271 1272 gmc_v7_0_mc_resume(adev, &save); 1273 udelay(50); 1274 1275 cik_print_gpu_status_regs(adev); 1276 } 1277 1278 struct kv_reset_save_regs { 1279 u32 gmcon_reng_execute; 1280 u32 gmcon_misc; 1281 u32 gmcon_misc3; 1282 }; 1283 1284 static void kv_save_regs_for_reset(struct amdgpu_device *adev, 1285 struct kv_reset_save_regs *save) 1286 { 1287 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); 1288 save->gmcon_misc = RREG32(mmGMCON_MISC); 1289 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); 1290 1291 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & 1292 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK); 1293 WREG32(mmGMCON_MISC, save->gmcon_misc & 1294 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK | 1295 GMCON_MISC__STCTRL_STUTTER_EN_MASK)); 1296 } 1297 1298 static void kv_restore_regs_for_reset(struct amdgpu_device *adev, 1299 struct kv_reset_save_regs *save) 1300 { 1301 int i; 1302 1303 WREG32(mmGMCON_PGFSM_WRITE, 0); 1304 WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); 1305 1306 for (i = 0; i < 5; i++) 1307 WREG32(mmGMCON_PGFSM_WRITE, 0); 1308 1309 WREG32(mmGMCON_PGFSM_WRITE, 0); 1310 WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); 1311 1312 for (i = 0; i < 5; i++) 1313 WREG32(mmGMCON_PGFSM_WRITE, 0); 1314 1315 WREG32(mmGMCON_PGFSM_WRITE, 0x210000); 1316 WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); 1317 1318 for (i = 0; i < 5; i++) 1319 WREG32(mmGMCON_PGFSM_WRITE, 0); 1320 1321 WREG32(mmGMCON_PGFSM_WRITE, 0x21003); 1322 WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); 1323 1324 for (i = 0; i < 5; i++) 1325 WREG32(mmGMCON_PGFSM_WRITE, 0); 1326 1327 WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); 1328 WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); 1329 1330 for (i = 0; i < 5; i++) 1331 WREG32(mmGMCON_PGFSM_WRITE, 0); 1332 1333 WREG32(mmGMCON_PGFSM_WRITE, 0); 1334 WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); 1335 1336 for (i = 0; i < 5; i++) 1337 WREG32(mmGMCON_PGFSM_WRITE, 0); 1338 1339 WREG32(mmGMCON_PGFSM_WRITE, 0x420000); 1340 WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); 1341 1342 for (i = 0; i < 5; i++) 1343 WREG32(mmGMCON_PGFSM_WRITE, 0); 1344 1345 WREG32(mmGMCON_PGFSM_WRITE, 0x120202); 1346 WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); 1347 1348 for (i = 0; i < 5; i++) 1349 WREG32(mmGMCON_PGFSM_WRITE, 0); 1350 1351 WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); 1352 WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); 1353 1354 for (i = 0; i < 5; i++) 1355 WREG32(mmGMCON_PGFSM_WRITE, 0); 1356 1357 WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); 1358 WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); 1359 1360 for (i = 0; i < 5; i++) 1361 WREG32(mmGMCON_PGFSM_WRITE, 0); 1362 1363 WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); 1364 WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); 1365 1366 WREG32(mmGMCON_MISC3, save->gmcon_misc3); 1367 WREG32(mmGMCON_MISC, save->gmcon_misc); 1368 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); 1369 } 1370 1371 static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) 1372 { 1373 struct amdgpu_mode_mc_save save; 1374 struct kv_reset_save_regs kv_save = { 0 }; 1375 u32 tmp, i; 1376 1377 dev_info(adev->dev, "GPU pci config reset\n"); 1378 1379 /* disable dpm? */ 1380 1381 /* disable cg/pg */ 1382 1383 /* Disable GFX parsing/prefetching */ 1384 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | 1385 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1386 1387 /* Disable MEC parsing/prefetching */ 1388 WREG32(mmCP_MEC_CNTL, 1389 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1390 1391 /* sdma0 */ 1392 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1393 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1394 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1395 /* sdma1 */ 1396 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1397 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1398 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1399 /* XXX other engines? */ 1400 1401 /* halt the rlc, disable cp internal ints */ 1402 gfx_v7_0_rlc_stop(adev); 1403 1404 udelay(50); 1405 1406 /* disable mem access */ 1407 gmc_v7_0_mc_stop(adev, &save); 1408 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1409 dev_warn(adev->dev, "Wait for MC idle timed out !\n"); 1410 } 1411 1412 if (adev->flags & AMDGPU_IS_APU) 1413 kv_save_regs_for_reset(adev, &kv_save); 1414 1415 /* disable BM */ 1416 pci_clear_master(adev->pdev); 1417 /* reset */ 1418 amdgpu_pci_config_reset(adev); 1419 1420 udelay(100); 1421 1422 /* wait for asic to come out of reset */ 1423 for (i = 0; i < adev->usec_timeout; i++) { 1424 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) 1425 break; 1426 udelay(1); 1427 } 1428 1429 /* does asic init need to be run first??? */ 1430 if (adev->flags & AMDGPU_IS_APU) 1431 kv_restore_regs_for_reset(adev, &kv_save); 1432 } 1433 1434 static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) 1435 { 1436 u32 tmp = RREG32(mmBIOS_SCRATCH_3); 1437 1438 if (hung) 1439 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1440 else 1441 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1442 1443 WREG32(mmBIOS_SCRATCH_3, tmp); 1444 } 1445 1446 /** 1447 * cik_asic_reset - soft reset GPU 1448 * 1449 * @adev: amdgpu_device pointer 1450 * 1451 * Look up which blocks are hung and attempt 1452 * to reset them. 1453 * Returns 0 for success. 1454 */ 1455 static int cik_asic_reset(struct amdgpu_device *adev) 1456 { 1457 u32 reset_mask; 1458 1459 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1460 1461 if (reset_mask) 1462 cik_set_bios_scratch_engine_hung(adev, true); 1463 1464 /* try soft reset */ 1465 cik_gpu_soft_reset(adev, reset_mask); 1466 1467 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1468 1469 /* try pci config reset */ 1470 if (reset_mask && amdgpu_hard_reset) 1471 cik_gpu_pci_config_reset(adev); 1472 1473 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1474 1475 if (!reset_mask) 1476 cik_set_bios_scratch_engine_hung(adev, false); 1477 1478 return 0; 1479 } 1480 1481 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 1482 u32 cntl_reg, u32 status_reg) 1483 { 1484 int r, i; 1485 struct atom_clock_dividers dividers; 1486 uint32_t tmp; 1487 1488 r = amdgpu_atombios_get_clock_dividers(adev, 1489 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1490 clock, false, ÷rs); 1491 if (r) 1492 return r; 1493 1494 tmp = RREG32_SMC(cntl_reg); 1495 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 1496 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 1497 tmp |= dividers.post_divider; 1498 WREG32_SMC(cntl_reg, tmp); 1499 1500 for (i = 0; i < 100; i++) { 1501 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1502 break; 1503 mdelay(10); 1504 } 1505 if (i == 100) 1506 return -ETIMEDOUT; 1507 1508 return 0; 1509 } 1510 1511 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1512 { 1513 int r = 0; 1514 1515 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1516 if (r) 1517 return r; 1518 1519 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1520 return r; 1521 } 1522 1523 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1524 { 1525 int r, i; 1526 struct atom_clock_dividers dividers; 1527 u32 tmp; 1528 1529 r = amdgpu_atombios_get_clock_dividers(adev, 1530 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1531 ecclk, false, ÷rs); 1532 if (r) 1533 return r; 1534 1535 for (i = 0; i < 100; i++) { 1536 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1537 break; 1538 mdelay(10); 1539 } 1540 if (i == 100) 1541 return -ETIMEDOUT; 1542 1543 tmp = RREG32_SMC(ixCG_ECLK_CNTL); 1544 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | 1545 CG_ECLK_CNTL__ECLK_DIVIDER_MASK); 1546 tmp |= dividers.post_divider; 1547 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 1548 1549 for (i = 0; i < 100; i++) { 1550 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1551 break; 1552 mdelay(10); 1553 } 1554 if (i == 100) 1555 return -ETIMEDOUT; 1556 1557 return 0; 1558 } 1559 1560 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1561 { 1562 struct pci_dev *root = adev->pdev->bus->self; 1563 int bridge_pos, gpu_pos; 1564 u32 speed_cntl, mask, current_data_rate; 1565 int ret, i; 1566 u16 tmp16; 1567 1568 if (amdgpu_pcie_gen2 == 0) 1569 return; 1570 1571 if (adev->flags & AMDGPU_IS_APU) 1572 return; 1573 1574 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1575 if (ret != 0) 1576 return; 1577 1578 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) 1579 return; 1580 1581 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1582 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> 1583 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 1584 if (mask & DRM_PCIE_SPEED_80) { 1585 if (current_data_rate == 2) { 1586 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1587 return; 1588 } 1589 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1590 } else if (mask & DRM_PCIE_SPEED_50) { 1591 if (current_data_rate == 1) { 1592 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1593 return; 1594 } 1595 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1596 } 1597 1598 bridge_pos = pci_pcie_cap(root); 1599 if (!bridge_pos) 1600 return; 1601 1602 gpu_pos = pci_pcie_cap(adev->pdev); 1603 if (!gpu_pos) 1604 return; 1605 1606 if (mask & DRM_PCIE_SPEED_80) { 1607 /* re-try equalization if gen3 is not already enabled */ 1608 if (current_data_rate != 2) { 1609 u16 bridge_cfg, gpu_cfg; 1610 u16 bridge_cfg2, gpu_cfg2; 1611 u32 max_lw, current_lw, tmp; 1612 1613 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1614 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1615 1616 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1617 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1618 1619 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1620 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1621 1622 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1623 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> 1624 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; 1625 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) 1626 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; 1627 1628 if (current_lw < max_lw) { 1629 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1630 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { 1631 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | 1632 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); 1633 tmp |= (max_lw << 1634 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); 1635 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | 1636 PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | 1637 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; 1638 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); 1639 } 1640 } 1641 1642 for (i = 0; i < 10; i++) { 1643 /* check status */ 1644 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1645 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1646 break; 1647 1648 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1649 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1650 1651 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1652 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1653 1654 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1655 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1656 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1657 1658 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1659 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; 1660 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1661 1662 mdelay(100); 1663 1664 /* linkctl */ 1665 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1666 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1667 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1668 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1669 1670 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1671 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1672 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1673 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1674 1675 /* linkctl2 */ 1676 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1677 tmp16 &= ~((1 << 4) | (7 << 9)); 1678 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 1679 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1680 1681 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1682 tmp16 &= ~((1 << 4) | (7 << 9)); 1683 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 1684 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1685 1686 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1687 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1688 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1689 } 1690 } 1691 } 1692 1693 /* set the link speed */ 1694 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | 1695 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; 1696 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1697 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1698 1699 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1700 tmp16 &= ~0xf; 1701 if (mask & DRM_PCIE_SPEED_80) 1702 tmp16 |= 3; /* gen3 */ 1703 else if (mask & DRM_PCIE_SPEED_50) 1704 tmp16 |= 2; /* gen2 */ 1705 else 1706 tmp16 |= 1; /* gen1 */ 1707 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1708 1709 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1710 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; 1711 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1712 1713 for (i = 0; i < adev->usec_timeout; i++) { 1714 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1715 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) 1716 break; 1717 udelay(1); 1718 } 1719 } 1720 1721 static void cik_program_aspm(struct amdgpu_device *adev) 1722 { 1723 u32 data, orig; 1724 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1725 bool disable_clkreq = false; 1726 1727 if (amdgpu_aspm == 0) 1728 return; 1729 1730 /* XXX double check APUs */ 1731 if (adev->flags & AMDGPU_IS_APU) 1732 return; 1733 1734 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1735 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1736 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | 1737 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1738 if (orig != data) 1739 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1740 1741 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1742 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1743 if (orig != data) 1744 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1745 1746 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1747 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1748 if (orig != data) 1749 WREG32_PCIE(ixPCIE_P_CNTL, data); 1750 1751 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1752 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | 1753 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 1754 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1755 if (!disable_l0s) 1756 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); 1757 1758 if (!disable_l1) { 1759 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); 1760 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1761 if (orig != data) 1762 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1763 1764 if (!disable_plloff_in_l1) { 1765 bool clk_req_support; 1766 1767 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0); 1768 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1769 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1770 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1771 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1772 if (orig != data) 1773 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data); 1774 1775 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1); 1776 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1777 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1778 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1779 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1780 if (orig != data) 1781 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data); 1782 1783 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0); 1784 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1785 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1786 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1787 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1788 if (orig != data) 1789 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data); 1790 1791 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1); 1792 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1793 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1794 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1795 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1796 if (orig != data) 1797 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data); 1798 1799 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1800 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1801 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); 1802 if (orig != data) 1803 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1804 1805 if (!disable_clkreq) { 1806 struct pci_dev *root = adev->pdev->bus->self; 1807 u32 lnkcap; 1808 1809 clk_req_support = false; 1810 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 1811 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 1812 clk_req_support = true; 1813 } else { 1814 clk_req_support = false; 1815 } 1816 1817 if (clk_req_support) { 1818 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1819 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 1820 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1821 if (orig != data) 1822 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1823 1824 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1825 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | 1826 THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1827 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1828 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1829 if (orig != data) 1830 WREG32_SMC(ixTHM_CLK_CNTL, data); 1831 1832 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1833 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1834 MISC_CLK_CTRL__ZCLK_SEL_MASK); 1835 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1836 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1837 if (orig != data) 1838 WREG32_SMC(ixMISC_CLK_CTRL, data); 1839 1840 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1841 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; 1842 if (orig != data) 1843 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1844 1845 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1846 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; 1847 if (orig != data) 1848 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); 1849 1850 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1851 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1852 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1853 if (orig != data) 1854 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1855 } 1856 } 1857 } else { 1858 if (orig != data) 1859 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1860 } 1861 1862 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 1863 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1864 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1865 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1866 if (orig != data) 1867 WREG32_PCIE(ixPCIE_CNTL2, data); 1868 1869 if (!disable_l0s) { 1870 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1871 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == 1872 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { 1873 data = RREG32_PCIE(ixPCIE_LC_STATUS1); 1874 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && 1875 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { 1876 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1877 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1878 if (orig != data) 1879 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1880 } 1881 } 1882 } 1883 } 1884 1885 static uint32_t cik_get_rev_id(struct amdgpu_device *adev) 1886 { 1887 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1888 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1889 } 1890 1891 static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = 1892 { 1893 /* ORDER MATTERS! */ 1894 { 1895 .type = AMD_IP_BLOCK_TYPE_COMMON, 1896 .major = 1, 1897 .minor = 0, 1898 .rev = 0, 1899 .funcs = &cik_common_ip_funcs, 1900 }, 1901 { 1902 .type = AMD_IP_BLOCK_TYPE_GMC, 1903 .major = 7, 1904 .minor = 0, 1905 .rev = 0, 1906 .funcs = &gmc_v7_0_ip_funcs, 1907 }, 1908 { 1909 .type = AMD_IP_BLOCK_TYPE_IH, 1910 .major = 2, 1911 .minor = 0, 1912 .rev = 0, 1913 .funcs = &cik_ih_ip_funcs, 1914 }, 1915 { 1916 .type = AMD_IP_BLOCK_TYPE_SMC, 1917 .major = 7, 1918 .minor = 0, 1919 .rev = 0, 1920 .funcs = &ci_dpm_ip_funcs, 1921 }, 1922 { 1923 .type = AMD_IP_BLOCK_TYPE_DCE, 1924 .major = 8, 1925 .minor = 2, 1926 .rev = 0, 1927 .funcs = &dce_v8_0_ip_funcs, 1928 }, 1929 { 1930 .type = AMD_IP_BLOCK_TYPE_GFX, 1931 .major = 7, 1932 .minor = 2, 1933 .rev = 0, 1934 .funcs = &gfx_v7_0_ip_funcs, 1935 }, 1936 { 1937 .type = AMD_IP_BLOCK_TYPE_SDMA, 1938 .major = 2, 1939 .minor = 0, 1940 .rev = 0, 1941 .funcs = &cik_sdma_ip_funcs, 1942 }, 1943 { 1944 .type = AMD_IP_BLOCK_TYPE_UVD, 1945 .major = 4, 1946 .minor = 2, 1947 .rev = 0, 1948 .funcs = &uvd_v4_2_ip_funcs, 1949 }, 1950 { 1951 .type = AMD_IP_BLOCK_TYPE_VCE, 1952 .major = 2, 1953 .minor = 0, 1954 .rev = 0, 1955 .funcs = &vce_v2_0_ip_funcs, 1956 }, 1957 }; 1958 1959 static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = 1960 { 1961 /* ORDER MATTERS! */ 1962 { 1963 .type = AMD_IP_BLOCK_TYPE_COMMON, 1964 .major = 1, 1965 .minor = 0, 1966 .rev = 0, 1967 .funcs = &cik_common_ip_funcs, 1968 }, 1969 { 1970 .type = AMD_IP_BLOCK_TYPE_GMC, 1971 .major = 7, 1972 .minor = 0, 1973 .rev = 0, 1974 .funcs = &gmc_v7_0_ip_funcs, 1975 }, 1976 { 1977 .type = AMD_IP_BLOCK_TYPE_IH, 1978 .major = 2, 1979 .minor = 0, 1980 .rev = 0, 1981 .funcs = &cik_ih_ip_funcs, 1982 }, 1983 { 1984 .type = AMD_IP_BLOCK_TYPE_SMC, 1985 .major = 7, 1986 .minor = 0, 1987 .rev = 0, 1988 .funcs = &ci_dpm_ip_funcs, 1989 }, 1990 { 1991 .type = AMD_IP_BLOCK_TYPE_DCE, 1992 .major = 8, 1993 .minor = 5, 1994 .rev = 0, 1995 .funcs = &dce_v8_0_ip_funcs, 1996 }, 1997 { 1998 .type = AMD_IP_BLOCK_TYPE_GFX, 1999 .major = 7, 2000 .minor = 3, 2001 .rev = 0, 2002 .funcs = &gfx_v7_0_ip_funcs, 2003 }, 2004 { 2005 .type = AMD_IP_BLOCK_TYPE_SDMA, 2006 .major = 2, 2007 .minor = 0, 2008 .rev = 0, 2009 .funcs = &cik_sdma_ip_funcs, 2010 }, 2011 { 2012 .type = AMD_IP_BLOCK_TYPE_UVD, 2013 .major = 4, 2014 .minor = 2, 2015 .rev = 0, 2016 .funcs = &uvd_v4_2_ip_funcs, 2017 }, 2018 { 2019 .type = AMD_IP_BLOCK_TYPE_VCE, 2020 .major = 2, 2021 .minor = 0, 2022 .rev = 0, 2023 .funcs = &vce_v2_0_ip_funcs, 2024 }, 2025 }; 2026 2027 static const struct amdgpu_ip_block_version kabini_ip_blocks[] = 2028 { 2029 /* ORDER MATTERS! */ 2030 { 2031 .type = AMD_IP_BLOCK_TYPE_COMMON, 2032 .major = 1, 2033 .minor = 0, 2034 .rev = 0, 2035 .funcs = &cik_common_ip_funcs, 2036 }, 2037 { 2038 .type = AMD_IP_BLOCK_TYPE_GMC, 2039 .major = 7, 2040 .minor = 0, 2041 .rev = 0, 2042 .funcs = &gmc_v7_0_ip_funcs, 2043 }, 2044 { 2045 .type = AMD_IP_BLOCK_TYPE_IH, 2046 .major = 2, 2047 .minor = 0, 2048 .rev = 0, 2049 .funcs = &cik_ih_ip_funcs, 2050 }, 2051 { 2052 .type = AMD_IP_BLOCK_TYPE_SMC, 2053 .major = 7, 2054 .minor = 0, 2055 .rev = 0, 2056 .funcs = &kv_dpm_ip_funcs, 2057 }, 2058 { 2059 .type = AMD_IP_BLOCK_TYPE_DCE, 2060 .major = 8, 2061 .minor = 3, 2062 .rev = 0, 2063 .funcs = &dce_v8_0_ip_funcs, 2064 }, 2065 { 2066 .type = AMD_IP_BLOCK_TYPE_GFX, 2067 .major = 7, 2068 .minor = 2, 2069 .rev = 0, 2070 .funcs = &gfx_v7_0_ip_funcs, 2071 }, 2072 { 2073 .type = AMD_IP_BLOCK_TYPE_SDMA, 2074 .major = 2, 2075 .minor = 0, 2076 .rev = 0, 2077 .funcs = &cik_sdma_ip_funcs, 2078 }, 2079 { 2080 .type = AMD_IP_BLOCK_TYPE_UVD, 2081 .major = 4, 2082 .minor = 2, 2083 .rev = 0, 2084 .funcs = &uvd_v4_2_ip_funcs, 2085 }, 2086 { 2087 .type = AMD_IP_BLOCK_TYPE_VCE, 2088 .major = 2, 2089 .minor = 0, 2090 .rev = 0, 2091 .funcs = &vce_v2_0_ip_funcs, 2092 }, 2093 }; 2094 2095 static const struct amdgpu_ip_block_version mullins_ip_blocks[] = 2096 { 2097 /* ORDER MATTERS! */ 2098 { 2099 .type = AMD_IP_BLOCK_TYPE_COMMON, 2100 .major = 1, 2101 .minor = 0, 2102 .rev = 0, 2103 .funcs = &cik_common_ip_funcs, 2104 }, 2105 { 2106 .type = AMD_IP_BLOCK_TYPE_GMC, 2107 .major = 7, 2108 .minor = 0, 2109 .rev = 0, 2110 .funcs = &gmc_v7_0_ip_funcs, 2111 }, 2112 { 2113 .type = AMD_IP_BLOCK_TYPE_IH, 2114 .major = 2, 2115 .minor = 0, 2116 .rev = 0, 2117 .funcs = &cik_ih_ip_funcs, 2118 }, 2119 { 2120 .type = AMD_IP_BLOCK_TYPE_SMC, 2121 .major = 7, 2122 .minor = 0, 2123 .rev = 0, 2124 .funcs = &kv_dpm_ip_funcs, 2125 }, 2126 { 2127 .type = AMD_IP_BLOCK_TYPE_DCE, 2128 .major = 8, 2129 .minor = 3, 2130 .rev = 0, 2131 .funcs = &dce_v8_0_ip_funcs, 2132 }, 2133 { 2134 .type = AMD_IP_BLOCK_TYPE_GFX, 2135 .major = 7, 2136 .minor = 2, 2137 .rev = 0, 2138 .funcs = &gfx_v7_0_ip_funcs, 2139 }, 2140 { 2141 .type = AMD_IP_BLOCK_TYPE_SDMA, 2142 .major = 2, 2143 .minor = 0, 2144 .rev = 0, 2145 .funcs = &cik_sdma_ip_funcs, 2146 }, 2147 { 2148 .type = AMD_IP_BLOCK_TYPE_UVD, 2149 .major = 4, 2150 .minor = 2, 2151 .rev = 0, 2152 .funcs = &uvd_v4_2_ip_funcs, 2153 }, 2154 { 2155 .type = AMD_IP_BLOCK_TYPE_VCE, 2156 .major = 2, 2157 .minor = 0, 2158 .rev = 0, 2159 .funcs = &vce_v2_0_ip_funcs, 2160 }, 2161 }; 2162 2163 static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = 2164 { 2165 /* ORDER MATTERS! */ 2166 { 2167 .type = AMD_IP_BLOCK_TYPE_COMMON, 2168 .major = 1, 2169 .minor = 0, 2170 .rev = 0, 2171 .funcs = &cik_common_ip_funcs, 2172 }, 2173 { 2174 .type = AMD_IP_BLOCK_TYPE_GMC, 2175 .major = 7, 2176 .minor = 0, 2177 .rev = 0, 2178 .funcs = &gmc_v7_0_ip_funcs, 2179 }, 2180 { 2181 .type = AMD_IP_BLOCK_TYPE_IH, 2182 .major = 2, 2183 .minor = 0, 2184 .rev = 0, 2185 .funcs = &cik_ih_ip_funcs, 2186 }, 2187 { 2188 .type = AMD_IP_BLOCK_TYPE_SMC, 2189 .major = 7, 2190 .minor = 0, 2191 .rev = 0, 2192 .funcs = &kv_dpm_ip_funcs, 2193 }, 2194 { 2195 .type = AMD_IP_BLOCK_TYPE_DCE, 2196 .major = 8, 2197 .minor = 1, 2198 .rev = 0, 2199 .funcs = &dce_v8_0_ip_funcs, 2200 }, 2201 { 2202 .type = AMD_IP_BLOCK_TYPE_GFX, 2203 .major = 7, 2204 .minor = 1, 2205 .rev = 0, 2206 .funcs = &gfx_v7_0_ip_funcs, 2207 }, 2208 { 2209 .type = AMD_IP_BLOCK_TYPE_SDMA, 2210 .major = 2, 2211 .minor = 0, 2212 .rev = 0, 2213 .funcs = &cik_sdma_ip_funcs, 2214 }, 2215 { 2216 .type = AMD_IP_BLOCK_TYPE_UVD, 2217 .major = 4, 2218 .minor = 2, 2219 .rev = 0, 2220 .funcs = &uvd_v4_2_ip_funcs, 2221 }, 2222 { 2223 .type = AMD_IP_BLOCK_TYPE_VCE, 2224 .major = 2, 2225 .minor = 0, 2226 .rev = 0, 2227 .funcs = &vce_v2_0_ip_funcs, 2228 }, 2229 }; 2230 2231 int cik_set_ip_blocks(struct amdgpu_device *adev) 2232 { 2233 switch (adev->asic_type) { 2234 case CHIP_BONAIRE: 2235 adev->ip_blocks = bonaire_ip_blocks; 2236 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); 2237 break; 2238 case CHIP_HAWAII: 2239 adev->ip_blocks = hawaii_ip_blocks; 2240 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); 2241 break; 2242 case CHIP_KAVERI: 2243 adev->ip_blocks = kaveri_ip_blocks; 2244 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); 2245 break; 2246 case CHIP_KABINI: 2247 adev->ip_blocks = kabini_ip_blocks; 2248 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); 2249 break; 2250 case CHIP_MULLINS: 2251 adev->ip_blocks = mullins_ip_blocks; 2252 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); 2253 break; 2254 default: 2255 /* FIXME: not supported yet */ 2256 return -EINVAL; 2257 } 2258 2259 return 0; 2260 } 2261 2262 static const struct amdgpu_asic_funcs cik_asic_funcs = 2263 { 2264 .read_disabled_bios = &cik_read_disabled_bios, 2265 .read_register = &cik_read_register, 2266 .reset = &cik_asic_reset, 2267 .set_vga_state = &cik_vga_set_state, 2268 .get_xclk = &cik_get_xclk, 2269 .set_uvd_clocks = &cik_set_uvd_clocks, 2270 .set_vce_clocks = &cik_set_vce_clocks, 2271 .get_cu_info = &gfx_v7_0_get_cu_info, 2272 /* these should be moved to their own ip modules */ 2273 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 2274 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, 2275 }; 2276 2277 static int cik_common_early_init(void *handle) 2278 { 2279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2280 2281 adev->smc_rreg = &cik_smc_rreg; 2282 adev->smc_wreg = &cik_smc_wreg; 2283 adev->pcie_rreg = &cik_pcie_rreg; 2284 adev->pcie_wreg = &cik_pcie_wreg; 2285 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; 2286 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; 2287 adev->didt_rreg = &cik_didt_rreg; 2288 adev->didt_wreg = &cik_didt_wreg; 2289 2290 adev->asic_funcs = &cik_asic_funcs; 2291 2292 adev->has_uvd = true; 2293 2294 adev->rev_id = cik_get_rev_id(adev); 2295 adev->external_rev_id = 0xFF; 2296 switch (adev->asic_type) { 2297 case CHIP_BONAIRE: 2298 adev->cg_flags = 2299 AMDGPU_CG_SUPPORT_GFX_MGCG | 2300 AMDGPU_CG_SUPPORT_GFX_MGLS | 2301 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2302 AMDGPU_CG_SUPPORT_GFX_CGLS | 2303 AMDGPU_CG_SUPPORT_GFX_CGTS | 2304 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2305 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2306 AMDGPU_CG_SUPPORT_MC_LS | 2307 AMDGPU_CG_SUPPORT_MC_MGCG | 2308 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2309 AMDGPU_CG_SUPPORT_SDMA_LS | 2310 AMDGPU_CG_SUPPORT_BIF_LS | 2311 AMDGPU_CG_SUPPORT_VCE_MGCG | 2312 AMDGPU_CG_SUPPORT_UVD_MGCG | 2313 AMDGPU_CG_SUPPORT_HDP_LS | 2314 AMDGPU_CG_SUPPORT_HDP_MGCG; 2315 adev->pg_flags = 0; 2316 adev->external_rev_id = adev->rev_id + 0x14; 2317 break; 2318 case CHIP_HAWAII: 2319 adev->cg_flags = 2320 AMDGPU_CG_SUPPORT_GFX_MGCG | 2321 AMDGPU_CG_SUPPORT_GFX_MGLS | 2322 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2323 AMDGPU_CG_SUPPORT_GFX_CGLS | 2324 AMDGPU_CG_SUPPORT_GFX_CGTS | 2325 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2326 AMDGPU_CG_SUPPORT_MC_LS | 2327 AMDGPU_CG_SUPPORT_MC_MGCG | 2328 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2329 AMDGPU_CG_SUPPORT_SDMA_LS | 2330 AMDGPU_CG_SUPPORT_BIF_LS | 2331 AMDGPU_CG_SUPPORT_VCE_MGCG | 2332 AMDGPU_CG_SUPPORT_UVD_MGCG | 2333 AMDGPU_CG_SUPPORT_HDP_LS | 2334 AMDGPU_CG_SUPPORT_HDP_MGCG; 2335 adev->pg_flags = 0; 2336 adev->external_rev_id = 0x28; 2337 break; 2338 case CHIP_KAVERI: 2339 adev->cg_flags = 2340 AMDGPU_CG_SUPPORT_GFX_MGCG | 2341 AMDGPU_CG_SUPPORT_GFX_MGLS | 2342 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2343 AMDGPU_CG_SUPPORT_GFX_CGLS | 2344 AMDGPU_CG_SUPPORT_GFX_CGTS | 2345 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2346 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2347 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2348 AMDGPU_CG_SUPPORT_SDMA_LS | 2349 AMDGPU_CG_SUPPORT_BIF_LS | 2350 AMDGPU_CG_SUPPORT_VCE_MGCG | 2351 AMDGPU_CG_SUPPORT_UVD_MGCG | 2352 AMDGPU_CG_SUPPORT_HDP_LS | 2353 AMDGPU_CG_SUPPORT_HDP_MGCG; 2354 adev->pg_flags = 2355 /*AMDGPU_PG_SUPPORT_GFX_PG | 2356 AMDGPU_PG_SUPPORT_GFX_SMG | 2357 AMDGPU_PG_SUPPORT_GFX_DMG |*/ 2358 AMDGPU_PG_SUPPORT_UVD | 2359 /*AMDGPU_PG_SUPPORT_VCE | 2360 AMDGPU_PG_SUPPORT_CP | 2361 AMDGPU_PG_SUPPORT_GDS | 2362 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2363 AMDGPU_PG_SUPPORT_ACP | 2364 AMDGPU_PG_SUPPORT_SAMU |*/ 2365 0; 2366 if (adev->pdev->device == 0x1312 || 2367 adev->pdev->device == 0x1316 || 2368 adev->pdev->device == 0x1317) 2369 adev->external_rev_id = 0x41; 2370 else 2371 adev->external_rev_id = 0x1; 2372 break; 2373 case CHIP_KABINI: 2374 case CHIP_MULLINS: 2375 adev->cg_flags = 2376 AMDGPU_CG_SUPPORT_GFX_MGCG | 2377 AMDGPU_CG_SUPPORT_GFX_MGLS | 2378 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2379 AMDGPU_CG_SUPPORT_GFX_CGLS | 2380 AMDGPU_CG_SUPPORT_GFX_CGTS | 2381 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2382 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2383 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2384 AMDGPU_CG_SUPPORT_SDMA_LS | 2385 AMDGPU_CG_SUPPORT_BIF_LS | 2386 AMDGPU_CG_SUPPORT_VCE_MGCG | 2387 AMDGPU_CG_SUPPORT_UVD_MGCG | 2388 AMDGPU_CG_SUPPORT_HDP_LS | 2389 AMDGPU_CG_SUPPORT_HDP_MGCG; 2390 adev->pg_flags = 2391 /*AMDGPU_PG_SUPPORT_GFX_PG | 2392 AMDGPU_PG_SUPPORT_GFX_SMG | */ 2393 AMDGPU_PG_SUPPORT_UVD | 2394 /*AMDGPU_PG_SUPPORT_VCE | 2395 AMDGPU_PG_SUPPORT_CP | 2396 AMDGPU_PG_SUPPORT_GDS | 2397 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2398 AMDGPU_PG_SUPPORT_SAMU |*/ 2399 0; 2400 if (adev->asic_type == CHIP_KABINI) { 2401 if (adev->rev_id == 0) 2402 adev->external_rev_id = 0x81; 2403 else if (adev->rev_id == 1) 2404 adev->external_rev_id = 0x82; 2405 else if (adev->rev_id == 2) 2406 adev->external_rev_id = 0x85; 2407 } else 2408 adev->external_rev_id = adev->rev_id + 0xa1; 2409 break; 2410 default: 2411 /* FIXME: not supported yet */ 2412 return -EINVAL; 2413 } 2414 2415 return 0; 2416 } 2417 2418 static int cik_common_sw_init(void *handle) 2419 { 2420 return 0; 2421 } 2422 2423 static int cik_common_sw_fini(void *handle) 2424 { 2425 return 0; 2426 } 2427 2428 static int cik_common_hw_init(void *handle) 2429 { 2430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2431 2432 /* move the golden regs per IP block */ 2433 cik_init_golden_registers(adev); 2434 /* enable pcie gen2/3 link */ 2435 cik_pcie_gen3_enable(adev); 2436 /* enable aspm */ 2437 cik_program_aspm(adev); 2438 2439 return 0; 2440 } 2441 2442 static int cik_common_hw_fini(void *handle) 2443 { 2444 return 0; 2445 } 2446 2447 static int cik_common_suspend(void *handle) 2448 { 2449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2450 2451 return cik_common_hw_fini(adev); 2452 } 2453 2454 static int cik_common_resume(void *handle) 2455 { 2456 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2457 2458 return cik_common_hw_init(adev); 2459 } 2460 2461 static bool cik_common_is_idle(void *handle) 2462 { 2463 return true; 2464 } 2465 2466 static int cik_common_wait_for_idle(void *handle) 2467 { 2468 return 0; 2469 } 2470 2471 static void cik_common_print_status(void *handle) 2472 { 2473 2474 } 2475 2476 static int cik_common_soft_reset(void *handle) 2477 { 2478 /* XXX hard reset?? */ 2479 return 0; 2480 } 2481 2482 static int cik_common_set_clockgating_state(void *handle, 2483 enum amd_clockgating_state state) 2484 { 2485 return 0; 2486 } 2487 2488 static int cik_common_set_powergating_state(void *handle, 2489 enum amd_powergating_state state) 2490 { 2491 return 0; 2492 } 2493 2494 const struct amd_ip_funcs cik_common_ip_funcs = { 2495 .early_init = cik_common_early_init, 2496 .late_init = NULL, 2497 .sw_init = cik_common_sw_init, 2498 .sw_fini = cik_common_sw_fini, 2499 .hw_init = cik_common_hw_init, 2500 .hw_fini = cik_common_hw_fini, 2501 .suspend = cik_common_suspend, 2502 .resume = cik_common_resume, 2503 .is_idle = cik_common_is_idle, 2504 .wait_for_idle = cik_common_wait_for_idle, 2505 .soft_reset = cik_common_soft_reset, 2506 .print_status = cik_common_print_status, 2507 .set_clockgating_state = cik_common_set_clockgating_state, 2508 .set_powergating_state = cik_common_set_powergating_state, 2509 }; 2510