1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "athub_v3_0.h" 26 #include "athub/athub_3_0_0_offset.h" 27 #include "athub/athub_3_0_0_sh_mask.h" 28 #include "navi10_enum.h" 29 #include "soc15_common.h" 30 31 #define regATHUB_MISC_CNTL_V3_0_1 0x00d7 32 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0 33 #define regATHUB_MISC_CNTL_V3_3_0 0x00d8 34 #define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0 35 36 37 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) 38 { 39 uint32_t data; 40 41 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { 42 case IP_VERSION(3, 0, 1): 43 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1); 44 break; 45 case IP_VERSION(3, 3, 0): 46 case IP_VERSION(3, 4, 2): 47 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0); 48 break; 49 default: 50 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL); 51 break; 52 } 53 return data; 54 } 55 56 static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) 57 { 58 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { 59 case IP_VERSION(3, 0, 1): 60 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data); 61 break; 62 case IP_VERSION(3, 3, 0): 63 case IP_VERSION(3, 4, 2): 64 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data); 65 break; 66 default: 67 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data); 68 break; 69 } 70 } 71 72 static void 73 athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 74 bool enable) 75 { 76 uint32_t def, data; 77 78 def = data = athub_v3_0_get_cg_cntl(adev); 79 80 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG)) 81 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 82 else 83 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 84 85 if (def != data) 86 athub_v3_0_set_cg_cntl(adev, data); 87 } 88 89 static void 90 athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 91 bool enable) 92 { 93 uint32_t def, data; 94 95 def = data = athub_v3_0_get_cg_cntl(adev); 96 97 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS)) 98 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 99 else 100 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 101 102 if (def != data) 103 athub_v3_0_set_cg_cntl(adev, data); 104 } 105 106 int athub_v3_0_set_clockgating(struct amdgpu_device *adev, 107 enum amd_clockgating_state state) 108 { 109 if (amdgpu_sriov_vf(adev)) 110 return 0; 111 112 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { 113 case IP_VERSION(3, 0, 0): 114 case IP_VERSION(3, 0, 1): 115 case IP_VERSION(3, 0, 2): 116 case IP_VERSION(3, 3, 0): 117 case IP_VERSION(3, 4, 2): 118 athub_v3_0_update_medium_grain_clock_gating(adev, 119 state == AMD_CG_STATE_GATE); 120 athub_v3_0_update_medium_grain_light_sleep(adev, 121 state == AMD_CG_STATE_GATE); 122 break; 123 default: 124 break; 125 } 126 127 return 0; 128 } 129 130 void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 131 { 132 int data; 133 134 /* AMD_CG_SUPPORT_ATHUB_MGCG */ 135 data = athub_v3_0_get_cg_cntl(adev); 136 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 137 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; 138 139 /* AMD_CG_SUPPORT_ATHUB_LS */ 140 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) 141 *flags |= AMD_CG_SUPPORT_ATHUB_LS; 142 } 143