1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "athub_v3_0.h" 26 #include "athub/athub_3_0_0_offset.h" 27 #include "athub/athub_3_0_0_sh_mask.h" 28 #include "navi10_enum.h" 29 #include "soc15_common.h" 30 31 #define regATHUB_MISC_CNTL_V3_0_1 0x00d7 32 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0 33 34 35 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) 36 { 37 uint32_t data; 38 39 switch (adev->ip_versions[ATHUB_HWIP][0]) { 40 case IP_VERSION(3, 0, 1): 41 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1); 42 break; 43 default: 44 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL); 45 break; 46 } 47 return data; 48 } 49 50 static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) 51 { 52 switch (adev->ip_versions[ATHUB_HWIP][0]) { 53 case IP_VERSION(3, 0, 1): 54 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data); 55 break; 56 default: 57 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data); 58 break; 59 } 60 } 61 62 static void 63 athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 64 bool enable) 65 { 66 uint32_t def, data; 67 68 def = data = athub_v3_0_get_cg_cntl(adev); 69 70 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG)) 71 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 72 else 73 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 74 75 if (def != data) 76 athub_v3_0_set_cg_cntl(adev, data); 77 } 78 79 static void 80 athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 81 bool enable) 82 { 83 uint32_t def, data; 84 85 def = data = athub_v3_0_get_cg_cntl(adev); 86 87 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS)) 88 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 89 else 90 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 91 92 if (def != data) 93 athub_v3_0_set_cg_cntl(adev, data); 94 } 95 96 int athub_v3_0_set_clockgating(struct amdgpu_device *adev, 97 enum amd_clockgating_state state) 98 { 99 if (amdgpu_sriov_vf(adev)) 100 return 0; 101 102 switch (adev->ip_versions[ATHUB_HWIP][0]) { 103 case IP_VERSION(3, 0, 0): 104 case IP_VERSION(3, 0, 1): 105 case IP_VERSION(3, 0, 2): 106 athub_v3_0_update_medium_grain_clock_gating(adev, 107 state == AMD_CG_STATE_GATE); 108 athub_v3_0_update_medium_grain_light_sleep(adev, 109 state == AMD_CG_STATE_GATE); 110 break; 111 default: 112 break; 113 } 114 115 return 0; 116 } 117 118 void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 119 { 120 int data; 121 122 /* AMD_CG_SUPPORT_ATHUB_MGCG */ 123 data = athub_v3_0_get_cg_cntl(adev); 124 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 125 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; 126 127 /* AMD_CG_SUPPORT_ATHUB_LS */ 128 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) 129 *flags |= AMD_CG_SUPPORT_ATHUB_LS; 130 } 131