1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "athub_v2_0.h" 26 27 #include "athub/athub_2_0_0_offset.h" 28 #include "athub/athub_2_0_0_sh_mask.h" 29 #include "athub/athub_2_0_0_default.h" 30 31 #include "soc15_common.h" 32 33 static void 34 athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 35 bool enable) 36 { 37 uint32_t def, data; 38 39 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 40 41 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 42 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 43 else 44 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 45 46 if (def != data) 47 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 48 } 49 50 static void 51 athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 52 bool enable) 53 { 54 uint32_t def, data; 55 56 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 57 58 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 59 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 60 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 61 else 62 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 63 64 if (def != data) 65 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 66 } 67 68 int athub_v2_0_set_clockgating(struct amdgpu_device *adev, 69 enum amd_clockgating_state state) 70 { 71 if (amdgpu_sriov_vf(adev)) 72 return 0; 73 74 switch (adev->asic_type) { 75 case CHIP_NAVI10: 76 case CHIP_NAVI14: 77 case CHIP_NAVI12: 78 athub_v2_0_update_medium_grain_clock_gating(adev, 79 state == AMD_CG_STATE_GATE); 80 athub_v2_0_update_medium_grain_light_sleep(adev, 81 state == AMD_CG_STATE_GATE); 82 break; 83 default: 84 break; 85 } 86 87 return 0; 88 } 89 90 void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 91 { 92 int data; 93 94 /* AMD_CG_SUPPORT_ATHUB_MGCG */ 95 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 96 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 97 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; 98 99 /* AMD_CG_SUPPORT_ATHUB_LS */ 100 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) 101 *flags |= AMD_CG_SUPPORT_ATHUB_LS; 102 } 103