1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 26 #include "soc15_common.h" 27 #include "amdgpu_reg_state.h" 28 #include "amdgpu_xcp.h" 29 #include "gfx_v9_4_3.h" 30 #include "gfxhub_v1_2.h" 31 #include "sdma_v4_4_2.h" 32 #include "amdgpu_ip.h" 33 34 void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) 35 { 36 int i; 37 38 adev->doorbell_index.kiq = AMDGPU_DOORBELL_LAYOUT1_KIQ_START; 39 40 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START; 41 42 adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START; 43 adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END; 44 adev->doorbell_index.xcc_doorbell_range = AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE; 45 46 adev->doorbell_index.sdma_doorbell_range = 20; 47 for (i = 0; i < adev->sdma.num_instances; i++) 48 adev->doorbell_index.sdma_engine[i] = 49 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START + 50 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 51 52 adev->doorbell_index.ih = AMDGPU_DOORBELL_LAYOUT1_IH; 53 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL_LAYOUT1_VCN_START; 54 55 adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP; 56 adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP; 57 58 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1; 59 } 60 61 static enum amdgpu_gfx_partition 62 __aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 63 { 64 struct amdgpu_device *adev = xcp_mgr->adev; 65 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 66 67 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 68 if (adev->gfx.funcs->get_xccs_per_xcp) 69 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 70 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 71 mode = num_xcc / num_xcc_per_xcp; 72 73 if (num_xcc_per_xcp == 1) 74 return AMDGPU_CPX_PARTITION_MODE; 75 76 switch (mode) { 77 case 1: 78 return AMDGPU_SPX_PARTITION_MODE; 79 case 2: 80 return AMDGPU_DPX_PARTITION_MODE; 81 case 3: 82 return AMDGPU_TPX_PARTITION_MODE; 83 case 4: 84 return AMDGPU_QPX_PARTITION_MODE; 85 default: 86 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 87 } 88 89 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 90 } 91 92 static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 93 { 94 enum amdgpu_gfx_partition derv_mode, 95 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 96 struct amdgpu_device *adev = xcp_mgr->adev; 97 98 derv_mode = __aqua_vanjaram_calc_xcp_mode(xcp_mgr); 99 100 if (amdgpu_sriov_vf(adev)) 101 return derv_mode; 102 103 if (adev->nbio.funcs->get_compute_partition_mode) { 104 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 105 if (mode != derv_mode) { 106 dev_warn( 107 adev->dev, 108 "Mismatch in compute partition mode - reported : %d derived : %d", 109 mode, derv_mode); 110 if (derv_mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 111 amdgpu_device_bus_status_check(adev); 112 } 113 } 114 115 return mode; 116 } 117 118 static int __aqua_vanjaram_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 119 { 120 int num_xcc, num_xcc_per_xcp = 0; 121 122 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 123 124 switch (mode) { 125 case AMDGPU_SPX_PARTITION_MODE: 126 num_xcc_per_xcp = num_xcc; 127 break; 128 case AMDGPU_DPX_PARTITION_MODE: 129 num_xcc_per_xcp = num_xcc / 2; 130 break; 131 case AMDGPU_TPX_PARTITION_MODE: 132 num_xcc_per_xcp = num_xcc / 3; 133 break; 134 case AMDGPU_QPX_PARTITION_MODE: 135 num_xcc_per_xcp = num_xcc / 4; 136 break; 137 case AMDGPU_CPX_PARTITION_MODE: 138 num_xcc_per_xcp = 1; 139 break; 140 } 141 142 return num_xcc_per_xcp; 143 } 144 145 static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 146 enum AMDGPU_XCP_IP_BLOCK ip_id, 147 struct amdgpu_xcp_ip *ip) 148 { 149 struct amdgpu_device *adev = xcp_mgr->adev; 150 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 151 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 152 153 num_sdma = adev->sdma.num_instances; 154 num_vcn = adev->vcn.num_vcn_inst; 155 num_shared_vcn = 1; 156 157 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 158 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 159 160 switch (xcp_mgr->mode) { 161 case AMDGPU_SPX_PARTITION_MODE: 162 case AMDGPU_DPX_PARTITION_MODE: 163 case AMDGPU_TPX_PARTITION_MODE: 164 case AMDGPU_QPX_PARTITION_MODE: 165 case AMDGPU_CPX_PARTITION_MODE: 166 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 167 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 168 break; 169 default: 170 return -EINVAL; 171 } 172 173 if (num_vcn && num_xcp > num_vcn) 174 num_shared_vcn = num_xcp / num_vcn; 175 176 switch (ip_id) { 177 case AMDGPU_XCP_GFXHUB: 178 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 179 ip->ip_funcs = &gfxhub_v1_2_xcp_funcs; 180 break; 181 case AMDGPU_XCP_GFX: 182 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 183 ip->ip_funcs = &gfx_v9_4_3_xcp_funcs; 184 break; 185 case AMDGPU_XCP_SDMA: 186 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 187 ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; 188 break; 189 case AMDGPU_XCP_VCN: 190 ip->inst_mask = 191 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 192 /* TODO : Assign IP funcs */ 193 break; 194 default: 195 return -EINVAL; 196 } 197 198 ip->ip_id = ip_id; 199 200 return 0; 201 } 202 203 static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr, 204 int px_mode, int *num_xcp, 205 uint16_t *nps_modes) 206 { 207 struct amdgpu_device *adev = xcp_mgr->adev; 208 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); 209 210 if (!num_xcp || !nps_modes || !(xcp_mgr->supp_xcp_modes & BIT(px_mode))) 211 return -EINVAL; 212 213 switch (px_mode) { 214 case AMDGPU_SPX_PARTITION_MODE: 215 *num_xcp = 1; 216 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 217 break; 218 case AMDGPU_DPX_PARTITION_MODE: 219 *num_xcp = 2; 220 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 221 BIT(AMDGPU_NPS2_PARTITION_MODE); 222 break; 223 case AMDGPU_TPX_PARTITION_MODE: 224 *num_xcp = 3; 225 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 226 BIT(AMDGPU_NPS4_PARTITION_MODE); 227 break; 228 case AMDGPU_QPX_PARTITION_MODE: 229 *num_xcp = 4; 230 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 231 BIT(AMDGPU_NPS4_PARTITION_MODE); 232 if (gc_ver == IP_VERSION(9, 5, 0)) 233 *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); 234 break; 235 case AMDGPU_CPX_PARTITION_MODE: 236 *num_xcp = NUM_XCC(adev->gfx.xcc_mask); 237 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 238 BIT(AMDGPU_NPS4_PARTITION_MODE); 239 if (gc_ver == IP_VERSION(9, 5, 0)) 240 *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 return 0; 247 } 248 249 static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 250 int mode, 251 struct amdgpu_xcp_cfg *xcp_cfg) 252 { 253 struct amdgpu_device *adev = xcp_mgr->adev; 254 int max_res[AMDGPU_XCP_RES_MAX] = {}; 255 bool res_lt_xcp; 256 int num_xcp, i, r; 257 u16 nps_modes; 258 259 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 260 return -EINVAL; 261 262 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 263 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 264 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 265 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 266 267 r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &num_xcp, &nps_modes); 268 if (r) 269 return r; 270 271 xcp_cfg->compatible_nps_modes = 272 (adev->gmc.supported_nps_modes & nps_modes); 273 xcp_cfg->num_res = ARRAY_SIZE(max_res); 274 275 for (i = 0; i < xcp_cfg->num_res; i++) { 276 xcp_cfg->xcp_res[i].id = i; 277 if (!max_res[i]) 278 continue; 279 res_lt_xcp = max_res[i] < num_xcp; 280 xcp_cfg->xcp_res[i].num_inst = 281 res_lt_xcp ? 1 : max_res[i] / num_xcp; 282 xcp_cfg->xcp_res[i].num_inst = 283 i == AMDGPU_XCP_RES_JPEG ? 284 xcp_cfg->xcp_res[i].num_inst * 285 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 286 xcp_cfg->xcp_res[i].num_shared = 287 res_lt_xcp ? num_xcp / max_res[i] : 1; 288 } 289 290 return 0; 291 } 292 293 static enum amdgpu_gfx_partition 294 __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 295 { 296 struct amdgpu_device *adev = xcp_mgr->adev; 297 int num_xcc; 298 299 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 300 301 if (adev->gmc.num_mem_partitions == 1) 302 return AMDGPU_SPX_PARTITION_MODE; 303 304 if (adev->gmc.num_mem_partitions == num_xcc) 305 return AMDGPU_CPX_PARTITION_MODE; 306 307 if (adev->gmc.num_mem_partitions == num_xcc / 2) 308 return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE : 309 AMDGPU_CPX_PARTITION_MODE; 310 311 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) 312 return AMDGPU_DPX_PARTITION_MODE; 313 314 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 315 } 316 317 static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 318 enum amdgpu_gfx_partition mode) 319 { 320 struct amdgpu_device *adev = xcp_mgr->adev; 321 int num_xcc, num_xccs_per_xcp, r; 322 int num_xcp, nps_mode; 323 u16 supp_nps_modes; 324 bool comp_mode; 325 326 nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 327 r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &num_xcp, 328 &supp_nps_modes); 329 if (r) 330 return false; 331 332 comp_mode = !!(BIT(nps_mode) & supp_nps_modes); 333 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 334 switch (mode) { 335 case AMDGPU_SPX_PARTITION_MODE: 336 return comp_mode && num_xcc > 0; 337 case AMDGPU_DPX_PARTITION_MODE: 338 return comp_mode && (num_xcc % 4) == 0; 339 case AMDGPU_TPX_PARTITION_MODE: 340 return comp_mode && ((num_xcc % 3) == 0); 341 case AMDGPU_QPX_PARTITION_MODE: 342 num_xccs_per_xcp = num_xcc / 4; 343 return comp_mode && (num_xccs_per_xcp >= 2); 344 case AMDGPU_CPX_PARTITION_MODE: 345 return comp_mode && (num_xcc > 1); 346 default: 347 return false; 348 } 349 350 return false; 351 } 352 353 static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 354 { 355 int mode; 356 357 xcp_mgr->avail_xcp_modes = 0; 358 359 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 360 if (__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) 361 xcp_mgr->avail_xcp_modes |= BIT(mode); 362 } 363 } 364 365 static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 366 int mode, int *num_xcps) 367 { 368 int num_xcc_per_xcp, num_xcc, ret; 369 struct amdgpu_device *adev; 370 u32 flags = 0; 371 372 adev = xcp_mgr->adev; 373 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 374 375 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 376 mode = __aqua_vanjaram_get_auto_mode(xcp_mgr); 377 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 378 dev_err(adev->dev, 379 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 380 adev->gmc.num_mem_partitions); 381 return -EINVAL; 382 } 383 } else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) { 384 dev_err(adev->dev, 385 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 386 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 387 return -EINVAL; 388 } 389 390 if (adev->kfd.init_complete && !amdgpu_in_reset(adev) && 391 !adev->in_suspend) 392 flags |= AMDGPU_XCP_OPS_KFD; 393 394 if (flags & AMDGPU_XCP_OPS_KFD) { 395 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 396 if (ret) 397 goto out; 398 } 399 400 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 401 if (ret) 402 goto unlock; 403 404 num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, mode); 405 if (adev->gfx.funcs->switch_partition_mode) 406 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, 407 num_xcc_per_xcp); 408 409 /* Init info about new xcps */ 410 *num_xcps = num_xcc / num_xcc_per_xcp; 411 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 412 413 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 414 if (!ret) 415 __aqua_vanjaram_update_available_partition_mode(xcp_mgr); 416 unlock: 417 if (flags & AMDGPU_XCP_OPS_KFD) 418 amdgpu_amdkfd_unlock_kfd(adev); 419 out: 420 return ret; 421 } 422 423 static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev, 424 int xcc_id, uint8_t *mem_id) 425 { 426 /* memory/spatial modes validation check is already done */ 427 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 428 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 429 430 return 0; 431 } 432 433 static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 434 struct amdgpu_xcp *xcp, uint8_t *mem_id) 435 { 436 struct amdgpu_numa_info numa_info; 437 struct amdgpu_device *adev; 438 uint32_t xcc_mask; 439 int r, i, xcc_id; 440 441 adev = xcp_mgr->adev; 442 /* TODO: BIOS is not returning the right info now 443 * Check on this later 444 */ 445 /* 446 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 447 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 448 */ 449 if (adev->gmc.num_mem_partitions == 1) { 450 /* Only one range */ 451 *mem_id = 0; 452 return 0; 453 } 454 455 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 456 if (r || !xcc_mask) 457 return -EINVAL; 458 459 xcc_id = ffs(xcc_mask) - 1; 460 if (!adev->gmc.is_app_apu) 461 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); 462 463 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 464 465 if (r) 466 return r; 467 468 r = -EINVAL; 469 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 470 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 471 *mem_id = i; 472 r = 0; 473 break; 474 } 475 } 476 477 return r; 478 } 479 480 static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 481 enum AMDGPU_XCP_IP_BLOCK ip_id, 482 struct amdgpu_xcp_ip *ip) 483 { 484 if (!ip) 485 return -EINVAL; 486 487 return __aqua_vanjaram_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 488 } 489 490 struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = { 491 .switch_partition_mode = &aqua_vanjaram_switch_partition_mode, 492 .query_partition_mode = &aqua_vanjaram_query_partition_mode, 493 .get_ip_details = &aqua_vanjaram_get_xcp_ip_details, 494 .get_xcp_res_info = &aqua_vanjaram_get_xcp_res_info, 495 .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id, 496 }; 497 498 static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) 499 { 500 int ret; 501 502 if (amdgpu_sriov_vf(adev)) 503 aqua_vanjaram_xcp_funcs.switch_partition_mode = NULL; 504 505 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 1, 506 &aqua_vanjaram_xcp_funcs); 507 if (ret) 508 return ret; 509 510 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 511 /* TODO: Default memory node affinity init */ 512 513 return ret; 514 } 515 516 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev) 517 { 518 u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask; 519 int ret, i; 520 521 /* generally 1 AID supports 4 instances */ 522 adev->sdma.num_inst_per_aid = 4; 523 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask); 524 525 adev->aid_mask = i = 1; 526 inst_mask >>= adev->sdma.num_inst_per_aid; 527 528 for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask; 529 inst_mask >>= adev->sdma.num_inst_per_aid, ++i) { 530 avail_inst = inst_mask & mask; 531 if (avail_inst == mask || avail_inst == 0x3 || 532 avail_inst == 0xc) 533 adev->aid_mask |= (1 << i); 534 } 535 536 /* Harvest config is not used for aqua vanjaram. VCN and JPEGs will be 537 * addressed based on logical instance ids. 538 */ 539 adev->vcn.harvest_config = 0; 540 adev->vcn.num_inst_per_aid = 1; 541 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); 542 adev->jpeg.harvest_config = 0; 543 adev->jpeg.num_inst_per_aid = 1; 544 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask); 545 546 ret = aqua_vanjaram_xcp_mgr_init(adev); 547 if (ret) 548 return ret; 549 550 amdgpu_ip_map_init(adev); 551 552 return 0; 553 } 554 555 static void aqua_read_smn(struct amdgpu_device *adev, 556 struct amdgpu_smn_reg_data *regdata, 557 uint64_t smn_addr) 558 { 559 regdata->addr = smn_addr; 560 regdata->value = RREG32_PCIE(smn_addr); 561 } 562 563 struct aqua_reg_list { 564 uint64_t start_addr; 565 uint32_t num_regs; 566 uint32_t incrx; 567 }; 568 569 #define DW_ADDR_INCR 4 570 571 static void aqua_read_smn_ext(struct amdgpu_device *adev, 572 struct amdgpu_smn_reg_data *regdata, 573 uint64_t smn_addr, int i) 574 { 575 regdata->addr = 576 smn_addr + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i); 577 regdata->value = RREG32_PCIE_EXT(regdata->addr); 578 } 579 580 #define smnreg_0x1A340218 0x1A340218 581 #define smnreg_0x1A3402E4 0x1A3402E4 582 #define smnreg_0x1A340294 0x1A340294 583 #define smreg_0x1A380088 0x1A380088 584 585 #define NUM_PCIE_SMN_REGS 14 586 587 static struct aqua_reg_list pcie_reg_addrs[] = { 588 { smnreg_0x1A340218, 1, 0 }, 589 { smnreg_0x1A3402E4, 1, 0 }, 590 { smnreg_0x1A340294, 6, DW_ADDR_INCR }, 591 { smreg_0x1A380088, 6, DW_ADDR_INCR }, 592 }; 593 594 /* 595 * Return the GPU's internal US switch port, or NULL if it is not visible 596 * (e.g. passthrough) or the EP is parented under an unrelated bridge. 597 */ 598 static struct pci_dev *aqua_vanjaram_get_us_pdev(struct amdgpu_device *adev) 599 { 600 struct pci_dev *ds_pdev, *us_pdev; 601 602 ds_pdev = pci_upstream_bridge(adev->pdev); 603 if (!ds_pdev || ds_pdev->vendor != PCI_VENDOR_ID_ATI || 604 pci_pcie_type(ds_pdev) != PCI_EXP_TYPE_DOWNSTREAM) 605 return NULL; 606 607 us_pdev = pci_upstream_bridge(ds_pdev); 608 if (!us_pdev || 609 (us_pdev->vendor != PCI_VENDOR_ID_ATI && 610 us_pdev->vendor != PCI_VENDOR_ID_AMD) || 611 pci_pcie_type(us_pdev) != PCI_EXP_TYPE_UPSTREAM) 612 return NULL; 613 614 return us_pdev; 615 } 616 617 static ssize_t aqua_vanjaram_read_pcie_state(struct amdgpu_device *adev, 618 void *buf, size_t max_size) 619 { 620 struct amdgpu_reg_state_pcie_v1_0 *pcie_reg_state; 621 uint32_t start_addr, incrx, num_regs, szbuf; 622 struct amdgpu_regs_pcie_v1_0 *pcie_regs; 623 struct amdgpu_smn_reg_data *reg_data; 624 struct pci_dev *us_pdev; 625 int aer_cap, r, n; 626 627 if (!buf || !max_size) 628 return -EINVAL; 629 630 pcie_reg_state = (struct amdgpu_reg_state_pcie_v1_0 *)buf; 631 632 szbuf = sizeof(*pcie_reg_state) + 633 amdgpu_reginst_size(1, sizeof(*pcie_regs), NUM_PCIE_SMN_REGS); 634 /* Only one instance of pcie regs */ 635 if (max_size < szbuf) 636 return -EOVERFLOW; 637 638 pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf + 639 sizeof(*pcie_reg_state)); 640 pcie_regs->inst_header.instance = 0; 641 pcie_regs->inst_header.state = AMDGPU_INST_S_OK; 642 pcie_regs->inst_header.num_smn_regs = NUM_PCIE_SMN_REGS; 643 644 reg_data = pcie_regs->smn_reg_values; 645 646 for (r = 0; r < ARRAY_SIZE(pcie_reg_addrs); r++) { 647 start_addr = pcie_reg_addrs[r].start_addr; 648 incrx = pcie_reg_addrs[r].incrx; 649 num_regs = pcie_reg_addrs[r].num_regs; 650 for (n = 0; n < num_regs; n++) { 651 aqua_read_smn(adev, reg_data, start_addr + n * incrx); 652 ++reg_data; 653 } 654 } 655 656 us_pdev = aqua_vanjaram_get_us_pdev(adev); 657 if (us_pdev) { 658 pcie_capability_read_word(us_pdev, PCI_EXP_DEVSTA, 659 &pcie_regs->device_status); 660 pcie_capability_read_word(us_pdev, PCI_EXP_LNKSTA, 661 &pcie_regs->link_status); 662 663 aer_cap = pci_find_ext_capability(us_pdev, PCI_EXT_CAP_ID_ERR); 664 if (aer_cap) { 665 pci_read_config_dword(us_pdev, 666 aer_cap + PCI_ERR_COR_STATUS, 667 &pcie_regs->pcie_corr_err_status); 668 pci_read_config_dword(us_pdev, 669 aer_cap + PCI_ERR_UNCOR_STATUS, 670 &pcie_regs->pcie_uncorr_err_status); 671 } 672 673 pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS, 674 &pcie_regs->sub_bus_number_latency); 675 } 676 677 pcie_reg_state->common_header.structure_size = szbuf; 678 pcie_reg_state->common_header.format_revision = 1; 679 pcie_reg_state->common_header.content_revision = 0; 680 pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE; 681 pcie_reg_state->common_header.num_instances = 1; 682 683 return pcie_reg_state->common_header.structure_size; 684 } 685 686 #define smnreg_0x11A00050 0x11A00050 687 #define smnreg_0x11A00180 0x11A00180 688 #define smnreg_0x11A00070 0x11A00070 689 #define smnreg_0x11A00200 0x11A00200 690 #define smnreg_0x11A0020C 0x11A0020C 691 #define smnreg_0x11A00210 0x11A00210 692 #define smnreg_0x11A00108 0x11A00108 693 694 #define XGMI_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 695 696 #define NUM_XGMI_SMN_REGS 25 697 698 static struct aqua_reg_list xgmi_reg_addrs[] = { 699 { smnreg_0x11A00050, 1, 0 }, 700 { smnreg_0x11A00180, 16, DW_ADDR_INCR }, 701 { smnreg_0x11A00070, 4, DW_ADDR_INCR }, 702 { smnreg_0x11A00200, 1, 0 }, 703 { smnreg_0x11A0020C, 1, 0 }, 704 { smnreg_0x11A00210, 1, 0 }, 705 { smnreg_0x11A00108, 1, 0 }, 706 }; 707 708 static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev, 709 void *buf, size_t max_size) 710 { 711 struct amdgpu_reg_state_xgmi_v1_0 *xgmi_reg_state; 712 uint32_t start_addr, incrx, num_regs, szbuf; 713 struct amdgpu_regs_xgmi_v1_0 *xgmi_regs; 714 struct amdgpu_smn_reg_data *reg_data; 715 const int max_xgmi_instances = 8; 716 int inst = 0, i, j, r, n; 717 const int xgmi_inst = 2; 718 void *p; 719 720 if (!buf || !max_size) 721 return -EINVAL; 722 723 xgmi_reg_state = (struct amdgpu_reg_state_xgmi_v1_0 *)buf; 724 725 szbuf = sizeof(*xgmi_reg_state) + 726 amdgpu_reginst_size(max_xgmi_instances, sizeof(*xgmi_regs), 727 NUM_XGMI_SMN_REGS); 728 /* Only one instance of pcie regs */ 729 if (max_size < szbuf) 730 return -EOVERFLOW; 731 732 p = &xgmi_reg_state->xgmi_state_regs[0]; 733 for_each_inst(i, adev->aid_mask) { 734 for (j = 0; j < xgmi_inst; ++j) { 735 xgmi_regs = (struct amdgpu_regs_xgmi_v1_0 *)p; 736 xgmi_regs->inst_header.instance = inst++; 737 738 xgmi_regs->inst_header.state = AMDGPU_INST_S_OK; 739 xgmi_regs->inst_header.num_smn_regs = NUM_XGMI_SMN_REGS; 740 741 reg_data = xgmi_regs->smn_reg_values; 742 743 for (r = 0; r < ARRAY_SIZE(xgmi_reg_addrs); r++) { 744 start_addr = xgmi_reg_addrs[r].start_addr; 745 incrx = xgmi_reg_addrs[r].incrx; 746 num_regs = xgmi_reg_addrs[r].num_regs; 747 748 for (n = 0; n < num_regs; n++) { 749 aqua_read_smn_ext( 750 adev, reg_data, 751 XGMI_LINK_REG(start_addr, j) + 752 n * incrx, 753 i); 754 ++reg_data; 755 } 756 } 757 p = reg_data; 758 } 759 } 760 761 xgmi_reg_state->common_header.structure_size = szbuf; 762 xgmi_reg_state->common_header.format_revision = 1; 763 xgmi_reg_state->common_header.content_revision = 0; 764 xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI; 765 xgmi_reg_state->common_header.num_instances = max_xgmi_instances; 766 767 return xgmi_reg_state->common_header.structure_size; 768 } 769 770 #define smnreg_0x11C00070 0x11C00070 771 #define smnreg_0x11C00210 0x11C00210 772 773 static struct aqua_reg_list wafl_reg_addrs[] = { 774 { smnreg_0x11C00070, 4, DW_ADDR_INCR }, 775 { smnreg_0x11C00210, 1, 0 }, 776 }; 777 778 #define WAFL_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 779 780 #define NUM_WAFL_SMN_REGS 5 781 782 static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev, 783 void *buf, size_t max_size) 784 { 785 struct amdgpu_reg_state_wafl_v1_0 *wafl_reg_state; 786 uint32_t start_addr, incrx, num_regs, szbuf; 787 struct amdgpu_regs_wafl_v1_0 *wafl_regs; 788 struct amdgpu_smn_reg_data *reg_data; 789 const int max_wafl_instances = 8; 790 int inst = 0, i, j, r, n; 791 const int wafl_inst = 2; 792 void *p; 793 794 if (!buf || !max_size) 795 return -EINVAL; 796 797 wafl_reg_state = (struct amdgpu_reg_state_wafl_v1_0 *)buf; 798 799 szbuf = sizeof(*wafl_reg_state) + 800 amdgpu_reginst_size(max_wafl_instances, sizeof(*wafl_regs), 801 NUM_WAFL_SMN_REGS); 802 803 if (max_size < szbuf) 804 return -EOVERFLOW; 805 806 p = &wafl_reg_state->wafl_state_regs[0]; 807 for_each_inst(i, adev->aid_mask) { 808 for (j = 0; j < wafl_inst; ++j) { 809 wafl_regs = (struct amdgpu_regs_wafl_v1_0 *)p; 810 wafl_regs->inst_header.instance = inst++; 811 812 wafl_regs->inst_header.state = AMDGPU_INST_S_OK; 813 wafl_regs->inst_header.num_smn_regs = NUM_WAFL_SMN_REGS; 814 815 reg_data = wafl_regs->smn_reg_values; 816 817 for (r = 0; r < ARRAY_SIZE(wafl_reg_addrs); r++) { 818 start_addr = wafl_reg_addrs[r].start_addr; 819 incrx = wafl_reg_addrs[r].incrx; 820 num_regs = wafl_reg_addrs[r].num_regs; 821 for (n = 0; n < num_regs; n++) { 822 aqua_read_smn_ext( 823 adev, reg_data, 824 WAFL_LINK_REG(start_addr, j) + 825 n * incrx, 826 i); 827 ++reg_data; 828 } 829 } 830 p = reg_data; 831 } 832 } 833 834 wafl_reg_state->common_header.structure_size = szbuf; 835 wafl_reg_state->common_header.format_revision = 1; 836 wafl_reg_state->common_header.content_revision = 0; 837 wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL; 838 wafl_reg_state->common_header.num_instances = max_wafl_instances; 839 840 return wafl_reg_state->common_header.structure_size; 841 } 842 843 #define smnreg_0x1B311060 0x1B311060 844 #define smnreg_0x1B411060 0x1B411060 845 #define smnreg_0x1B511060 0x1B511060 846 #define smnreg_0x1B611060 0x1B611060 847 848 #define smnreg_0x1C307120 0x1C307120 849 #define smnreg_0x1C317120 0x1C317120 850 851 #define smnreg_0x1C320830 0x1C320830 852 #define smnreg_0x1C380830 0x1C380830 853 #define smnreg_0x1C3D0830 0x1C3D0830 854 #define smnreg_0x1C420830 0x1C420830 855 856 #define smnreg_0x1C320100 0x1C320100 857 #define smnreg_0x1C380100 0x1C380100 858 #define smnreg_0x1C3D0100 0x1C3D0100 859 #define smnreg_0x1C420100 0x1C420100 860 861 #define smnreg_0x1B310500 0x1B310500 862 #define smnreg_0x1C300400 0x1C300400 863 864 #define USR_CAKE_INCR 0x11000 865 #define USR_LINK_INCR 0x100000 866 #define USR_CP_INCR 0x10000 867 868 #define NUM_USR_SMN_REGS 20 869 870 struct aqua_reg_list usr_reg_addrs[] = { 871 { smnreg_0x1B311060, 4, DW_ADDR_INCR }, 872 { smnreg_0x1B411060, 4, DW_ADDR_INCR }, 873 { smnreg_0x1B511060, 4, DW_ADDR_INCR }, 874 { smnreg_0x1B611060, 4, DW_ADDR_INCR }, 875 { smnreg_0x1C307120, 2, DW_ADDR_INCR }, 876 { smnreg_0x1C317120, 2, DW_ADDR_INCR }, 877 }; 878 879 #define NUM_USR1_SMN_REGS 46 880 struct aqua_reg_list usr1_reg_addrs[] = { 881 { smnreg_0x1C320830, 6, USR_CAKE_INCR }, 882 { smnreg_0x1C380830, 5, USR_CAKE_INCR }, 883 { smnreg_0x1C3D0830, 5, USR_CAKE_INCR }, 884 { smnreg_0x1C420830, 4, USR_CAKE_INCR }, 885 { smnreg_0x1C320100, 6, USR_CAKE_INCR }, 886 { smnreg_0x1C380100, 5, USR_CAKE_INCR }, 887 { smnreg_0x1C3D0100, 5, USR_CAKE_INCR }, 888 { smnreg_0x1C420100, 4, USR_CAKE_INCR }, 889 { smnreg_0x1B310500, 4, USR_LINK_INCR }, 890 { smnreg_0x1C300400, 2, USR_CP_INCR }, 891 }; 892 893 static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev, 894 void *buf, size_t max_size, 895 int reg_state) 896 { 897 uint32_t start_addr, incrx, num_regs, szbuf, num_smn; 898 struct amdgpu_reg_state_usr_v1_0 *usr_reg_state; 899 struct amdgpu_regs_usr_v1_0 *usr_regs; 900 struct amdgpu_smn_reg_data *reg_data; 901 const int max_usr_instances = 4; 902 struct aqua_reg_list *reg_addrs; 903 int inst = 0, i, n, r, arr_size; 904 void *p; 905 906 if (!buf || !max_size) 907 return -EINVAL; 908 909 switch (reg_state) { 910 case AMDGPU_REG_STATE_TYPE_USR: 911 arr_size = ARRAY_SIZE(usr_reg_addrs); 912 reg_addrs = usr_reg_addrs; 913 num_smn = NUM_USR_SMN_REGS; 914 break; 915 case AMDGPU_REG_STATE_TYPE_USR_1: 916 arr_size = ARRAY_SIZE(usr1_reg_addrs); 917 reg_addrs = usr1_reg_addrs; 918 num_smn = NUM_USR1_SMN_REGS; 919 break; 920 default: 921 return -EINVAL; 922 } 923 924 usr_reg_state = (struct amdgpu_reg_state_usr_v1_0 *)buf; 925 926 szbuf = sizeof(*usr_reg_state) + amdgpu_reginst_size(max_usr_instances, 927 sizeof(*usr_regs), 928 num_smn); 929 if (max_size < szbuf) 930 return -EOVERFLOW; 931 932 p = &usr_reg_state->usr_state_regs[0]; 933 for_each_inst(i, adev->aid_mask) { 934 usr_regs = (struct amdgpu_regs_usr_v1_0 *)p; 935 usr_regs->inst_header.instance = inst++; 936 usr_regs->inst_header.state = AMDGPU_INST_S_OK; 937 usr_regs->inst_header.num_smn_regs = num_smn; 938 reg_data = usr_regs->smn_reg_values; 939 940 for (r = 0; r < arr_size; r++) { 941 start_addr = reg_addrs[r].start_addr; 942 incrx = reg_addrs[r].incrx; 943 num_regs = reg_addrs[r].num_regs; 944 for (n = 0; n < num_regs; n++) { 945 aqua_read_smn_ext(adev, reg_data, 946 start_addr + n * incrx, i); 947 reg_data++; 948 } 949 } 950 p = reg_data; 951 } 952 953 usr_reg_state->common_header.structure_size = szbuf; 954 usr_reg_state->common_header.format_revision = 1; 955 usr_reg_state->common_header.content_revision = 0; 956 usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR; 957 usr_reg_state->common_header.num_instances = max_usr_instances; 958 959 return usr_reg_state->common_header.structure_size; 960 } 961 962 ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, 963 enum amdgpu_reg_state reg_state, void *buf, 964 size_t max_size) 965 { 966 ssize_t size; 967 968 switch (reg_state) { 969 case AMDGPU_REG_STATE_TYPE_PCIE: 970 size = aqua_vanjaram_read_pcie_state(adev, buf, max_size); 971 break; 972 case AMDGPU_REG_STATE_TYPE_XGMI: 973 size = aqua_vanjaram_read_xgmi_state(adev, buf, max_size); 974 break; 975 case AMDGPU_REG_STATE_TYPE_WAFL: 976 size = aqua_vanjaram_read_wafl_state(adev, buf, max_size); 977 break; 978 case AMDGPU_REG_STATE_TYPE_USR: 979 size = aqua_vanjaram_read_usr_state(adev, buf, max_size, 980 AMDGPU_REG_STATE_TYPE_USR); 981 break; 982 case AMDGPU_REG_STATE_TYPE_USR_1: 983 size = aqua_vanjaram_read_usr_state( 984 adev, buf, max_size, AMDGPU_REG_STATE_TYPE_USR_1); 985 break; 986 default: 987 return -EINVAL; 988 } 989 990 return size; 991 } 992