1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 26 #include "soc15_common.h" 27 #include "amdgpu_reg_state.h" 28 #include "amdgpu_xcp.h" 29 #include "gfx_v9_4_3.h" 30 #include "gfxhub_v1_2.h" 31 #include "sdma_v4_4_2.h" 32 33 #define XCP_INST_MASK(num_inst, xcp_id) \ 34 (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0) 35 36 #define AMDGPU_XCP_OPS_KFD (1 << 0) 37 38 void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) 39 { 40 int i; 41 42 adev->doorbell_index.kiq = AMDGPU_DOORBELL_LAYOUT1_KIQ_START; 43 44 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START; 45 46 adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START; 47 adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END; 48 adev->doorbell_index.xcc_doorbell_range = AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE; 49 50 adev->doorbell_index.sdma_doorbell_range = 20; 51 for (i = 0; i < adev->sdma.num_instances; i++) 52 adev->doorbell_index.sdma_engine[i] = 53 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START + 54 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 55 56 adev->doorbell_index.ih = AMDGPU_DOORBELL_LAYOUT1_IH; 57 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL_LAYOUT1_VCN_START; 58 59 adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP; 60 adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP; 61 62 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1; 63 } 64 65 static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev) 66 { 67 return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst); 68 } 69 70 static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, 71 uint32_t inst_idx, struct amdgpu_ring *ring) 72 { 73 int xcp_id; 74 enum AMDGPU_XCP_IP_BLOCK ip_blk; 75 uint32_t inst_mask; 76 77 ring->xcp_id = AMDGPU_XCP_NO_PARTITION; 78 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE) 79 return; 80 81 inst_mask = 1 << inst_idx; 82 83 switch (ring->funcs->type) { 84 case AMDGPU_HW_IP_GFX: 85 case AMDGPU_RING_TYPE_COMPUTE: 86 case AMDGPU_RING_TYPE_KIQ: 87 ip_blk = AMDGPU_XCP_GFX; 88 break; 89 case AMDGPU_RING_TYPE_SDMA: 90 ip_blk = AMDGPU_XCP_SDMA; 91 break; 92 case AMDGPU_RING_TYPE_VCN_ENC: 93 case AMDGPU_RING_TYPE_VCN_JPEG: 94 ip_blk = AMDGPU_XCP_VCN; 95 if (aqua_vanjaram_xcp_vcn_shared(adev)) 96 inst_mask = 1 << (inst_idx * 2); 97 break; 98 default: 99 DRM_ERROR("Not support ring type %d!", ring->funcs->type); 100 return; 101 } 102 103 for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) { 104 if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { 105 ring->xcp_id = xcp_id; 106 break; 107 } 108 } 109 } 110 111 static void aqua_vanjaram_xcp_gpu_sched_update( 112 struct amdgpu_device *adev, 113 struct amdgpu_ring *ring, 114 unsigned int sel_xcp_id) 115 { 116 unsigned int *num_gpu_sched; 117 118 num_gpu_sched = &adev->xcp_mgr->xcp[sel_xcp_id] 119 .gpu_sched[ring->funcs->type][ring->hw_prio].num_scheds; 120 adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[ring->funcs->type][ring->hw_prio] 121 .sched[(*num_gpu_sched)++] = &ring->sched; 122 DRM_DEBUG("%s :[%d] gpu_sched[%d][%d] = %d", ring->name, 123 sel_xcp_id, ring->funcs->type, 124 ring->hw_prio, *num_gpu_sched); 125 } 126 127 static int aqua_vanjaram_xcp_sched_list_update( 128 struct amdgpu_device *adev) 129 { 130 struct amdgpu_ring *ring; 131 int i; 132 133 for (i = 0; i < MAX_XCP; i++) { 134 atomic_set(&adev->xcp_mgr->xcp[i].ref_cnt, 0); 135 memset(adev->xcp_mgr->xcp[i].gpu_sched, 0, sizeof(adev->xcp_mgr->xcp->gpu_sched)); 136 } 137 138 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE) 139 return 0; 140 141 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 142 ring = adev->rings[i]; 143 if (!ring || !ring->sched.ready || ring->no_scheduler) 144 continue; 145 146 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id); 147 148 /* VCN may be shared by two partitions under CPX MODE in certain 149 * configs. 150 */ 151 if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC || 152 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) && 153 aqua_vanjaram_xcp_vcn_shared(adev)) 154 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1); 155 } 156 157 return 0; 158 } 159 160 static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev) 161 { 162 int i; 163 164 for (i = 0; i < adev->num_rings; i++) { 165 struct amdgpu_ring *ring = adev->rings[i]; 166 167 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE || 168 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 169 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring); 170 else 171 aqua_vanjaram_set_xcp_id(adev, ring->me, ring); 172 } 173 174 return aqua_vanjaram_xcp_sched_list_update(adev); 175 } 176 177 static int aqua_vanjaram_select_scheds( 178 struct amdgpu_device *adev, 179 u32 hw_ip, 180 u32 hw_prio, 181 struct amdgpu_fpriv *fpriv, 182 unsigned int *num_scheds, 183 struct drm_gpu_scheduler ***scheds) 184 { 185 u32 sel_xcp_id; 186 int i; 187 188 if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) { 189 u32 least_ref_cnt = ~0; 190 191 fpriv->xcp_id = 0; 192 for (i = 0; i < adev->xcp_mgr->num_xcps; i++) { 193 u32 total_ref_cnt; 194 195 total_ref_cnt = atomic_read(&adev->xcp_mgr->xcp[i].ref_cnt); 196 if (total_ref_cnt < least_ref_cnt) { 197 fpriv->xcp_id = i; 198 least_ref_cnt = total_ref_cnt; 199 } 200 } 201 } 202 sel_xcp_id = fpriv->xcp_id; 203 204 if (adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) { 205 *num_scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds; 206 *scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].sched; 207 atomic_inc(&adev->xcp_mgr->xcp[sel_xcp_id].ref_cnt); 208 DRM_DEBUG("Selected partition #%d", sel_xcp_id); 209 } else { 210 DRM_ERROR("Failed to schedule partition #%d.", sel_xcp_id); 211 return -ENOENT; 212 } 213 214 return 0; 215 } 216 217 static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev, 218 enum amd_hw_ip_block_type block, 219 int8_t inst) 220 { 221 int8_t dev_inst; 222 223 switch (block) { 224 case GC_HWIP: 225 case SDMA0_HWIP: 226 /* Both JPEG and VCN as JPEG is only alias of VCN */ 227 case VCN_HWIP: 228 dev_inst = adev->ip_map.dev_inst[block][inst]; 229 break; 230 default: 231 /* For rest of the IPs, no look up required. 232 * Assume 'logical instance == physical instance' for all configs. */ 233 dev_inst = inst; 234 break; 235 } 236 237 return dev_inst; 238 } 239 240 static uint32_t aqua_vanjaram_logical_to_dev_mask(struct amdgpu_device *adev, 241 enum amd_hw_ip_block_type block, 242 uint32_t mask) 243 { 244 uint32_t dev_mask = 0; 245 int8_t log_inst, dev_inst; 246 247 while (mask) { 248 log_inst = ffs(mask) - 1; 249 dev_inst = aqua_vanjaram_logical_to_dev_inst(adev, block, log_inst); 250 dev_mask |= (1 << dev_inst); 251 mask &= ~(1 << log_inst); 252 } 253 254 return dev_mask; 255 } 256 257 static void aqua_vanjaram_populate_ip_map(struct amdgpu_device *adev, 258 enum amd_hw_ip_block_type ip_block, 259 uint32_t inst_mask) 260 { 261 int l = 0, i; 262 263 while (inst_mask) { 264 i = ffs(inst_mask) - 1; 265 adev->ip_map.dev_inst[ip_block][l++] = i; 266 inst_mask &= ~(1 << i); 267 } 268 for (; l < HWIP_MAX_INSTANCE; l++) 269 adev->ip_map.dev_inst[ip_block][l] = -1; 270 } 271 272 void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev) 273 { 274 u32 ip_map[][2] = { 275 { GC_HWIP, adev->gfx.xcc_mask }, 276 { SDMA0_HWIP, adev->sdma.sdma_mask }, 277 { VCN_HWIP, adev->vcn.inst_mask }, 278 }; 279 int i; 280 281 for (i = 0; i < ARRAY_SIZE(ip_map); ++i) 282 aqua_vanjaram_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]); 283 284 adev->ip_map.logical_to_dev_inst = aqua_vanjaram_logical_to_dev_inst; 285 adev->ip_map.logical_to_dev_mask = aqua_vanjaram_logical_to_dev_mask; 286 } 287 288 /* Fixed pattern for smn addressing on different AIDs: 289 * bit[34]: indicate cross AID access 290 * bit[33:32]: indicate target AID id 291 * AID id range is 0 ~ 3 as maximum AID number is 4. 292 */ 293 u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id) 294 { 295 u64 ext_offset; 296 297 /* local routing and bit[34:32] will be zeros */ 298 if (ext_id == 0) 299 return 0; 300 301 /* Initiated from host, accessing to all non-zero aids are cross traffic */ 302 ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34); 303 304 return ext_offset; 305 } 306 307 static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 308 { 309 enum amdgpu_gfx_partition mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 310 struct amdgpu_device *adev = xcp_mgr->adev; 311 312 if (adev->nbio.funcs->get_compute_partition_mode) 313 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 314 315 return mode; 316 } 317 318 static int __aqua_vanjaram_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 319 { 320 int num_xcc, num_xcc_per_xcp = 0; 321 322 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 323 324 switch (mode) { 325 case AMDGPU_SPX_PARTITION_MODE: 326 num_xcc_per_xcp = num_xcc; 327 break; 328 case AMDGPU_DPX_PARTITION_MODE: 329 num_xcc_per_xcp = num_xcc / 2; 330 break; 331 case AMDGPU_TPX_PARTITION_MODE: 332 num_xcc_per_xcp = num_xcc / 3; 333 break; 334 case AMDGPU_QPX_PARTITION_MODE: 335 num_xcc_per_xcp = num_xcc / 4; 336 break; 337 case AMDGPU_CPX_PARTITION_MODE: 338 num_xcc_per_xcp = 1; 339 break; 340 } 341 342 return num_xcc_per_xcp; 343 } 344 345 static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 346 enum AMDGPU_XCP_IP_BLOCK ip_id, 347 struct amdgpu_xcp_ip *ip) 348 { 349 struct amdgpu_device *adev = xcp_mgr->adev; 350 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 351 int num_sdma, num_vcn; 352 353 num_sdma = adev->sdma.num_instances; 354 num_vcn = adev->vcn.num_vcn_inst; 355 356 switch (xcp_mgr->mode) { 357 case AMDGPU_SPX_PARTITION_MODE: 358 num_sdma_xcp = num_sdma; 359 num_vcn_xcp = num_vcn; 360 break; 361 case AMDGPU_DPX_PARTITION_MODE: 362 num_sdma_xcp = num_sdma / 2; 363 num_vcn_xcp = num_vcn / 2; 364 break; 365 case AMDGPU_TPX_PARTITION_MODE: 366 num_sdma_xcp = num_sdma / 3; 367 num_vcn_xcp = num_vcn / 3; 368 break; 369 case AMDGPU_QPX_PARTITION_MODE: 370 num_sdma_xcp = num_sdma / 4; 371 num_vcn_xcp = num_vcn / 4; 372 break; 373 case AMDGPU_CPX_PARTITION_MODE: 374 num_sdma_xcp = 2; 375 num_vcn_xcp = num_vcn ? 1 : 0; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 382 383 switch (ip_id) { 384 case AMDGPU_XCP_GFXHUB: 385 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 386 ip->ip_funcs = &gfxhub_v1_2_xcp_funcs; 387 break; 388 case AMDGPU_XCP_GFX: 389 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 390 ip->ip_funcs = &gfx_v9_4_3_xcp_funcs; 391 break; 392 case AMDGPU_XCP_SDMA: 393 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 394 ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; 395 break; 396 case AMDGPU_XCP_VCN: 397 ip->inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id); 398 /* TODO : Assign IP funcs */ 399 break; 400 default: 401 return -EINVAL; 402 } 403 404 ip->ip_id = ip_id; 405 406 return 0; 407 } 408 409 static enum amdgpu_gfx_partition 410 __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 411 { 412 struct amdgpu_device *adev = xcp_mgr->adev; 413 int num_xcc; 414 415 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 416 417 if (adev->gmc.num_mem_partitions == 1) 418 return AMDGPU_SPX_PARTITION_MODE; 419 420 if (adev->gmc.num_mem_partitions == num_xcc) 421 return AMDGPU_CPX_PARTITION_MODE; 422 423 if (adev->gmc.num_mem_partitions == num_xcc / 2) 424 return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE : 425 AMDGPU_CPX_PARTITION_MODE; 426 427 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) 428 return AMDGPU_DPX_PARTITION_MODE; 429 430 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 431 } 432 433 static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 434 enum amdgpu_gfx_partition mode) 435 { 436 struct amdgpu_device *adev = xcp_mgr->adev; 437 int num_xcc, num_xccs_per_xcp; 438 439 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 440 switch (mode) { 441 case AMDGPU_SPX_PARTITION_MODE: 442 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 443 case AMDGPU_DPX_PARTITION_MODE: 444 return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0; 445 case AMDGPU_TPX_PARTITION_MODE: 446 return (adev->gmc.num_mem_partitions == 1 || 447 adev->gmc.num_mem_partitions == 3) && 448 ((num_xcc % 3) == 0); 449 case AMDGPU_QPX_PARTITION_MODE: 450 num_xccs_per_xcp = num_xcc / 4; 451 return (adev->gmc.num_mem_partitions == 1 || 452 adev->gmc.num_mem_partitions == 4) && 453 (num_xccs_per_xcp >= 2); 454 case AMDGPU_CPX_PARTITION_MODE: 455 return ((num_xcc > 1) && 456 (adev->gmc.num_mem_partitions == 1 || adev->gmc.num_mem_partitions == 4) && 457 (num_xcc % adev->gmc.num_mem_partitions) == 0); 458 default: 459 return false; 460 } 461 462 return false; 463 } 464 465 static int __aqua_vanjaram_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags) 466 { 467 /* TODO: 468 * Stop user queues and threads, and make sure GPU is empty of work. 469 */ 470 471 if (flags & AMDGPU_XCP_OPS_KFD) 472 amdgpu_amdkfd_device_fini_sw(xcp_mgr->adev); 473 474 return 0; 475 } 476 477 static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags) 478 { 479 int ret = 0; 480 481 if (flags & AMDGPU_XCP_OPS_KFD) { 482 amdgpu_amdkfd_device_probe(xcp_mgr->adev); 483 amdgpu_amdkfd_device_init(xcp_mgr->adev); 484 /* If KFD init failed, return failure */ 485 if (!xcp_mgr->adev->kfd.init_complete) 486 ret = -EIO; 487 } 488 489 return ret; 490 } 491 492 static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 493 int mode, int *num_xcps) 494 { 495 int num_xcc_per_xcp, num_xcc, ret; 496 struct amdgpu_device *adev; 497 u32 flags = 0; 498 499 adev = xcp_mgr->adev; 500 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 501 502 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 503 mode = __aqua_vanjaram_get_auto_mode(xcp_mgr); 504 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 505 dev_err(adev->dev, 506 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 507 adev->gmc.num_mem_partitions); 508 return -EINVAL; 509 } 510 } else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) { 511 dev_err(adev->dev, 512 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 513 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 514 return -EINVAL; 515 } 516 517 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 518 flags |= AMDGPU_XCP_OPS_KFD; 519 520 if (flags & AMDGPU_XCP_OPS_KFD) { 521 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 522 if (ret) 523 goto out; 524 } 525 526 ret = __aqua_vanjaram_pre_partition_switch(xcp_mgr, flags); 527 if (ret) 528 goto unlock; 529 530 num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, mode); 531 if (adev->gfx.funcs->switch_partition_mode) 532 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, 533 num_xcc_per_xcp); 534 535 /* Init info about new xcps */ 536 *num_xcps = num_xcc / num_xcc_per_xcp; 537 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 538 539 ret = __aqua_vanjaram_post_partition_switch(xcp_mgr, flags); 540 unlock: 541 if (flags & AMDGPU_XCP_OPS_KFD) 542 amdgpu_amdkfd_unlock_kfd(adev); 543 out: 544 return ret; 545 } 546 547 static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev, 548 int xcc_id, uint8_t *mem_id) 549 { 550 /* memory/spatial modes validation check is already done */ 551 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 552 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 553 554 return 0; 555 } 556 557 static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 558 struct amdgpu_xcp *xcp, uint8_t *mem_id) 559 { 560 struct amdgpu_numa_info numa_info; 561 struct amdgpu_device *adev; 562 uint32_t xcc_mask; 563 int r, i, xcc_id; 564 565 adev = xcp_mgr->adev; 566 /* TODO: BIOS is not returning the right info now 567 * Check on this later 568 */ 569 /* 570 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 571 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 572 */ 573 if (adev->gmc.num_mem_partitions == 1) { 574 /* Only one range */ 575 *mem_id = 0; 576 return 0; 577 } 578 579 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 580 if (r || !xcc_mask) 581 return -EINVAL; 582 583 xcc_id = ffs(xcc_mask) - 1; 584 if (!adev->gmc.is_app_apu) 585 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); 586 587 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 588 589 if (r) 590 return r; 591 592 r = -EINVAL; 593 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 594 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 595 *mem_id = i; 596 r = 0; 597 break; 598 } 599 } 600 601 return r; 602 } 603 604 static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 605 enum AMDGPU_XCP_IP_BLOCK ip_id, 606 struct amdgpu_xcp_ip *ip) 607 { 608 if (!ip) 609 return -EINVAL; 610 611 return __aqua_vanjaram_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 612 } 613 614 struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = { 615 .switch_partition_mode = &aqua_vanjaram_switch_partition_mode, 616 .query_partition_mode = &aqua_vanjaram_query_partition_mode, 617 .get_ip_details = &aqua_vanjaram_get_xcp_ip_details, 618 .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id, 619 .select_scheds = &aqua_vanjaram_select_scheds, 620 .update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list 621 }; 622 623 static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) 624 { 625 int ret; 626 627 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 1, 628 &aqua_vanjaram_xcp_funcs); 629 if (ret) 630 return ret; 631 632 /* TODO: Default memory node affinity init */ 633 634 return ret; 635 } 636 637 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev) 638 { 639 u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask; 640 int ret, i; 641 642 /* generally 1 AID supports 4 instances */ 643 adev->sdma.num_inst_per_aid = 4; 644 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask); 645 646 adev->aid_mask = i = 1; 647 inst_mask >>= adev->sdma.num_inst_per_aid; 648 649 for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask; 650 inst_mask >>= adev->sdma.num_inst_per_aid, ++i) { 651 avail_inst = inst_mask & mask; 652 if (avail_inst == mask || avail_inst == 0x3 || 653 avail_inst == 0xc) 654 adev->aid_mask |= (1 << i); 655 } 656 657 /* Harvest config is not used for aqua vanjaram. VCN and JPEGs will be 658 * addressed based on logical instance ids. 659 */ 660 adev->vcn.harvest_config = 0; 661 adev->vcn.num_inst_per_aid = 1; 662 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); 663 adev->jpeg.harvest_config = 0; 664 adev->jpeg.num_inst_per_aid = 1; 665 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask); 666 667 ret = aqua_vanjaram_xcp_mgr_init(adev); 668 if (ret) 669 return ret; 670 671 aqua_vanjaram_ip_map_init(adev); 672 673 return 0; 674 } 675 676 static void aqua_read_smn(struct amdgpu_device *adev, 677 struct amdgpu_smn_reg_data *regdata, 678 uint64_t smn_addr) 679 { 680 regdata->addr = smn_addr; 681 regdata->value = RREG32_PCIE(smn_addr); 682 } 683 684 struct aqua_reg_list { 685 uint64_t start_addr; 686 uint32_t num_regs; 687 uint32_t incrx; 688 }; 689 690 #define DW_ADDR_INCR 4 691 692 static void aqua_read_smn_ext(struct amdgpu_device *adev, 693 struct amdgpu_smn_reg_data *regdata, 694 uint64_t smn_addr, int i) 695 { 696 regdata->addr = 697 smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i); 698 regdata->value = RREG32_PCIE_EXT(regdata->addr); 699 } 700 701 #define smnreg_0x1A340218 0x1A340218 702 #define smnreg_0x1A3402E4 0x1A3402E4 703 #define smnreg_0x1A340294 0x1A340294 704 #define smreg_0x1A380088 0x1A380088 705 706 #define NUM_PCIE_SMN_REGS 14 707 708 static struct aqua_reg_list pcie_reg_addrs[] = { 709 { smnreg_0x1A340218, 1, 0 }, 710 { smnreg_0x1A3402E4, 1, 0 }, 711 { smnreg_0x1A340294, 6, DW_ADDR_INCR }, 712 { smreg_0x1A380088, 6, DW_ADDR_INCR }, 713 }; 714 715 static ssize_t aqua_vanjaram_read_pcie_state(struct amdgpu_device *adev, 716 void *buf, size_t max_size) 717 { 718 struct amdgpu_reg_state_pcie_v1_0 *pcie_reg_state; 719 uint32_t start_addr, incrx, num_regs, szbuf; 720 struct amdgpu_regs_pcie_v1_0 *pcie_regs; 721 struct amdgpu_smn_reg_data *reg_data; 722 struct pci_dev *us_pdev, *ds_pdev; 723 int aer_cap, r, n; 724 725 if (!buf || !max_size) 726 return -EINVAL; 727 728 pcie_reg_state = (struct amdgpu_reg_state_pcie_v1_0 *)buf; 729 730 szbuf = sizeof(*pcie_reg_state) + 731 amdgpu_reginst_size(1, sizeof(*pcie_regs), NUM_PCIE_SMN_REGS); 732 /* Only one instance of pcie regs */ 733 if (max_size < szbuf) 734 return -EOVERFLOW; 735 736 pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf + 737 sizeof(*pcie_reg_state)); 738 pcie_regs->inst_header.instance = 0; 739 pcie_regs->inst_header.state = AMDGPU_INST_S_OK; 740 pcie_regs->inst_header.num_smn_regs = NUM_PCIE_SMN_REGS; 741 742 reg_data = pcie_regs->smn_reg_values; 743 744 for (r = 0; r < ARRAY_SIZE(pcie_reg_addrs); r++) { 745 start_addr = pcie_reg_addrs[r].start_addr; 746 incrx = pcie_reg_addrs[r].incrx; 747 num_regs = pcie_reg_addrs[r].num_regs; 748 for (n = 0; n < num_regs; n++) { 749 aqua_read_smn(adev, reg_data, start_addr + n * incrx); 750 ++reg_data; 751 } 752 } 753 754 ds_pdev = pci_upstream_bridge(adev->pdev); 755 us_pdev = pci_upstream_bridge(ds_pdev); 756 757 pcie_capability_read_word(us_pdev, PCI_EXP_DEVSTA, 758 &pcie_regs->device_status); 759 pcie_capability_read_word(us_pdev, PCI_EXP_LNKSTA, 760 &pcie_regs->link_status); 761 762 aer_cap = pci_find_ext_capability(us_pdev, PCI_EXT_CAP_ID_ERR); 763 if (aer_cap) { 764 pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_COR_STATUS, 765 &pcie_regs->pcie_corr_err_status); 766 pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_UNCOR_STATUS, 767 &pcie_regs->pcie_uncorr_err_status); 768 } 769 770 pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS, 771 &pcie_regs->sub_bus_number_latency); 772 773 pcie_reg_state->common_header.structure_size = szbuf; 774 pcie_reg_state->common_header.format_revision = 1; 775 pcie_reg_state->common_header.content_revision = 0; 776 pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE; 777 pcie_reg_state->common_header.num_instances = 1; 778 779 return pcie_reg_state->common_header.structure_size; 780 } 781 782 #define smnreg_0x11A00050 0x11A00050 783 #define smnreg_0x11A00180 0x11A00180 784 #define smnreg_0x11A00070 0x11A00070 785 #define smnreg_0x11A00200 0x11A00200 786 #define smnreg_0x11A0020C 0x11A0020C 787 #define smnreg_0x11A00210 0x11A00210 788 #define smnreg_0x11A00108 0x11A00108 789 790 #define XGMI_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 791 792 #define NUM_XGMI_SMN_REGS 25 793 794 static struct aqua_reg_list xgmi_reg_addrs[] = { 795 { smnreg_0x11A00050, 1, 0 }, 796 { smnreg_0x11A00180, 16, DW_ADDR_INCR }, 797 { smnreg_0x11A00070, 4, DW_ADDR_INCR }, 798 { smnreg_0x11A00200, 1, 0 }, 799 { smnreg_0x11A0020C, 1, 0 }, 800 { smnreg_0x11A00210, 1, 0 }, 801 { smnreg_0x11A00108, 1, 0 }, 802 }; 803 804 static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev, 805 void *buf, size_t max_size) 806 { 807 struct amdgpu_reg_state_xgmi_v1_0 *xgmi_reg_state; 808 uint32_t start_addr, incrx, num_regs, szbuf; 809 struct amdgpu_regs_xgmi_v1_0 *xgmi_regs; 810 struct amdgpu_smn_reg_data *reg_data; 811 const int max_xgmi_instances = 8; 812 int inst = 0, i, j, r, n; 813 const int xgmi_inst = 2; 814 void *p; 815 816 if (!buf || !max_size) 817 return -EINVAL; 818 819 xgmi_reg_state = (struct amdgpu_reg_state_xgmi_v1_0 *)buf; 820 821 szbuf = sizeof(*xgmi_reg_state) + 822 amdgpu_reginst_size(max_xgmi_instances, sizeof(*xgmi_regs), 823 NUM_XGMI_SMN_REGS); 824 /* Only one instance of pcie regs */ 825 if (max_size < szbuf) 826 return -EOVERFLOW; 827 828 p = &xgmi_reg_state->xgmi_state_regs[0]; 829 for_each_inst(i, adev->aid_mask) { 830 for (j = 0; j < xgmi_inst; ++j) { 831 xgmi_regs = (struct amdgpu_regs_xgmi_v1_0 *)p; 832 xgmi_regs->inst_header.instance = inst++; 833 834 xgmi_regs->inst_header.state = AMDGPU_INST_S_OK; 835 xgmi_regs->inst_header.num_smn_regs = NUM_XGMI_SMN_REGS; 836 837 reg_data = xgmi_regs->smn_reg_values; 838 839 for (r = 0; r < ARRAY_SIZE(xgmi_reg_addrs); r++) { 840 start_addr = xgmi_reg_addrs[r].start_addr; 841 incrx = xgmi_reg_addrs[r].incrx; 842 num_regs = xgmi_reg_addrs[r].num_regs; 843 844 for (n = 0; n < num_regs; n++) { 845 aqua_read_smn_ext( 846 adev, reg_data, 847 XGMI_LINK_REG(start_addr, j) + 848 n * incrx, 849 i); 850 ++reg_data; 851 } 852 } 853 p = reg_data; 854 } 855 } 856 857 xgmi_reg_state->common_header.structure_size = szbuf; 858 xgmi_reg_state->common_header.format_revision = 1; 859 xgmi_reg_state->common_header.content_revision = 0; 860 xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI; 861 xgmi_reg_state->common_header.num_instances = max_xgmi_instances; 862 863 return xgmi_reg_state->common_header.structure_size; 864 } 865 866 #define smnreg_0x11C00070 0x11C00070 867 #define smnreg_0x11C00210 0x11C00210 868 869 static struct aqua_reg_list wafl_reg_addrs[] = { 870 { smnreg_0x11C00070, 4, DW_ADDR_INCR }, 871 { smnreg_0x11C00210, 1, 0 }, 872 }; 873 874 #define WAFL_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 875 876 #define NUM_WAFL_SMN_REGS 5 877 878 static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev, 879 void *buf, size_t max_size) 880 { 881 struct amdgpu_reg_state_wafl_v1_0 *wafl_reg_state; 882 uint32_t start_addr, incrx, num_regs, szbuf; 883 struct amdgpu_regs_wafl_v1_0 *wafl_regs; 884 struct amdgpu_smn_reg_data *reg_data; 885 const int max_wafl_instances = 8; 886 int inst = 0, i, j, r, n; 887 const int wafl_inst = 2; 888 void *p; 889 890 if (!buf || !max_size) 891 return -EINVAL; 892 893 wafl_reg_state = (struct amdgpu_reg_state_wafl_v1_0 *)buf; 894 895 szbuf = sizeof(*wafl_reg_state) + 896 amdgpu_reginst_size(max_wafl_instances, sizeof(*wafl_regs), 897 NUM_WAFL_SMN_REGS); 898 899 if (max_size < szbuf) 900 return -EOVERFLOW; 901 902 p = &wafl_reg_state->wafl_state_regs[0]; 903 for_each_inst(i, adev->aid_mask) { 904 for (j = 0; j < wafl_inst; ++j) { 905 wafl_regs = (struct amdgpu_regs_wafl_v1_0 *)p; 906 wafl_regs->inst_header.instance = inst++; 907 908 wafl_regs->inst_header.state = AMDGPU_INST_S_OK; 909 wafl_regs->inst_header.num_smn_regs = NUM_WAFL_SMN_REGS; 910 911 reg_data = wafl_regs->smn_reg_values; 912 913 for (r = 0; r < ARRAY_SIZE(wafl_reg_addrs); r++) { 914 start_addr = wafl_reg_addrs[r].start_addr; 915 incrx = wafl_reg_addrs[r].incrx; 916 num_regs = wafl_reg_addrs[r].num_regs; 917 for (n = 0; n < num_regs; n++) { 918 aqua_read_smn_ext( 919 adev, reg_data, 920 WAFL_LINK_REG(start_addr, j) + 921 n * incrx, 922 i); 923 ++reg_data; 924 } 925 } 926 p = reg_data; 927 } 928 } 929 930 wafl_reg_state->common_header.structure_size = szbuf; 931 wafl_reg_state->common_header.format_revision = 1; 932 wafl_reg_state->common_header.content_revision = 0; 933 wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL; 934 wafl_reg_state->common_header.num_instances = max_wafl_instances; 935 936 return wafl_reg_state->common_header.structure_size; 937 } 938 939 #define smnreg_0x1B311060 0x1B311060 940 #define smnreg_0x1B411060 0x1B411060 941 #define smnreg_0x1B511060 0x1B511060 942 #define smnreg_0x1B611060 0x1B611060 943 944 #define smnreg_0x1C307120 0x1C307120 945 #define smnreg_0x1C317120 0x1C317120 946 947 #define smnreg_0x1C320830 0x1C320830 948 #define smnreg_0x1C380830 0x1C380830 949 #define smnreg_0x1C3D0830 0x1C3D0830 950 #define smnreg_0x1C420830 0x1C420830 951 952 #define smnreg_0x1C320100 0x1C320100 953 #define smnreg_0x1C380100 0x1C380100 954 #define smnreg_0x1C3D0100 0x1C3D0100 955 #define smnreg_0x1C420100 0x1C420100 956 957 #define smnreg_0x1B310500 0x1B310500 958 #define smnreg_0x1C300400 0x1C300400 959 960 #define USR_CAKE_INCR 0x11000 961 #define USR_LINK_INCR 0x100000 962 #define USR_CP_INCR 0x10000 963 964 #define NUM_USR_SMN_REGS 20 965 966 struct aqua_reg_list usr_reg_addrs[] = { 967 { smnreg_0x1B311060, 4, DW_ADDR_INCR }, 968 { smnreg_0x1B411060, 4, DW_ADDR_INCR }, 969 { smnreg_0x1B511060, 4, DW_ADDR_INCR }, 970 { smnreg_0x1B611060, 4, DW_ADDR_INCR }, 971 { smnreg_0x1C307120, 2, DW_ADDR_INCR }, 972 { smnreg_0x1C317120, 2, DW_ADDR_INCR }, 973 }; 974 975 #define NUM_USR1_SMN_REGS 46 976 struct aqua_reg_list usr1_reg_addrs[] = { 977 { smnreg_0x1C320830, 6, USR_CAKE_INCR }, 978 { smnreg_0x1C380830, 5, USR_CAKE_INCR }, 979 { smnreg_0x1C3D0830, 5, USR_CAKE_INCR }, 980 { smnreg_0x1C420830, 4, USR_CAKE_INCR }, 981 { smnreg_0x1C320100, 6, USR_CAKE_INCR }, 982 { smnreg_0x1C380100, 5, USR_CAKE_INCR }, 983 { smnreg_0x1C3D0100, 5, USR_CAKE_INCR }, 984 { smnreg_0x1C420100, 4, USR_CAKE_INCR }, 985 { smnreg_0x1B310500, 4, USR_LINK_INCR }, 986 { smnreg_0x1C300400, 2, USR_CP_INCR }, 987 }; 988 989 static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev, 990 void *buf, size_t max_size, 991 int reg_state) 992 { 993 uint32_t start_addr, incrx, num_regs, szbuf, num_smn; 994 struct amdgpu_reg_state_usr_v1_0 *usr_reg_state; 995 struct amdgpu_regs_usr_v1_0 *usr_regs; 996 struct amdgpu_smn_reg_data *reg_data; 997 const int max_usr_instances = 4; 998 struct aqua_reg_list *reg_addrs; 999 int inst = 0, i, n, r, arr_size; 1000 void *p; 1001 1002 if (!buf || !max_size) 1003 return -EINVAL; 1004 1005 switch (reg_state) { 1006 case AMDGPU_REG_STATE_TYPE_USR: 1007 arr_size = ARRAY_SIZE(usr_reg_addrs); 1008 reg_addrs = usr_reg_addrs; 1009 num_smn = NUM_USR_SMN_REGS; 1010 break; 1011 case AMDGPU_REG_STATE_TYPE_USR_1: 1012 arr_size = ARRAY_SIZE(usr1_reg_addrs); 1013 reg_addrs = usr1_reg_addrs; 1014 num_smn = NUM_USR1_SMN_REGS; 1015 break; 1016 default: 1017 return -EINVAL; 1018 } 1019 1020 usr_reg_state = (struct amdgpu_reg_state_usr_v1_0 *)buf; 1021 1022 szbuf = sizeof(*usr_reg_state) + amdgpu_reginst_size(max_usr_instances, 1023 sizeof(*usr_regs), 1024 num_smn); 1025 if (max_size < szbuf) 1026 return -EOVERFLOW; 1027 1028 p = &usr_reg_state->usr_state_regs[0]; 1029 for_each_inst(i, adev->aid_mask) { 1030 usr_regs = (struct amdgpu_regs_usr_v1_0 *)p; 1031 usr_regs->inst_header.instance = inst++; 1032 usr_regs->inst_header.state = AMDGPU_INST_S_OK; 1033 usr_regs->inst_header.num_smn_regs = num_smn; 1034 reg_data = usr_regs->smn_reg_values; 1035 1036 for (r = 0; r < arr_size; r++) { 1037 start_addr = reg_addrs[r].start_addr; 1038 incrx = reg_addrs[r].incrx; 1039 num_regs = reg_addrs[r].num_regs; 1040 for (n = 0; n < num_regs; n++) { 1041 aqua_read_smn_ext(adev, reg_data, 1042 start_addr + n * incrx, i); 1043 reg_data++; 1044 } 1045 } 1046 p = reg_data; 1047 } 1048 1049 usr_reg_state->common_header.structure_size = szbuf; 1050 usr_reg_state->common_header.format_revision = 1; 1051 usr_reg_state->common_header.content_revision = 0; 1052 usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR; 1053 usr_reg_state->common_header.num_instances = max_usr_instances; 1054 1055 return usr_reg_state->common_header.structure_size; 1056 } 1057 1058 ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, 1059 enum amdgpu_reg_state reg_state, void *buf, 1060 size_t max_size) 1061 { 1062 ssize_t size; 1063 1064 switch (reg_state) { 1065 case AMDGPU_REG_STATE_TYPE_PCIE: 1066 size = aqua_vanjaram_read_pcie_state(adev, buf, max_size); 1067 break; 1068 case AMDGPU_REG_STATE_TYPE_XGMI: 1069 size = aqua_vanjaram_read_xgmi_state(adev, buf, max_size); 1070 break; 1071 case AMDGPU_REG_STATE_TYPE_WAFL: 1072 size = aqua_vanjaram_read_wafl_state(adev, buf, max_size); 1073 break; 1074 case AMDGPU_REG_STATE_TYPE_USR: 1075 size = aqua_vanjaram_read_usr_state(adev, buf, max_size, 1076 AMDGPU_REG_STATE_TYPE_USR); 1077 break; 1078 case AMDGPU_REG_STATE_TYPE_USR_1: 1079 size = aqua_vanjaram_read_usr_state( 1080 adev, buf, max_size, AMDGPU_REG_STATE_TYPE_USR_1); 1081 break; 1082 default: 1083 return -EINVAL; 1084 } 1085 1086 return size; 1087 } 1088