1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 26 #include "soc15_common.h" 27 #include "amdgpu_reg_state.h" 28 #include "amdgpu_xcp.h" 29 #include "gfx_v9_4_3.h" 30 #include "gfxhub_v1_2.h" 31 #include "sdma_v4_4_2.h" 32 #include "amdgpu_ip.h" 33 34 #define XCP_INST_MASK(num_inst, xcp_id) \ 35 (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0) 36 37 void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) 38 { 39 int i; 40 41 adev->doorbell_index.kiq = AMDGPU_DOORBELL_LAYOUT1_KIQ_START; 42 43 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START; 44 45 adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START; 46 adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END; 47 adev->doorbell_index.xcc_doorbell_range = AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE; 48 49 adev->doorbell_index.sdma_doorbell_range = 20; 50 for (i = 0; i < adev->sdma.num_instances; i++) 51 adev->doorbell_index.sdma_engine[i] = 52 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START + 53 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 54 55 adev->doorbell_index.ih = AMDGPU_DOORBELL_LAYOUT1_IH; 56 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL_LAYOUT1_VCN_START; 57 58 adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP; 59 adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP; 60 61 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1; 62 } 63 64 /* Fixed pattern for smn addressing on different AIDs: 65 * bit[34]: indicate cross AID access 66 * bit[33:32]: indicate target AID id 67 * AID id range is 0 ~ 3 as maximum AID number is 4. 68 */ 69 u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id) 70 { 71 u64 ext_offset; 72 73 /* local routing and bit[34:32] will be zeros */ 74 if (ext_id == 0) 75 return 0; 76 77 /* Initiated from host, accessing to all non-zero aids are cross traffic */ 78 ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34); 79 80 return ext_offset; 81 } 82 83 static enum amdgpu_gfx_partition 84 __aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 85 { 86 struct amdgpu_device *adev = xcp_mgr->adev; 87 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 88 89 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 90 if (adev->gfx.funcs->get_xccs_per_xcp) 91 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 92 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 93 mode = num_xcc / num_xcc_per_xcp; 94 95 if (num_xcc_per_xcp == 1) 96 return AMDGPU_CPX_PARTITION_MODE; 97 98 switch (mode) { 99 case 1: 100 return AMDGPU_SPX_PARTITION_MODE; 101 case 2: 102 return AMDGPU_DPX_PARTITION_MODE; 103 case 3: 104 return AMDGPU_TPX_PARTITION_MODE; 105 case 4: 106 return AMDGPU_QPX_PARTITION_MODE; 107 default: 108 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 109 } 110 111 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 112 } 113 114 static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 115 { 116 enum amdgpu_gfx_partition derv_mode, 117 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 118 struct amdgpu_device *adev = xcp_mgr->adev; 119 120 derv_mode = __aqua_vanjaram_calc_xcp_mode(xcp_mgr); 121 122 if (amdgpu_sriov_vf(adev)) 123 return derv_mode; 124 125 if (adev->nbio.funcs->get_compute_partition_mode) { 126 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 127 if (mode != derv_mode) { 128 dev_warn( 129 adev->dev, 130 "Mismatch in compute partition mode - reported : %d derived : %d", 131 mode, derv_mode); 132 if (derv_mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 133 amdgpu_device_bus_status_check(adev); 134 } 135 } 136 137 return mode; 138 } 139 140 static int __aqua_vanjaram_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 141 { 142 int num_xcc, num_xcc_per_xcp = 0; 143 144 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 145 146 switch (mode) { 147 case AMDGPU_SPX_PARTITION_MODE: 148 num_xcc_per_xcp = num_xcc; 149 break; 150 case AMDGPU_DPX_PARTITION_MODE: 151 num_xcc_per_xcp = num_xcc / 2; 152 break; 153 case AMDGPU_TPX_PARTITION_MODE: 154 num_xcc_per_xcp = num_xcc / 3; 155 break; 156 case AMDGPU_QPX_PARTITION_MODE: 157 num_xcc_per_xcp = num_xcc / 4; 158 break; 159 case AMDGPU_CPX_PARTITION_MODE: 160 num_xcc_per_xcp = 1; 161 break; 162 } 163 164 return num_xcc_per_xcp; 165 } 166 167 static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 168 enum AMDGPU_XCP_IP_BLOCK ip_id, 169 struct amdgpu_xcp_ip *ip) 170 { 171 struct amdgpu_device *adev = xcp_mgr->adev; 172 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 173 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 174 175 num_sdma = adev->sdma.num_instances; 176 num_vcn = adev->vcn.num_vcn_inst; 177 num_shared_vcn = 1; 178 179 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 180 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 181 182 switch (xcp_mgr->mode) { 183 case AMDGPU_SPX_PARTITION_MODE: 184 case AMDGPU_DPX_PARTITION_MODE: 185 case AMDGPU_TPX_PARTITION_MODE: 186 case AMDGPU_QPX_PARTITION_MODE: 187 case AMDGPU_CPX_PARTITION_MODE: 188 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 189 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 190 break; 191 default: 192 return -EINVAL; 193 } 194 195 if (num_vcn && num_xcp > num_vcn) 196 num_shared_vcn = num_xcp / num_vcn; 197 198 switch (ip_id) { 199 case AMDGPU_XCP_GFXHUB: 200 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 201 ip->ip_funcs = &gfxhub_v1_2_xcp_funcs; 202 break; 203 case AMDGPU_XCP_GFX: 204 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 205 ip->ip_funcs = &gfx_v9_4_3_xcp_funcs; 206 break; 207 case AMDGPU_XCP_SDMA: 208 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 209 ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; 210 break; 211 case AMDGPU_XCP_VCN: 212 ip->inst_mask = 213 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 214 /* TODO : Assign IP funcs */ 215 break; 216 default: 217 return -EINVAL; 218 } 219 220 ip->ip_id = ip_id; 221 222 return 0; 223 } 224 225 static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr, 226 int px_mode, int *num_xcp, 227 uint16_t *nps_modes) 228 { 229 struct amdgpu_device *adev = xcp_mgr->adev; 230 231 if (!num_xcp || !nps_modes || !(xcp_mgr->supp_xcp_modes & BIT(px_mode))) 232 return -EINVAL; 233 234 switch (px_mode) { 235 case AMDGPU_SPX_PARTITION_MODE: 236 *num_xcp = 1; 237 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 238 break; 239 case AMDGPU_DPX_PARTITION_MODE: 240 *num_xcp = 2; 241 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 242 BIT(AMDGPU_NPS2_PARTITION_MODE); 243 break; 244 case AMDGPU_TPX_PARTITION_MODE: 245 *num_xcp = 3; 246 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 247 BIT(AMDGPU_NPS4_PARTITION_MODE); 248 break; 249 case AMDGPU_QPX_PARTITION_MODE: 250 *num_xcp = 4; 251 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 252 BIT(AMDGPU_NPS4_PARTITION_MODE); 253 break; 254 case AMDGPU_CPX_PARTITION_MODE: 255 *num_xcp = NUM_XCC(adev->gfx.xcc_mask); 256 *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 257 BIT(AMDGPU_NPS4_PARTITION_MODE); 258 if (amdgpu_sriov_vf(adev)) 259 *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); 260 break; 261 default: 262 return -EINVAL; 263 } 264 265 return 0; 266 } 267 268 static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 269 int mode, 270 struct amdgpu_xcp_cfg *xcp_cfg) 271 { 272 struct amdgpu_device *adev = xcp_mgr->adev; 273 int max_res[AMDGPU_XCP_RES_MAX] = {}; 274 bool res_lt_xcp; 275 int num_xcp, i, r; 276 u16 nps_modes; 277 278 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 279 return -EINVAL; 280 281 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 282 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 283 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 284 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 285 286 r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &num_xcp, &nps_modes); 287 if (r) 288 return r; 289 290 xcp_cfg->compatible_nps_modes = 291 (adev->gmc.supported_nps_modes & nps_modes); 292 xcp_cfg->num_res = ARRAY_SIZE(max_res); 293 294 for (i = 0; i < xcp_cfg->num_res; i++) { 295 res_lt_xcp = max_res[i] < num_xcp; 296 xcp_cfg->xcp_res[i].id = i; 297 xcp_cfg->xcp_res[i].num_inst = 298 res_lt_xcp ? 1 : max_res[i] / num_xcp; 299 xcp_cfg->xcp_res[i].num_inst = 300 i == AMDGPU_XCP_RES_JPEG ? 301 xcp_cfg->xcp_res[i].num_inst * 302 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 303 xcp_cfg->xcp_res[i].num_shared = 304 res_lt_xcp ? num_xcp / max_res[i] : 1; 305 } 306 307 return 0; 308 } 309 310 static enum amdgpu_gfx_partition 311 __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 312 { 313 struct amdgpu_device *adev = xcp_mgr->adev; 314 int num_xcc; 315 316 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 317 318 if (adev->gmc.num_mem_partitions == 1) 319 return AMDGPU_SPX_PARTITION_MODE; 320 321 if (adev->gmc.num_mem_partitions == num_xcc) 322 return AMDGPU_CPX_PARTITION_MODE; 323 324 if (adev->gmc.num_mem_partitions == num_xcc / 2) 325 return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE : 326 AMDGPU_CPX_PARTITION_MODE; 327 328 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) 329 return AMDGPU_DPX_PARTITION_MODE; 330 331 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 332 } 333 334 static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 335 enum amdgpu_gfx_partition mode) 336 { 337 struct amdgpu_device *adev = xcp_mgr->adev; 338 int num_xcc, num_xccs_per_xcp, r; 339 int num_xcp, nps_mode; 340 u16 supp_nps_modes; 341 bool comp_mode; 342 343 nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 344 r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &num_xcp, 345 &supp_nps_modes); 346 if (r) 347 return false; 348 349 comp_mode = !!(BIT(nps_mode) & supp_nps_modes); 350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 351 switch (mode) { 352 case AMDGPU_SPX_PARTITION_MODE: 353 return comp_mode && num_xcc > 0; 354 case AMDGPU_DPX_PARTITION_MODE: 355 return comp_mode && (num_xcc % 4) == 0; 356 case AMDGPU_TPX_PARTITION_MODE: 357 return comp_mode && ((num_xcc % 3) == 0); 358 case AMDGPU_QPX_PARTITION_MODE: 359 num_xccs_per_xcp = num_xcc / 4; 360 return comp_mode && (num_xccs_per_xcp >= 2); 361 case AMDGPU_CPX_PARTITION_MODE: 362 return comp_mode && (num_xcc > 1); 363 default: 364 return false; 365 } 366 367 return false; 368 } 369 370 static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 371 { 372 int mode; 373 374 xcp_mgr->avail_xcp_modes = 0; 375 376 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 377 if (__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) 378 xcp_mgr->avail_xcp_modes |= BIT(mode); 379 } 380 } 381 382 static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 383 int mode, int *num_xcps) 384 { 385 int num_xcc_per_xcp, num_xcc, ret; 386 struct amdgpu_device *adev; 387 u32 flags = 0; 388 389 adev = xcp_mgr->adev; 390 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 391 392 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 393 mode = __aqua_vanjaram_get_auto_mode(xcp_mgr); 394 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 395 dev_err(adev->dev, 396 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 397 adev->gmc.num_mem_partitions); 398 return -EINVAL; 399 } 400 } else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) { 401 dev_err(adev->dev, 402 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 403 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 404 return -EINVAL; 405 } 406 407 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 408 flags |= AMDGPU_XCP_OPS_KFD; 409 410 if (flags & AMDGPU_XCP_OPS_KFD) { 411 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 412 if (ret) 413 goto out; 414 } 415 416 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 417 if (ret) 418 goto unlock; 419 420 num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, mode); 421 if (adev->gfx.funcs->switch_partition_mode) 422 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, 423 num_xcc_per_xcp); 424 425 /* Init info about new xcps */ 426 *num_xcps = num_xcc / num_xcc_per_xcp; 427 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 428 429 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 430 if (!ret) 431 __aqua_vanjaram_update_available_partition_mode(xcp_mgr); 432 unlock: 433 if (flags & AMDGPU_XCP_OPS_KFD) 434 amdgpu_amdkfd_unlock_kfd(adev); 435 out: 436 return ret; 437 } 438 439 static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev, 440 int xcc_id, uint8_t *mem_id) 441 { 442 /* memory/spatial modes validation check is already done */ 443 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 444 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 445 446 return 0; 447 } 448 449 static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 450 struct amdgpu_xcp *xcp, uint8_t *mem_id) 451 { 452 struct amdgpu_numa_info numa_info; 453 struct amdgpu_device *adev; 454 uint32_t xcc_mask; 455 int r, i, xcc_id; 456 457 adev = xcp_mgr->adev; 458 /* TODO: BIOS is not returning the right info now 459 * Check on this later 460 */ 461 /* 462 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 463 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 464 */ 465 if (adev->gmc.num_mem_partitions == 1) { 466 /* Only one range */ 467 *mem_id = 0; 468 return 0; 469 } 470 471 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 472 if (r || !xcc_mask) 473 return -EINVAL; 474 475 xcc_id = ffs(xcc_mask) - 1; 476 if (!adev->gmc.is_app_apu) 477 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id); 478 479 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 480 481 if (r) 482 return r; 483 484 r = -EINVAL; 485 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 486 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 487 *mem_id = i; 488 r = 0; 489 break; 490 } 491 } 492 493 return r; 494 } 495 496 static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 497 enum AMDGPU_XCP_IP_BLOCK ip_id, 498 struct amdgpu_xcp_ip *ip) 499 { 500 if (!ip) 501 return -EINVAL; 502 503 return __aqua_vanjaram_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 504 } 505 506 struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = { 507 .switch_partition_mode = &aqua_vanjaram_switch_partition_mode, 508 .query_partition_mode = &aqua_vanjaram_query_partition_mode, 509 .get_ip_details = &aqua_vanjaram_get_xcp_ip_details, 510 .get_xcp_res_info = &aqua_vanjaram_get_xcp_res_info, 511 .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id, 512 }; 513 514 static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) 515 { 516 int ret; 517 518 if (amdgpu_sriov_vf(adev)) 519 aqua_vanjaram_xcp_funcs.switch_partition_mode = NULL; 520 521 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 1, 522 &aqua_vanjaram_xcp_funcs); 523 if (ret) 524 return ret; 525 526 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 527 /* TODO: Default memory node affinity init */ 528 529 return ret; 530 } 531 532 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev) 533 { 534 u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask; 535 int ret, i; 536 537 /* generally 1 AID supports 4 instances */ 538 adev->sdma.num_inst_per_aid = 4; 539 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask); 540 541 adev->aid_mask = i = 1; 542 inst_mask >>= adev->sdma.num_inst_per_aid; 543 544 for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask; 545 inst_mask >>= adev->sdma.num_inst_per_aid, ++i) { 546 avail_inst = inst_mask & mask; 547 if (avail_inst == mask || avail_inst == 0x3 || 548 avail_inst == 0xc) 549 adev->aid_mask |= (1 << i); 550 } 551 552 /* Harvest config is not used for aqua vanjaram. VCN and JPEGs will be 553 * addressed based on logical instance ids. 554 */ 555 adev->vcn.harvest_config = 0; 556 adev->vcn.num_inst_per_aid = 1; 557 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); 558 adev->jpeg.harvest_config = 0; 559 adev->jpeg.num_inst_per_aid = 1; 560 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask); 561 562 ret = aqua_vanjaram_xcp_mgr_init(adev); 563 if (ret) 564 return ret; 565 566 amdgpu_ip_map_init(adev); 567 568 return 0; 569 } 570 571 static void aqua_read_smn(struct amdgpu_device *adev, 572 struct amdgpu_smn_reg_data *regdata, 573 uint64_t smn_addr) 574 { 575 regdata->addr = smn_addr; 576 regdata->value = RREG32_PCIE(smn_addr); 577 } 578 579 struct aqua_reg_list { 580 uint64_t start_addr; 581 uint32_t num_regs; 582 uint32_t incrx; 583 }; 584 585 #define DW_ADDR_INCR 4 586 587 static void aqua_read_smn_ext(struct amdgpu_device *adev, 588 struct amdgpu_smn_reg_data *regdata, 589 uint64_t smn_addr, int i) 590 { 591 regdata->addr = 592 smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i); 593 regdata->value = RREG32_PCIE_EXT(regdata->addr); 594 } 595 596 #define smnreg_0x1A340218 0x1A340218 597 #define smnreg_0x1A3402E4 0x1A3402E4 598 #define smnreg_0x1A340294 0x1A340294 599 #define smreg_0x1A380088 0x1A380088 600 601 #define NUM_PCIE_SMN_REGS 14 602 603 static struct aqua_reg_list pcie_reg_addrs[] = { 604 { smnreg_0x1A340218, 1, 0 }, 605 { smnreg_0x1A3402E4, 1, 0 }, 606 { smnreg_0x1A340294, 6, DW_ADDR_INCR }, 607 { smreg_0x1A380088, 6, DW_ADDR_INCR }, 608 }; 609 610 static ssize_t aqua_vanjaram_read_pcie_state(struct amdgpu_device *adev, 611 void *buf, size_t max_size) 612 { 613 struct amdgpu_reg_state_pcie_v1_0 *pcie_reg_state; 614 uint32_t start_addr, incrx, num_regs, szbuf; 615 struct amdgpu_regs_pcie_v1_0 *pcie_regs; 616 struct amdgpu_smn_reg_data *reg_data; 617 struct pci_dev *us_pdev, *ds_pdev; 618 int aer_cap, r, n; 619 620 if (!buf || !max_size) 621 return -EINVAL; 622 623 pcie_reg_state = (struct amdgpu_reg_state_pcie_v1_0 *)buf; 624 625 szbuf = sizeof(*pcie_reg_state) + 626 amdgpu_reginst_size(1, sizeof(*pcie_regs), NUM_PCIE_SMN_REGS); 627 /* Only one instance of pcie regs */ 628 if (max_size < szbuf) 629 return -EOVERFLOW; 630 631 pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf + 632 sizeof(*pcie_reg_state)); 633 pcie_regs->inst_header.instance = 0; 634 pcie_regs->inst_header.state = AMDGPU_INST_S_OK; 635 pcie_regs->inst_header.num_smn_regs = NUM_PCIE_SMN_REGS; 636 637 reg_data = pcie_regs->smn_reg_values; 638 639 for (r = 0; r < ARRAY_SIZE(pcie_reg_addrs); r++) { 640 start_addr = pcie_reg_addrs[r].start_addr; 641 incrx = pcie_reg_addrs[r].incrx; 642 num_regs = pcie_reg_addrs[r].num_regs; 643 for (n = 0; n < num_regs; n++) { 644 aqua_read_smn(adev, reg_data, start_addr + n * incrx); 645 ++reg_data; 646 } 647 } 648 649 ds_pdev = pci_upstream_bridge(adev->pdev); 650 us_pdev = pci_upstream_bridge(ds_pdev); 651 652 pcie_capability_read_word(us_pdev, PCI_EXP_DEVSTA, 653 &pcie_regs->device_status); 654 pcie_capability_read_word(us_pdev, PCI_EXP_LNKSTA, 655 &pcie_regs->link_status); 656 657 aer_cap = pci_find_ext_capability(us_pdev, PCI_EXT_CAP_ID_ERR); 658 if (aer_cap) { 659 pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_COR_STATUS, 660 &pcie_regs->pcie_corr_err_status); 661 pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_UNCOR_STATUS, 662 &pcie_regs->pcie_uncorr_err_status); 663 } 664 665 pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS, 666 &pcie_regs->sub_bus_number_latency); 667 668 pcie_reg_state->common_header.structure_size = szbuf; 669 pcie_reg_state->common_header.format_revision = 1; 670 pcie_reg_state->common_header.content_revision = 0; 671 pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE; 672 pcie_reg_state->common_header.num_instances = 1; 673 674 return pcie_reg_state->common_header.structure_size; 675 } 676 677 #define smnreg_0x11A00050 0x11A00050 678 #define smnreg_0x11A00180 0x11A00180 679 #define smnreg_0x11A00070 0x11A00070 680 #define smnreg_0x11A00200 0x11A00200 681 #define smnreg_0x11A0020C 0x11A0020C 682 #define smnreg_0x11A00210 0x11A00210 683 #define smnreg_0x11A00108 0x11A00108 684 685 #define XGMI_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 686 687 #define NUM_XGMI_SMN_REGS 25 688 689 static struct aqua_reg_list xgmi_reg_addrs[] = { 690 { smnreg_0x11A00050, 1, 0 }, 691 { smnreg_0x11A00180, 16, DW_ADDR_INCR }, 692 { smnreg_0x11A00070, 4, DW_ADDR_INCR }, 693 { smnreg_0x11A00200, 1, 0 }, 694 { smnreg_0x11A0020C, 1, 0 }, 695 { smnreg_0x11A00210, 1, 0 }, 696 { smnreg_0x11A00108, 1, 0 }, 697 }; 698 699 static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev, 700 void *buf, size_t max_size) 701 { 702 struct amdgpu_reg_state_xgmi_v1_0 *xgmi_reg_state; 703 uint32_t start_addr, incrx, num_regs, szbuf; 704 struct amdgpu_regs_xgmi_v1_0 *xgmi_regs; 705 struct amdgpu_smn_reg_data *reg_data; 706 const int max_xgmi_instances = 8; 707 int inst = 0, i, j, r, n; 708 const int xgmi_inst = 2; 709 void *p; 710 711 if (!buf || !max_size) 712 return -EINVAL; 713 714 xgmi_reg_state = (struct amdgpu_reg_state_xgmi_v1_0 *)buf; 715 716 szbuf = sizeof(*xgmi_reg_state) + 717 amdgpu_reginst_size(max_xgmi_instances, sizeof(*xgmi_regs), 718 NUM_XGMI_SMN_REGS); 719 /* Only one instance of pcie regs */ 720 if (max_size < szbuf) 721 return -EOVERFLOW; 722 723 p = &xgmi_reg_state->xgmi_state_regs[0]; 724 for_each_inst(i, adev->aid_mask) { 725 for (j = 0; j < xgmi_inst; ++j) { 726 xgmi_regs = (struct amdgpu_regs_xgmi_v1_0 *)p; 727 xgmi_regs->inst_header.instance = inst++; 728 729 xgmi_regs->inst_header.state = AMDGPU_INST_S_OK; 730 xgmi_regs->inst_header.num_smn_regs = NUM_XGMI_SMN_REGS; 731 732 reg_data = xgmi_regs->smn_reg_values; 733 734 for (r = 0; r < ARRAY_SIZE(xgmi_reg_addrs); r++) { 735 start_addr = xgmi_reg_addrs[r].start_addr; 736 incrx = xgmi_reg_addrs[r].incrx; 737 num_regs = xgmi_reg_addrs[r].num_regs; 738 739 for (n = 0; n < num_regs; n++) { 740 aqua_read_smn_ext( 741 adev, reg_data, 742 XGMI_LINK_REG(start_addr, j) + 743 n * incrx, 744 i); 745 ++reg_data; 746 } 747 } 748 p = reg_data; 749 } 750 } 751 752 xgmi_reg_state->common_header.structure_size = szbuf; 753 xgmi_reg_state->common_header.format_revision = 1; 754 xgmi_reg_state->common_header.content_revision = 0; 755 xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI; 756 xgmi_reg_state->common_header.num_instances = max_xgmi_instances; 757 758 return xgmi_reg_state->common_header.structure_size; 759 } 760 761 #define smnreg_0x11C00070 0x11C00070 762 #define smnreg_0x11C00210 0x11C00210 763 764 static struct aqua_reg_list wafl_reg_addrs[] = { 765 { smnreg_0x11C00070, 4, DW_ADDR_INCR }, 766 { smnreg_0x11C00210, 1, 0 }, 767 }; 768 769 #define WAFL_LINK_REG(smnreg, l) ((smnreg) | (l << 20)) 770 771 #define NUM_WAFL_SMN_REGS 5 772 773 static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev, 774 void *buf, size_t max_size) 775 { 776 struct amdgpu_reg_state_wafl_v1_0 *wafl_reg_state; 777 uint32_t start_addr, incrx, num_regs, szbuf; 778 struct amdgpu_regs_wafl_v1_0 *wafl_regs; 779 struct amdgpu_smn_reg_data *reg_data; 780 const int max_wafl_instances = 8; 781 int inst = 0, i, j, r, n; 782 const int wafl_inst = 2; 783 void *p; 784 785 if (!buf || !max_size) 786 return -EINVAL; 787 788 wafl_reg_state = (struct amdgpu_reg_state_wafl_v1_0 *)buf; 789 790 szbuf = sizeof(*wafl_reg_state) + 791 amdgpu_reginst_size(max_wafl_instances, sizeof(*wafl_regs), 792 NUM_WAFL_SMN_REGS); 793 794 if (max_size < szbuf) 795 return -EOVERFLOW; 796 797 p = &wafl_reg_state->wafl_state_regs[0]; 798 for_each_inst(i, adev->aid_mask) { 799 for (j = 0; j < wafl_inst; ++j) { 800 wafl_regs = (struct amdgpu_regs_wafl_v1_0 *)p; 801 wafl_regs->inst_header.instance = inst++; 802 803 wafl_regs->inst_header.state = AMDGPU_INST_S_OK; 804 wafl_regs->inst_header.num_smn_regs = NUM_WAFL_SMN_REGS; 805 806 reg_data = wafl_regs->smn_reg_values; 807 808 for (r = 0; r < ARRAY_SIZE(wafl_reg_addrs); r++) { 809 start_addr = wafl_reg_addrs[r].start_addr; 810 incrx = wafl_reg_addrs[r].incrx; 811 num_regs = wafl_reg_addrs[r].num_regs; 812 for (n = 0; n < num_regs; n++) { 813 aqua_read_smn_ext( 814 adev, reg_data, 815 WAFL_LINK_REG(start_addr, j) + 816 n * incrx, 817 i); 818 ++reg_data; 819 } 820 } 821 p = reg_data; 822 } 823 } 824 825 wafl_reg_state->common_header.structure_size = szbuf; 826 wafl_reg_state->common_header.format_revision = 1; 827 wafl_reg_state->common_header.content_revision = 0; 828 wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL; 829 wafl_reg_state->common_header.num_instances = max_wafl_instances; 830 831 return wafl_reg_state->common_header.structure_size; 832 } 833 834 #define smnreg_0x1B311060 0x1B311060 835 #define smnreg_0x1B411060 0x1B411060 836 #define smnreg_0x1B511060 0x1B511060 837 #define smnreg_0x1B611060 0x1B611060 838 839 #define smnreg_0x1C307120 0x1C307120 840 #define smnreg_0x1C317120 0x1C317120 841 842 #define smnreg_0x1C320830 0x1C320830 843 #define smnreg_0x1C380830 0x1C380830 844 #define smnreg_0x1C3D0830 0x1C3D0830 845 #define smnreg_0x1C420830 0x1C420830 846 847 #define smnreg_0x1C320100 0x1C320100 848 #define smnreg_0x1C380100 0x1C380100 849 #define smnreg_0x1C3D0100 0x1C3D0100 850 #define smnreg_0x1C420100 0x1C420100 851 852 #define smnreg_0x1B310500 0x1B310500 853 #define smnreg_0x1C300400 0x1C300400 854 855 #define USR_CAKE_INCR 0x11000 856 #define USR_LINK_INCR 0x100000 857 #define USR_CP_INCR 0x10000 858 859 #define NUM_USR_SMN_REGS 20 860 861 struct aqua_reg_list usr_reg_addrs[] = { 862 { smnreg_0x1B311060, 4, DW_ADDR_INCR }, 863 { smnreg_0x1B411060, 4, DW_ADDR_INCR }, 864 { smnreg_0x1B511060, 4, DW_ADDR_INCR }, 865 { smnreg_0x1B611060, 4, DW_ADDR_INCR }, 866 { smnreg_0x1C307120, 2, DW_ADDR_INCR }, 867 { smnreg_0x1C317120, 2, DW_ADDR_INCR }, 868 }; 869 870 #define NUM_USR1_SMN_REGS 46 871 struct aqua_reg_list usr1_reg_addrs[] = { 872 { smnreg_0x1C320830, 6, USR_CAKE_INCR }, 873 { smnreg_0x1C380830, 5, USR_CAKE_INCR }, 874 { smnreg_0x1C3D0830, 5, USR_CAKE_INCR }, 875 { smnreg_0x1C420830, 4, USR_CAKE_INCR }, 876 { smnreg_0x1C320100, 6, USR_CAKE_INCR }, 877 { smnreg_0x1C380100, 5, USR_CAKE_INCR }, 878 { smnreg_0x1C3D0100, 5, USR_CAKE_INCR }, 879 { smnreg_0x1C420100, 4, USR_CAKE_INCR }, 880 { smnreg_0x1B310500, 4, USR_LINK_INCR }, 881 { smnreg_0x1C300400, 2, USR_CP_INCR }, 882 }; 883 884 static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev, 885 void *buf, size_t max_size, 886 int reg_state) 887 { 888 uint32_t start_addr, incrx, num_regs, szbuf, num_smn; 889 struct amdgpu_reg_state_usr_v1_0 *usr_reg_state; 890 struct amdgpu_regs_usr_v1_0 *usr_regs; 891 struct amdgpu_smn_reg_data *reg_data; 892 const int max_usr_instances = 4; 893 struct aqua_reg_list *reg_addrs; 894 int inst = 0, i, n, r, arr_size; 895 void *p; 896 897 if (!buf || !max_size) 898 return -EINVAL; 899 900 switch (reg_state) { 901 case AMDGPU_REG_STATE_TYPE_USR: 902 arr_size = ARRAY_SIZE(usr_reg_addrs); 903 reg_addrs = usr_reg_addrs; 904 num_smn = NUM_USR_SMN_REGS; 905 break; 906 case AMDGPU_REG_STATE_TYPE_USR_1: 907 arr_size = ARRAY_SIZE(usr1_reg_addrs); 908 reg_addrs = usr1_reg_addrs; 909 num_smn = NUM_USR1_SMN_REGS; 910 break; 911 default: 912 return -EINVAL; 913 } 914 915 usr_reg_state = (struct amdgpu_reg_state_usr_v1_0 *)buf; 916 917 szbuf = sizeof(*usr_reg_state) + amdgpu_reginst_size(max_usr_instances, 918 sizeof(*usr_regs), 919 num_smn); 920 if (max_size < szbuf) 921 return -EOVERFLOW; 922 923 p = &usr_reg_state->usr_state_regs[0]; 924 for_each_inst(i, adev->aid_mask) { 925 usr_regs = (struct amdgpu_regs_usr_v1_0 *)p; 926 usr_regs->inst_header.instance = inst++; 927 usr_regs->inst_header.state = AMDGPU_INST_S_OK; 928 usr_regs->inst_header.num_smn_regs = num_smn; 929 reg_data = usr_regs->smn_reg_values; 930 931 for (r = 0; r < arr_size; r++) { 932 start_addr = reg_addrs[r].start_addr; 933 incrx = reg_addrs[r].incrx; 934 num_regs = reg_addrs[r].num_regs; 935 for (n = 0; n < num_regs; n++) { 936 aqua_read_smn_ext(adev, reg_data, 937 start_addr + n * incrx, i); 938 reg_data++; 939 } 940 } 941 p = reg_data; 942 } 943 944 usr_reg_state->common_header.structure_size = szbuf; 945 usr_reg_state->common_header.format_revision = 1; 946 usr_reg_state->common_header.content_revision = 0; 947 usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR; 948 usr_reg_state->common_header.num_instances = max_usr_instances; 949 950 return usr_reg_state->common_header.structure_size; 951 } 952 953 ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, 954 enum amdgpu_reg_state reg_state, void *buf, 955 size_t max_size) 956 { 957 ssize_t size; 958 959 switch (reg_state) { 960 case AMDGPU_REG_STATE_TYPE_PCIE: 961 size = aqua_vanjaram_read_pcie_state(adev, buf, max_size); 962 break; 963 case AMDGPU_REG_STATE_TYPE_XGMI: 964 size = aqua_vanjaram_read_xgmi_state(adev, buf, max_size); 965 break; 966 case AMDGPU_REG_STATE_TYPE_WAFL: 967 size = aqua_vanjaram_read_wafl_state(adev, buf, max_size); 968 break; 969 case AMDGPU_REG_STATE_TYPE_USR: 970 size = aqua_vanjaram_read_usr_state(adev, buf, max_size, 971 AMDGPU_REG_STATE_TYPE_USR); 972 break; 973 case AMDGPU_REG_STATE_TYPE_USR_1: 974 size = aqua_vanjaram_read_usr_state( 975 adev, buf, max_size, AMDGPU_REG_STATE_TYPE_USR_1); 976 break; 977 default: 978 return -EINVAL; 979 } 980 981 return size; 982 } 983