1 /* 2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #ifndef AMDGV_SRIOV_MSG__H_ 24 #define AMDGV_SRIOV_MSG__H_ 25 26 #define AMD_SRIOV_MSG_SIZE_KB 1 27 28 /* 29 * layout v1 30 * 0 64KB 65KB 66KB 68KB 132KB 31 * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... 32 * | 64KB | 1KB | 1KB | 2KB | 64KB | ... 33 */ 34 35 /* 36 * layout v2 (offsets are dynamically allocated and the offsets below are examples) 37 * 0 1KB 64KB 65KB 66KB 68KB 132KB 38 * | INITD_H | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... 39 * | 1KB | 64KB | 1KB | 1KB | 2KB | 64KB | ... 40 * 41 * Note: PF2VF + VF2PF + Bad Page = DataExchange region (allocated contiguously) 42 */ 43 44 /* v1 layout sizes */ 45 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 64 46 #define AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 1 47 #define AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 1 48 #define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1 2 49 #define AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 64 50 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 \ 51 (AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 + AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 + \ 52 AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1) 53 54 /* v1 offsets */ 55 #define AMD_SRIOV_MSG_VBIOS_OFFSET_V1 0 56 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1 AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 57 #define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 58 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1 59 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 \ 60 (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB) 61 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 \ 62 (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB) 63 #define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 \ 64 (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1) 65 #define AMD_SRIOV_MSG_INIT_DATA_TOT_SIZE_KB_V1 \ 66 (AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \ 67 AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1) 68 69 enum amd_sriov_crit_region_version { 70 GPU_CRIT_REGION_V1 = 1, 71 GPU_CRIT_REGION_V2 = 2, 72 }; 73 74 /* v2 layout offset enum (in order of allocation) */ 75 enum amd_sriov_msg_table_id_enum { 76 AMD_SRIOV_MSG_IPD_TABLE_ID = 0, 77 AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, 78 AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID, 79 AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID, 80 AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID, 81 AMD_SRIOV_MSG_INITD_H_TABLE_ID, 82 AMD_SRIOV_MSG_MAX_TABLE_ID, 83 }; 84 85 struct amd_sriov_msg_init_data_header { 86 char signature[4]; /* "INDA" */ 87 uint32_t version; 88 uint32_t checksum; 89 uint32_t initdata_offset; /* 0 */ 90 uint32_t initdata_size_in_kb; /* 5MB */ 91 uint32_t valid_tables; 92 uint32_t vbios_img_offset; 93 uint32_t vbios_img_size_in_kb; 94 uint32_t dataexchange_offset; 95 uint32_t dataexchange_size_in_kb; 96 uint32_t ras_tele_info_offset; 97 uint32_t ras_tele_info_size_in_kb; 98 uint32_t ip_discovery_offset; 99 uint32_t ip_discovery_size_in_kb; 100 uint32_t bad_page_info_offset; 101 uint32_t bad_page_size_in_kb; 102 uint32_t reserved[8]; 103 }; 104 105 /* 106 * PF2VF history log: 107 * v1 defined in amdgim 108 * v2 current 109 * 110 * VF2PF history log: 111 * v1 defined in amdgim 112 * v2 defined in amdgim 113 * v3 current 114 */ 115 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2 116 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3 117 118 #define AMD_SRIOV_MSG_RESERVE_UCODE 24 119 120 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 121 122 enum amd_sriov_ucode_engine_id { 123 AMD_SRIOV_UCODE_ID_VCE = 0, 124 AMD_SRIOV_UCODE_ID_UVD, 125 AMD_SRIOV_UCODE_ID_MC, 126 AMD_SRIOV_UCODE_ID_ME, 127 AMD_SRIOV_UCODE_ID_PFP, 128 AMD_SRIOV_UCODE_ID_CE, 129 AMD_SRIOV_UCODE_ID_RLC, 130 AMD_SRIOV_UCODE_ID_RLC_SRLC, 131 AMD_SRIOV_UCODE_ID_RLC_SRLG, 132 AMD_SRIOV_UCODE_ID_RLC_SRLS, 133 AMD_SRIOV_UCODE_ID_MEC, 134 AMD_SRIOV_UCODE_ID_MEC2, 135 AMD_SRIOV_UCODE_ID_SOS, 136 AMD_SRIOV_UCODE_ID_ASD, 137 AMD_SRIOV_UCODE_ID_TA_RAS, 138 AMD_SRIOV_UCODE_ID_TA_XGMI, 139 AMD_SRIOV_UCODE_ID_SMC, 140 AMD_SRIOV_UCODE_ID_SDMA, 141 AMD_SRIOV_UCODE_ID_SDMA2, 142 AMD_SRIOV_UCODE_ID_VCN, 143 AMD_SRIOV_UCODE_ID_DMCU, 144 AMD_SRIOV_UCODE_ID__MAX 145 }; 146 147 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed 148 149 union amd_sriov_msg_feature_flags { 150 struct { 151 uint32_t error_log_collect : 1; 152 uint32_t host_load_ucodes : 1; 153 uint32_t host_flr_vramlost : 1; 154 uint32_t mm_bw_management : 1; 155 uint32_t pp_one_vf_mode : 1; 156 uint32_t reg_indirect_acc : 1; 157 uint32_t av1_support : 1; 158 uint32_t vcn_rb_decouple : 1; 159 uint32_t mes_info_dump_enable : 1; 160 uint32_t ras_caps : 1; 161 uint32_t ras_telemetry : 1; 162 uint32_t ras_cper : 1; 163 uint32_t reserved : 20; 164 } flags; 165 uint32_t all; 166 }; 167 168 union amd_sriov_reg_access_flags { 169 struct { 170 uint32_t vf_reg_access_ih : 1; 171 uint32_t vf_reg_access_mmhub : 1; 172 uint32_t vf_reg_access_gc : 1; 173 uint32_t vf_reg_access_l1_tlb_cntl : 1; 174 uint32_t vf_reg_access_sq_config : 1; 175 uint32_t reserved : 27; 176 } flags; 177 uint32_t all; 178 }; 179 180 union amd_sriov_ras_caps { 181 struct { 182 uint64_t block_umc : 1; 183 uint64_t block_sdma : 1; 184 uint64_t block_gfx : 1; 185 uint64_t block_mmhub : 1; 186 uint64_t block_athub : 1; 187 uint64_t block_pcie_bif : 1; 188 uint64_t block_hdp : 1; 189 uint64_t block_xgmi_wafl : 1; 190 uint64_t block_df : 1; 191 uint64_t block_smn : 1; 192 uint64_t block_sem : 1; 193 uint64_t block_mp0 : 1; 194 uint64_t block_mp1 : 1; 195 uint64_t block_fuse : 1; 196 uint64_t block_mca : 1; 197 uint64_t block_vcn : 1; 198 uint64_t block_jpeg : 1; 199 uint64_t block_ih : 1; 200 uint64_t block_mpio : 1; 201 uint64_t poison_propogation_mode : 1; 202 uint64_t reserved : 44; 203 } bits; 204 uint64_t all; 205 }; 206 207 union amd_sriov_msg_os_info { 208 struct { 209 uint32_t windows : 1; 210 uint32_t reserved : 31; 211 } info; 212 uint32_t all; 213 }; 214 215 struct amd_sriov_msg_uuid_info { 216 union { 217 struct { 218 uint32_t did : 16; 219 uint32_t fcn : 8; 220 uint32_t asic_7 : 8; 221 }; 222 uint32_t time_low; 223 }; 224 225 struct { 226 uint32_t time_mid : 16; 227 uint32_t time_high : 12; 228 uint32_t version : 4; 229 }; 230 231 struct { 232 struct { 233 uint8_t clk_seq_hi : 6; 234 uint8_t variant : 2; 235 }; 236 union { 237 uint8_t clk_seq_low; 238 uint8_t asic_6; 239 }; 240 uint16_t asic_4; 241 }; 242 243 uint32_t asic_0; 244 }; 245 246 struct amd_sriov_msg_pf2vf_info_header { 247 /* the total structure size in byte */ 248 uint32_t size; 249 /* version of this structure, written by the HOST */ 250 uint32_t version; 251 /* reserved */ 252 uint32_t reserved[2]; 253 }; 254 255 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) 256 struct amd_sriov_msg_pf2vf_info { 257 /* header contains size and version */ 258 struct amd_sriov_msg_pf2vf_info_header header; 259 /* use private key from mailbox 2 to create checksum */ 260 uint32_t checksum; 261 /* The features flags of the HOST driver supports */ 262 union amd_sriov_msg_feature_flags feature_flags; 263 /* (max_width * max_height * fps) / (16 * 16) */ 264 uint32_t hevc_enc_max_mb_per_second; 265 /* (max_width * max_height) / (16 * 16) */ 266 uint32_t hevc_enc_max_mb_per_frame; 267 /* (max_width * max_height * fps) / (16 * 16) */ 268 uint32_t avc_enc_max_mb_per_second; 269 /* (max_width * max_height) / (16 * 16) */ 270 uint32_t avc_enc_max_mb_per_frame; 271 /* MEC FW position in BYTE from the start of VF visible frame buffer */ 272 uint64_t mecfw_offset; 273 /* MEC FW size in BYTE */ 274 uint32_t mecfw_size; 275 /* UVD FW position in BYTE from the start of VF visible frame buffer */ 276 uint64_t uvdfw_offset; 277 /* UVD FW size in BYTE */ 278 uint32_t uvdfw_size; 279 /* VCE FW position in BYTE from the start of VF visible frame buffer */ 280 uint64_t vcefw_offset; 281 /* VCE FW size in BYTE */ 282 uint32_t vcefw_size; 283 /* Bad pages block position in BYTE */ 284 uint32_t bp_block_offset_low; 285 uint32_t bp_block_offset_high; 286 /* Bad pages block size in BYTE */ 287 uint32_t bp_block_size; 288 /* frequency for VF to update the VF2PF area in msec, 0 = manual */ 289 uint32_t vf2pf_update_interval_ms; 290 /* identification in ROCm SMI */ 291 uint64_t uuid; 292 uint32_t fcn_idx; 293 /* flags to indicate which register access method VF should use */ 294 union amd_sriov_reg_access_flags reg_access_flags; 295 /* MM BW management */ 296 struct { 297 uint32_t decode_max_dimension_pixels; 298 uint32_t decode_max_frame_pixels; 299 uint32_t encode_max_dimension_pixels; 300 uint32_t encode_max_frame_pixels; 301 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; 302 /* UUID info */ 303 struct amd_sriov_msg_uuid_info uuid_info; 304 /* PCIE atomic ops support flag */ 305 uint32_t pcie_atomic_ops_support_flags; 306 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */ 307 uint32_t gpu_capacity; 308 /* vf bdf on host pci tree for debug only */ 309 uint32_t bdf_on_host; 310 uint32_t more_bp; //Reserved for future use. 311 union amd_sriov_ras_caps ras_en_caps; 312 union amd_sriov_ras_caps ras_telemetry_en_caps; 313 314 /* reserved */ 315 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; 316 } __packed; 317 318 struct amd_sriov_msg_vf2pf_info_header { 319 /* the total structure size in byte */ 320 uint32_t size; 321 /* version of this structure, written by the guest */ 322 uint32_t version; 323 /* reserved */ 324 uint32_t reserved[2]; 325 }; 326 327 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73) 328 struct amd_sriov_msg_vf2pf_info { 329 /* header contains size and version */ 330 struct amd_sriov_msg_vf2pf_info_header header; 331 uint32_t checksum; 332 /* driver version */ 333 uint8_t driver_version[64]; 334 /* driver certification, 1=WHQL, 0=None */ 335 uint32_t driver_cert; 336 /* guest OS type and version */ 337 union amd_sriov_msg_os_info os_info; 338 /* guest fb information in the unit of MB */ 339 uint32_t fb_usage; 340 /* guest gfx engine usage percentage */ 341 uint32_t gfx_usage; 342 /* guest gfx engine health percentage */ 343 uint32_t gfx_health; 344 /* guest compute engine usage percentage */ 345 uint32_t compute_usage; 346 /* guest compute engine health percentage */ 347 uint32_t compute_health; 348 /* guest avc engine usage percentage. 0xffff means N/A */ 349 uint32_t avc_enc_usage; 350 /* guest avc engine health percentage. 0xffff means N/A */ 351 uint32_t avc_enc_health; 352 /* guest hevc engine usage percentage. 0xffff means N/A */ 353 uint32_t hevc_enc_usage; 354 /* guest hevc engine usage percentage. 0xffff means N/A */ 355 uint32_t hevc_enc_health; 356 /* combined encode/decode usage */ 357 uint32_t encode_usage; 358 uint32_t decode_usage; 359 /* Version of PF2VF that VF understands */ 360 uint32_t pf2vf_version_required; 361 /* additional FB usage */ 362 uint32_t fb_vis_usage; 363 uint32_t fb_vis_size; 364 uint32_t fb_size; 365 /* guest ucode data, each one is 1.25 Dword */ 366 struct { 367 uint8_t id; 368 uint32_t version; 369 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE]; 370 uint64_t dummy_page_addr; 371 /* FB allocated for guest MES to record UQ info */ 372 uint64_t mes_info_addr; 373 uint32_t mes_info_size; 374 /* reserved */ 375 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE]; 376 } __packed; 377 378 /* mailbox message send from guest to host */ 379 enum amd_sriov_mailbox_request_message { 380 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1, 381 MB_REQ_MSG_REL_GPU_INIT_ACCESS, 382 MB_REQ_MSG_REQ_GPU_FINI_ACCESS, 383 MB_REQ_MSG_REL_GPU_FINI_ACCESS, 384 MB_REQ_MSG_REQ_GPU_RESET_ACCESS, 385 MB_REQ_MSG_REQ_GPU_INIT_DATA, 386 MB_REQ_MSG_PSP_VF_CMD_RELAY, 387 388 MB_REQ_MSG_LOG_VF_ERROR = 200, 389 MB_REQ_MSG_READY_TO_RESET = 201, 390 MB_REQ_MSG_RAS_POISON = 202, 391 MB_REQ_RAS_ERROR_COUNT = 203, 392 MB_REQ_RAS_CPER_DUMP = 204, 393 MB_REQ_RAS_BAD_PAGES = 205, 394 }; 395 396 /* mailbox message send from host to guest */ 397 enum amd_sriov_mailbox_response_message { 398 MB_RES_MSG_CLR_MSG_BUF = 0, 399 MB_RES_MSG_READY_TO_ACCESS_GPU = 1, 400 MB_RES_MSG_FLR_NOTIFICATION = 2, 401 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION = 3, 402 MB_RES_MSG_SUCCESS = 4, 403 MB_RES_MSG_FAIL = 5, 404 MB_RES_MSG_QUERY_ALIVE = 6, 405 MB_RES_MSG_GPU_INIT_DATA_READY = 7, 406 MB_RES_MSG_RAS_POISON_READY = 8, 407 MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION = 9, 408 MB_RES_MSG_GPU_RMA = 10, 409 MB_RES_MSG_RAS_ERROR_COUNT_READY = 11, 410 MB_REQ_RAS_CPER_DUMP_READY = 14, 411 MB_RES_MSG_RAS_BAD_PAGES_READY = 15, 412 MB_RES_MSG_RAS_BAD_PAGES_NOTIFICATION = 16, 413 MB_RES_MSG_UNRECOV_ERR_NOTIFICATION = 17, 414 MB_RES_MSG_TEXT_MESSAGE = 255 415 }; 416 417 enum amd_sriov_ras_telemetry_gpu_block { 418 RAS_TELEMETRY_GPU_BLOCK_UMC = 0, 419 RAS_TELEMETRY_GPU_BLOCK_SDMA = 1, 420 RAS_TELEMETRY_GPU_BLOCK_GFX = 2, 421 RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3, 422 RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4, 423 RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5, 424 RAS_TELEMETRY_GPU_BLOCK_HDP = 6, 425 RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7, 426 RAS_TELEMETRY_GPU_BLOCK_DF = 8, 427 RAS_TELEMETRY_GPU_BLOCK_SMN = 9, 428 RAS_TELEMETRY_GPU_BLOCK_SEM = 10, 429 RAS_TELEMETRY_GPU_BLOCK_MP0 = 11, 430 RAS_TELEMETRY_GPU_BLOCK_MP1 = 12, 431 RAS_TELEMETRY_GPU_BLOCK_FUSE = 13, 432 RAS_TELEMETRY_GPU_BLOCK_MCA = 14, 433 RAS_TELEMETRY_GPU_BLOCK_VCN = 15, 434 RAS_TELEMETRY_GPU_BLOCK_JPEG = 16, 435 RAS_TELEMETRY_GPU_BLOCK_IH = 17, 436 RAS_TELEMETRY_GPU_BLOCK_MPIO = 18, 437 RAS_TELEMETRY_GPU_BLOCK_COUNT = 19, 438 }; 439 440 struct amd_sriov_ras_telemetry_header { 441 uint32_t checksum; 442 uint32_t used_size; 443 uint32_t reserved[2]; 444 }; 445 446 struct amd_sriov_ras_telemetry_error_count { 447 struct { 448 uint32_t ce_count; 449 uint32_t ue_count; 450 uint32_t de_count; 451 uint32_t ce_overflow_count; 452 uint32_t ue_overflow_count; 453 uint32_t de_overflow_count; 454 uint32_t reserved[6]; 455 } block[RAS_TELEMETRY_GPU_BLOCK_COUNT]; 456 }; 457 458 struct amd_sriov_ras_cper_dump { 459 uint32_t more; 460 uint64_t overflow_count; 461 uint64_t count; 462 uint64_t wptr; 463 uint32_t buf[]; 464 }; 465 466 struct amd_sriov_ras_chk_criti { 467 uint32_t hit; 468 }; 469 470 struct amdsriov_ras_telemetry { 471 struct amd_sriov_ras_telemetry_header header; 472 473 union { 474 struct amd_sriov_ras_telemetry_error_count error_count; 475 struct amd_sriov_ras_cper_dump cper_dump; 476 struct amd_sriov_ras_chk_criti chk_criti; 477 } body; 478 }; 479 480 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ 481 enum amd_sriov_gpu_init_data_version { 482 GPU_INIT_DATA_READY_V1 = 1, 483 }; 484 485 #pragma pack(pop) // Restore previous packing option 486 487 /* checksum function between host and guest */ 488 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key, 489 unsigned int checksum); 490 491 /* assertion at compile time */ 492 #ifdef __linux__ 493 #define stringification(s) _stringification(s) 494 #define _stringification(s) #s 495 496 _Static_assert( 497 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 498 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 499 500 _Static_assert( 501 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 502 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 503 504 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, 505 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4"); 506 507 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, 508 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); 509 510 #undef _stringification 511 #undef stringification 512 #endif 513 514 #endif /* AMDGV_SRIOV_MSG__H_ */ 515