1 /* 2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #ifndef AMDGV_SRIOV_MSG__H_ 24 #define AMDGV_SRIOV_MSG__H_ 25 26 /* unit in kilobytes */ 27 #define AMD_SRIOV_MSG_VBIOS_OFFSET 0 28 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 29 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB 30 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 31 32 /* 33 * layout 34 * 0 64KB 65KB 66KB 35 * | VBIOS | PF2VF | VF2PF | Bad Page | ... 36 * | 64KB | 1KB | 1KB | 37 */ 38 #define AMD_SRIOV_MSG_SIZE_KB 1 39 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB 40 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 41 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 42 43 /* 44 * PF2VF history log: 45 * v1 defined in amdgim 46 * v2 current 47 * 48 * VF2PF history log: 49 * v1 defined in amdgim 50 * v2 defined in amdgim 51 * v3 current 52 */ 53 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2 54 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3 55 56 #define AMD_SRIOV_MSG_RESERVE_UCODE 24 57 58 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 59 60 enum amd_sriov_ucode_engine_id { 61 AMD_SRIOV_UCODE_ID_VCE = 0, 62 AMD_SRIOV_UCODE_ID_UVD, 63 AMD_SRIOV_UCODE_ID_MC, 64 AMD_SRIOV_UCODE_ID_ME, 65 AMD_SRIOV_UCODE_ID_PFP, 66 AMD_SRIOV_UCODE_ID_CE, 67 AMD_SRIOV_UCODE_ID_RLC, 68 AMD_SRIOV_UCODE_ID_RLC_SRLC, 69 AMD_SRIOV_UCODE_ID_RLC_SRLG, 70 AMD_SRIOV_UCODE_ID_RLC_SRLS, 71 AMD_SRIOV_UCODE_ID_MEC, 72 AMD_SRIOV_UCODE_ID_MEC2, 73 AMD_SRIOV_UCODE_ID_SOS, 74 AMD_SRIOV_UCODE_ID_ASD, 75 AMD_SRIOV_UCODE_ID_TA_RAS, 76 AMD_SRIOV_UCODE_ID_TA_XGMI, 77 AMD_SRIOV_UCODE_ID_SMC, 78 AMD_SRIOV_UCODE_ID_SDMA, 79 AMD_SRIOV_UCODE_ID_SDMA2, 80 AMD_SRIOV_UCODE_ID_VCN, 81 AMD_SRIOV_UCODE_ID_DMCU, 82 AMD_SRIOV_UCODE_ID__MAX 83 }; 84 85 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed 86 87 union amd_sriov_msg_feature_flags { 88 struct { 89 uint32_t error_log_collect : 1; 90 uint32_t host_load_ucodes : 1; 91 uint32_t host_flr_vramlost : 1; 92 uint32_t mm_bw_management : 1; 93 uint32_t pp_one_vf_mode : 1; 94 uint32_t reg_indirect_acc : 1; 95 uint32_t av1_support : 1; 96 uint32_t vcn_rb_decouple : 1; 97 uint32_t mes_info_enable : 1; 98 uint32_t reserved : 23; 99 } flags; 100 uint32_t all; 101 }; 102 103 union amd_sriov_reg_access_flags { 104 struct { 105 uint32_t vf_reg_access_ih : 1; 106 uint32_t vf_reg_access_mmhub : 1; 107 uint32_t vf_reg_access_gc : 1; 108 uint32_t reserved : 29; 109 } flags; 110 uint32_t all; 111 }; 112 113 union amd_sriov_msg_os_info { 114 struct { 115 uint32_t windows : 1; 116 uint32_t reserved : 31; 117 } info; 118 uint32_t all; 119 }; 120 121 struct amd_sriov_msg_uuid_info { 122 union { 123 struct { 124 uint32_t did : 16; 125 uint32_t fcn : 8; 126 uint32_t asic_7 : 8; 127 }; 128 uint32_t time_low; 129 }; 130 131 struct { 132 uint32_t time_mid : 16; 133 uint32_t time_high : 12; 134 uint32_t version : 4; 135 }; 136 137 struct { 138 struct { 139 uint8_t clk_seq_hi : 6; 140 uint8_t variant : 2; 141 }; 142 union { 143 uint8_t clk_seq_low; 144 uint8_t asic_6; 145 }; 146 uint16_t asic_4; 147 }; 148 149 uint32_t asic_0; 150 }; 151 152 struct amd_sriov_msg_pf2vf_info_header { 153 /* the total structure size in byte */ 154 uint32_t size; 155 /* version of this structure, written by the HOST */ 156 uint32_t version; 157 /* reserved */ 158 uint32_t reserved[2]; 159 }; 160 161 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (49) 162 struct amd_sriov_msg_pf2vf_info { 163 /* header contains size and version */ 164 struct amd_sriov_msg_pf2vf_info_header header; 165 /* use private key from mailbox 2 to create checksum */ 166 uint32_t checksum; 167 /* The features flags of the HOST driver supports */ 168 union amd_sriov_msg_feature_flags feature_flags; 169 /* (max_width * max_height * fps) / (16 * 16) */ 170 uint32_t hevc_enc_max_mb_per_second; 171 /* (max_width * max_height) / (16 * 16) */ 172 uint32_t hevc_enc_max_mb_per_frame; 173 /* (max_width * max_height * fps) / (16 * 16) */ 174 uint32_t avc_enc_max_mb_per_second; 175 /* (max_width * max_height) / (16 * 16) */ 176 uint32_t avc_enc_max_mb_per_frame; 177 /* MEC FW position in BYTE from the start of VF visible frame buffer */ 178 uint64_t mecfw_offset; 179 /* MEC FW size in BYTE */ 180 uint32_t mecfw_size; 181 /* UVD FW position in BYTE from the start of VF visible frame buffer */ 182 uint64_t uvdfw_offset; 183 /* UVD FW size in BYTE */ 184 uint32_t uvdfw_size; 185 /* VCE FW position in BYTE from the start of VF visible frame buffer */ 186 uint64_t vcefw_offset; 187 /* VCE FW size in BYTE */ 188 uint32_t vcefw_size; 189 /* Bad pages block position in BYTE */ 190 uint32_t bp_block_offset_low; 191 uint32_t bp_block_offset_high; 192 /* Bad pages block size in BYTE */ 193 uint32_t bp_block_size; 194 /* frequency for VF to update the VF2PF area in msec, 0 = manual */ 195 uint32_t vf2pf_update_interval_ms; 196 /* identification in ROCm SMI */ 197 uint64_t uuid; 198 uint32_t fcn_idx; 199 /* flags to indicate which register access method VF should use */ 200 union amd_sriov_reg_access_flags reg_access_flags; 201 /* MM BW management */ 202 struct { 203 uint32_t decode_max_dimension_pixels; 204 uint32_t decode_max_frame_pixels; 205 uint32_t encode_max_dimension_pixels; 206 uint32_t encode_max_frame_pixels; 207 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; 208 /* UUID info */ 209 struct amd_sriov_msg_uuid_info uuid_info; 210 /* PCIE atomic ops support flag */ 211 uint32_t pcie_atomic_ops_support_flags; 212 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */ 213 uint32_t gpu_capacity; 214 /* reserved */ 215 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; 216 }; 217 218 struct amd_sriov_msg_vf2pf_info_header { 219 /* the total structure size in byte */ 220 uint32_t size; 221 /* version of this structure, written by the guest */ 222 uint32_t version; 223 /* reserved */ 224 uint32_t reserved[2]; 225 }; 226 227 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73) 228 struct amd_sriov_msg_vf2pf_info { 229 /* header contains size and version */ 230 struct amd_sriov_msg_vf2pf_info_header header; 231 uint32_t checksum; 232 /* driver version */ 233 uint8_t driver_version[64]; 234 /* driver certification, 1=WHQL, 0=None */ 235 uint32_t driver_cert; 236 /* guest OS type and version */ 237 union amd_sriov_msg_os_info os_info; 238 /* guest fb information in the unit of MB */ 239 uint32_t fb_usage; 240 /* guest gfx engine usage percentage */ 241 uint32_t gfx_usage; 242 /* guest gfx engine health percentage */ 243 uint32_t gfx_health; 244 /* guest compute engine usage percentage */ 245 uint32_t compute_usage; 246 /* guest compute engine health percentage */ 247 uint32_t compute_health; 248 /* guest avc engine usage percentage. 0xffff means N/A */ 249 uint32_t avc_enc_usage; 250 /* guest avc engine health percentage. 0xffff means N/A */ 251 uint32_t avc_enc_health; 252 /* guest hevc engine usage percentage. 0xffff means N/A */ 253 uint32_t hevc_enc_usage; 254 /* guest hevc engine usage percentage. 0xffff means N/A */ 255 uint32_t hevc_enc_health; 256 /* combined encode/decode usage */ 257 uint32_t encode_usage; 258 uint32_t decode_usage; 259 /* Version of PF2VF that VF understands */ 260 uint32_t pf2vf_version_required; 261 /* additional FB usage */ 262 uint32_t fb_vis_usage; 263 uint32_t fb_vis_size; 264 uint32_t fb_size; 265 /* guest ucode data, each one is 1.25 Dword */ 266 struct { 267 uint8_t id; 268 uint32_t version; 269 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE]; 270 uint64_t dummy_page_addr; 271 /* FB allocated for guest MES to record UQ info */ 272 uint64_t mes_info_addr; 273 uint32_t mes_info_size; 274 /* reserved */ 275 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE]; 276 }; 277 278 /* mailbox message send from guest to host */ 279 enum amd_sriov_mailbox_request_message { 280 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1, 281 MB_REQ_MSG_REL_GPU_INIT_ACCESS, 282 MB_REQ_MSG_REQ_GPU_FINI_ACCESS, 283 MB_REQ_MSG_REL_GPU_FINI_ACCESS, 284 MB_REQ_MSG_REQ_GPU_RESET_ACCESS, 285 MB_REQ_MSG_REQ_GPU_INIT_DATA, 286 287 MB_REQ_MSG_LOG_VF_ERROR = 200, 288 }; 289 290 /* mailbox message send from host to guest */ 291 enum amd_sriov_mailbox_response_message { 292 MB_RES_MSG_CLR_MSG_BUF = 0, 293 MB_RES_MSG_READY_TO_ACCESS_GPU = 1, 294 MB_RES_MSG_FLR_NOTIFICATION, 295 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION, 296 MB_RES_MSG_SUCCESS, 297 MB_RES_MSG_FAIL, 298 MB_RES_MSG_QUERY_ALIVE, 299 MB_RES_MSG_GPU_INIT_DATA_READY, 300 301 MB_RES_MSG_TEXT_MESSAGE = 255 302 }; 303 304 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ 305 enum amd_sriov_gpu_init_data_version { 306 GPU_INIT_DATA_READY_V1 = 1, 307 }; 308 309 #pragma pack(pop) // Restore previous packing option 310 311 /* checksum function between host and guest */ 312 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key, 313 unsigned int checksum); 314 315 /* assertion at compile time */ 316 #ifdef __linux__ 317 #define stringification(s) _stringification(s) 318 #define _stringification(s) #s 319 320 _Static_assert( 321 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 322 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 323 324 _Static_assert( 325 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 326 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 327 328 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, 329 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4"); 330 331 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, 332 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); 333 334 #undef _stringification 335 #undef stringification 336 #endif 337 338 #endif /* AMDGV_SRIOV_MSG__H_ */ 339