1 /* 2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #ifndef AMDGV_SRIOV_MSG__H_ 24 #define AMDGV_SRIOV_MSG__H_ 25 26 /* unit in kilobytes */ 27 #define AMD_SRIOV_MSG_VBIOS_OFFSET 0 28 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 29 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB 30 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 31 #define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 32 #define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB 2 33 #define AMD_SRIOV_RAS_TELEMETRY_SIZE_KB 64 34 /* 35 * layout 36 * 0 64KB 65KB 66KB 68KB 132KB 37 * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... 38 * | 64KB | 1KB | 1KB | 2KB | 64KB | ... 39 */ 40 41 #define AMD_SRIOV_MSG_SIZE_KB 1 42 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB 43 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 44 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) 45 #define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB) 46 47 /* 48 * PF2VF history log: 49 * v1 defined in amdgim 50 * v2 current 51 * 52 * VF2PF history log: 53 * v1 defined in amdgim 54 * v2 defined in amdgim 55 * v3 current 56 */ 57 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2 58 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3 59 60 #define AMD_SRIOV_MSG_RESERVE_UCODE 24 61 62 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4 63 64 enum amd_sriov_ucode_engine_id { 65 AMD_SRIOV_UCODE_ID_VCE = 0, 66 AMD_SRIOV_UCODE_ID_UVD, 67 AMD_SRIOV_UCODE_ID_MC, 68 AMD_SRIOV_UCODE_ID_ME, 69 AMD_SRIOV_UCODE_ID_PFP, 70 AMD_SRIOV_UCODE_ID_CE, 71 AMD_SRIOV_UCODE_ID_RLC, 72 AMD_SRIOV_UCODE_ID_RLC_SRLC, 73 AMD_SRIOV_UCODE_ID_RLC_SRLG, 74 AMD_SRIOV_UCODE_ID_RLC_SRLS, 75 AMD_SRIOV_UCODE_ID_MEC, 76 AMD_SRIOV_UCODE_ID_MEC2, 77 AMD_SRIOV_UCODE_ID_SOS, 78 AMD_SRIOV_UCODE_ID_ASD, 79 AMD_SRIOV_UCODE_ID_TA_RAS, 80 AMD_SRIOV_UCODE_ID_TA_XGMI, 81 AMD_SRIOV_UCODE_ID_SMC, 82 AMD_SRIOV_UCODE_ID_SDMA, 83 AMD_SRIOV_UCODE_ID_SDMA2, 84 AMD_SRIOV_UCODE_ID_VCN, 85 AMD_SRIOV_UCODE_ID_DMCU, 86 AMD_SRIOV_UCODE_ID__MAX 87 }; 88 89 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed 90 91 union amd_sriov_msg_feature_flags { 92 struct { 93 uint32_t error_log_collect : 1; 94 uint32_t host_load_ucodes : 1; 95 uint32_t host_flr_vramlost : 1; 96 uint32_t mm_bw_management : 1; 97 uint32_t pp_one_vf_mode : 1; 98 uint32_t reg_indirect_acc : 1; 99 uint32_t av1_support : 1; 100 uint32_t vcn_rb_decouple : 1; 101 uint32_t mes_info_dump_enable : 1; 102 uint32_t ras_caps : 1; 103 uint32_t ras_telemetry : 1; 104 uint32_t ras_cper : 1; 105 uint32_t reserved : 20; 106 } flags; 107 uint32_t all; 108 }; 109 110 union amd_sriov_reg_access_flags { 111 struct { 112 uint32_t vf_reg_access_ih : 1; 113 uint32_t vf_reg_access_mmhub : 1; 114 uint32_t vf_reg_access_gc : 1; 115 uint32_t vf_reg_access_l1_tlb_cntl : 1; 116 uint32_t reserved : 28; 117 } flags; 118 uint32_t all; 119 }; 120 121 union amd_sriov_ras_caps { 122 struct { 123 uint64_t block_umc : 1; 124 uint64_t block_sdma : 1; 125 uint64_t block_gfx : 1; 126 uint64_t block_mmhub : 1; 127 uint64_t block_athub : 1; 128 uint64_t block_pcie_bif : 1; 129 uint64_t block_hdp : 1; 130 uint64_t block_xgmi_wafl : 1; 131 uint64_t block_df : 1; 132 uint64_t block_smn : 1; 133 uint64_t block_sem : 1; 134 uint64_t block_mp0 : 1; 135 uint64_t block_mp1 : 1; 136 uint64_t block_fuse : 1; 137 uint64_t block_mca : 1; 138 uint64_t block_vcn : 1; 139 uint64_t block_jpeg : 1; 140 uint64_t block_ih : 1; 141 uint64_t block_mpio : 1; 142 uint64_t poison_propogation_mode : 1; 143 uint64_t reserved : 44; 144 } bits; 145 uint64_t all; 146 }; 147 148 union amd_sriov_msg_os_info { 149 struct { 150 uint32_t windows : 1; 151 uint32_t reserved : 31; 152 } info; 153 uint32_t all; 154 }; 155 156 struct amd_sriov_msg_uuid_info { 157 union { 158 struct { 159 uint32_t did : 16; 160 uint32_t fcn : 8; 161 uint32_t asic_7 : 8; 162 }; 163 uint32_t time_low; 164 }; 165 166 struct { 167 uint32_t time_mid : 16; 168 uint32_t time_high : 12; 169 uint32_t version : 4; 170 }; 171 172 struct { 173 struct { 174 uint8_t clk_seq_hi : 6; 175 uint8_t variant : 2; 176 }; 177 union { 178 uint8_t clk_seq_low; 179 uint8_t asic_6; 180 }; 181 uint16_t asic_4; 182 }; 183 184 uint32_t asic_0; 185 }; 186 187 struct amd_sriov_msg_pf2vf_info_header { 188 /* the total structure size in byte */ 189 uint32_t size; 190 /* version of this structure, written by the HOST */ 191 uint32_t version; 192 /* reserved */ 193 uint32_t reserved[2]; 194 }; 195 196 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) 197 struct amd_sriov_msg_pf2vf_info { 198 /* header contains size and version */ 199 struct amd_sriov_msg_pf2vf_info_header header; 200 /* use private key from mailbox 2 to create checksum */ 201 uint32_t checksum; 202 /* The features flags of the HOST driver supports */ 203 union amd_sriov_msg_feature_flags feature_flags; 204 /* (max_width * max_height * fps) / (16 * 16) */ 205 uint32_t hevc_enc_max_mb_per_second; 206 /* (max_width * max_height) / (16 * 16) */ 207 uint32_t hevc_enc_max_mb_per_frame; 208 /* (max_width * max_height * fps) / (16 * 16) */ 209 uint32_t avc_enc_max_mb_per_second; 210 /* (max_width * max_height) / (16 * 16) */ 211 uint32_t avc_enc_max_mb_per_frame; 212 /* MEC FW position in BYTE from the start of VF visible frame buffer */ 213 uint64_t mecfw_offset; 214 /* MEC FW size in BYTE */ 215 uint32_t mecfw_size; 216 /* UVD FW position in BYTE from the start of VF visible frame buffer */ 217 uint64_t uvdfw_offset; 218 /* UVD FW size in BYTE */ 219 uint32_t uvdfw_size; 220 /* VCE FW position in BYTE from the start of VF visible frame buffer */ 221 uint64_t vcefw_offset; 222 /* VCE FW size in BYTE */ 223 uint32_t vcefw_size; 224 /* Bad pages block position in BYTE */ 225 uint32_t bp_block_offset_low; 226 uint32_t bp_block_offset_high; 227 /* Bad pages block size in BYTE */ 228 uint32_t bp_block_size; 229 /* frequency for VF to update the VF2PF area in msec, 0 = manual */ 230 uint32_t vf2pf_update_interval_ms; 231 /* identification in ROCm SMI */ 232 uint64_t uuid; 233 uint32_t fcn_idx; 234 /* flags to indicate which register access method VF should use */ 235 union amd_sriov_reg_access_flags reg_access_flags; 236 /* MM BW management */ 237 struct { 238 uint32_t decode_max_dimension_pixels; 239 uint32_t decode_max_frame_pixels; 240 uint32_t encode_max_dimension_pixels; 241 uint32_t encode_max_frame_pixels; 242 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST]; 243 /* UUID info */ 244 struct amd_sriov_msg_uuid_info uuid_info; 245 /* PCIE atomic ops support flag */ 246 uint32_t pcie_atomic_ops_support_flags; 247 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */ 248 uint32_t gpu_capacity; 249 /* vf bdf on host pci tree for debug only */ 250 uint32_t bdf_on_host; 251 uint32_t more_bp; //Reserved for future use. 252 union amd_sriov_ras_caps ras_en_caps; 253 union amd_sriov_ras_caps ras_telemetry_en_caps; 254 255 /* reserved */ 256 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; 257 } __packed; 258 259 struct amd_sriov_msg_vf2pf_info_header { 260 /* the total structure size in byte */ 261 uint32_t size; 262 /* version of this structure, written by the guest */ 263 uint32_t version; 264 /* reserved */ 265 uint32_t reserved[2]; 266 }; 267 268 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73) 269 struct amd_sriov_msg_vf2pf_info { 270 /* header contains size and version */ 271 struct amd_sriov_msg_vf2pf_info_header header; 272 uint32_t checksum; 273 /* driver version */ 274 uint8_t driver_version[64]; 275 /* driver certification, 1=WHQL, 0=None */ 276 uint32_t driver_cert; 277 /* guest OS type and version */ 278 union amd_sriov_msg_os_info os_info; 279 /* guest fb information in the unit of MB */ 280 uint32_t fb_usage; 281 /* guest gfx engine usage percentage */ 282 uint32_t gfx_usage; 283 /* guest gfx engine health percentage */ 284 uint32_t gfx_health; 285 /* guest compute engine usage percentage */ 286 uint32_t compute_usage; 287 /* guest compute engine health percentage */ 288 uint32_t compute_health; 289 /* guest avc engine usage percentage. 0xffff means N/A */ 290 uint32_t avc_enc_usage; 291 /* guest avc engine health percentage. 0xffff means N/A */ 292 uint32_t avc_enc_health; 293 /* guest hevc engine usage percentage. 0xffff means N/A */ 294 uint32_t hevc_enc_usage; 295 /* guest hevc engine usage percentage. 0xffff means N/A */ 296 uint32_t hevc_enc_health; 297 /* combined encode/decode usage */ 298 uint32_t encode_usage; 299 uint32_t decode_usage; 300 /* Version of PF2VF that VF understands */ 301 uint32_t pf2vf_version_required; 302 /* additional FB usage */ 303 uint32_t fb_vis_usage; 304 uint32_t fb_vis_size; 305 uint32_t fb_size; 306 /* guest ucode data, each one is 1.25 Dword */ 307 struct { 308 uint8_t id; 309 uint32_t version; 310 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE]; 311 uint64_t dummy_page_addr; 312 /* FB allocated for guest MES to record UQ info */ 313 uint64_t mes_info_addr; 314 uint32_t mes_info_size; 315 /* reserved */ 316 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE]; 317 } __packed; 318 319 /* mailbox message send from guest to host */ 320 enum amd_sriov_mailbox_request_message { 321 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1, 322 MB_REQ_MSG_REL_GPU_INIT_ACCESS, 323 MB_REQ_MSG_REQ_GPU_FINI_ACCESS, 324 MB_REQ_MSG_REL_GPU_FINI_ACCESS, 325 MB_REQ_MSG_REQ_GPU_RESET_ACCESS, 326 MB_REQ_MSG_REQ_GPU_INIT_DATA, 327 MB_REQ_MSG_PSP_VF_CMD_RELAY, 328 329 MB_REQ_MSG_LOG_VF_ERROR = 200, 330 MB_REQ_MSG_READY_TO_RESET = 201, 331 MB_REQ_MSG_RAS_POISON = 202, 332 MB_REQ_RAS_ERROR_COUNT = 203, 333 MB_REQ_RAS_CPER_DUMP = 204, 334 MB_REQ_RAS_BAD_PAGES = 205, 335 }; 336 337 /* mailbox message send from host to guest */ 338 enum amd_sriov_mailbox_response_message { 339 MB_RES_MSG_CLR_MSG_BUF = 0, 340 MB_RES_MSG_READY_TO_ACCESS_GPU = 1, 341 MB_RES_MSG_FLR_NOTIFICATION = 2, 342 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION = 3, 343 MB_RES_MSG_SUCCESS = 4, 344 MB_RES_MSG_FAIL = 5, 345 MB_RES_MSG_QUERY_ALIVE = 6, 346 MB_RES_MSG_GPU_INIT_DATA_READY = 7, 347 MB_RES_MSG_RAS_POISON_READY = 8, 348 MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION = 9, 349 MB_RES_MSG_GPU_RMA = 10, 350 MB_RES_MSG_RAS_ERROR_COUNT_READY = 11, 351 MB_REQ_RAS_CPER_DUMP_READY = 14, 352 MB_RES_MSG_RAS_BAD_PAGES_READY = 15, 353 MB_RES_MSG_RAS_BAD_PAGES_NOTIFICATION = 16, 354 MB_RES_MSG_UNRECOV_ERR_NOTIFICATION = 17, 355 MB_RES_MSG_TEXT_MESSAGE = 255 356 }; 357 358 enum amd_sriov_ras_telemetry_gpu_block { 359 RAS_TELEMETRY_GPU_BLOCK_UMC = 0, 360 RAS_TELEMETRY_GPU_BLOCK_SDMA = 1, 361 RAS_TELEMETRY_GPU_BLOCK_GFX = 2, 362 RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3, 363 RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4, 364 RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5, 365 RAS_TELEMETRY_GPU_BLOCK_HDP = 6, 366 RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7, 367 RAS_TELEMETRY_GPU_BLOCK_DF = 8, 368 RAS_TELEMETRY_GPU_BLOCK_SMN = 9, 369 RAS_TELEMETRY_GPU_BLOCK_SEM = 10, 370 RAS_TELEMETRY_GPU_BLOCK_MP0 = 11, 371 RAS_TELEMETRY_GPU_BLOCK_MP1 = 12, 372 RAS_TELEMETRY_GPU_BLOCK_FUSE = 13, 373 RAS_TELEMETRY_GPU_BLOCK_MCA = 14, 374 RAS_TELEMETRY_GPU_BLOCK_VCN = 15, 375 RAS_TELEMETRY_GPU_BLOCK_JPEG = 16, 376 RAS_TELEMETRY_GPU_BLOCK_IH = 17, 377 RAS_TELEMETRY_GPU_BLOCK_MPIO = 18, 378 RAS_TELEMETRY_GPU_BLOCK_COUNT = 19, 379 }; 380 381 struct amd_sriov_ras_telemetry_header { 382 uint32_t checksum; 383 uint32_t used_size; 384 uint32_t reserved[2]; 385 }; 386 387 struct amd_sriov_ras_telemetry_error_count { 388 struct { 389 uint32_t ce_count; 390 uint32_t ue_count; 391 uint32_t de_count; 392 uint32_t ce_overflow_count; 393 uint32_t ue_overflow_count; 394 uint32_t de_overflow_count; 395 uint32_t reserved[6]; 396 } block[RAS_TELEMETRY_GPU_BLOCK_COUNT]; 397 }; 398 399 struct amd_sriov_ras_cper_dump { 400 uint32_t more; 401 uint64_t overflow_count; 402 uint64_t count; 403 uint64_t wptr; 404 uint32_t buf[]; 405 }; 406 407 struct amdsriov_ras_telemetry { 408 struct amd_sriov_ras_telemetry_header header; 409 410 union { 411 struct amd_sriov_ras_telemetry_error_count error_count; 412 struct amd_sriov_ras_cper_dump cper_dump; 413 } body; 414 }; 415 416 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ 417 enum amd_sriov_gpu_init_data_version { 418 GPU_INIT_DATA_READY_V1 = 1, 419 }; 420 421 #pragma pack(pop) // Restore previous packing option 422 423 /* checksum function between host and guest */ 424 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key, 425 unsigned int checksum); 426 427 /* assertion at compile time */ 428 #ifdef __linux__ 429 #define stringification(s) _stringification(s) 430 #define _stringification(s) #s 431 432 _Static_assert( 433 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 434 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 435 436 _Static_assert( 437 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10, 438 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB"); 439 440 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, 441 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4"); 442 443 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, 444 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); 445 446 #undef _stringification 447 #undef stringification 448 #endif 449 450 #endif /* AMDGV_SRIOV_MSG__H_ */ 451