1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "xgmi/xgmi_6_1_0_sh_mask.h" 33 #include "wafl/wafl2_4_0_0_smn.h" 34 #include "wafl/wafl2_4_0_0_sh_mask.h" 35 36 #include "amdgpu_reset.h" 37 38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK 0x11a00218 40 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK 0x12200218 42 43 #define XGMI_STATE_DISABLE 0xD1 44 #define XGMI_STATE_LS0 0x81 45 #define XGMI_LINK_ACTIVE 1 46 #define XGMI_LINK_INACTIVE 0 47 48 static DEFINE_MUTEX(xgmi_mutex); 49 50 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 51 52 static LIST_HEAD(xgmi_hive_list); 53 54 static const int xgmi_pcs_err_status_reg_vg20[] = { 55 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 57 }; 58 59 static const int wafl_pcs_err_status_reg_vg20[] = { 60 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 61 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 62 }; 63 64 static const int xgmi_pcs_err_status_reg_arct[] = { 65 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 66 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 67 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 68 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 69 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 70 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 71 }; 72 73 /* same as vg20*/ 74 static const int wafl_pcs_err_status_reg_arct[] = { 75 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 76 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 77 }; 78 79 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 80 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 81 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 83 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 84 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 85 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 86 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 87 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 88 }; 89 90 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 91 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK, 92 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000, 93 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000, 94 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000, 95 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000, 96 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000, 97 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000, 98 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000 99 }; 100 101 static const int walf_pcs_err_status_reg_aldebaran[] = { 102 smnPCS_GOPX1_PCS_ERROR_STATUS, 103 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 104 }; 105 106 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 107 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK, 108 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 109 }; 110 111 static const int xgmi3x16_pcs_err_status_reg_v6_4[] = { 112 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 113 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000 114 }; 115 116 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[] = { 117 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK, 118 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 119 }; 120 121 static const u64 xgmi_v6_4_0_mca_base_array[] = { 122 0x11a09200, 123 0x11b09200, 124 }; 125 126 static const char *xgmi_v6_4_0_ras_error_code_ext[32] = { 127 [0x00] = "XGMI PCS DataLossErr", 128 [0x01] = "XGMI PCS TrainingErr", 129 [0x02] = "XGMI PCS FlowCtrlAckErr", 130 [0x03] = "XGMI PCS RxFifoUnderflowErr", 131 [0x04] = "XGMI PCS RxFifoOverflowErr", 132 [0x05] = "XGMI PCS CRCErr", 133 [0x06] = "XGMI PCS BERExceededErr", 134 [0x07] = "XGMI PCS TxMetaDataErr", 135 [0x08] = "XGMI PCS ReplayBufParityErr", 136 [0x09] = "XGMI PCS DataParityErr", 137 [0x0a] = "XGMI PCS ReplayFifoOverflowErr", 138 [0x0b] = "XGMI PCS ReplayFifoUnderflowErr", 139 [0x0c] = "XGMI PCS ElasticFifoOverflowErr", 140 [0x0d] = "XGMI PCS DeskewErr", 141 [0x0e] = "XGMI PCS FlowCtrlCRCErr", 142 [0x0f] = "XGMI PCS DataStartupLimitErr", 143 [0x10] = "XGMI PCS FCInitTimeoutErr", 144 [0x11] = "XGMI PCS RecoveryTimeoutErr", 145 [0x12] = "XGMI PCS ReadySerialTimeoutErr", 146 [0x13] = "XGMI PCS ReadySerialAttemptErr", 147 [0x14] = "XGMI PCS RecoveryAttemptErr", 148 [0x15] = "XGMI PCS RecoveryRelockAttemptErr", 149 [0x16] = "XGMI PCS ReplayAttemptErr", 150 [0x17] = "XGMI PCS SyncHdrErr", 151 [0x18] = "XGMI PCS TxReplayTimeoutErr", 152 [0x19] = "XGMI PCS RxReplayTimeoutErr", 153 [0x1a] = "XGMI PCS LinkSubTxTimeoutErr", 154 [0x1b] = "XGMI PCS LinkSubRxTimeoutErr", 155 [0x1c] = "XGMI PCS RxCMDPktErr", 156 }; 157 158 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 159 {"XGMI PCS DataLossErr", 160 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 161 {"XGMI PCS TrainingErr", 162 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 163 {"XGMI PCS CRCErr", 164 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 165 {"XGMI PCS BERExceededErr", 166 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 167 {"XGMI PCS TxMetaDataErr", 168 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 169 {"XGMI PCS ReplayBufParityErr", 170 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 171 {"XGMI PCS DataParityErr", 172 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 173 {"XGMI PCS ReplayFifoOverflowErr", 174 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 175 {"XGMI PCS ReplayFifoUnderflowErr", 176 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 177 {"XGMI PCS ElasticFifoOverflowErr", 178 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 179 {"XGMI PCS DeskewErr", 180 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 181 {"XGMI PCS DataStartupLimitErr", 182 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 183 {"XGMI PCS FCInitTimeoutErr", 184 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 185 {"XGMI PCS RecoveryTimeoutErr", 186 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 187 {"XGMI PCS ReadySerialTimeoutErr", 188 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 189 {"XGMI PCS ReadySerialAttemptErr", 190 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 191 {"XGMI PCS RecoveryAttemptErr", 192 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 193 {"XGMI PCS RecoveryRelockAttemptErr", 194 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 195 }; 196 197 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 198 {"WAFL PCS DataLossErr", 199 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 200 {"WAFL PCS TrainingErr", 201 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 202 {"WAFL PCS CRCErr", 203 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 204 {"WAFL PCS BERExceededErr", 205 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 206 {"WAFL PCS TxMetaDataErr", 207 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 208 {"WAFL PCS ReplayBufParityErr", 209 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 210 {"WAFL PCS DataParityErr", 211 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 212 {"WAFL PCS ReplayFifoOverflowErr", 213 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 214 {"WAFL PCS ReplayFifoUnderflowErr", 215 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 216 {"WAFL PCS ElasticFifoOverflowErr", 217 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 218 {"WAFL PCS DeskewErr", 219 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 220 {"WAFL PCS DataStartupLimitErr", 221 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 222 {"WAFL PCS FCInitTimeoutErr", 223 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 224 {"WAFL PCS RecoveryTimeoutErr", 225 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 226 {"WAFL PCS ReadySerialTimeoutErr", 227 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 228 {"WAFL PCS ReadySerialAttemptErr", 229 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 230 {"WAFL PCS RecoveryAttemptErr", 231 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 232 {"WAFL PCS RecoveryRelockAttemptErr", 233 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 234 }; 235 236 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = { 237 {"XGMI3X16 PCS DataLossErr", 238 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)}, 239 {"XGMI3X16 PCS TrainingErr", 240 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)}, 241 {"XGMI3X16 PCS FlowCtrlAckErr", 242 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)}, 243 {"XGMI3X16 PCS RxFifoUnderflowErr", 244 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)}, 245 {"XGMI3X16 PCS RxFifoOverflowErr", 246 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)}, 247 {"XGMI3X16 PCS CRCErr", 248 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)}, 249 {"XGMI3X16 PCS BERExceededErr", 250 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)}, 251 {"XGMI3X16 PCS TxVcidDataErr", 252 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)}, 253 {"XGMI3X16 PCS ReplayBufParityErr", 254 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 255 {"XGMI3X16 PCS DataParityErr", 256 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)}, 257 {"XGMI3X16 PCS ReplayFifoOverflowErr", 258 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 259 {"XGMI3X16 PCS ReplayFifoUnderflowErr", 260 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 261 {"XGMI3X16 PCS ElasticFifoOverflowErr", 262 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 263 {"XGMI3X16 PCS DeskewErr", 264 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)}, 265 {"XGMI3X16 PCS FlowCtrlCRCErr", 266 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)}, 267 {"XGMI3X16 PCS DataStartupLimitErr", 268 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 269 {"XGMI3X16 PCS FCInitTimeoutErr", 270 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 271 {"XGMI3X16 PCS RecoveryTimeoutErr", 272 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 273 {"XGMI3X16 PCS ReadySerialTimeoutErr", 274 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 275 {"XGMI3X16 PCS ReadySerialAttemptErr", 276 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 277 {"XGMI3X16 PCS RecoveryAttemptErr", 278 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 279 {"XGMI3X16 PCS RecoveryRelockAttemptErr", 280 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 281 {"XGMI3X16 PCS ReplayAttemptErr", 282 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)}, 283 {"XGMI3X16 PCS SyncHdrErr", 284 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)}, 285 {"XGMI3X16 PCS TxReplayTimeoutErr", 286 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)}, 287 {"XGMI3X16 PCS RxReplayTimeoutErr", 288 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)}, 289 {"XGMI3X16 PCS LinkSubTxTimeoutErr", 290 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)}, 291 {"XGMI3X16 PCS LinkSubRxTimeoutErr", 292 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)}, 293 {"XGMI3X16 PCS RxCMDPktErr", 294 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)}, 295 }; 296 297 static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link_num) 298 { 299 const u32 smn_xgmi_6_4_pcs_state_hist1[2] = { 0x11a00070, 0x11b00070 }; 300 const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x11b00070, 301 0x12100070 }; 302 u32 i, n; 303 u64 addr; 304 305 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 306 case IP_VERSION(6, 4, 0): 307 n = ARRAY_SIZE(smn_xgmi_6_4_pcs_state_hist1); 308 addr = smn_xgmi_6_4_pcs_state_hist1[global_link_num % n]; 309 break; 310 case IP_VERSION(6, 4, 1): 311 n = ARRAY_SIZE(smn_xgmi_6_4_1_pcs_state_hist1); 312 addr = smn_xgmi_6_4_1_pcs_state_hist1[global_link_num % n]; 313 break; 314 default: 315 return U32_MAX; 316 } 317 318 i = global_link_num / n; 319 addr += adev->asic_funcs->encode_ext_smn_addressing(i); 320 321 return RREG32_PCIE_EXT(addr); 322 } 323 324 int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) 325 { 326 u32 xgmi_state_reg_val; 327 328 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 329 case IP_VERSION(6, 4, 0): 330 case IP_VERSION(6, 4, 1): 331 xgmi_state_reg_val = xgmi_v6_4_get_link_status(adev, global_link_num); 332 break; 333 default: 334 return -EOPNOTSUPP; 335 } 336 337 if ((xgmi_state_reg_val & 0xFF) == XGMI_STATE_DISABLE) 338 return -ENOLINK; 339 340 if ((xgmi_state_reg_val & 0xFF) == XGMI_STATE_LS0) 341 return XGMI_LINK_ACTIVE; 342 343 return XGMI_LINK_INACTIVE; 344 } 345 346 /** 347 * DOC: AMDGPU XGMI Support 348 * 349 * XGMI is a high speed interconnect that joins multiple GPU cards 350 * into a homogeneous memory space that is organized by a collective 351 * hive ID and individual node IDs, both of which are 64-bit numbers. 352 * 353 * The file xgmi_device_id contains the unique per GPU device ID and 354 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 355 * 356 * Inside the device directory a sub-directory 'xgmi_hive_info' is 357 * created which contains the hive ID and the list of nodes. 358 * 359 * The hive ID is stored in: 360 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 361 * 362 * The node information is stored in numbered directories: 363 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 364 * 365 * Each device has their own xgmi_hive_info direction with a mirror 366 * set of node sub-directories. 367 * 368 * The XGMI memory space is built by contiguously adding the power of 369 * two padded VRAM space from each node to each other. 370 * 371 */ 372 373 static struct attribute amdgpu_xgmi_hive_id = { 374 .name = "xgmi_hive_id", 375 .mode = S_IRUGO 376 }; 377 378 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 379 &amdgpu_xgmi_hive_id, 380 NULL 381 }; 382 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); 383 384 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 385 struct attribute *attr, char *buf) 386 { 387 struct amdgpu_hive_info *hive = container_of( 388 kobj, struct amdgpu_hive_info, kobj); 389 390 if (attr == &amdgpu_xgmi_hive_id) 391 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 392 393 return 0; 394 } 395 396 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 397 { 398 struct amdgpu_hive_info *hive = container_of( 399 kobj, struct amdgpu_hive_info, kobj); 400 401 amdgpu_reset_put_reset_domain(hive->reset_domain); 402 hive->reset_domain = NULL; 403 404 mutex_destroy(&hive->hive_lock); 405 kfree(hive); 406 } 407 408 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 409 .show = amdgpu_xgmi_show_attrs, 410 }; 411 412 static const struct kobj_type amdgpu_xgmi_hive_type = { 413 .release = amdgpu_xgmi_hive_release, 414 .sysfs_ops = &amdgpu_xgmi_hive_ops, 415 .default_groups = amdgpu_xgmi_hive_groups, 416 }; 417 418 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 419 struct device_attribute *attr, 420 char *buf) 421 { 422 struct drm_device *ddev = dev_get_drvdata(dev); 423 struct amdgpu_device *adev = drm_to_adev(ddev); 424 425 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 426 427 } 428 429 static ssize_t amdgpu_xgmi_show_physical_id(struct device *dev, 430 struct device_attribute *attr, 431 char *buf) 432 { 433 struct drm_device *ddev = dev_get_drvdata(dev); 434 struct amdgpu_device *adev = drm_to_adev(ddev); 435 436 return sysfs_emit(buf, "%u\n", adev->gmc.xgmi.physical_node_id); 437 438 } 439 440 static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev, 441 struct device_attribute *attr, 442 char *buf) 443 { 444 struct drm_device *ddev = dev_get_drvdata(dev); 445 struct amdgpu_device *adev = drm_to_adev(ddev); 446 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 447 int i; 448 449 for (i = 0; i < top->num_nodes; i++) 450 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops); 451 452 return sysfs_emit(buf, "%s\n", buf); 453 } 454 455 static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, 456 struct device_attribute *attr, 457 char *buf) 458 { 459 struct drm_device *ddev = dev_get_drvdata(dev); 460 struct amdgpu_device *adev = drm_to_adev(ddev); 461 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 462 int i; 463 464 for (i = 0; i < top->num_nodes; i++) 465 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links); 466 467 return sysfs_emit(buf, "%s\n", buf); 468 } 469 470 static ssize_t amdgpu_xgmi_show_connected_port_num(struct device *dev, 471 struct device_attribute *attr, 472 char *buf) 473 { 474 struct drm_device *ddev = dev_get_drvdata(dev); 475 struct amdgpu_device *adev = drm_to_adev(ddev); 476 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 477 int i, j, size = 0; 478 int current_node; 479 /* 480 * get the node id in the sysfs for the current socket and show 481 * it in the port num info output in the sysfs for easy reading. 482 * it is NOT the one retrieved from xgmi ta. 483 */ 484 for (i = 0; i < top->num_nodes; i++) { 485 if (top->nodes[i].node_id == adev->gmc.xgmi.node_id) { 486 current_node = i; 487 break; 488 } 489 } 490 491 if (i == top->num_nodes) 492 return -EINVAL; 493 494 for (i = 0; i < top->num_nodes; i++) { 495 for (j = 0; j < top->nodes[i].num_links; j++) 496 /* node id in sysfs starts from 1 rather than 0 so +1 here */ 497 size += sysfs_emit_at(buf, size, "%02x:%02x -> %02x:%02x\n", current_node + 1, 498 top->nodes[i].port_num[j].src_xgmi_port_num, i + 1, 499 top->nodes[i].port_num[j].dst_xgmi_port_num); 500 } 501 502 return size; 503 } 504 505 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 506 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 507 struct device_attribute *attr, 508 char *buf) 509 { 510 struct drm_device *ddev = dev_get_drvdata(dev); 511 struct amdgpu_device *adev = drm_to_adev(ddev); 512 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 513 uint64_t fica_out; 514 unsigned int error_count = 0; 515 516 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 517 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 518 519 if ((!adev->df.funcs) || 520 (!adev->df.funcs->get_fica) || 521 (!adev->df.funcs->set_fica)) 522 return -EINVAL; 523 524 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 525 if (fica_out != 0x1f) 526 pr_err("xGMI error counters not enabled!\n"); 527 528 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 529 530 if ((fica_out & 0xffff) == 2) 531 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 532 533 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 534 535 return sysfs_emit(buf, "%u\n", error_count); 536 } 537 538 539 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 540 static DEVICE_ATTR(xgmi_physical_id, 0444, amdgpu_xgmi_show_physical_id, NULL); 541 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 542 static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL); 543 static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL); 544 static DEVICE_ATTR(xgmi_port_num, S_IRUGO, amdgpu_xgmi_show_connected_port_num, NULL); 545 546 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 547 struct amdgpu_hive_info *hive) 548 { 549 int ret = 0; 550 char node[10] = { 0 }; 551 552 /* Create xgmi device id file */ 553 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 554 if (ret) { 555 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 556 return ret; 557 } 558 559 ret = device_create_file(adev->dev, &dev_attr_xgmi_physical_id); 560 if (ret) { 561 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_physical_id\n"); 562 return ret; 563 } 564 565 /* Create xgmi error file */ 566 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 567 if (ret) 568 pr_err("failed to create xgmi_error\n"); 569 570 /* Create xgmi num hops file */ 571 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops); 572 if (ret) 573 pr_err("failed to create xgmi_num_hops\n"); 574 575 /* Create xgmi num links file */ 576 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links); 577 if (ret) 578 pr_err("failed to create xgmi_num_links\n"); 579 580 /* Create xgmi port num file if supported */ 581 if (adev->psp.xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG) { 582 ret = device_create_file(adev->dev, &dev_attr_xgmi_port_num); 583 if (ret) 584 dev_err(adev->dev, "failed to create xgmi_port_num\n"); 585 } 586 587 /* Create sysfs link to hive info folder on the first device */ 588 if (hive->kobj.parent != (&adev->dev->kobj)) { 589 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 590 "xgmi_hive_info"); 591 if (ret) { 592 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 593 goto remove_file; 594 } 595 } 596 597 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 598 /* Create sysfs link form the hive folder to yourself */ 599 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 600 if (ret) { 601 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 602 goto remove_link; 603 } 604 605 goto success; 606 607 608 remove_link: 609 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 610 611 remove_file: 612 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 613 device_remove_file(adev->dev, &dev_attr_xgmi_physical_id); 614 device_remove_file(adev->dev, &dev_attr_xgmi_error); 615 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 616 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 617 if (adev->psp.xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG) 618 device_remove_file(adev->dev, &dev_attr_xgmi_port_num); 619 620 success: 621 return ret; 622 } 623 624 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 625 struct amdgpu_hive_info *hive) 626 { 627 char node[10]; 628 memset(node, 0, sizeof(node)); 629 630 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 631 device_remove_file(adev->dev, &dev_attr_xgmi_physical_id); 632 device_remove_file(adev->dev, &dev_attr_xgmi_error); 633 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 634 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 635 if (adev->psp.xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG) 636 device_remove_file(adev->dev, &dev_attr_xgmi_port_num); 637 638 if (hive->kobj.parent != (&adev->dev->kobj)) 639 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 640 641 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 642 sysfs_remove_link(&hive->kobj, node); 643 644 } 645 646 647 648 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 649 { 650 struct amdgpu_hive_info *hive = NULL; 651 int ret; 652 653 if (!adev->gmc.xgmi.hive_id) 654 return NULL; 655 656 if (adev->hive) { 657 kobject_get(&adev->hive->kobj); 658 return adev->hive; 659 } 660 661 mutex_lock(&xgmi_mutex); 662 663 list_for_each_entry(hive, &xgmi_hive_list, node) { 664 if (hive->hive_id == adev->gmc.xgmi.hive_id) 665 goto pro_end; 666 } 667 668 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 669 if (!hive) { 670 dev_err(adev->dev, "XGMI: allocation failed\n"); 671 ret = -ENOMEM; 672 hive = NULL; 673 goto pro_end; 674 } 675 676 /* initialize new hive if not exist */ 677 ret = kobject_init_and_add(&hive->kobj, 678 &amdgpu_xgmi_hive_type, 679 &adev->dev->kobj, 680 "%s", "xgmi_hive_info"); 681 if (ret) { 682 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 683 kobject_put(&hive->kobj); 684 hive = NULL; 685 goto pro_end; 686 } 687 688 /** 689 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV, 690 * Host driver decide how to reset the GPU either through FLR or chain reset. 691 * Guest side will get individual notifications from the host for the FLR 692 * if necessary. 693 */ 694 if (!amdgpu_sriov_vf(adev)) { 695 /** 696 * Avoid recreating reset domain when hive is reconstructed for the case 697 * of reset the devices in the XGMI hive during probe for passthrough GPU 698 * See https://www.spinics.net/lists/amd-gfx/msg58836.html 699 */ 700 if (adev->reset_domain->type != XGMI_HIVE) { 701 hive->reset_domain = 702 amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); 703 if (!hive->reset_domain) { 704 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n"); 705 ret = -ENOMEM; 706 kobject_put(&hive->kobj); 707 hive = NULL; 708 goto pro_end; 709 } 710 } else { 711 amdgpu_reset_get_reset_domain(adev->reset_domain); 712 hive->reset_domain = adev->reset_domain; 713 } 714 } 715 716 hive->hive_id = adev->gmc.xgmi.hive_id; 717 INIT_LIST_HEAD(&hive->device_list); 718 INIT_LIST_HEAD(&hive->node); 719 mutex_init(&hive->hive_lock); 720 atomic_set(&hive->number_devices, 0); 721 task_barrier_init(&hive->tb); 722 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 723 hive->hi_req_gpu = NULL; 724 atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE); 725 726 /* 727 * hive pstate on boot is high in vega20 so we have to go to low 728 * pstate on after boot. 729 */ 730 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 731 list_add_tail(&hive->node, &xgmi_hive_list); 732 733 pro_end: 734 if (hive) 735 kobject_get(&hive->kobj); 736 mutex_unlock(&xgmi_mutex); 737 return hive; 738 } 739 740 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 741 { 742 if (hive) 743 kobject_put(&hive->kobj); 744 } 745 746 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 747 { 748 int ret = 0; 749 struct amdgpu_hive_info *hive; 750 struct amdgpu_device *request_adev; 751 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 752 bool init_low; 753 754 hive = amdgpu_get_xgmi_hive(adev); 755 if (!hive) 756 return 0; 757 758 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 759 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 760 amdgpu_put_xgmi_hive(hive); 761 /* fw bug so temporarily disable pstate switching */ 762 return 0; 763 764 if (!hive || adev->asic_type != CHIP_VEGA20) 765 return 0; 766 767 mutex_lock(&hive->hive_lock); 768 769 if (is_hi_req) 770 hive->hi_req_count++; 771 else 772 hive->hi_req_count--; 773 774 /* 775 * Vega20 only needs single peer to request pstate high for the hive to 776 * go high but all peers must request pstate low for the hive to go low 777 */ 778 if (hive->pstate == pstate || 779 (!is_hi_req && hive->hi_req_count && !init_low)) 780 goto out; 781 782 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 783 784 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 785 if (ret) { 786 dev_err(request_adev->dev, 787 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 788 request_adev->gmc.xgmi.node_id, 789 request_adev->gmc.xgmi.hive_id, ret); 790 goto out; 791 } 792 793 if (init_low) 794 hive->pstate = hive->hi_req_count ? 795 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 796 else { 797 hive->pstate = pstate; 798 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 799 adev : NULL; 800 } 801 out: 802 mutex_unlock(&hive->hive_lock); 803 return ret; 804 } 805 806 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 807 { 808 int ret; 809 810 if (amdgpu_sriov_vf(adev)) 811 return 0; 812 813 /* Each psp need to set the latest topology */ 814 ret = psp_xgmi_set_topology_info(&adev->psp, 815 atomic_read(&hive->number_devices), 816 &adev->psp.xgmi_context.top_info); 817 if (ret) 818 dev_err(adev->dev, 819 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 820 adev->gmc.xgmi.node_id, 821 adev->gmc.xgmi.hive_id, ret); 822 823 return ret; 824 } 825 826 827 /* 828 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 829 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 830 * num_hops[5:3] = reserved 831 * num_hops[2:0] = number of hops 832 */ 833 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 834 struct amdgpu_device *peer_adev) 835 { 836 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 837 uint8_t num_hops_mask = 0x7; 838 int i; 839 840 if (!adev->gmc.xgmi.supported) 841 return 0; 842 843 for (i = 0 ; i < top->num_nodes; ++i) 844 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 845 return top->nodes[i].num_hops & num_hops_mask; 846 847 dev_err(adev->dev, "Failed to get xgmi hops count for peer %d.\n", 848 peer_adev->gmc.xgmi.physical_node_id); 849 850 return 0; 851 } 852 853 int amdgpu_xgmi_get_bandwidth(struct amdgpu_device *adev, struct amdgpu_device *peer_adev, 854 enum amdgpu_xgmi_bw_mode bw_mode, enum amdgpu_xgmi_bw_unit bw_unit, 855 uint32_t *min_bw, uint32_t *max_bw) 856 { 857 bool peer_mode = bw_mode == AMDGPU_XGMI_BW_MODE_PER_PEER; 858 int unit_scale = bw_unit == AMDGPU_XGMI_BW_UNIT_MBYTES ? 1000 : 1; 859 int num_lanes = adev->gmc.xgmi.max_width; 860 int speed = adev->gmc.xgmi.max_speed; 861 int num_links = !peer_mode ? 1 : -1; 862 863 if (!(min_bw && max_bw)) 864 return -EINVAL; 865 866 *min_bw = 0; 867 *max_bw = 0; 868 869 if (!adev->gmc.xgmi.supported) 870 return -ENODATA; 871 872 if (peer_mode && !peer_adev) 873 return -EINVAL; 874 875 if (peer_mode) { 876 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 877 int i; 878 879 for (i = 0 ; i < top->num_nodes; ++i) { 880 if (top->nodes[i].node_id != peer_adev->gmc.xgmi.node_id) 881 continue; 882 883 num_links = top->nodes[i].num_links; 884 break; 885 } 886 } 887 888 if (num_links == -1) { 889 dev_err(adev->dev, "Failed to get number of xgmi links for peer %d.\n", 890 peer_adev->gmc.xgmi.physical_node_id); 891 } else if (num_links) { 892 int per_link_bw = (speed * num_lanes * unit_scale)/BITS_PER_BYTE; 893 894 *min_bw = per_link_bw; 895 *max_bw = num_links * per_link_bw; 896 } 897 898 return 0; 899 } 900 901 bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev, 902 struct amdgpu_device *peer_adev) 903 { 904 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 905 int i; 906 907 /* Sharing should always be enabled for non-SRIOV. */ 908 if (!amdgpu_sriov_vf(adev)) 909 return true; 910 911 for (i = 0 ; i < top->num_nodes; ++i) 912 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 913 return !!top->nodes[i].is_sharing_enabled; 914 915 return false; 916 } 917 918 /* 919 * Devices that support extended data require the entire hive to initialize with 920 * the shared memory buffer flag set. 921 * 922 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 923 */ 924 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 925 bool set_extended_data) 926 { 927 struct amdgpu_device *tmp_adev; 928 int ret; 929 930 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 931 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 932 if (ret) { 933 dev_err(tmp_adev->dev, 934 "XGMI: Failed to initialize xgmi session for data partition %i\n", 935 set_extended_data); 936 return ret; 937 } 938 939 } 940 941 return 0; 942 } 943 944 static void amdgpu_xgmi_fill_topology_info(struct amdgpu_device *adev, 945 struct amdgpu_device *peer_adev) 946 { 947 struct psp_xgmi_topology_info *top_info = &adev->psp.xgmi_context.top_info; 948 struct psp_xgmi_topology_info *peer_info = &peer_adev->psp.xgmi_context.top_info; 949 950 for (int i = 0; i < peer_info->num_nodes; i++) { 951 if (peer_info->nodes[i].node_id == adev->gmc.xgmi.node_id) { 952 for (int j = 0; j < top_info->num_nodes; j++) { 953 if (top_info->nodes[j].node_id == peer_adev->gmc.xgmi.node_id) { 954 peer_info->nodes[i].num_hops = top_info->nodes[j].num_hops; 955 peer_info->nodes[i].is_sharing_enabled = 956 top_info->nodes[j].is_sharing_enabled; 957 peer_info->nodes[i].num_links = 958 top_info->nodes[j].num_links; 959 return; 960 } 961 } 962 } 963 } 964 } 965 966 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 967 { 968 struct psp_xgmi_topology_info *top_info; 969 struct amdgpu_hive_info *hive; 970 struct amdgpu_xgmi *entry; 971 struct amdgpu_device *tmp_adev = NULL; 972 973 int count = 0, ret = 0; 974 975 if (!adev->gmc.xgmi.supported) 976 return 0; 977 978 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 979 ret = psp_xgmi_initialize(&adev->psp, false, true); 980 if (ret) { 981 dev_err(adev->dev, 982 "XGMI: Failed to initialize xgmi session\n"); 983 return ret; 984 } 985 986 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 987 if (ret) { 988 dev_err(adev->dev, 989 "XGMI: Failed to get hive id\n"); 990 return ret; 991 } 992 993 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 994 if (ret) { 995 dev_err(adev->dev, 996 "XGMI: Failed to get node id\n"); 997 return ret; 998 } 999 } else { 1000 adev->gmc.xgmi.hive_id = 16; 1001 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 1002 } 1003 1004 hive = amdgpu_get_xgmi_hive(adev); 1005 if (!hive) { 1006 ret = -EINVAL; 1007 dev_err(adev->dev, 1008 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 1009 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 1010 goto exit; 1011 } 1012 mutex_lock(&hive->hive_lock); 1013 1014 top_info = &adev->psp.xgmi_context.top_info; 1015 1016 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 1017 list_for_each_entry(entry, &hive->device_list, head) 1018 top_info->nodes[count++].node_id = entry->node_id; 1019 top_info->num_nodes = count; 1020 atomic_set(&hive->number_devices, count); 1021 1022 task_barrier_add_task(&hive->tb); 1023 1024 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 1025 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1026 /* update node list for other device in the hive */ 1027 if (tmp_adev != adev) { 1028 top_info = &tmp_adev->psp.xgmi_context.top_info; 1029 top_info->nodes[count - 1].node_id = 1030 adev->gmc.xgmi.node_id; 1031 top_info->num_nodes = count; 1032 } 1033 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 1034 if (ret) 1035 goto exit_unlock; 1036 } 1037 1038 if (amdgpu_sriov_vf(adev) && 1039 adev->psp.xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG) { 1040 /* only get topology for VF being init if it can support full duplex */ 1041 ret = psp_xgmi_get_topology_info(&adev->psp, count, 1042 &adev->psp.xgmi_context.top_info, false); 1043 if (ret) { 1044 dev_err(adev->dev, 1045 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 1046 adev->gmc.xgmi.node_id, 1047 adev->gmc.xgmi.hive_id, ret); 1048 /* To do: continue with some node failed or disable the whole hive*/ 1049 goto exit_unlock; 1050 } 1051 1052 /* fill the topology info for peers instead of getting from PSP */ 1053 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1054 amdgpu_xgmi_fill_topology_info(adev, tmp_adev); 1055 } 1056 } else { 1057 /* get latest topology info for each device from psp */ 1058 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1059 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 1060 &tmp_adev->psp.xgmi_context.top_info, false); 1061 if (ret) { 1062 dev_err(tmp_adev->dev, 1063 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 1064 tmp_adev->gmc.xgmi.node_id, 1065 tmp_adev->gmc.xgmi.hive_id, ret); 1066 /* To do : continue with some node failed or disable the whole hive */ 1067 goto exit_unlock; 1068 } 1069 } 1070 } 1071 1072 /* get topology again for hives that support extended data */ 1073 if (adev->psp.xgmi_context.supports_extended_data) { 1074 1075 /* initialize the hive to get extended data. */ 1076 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 1077 if (ret) 1078 goto exit_unlock; 1079 1080 /* get the extended data. */ 1081 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1082 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 1083 &tmp_adev->psp.xgmi_context.top_info, true); 1084 if (ret) { 1085 dev_err(tmp_adev->dev, 1086 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 1087 tmp_adev->gmc.xgmi.node_id, 1088 tmp_adev->gmc.xgmi.hive_id, ret); 1089 goto exit_unlock; 1090 } 1091 } 1092 1093 /* initialize the hive to get non-extended data for the next round. */ 1094 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 1095 if (ret) 1096 goto exit_unlock; 1097 1098 } 1099 } 1100 1101 if (!ret) 1102 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 1103 1104 exit_unlock: 1105 mutex_unlock(&hive->hive_lock); 1106 exit: 1107 if (!ret) { 1108 adev->hive = hive; 1109 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 1110 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 1111 } else { 1112 amdgpu_put_xgmi_hive(hive); 1113 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 1114 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 1115 ret); 1116 } 1117 1118 return ret; 1119 } 1120 1121 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 1122 { 1123 struct amdgpu_hive_info *hive = adev->hive; 1124 1125 if (!adev->gmc.xgmi.supported) 1126 return -EINVAL; 1127 1128 if (!hive) 1129 return -EINVAL; 1130 1131 mutex_lock(&hive->hive_lock); 1132 task_barrier_rem_task(&hive->tb); 1133 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 1134 if (hive->hi_req_gpu == adev) 1135 hive->hi_req_gpu = NULL; 1136 list_del(&adev->gmc.xgmi.head); 1137 mutex_unlock(&hive->hive_lock); 1138 1139 amdgpu_put_xgmi_hive(hive); 1140 adev->hive = NULL; 1141 1142 if (atomic_dec_return(&hive->number_devices) == 0) { 1143 /* Remove the hive from global hive list */ 1144 mutex_lock(&xgmi_mutex); 1145 list_del(&hive->node); 1146 mutex_unlock(&xgmi_mutex); 1147 1148 amdgpu_put_xgmi_hive(hive); 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1155 enum aca_smu_type type, void *data) 1156 { 1157 struct amdgpu_device *adev = handle->adev; 1158 struct aca_bank_info info; 1159 const char *error_str; 1160 u64 status, count; 1161 int ret, ext_error_code; 1162 1163 ret = aca_bank_info_decode(bank, &info); 1164 if (ret) 1165 return ret; 1166 1167 status = bank->regs[ACA_REG_IDX_STATUS]; 1168 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 1169 1170 error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? 1171 xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; 1172 if (error_str) 1173 dev_info(adev->dev, "%s detected\n", error_str); 1174 1175 count = ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]); 1176 1177 switch (type) { 1178 case ACA_SMU_TYPE_UE: 1179 if (ext_error_code != 0 && ext_error_code != 9) 1180 count = 0ULL; 1181 1182 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1183 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, count); 1184 break; 1185 case ACA_SMU_TYPE_CE: 1186 count = ext_error_code == 6 ? count : 0ULL; 1187 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1188 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, count); 1189 break; 1190 default: 1191 return -EINVAL; 1192 } 1193 1194 return ret; 1195 } 1196 1197 static const struct aca_bank_ops xgmi_v6_4_0_aca_bank_ops = { 1198 .aca_bank_parser = xgmi_v6_4_0_aca_bank_parser, 1199 }; 1200 1201 static const struct aca_info xgmi_v6_4_0_aca_info = { 1202 .hwip = ACA_HWIP_TYPE_PCS_XGMI, 1203 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 1204 .bank_ops = &xgmi_v6_4_0_aca_bank_ops, 1205 }; 1206 1207 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1208 { 1209 int r; 1210 1211 if (!adev->gmc.xgmi.supported || 1212 adev->gmc.xgmi.num_physical_nodes == 0) 1213 return 0; 1214 1215 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL); 1216 1217 r = amdgpu_ras_block_late_init(adev, ras_block); 1218 if (r) 1219 return r; 1220 1221 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1222 case IP_VERSION(6, 4, 0): 1223 case IP_VERSION(6, 4, 1): 1224 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL, 1225 &xgmi_v6_4_0_aca_info, NULL); 1226 if (r) 1227 goto late_fini; 1228 break; 1229 default: 1230 break; 1231 } 1232 1233 return 0; 1234 1235 late_fini: 1236 amdgpu_ras_block_late_fini(adev, ras_block); 1237 1238 return r; 1239 } 1240 1241 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 1242 uint64_t addr) 1243 { 1244 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 1245 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 1246 } 1247 1248 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 1249 { 1250 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 1251 WREG32_PCIE(pcs_status_reg, 0); 1252 } 1253 1254 static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) 1255 { 1256 uint32_t i; 1257 1258 switch (adev->asic_type) { 1259 case CHIP_ARCTURUS: 1260 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 1261 pcs_clear_status(adev, 1262 xgmi_pcs_err_status_reg_arct[i]); 1263 break; 1264 case CHIP_VEGA20: 1265 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 1266 pcs_clear_status(adev, 1267 xgmi_pcs_err_status_reg_vg20[i]); 1268 break; 1269 case CHIP_ALDEBARAN: 1270 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 1271 pcs_clear_status(adev, 1272 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 1273 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 1274 pcs_clear_status(adev, 1275 walf_pcs_err_status_reg_aldebaran[i]); 1276 break; 1277 default: 1278 break; 1279 } 1280 1281 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1282 case IP_VERSION(6, 4, 0): 1283 case IP_VERSION(6, 4, 1): 1284 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) 1285 pcs_clear_status(adev, 1286 xgmi3x16_pcs_err_status_reg_v6_4[i]); 1287 break; 1288 default: 1289 break; 1290 } 1291 } 1292 1293 static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) 1294 { 1295 WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); 1296 } 1297 1298 static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) 1299 { 1300 int i; 1301 1302 for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++) 1303 __xgmi_v6_4_0_reset_error_count(adev, xgmi_inst, xgmi_v6_4_0_mca_base_array[i]); 1304 } 1305 1306 static void xgmi_v6_4_0_reset_ras_error_count(struct amdgpu_device *adev) 1307 { 1308 int i; 1309 1310 for_each_inst(i, adev->aid_mask) 1311 xgmi_v6_4_0_reset_error_count(adev, i); 1312 } 1313 1314 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 1315 { 1316 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1317 case IP_VERSION(6, 4, 0): 1318 case IP_VERSION(6, 4, 1): 1319 xgmi_v6_4_0_reset_ras_error_count(adev); 1320 break; 1321 default: 1322 amdgpu_xgmi_legacy_reset_ras_error_count(adev); 1323 break; 1324 } 1325 } 1326 1327 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 1328 uint32_t value, 1329 uint32_t mask_value, 1330 uint32_t *ue_count, 1331 uint32_t *ce_count, 1332 bool is_xgmi_pcs, 1333 bool check_mask) 1334 { 1335 int i; 1336 int ue_cnt = 0; 1337 const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL; 1338 uint32_t field_array_size = 0; 1339 1340 if (is_xgmi_pcs) { 1341 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == 1342 IP_VERSION(6, 1, 0) || 1343 amdgpu_ip_version(adev, XGMI_HWIP, 0) == 1344 IP_VERSION(6, 4, 0) || 1345 amdgpu_ip_version(adev, XGMI_HWIP, 0) == 1346 IP_VERSION(6, 4, 1)) { 1347 pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0]; 1348 field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields); 1349 } else { 1350 pcs_ras_fields = &xgmi_pcs_ras_fields[0]; 1351 field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields); 1352 } 1353 } else { 1354 pcs_ras_fields = &wafl_pcs_ras_fields[0]; 1355 field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields); 1356 } 1357 1358 if (check_mask) 1359 value = value & ~mask_value; 1360 1361 /* query xgmi/walf pcs error status, 1362 * only ue is supported */ 1363 for (i = 0; value && i < field_array_size; i++) { 1364 ue_cnt = (value & 1365 pcs_ras_fields[i].pcs_err_mask) >> 1366 pcs_ras_fields[i].pcs_err_shift; 1367 if (ue_cnt) { 1368 dev_info(adev->dev, "%s detected\n", 1369 pcs_ras_fields[i].err_name); 1370 *ue_count += ue_cnt; 1371 } 1372 1373 /* reset bit value if the bit is checked */ 1374 value &= ~(pcs_ras_fields[i].pcs_err_mask); 1375 } 1376 1377 return 0; 1378 } 1379 1380 static void amdgpu_xgmi_legacy_query_ras_error_count(struct amdgpu_device *adev, 1381 void *ras_error_status) 1382 { 1383 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1384 int i, supported = 1; 1385 uint32_t data, mask_data = 0; 1386 uint32_t ue_cnt = 0, ce_cnt = 0; 1387 1388 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 1389 return ; 1390 1391 err_data->ue_count = 0; 1392 err_data->ce_count = 0; 1393 1394 switch (adev->asic_type) { 1395 case CHIP_ARCTURUS: 1396 /* check xgmi pcs error */ 1397 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 1398 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 1399 if (data) 1400 amdgpu_xgmi_query_pcs_error_status(adev, data, 1401 mask_data, &ue_cnt, &ce_cnt, true, false); 1402 } 1403 /* check wafl pcs error */ 1404 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 1405 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 1406 if (data) 1407 amdgpu_xgmi_query_pcs_error_status(adev, data, 1408 mask_data, &ue_cnt, &ce_cnt, false, false); 1409 } 1410 break; 1411 case CHIP_VEGA20: 1412 /* check xgmi pcs error */ 1413 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 1414 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 1415 if (data) 1416 amdgpu_xgmi_query_pcs_error_status(adev, data, 1417 mask_data, &ue_cnt, &ce_cnt, true, false); 1418 } 1419 /* check wafl pcs error */ 1420 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 1421 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 1422 if (data) 1423 amdgpu_xgmi_query_pcs_error_status(adev, data, 1424 mask_data, &ue_cnt, &ce_cnt, false, false); 1425 } 1426 break; 1427 case CHIP_ALDEBARAN: 1428 /* check xgmi3x16 pcs error */ 1429 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 1430 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 1431 mask_data = 1432 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1433 if (data) 1434 amdgpu_xgmi_query_pcs_error_status(adev, data, 1435 mask_data, &ue_cnt, &ce_cnt, true, true); 1436 } 1437 /* check wafl pcs error */ 1438 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 1439 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 1440 mask_data = 1441 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1442 if (data) 1443 amdgpu_xgmi_query_pcs_error_status(adev, data, 1444 mask_data, &ue_cnt, &ce_cnt, false, true); 1445 } 1446 break; 1447 default: 1448 supported = 0; 1449 break; 1450 } 1451 1452 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1453 case IP_VERSION(6, 4, 0): 1454 case IP_VERSION(6, 4, 1): 1455 /* check xgmi3x16 pcs error */ 1456 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) { 1457 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]); 1458 mask_data = 1459 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[i]); 1460 if (data) 1461 amdgpu_xgmi_query_pcs_error_status(adev, data, 1462 mask_data, &ue_cnt, &ce_cnt, true, true); 1463 } 1464 break; 1465 default: 1466 if (!supported) 1467 dev_warn(adev->dev, "XGMI RAS error query not supported"); 1468 break; 1469 } 1470 1471 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL); 1472 1473 err_data->ue_count += ue_cnt; 1474 err_data->ce_count += ce_cnt; 1475 } 1476 1477 static enum aca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status) 1478 { 1479 const char *error_str; 1480 int ext_error_code; 1481 1482 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 1483 1484 error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? 1485 xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; 1486 if (error_str) 1487 dev_info(adev->dev, "%s detected\n", error_str); 1488 1489 switch (ext_error_code) { 1490 case 0: 1491 return ACA_ERROR_TYPE_UE; 1492 case 6: 1493 return ACA_ERROR_TYPE_CE; 1494 default: 1495 return -EINVAL; 1496 } 1497 1498 return -EINVAL; 1499 } 1500 1501 static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct amdgpu_smuio_mcm_config_info *mcm_info, 1502 u64 mca_base, struct ras_err_data *err_data) 1503 { 1504 int xgmi_inst = mcm_info->die_id; 1505 u64 status = 0; 1506 1507 status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS); 1508 if (!ACA_REG__STATUS__VAL(status)) 1509 return; 1510 1511 switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) { 1512 case ACA_ERROR_TYPE_UE: 1513 amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, 1ULL); 1514 break; 1515 case ACA_ERROR_TYPE_CE: 1516 amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, 1ULL); 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); 1523 } 1524 1525 static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) 1526 { 1527 struct amdgpu_smuio_mcm_config_info mcm_info = { 1528 .socket_id = adev->smuio.funcs->get_socket_id(adev), 1529 .die_id = xgmi_inst, 1530 }; 1531 int i; 1532 1533 for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++) 1534 __xgmi_v6_4_0_query_error_count(adev, &mcm_info, xgmi_v6_4_0_mca_base_array[i], err_data); 1535 } 1536 1537 static void xgmi_v6_4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 1538 { 1539 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1540 int i; 1541 1542 for_each_inst(i, adev->aid_mask) 1543 xgmi_v6_4_0_query_error_count(adev, i, err_data); 1544 } 1545 1546 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 1547 void *ras_error_status) 1548 { 1549 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1550 case IP_VERSION(6, 4, 0): 1551 case IP_VERSION(6, 4, 1): 1552 xgmi_v6_4_0_query_ras_error_count(adev, ras_error_status); 1553 break; 1554 default: 1555 amdgpu_xgmi_legacy_query_ras_error_count(adev, ras_error_status); 1556 break; 1557 } 1558 } 1559 1560 /* Trigger XGMI/WAFL error */ 1561 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, 1562 void *inject_if, uint32_t instance_mask) 1563 { 1564 int ret1, ret2; 1565 struct ta_ras_trigger_error_input *block_info = 1566 (struct ta_ras_trigger_error_input *)inject_if; 1567 1568 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) 1569 dev_warn(adev->dev, "Failed to disallow df cstate"); 1570 1571 ret1 = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DISALLOW); 1572 if (ret1 && ret1 != -EOPNOTSUPP) 1573 dev_warn(adev->dev, "Failed to disallow XGMI power down"); 1574 1575 ret2 = psp_ras_trigger_error(&adev->psp, block_info, instance_mask); 1576 1577 if (amdgpu_ras_intr_triggered()) 1578 return ret2; 1579 1580 ret1 = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DEFAULT); 1581 if (ret1 && ret1 != -EOPNOTSUPP) 1582 dev_warn(adev->dev, "Failed to allow XGMI power down"); 1583 1584 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) 1585 dev_warn(adev->dev, "Failed to allow df cstate"); 1586 1587 return ret2; 1588 } 1589 1590 struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = { 1591 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 1592 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 1593 .ras_error_inject = amdgpu_ras_error_inject_xgmi, 1594 }; 1595 1596 struct amdgpu_xgmi_ras xgmi_ras = { 1597 .ras_block = { 1598 .hw_ops = &xgmi_ras_hw_ops, 1599 .ras_late_init = amdgpu_xgmi_ras_late_init, 1600 }, 1601 }; 1602 1603 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev) 1604 { 1605 int err; 1606 struct amdgpu_xgmi_ras *ras; 1607 1608 if (!adev->gmc.xgmi.ras) 1609 return 0; 1610 1611 ras = adev->gmc.xgmi.ras; 1612 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1613 if (err) { 1614 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); 1615 return err; 1616 } 1617 1618 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); 1619 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 1620 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1621 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; 1622 1623 return 0; 1624 } 1625 1626 static void amdgpu_xgmi_reset_on_init_work(struct work_struct *work) 1627 { 1628 struct amdgpu_hive_info *hive = 1629 container_of(work, struct amdgpu_hive_info, reset_on_init_work); 1630 struct amdgpu_reset_context reset_context; 1631 struct amdgpu_device *tmp_adev; 1632 struct list_head device_list; 1633 int r; 1634 1635 mutex_lock(&hive->hive_lock); 1636 1637 INIT_LIST_HEAD(&device_list); 1638 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) 1639 list_add_tail(&tmp_adev->reset_list, &device_list); 1640 1641 tmp_adev = list_first_entry(&device_list, struct amdgpu_device, 1642 reset_list); 1643 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain); 1644 1645 reset_context.method = AMD_RESET_METHOD_ON_INIT; 1646 reset_context.reset_req_dev = tmp_adev; 1647 reset_context.hive = hive; 1648 reset_context.reset_device_list = &device_list; 1649 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1650 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 1651 1652 amdgpu_reset_do_xgmi_reset_on_init(&reset_context); 1653 mutex_unlock(&hive->hive_lock); 1654 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); 1655 1656 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1657 r = amdgpu_ras_init_badpage_info(tmp_adev); 1658 if (r && r != -EHWPOISON) 1659 dev_err(tmp_adev->dev, 1660 "error during bad page data initialization"); 1661 } 1662 } 1663 1664 static void amdgpu_xgmi_schedule_reset_on_init(struct amdgpu_hive_info *hive) 1665 { 1666 INIT_WORK(&hive->reset_on_init_work, amdgpu_xgmi_reset_on_init_work); 1667 amdgpu_reset_domain_schedule(hive->reset_domain, 1668 &hive->reset_on_init_work); 1669 } 1670 1671 int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev) 1672 { 1673 struct amdgpu_hive_info *hive; 1674 bool reset_scheduled; 1675 int num_devs; 1676 1677 hive = amdgpu_get_xgmi_hive(adev); 1678 if (!hive) 1679 return -EINVAL; 1680 1681 mutex_lock(&hive->hive_lock); 1682 num_devs = atomic_read(&hive->number_devices); 1683 reset_scheduled = false; 1684 if (num_devs == adev->gmc.xgmi.num_physical_nodes) { 1685 amdgpu_xgmi_schedule_reset_on_init(hive); 1686 reset_scheduled = true; 1687 } 1688 1689 mutex_unlock(&hive->hive_lock); 1690 amdgpu_put_xgmi_hive(hive); 1691 1692 if (reset_scheduled) 1693 flush_work(&hive->reset_on_init_work); 1694 1695 return 0; 1696 } 1697 1698 int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev, 1699 struct amdgpu_hive_info *hive, 1700 int req_nps_mode) 1701 { 1702 struct amdgpu_device *tmp_adev; 1703 int cur_nps_mode, r; 1704 1705 /* This is expected to be called only during unload of driver. The 1706 * request needs to be placed only once for all devices in the hive. If 1707 * one of them fail, revert the request for previous successful devices. 1708 * After placing the request, make hive mode as UNKNOWN so that other 1709 * devices don't request anymore. 1710 */ 1711 mutex_lock(&hive->hive_lock); 1712 if (atomic_read(&hive->requested_nps_mode) == 1713 UNKNOWN_MEMORY_PARTITION_MODE) { 1714 dev_dbg(adev->dev, "Unexpected entry for hive NPS change"); 1715 mutex_unlock(&hive->hive_lock); 1716 return 0; 1717 } 1718 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 1719 r = adev->gmc.gmc_funcs->request_mem_partition_mode( 1720 tmp_adev, req_nps_mode); 1721 if (r) 1722 break; 1723 } 1724 if (r) { 1725 /* Request back current mode if one of the requests failed */ 1726 cur_nps_mode = 1727 adev->gmc.gmc_funcs->query_mem_partition_mode(tmp_adev); 1728 list_for_each_entry_continue_reverse( 1729 tmp_adev, &hive->device_list, gmc.xgmi.head) 1730 adev->gmc.gmc_funcs->request_mem_partition_mode( 1731 tmp_adev, cur_nps_mode); 1732 } 1733 /* Set to UNKNOWN so that other devices don't request anymore */ 1734 atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE); 1735 mutex_unlock(&hive->hive_lock); 1736 1737 return r; 1738 } 1739 1740 bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, 1741 struct amdgpu_device *bo_adev) 1742 { 1743 return (amdgpu_use_xgmi_p2p && adev != bo_adev && 1744 adev->gmc.xgmi.hive_id && 1745 adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id); 1746 } 1747 1748 void amdgpu_xgmi_early_init(struct amdgpu_device *adev) 1749 { 1750 if (!adev->gmc.xgmi.supported) 1751 return; 1752 1753 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1754 case IP_VERSION(9, 4, 0): 1755 case IP_VERSION(9, 4, 1): 1756 case IP_VERSION(9, 4, 2): 1757 adev->gmc.xgmi.max_speed = XGMI_SPEED_25GT; 1758 adev->gmc.xgmi.max_width = 16; 1759 break; 1760 case IP_VERSION(9, 4, 3): 1761 case IP_VERSION(9, 4, 4): 1762 case IP_VERSION(9, 5, 0): 1763 adev->gmc.xgmi.max_speed = XGMI_SPEED_32GT; 1764 adev->gmc.xgmi.max_width = 16; 1765 break; 1766 default: 1767 break; 1768 } 1769 } 1770