1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef AMDGPU_XCP_H 25 #define AMDGPU_XCP_H 26 27 #include <linux/pci.h> 28 #include <linux/xarray.h> 29 30 #include "amdgpu_ctx.h" 31 32 #define MAX_XCP 8 33 34 #define AMDGPU_XCP_MODE_NONE -1 35 #define AMDGPU_XCP_MODE_TRANS -2 36 37 #define AMDGPU_XCP_FL_NONE 0 38 #define AMDGPU_XCP_FL_LOCKED (1 << 0) 39 40 #define AMDGPU_XCP_NO_PARTITION (~0) 41 42 struct amdgpu_fpriv; 43 44 enum AMDGPU_XCP_IP_BLOCK { 45 AMDGPU_XCP_GFXHUB, 46 AMDGPU_XCP_GFX, 47 AMDGPU_XCP_SDMA, 48 AMDGPU_XCP_VCN, 49 AMDGPU_XCP_MAX_BLOCKS 50 }; 51 52 enum AMDGPU_XCP_STATE { 53 AMDGPU_XCP_PREPARE_SUSPEND, 54 AMDGPU_XCP_SUSPEND, 55 AMDGPU_XCP_PREPARE_RESUME, 56 AMDGPU_XCP_RESUME, 57 }; 58 59 enum amdgpu_xcp_res_id { 60 AMDGPU_XCP_RES_XCC, 61 AMDGPU_XCP_RES_DMA, 62 AMDGPU_XCP_RES_DEC, 63 AMDGPU_XCP_RES_JPEG, 64 AMDGPU_XCP_RES_MAX, 65 }; 66 67 struct amdgpu_xcp_res_details { 68 enum amdgpu_xcp_res_id id; 69 u8 num_inst; 70 u8 num_shared; 71 struct kobject kobj; 72 }; 73 74 struct amdgpu_xcp_cfg { 75 u8 mode; 76 struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX]; 77 u8 num_res; 78 struct amdgpu_xcp_mgr *xcp_mgr; 79 struct kobject kobj; 80 u16 compatible_nps_modes; 81 }; 82 83 struct amdgpu_xcp_ip_funcs { 84 int (*prepare_suspend)(void *handle, uint32_t inst_mask); 85 int (*suspend)(void *handle, uint32_t inst_mask); 86 int (*prepare_resume)(void *handle, uint32_t inst_mask); 87 int (*resume)(void *handle, uint32_t inst_mask); 88 }; 89 90 struct amdgpu_xcp_ip { 91 struct amdgpu_xcp_ip_funcs *ip_funcs; 92 uint32_t inst_mask; 93 94 enum AMDGPU_XCP_IP_BLOCK ip_id; 95 bool valid; 96 }; 97 98 struct amdgpu_xcp { 99 struct amdgpu_xcp_ip ip[AMDGPU_XCP_MAX_BLOCKS]; 100 101 uint8_t id; 102 uint8_t mem_id; 103 bool valid; 104 atomic_t ref_cnt; 105 struct drm_device *ddev; 106 struct drm_device *rdev; 107 struct drm_device *pdev; 108 struct drm_driver *driver; 109 struct drm_vma_offset_manager *vma_offset_manager; 110 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 111 }; 112 113 struct amdgpu_xcp_mgr { 114 struct amdgpu_device *adev; 115 struct mutex xcp_lock; 116 struct amdgpu_xcp_mgr_funcs *funcs; 117 118 struct amdgpu_xcp xcp[MAX_XCP]; 119 uint8_t num_xcps; 120 int8_t mode; 121 122 /* Used to determine KFD memory size limits per XCP */ 123 unsigned int num_xcp_per_mem_partition; 124 struct amdgpu_xcp_cfg *xcp_cfg; 125 uint32_t supp_xcp_modes; 126 uint32_t avail_xcp_modes; 127 }; 128 129 struct amdgpu_xcp_mgr_funcs { 130 int (*switch_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr, int mode, 131 int *num_xcps); 132 int (*query_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr); 133 int (*get_ip_details)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 134 enum AMDGPU_XCP_IP_BLOCK ip_id, 135 struct amdgpu_xcp_ip *ip); 136 int (*get_xcp_mem_id)(struct amdgpu_xcp_mgr *xcp_mgr, 137 struct amdgpu_xcp *xcp, uint8_t *mem_id); 138 int (*get_xcp_res_info)(struct amdgpu_xcp_mgr *xcp_mgr, 139 int mode, 140 struct amdgpu_xcp_cfg *xcp_cfg); 141 int (*prepare_suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 142 int (*suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 143 int (*prepare_resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 144 int (*resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 145 int (*select_scheds)(struct amdgpu_device *adev, 146 u32 hw_ip, u32 hw_prio, struct amdgpu_fpriv *fpriv, 147 unsigned int *num_scheds, struct drm_gpu_scheduler ***scheds); 148 int (*update_partition_sched_list)(struct amdgpu_device *adev); 149 }; 150 151 int amdgpu_xcp_prepare_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 152 int amdgpu_xcp_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 153 int amdgpu_xcp_prepare_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 154 int amdgpu_xcp_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 155 156 int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode, 157 int init_xcps, struct amdgpu_xcp_mgr_funcs *xcp_funcs); 158 int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode); 159 int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags); 160 int amdgpu_xcp_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, int mode); 161 int amdgpu_xcp_restore_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr); 162 int amdgpu_xcp_get_partition(struct amdgpu_xcp_mgr *xcp_mgr, 163 enum AMDGPU_XCP_IP_BLOCK ip, int instance); 164 165 int amdgpu_xcp_get_inst_details(struct amdgpu_xcp *xcp, 166 enum AMDGPU_XCP_IP_BLOCK ip, 167 uint32_t *inst_mask); 168 169 int amdgpu_xcp_dev_register(struct amdgpu_device *adev, 170 const struct pci_device_id *ent); 171 void amdgpu_xcp_dev_unplug(struct amdgpu_device *adev); 172 int amdgpu_xcp_open_device(struct amdgpu_device *adev, 173 struct amdgpu_fpriv *fpriv, 174 struct drm_file *file_priv); 175 void amdgpu_xcp_release_sched(struct amdgpu_device *adev, 176 struct amdgpu_ctx_entity *entity); 177 178 void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev); 179 void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev); 180 181 #define amdgpu_xcp_select_scheds(adev, e, c, d, x, y) \ 182 ((adev)->xcp_mgr && (adev)->xcp_mgr->funcs && \ 183 (adev)->xcp_mgr->funcs->select_scheds ? \ 184 (adev)->xcp_mgr->funcs->select_scheds((adev), (e), (c), (d), (x), (y)) : -ENOENT) 185 #define amdgpu_xcp_update_partition_sched_list(adev) \ 186 ((adev)->xcp_mgr && (adev)->xcp_mgr->funcs && \ 187 (adev)->xcp_mgr->funcs->update_partition_sched_list ? \ 188 (adev)->xcp_mgr->funcs->update_partition_sched_list(adev) : 0) 189 190 static inline int amdgpu_xcp_get_num_xcp(struct amdgpu_xcp_mgr *xcp_mgr) 191 { 192 if (!xcp_mgr) 193 return 1; 194 else 195 return xcp_mgr->num_xcps; 196 } 197 198 static inline struct amdgpu_xcp * 199 amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from) 200 { 201 if (!xcp_mgr) 202 return NULL; 203 204 while (*from < MAX_XCP) { 205 if (xcp_mgr->xcp[*from].valid) 206 return &xcp_mgr->xcp[*from]; 207 ++(*from); 208 } 209 210 return NULL; 211 } 212 213 #define for_each_xcp(xcp_mgr, xcp, i) \ 214 for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &i); xcp; \ 215 ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) 216 217 #endif 218