1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef AMDGPU_XCP_H 25 #define AMDGPU_XCP_H 26 27 #include <linux/pci.h> 28 #include <linux/xarray.h> 29 30 #include "amdgpu_ctx.h" 31 32 #define MAX_XCP 8 33 34 #define AMDGPU_XCP_MODE_NONE -1 35 #define AMDGPU_XCP_MODE_TRANS -2 36 37 #define AMDGPU_XCP_FL_NONE 0 38 #define AMDGPU_XCP_FL_LOCKED (1 << 0) 39 40 #define AMDGPU_XCP_NO_PARTITION (~0) 41 42 #define AMDGPU_XCP_OPS_KFD (1 << 0) 43 44 struct amdgpu_fpriv; 45 46 enum AMDGPU_XCP_IP_BLOCK { 47 AMDGPU_XCP_GFXHUB, 48 AMDGPU_XCP_GFX, 49 AMDGPU_XCP_SDMA, 50 AMDGPU_XCP_VCN, 51 AMDGPU_XCP_MAX_BLOCKS 52 }; 53 54 enum AMDGPU_XCP_STATE { 55 AMDGPU_XCP_PREPARE_SUSPEND, 56 AMDGPU_XCP_SUSPEND, 57 AMDGPU_XCP_PREPARE_RESUME, 58 AMDGPU_XCP_RESUME, 59 }; 60 61 enum amdgpu_xcp_res_id { 62 AMDGPU_XCP_RES_XCC, 63 AMDGPU_XCP_RES_DMA, 64 AMDGPU_XCP_RES_DEC, 65 AMDGPU_XCP_RES_JPEG, 66 AMDGPU_XCP_RES_MAX, 67 }; 68 69 struct amdgpu_xcp_res_details { 70 enum amdgpu_xcp_res_id id; 71 u8 num_inst; 72 u8 num_shared; 73 struct kobject kobj; 74 }; 75 76 struct amdgpu_xcp_cfg { 77 u8 mode; 78 struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX]; 79 u8 num_res; 80 struct amdgpu_xcp_mgr *xcp_mgr; 81 struct kobject kobj; 82 u16 compatible_nps_modes; 83 }; 84 85 struct amdgpu_xcp_ip_funcs { 86 int (*prepare_suspend)(void *handle, uint32_t inst_mask); 87 int (*suspend)(void *handle, uint32_t inst_mask); 88 int (*prepare_resume)(void *handle, uint32_t inst_mask); 89 int (*resume)(void *handle, uint32_t inst_mask); 90 }; 91 92 struct amdgpu_xcp_ip { 93 struct amdgpu_xcp_ip_funcs *ip_funcs; 94 uint32_t inst_mask; 95 96 enum AMDGPU_XCP_IP_BLOCK ip_id; 97 bool valid; 98 }; 99 100 struct amdgpu_xcp { 101 struct amdgpu_xcp_ip ip[AMDGPU_XCP_MAX_BLOCKS]; 102 103 uint8_t id; 104 uint8_t mem_id; 105 bool valid; 106 atomic_t ref_cnt; 107 struct drm_device *ddev; 108 struct drm_device *rdev; 109 struct drm_device *pdev; 110 struct drm_driver *driver; 111 struct drm_vma_offset_manager *vma_offset_manager; 112 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 113 struct amdgpu_xcp_mgr *xcp_mgr; 114 struct kobject kobj; 115 uint64_t unique_id; 116 }; 117 118 struct amdgpu_xcp_mgr { 119 struct amdgpu_device *adev; 120 struct mutex xcp_lock; 121 struct amdgpu_xcp_mgr_funcs *funcs; 122 123 struct amdgpu_xcp xcp[MAX_XCP]; 124 uint8_t num_xcps; 125 int8_t mode; 126 127 /* Used to determine KFD memory size limits per XCP */ 128 unsigned int num_xcp_per_mem_partition; 129 struct amdgpu_xcp_cfg *xcp_cfg; 130 uint32_t supp_xcp_modes; 131 uint32_t avail_xcp_modes; 132 }; 133 134 struct amdgpu_xcp_mgr_funcs { 135 int (*switch_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr, int mode, 136 int *num_xcps); 137 int (*query_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr); 138 int (*get_ip_details)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 139 enum AMDGPU_XCP_IP_BLOCK ip_id, 140 struct amdgpu_xcp_ip *ip); 141 int (*get_xcp_mem_id)(struct amdgpu_xcp_mgr *xcp_mgr, 142 struct amdgpu_xcp *xcp, uint8_t *mem_id); 143 int (*get_xcp_res_info)(struct amdgpu_xcp_mgr *xcp_mgr, 144 int mode, 145 struct amdgpu_xcp_cfg *xcp_cfg); 146 int (*prepare_suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 147 int (*suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 148 int (*prepare_resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 149 int (*resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 150 }; 151 152 int amdgpu_xcp_prepare_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 153 int amdgpu_xcp_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 154 int amdgpu_xcp_prepare_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 155 int amdgpu_xcp_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); 156 157 int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode, 158 int init_xcps, struct amdgpu_xcp_mgr_funcs *xcp_funcs); 159 int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode); 160 int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags); 161 int amdgpu_xcp_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, int mode); 162 int amdgpu_xcp_restore_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr); 163 int amdgpu_xcp_get_partition(struct amdgpu_xcp_mgr *xcp_mgr, 164 enum AMDGPU_XCP_IP_BLOCK ip, int instance); 165 166 int amdgpu_xcp_get_inst_details(struct amdgpu_xcp *xcp, 167 enum AMDGPU_XCP_IP_BLOCK ip, 168 uint32_t *inst_mask); 169 170 int amdgpu_xcp_dev_register(struct amdgpu_device *adev, 171 const struct pci_device_id *ent); 172 void amdgpu_xcp_dev_unplug(struct amdgpu_device *adev); 173 int amdgpu_xcp_open_device(struct amdgpu_device *adev, 174 struct amdgpu_fpriv *fpriv, 175 struct drm_file *file_priv); 176 void amdgpu_xcp_release_sched(struct amdgpu_device *adev, 177 struct amdgpu_ctx_entity *entity); 178 int amdgpu_xcp_select_scheds(struct amdgpu_device *adev, 179 u32 hw_ip, u32 hw_prio, 180 struct amdgpu_fpriv *fpriv, 181 unsigned int *num_scheds, 182 struct drm_gpu_scheduler ***scheds); 183 void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr); 184 int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev); 185 int amdgpu_xcp_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags); 186 int amdgpu_xcp_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags); 187 void amdgpu_xcp_sysfs_init(struct amdgpu_device *adev); 188 void amdgpu_xcp_sysfs_fini(struct amdgpu_device *adev); 189 190 static inline int amdgpu_xcp_get_num_xcp(struct amdgpu_xcp_mgr *xcp_mgr) 191 { 192 if (!xcp_mgr) 193 return 1; 194 else 195 return xcp_mgr->num_xcps; 196 } 197 198 static inline struct amdgpu_xcp * 199 amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from) 200 { 201 if (!xcp_mgr) 202 return NULL; 203 204 while (*from < MAX_XCP) { 205 if (xcp_mgr->xcp[*from].valid) 206 return &xcp_mgr->xcp[*from]; 207 ++(*from); 208 } 209 210 return NULL; 211 } 212 213 #define for_each_xcp(xcp_mgr, xcp, i) \ 214 for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &i); xcp; \ 215 ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) 216 217 #endif 218