1 /* SPDX-License-Identifier: MIT 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_VRAM_MGR_H__ 25 #define __AMDGPU_VRAM_MGR_H__ 26 27 #include <linux/gpu_buddy.h> 28 29 struct dmem_cgroup_region; 30 31 struct amdgpu_vram_mgr { 32 struct ttm_resource_manager manager; 33 struct gpu_buddy mm; 34 /* protects access to buffer objects */ 35 struct mutex lock; 36 struct list_head reservations_pending; 37 struct list_head reserved_pages; 38 atomic64_t vis_usage; 39 u64 default_page_size; 40 struct list_head allocated_vres_list; 41 struct dmem_cgroup_region *cg_region; 42 }; 43 44 struct amdgpu_vres_task { 45 pid_t pid; 46 char comm[TASK_COMM_LEN]; 47 }; 48 49 struct amdgpu_vram_block_info { 50 u64 start; 51 u64 size; 52 struct amdgpu_vres_task task; 53 }; 54 55 struct amdgpu_vram_mgr_resource { 56 struct ttm_resource base; 57 struct list_head blocks; 58 unsigned long flags; 59 struct list_head vres_node; 60 struct amdgpu_vres_task task; 61 }; 62 63 static inline u64 amdgpu_vram_mgr_block_start(struct gpu_buddy_block *block) 64 { 65 return gpu_buddy_block_offset(block); 66 } 67 68 static inline u64 amdgpu_vram_mgr_block_size(struct gpu_buddy_block *block) 69 { 70 return (u64)PAGE_SIZE << gpu_buddy_block_order(block); 71 } 72 73 static inline bool amdgpu_vram_mgr_is_cleared(struct gpu_buddy_block *block) 74 { 75 return gpu_buddy_block_is_clear(block); 76 } 77 78 static inline struct amdgpu_vram_mgr_resource * 79 to_amdgpu_vram_mgr_resource(struct ttm_resource *res) 80 { 81 return container_of(res, struct amdgpu_vram_mgr_resource, base); 82 } 83 84 static inline void amdgpu_vram_mgr_set_cleared(struct ttm_resource *res) 85 { 86 struct amdgpu_vram_mgr_resource *ares = to_amdgpu_vram_mgr_resource(res); 87 88 WARN_ON(ares->flags & GPU_BUDDY_CLEARED); 89 ares->flags |= GPU_BUDDY_CLEARED; 90 } 91 92 int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr, 93 uint64_t address, struct amdgpu_vram_block_info *info); 94 95 #endif 96