1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <drm/drm_drv.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_vpe.h" 29 #include "amdgpu_smu.h" 30 #include "soc15_common.h" 31 #include "vpe_v6_1.h" 32 33 #define AMDGPU_CSA_VPE_SIZE 64 34 /* VPE CSA resides in the 4th page of CSA */ 35 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3) 36 37 /* 1 second timeout */ 38 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000) 39 40 #define VPE_MAX_DPM_LEVEL 4 41 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8 42 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART) 43 44 static void vpe_set_ring_funcs(struct amdgpu_device *adev); 45 46 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) 47 { 48 *remainder = dividend % divisor; 49 return dividend / divisor; 50 } 51 52 static inline uint16_t complete_integer_division_u16( 53 uint16_t dividend, 54 uint16_t divisor, 55 uint16_t *remainder) 56 { 57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder); 58 } 59 60 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) 61 { 62 u16 arg1_value = numerator; 63 u16 arg2_value = denominator; 64 65 uint16_t remainder; 66 67 /* determine integer part */ 68 uint16_t res_value = complete_integer_division_u16( 69 arg1_value, arg2_value, &remainder); 70 71 if (res_value > 127 /* CHAR_MAX */) 72 return 0; 73 74 /* determine fractional part */ 75 { 76 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART; 77 78 do { 79 remainder <<= 1; 80 81 res_value <<= 1; 82 83 if (remainder >= arg2_value) { 84 res_value |= 1; 85 remainder -= arg2_value; 86 } 87 } while (--i != 0); 88 } 89 90 /* round up LSB */ 91 { 92 uint16_t summand = (remainder << 1) >= arg2_value; 93 94 if ((res_value + summand) > 32767 /* SHRT_MAX */) 95 return 0; 96 97 res_value += summand; 98 } 99 100 return res_value; 101 } 102 103 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) 104 { 105 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency); 106 107 if (GET_PRATIO_INTEGER_PART(pratio) > 1) 108 pratio = 0; 109 110 return pratio; 111 } 112 113 /* 114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), 115 * VPE FW will dynamically decide which level should be used according to current loading. 116 * 117 * Get VPE and SOC clocks from PM, and select the appropriate four clock values, 118 * calculate the ratios of adjusting from one clock to another. 119 * The VPE FW can then request the appropriate frequency from the PMFW. 120 */ 121 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) 122 { 123 struct amdgpu_device *adev = vpe->ring.adev; 124 uint32_t dpm_ctl; 125 126 if (adev->pm.dpm_enabled) { 127 struct dpm_clocks clock_table = { 0 }; 128 struct dpm_clock *VPEClks; 129 struct dpm_clock *SOCClks; 130 uint32_t idx; 131 uint32_t vpeclk_enalbled_num = 0; 132 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0; 133 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0; 134 135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 136 dpm_ctl |= 1; /* DPM enablement */ 137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 138 139 /* Get VPECLK and SOCCLK */ 140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { 141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); 142 goto disable_dpm; 143 } 144 145 SOCClks = clock_table.SocClocks; 146 VPEClks = clock_table.VPEClocks; 147 148 /* Comfirm enabled vpe clk num 149 * Enabled VPE clocks are ordered from low to high in VPEClks 150 * The highest valid clock index+1 is the number of VPEClks 151 */ 152 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--) 153 if (VPEClks[idx-1].Freq) 154 vpeclk_enalbled_num = idx; 155 156 /* vpe dpm only cares 4 levels. */ 157 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) { 158 uint32_t soc_dpm_level; 159 uint32_t min_freq; 160 161 if (idx == 0) 162 soc_dpm_level = 0; 163 else 164 soc_dpm_level = (idx * 2) + 1; 165 166 /* clamp the max level */ 167 if (soc_dpm_level > vpeclk_enalbled_num - 1) 168 soc_dpm_level = vpeclk_enalbled_num - 1; 169 170 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ? 171 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq; 172 173 switch (idx) { 174 case 0: 175 pratio_vmin_freq = min_freq; 176 break; 177 case 1: 178 pratio_vmid_freq = min_freq; 179 break; 180 case 2: 181 pratio_vnorm_freq = min_freq; 182 break; 183 case 3: 184 pratio_vmax_freq = min_freq; 185 break; 186 default: 187 break; 188 } 189 } 190 191 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) { 192 uint32_t pratio_ctl; 193 194 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq); 195 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq); 196 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq); 197 198 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18); 199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */ 200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */ 201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */ 202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */ 203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */ 204 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__); 205 } else { 206 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__); 207 goto disable_dpm; 208 } 209 } 210 return 0; 211 212 disable_dpm: 213 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 214 dpm_ctl &= 0xfffffffe; /* Disable DPM */ 215 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 216 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); 217 return -EINVAL; 218 } 219 220 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) 221 { 222 struct amdgpu_firmware_info ucode = { 223 .ucode_id = AMDGPU_UCODE_ID_VPE, 224 .mc_addr = adev->vpe.cmdbuf_gpu_addr, 225 .ucode_size = 8, 226 }; 227 228 return psp_execute_ip_fw_load(&adev->psp, &ucode); 229 } 230 231 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) 232 { 233 struct amdgpu_device *adev = vpe->ring.adev; 234 const struct vpe_firmware_header_v1_0 *vpe_hdr; 235 char fw_prefix[32], fw_name[64]; 236 int ret; 237 238 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix)); 239 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", fw_prefix); 240 241 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, fw_name); 242 if (ret) 243 goto out; 244 245 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 246 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); 247 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); 248 249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 250 struct amdgpu_firmware_info *info; 251 252 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX]; 253 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX; 254 info->fw = adev->vpe.fw; 255 adev->firmware.fw_size += 256 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 257 258 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL]; 259 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL; 260 info->fw = adev->vpe.fw; 261 adev->firmware.fw_size += 262 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 263 } 264 265 return 0; 266 out: 267 dev_err(adev->dev, "fail to initialize vpe microcode\n"); 268 release_firmware(adev->vpe.fw); 269 adev->vpe.fw = NULL; 270 return ret; 271 } 272 273 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) 274 { 275 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 276 struct amdgpu_ring *ring = &vpe->ring; 277 int ret; 278 279 ring->ring_obj = NULL; 280 ring->use_doorbell = true; 281 ring->vm_hub = AMDGPU_MMHUB0(0); 282 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1); 283 snprintf(ring->name, 4, "vpe"); 284 285 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0, 286 AMDGPU_RING_PRIO_DEFAULT, NULL); 287 if (ret) 288 return ret; 289 290 return 0; 291 } 292 293 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) 294 { 295 amdgpu_ring_fini(&vpe->ring); 296 297 return 0; 298 } 299 300 static int vpe_early_init(void *handle) 301 { 302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 303 struct amdgpu_vpe *vpe = &adev->vpe; 304 305 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 306 case IP_VERSION(6, 1, 0): 307 vpe_v6_1_set_funcs(vpe); 308 break; 309 case IP_VERSION(6, 1, 1): 310 vpe_v6_1_set_funcs(vpe); 311 vpe->collaborate_mode = true; 312 break; 313 default: 314 return -EINVAL; 315 } 316 317 vpe_set_ring_funcs(adev); 318 vpe_set_regs(vpe); 319 320 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false"); 321 322 return 0; 323 } 324 325 static void vpe_idle_work_handler(struct work_struct *work) 326 { 327 struct amdgpu_device *adev = 328 container_of(work, struct amdgpu_device, vpe.idle_work.work); 329 unsigned int fences = 0; 330 331 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 332 333 if (fences == 0) 334 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 335 else 336 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 337 } 338 339 static int vpe_common_init(struct amdgpu_vpe *vpe) 340 { 341 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 342 int r; 343 344 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 345 AMDGPU_GEM_DOMAIN_GTT, 346 &adev->vpe.cmdbuf_obj, 347 &adev->vpe.cmdbuf_gpu_addr, 348 (void **)&adev->vpe.cmdbuf_cpu_addr); 349 if (r) { 350 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r); 351 return r; 352 } 353 354 vpe->context_started = false; 355 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler); 356 357 return 0; 358 } 359 360 static int vpe_sw_init(void *handle) 361 { 362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 363 struct amdgpu_vpe *vpe = &adev->vpe; 364 int ret; 365 366 ret = vpe_common_init(vpe); 367 if (ret) 368 goto out; 369 370 ret = vpe_irq_init(vpe); 371 if (ret) 372 goto out; 373 374 ret = vpe_ring_init(vpe); 375 if (ret) 376 goto out; 377 378 ret = vpe_init_microcode(vpe); 379 if (ret) 380 goto out; 381 out: 382 return ret; 383 } 384 385 static int vpe_sw_fini(void *handle) 386 { 387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 388 struct amdgpu_vpe *vpe = &adev->vpe; 389 390 release_firmware(vpe->fw); 391 vpe->fw = NULL; 392 393 vpe_ring_fini(vpe); 394 395 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj, 396 &adev->vpe.cmdbuf_gpu_addr, 397 (void **)&adev->vpe.cmdbuf_cpu_addr); 398 399 return 0; 400 } 401 402 static int vpe_hw_init(void *handle) 403 { 404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 405 struct amdgpu_vpe *vpe = &adev->vpe; 406 int ret; 407 408 /* Power on VPE */ 409 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 410 AMD_PG_STATE_UNGATE); 411 if (ret) 412 return ret; 413 414 ret = vpe_load_microcode(vpe); 415 if (ret) 416 return ret; 417 418 ret = vpe_ring_start(vpe); 419 if (ret) 420 return ret; 421 422 return 0; 423 } 424 425 static int vpe_hw_fini(void *handle) 426 { 427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 428 struct amdgpu_vpe *vpe = &adev->vpe; 429 430 vpe_ring_stop(vpe); 431 432 /* Power off VPE */ 433 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 434 435 return 0; 436 } 437 438 static int vpe_suspend(void *handle) 439 { 440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 441 442 cancel_delayed_work_sync(&adev->vpe.idle_work); 443 444 return vpe_hw_fini(adev); 445 } 446 447 static int vpe_resume(void *handle) 448 { 449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 450 451 return vpe_hw_init(adev); 452 } 453 454 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 455 { 456 int i; 457 458 for (i = 0; i < count; i++) 459 if (i == 0) 460 amdgpu_ring_write(ring, ring->funcs->nop | 461 VPE_CMD_NOP_HEADER_COUNT(count - 1)); 462 else 463 amdgpu_ring_write(ring, ring->funcs->nop); 464 } 465 466 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) 467 { 468 struct amdgpu_device *adev = ring->adev; 469 uint32_t index = 0; 470 uint64_t csa_mc_addr; 471 472 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) 473 return 0; 474 475 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET + 476 index * AMDGPU_CSA_VPE_SIZE; 477 478 return csa_mc_addr; 479 } 480 481 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring, 482 uint32_t device_select, 483 uint32_t exec_count) 484 { 485 if (!ring->adev->vpe.collaborate_mode) 486 return; 487 488 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | 489 (device_select << 16)); 490 amdgpu_ring_write(ring, exec_count & 0x1fff); 491 } 492 493 static void vpe_ring_emit_ib(struct amdgpu_ring *ring, 494 struct amdgpu_job *job, 495 struct amdgpu_ib *ib, 496 uint32_t flags) 497 { 498 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 499 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid); 500 501 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | 502 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf)); 503 504 /* base must be 32 byte aligned */ 505 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); 506 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 507 amdgpu_ring_write(ring, ib->length_dw); 508 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 509 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 510 } 511 512 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 513 uint64_t seq, unsigned int flags) 514 { 515 int i = 0; 516 517 do { 518 /* write the fence */ 519 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 520 /* zero in first two bits */ 521 WARN_ON_ONCE(addr & 0x3); 522 amdgpu_ring_write(ring, lower_32_bits(addr)); 523 amdgpu_ring_write(ring, upper_32_bits(addr)); 524 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); 525 addr += 4; 526 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1)); 527 528 if (flags & AMDGPU_FENCE_FLAG_INT) { 529 /* generate an interrupt */ 530 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); 531 amdgpu_ring_write(ring, 0); 532 } 533 534 } 535 536 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 537 { 538 uint32_t seq = ring->fence_drv.sync_seq; 539 uint64_t addr = ring->fence_drv.gpu_addr; 540 541 vpe_ring_emit_pred_exec(ring, 0, 6); 542 543 /* wait for idle */ 544 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 545 VPE_POLL_REGMEM_SUBOP_REGMEM) | 546 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 547 VPE_CMD_POLL_REGMEM_HEADER_MEM(1)); 548 amdgpu_ring_write(ring, addr & 0xfffffffc); 549 amdgpu_ring_write(ring, upper_32_bits(addr)); 550 amdgpu_ring_write(ring, seq); /* reference */ 551 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 552 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 553 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4)); 554 } 555 556 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 557 { 558 vpe_ring_emit_pred_exec(ring, 0, 3); 559 560 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); 561 amdgpu_ring_write(ring, reg << 2); 562 amdgpu_ring_write(ring, val); 563 } 564 565 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 566 uint32_t val, uint32_t mask) 567 { 568 vpe_ring_emit_pred_exec(ring, 0, 6); 569 570 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 571 VPE_POLL_REGMEM_SUBOP_REGMEM) | 572 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 573 VPE_CMD_POLL_REGMEM_HEADER_MEM(0)); 574 amdgpu_ring_write(ring, reg << 2); 575 amdgpu_ring_write(ring, 0); 576 amdgpu_ring_write(ring, val); /* reference */ 577 amdgpu_ring_write(ring, mask); /* mask */ 578 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 579 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10)); 580 } 581 582 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, 583 uint64_t pd_addr) 584 { 585 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 586 } 587 588 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring, 589 uint64_t addr) 590 { 591 unsigned int ret; 592 593 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); 594 amdgpu_ring_write(ring, lower_32_bits(addr)); 595 amdgpu_ring_write(ring, upper_32_bits(addr)); 596 amdgpu_ring_write(ring, 1); 597 ret = ring->wptr & ring->buf_mask; 598 amdgpu_ring_write(ring, 0); 599 600 return ret; 601 } 602 603 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) 604 { 605 struct amdgpu_device *adev = ring->adev; 606 struct amdgpu_vpe *vpe = &adev->vpe; 607 uint32_t preempt_reg = vpe->regs.queue0_preempt; 608 int i, r = 0; 609 610 /* assert preemption condition */ 611 amdgpu_ring_set_preempt_cond_exec(ring, false); 612 613 /* emit the trailing fence */ 614 ring->trail_seq += 1; 615 amdgpu_ring_alloc(ring, 10); 616 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0); 617 amdgpu_ring_commit(ring); 618 619 /* assert IB preemption */ 620 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1); 621 622 /* poll the trailing fence */ 623 for (i = 0; i < adev->usec_timeout; i++) { 624 if (ring->trail_seq == 625 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 626 break; 627 udelay(1); 628 } 629 630 if (i >= adev->usec_timeout) { 631 r = -EINVAL; 632 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx); 633 } 634 635 /* deassert IB preemption */ 636 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0); 637 638 /* deassert the preemption condition */ 639 amdgpu_ring_set_preempt_cond_exec(ring, true); 640 641 return r; 642 } 643 644 static int vpe_set_clockgating_state(void *handle, 645 enum amd_clockgating_state state) 646 { 647 return 0; 648 } 649 650 static int vpe_set_powergating_state(void *handle, 651 enum amd_powergating_state state) 652 { 653 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 654 struct amdgpu_vpe *vpe = &adev->vpe; 655 656 if (!adev->pm.dpm_enabled) 657 dev_err(adev->dev, "Without PM, cannot support powergating\n"); 658 659 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE"); 660 661 if (state == AMD_PG_STATE_GATE) { 662 amdgpu_dpm_enable_vpe(adev, false); 663 vpe->context_started = false; 664 } else { 665 amdgpu_dpm_enable_vpe(adev, true); 666 } 667 668 return 0; 669 } 670 671 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) 672 { 673 struct amdgpu_device *adev = ring->adev; 674 struct amdgpu_vpe *vpe = &adev->vpe; 675 uint64_t rptr; 676 677 if (ring->use_doorbell) { 678 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr); 679 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr); 680 } else { 681 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi)); 682 rptr = rptr << 32; 683 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo)); 684 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr); 685 } 686 687 return (rptr >> 2); 688 } 689 690 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) 691 { 692 struct amdgpu_device *adev = ring->adev; 693 struct amdgpu_vpe *vpe = &adev->vpe; 694 uint64_t wptr; 695 696 if (ring->use_doorbell) { 697 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 698 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr); 699 } else { 700 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi)); 701 wptr = wptr << 32; 702 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo)); 703 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr); 704 } 705 706 return (wptr >> 2); 707 } 708 709 static void vpe_ring_set_wptr(struct amdgpu_ring *ring) 710 { 711 struct amdgpu_device *adev = ring->adev; 712 struct amdgpu_vpe *vpe = &adev->vpe; 713 714 if (ring->use_doorbell) { 715 dev_dbg(adev->dev, "Using doorbell, \ 716 wptr_offs == 0x%08x, \ 717 lower_32_bits(ring->wptr) << 2 == 0x%08x, \ 718 upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 719 ring->wptr_offs, 720 lower_32_bits(ring->wptr << 2), 721 upper_32_bits(ring->wptr << 2)); 722 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2); 723 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 724 if (vpe->collaborate_mode) 725 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2); 726 } else { 727 int i; 728 729 for (i = 0; i < vpe->num_instances; i++) { 730 dev_dbg(adev->dev, "Not using doorbell, \ 731 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \ 732 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n", 733 lower_32_bits(ring->wptr << 2), 734 upper_32_bits(ring->wptr << 2)); 735 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo), 736 lower_32_bits(ring->wptr << 2)); 737 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi), 738 upper_32_bits(ring->wptr << 2)); 739 } 740 } 741 } 742 743 static int vpe_ring_test_ring(struct amdgpu_ring *ring) 744 { 745 struct amdgpu_device *adev = ring->adev; 746 const uint32_t test_pattern = 0xdeadbeef; 747 uint32_t index, i; 748 uint64_t wb_addr; 749 int ret; 750 751 ret = amdgpu_device_wb_get(adev, &index); 752 if (ret) { 753 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 754 return ret; 755 } 756 757 adev->wb.wb[index] = 0; 758 wb_addr = adev->wb.gpu_addr + (index * 4); 759 760 ret = amdgpu_ring_alloc(ring, 4); 761 if (ret) { 762 dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret); 763 goto out; 764 } 765 766 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 767 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); 768 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); 769 amdgpu_ring_write(ring, test_pattern); 770 amdgpu_ring_commit(ring); 771 772 for (i = 0; i < adev->usec_timeout; i++) { 773 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern) 774 goto out; 775 udelay(1); 776 } 777 778 ret = -ETIMEDOUT; 779 out: 780 amdgpu_device_wb_free(adev, index); 781 782 return ret; 783 } 784 785 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) 786 { 787 struct amdgpu_device *adev = ring->adev; 788 const uint32_t test_pattern = 0xdeadbeef; 789 struct amdgpu_ib ib = {}; 790 struct dma_fence *f = NULL; 791 uint32_t index; 792 uint64_t wb_addr; 793 int ret; 794 795 ret = amdgpu_device_wb_get(adev, &index); 796 if (ret) { 797 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 798 return ret; 799 } 800 801 adev->wb.wb[index] = 0; 802 wb_addr = adev->wb.gpu_addr + (index * 4); 803 804 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 805 if (ret) 806 goto err0; 807 808 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0); 809 ib.ptr[1] = lower_32_bits(wb_addr); 810 ib.ptr[2] = upper_32_bits(wb_addr); 811 ib.ptr[3] = test_pattern; 812 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 813 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 814 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 815 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 816 ib.length_dw = 8; 817 818 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 819 if (ret) 820 goto err1; 821 822 ret = dma_fence_wait_timeout(f, false, timeout); 823 if (ret <= 0) { 824 ret = ret ? : -ETIMEDOUT; 825 goto err1; 826 } 827 828 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL; 829 830 err1: 831 amdgpu_ib_free(adev, &ib, NULL); 832 dma_fence_put(f); 833 err0: 834 amdgpu_device_wb_free(adev, index); 835 836 return ret; 837 } 838 839 static void vpe_ring_begin_use(struct amdgpu_ring *ring) 840 { 841 struct amdgpu_device *adev = ring->adev; 842 struct amdgpu_vpe *vpe = &adev->vpe; 843 844 cancel_delayed_work_sync(&adev->vpe.idle_work); 845 846 /* Power on VPE and notify VPE of new context */ 847 if (!vpe->context_started) { 848 uint32_t context_notify; 849 850 /* Power on VPE */ 851 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE); 852 853 /* Indicates that a job from a new context has been submitted. */ 854 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator)); 855 if ((context_notify & 0x1) == 0) 856 context_notify |= 0x1; 857 else 858 context_notify &= ~(0x1); 859 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify); 860 vpe->context_started = true; 861 } 862 } 863 864 static void vpe_ring_end_use(struct amdgpu_ring *ring) 865 { 866 struct amdgpu_device *adev = ring->adev; 867 868 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 869 } 870 871 static const struct amdgpu_ring_funcs vpe_ring_funcs = { 872 .type = AMDGPU_RING_TYPE_VPE, 873 .align_mask = 0xf, 874 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0), 875 .support_64bit_ptrs = true, 876 .get_rptr = vpe_ring_get_rptr, 877 .get_wptr = vpe_ring_get_wptr, 878 .set_wptr = vpe_ring_set_wptr, 879 .emit_frame_size = 880 5 + /* vpe_ring_init_cond_exec */ 881 6 + /* vpe_ring_emit_pipeline_sync */ 882 10 + 10 + 10 + /* vpe_ring_emit_fence */ 883 /* vpe_ring_emit_vm_flush */ 884 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 885 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, 886 .emit_ib_size = 7 + 6, 887 .emit_ib = vpe_ring_emit_ib, 888 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync, 889 .emit_fence = vpe_ring_emit_fence, 890 .emit_vm_flush = vpe_ring_emit_vm_flush, 891 .emit_wreg = vpe_ring_emit_wreg, 892 .emit_reg_wait = vpe_ring_emit_reg_wait, 893 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 894 .insert_nop = vpe_ring_insert_nop, 895 .pad_ib = amdgpu_ring_generic_pad_ib, 896 .test_ring = vpe_ring_test_ring, 897 .test_ib = vpe_ring_test_ib, 898 .init_cond_exec = vpe_ring_init_cond_exec, 899 .preempt_ib = vpe_ring_preempt_ib, 900 .begin_use = vpe_ring_begin_use, 901 .end_use = vpe_ring_end_use, 902 }; 903 904 static void vpe_set_ring_funcs(struct amdgpu_device *adev) 905 { 906 adev->vpe.ring.funcs = &vpe_ring_funcs; 907 } 908 909 const struct amd_ip_funcs vpe_ip_funcs = { 910 .name = "vpe_v6_1", 911 .early_init = vpe_early_init, 912 .late_init = NULL, 913 .sw_init = vpe_sw_init, 914 .sw_fini = vpe_sw_fini, 915 .hw_init = vpe_hw_init, 916 .hw_fini = vpe_hw_fini, 917 .suspend = vpe_suspend, 918 .resume = vpe_resume, 919 .soft_reset = NULL, 920 .set_clockgating_state = vpe_set_clockgating_state, 921 .set_powergating_state = vpe_set_powergating_state, 922 }; 923 924 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { 925 .type = AMD_IP_BLOCK_TYPE_VPE, 926 .major = 6, 927 .minor = 1, 928 .rev = 0, 929 .funcs = &vpe_ip_funcs, 930 }; 931