1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <drm/drm_drv.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_vpe.h" 29 #include "amdgpu_smu.h" 30 #include "soc15_common.h" 31 #include "vpe_v6_1.h" 32 #include "vpe_v2_0.h" 33 34 #define AMDGPU_CSA_VPE_SIZE 64 35 /* VPE CSA resides in the 4th page of CSA */ 36 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3) 37 38 /* 1 second timeout */ 39 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000) 40 41 #define VPE_MAX_DPM_LEVEL 4 42 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8 43 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART) 44 45 static void vpe_set_ring_funcs(struct amdgpu_device *adev); 46 47 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) 48 { 49 *remainder = dividend % divisor; 50 return dividend / divisor; 51 } 52 53 static inline uint16_t complete_integer_division_u16( 54 uint16_t dividend, 55 uint16_t divisor, 56 uint16_t *remainder) 57 { 58 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder); 59 } 60 61 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) 62 { 63 u16 arg1_value = numerator; 64 u16 arg2_value = denominator; 65 66 uint16_t remainder; 67 68 /* determine integer part */ 69 uint16_t res_value = complete_integer_division_u16( 70 arg1_value, arg2_value, &remainder); 71 72 if (res_value > 127 /* CHAR_MAX */) 73 return 0; 74 75 /* determine fractional part */ 76 { 77 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART; 78 79 do { 80 remainder <<= 1; 81 82 res_value <<= 1; 83 84 if (remainder >= arg2_value) { 85 res_value |= 1; 86 remainder -= arg2_value; 87 } 88 } while (--i != 0); 89 } 90 91 /* round up LSB */ 92 { 93 uint16_t summand = (remainder << 1) >= arg2_value; 94 95 if ((res_value + summand) > 32767 /* SHRT_MAX */) 96 return 0; 97 98 res_value += summand; 99 } 100 101 return res_value; 102 } 103 104 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) 105 { 106 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency); 107 108 if (GET_PRATIO_INTEGER_PART(pratio) > 1) 109 pratio = 0; 110 111 return pratio; 112 } 113 114 /* 115 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), 116 * VPE FW will dynamically decide which level should be used according to current loading. 117 * 118 * Get VPE and SOC clocks from PM, and select the appropriate four clock values, 119 * calculate the ratios of adjusting from one clock to another. 120 * The VPE FW can then request the appropriate frequency from the PMFW. 121 */ 122 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) 123 { 124 struct amdgpu_device *adev = vpe->ring.adev; 125 uint32_t dpm_ctl; 126 127 if (adev->pm.dpm_enabled) { 128 struct dpm_clocks clock_table = { 0 }; 129 struct dpm_clock *VPEClks; 130 struct dpm_clock *SOCClks; 131 uint32_t idx; 132 uint32_t vpeclk_enalbled_num = 0; 133 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0; 134 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0; 135 136 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 137 dpm_ctl |= 1; /* DPM enablement */ 138 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 139 140 /* Get VPECLK and SOCCLK */ 141 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { 142 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); 143 goto disable_dpm; 144 } 145 146 SOCClks = clock_table.SocClocks; 147 VPEClks = clock_table.VPEClocks; 148 149 /* Comfirm enabled vpe clk num 150 * Enabled VPE clocks are ordered from low to high in VPEClks 151 * The highest valid clock index+1 is the number of VPEClks 152 */ 153 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--) 154 if (VPEClks[idx-1].Freq) 155 vpeclk_enalbled_num = idx; 156 157 /* vpe dpm only cares 4 levels. */ 158 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) { 159 uint32_t soc_dpm_level; 160 uint32_t min_freq; 161 162 if (idx == 0) 163 soc_dpm_level = 0; 164 else 165 soc_dpm_level = (idx * 2) + 1; 166 167 /* clamp the max level */ 168 if (soc_dpm_level > vpeclk_enalbled_num - 1) 169 soc_dpm_level = vpeclk_enalbled_num - 1; 170 171 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ? 172 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq; 173 174 switch (idx) { 175 case 0: 176 pratio_vmin_freq = min_freq; 177 break; 178 case 1: 179 pratio_vmid_freq = min_freq; 180 break; 181 case 2: 182 pratio_vnorm_freq = min_freq; 183 break; 184 case 3: 185 pratio_vmax_freq = min_freq; 186 break; 187 default: 188 break; 189 } 190 } 191 192 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) { 193 uint32_t pratio_ctl; 194 195 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq); 196 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq); 197 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq); 198 199 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18); 200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */ 201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */ 202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */ 203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */ 204 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */ 205 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__); 206 } else { 207 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__); 208 goto disable_dpm; 209 } 210 } 211 return 0; 212 213 disable_dpm: 214 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 215 dpm_ctl &= 0xfffffffe; /* Disable DPM */ 216 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 217 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); 218 return -EINVAL; 219 } 220 221 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) 222 { 223 struct amdgpu_firmware_info ucode = { 224 .ucode_id = AMDGPU_UCODE_ID_VPE, 225 .mc_addr = adev->vpe.cmdbuf_gpu_addr, 226 .ucode_size = 8, 227 }; 228 229 return psp_execute_ip_fw_load(&adev->psp, &ucode); 230 } 231 232 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) 233 { 234 struct amdgpu_device *adev = vpe->ring.adev; 235 const struct vpe_firmware_header_v1_0 *vpe_hdr; 236 char fw_prefix[32]; 237 int ret; 238 239 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix)); 240 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED, 241 "amdgpu/%s.bin", fw_prefix); 242 if (ret) 243 goto out; 244 245 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 246 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); 247 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); 248 249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 250 struct amdgpu_firmware_info *info; 251 252 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX]; 253 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX; 254 info->fw = adev->vpe.fw; 255 adev->firmware.fw_size += 256 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 257 258 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL]; 259 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL; 260 info->fw = adev->vpe.fw; 261 adev->firmware.fw_size += 262 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 263 } 264 265 return 0; 266 out: 267 dev_err(adev->dev, "fail to initialize vpe microcode\n"); 268 release_firmware(adev->vpe.fw); 269 adev->vpe.fw = NULL; 270 return ret; 271 } 272 273 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) 274 { 275 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 276 struct amdgpu_ring *ring = &vpe->ring; 277 int ret; 278 279 ring->ring_obj = NULL; 280 ring->use_doorbell = true; 281 ring->vm_hub = AMDGPU_MMHUB0(0); 282 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1); 283 snprintf(ring->name, 4, "vpe"); 284 285 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0, 286 AMDGPU_RING_PRIO_DEFAULT, NULL); 287 if (ret) 288 return ret; 289 290 return 0; 291 } 292 293 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) 294 { 295 amdgpu_ring_fini(&vpe->ring); 296 297 return 0; 298 } 299 300 static int vpe_early_init(struct amdgpu_ip_block *ip_block) 301 { 302 struct amdgpu_device *adev = ip_block->adev; 303 struct amdgpu_vpe *vpe = &adev->vpe; 304 305 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 306 case IP_VERSION(6, 1, 0): 307 case IP_VERSION(6, 1, 3): 308 vpe_v6_1_set_funcs(vpe); 309 break; 310 case IP_VERSION(6, 1, 1): 311 vpe_v6_1_set_funcs(vpe); 312 vpe->collaborate_mode = true; 313 break; 314 case IP_VERSION(2, 0, 0): 315 vpe_v2_0_set_funcs(vpe); 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 vpe_set_ring_funcs(adev); 322 vpe_set_regs(vpe); 323 324 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false"); 325 326 return 0; 327 } 328 329 static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev) 330 { 331 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 332 case IP_VERSION(6, 1, 1): 333 return adev->pm.fw_version < 0x0a640500; 334 default: 335 return false; 336 } 337 } 338 339 static int vpe_get_dpm_level(struct amdgpu_device *adev) 340 { 341 struct amdgpu_vpe *vpe = &adev->vpe; 342 343 if (!adev->pm.dpm_enabled) 344 return 0; 345 346 return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv)); 347 } 348 349 static void vpe_idle_work_handler(struct work_struct *work) 350 { 351 struct amdgpu_device *adev = 352 container_of(work, struct amdgpu_device, vpe.idle_work.work); 353 unsigned int fences = 0; 354 355 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 356 if (fences) 357 goto reschedule; 358 359 if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0) 360 goto reschedule; 361 362 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 363 return; 364 365 reschedule: 366 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 367 } 368 369 static int vpe_common_init(struct amdgpu_vpe *vpe) 370 { 371 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 372 int r; 373 374 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 375 AMDGPU_GEM_DOMAIN_GTT, 376 &adev->vpe.cmdbuf_obj, 377 &adev->vpe.cmdbuf_gpu_addr, 378 (void **)&adev->vpe.cmdbuf_cpu_addr); 379 if (r) { 380 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r); 381 return r; 382 } 383 384 vpe->context_started = false; 385 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler); 386 387 return 0; 388 } 389 390 static int vpe_sw_init(struct amdgpu_ip_block *ip_block) 391 { 392 struct amdgpu_device *adev = ip_block->adev; 393 struct amdgpu_vpe *vpe = &adev->vpe; 394 int ret; 395 396 ret = vpe_common_init(vpe); 397 if (ret) 398 goto out; 399 400 ret = vpe_irq_init(vpe); 401 if (ret) 402 goto out; 403 404 ret = vpe_ring_init(vpe); 405 if (ret) 406 goto out; 407 408 ret = vpe_init_microcode(vpe); 409 if (ret) 410 goto out; 411 412 adev->vpe.supported_reset = 413 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring); 414 if (!amdgpu_sriov_vf(adev)) 415 adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 416 ret = amdgpu_vpe_sysfs_reset_mask_init(adev); 417 if (ret) 418 goto out; 419 out: 420 return ret; 421 } 422 423 static int vpe_sw_fini(struct amdgpu_ip_block *ip_block) 424 { 425 struct amdgpu_device *adev = ip_block->adev; 426 struct amdgpu_vpe *vpe = &adev->vpe; 427 428 release_firmware(vpe->fw); 429 vpe->fw = NULL; 430 431 amdgpu_vpe_sysfs_reset_mask_fini(adev); 432 vpe_ring_fini(vpe); 433 434 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj, 435 &adev->vpe.cmdbuf_gpu_addr, 436 (void **)&adev->vpe.cmdbuf_cpu_addr); 437 438 return 0; 439 } 440 441 static int vpe_hw_init(struct amdgpu_ip_block *ip_block) 442 { 443 struct amdgpu_device *adev = ip_block->adev; 444 struct amdgpu_vpe *vpe = &adev->vpe; 445 int ret; 446 447 /* Power on VPE */ 448 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 449 AMD_PG_STATE_UNGATE); 450 if (ret) 451 return ret; 452 453 ret = vpe_load_microcode(vpe); 454 if (ret) 455 return ret; 456 457 ret = vpe_ring_start(vpe); 458 if (ret) 459 return ret; 460 461 return 0; 462 } 463 464 static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) 465 { 466 struct amdgpu_device *adev = ip_block->adev; 467 struct amdgpu_vpe *vpe = &adev->vpe; 468 469 cancel_delayed_work_sync(&adev->vpe.idle_work); 470 471 vpe_ring_stop(vpe); 472 473 /* Power off VPE */ 474 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 475 476 return 0; 477 } 478 479 static int vpe_suspend(struct amdgpu_ip_block *ip_block) 480 { 481 return vpe_hw_fini(ip_block); 482 } 483 484 static int vpe_resume(struct amdgpu_ip_block *ip_block) 485 { 486 return vpe_hw_init(ip_block); 487 } 488 489 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 490 { 491 int i; 492 493 for (i = 0; i < count; i++) 494 if (i == 0) 495 amdgpu_ring_write(ring, ring->funcs->nop | 496 VPE_CMD_NOP_HEADER_COUNT(count - 1)); 497 else 498 amdgpu_ring_write(ring, ring->funcs->nop); 499 } 500 501 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) 502 { 503 struct amdgpu_device *adev = ring->adev; 504 uint32_t index = 0; 505 uint64_t csa_mc_addr; 506 507 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) 508 return 0; 509 510 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET + 511 index * AMDGPU_CSA_VPE_SIZE; 512 513 return csa_mc_addr; 514 } 515 516 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring, 517 uint32_t device_select, 518 uint32_t exec_count) 519 { 520 if (!ring->adev->vpe.collaborate_mode) 521 return; 522 523 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | 524 (device_select << 16)); 525 amdgpu_ring_write(ring, exec_count & 0x1fff); 526 } 527 528 static void vpe_ring_emit_ib(struct amdgpu_ring *ring, 529 struct amdgpu_job *job, 530 struct amdgpu_ib *ib, 531 uint32_t flags) 532 { 533 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 534 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid); 535 536 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | 537 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf)); 538 539 /* base must be 32 byte aligned */ 540 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); 541 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 542 amdgpu_ring_write(ring, ib->length_dw); 543 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 544 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 545 } 546 547 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 548 uint64_t seq, unsigned int flags) 549 { 550 int i = 0; 551 552 do { 553 /* write the fence */ 554 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 555 /* zero in first two bits */ 556 WARN_ON_ONCE(addr & 0x3); 557 amdgpu_ring_write(ring, lower_32_bits(addr)); 558 amdgpu_ring_write(ring, upper_32_bits(addr)); 559 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); 560 addr += 4; 561 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1)); 562 563 if (flags & AMDGPU_FENCE_FLAG_INT) { 564 /* generate an interrupt */ 565 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); 566 amdgpu_ring_write(ring, 0); 567 } 568 569 /* WA: Force sync after TRAP to avoid VPE1 fail to power off */ 570 if (ring->adev->vpe.collaborate_mode) { 571 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLAB_SYNC, 0)); 572 amdgpu_ring_write(ring, 0xabcd); 573 } 574 } 575 576 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 577 { 578 uint32_t seq = ring->fence_drv.sync_seq; 579 uint64_t addr = ring->fence_drv.gpu_addr; 580 581 vpe_ring_emit_pred_exec(ring, 0, 6); 582 583 /* wait for idle */ 584 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 585 VPE_POLL_REGMEM_SUBOP_REGMEM) | 586 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 587 VPE_CMD_POLL_REGMEM_HEADER_MEM(1)); 588 amdgpu_ring_write(ring, addr & 0xfffffffc); 589 amdgpu_ring_write(ring, upper_32_bits(addr)); 590 amdgpu_ring_write(ring, seq); /* reference */ 591 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 592 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 593 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4)); 594 } 595 596 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 597 { 598 vpe_ring_emit_pred_exec(ring, 0, 3); 599 600 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); 601 amdgpu_ring_write(ring, reg << 2); 602 amdgpu_ring_write(ring, val); 603 } 604 605 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 606 uint32_t val, uint32_t mask) 607 { 608 vpe_ring_emit_pred_exec(ring, 0, 6); 609 610 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 611 VPE_POLL_REGMEM_SUBOP_REGMEM) | 612 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 613 VPE_CMD_POLL_REGMEM_HEADER_MEM(0)); 614 amdgpu_ring_write(ring, reg << 2); 615 amdgpu_ring_write(ring, 0); 616 amdgpu_ring_write(ring, val); /* reference */ 617 amdgpu_ring_write(ring, mask); /* mask */ 618 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 619 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10)); 620 } 621 622 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, 623 uint64_t pd_addr) 624 { 625 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 626 } 627 628 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring, 629 uint64_t addr) 630 { 631 unsigned int ret; 632 633 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); 634 amdgpu_ring_write(ring, lower_32_bits(addr)); 635 amdgpu_ring_write(ring, upper_32_bits(addr)); 636 amdgpu_ring_write(ring, 1); 637 ret = ring->wptr & ring->buf_mask; 638 amdgpu_ring_write(ring, 0); 639 640 return ret; 641 } 642 643 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) 644 { 645 struct amdgpu_device *adev = ring->adev; 646 struct amdgpu_vpe *vpe = &adev->vpe; 647 uint32_t preempt_reg = vpe->regs.queue0_preempt; 648 int i, r = 0; 649 650 /* assert preemption condition */ 651 amdgpu_ring_set_preempt_cond_exec(ring, false); 652 653 /* emit the trailing fence */ 654 ring->trail_seq += 1; 655 amdgpu_ring_alloc(ring, 10); 656 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0); 657 amdgpu_ring_commit(ring); 658 659 /* assert IB preemption */ 660 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1); 661 662 /* poll the trailing fence */ 663 for (i = 0; i < adev->usec_timeout; i++) { 664 if (ring->trail_seq == 665 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 666 break; 667 udelay(1); 668 } 669 670 if (i >= adev->usec_timeout) { 671 r = -EINVAL; 672 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx); 673 } 674 675 /* deassert IB preemption */ 676 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0); 677 678 /* deassert the preemption condition */ 679 amdgpu_ring_set_preempt_cond_exec(ring, true); 680 681 return r; 682 } 683 684 static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block, 685 enum amd_clockgating_state state) 686 { 687 return 0; 688 } 689 690 static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block, 691 enum amd_powergating_state state) 692 { 693 struct amdgpu_device *adev = ip_block->adev; 694 struct amdgpu_vpe *vpe = &adev->vpe; 695 696 if (!adev->pm.dpm_enabled) 697 dev_err(adev->dev, "Without PM, cannot support powergating\n"); 698 699 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE"); 700 701 if (state == AMD_PG_STATE_GATE) { 702 amdgpu_dpm_enable_vpe(adev, false); 703 vpe->context_started = false; 704 } else { 705 amdgpu_dpm_enable_vpe(adev, true); 706 } 707 708 return 0; 709 } 710 711 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) 712 { 713 struct amdgpu_device *adev = ring->adev; 714 struct amdgpu_vpe *vpe = &adev->vpe; 715 uint64_t rptr; 716 717 if (ring->use_doorbell) { 718 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr); 719 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr); 720 } else { 721 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi)); 722 rptr = rptr << 32; 723 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo)); 724 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr); 725 } 726 727 return (rptr >> 2); 728 } 729 730 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) 731 { 732 struct amdgpu_device *adev = ring->adev; 733 struct amdgpu_vpe *vpe = &adev->vpe; 734 uint64_t wptr; 735 736 if (ring->use_doorbell) { 737 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 738 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr); 739 } else { 740 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi)); 741 wptr = wptr << 32; 742 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo)); 743 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr); 744 } 745 746 return (wptr >> 2); 747 } 748 749 static void vpe_ring_set_wptr(struct amdgpu_ring *ring) 750 { 751 struct amdgpu_device *adev = ring->adev; 752 struct amdgpu_vpe *vpe = &adev->vpe; 753 754 if (ring->use_doorbell) { 755 dev_dbg(adev->dev, "Using doorbell, \ 756 wptr_offs == 0x%08x, \ 757 lower_32_bits(ring->wptr) << 2 == 0x%08x, \ 758 upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 759 ring->wptr_offs, 760 lower_32_bits(ring->wptr << 2), 761 upper_32_bits(ring->wptr << 2)); 762 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2); 763 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 764 if (vpe->collaborate_mode) 765 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2); 766 } else { 767 int i; 768 769 for (i = 0; i < vpe->num_instances; i++) { 770 dev_dbg(adev->dev, "Not using doorbell, \ 771 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \ 772 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n", 773 lower_32_bits(ring->wptr << 2), 774 upper_32_bits(ring->wptr << 2)); 775 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo), 776 lower_32_bits(ring->wptr << 2)); 777 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi), 778 upper_32_bits(ring->wptr << 2)); 779 } 780 } 781 } 782 783 static int vpe_ring_test_ring(struct amdgpu_ring *ring) 784 { 785 struct amdgpu_device *adev = ring->adev; 786 const uint32_t test_pattern = 0xdeadbeef; 787 uint32_t index, i; 788 uint64_t wb_addr; 789 int ret; 790 791 ret = amdgpu_device_wb_get(adev, &index); 792 if (ret) { 793 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 794 return ret; 795 } 796 797 adev->wb.wb[index] = 0; 798 wb_addr = adev->wb.gpu_addr + (index * 4); 799 800 ret = amdgpu_ring_alloc(ring, 4); 801 if (ret) { 802 dev_err(adev->dev, "dma failed to lock ring %d (%d).\n", ring->idx, ret); 803 goto out; 804 } 805 806 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 807 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); 808 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); 809 amdgpu_ring_write(ring, test_pattern); 810 amdgpu_ring_commit(ring); 811 812 for (i = 0; i < adev->usec_timeout; i++) { 813 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern) 814 goto out; 815 udelay(1); 816 } 817 818 ret = -ETIMEDOUT; 819 out: 820 amdgpu_device_wb_free(adev, index); 821 822 return ret; 823 } 824 825 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) 826 { 827 struct amdgpu_device *adev = ring->adev; 828 const uint32_t test_pattern = 0xdeadbeef; 829 struct amdgpu_ib ib = {}; 830 struct dma_fence *f = NULL; 831 uint32_t index; 832 uint64_t wb_addr; 833 int ret; 834 835 ret = amdgpu_device_wb_get(adev, &index); 836 if (ret) { 837 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 838 return ret; 839 } 840 841 adev->wb.wb[index] = 0; 842 wb_addr = adev->wb.gpu_addr + (index * 4); 843 844 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 845 if (ret) 846 goto err0; 847 848 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0); 849 ib.ptr[1] = lower_32_bits(wb_addr); 850 ib.ptr[2] = upper_32_bits(wb_addr); 851 ib.ptr[3] = test_pattern; 852 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 853 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 854 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 855 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 856 ib.length_dw = 8; 857 858 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 859 if (ret) 860 goto err1; 861 862 ret = dma_fence_wait_timeout(f, false, timeout); 863 if (ret <= 0) { 864 ret = ret ? : -ETIMEDOUT; 865 goto err1; 866 } 867 868 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL; 869 870 err1: 871 amdgpu_ib_free(&ib, NULL); 872 dma_fence_put(f); 873 err0: 874 amdgpu_device_wb_free(adev, index); 875 876 return ret; 877 } 878 879 static void vpe_ring_begin_use(struct amdgpu_ring *ring) 880 { 881 struct amdgpu_device *adev = ring->adev; 882 struct amdgpu_vpe *vpe = &adev->vpe; 883 884 cancel_delayed_work_sync(&adev->vpe.idle_work); 885 886 /* Power on VPE and notify VPE of new context */ 887 if (!vpe->context_started) { 888 uint32_t context_notify; 889 890 /* Power on VPE */ 891 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE); 892 893 /* Indicates that a job from a new context has been submitted. */ 894 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator)); 895 if ((context_notify & 0x1) == 0) 896 context_notify |= 0x1; 897 else 898 context_notify &= ~(0x1); 899 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify); 900 vpe->context_started = true; 901 } 902 } 903 904 static void vpe_ring_end_use(struct amdgpu_ring *ring) 905 { 906 struct amdgpu_device *adev = ring->adev; 907 908 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 909 } 910 911 static int vpe_ring_reset(struct amdgpu_ring *ring, 912 unsigned int vmid, 913 struct amdgpu_fence *timedout_fence) 914 { 915 struct amdgpu_device *adev = ring->adev; 916 int r; 917 918 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 919 920 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 921 AMD_PG_STATE_GATE); 922 if (r) 923 return r; 924 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 925 AMD_PG_STATE_UNGATE); 926 if (r) 927 return r; 928 929 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 930 } 931 932 static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev, 933 struct device_attribute *attr, 934 char *buf) 935 { 936 struct drm_device *ddev = dev_get_drvdata(dev); 937 struct amdgpu_device *adev = drm_to_adev(ddev); 938 939 if (!adev) 940 return -ENODEV; 941 942 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset); 943 } 944 945 static DEVICE_ATTR(vpe_reset_mask, 0444, 946 amdgpu_get_vpe_reset_mask, NULL); 947 948 int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev) 949 { 950 int r = 0; 951 952 if (adev->vpe.num_instances) { 953 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask); 954 if (r) 955 return r; 956 } 957 958 return r; 959 } 960 961 void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev) 962 { 963 if (adev->dev->kobj.sd) { 964 if (adev->vpe.num_instances) 965 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask); 966 } 967 } 968 969 static const struct amdgpu_ring_funcs vpe_ring_funcs = { 970 .type = AMDGPU_RING_TYPE_VPE, 971 .align_mask = 0xf, 972 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0), 973 .support_64bit_ptrs = true, 974 .get_rptr = vpe_ring_get_rptr, 975 .get_wptr = vpe_ring_get_wptr, 976 .set_wptr = vpe_ring_set_wptr, 977 .emit_frame_size = 978 5 + /* vpe_ring_init_cond_exec */ 979 6 + /* vpe_ring_emit_pipeline_sync */ 980 12 + 12 + 12 + /* vpe_ring_emit_fence */ 981 /* vpe_ring_emit_vm_flush */ 982 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 983 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, 984 .emit_ib_size = 7 + 6, 985 .emit_ib = vpe_ring_emit_ib, 986 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync, 987 .emit_fence = vpe_ring_emit_fence, 988 .emit_vm_flush = vpe_ring_emit_vm_flush, 989 .emit_wreg = vpe_ring_emit_wreg, 990 .emit_reg_wait = vpe_ring_emit_reg_wait, 991 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 992 .insert_nop = vpe_ring_insert_nop, 993 .pad_ib = amdgpu_ring_generic_pad_ib, 994 .test_ring = vpe_ring_test_ring, 995 .test_ib = vpe_ring_test_ib, 996 .init_cond_exec = vpe_ring_init_cond_exec, 997 .preempt_ib = vpe_ring_preempt_ib, 998 .begin_use = vpe_ring_begin_use, 999 .end_use = vpe_ring_end_use, 1000 .reset = vpe_ring_reset, 1001 }; 1002 1003 static void vpe_set_ring_funcs(struct amdgpu_device *adev) 1004 { 1005 adev->vpe.ring.funcs = &vpe_ring_funcs; 1006 } 1007 1008 const struct amd_ip_funcs vpe_ip_funcs = { 1009 .name = "vpe_v6_1", 1010 .early_init = vpe_early_init, 1011 .sw_init = vpe_sw_init, 1012 .sw_fini = vpe_sw_fini, 1013 .hw_init = vpe_hw_init, 1014 .hw_fini = vpe_hw_fini, 1015 .suspend = vpe_suspend, 1016 .resume = vpe_resume, 1017 .set_clockgating_state = vpe_set_clockgating_state, 1018 .set_powergating_state = vpe_set_powergating_state, 1019 }; 1020 1021 const struct amd_ip_funcs vpe2_ip_funcs = { 1022 .name = "vpe_v2_0", 1023 .early_init = vpe_early_init, 1024 .sw_init = vpe_sw_init, 1025 .sw_fini = vpe_sw_fini, 1026 .hw_init = vpe_hw_init, 1027 .hw_fini = vpe_hw_fini, 1028 .suspend = vpe_suspend, 1029 .resume = vpe_resume, 1030 .set_clockgating_state = vpe_set_clockgating_state, 1031 .set_powergating_state = vpe_set_powergating_state, 1032 }; 1033 1034 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { 1035 .type = AMD_IP_BLOCK_TYPE_VPE, 1036 .major = 6, 1037 .minor = 1, 1038 .rev = 0, 1039 .funcs = &vpe_ip_funcs, 1040 }; 1041 1042 const struct amdgpu_ip_block_version vpe_v2_0_ip_block = { 1043 .type = AMD_IP_BLOCK_TYPE_VPE, 1044 .major = 2, 1045 .minor = 0, 1046 .rev = 0, 1047 .funcs = &vpe2_ip_funcs, 1048 }; 1049