1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <drm/drm_drv.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_vpe.h" 29 #include "amdgpu_smu.h" 30 #include "soc15_common.h" 31 #include "vpe_v6_1.h" 32 #include "vpe_v2_0.h" 33 #include "vpe_v3_0.h" 34 35 #define AMDGPU_CSA_VPE_SIZE 64 36 /* VPE CSA resides in the 4th page of CSA */ 37 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3) 38 39 /* 1 second timeout */ 40 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000) 41 42 #define VPE_MAX_DPM_LEVEL 4 43 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8 44 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART) 45 46 static void vpe_set_ring_funcs(struct amdgpu_device *adev); 47 48 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) 49 { 50 *remainder = dividend % divisor; 51 return dividend / divisor; 52 } 53 54 static inline uint16_t complete_integer_division_u16( 55 uint16_t dividend, 56 uint16_t divisor, 57 uint16_t *remainder) 58 { 59 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder); 60 } 61 62 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) 63 { 64 u16 arg1_value = numerator; 65 u16 arg2_value = denominator; 66 67 uint16_t remainder; 68 69 /* determine integer part */ 70 uint16_t res_value = complete_integer_division_u16( 71 arg1_value, arg2_value, &remainder); 72 73 if (res_value > 127 /* CHAR_MAX */) 74 return 0; 75 76 /* determine fractional part */ 77 { 78 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART; 79 80 do { 81 remainder <<= 1; 82 83 res_value <<= 1; 84 85 if (remainder >= arg2_value) { 86 res_value |= 1; 87 remainder -= arg2_value; 88 } 89 } while (--i != 0); 90 } 91 92 /* round up LSB */ 93 { 94 uint16_t summand = (remainder << 1) >= arg2_value; 95 96 if ((res_value + summand) > 32767 /* SHRT_MAX */) 97 return 0; 98 99 res_value += summand; 100 } 101 102 return res_value; 103 } 104 105 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) 106 { 107 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency); 108 109 if (GET_PRATIO_INTEGER_PART(pratio) > 1) 110 pratio = 0; 111 112 return pratio; 113 } 114 115 /* 116 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), 117 * VPE FW will dynamically decide which level should be used according to current loading. 118 * 119 * Get VPE and SOC clocks from PM, and select the appropriate four clock values, 120 * calculate the ratios of adjusting from one clock to another. 121 * The VPE FW can then request the appropriate frequency from the PMFW. 122 */ 123 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) 124 { 125 struct amdgpu_device *adev = vpe->ring.adev; 126 uint32_t dpm_ctl; 127 128 if (adev->pm.dpm_enabled) { 129 struct dpm_clocks clock_table = { 0 }; 130 struct dpm_clock *VPEClks; 131 struct dpm_clock *SOCClks; 132 uint32_t idx; 133 uint32_t vpeclk_enalbled_num = 0; 134 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0; 135 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0; 136 137 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 138 dpm_ctl |= 1; /* DPM enablement */ 139 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 140 141 /* Get VPECLK and SOCCLK */ 142 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { 143 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); 144 goto disable_dpm; 145 } 146 147 SOCClks = clock_table.SocClocks; 148 VPEClks = clock_table.VPEClocks; 149 150 /* Comfirm enabled vpe clk num 151 * Enabled VPE clocks are ordered from low to high in VPEClks 152 * The highest valid clock index+1 is the number of VPEClks 153 */ 154 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--) 155 if (VPEClks[idx-1].Freq) 156 vpeclk_enalbled_num = idx; 157 158 /* vpe dpm only cares 4 levels. */ 159 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) { 160 uint32_t soc_dpm_level; 161 uint32_t min_freq; 162 163 if (idx == 0) 164 soc_dpm_level = 0; 165 else 166 soc_dpm_level = (idx * 2) + 1; 167 168 /* clamp the max level */ 169 if (soc_dpm_level > vpeclk_enalbled_num - 1) 170 soc_dpm_level = vpeclk_enalbled_num - 1; 171 172 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ? 173 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq; 174 175 switch (idx) { 176 case 0: 177 pratio_vmin_freq = min_freq; 178 break; 179 case 1: 180 pratio_vmid_freq = min_freq; 181 break; 182 case 2: 183 pratio_vnorm_freq = min_freq; 184 break; 185 case 3: 186 pratio_vmax_freq = min_freq; 187 break; 188 default: 189 break; 190 } 191 } 192 193 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) { 194 uint32_t pratio_ctl; 195 196 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq); 197 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq); 198 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq); 199 200 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18); 201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */ 202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */ 203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */ 204 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */ 205 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */ 206 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__); 207 } else { 208 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__); 209 goto disable_dpm; 210 } 211 } 212 return 0; 213 214 disable_dpm: 215 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 216 dpm_ctl &= 0xfffffffe; /* Disable DPM */ 217 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 218 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); 219 return -EINVAL; 220 } 221 222 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) 223 { 224 struct amdgpu_firmware_info ucode = { 225 .ucode_id = AMDGPU_UCODE_ID_VPE, 226 .mc_addr = adev->vpe.cmdbuf_gpu_addr, 227 .ucode_size = 8, 228 }; 229 230 return psp_execute_ip_fw_load(&adev->psp, &ucode); 231 } 232 233 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) 234 { 235 struct amdgpu_device *adev = vpe->ring.adev; 236 const struct vpe_firmware_header_v1_0 *vpe_hdr; 237 char fw_prefix[32]; 238 int ret; 239 240 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix)); 241 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED, 242 "amdgpu/%s.bin", fw_prefix); 243 if (ret) 244 goto out; 245 246 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 247 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); 248 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); 249 250 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 251 struct amdgpu_firmware_info *info; 252 253 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX]; 254 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX; 255 info->fw = adev->vpe.fw; 256 adev->firmware.fw_size += 257 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 258 259 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL]; 260 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL; 261 info->fw = adev->vpe.fw; 262 adev->firmware.fw_size += 263 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 264 } 265 266 return 0; 267 out: 268 dev_err(adev->dev, "fail to initialize vpe microcode\n"); 269 release_firmware(adev->vpe.fw); 270 adev->vpe.fw = NULL; 271 return ret; 272 } 273 274 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) 275 { 276 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 277 struct amdgpu_ring *ring = &vpe->ring; 278 int ret; 279 280 ring->ring_obj = NULL; 281 ring->use_doorbell = true; 282 ring->vm_hub = AMDGPU_MMHUB0(0); 283 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1); 284 snprintf(ring->name, 4, "vpe"); 285 286 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0, 287 AMDGPU_RING_PRIO_DEFAULT, NULL); 288 if (ret) 289 return ret; 290 291 return 0; 292 } 293 294 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) 295 { 296 amdgpu_ring_fini(&vpe->ring); 297 298 return 0; 299 } 300 301 static int vpe_early_init(struct amdgpu_ip_block *ip_block) 302 { 303 struct amdgpu_device *adev = ip_block->adev; 304 struct amdgpu_vpe *vpe = &adev->vpe; 305 306 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 307 case IP_VERSION(6, 1, 0): 308 case IP_VERSION(6, 1, 3): 309 vpe_v6_1_set_funcs(vpe); 310 break; 311 case IP_VERSION(6, 1, 1): 312 vpe_v6_1_set_funcs(vpe); 313 vpe->collaborate_mode = true; 314 break; 315 case IP_VERSION(2, 0, 0): 316 case IP_VERSION(2, 2, 0): 317 vpe_v2_0_set_funcs(vpe); 318 break; 319 case IP_VERSION(3, 0, 0): 320 case IP_VERSION(3, 0, 1): 321 vpe_v3_0_set_funcs(vpe); 322 break; 323 default: 324 return -EINVAL; 325 } 326 327 vpe_set_ring_funcs(adev); 328 vpe_set_regs(vpe); 329 330 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false"); 331 332 return 0; 333 } 334 335 static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev) 336 { 337 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 338 case IP_VERSION(6, 1, 1): 339 return adev->pm.fw_version < 0x0a640500; 340 default: 341 return false; 342 } 343 } 344 345 static int vpe_get_dpm_level(struct amdgpu_device *adev) 346 { 347 struct amdgpu_vpe *vpe = &adev->vpe; 348 349 if (!adev->pm.dpm_enabled) 350 return 0; 351 352 return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv)); 353 } 354 355 static void vpe_idle_work_handler(struct work_struct *work) 356 { 357 struct amdgpu_device *adev = 358 container_of(work, struct amdgpu_device, vpe.idle_work.work); 359 unsigned int fences = 0; 360 361 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 362 if (fences) 363 goto reschedule; 364 365 if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0) 366 goto reschedule; 367 368 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 369 return; 370 371 reschedule: 372 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 373 } 374 375 static int vpe_common_init(struct amdgpu_vpe *vpe) 376 { 377 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 378 int r; 379 380 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 381 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 382 &adev->vpe.cmdbuf_obj, 383 &adev->vpe.cmdbuf_gpu_addr, 384 (void **)&adev->vpe.cmdbuf_cpu_addr); 385 if (r) { 386 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r); 387 return r; 388 } 389 390 vpe->context_started = false; 391 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler); 392 393 return 0; 394 } 395 396 static int vpe_sw_init(struct amdgpu_ip_block *ip_block) 397 { 398 struct amdgpu_device *adev = ip_block->adev; 399 struct amdgpu_vpe *vpe = &adev->vpe; 400 int ret; 401 402 ret = vpe_common_init(vpe); 403 if (ret) 404 goto out; 405 406 ret = vpe_irq_init(vpe); 407 if (ret) 408 goto out; 409 410 ret = vpe_ring_init(vpe); 411 if (ret) 412 goto out; 413 414 ret = vpe_init_microcode(vpe); 415 if (ret) 416 goto out; 417 418 adev->vpe.supported_reset = 419 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring); 420 if (!amdgpu_sriov_vf(adev)) 421 adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 422 ret = amdgpu_vpe_sysfs_reset_mask_init(adev); 423 if (ret) 424 goto out; 425 out: 426 return ret; 427 } 428 429 static int vpe_sw_fini(struct amdgpu_ip_block *ip_block) 430 { 431 struct amdgpu_device *adev = ip_block->adev; 432 struct amdgpu_vpe *vpe = &adev->vpe; 433 434 release_firmware(vpe->fw); 435 vpe->fw = NULL; 436 437 amdgpu_vpe_sysfs_reset_mask_fini(adev); 438 vpe_ring_fini(vpe); 439 440 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj, 441 &adev->vpe.cmdbuf_gpu_addr, 442 (void **)&adev->vpe.cmdbuf_cpu_addr); 443 444 return 0; 445 } 446 447 static int vpe_hw_init(struct amdgpu_ip_block *ip_block) 448 { 449 struct amdgpu_device *adev = ip_block->adev; 450 struct amdgpu_vpe *vpe = &adev->vpe; 451 int ret; 452 453 /* Power on VPE */ 454 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 455 AMD_PG_STATE_UNGATE); 456 if (ret) 457 return ret; 458 459 ret = vpe_load_microcode(vpe); 460 if (ret) 461 return ret; 462 463 ret = vpe_ring_start(vpe); 464 if (ret) 465 return ret; 466 467 return 0; 468 } 469 470 static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) 471 { 472 struct amdgpu_device *adev = ip_block->adev; 473 struct amdgpu_vpe *vpe = &adev->vpe; 474 475 cancel_delayed_work_sync(&adev->vpe.idle_work); 476 477 vpe_ring_stop(vpe); 478 479 /* Power off VPE */ 480 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 481 482 return 0; 483 } 484 485 static int vpe_suspend(struct amdgpu_ip_block *ip_block) 486 { 487 return vpe_hw_fini(ip_block); 488 } 489 490 static int vpe_resume(struct amdgpu_ip_block *ip_block) 491 { 492 return vpe_hw_init(ip_block); 493 } 494 495 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 496 { 497 int i; 498 499 for (i = 0; i < count; i++) 500 if (i == 0) 501 amdgpu_ring_write(ring, ring->funcs->nop | 502 VPE_CMD_NOP_HEADER_COUNT(count - 1)); 503 else 504 amdgpu_ring_write(ring, ring->funcs->nop); 505 } 506 507 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) 508 { 509 struct amdgpu_device *adev = ring->adev; 510 uint32_t index = 0; 511 uint64_t csa_mc_addr; 512 513 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) 514 return 0; 515 516 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET + 517 index * AMDGPU_CSA_VPE_SIZE; 518 519 return csa_mc_addr; 520 } 521 522 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring, 523 uint32_t device_select, 524 uint32_t exec_count) 525 { 526 if (!ring->adev->vpe.collaborate_mode) 527 return; 528 529 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | 530 (device_select << 16)); 531 amdgpu_ring_write(ring, exec_count & 0x1fff); 532 } 533 534 static void vpe_ring_emit_ib(struct amdgpu_ring *ring, 535 struct amdgpu_job *job, 536 struct amdgpu_ib *ib, 537 uint32_t flags) 538 { 539 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 540 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid); 541 542 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | 543 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf)); 544 545 /* base must be 32 byte aligned */ 546 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); 547 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 548 amdgpu_ring_write(ring, ib->length_dw); 549 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 550 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 551 } 552 553 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 554 uint64_t seq, unsigned int flags) 555 { 556 int i = 0; 557 558 do { 559 /* write the fence */ 560 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 561 /* zero in first two bits */ 562 WARN_ON_ONCE(addr & 0x3); 563 amdgpu_ring_write(ring, lower_32_bits(addr)); 564 amdgpu_ring_write(ring, upper_32_bits(addr)); 565 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); 566 addr += 4; 567 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1)); 568 569 if (flags & AMDGPU_FENCE_FLAG_INT) { 570 /* generate an interrupt */ 571 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); 572 amdgpu_ring_write(ring, 0); 573 } 574 575 /* WA: Force sync after TRAP to avoid VPE1 fail to power off */ 576 if (ring->adev->vpe.collaborate_mode) { 577 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COLLAB_SYNC, 0)); 578 amdgpu_ring_write(ring, 0xabcd); 579 } 580 } 581 582 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 583 { 584 uint32_t seq = ring->fence_drv.sync_seq; 585 uint64_t addr = ring->fence_drv.gpu_addr; 586 587 vpe_ring_emit_pred_exec(ring, 0, 6); 588 589 /* wait for idle */ 590 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 591 VPE_POLL_REGMEM_SUBOP_REGMEM) | 592 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 593 VPE_CMD_POLL_REGMEM_HEADER_MEM(1)); 594 amdgpu_ring_write(ring, addr & 0xfffffffc); 595 amdgpu_ring_write(ring, upper_32_bits(addr)); 596 amdgpu_ring_write(ring, seq); /* reference */ 597 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 598 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 599 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4)); 600 } 601 602 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 603 { 604 vpe_ring_emit_pred_exec(ring, 0, 3); 605 606 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); 607 amdgpu_ring_write(ring, reg << 2); 608 amdgpu_ring_write(ring, val); 609 } 610 611 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 612 uint32_t val, uint32_t mask) 613 { 614 vpe_ring_emit_pred_exec(ring, 0, 6); 615 616 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 617 VPE_POLL_REGMEM_SUBOP_REGMEM) | 618 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 619 VPE_CMD_POLL_REGMEM_HEADER_MEM(0)); 620 amdgpu_ring_write(ring, reg << 2); 621 amdgpu_ring_write(ring, 0); 622 amdgpu_ring_write(ring, val); /* reference */ 623 amdgpu_ring_write(ring, mask); /* mask */ 624 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 625 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10)); 626 } 627 628 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, 629 uint64_t pd_addr) 630 { 631 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 632 } 633 634 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring, 635 uint64_t addr) 636 { 637 unsigned int ret; 638 639 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); 640 amdgpu_ring_write(ring, lower_32_bits(addr)); 641 amdgpu_ring_write(ring, upper_32_bits(addr)); 642 amdgpu_ring_write(ring, 1); 643 ret = ring->wptr & ring->buf_mask; 644 amdgpu_ring_write(ring, 0); 645 646 return ret; 647 } 648 649 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) 650 { 651 struct amdgpu_device *adev = ring->adev; 652 struct amdgpu_vpe *vpe = &adev->vpe; 653 uint32_t preempt_reg = vpe->regs.queue0_preempt; 654 int i, r = 0; 655 656 /* assert preemption condition */ 657 amdgpu_ring_set_preempt_cond_exec(ring, false); 658 659 /* emit the trailing fence */ 660 ring->trail_seq += 1; 661 amdgpu_ring_alloc(ring, 10); 662 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0); 663 amdgpu_ring_commit(ring); 664 665 /* assert IB preemption */ 666 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1); 667 668 /* poll the trailing fence */ 669 for (i = 0; i < adev->usec_timeout; i++) { 670 if (ring->trail_seq == 671 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 672 break; 673 udelay(1); 674 } 675 676 if (i >= adev->usec_timeout) { 677 r = -EINVAL; 678 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx); 679 } 680 681 /* deassert IB preemption */ 682 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0); 683 684 /* deassert the preemption condition */ 685 amdgpu_ring_set_preempt_cond_exec(ring, true); 686 687 return r; 688 } 689 690 static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block, 691 enum amd_clockgating_state state) 692 { 693 return 0; 694 } 695 696 static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block, 697 enum amd_powergating_state state) 698 { 699 struct amdgpu_device *adev = ip_block->adev; 700 struct amdgpu_vpe *vpe = &adev->vpe; 701 702 if (!adev->pm.dpm_enabled) { 703 dev_err(adev->dev, "Without PM, cannot support powergating\n"); 704 return 0; 705 } 706 707 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE"); 708 709 if (state == AMD_PG_STATE_GATE) { 710 amdgpu_dpm_enable_vpe(adev, false); 711 vpe->context_started = false; 712 } else { 713 amdgpu_dpm_enable_vpe(adev, true); 714 } 715 716 return 0; 717 } 718 719 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) 720 { 721 struct amdgpu_device *adev = ring->adev; 722 struct amdgpu_vpe *vpe = &adev->vpe; 723 uint64_t rptr; 724 725 if (ring->use_doorbell) { 726 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr); 727 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr); 728 } else { 729 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi)); 730 rptr = rptr << 32; 731 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo)); 732 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr); 733 } 734 735 return (rptr >> 2); 736 } 737 738 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) 739 { 740 struct amdgpu_device *adev = ring->adev; 741 struct amdgpu_vpe *vpe = &adev->vpe; 742 uint64_t wptr; 743 744 if (ring->use_doorbell) { 745 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 746 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr); 747 } else { 748 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi)); 749 wptr = wptr << 32; 750 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo)); 751 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr); 752 } 753 754 return (wptr >> 2); 755 } 756 757 static void vpe_ring_set_wptr(struct amdgpu_ring *ring) 758 { 759 struct amdgpu_device *adev = ring->adev; 760 struct amdgpu_vpe *vpe = &adev->vpe; 761 762 if (ring->use_doorbell) { 763 dev_dbg(adev->dev, "Using doorbell, \ 764 wptr_offs == 0x%08x, \ 765 lower_32_bits(ring->wptr) << 2 == 0x%08x, \ 766 upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 767 ring->wptr_offs, 768 lower_32_bits(ring->wptr << 2), 769 upper_32_bits(ring->wptr << 2)); 770 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2); 771 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 772 if (vpe->collaborate_mode) 773 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2); 774 } else { 775 int i; 776 777 for (i = 0; i < vpe->num_instances; i++) { 778 dev_dbg(adev->dev, "Not using doorbell, \ 779 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \ 780 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n", 781 lower_32_bits(ring->wptr << 2), 782 upper_32_bits(ring->wptr << 2)); 783 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo), 784 lower_32_bits(ring->wptr << 2)); 785 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi), 786 upper_32_bits(ring->wptr << 2)); 787 } 788 } 789 } 790 791 static int vpe_ring_test_ring(struct amdgpu_ring *ring) 792 { 793 struct amdgpu_device *adev = ring->adev; 794 const uint32_t test_pattern = 0xdeadbeef; 795 uint32_t index, i; 796 uint64_t wb_addr; 797 int ret; 798 799 ret = amdgpu_wb_get(adev, &index); 800 if (ret) { 801 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 802 return ret; 803 } 804 805 adev->wb.wb[index] = 0; 806 wb_addr = adev->wb.gpu_addr + (index * 4); 807 808 ret = amdgpu_ring_alloc(ring, 4); 809 if (ret) { 810 dev_err(adev->dev, "dma failed to lock ring %d (%d).\n", ring->idx, ret); 811 goto out; 812 } 813 814 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 815 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); 816 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); 817 amdgpu_ring_write(ring, test_pattern); 818 amdgpu_ring_commit(ring); 819 820 for (i = 0; i < adev->usec_timeout; i++) { 821 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern) 822 goto out; 823 udelay(1); 824 } 825 826 ret = -ETIMEDOUT; 827 out: 828 amdgpu_wb_free(adev, index); 829 830 return ret; 831 } 832 833 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) 834 { 835 struct amdgpu_device *adev = ring->adev; 836 const uint32_t test_pattern = 0xdeadbeef; 837 struct amdgpu_job *job; 838 struct amdgpu_ib *ib; 839 struct dma_fence *f = NULL; 840 uint32_t index; 841 uint64_t wb_addr; 842 int ret; 843 844 ret = amdgpu_wb_get(adev, &index); 845 if (ret) { 846 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 847 return ret; 848 } 849 850 adev->wb.wb[index] = 0; 851 wb_addr = adev->wb.gpu_addr + (index * 4); 852 853 ret = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256, 854 AMDGPU_IB_POOL_DIRECT, 855 AMDGPU_KERNEL_JOB_ID_VPE_RING_TEST, 856 &job); 857 if (ret) 858 goto err0; 859 ib = &job->ibs[0]; 860 861 ib->ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0); 862 ib->ptr[1] = lower_32_bits(wb_addr); 863 ib->ptr[2] = upper_32_bits(wb_addr); 864 ib->ptr[3] = test_pattern; 865 ib->ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 866 ib->ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 867 ib->ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 868 ib->ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 869 ib->length_dw = 8; 870 871 ret = amdgpu_job_submit_direct(job, ring, &f); 872 if (ret) { 873 amdgpu_job_free(job); 874 goto err1; 875 } 876 877 ret = dma_fence_wait_timeout(f, false, timeout); 878 if (ret <= 0) { 879 ret = ret ? : -ETIMEDOUT; 880 goto err1; 881 } 882 883 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL; 884 885 err1: 886 dma_fence_put(f); 887 err0: 888 amdgpu_wb_free(adev, index); 889 890 return ret; 891 } 892 893 static void vpe_ring_begin_use(struct amdgpu_ring *ring) 894 { 895 struct amdgpu_device *adev = ring->adev; 896 struct amdgpu_vpe *vpe = &adev->vpe; 897 898 cancel_delayed_work_sync(&adev->vpe.idle_work); 899 900 /* Power on VPE and notify VPE of new context */ 901 if (!vpe->context_started) { 902 uint32_t context_notify; 903 904 /* Power on VPE */ 905 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE); 906 907 /* Indicates that a job from a new context has been submitted. */ 908 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator)); 909 if ((context_notify & 0x1) == 0) 910 context_notify |= 0x1; 911 else 912 context_notify &= ~(0x1); 913 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify); 914 vpe->context_started = true; 915 } 916 } 917 918 static void vpe_ring_end_use(struct amdgpu_ring *ring) 919 { 920 struct amdgpu_device *adev = ring->adev; 921 922 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 923 } 924 925 static int vpe_ring_reset(struct amdgpu_ring *ring, 926 unsigned int vmid, 927 struct amdgpu_fence *timedout_fence) 928 { 929 struct amdgpu_device *adev = ring->adev; 930 int r; 931 932 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 933 934 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 935 AMD_PG_STATE_GATE); 936 if (r) 937 return r; 938 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 939 AMD_PG_STATE_UNGATE); 940 if (r) 941 return r; 942 943 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 944 } 945 946 static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev, 947 struct device_attribute *attr, 948 char *buf) 949 { 950 struct drm_device *ddev = dev_get_drvdata(dev); 951 struct amdgpu_device *adev = drm_to_adev(ddev); 952 953 if (!adev) 954 return -ENODEV; 955 956 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset); 957 } 958 959 static DEVICE_ATTR(vpe_reset_mask, 0444, 960 amdgpu_get_vpe_reset_mask, NULL); 961 962 int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev) 963 { 964 int r = 0; 965 966 if (adev->vpe.num_instances) { 967 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask); 968 if (r) 969 return r; 970 } 971 972 return r; 973 } 974 975 void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev) 976 { 977 if (adev->dev->kobj.sd) { 978 if (adev->vpe.num_instances) 979 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask); 980 } 981 } 982 983 static const struct amdgpu_ring_funcs vpe_ring_funcs = { 984 .type = AMDGPU_RING_TYPE_VPE, 985 .align_mask = 0xf, 986 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0), 987 .support_64bit_ptrs = true, 988 .get_rptr = vpe_ring_get_rptr, 989 .get_wptr = vpe_ring_get_wptr, 990 .set_wptr = vpe_ring_set_wptr, 991 .emit_frame_size = 992 5 + /* vpe_ring_init_cond_exec */ 993 6 + /* vpe_ring_emit_pipeline_sync */ 994 12 + 12 + 12 + /* vpe_ring_emit_fence */ 995 /* vpe_ring_emit_vm_flush */ 996 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 997 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, 998 .emit_ib_size = 7 + 6, 999 .emit_ib = vpe_ring_emit_ib, 1000 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync, 1001 .emit_fence = vpe_ring_emit_fence, 1002 .emit_vm_flush = vpe_ring_emit_vm_flush, 1003 .emit_wreg = vpe_ring_emit_wreg, 1004 .emit_reg_wait = vpe_ring_emit_reg_wait, 1005 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1006 .insert_nop = vpe_ring_insert_nop, 1007 .pad_ib = amdgpu_ring_generic_pad_ib, 1008 .test_ring = vpe_ring_test_ring, 1009 .test_ib = vpe_ring_test_ib, 1010 .init_cond_exec = vpe_ring_init_cond_exec, 1011 .preempt_ib = vpe_ring_preempt_ib, 1012 .begin_use = vpe_ring_begin_use, 1013 .end_use = vpe_ring_end_use, 1014 .reset = vpe_ring_reset, 1015 }; 1016 1017 static void vpe_set_ring_funcs(struct amdgpu_device *adev) 1018 { 1019 adev->vpe.ring.funcs = &vpe_ring_funcs; 1020 } 1021 1022 const struct amd_ip_funcs vpe_ip_funcs = { 1023 .name = "vpe_v6_1", 1024 .early_init = vpe_early_init, 1025 .sw_init = vpe_sw_init, 1026 .sw_fini = vpe_sw_fini, 1027 .hw_init = vpe_hw_init, 1028 .hw_fini = vpe_hw_fini, 1029 .suspend = vpe_suspend, 1030 .resume = vpe_resume, 1031 .set_clockgating_state = vpe_set_clockgating_state, 1032 .set_powergating_state = vpe_set_powergating_state, 1033 }; 1034 1035 const struct amd_ip_funcs vpe2_ip_funcs = { 1036 .name = "vpe_v2_0", 1037 .early_init = vpe_early_init, 1038 .sw_init = vpe_sw_init, 1039 .sw_fini = vpe_sw_fini, 1040 .hw_init = vpe_hw_init, 1041 .hw_fini = vpe_hw_fini, 1042 .suspend = vpe_suspend, 1043 .resume = vpe_resume, 1044 .set_clockgating_state = vpe_set_clockgating_state, 1045 .set_powergating_state = vpe_set_powergating_state, 1046 }; 1047 1048 const struct amd_ip_funcs vpe3_ip_funcs = { 1049 .name = "vpe_v3_0", 1050 .early_init = vpe_early_init, 1051 .sw_init = vpe_sw_init, 1052 .sw_fini = vpe_sw_fini, 1053 .hw_init = vpe_hw_init, 1054 .hw_fini = vpe_hw_fini, 1055 .suspend = vpe_suspend, 1056 .resume = vpe_resume, 1057 .set_clockgating_state = vpe_set_clockgating_state, 1058 .set_powergating_state = vpe_set_powergating_state, 1059 }; 1060 1061 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { 1062 .type = AMD_IP_BLOCK_TYPE_VPE, 1063 .major = 6, 1064 .minor = 1, 1065 .rev = 0, 1066 .funcs = &vpe_ip_funcs, 1067 }; 1068 1069 const struct amdgpu_ip_block_version vpe_v2_0_ip_block = { 1070 .type = AMD_IP_BLOCK_TYPE_VPE, 1071 .major = 2, 1072 .minor = 0, 1073 .rev = 0, 1074 .funcs = &vpe2_ip_funcs, 1075 }; 1076 1077 const struct amdgpu_ip_block_version vpe_v3_0_ip_block = { 1078 .type = AMD_IP_BLOCK_TYPE_VPE, 1079 .major = 3, 1080 .minor = 0, 1081 .rev = 0, 1082 .funcs = &vpe3_ip_funcs, 1083 }; 1084