1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <drm/drm_drv.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_vpe.h" 29 #include "amdgpu_smu.h" 30 #include "soc15_common.h" 31 #include "vpe_v6_1.h" 32 33 #define AMDGPU_CSA_VPE_SIZE 64 34 /* VPE CSA resides in the 4th page of CSA */ 35 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3) 36 37 /* 1 second timeout */ 38 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000) 39 40 #define VPE_MAX_DPM_LEVEL 4 41 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8 42 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART) 43 44 static void vpe_set_ring_funcs(struct amdgpu_device *adev); 45 46 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) 47 { 48 *remainder = dividend % divisor; 49 return dividend / divisor; 50 } 51 52 static inline uint16_t complete_integer_division_u16( 53 uint16_t dividend, 54 uint16_t divisor, 55 uint16_t *remainder) 56 { 57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder); 58 } 59 60 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) 61 { 62 bool arg1_negative = numerator < 0; 63 bool arg2_negative = denominator < 0; 64 65 uint16_t arg1_value = (uint16_t)(arg1_negative ? -numerator : numerator); 66 uint16_t arg2_value = (uint16_t)(arg2_negative ? -denominator : denominator); 67 68 uint16_t remainder; 69 70 /* determine integer part */ 71 uint16_t res_value = complete_integer_division_u16( 72 arg1_value, arg2_value, &remainder); 73 74 if (res_value > 127 /* CHAR_MAX */) 75 return 0; 76 77 /* determine fractional part */ 78 { 79 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART; 80 81 do { 82 remainder <<= 1; 83 84 res_value <<= 1; 85 86 if (remainder >= arg2_value) { 87 res_value |= 1; 88 remainder -= arg2_value; 89 } 90 } while (--i != 0); 91 } 92 93 /* round up LSB */ 94 { 95 uint16_t summand = (remainder << 1) >= arg2_value; 96 97 if ((res_value + summand) > 32767 /* SHRT_MAX */) 98 return 0; 99 100 res_value += summand; 101 } 102 103 if (arg1_negative ^ arg2_negative) 104 res_value = -res_value; 105 106 return res_value; 107 } 108 109 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) 110 { 111 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency); 112 113 if (GET_PRATIO_INTEGER_PART(pratio) > 1) 114 pratio = 0; 115 116 return pratio; 117 } 118 119 /* 120 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), 121 * VPE FW will dynamically decide which level should be used according to current loading. 122 * 123 * Get VPE and SOC clocks from PM, and select the appropriate four clock values, 124 * calculate the ratios of adjusting from one clock to another. 125 * The VPE FW can then request the appropriate frequency from the PMFW. 126 */ 127 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) 128 { 129 struct amdgpu_device *adev = vpe->ring.adev; 130 uint32_t dpm_ctl; 131 132 if (adev->pm.dpm_enabled) { 133 struct dpm_clocks clock_table = { 0 }; 134 struct dpm_clock *VPEClks; 135 struct dpm_clock *SOCClks; 136 uint32_t idx; 137 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0; 138 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0; 139 140 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 141 dpm_ctl |= 1; /* DPM enablement */ 142 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 143 144 /* Get VPECLK and SOCCLK */ 145 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { 146 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); 147 goto disable_dpm; 148 } 149 150 SOCClks = clock_table.SocClocks; 151 VPEClks = clock_table.VPEClocks; 152 153 /* vpe dpm only cares 4 levels. */ 154 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) { 155 uint32_t soc_dpm_level; 156 uint32_t min_freq; 157 158 if (idx == 0) 159 soc_dpm_level = 0; 160 else 161 soc_dpm_level = (idx * 2) + 1; 162 163 /* clamp the max level */ 164 if (soc_dpm_level > PP_SMU_NUM_VPECLK_DPM_LEVELS - 1) 165 soc_dpm_level = PP_SMU_NUM_VPECLK_DPM_LEVELS - 1; 166 167 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ? 168 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq; 169 170 switch (idx) { 171 case 0: 172 pratio_vmin_freq = min_freq; 173 break; 174 case 1: 175 pratio_vmid_freq = min_freq; 176 break; 177 case 2: 178 pratio_vnorm_freq = min_freq; 179 break; 180 case 3: 181 pratio_vmax_freq = min_freq; 182 break; 183 default: 184 break; 185 } 186 } 187 188 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) { 189 uint32_t pratio_ctl; 190 191 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq); 192 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq); 193 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq); 194 195 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18); 196 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */ 197 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */ 198 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */ 199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */ 200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */ 201 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__); 202 } else { 203 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__); 204 goto disable_dpm; 205 } 206 } 207 return 0; 208 209 disable_dpm: 210 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 211 dpm_ctl &= 0xfffffffe; /* Disable DPM */ 212 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 213 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); 214 return 0; 215 } 216 217 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) 218 { 219 struct amdgpu_firmware_info ucode = { 220 .ucode_id = AMDGPU_UCODE_ID_VPE, 221 .mc_addr = adev->vpe.cmdbuf_gpu_addr, 222 .ucode_size = 8, 223 }; 224 225 return psp_execute_ip_fw_load(&adev->psp, &ucode); 226 } 227 228 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) 229 { 230 struct amdgpu_device *adev = vpe->ring.adev; 231 const struct vpe_firmware_header_v1_0 *vpe_hdr; 232 char fw_prefix[32], fw_name[64]; 233 int ret; 234 235 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix)); 236 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", fw_prefix); 237 238 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, fw_name); 239 if (ret) 240 goto out; 241 242 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 243 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); 244 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); 245 246 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 247 struct amdgpu_firmware_info *info; 248 249 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX]; 250 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX; 251 info->fw = adev->vpe.fw; 252 adev->firmware.fw_size += 253 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 254 255 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL]; 256 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL; 257 info->fw = adev->vpe.fw; 258 adev->firmware.fw_size += 259 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 260 } 261 262 return 0; 263 out: 264 dev_err(adev->dev, "fail to initialize vpe microcode\n"); 265 release_firmware(adev->vpe.fw); 266 adev->vpe.fw = NULL; 267 return ret; 268 } 269 270 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) 271 { 272 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 273 struct amdgpu_ring *ring = &vpe->ring; 274 int ret; 275 276 ring->ring_obj = NULL; 277 ring->use_doorbell = true; 278 ring->vm_hub = AMDGPU_MMHUB0(0); 279 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1); 280 snprintf(ring->name, 4, "vpe"); 281 282 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0, 283 AMDGPU_RING_PRIO_DEFAULT, NULL); 284 if (ret) 285 return ret; 286 287 return 0; 288 } 289 290 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) 291 { 292 amdgpu_ring_fini(&vpe->ring); 293 294 return 0; 295 } 296 297 static int vpe_early_init(void *handle) 298 { 299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 300 struct amdgpu_vpe *vpe = &adev->vpe; 301 302 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 303 case IP_VERSION(6, 1, 0): 304 vpe_v6_1_set_funcs(vpe); 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 vpe_set_ring_funcs(adev); 311 vpe_set_regs(vpe); 312 313 return 0; 314 } 315 316 static void vpe_idle_work_handler(struct work_struct *work) 317 { 318 struct amdgpu_device *adev = 319 container_of(work, struct amdgpu_device, vpe.idle_work.work); 320 unsigned int fences = 0; 321 322 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 323 324 if (fences == 0) 325 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 326 else 327 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 328 } 329 330 static int vpe_common_init(struct amdgpu_vpe *vpe) 331 { 332 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 333 int r; 334 335 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 336 AMDGPU_GEM_DOMAIN_GTT, 337 &adev->vpe.cmdbuf_obj, 338 &adev->vpe.cmdbuf_gpu_addr, 339 (void **)&adev->vpe.cmdbuf_cpu_addr); 340 if (r) { 341 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r); 342 return r; 343 } 344 345 vpe->context_started = false; 346 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler); 347 348 return 0; 349 } 350 351 static int vpe_sw_init(void *handle) 352 { 353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 354 struct amdgpu_vpe *vpe = &adev->vpe; 355 int ret; 356 357 ret = vpe_common_init(vpe); 358 if (ret) 359 goto out; 360 361 ret = vpe_irq_init(vpe); 362 if (ret) 363 goto out; 364 365 ret = vpe_ring_init(vpe); 366 if (ret) 367 goto out; 368 369 ret = vpe_init_microcode(vpe); 370 if (ret) 371 goto out; 372 out: 373 return ret; 374 } 375 376 static int vpe_sw_fini(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 struct amdgpu_vpe *vpe = &adev->vpe; 380 381 release_firmware(vpe->fw); 382 vpe->fw = NULL; 383 384 vpe_ring_fini(vpe); 385 386 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj, 387 &adev->vpe.cmdbuf_gpu_addr, 388 (void **)&adev->vpe.cmdbuf_cpu_addr); 389 390 return 0; 391 } 392 393 static int vpe_hw_init(void *handle) 394 { 395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 396 struct amdgpu_vpe *vpe = &adev->vpe; 397 int ret; 398 399 ret = vpe_load_microcode(vpe); 400 if (ret) 401 return ret; 402 403 ret = vpe_ring_start(vpe); 404 if (ret) 405 return ret; 406 407 return 0; 408 } 409 410 static int vpe_hw_fini(void *handle) 411 { 412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 413 struct amdgpu_vpe *vpe = &adev->vpe; 414 415 vpe_ring_stop(vpe); 416 417 /* Power off VPE */ 418 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 419 420 return 0; 421 } 422 423 static int vpe_suspend(void *handle) 424 { 425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 426 427 cancel_delayed_work_sync(&adev->vpe.idle_work); 428 429 return vpe_hw_fini(adev); 430 } 431 432 static int vpe_resume(void *handle) 433 { 434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 435 436 return vpe_hw_init(adev); 437 } 438 439 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 440 { 441 int i; 442 443 for (i = 0; i < count; i++) 444 if (i == 0) 445 amdgpu_ring_write(ring, ring->funcs->nop | 446 VPE_CMD_NOP_HEADER_COUNT(count - 1)); 447 else 448 amdgpu_ring_write(ring, ring->funcs->nop); 449 } 450 451 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t index = 0; 455 uint64_t csa_mc_addr; 456 457 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) 458 return 0; 459 460 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET + 461 index * AMDGPU_CSA_VPE_SIZE; 462 463 return csa_mc_addr; 464 } 465 466 static void vpe_ring_emit_ib(struct amdgpu_ring *ring, 467 struct amdgpu_job *job, 468 struct amdgpu_ib *ib, 469 uint32_t flags) 470 { 471 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 472 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid); 473 474 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | 475 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf)); 476 477 /* base must be 32 byte aligned */ 478 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); 479 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 480 amdgpu_ring_write(ring, ib->length_dw); 481 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 482 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 483 } 484 485 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 486 uint64_t seq, unsigned int flags) 487 { 488 int i = 0; 489 490 do { 491 /* write the fence */ 492 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 493 /* zero in first two bits */ 494 WARN_ON_ONCE(addr & 0x3); 495 amdgpu_ring_write(ring, lower_32_bits(addr)); 496 amdgpu_ring_write(ring, upper_32_bits(addr)); 497 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); 498 addr += 4; 499 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1)); 500 501 if (flags & AMDGPU_FENCE_FLAG_INT) { 502 /* generate an interrupt */ 503 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); 504 amdgpu_ring_write(ring, 0); 505 } 506 507 } 508 509 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 510 { 511 uint32_t seq = ring->fence_drv.sync_seq; 512 uint64_t addr = ring->fence_drv.gpu_addr; 513 514 /* wait for idle */ 515 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 516 VPE_POLL_REGMEM_SUBOP_REGMEM) | 517 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 518 VPE_CMD_POLL_REGMEM_HEADER_MEM(1)); 519 amdgpu_ring_write(ring, addr & 0xfffffffc); 520 amdgpu_ring_write(ring, upper_32_bits(addr)); 521 amdgpu_ring_write(ring, seq); /* reference */ 522 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 523 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 524 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4)); 525 } 526 527 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 528 { 529 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); 530 amdgpu_ring_write(ring, reg << 2); 531 amdgpu_ring_write(ring, val); 532 } 533 534 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 535 uint32_t val, uint32_t mask) 536 { 537 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 538 VPE_POLL_REGMEM_SUBOP_REGMEM) | 539 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 540 VPE_CMD_POLL_REGMEM_HEADER_MEM(0)); 541 amdgpu_ring_write(ring, reg << 2); 542 amdgpu_ring_write(ring, 0); 543 amdgpu_ring_write(ring, val); /* reference */ 544 amdgpu_ring_write(ring, mask); /* mask */ 545 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 546 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10)); 547 } 548 549 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, 550 uint64_t pd_addr) 551 { 552 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 553 } 554 555 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring) 556 { 557 unsigned int ret; 558 559 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); 560 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 561 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 562 amdgpu_ring_write(ring, 1); 563 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 564 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 565 566 return ret; 567 } 568 569 static void vpe_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) 570 { 571 unsigned int cur; 572 573 WARN_ON_ONCE(offset > ring->buf_mask); 574 WARN_ON_ONCE(ring->ring[offset] != 0x55aa55aa); 575 576 cur = (ring->wptr - 1) & ring->buf_mask; 577 if (cur > offset) 578 ring->ring[offset] = cur - offset; 579 else 580 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 581 } 582 583 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) 584 { 585 struct amdgpu_device *adev = ring->adev; 586 struct amdgpu_vpe *vpe = &adev->vpe; 587 uint32_t preempt_reg = vpe->regs.queue0_preempt; 588 int i, r = 0; 589 590 /* assert preemption condition */ 591 amdgpu_ring_set_preempt_cond_exec(ring, false); 592 593 /* emit the trailing fence */ 594 ring->trail_seq += 1; 595 amdgpu_ring_alloc(ring, 10); 596 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0); 597 amdgpu_ring_commit(ring); 598 599 /* assert IB preemption */ 600 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1); 601 602 /* poll the trailing fence */ 603 for (i = 0; i < adev->usec_timeout; i++) { 604 if (ring->trail_seq == 605 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 606 break; 607 udelay(1); 608 } 609 610 if (i >= adev->usec_timeout) { 611 r = -EINVAL; 612 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx); 613 } 614 615 /* deassert IB preemption */ 616 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0); 617 618 /* deassert the preemption condition */ 619 amdgpu_ring_set_preempt_cond_exec(ring, true); 620 621 return r; 622 } 623 624 static int vpe_set_clockgating_state(void *handle, 625 enum amd_clockgating_state state) 626 { 627 return 0; 628 } 629 630 static int vpe_set_powergating_state(void *handle, 631 enum amd_powergating_state state) 632 { 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634 struct amdgpu_vpe *vpe = &adev->vpe; 635 636 if (!adev->pm.dpm_enabled) 637 dev_err(adev->dev, "Without PM, cannot support powergating\n"); 638 639 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE"); 640 641 if (state == AMD_PG_STATE_GATE) { 642 amdgpu_dpm_enable_vpe(adev, false); 643 vpe->context_started = false; 644 } else { 645 amdgpu_dpm_enable_vpe(adev, true); 646 } 647 648 return 0; 649 } 650 651 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) 652 { 653 struct amdgpu_device *adev = ring->adev; 654 struct amdgpu_vpe *vpe = &adev->vpe; 655 uint64_t rptr; 656 657 if (ring->use_doorbell) { 658 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr); 659 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr); 660 } else { 661 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi)); 662 rptr = rptr << 32; 663 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo)); 664 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr); 665 } 666 667 return (rptr >> 2); 668 } 669 670 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) 671 { 672 struct amdgpu_device *adev = ring->adev; 673 struct amdgpu_vpe *vpe = &adev->vpe; 674 uint64_t wptr; 675 676 if (ring->use_doorbell) { 677 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 678 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr); 679 } else { 680 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi)); 681 wptr = wptr << 32; 682 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo)); 683 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr); 684 } 685 686 return (wptr >> 2); 687 } 688 689 static void vpe_ring_set_wptr(struct amdgpu_ring *ring) 690 { 691 struct amdgpu_device *adev = ring->adev; 692 struct amdgpu_vpe *vpe = &adev->vpe; 693 694 if (ring->use_doorbell) { 695 dev_dbg(adev->dev, "Using doorbell, \ 696 wptr_offs == 0x%08x, \ 697 lower_32_bits(ring->wptr) << 2 == 0x%08x, \ 698 upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 699 ring->wptr_offs, 700 lower_32_bits(ring->wptr << 2), 701 upper_32_bits(ring->wptr << 2)); 702 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2); 703 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 704 } else { 705 dev_dbg(adev->dev, "Not using doorbell, \ 706 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \ 707 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n", 708 lower_32_bits(ring->wptr << 2), 709 upper_32_bits(ring->wptr << 2)); 710 WREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo), 711 lower_32_bits(ring->wptr << 2)); 712 WREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi), 713 upper_32_bits(ring->wptr << 2)); 714 } 715 } 716 717 static int vpe_ring_test_ring(struct amdgpu_ring *ring) 718 { 719 struct amdgpu_device *adev = ring->adev; 720 const uint32_t test_pattern = 0xdeadbeef; 721 uint32_t index, i; 722 uint64_t wb_addr; 723 int ret; 724 725 ret = amdgpu_device_wb_get(adev, &index); 726 if (ret) { 727 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 728 return ret; 729 } 730 731 adev->wb.wb[index] = 0; 732 wb_addr = adev->wb.gpu_addr + (index * 4); 733 734 ret = amdgpu_ring_alloc(ring, 4); 735 if (ret) { 736 dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret); 737 goto out; 738 } 739 740 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 741 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); 742 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); 743 amdgpu_ring_write(ring, test_pattern); 744 amdgpu_ring_commit(ring); 745 746 for (i = 0; i < adev->usec_timeout; i++) { 747 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern) 748 goto out; 749 udelay(1); 750 } 751 752 ret = -ETIMEDOUT; 753 out: 754 amdgpu_device_wb_free(adev, index); 755 756 return ret; 757 } 758 759 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) 760 { 761 struct amdgpu_device *adev = ring->adev; 762 const uint32_t test_pattern = 0xdeadbeef; 763 struct amdgpu_ib ib = {}; 764 struct dma_fence *f = NULL; 765 uint32_t index; 766 uint64_t wb_addr; 767 int ret; 768 769 ret = amdgpu_device_wb_get(adev, &index); 770 if (ret) { 771 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 772 return ret; 773 } 774 775 adev->wb.wb[index] = 0; 776 wb_addr = adev->wb.gpu_addr + (index * 4); 777 778 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 779 if (ret) 780 goto err0; 781 782 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0); 783 ib.ptr[1] = lower_32_bits(wb_addr); 784 ib.ptr[2] = upper_32_bits(wb_addr); 785 ib.ptr[3] = test_pattern; 786 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 787 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 788 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 789 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 790 ib.length_dw = 8; 791 792 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 793 if (ret) 794 goto err1; 795 796 ret = dma_fence_wait_timeout(f, false, timeout); 797 if (ret <= 0) { 798 ret = ret ? : -ETIMEDOUT; 799 goto err1; 800 } 801 802 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL; 803 804 err1: 805 amdgpu_ib_free(adev, &ib, NULL); 806 dma_fence_put(f); 807 err0: 808 amdgpu_device_wb_free(adev, index); 809 810 return ret; 811 } 812 813 static void vpe_ring_begin_use(struct amdgpu_ring *ring) 814 { 815 struct amdgpu_device *adev = ring->adev; 816 struct amdgpu_vpe *vpe = &adev->vpe; 817 818 cancel_delayed_work_sync(&adev->vpe.idle_work); 819 820 /* Power on VPE and notify VPE of new context */ 821 if (!vpe->context_started) { 822 uint32_t context_notify; 823 824 /* Power on VPE */ 825 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE); 826 827 /* Indicates that a job from a new context has been submitted. */ 828 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator)); 829 if ((context_notify & 0x1) == 0) 830 context_notify |= 0x1; 831 else 832 context_notify &= ~(0x1); 833 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify); 834 vpe->context_started = true; 835 } 836 } 837 838 static void vpe_ring_end_use(struct amdgpu_ring *ring) 839 { 840 struct amdgpu_device *adev = ring->adev; 841 842 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 843 } 844 845 static const struct amdgpu_ring_funcs vpe_ring_funcs = { 846 .type = AMDGPU_RING_TYPE_VPE, 847 .align_mask = 0xf, 848 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0), 849 .support_64bit_ptrs = true, 850 .get_rptr = vpe_ring_get_rptr, 851 .get_wptr = vpe_ring_get_wptr, 852 .set_wptr = vpe_ring_set_wptr, 853 .emit_frame_size = 854 5 + /* vpe_ring_init_cond_exec */ 855 6 + /* vpe_ring_emit_pipeline_sync */ 856 10 + 10 + 10 + /* vpe_ring_emit_fence */ 857 /* vpe_ring_emit_vm_flush */ 858 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 859 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, 860 .emit_ib_size = 7 + 6, 861 .emit_ib = vpe_ring_emit_ib, 862 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync, 863 .emit_fence = vpe_ring_emit_fence, 864 .emit_vm_flush = vpe_ring_emit_vm_flush, 865 .emit_wreg = vpe_ring_emit_wreg, 866 .emit_reg_wait = vpe_ring_emit_reg_wait, 867 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 868 .insert_nop = vpe_ring_insert_nop, 869 .pad_ib = amdgpu_ring_generic_pad_ib, 870 .test_ring = vpe_ring_test_ring, 871 .test_ib = vpe_ring_test_ib, 872 .init_cond_exec = vpe_ring_init_cond_exec, 873 .patch_cond_exec = vpe_ring_patch_cond_exec, 874 .preempt_ib = vpe_ring_preempt_ib, 875 .begin_use = vpe_ring_begin_use, 876 .end_use = vpe_ring_end_use, 877 }; 878 879 static void vpe_set_ring_funcs(struct amdgpu_device *adev) 880 { 881 adev->vpe.ring.funcs = &vpe_ring_funcs; 882 } 883 884 const struct amd_ip_funcs vpe_ip_funcs = { 885 .name = "vpe_v6_1", 886 .early_init = vpe_early_init, 887 .late_init = NULL, 888 .sw_init = vpe_sw_init, 889 .sw_fini = vpe_sw_fini, 890 .hw_init = vpe_hw_init, 891 .hw_fini = vpe_hw_fini, 892 .suspend = vpe_suspend, 893 .resume = vpe_resume, 894 .soft_reset = NULL, 895 .set_clockgating_state = vpe_set_clockgating_state, 896 .set_powergating_state = vpe_set_powergating_state, 897 }; 898 899 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { 900 .type = AMD_IP_BLOCK_TYPE_VPE, 901 .major = 6, 902 .minor = 1, 903 .rev = 0, 904 .funcs = &vpe_ip_funcs, 905 }; 906