1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_vm.h" 24 #include "amdgpu_job.h" 25 #include "amdgpu_object.h" 26 #include "amdgpu_trace.h" 27 28 #define AMDGPU_VM_SDMA_MIN_NUM_DW 256u 29 #define AMDGPU_VM_SDMA_MAX_NUM_DW (16u * 1024u) 30 31 /** 32 * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped 33 * 34 * @table: newly allocated or validated PD/PT 35 */ 36 static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) 37 { 38 int r; 39 40 r = amdgpu_ttm_alloc_gart(&table->bo.tbo); 41 if (r) 42 return r; 43 44 if (table->shadow) 45 r = amdgpu_ttm_alloc_gart(&table->shadow->tbo); 46 47 return r; 48 } 49 50 /* Allocate a new job for @count PTE updates */ 51 static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p, 52 unsigned int count) 53 { 54 enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE 55 : AMDGPU_IB_POOL_DELAYED; 56 struct drm_sched_entity *entity = p->immediate ? &p->vm->immediate 57 : &p->vm->delayed; 58 unsigned int ndw; 59 int r; 60 61 /* estimate how many dw we need */ 62 ndw = AMDGPU_VM_SDMA_MIN_NUM_DW; 63 if (p->pages_addr) 64 ndw += count * 2; 65 ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW); 66 67 r = amdgpu_job_alloc_with_ib(p->adev, entity, AMDGPU_FENCE_OWNER_VM, 68 ndw * 4, pool, &p->job); 69 if (r) 70 return r; 71 72 p->num_dw_left = ndw; 73 return 0; 74 } 75 76 /** 77 * amdgpu_vm_sdma_prepare - prepare SDMA command submission 78 * 79 * @p: see amdgpu_vm_update_params definition 80 * @sync: amdgpu_sync object with fences to wait for 81 * 82 * Returns: 83 * Negativ errno, 0 for success. 84 */ 85 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, 86 struct amdgpu_sync *sync) 87 { 88 int r; 89 90 r = amdgpu_vm_sdma_alloc_job(p, 0); 91 if (r) 92 return r; 93 94 if (!sync) 95 return 0; 96 97 r = amdgpu_sync_push_to_job(sync, p->job); 98 if (r) { 99 p->num_dw_left = 0; 100 amdgpu_job_free(p->job); 101 } 102 return r; 103 } 104 105 /** 106 * amdgpu_vm_sdma_commit - commit SDMA command submission 107 * 108 * @p: see amdgpu_vm_update_params definition 109 * @fence: resulting fence 110 * 111 * Returns: 112 * Negativ errno, 0 for success. 113 */ 114 static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, 115 struct dma_fence **fence) 116 { 117 struct amdgpu_ib *ib = p->job->ibs; 118 struct amdgpu_ring *ring; 119 struct dma_fence *f; 120 121 ring = container_of(p->vm->delayed.rq->sched, struct amdgpu_ring, 122 sched); 123 124 WARN_ON(ib->length_dw == 0); 125 amdgpu_ring_pad_ib(ring, ib); 126 127 if (p->needs_flush) 128 atomic64_inc(&p->vm->tlb_seq); 129 130 WARN_ON(ib->length_dw > p->num_dw_left); 131 f = amdgpu_job_submit(p->job); 132 133 if (p->unlocked) { 134 struct dma_fence *tmp = dma_fence_get(f); 135 136 swap(p->vm->last_unlocked, tmp); 137 dma_fence_put(tmp); 138 } else { 139 dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, 140 DMA_RESV_USAGE_BOOKKEEP); 141 } 142 143 if (fence && !p->immediate) { 144 /* 145 * Most hw generations now have a separate queue for page table 146 * updates, but when the queue is shared with userspace we need 147 * the extra CPU round trip to correctly flush the TLB. 148 */ 149 set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags); 150 swap(*fence, f); 151 } 152 dma_fence_put(f); 153 return 0; 154 } 155 156 /** 157 * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping 158 * 159 * @p: see amdgpu_vm_update_params definition 160 * @bo: PD/PT to update 161 * @pe: addr of the page entry 162 * @count: number of page entries to copy 163 * 164 * Traces the parameters and calls the DMA function to copy the PTEs. 165 */ 166 static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p, 167 struct amdgpu_bo *bo, uint64_t pe, 168 unsigned count) 169 { 170 struct amdgpu_ib *ib = p->job->ibs; 171 uint64_t src = ib->gpu_addr; 172 173 src += p->num_dw_left * 4; 174 175 pe += amdgpu_bo_gpu_offset_no_check(bo); 176 trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate); 177 178 amdgpu_vm_copy_pte(p->adev, ib, pe, src, count); 179 } 180 181 /** 182 * amdgpu_vm_sdma_set_ptes - helper to call the right asic function 183 * 184 * @p: see amdgpu_vm_update_params definition 185 * @bo: PD/PT to update 186 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB 187 * @addr: dst addr to write into pe 188 * @count: number of page entries to update 189 * @incr: increase next addr by incr bytes 190 * @flags: hw access flags 191 * 192 * Traces the parameters and calls the right asic functions 193 * to setup the page table using the DMA. 194 */ 195 static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p, 196 struct amdgpu_bo *bo, uint64_t pe, 197 uint64_t addr, unsigned count, 198 uint32_t incr, uint64_t flags) 199 { 200 struct amdgpu_ib *ib = p->job->ibs; 201 202 pe += amdgpu_bo_gpu_offset_no_check(bo); 203 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); 204 if (count < 3) { 205 amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags, 206 count, incr); 207 } else { 208 amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr, 209 count, incr, flags); 210 } 211 } 212 213 /** 214 * amdgpu_vm_sdma_update - execute VM update 215 * 216 * @p: see amdgpu_vm_update_params definition 217 * @vmbo: PD/PT to update 218 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB 219 * @addr: dst addr to write into pe 220 * @count: number of page entries to update 221 * @incr: increase next addr by incr bytes 222 * @flags: hw access flags 223 * 224 * Reserve space in the IB, setup mapping buffer on demand and write commands to 225 * the IB. 226 */ 227 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, 228 struct amdgpu_bo_vm *vmbo, uint64_t pe, 229 uint64_t addr, unsigned count, uint32_t incr, 230 uint64_t flags) 231 { 232 struct amdgpu_bo *bo = &vmbo->bo; 233 struct dma_resv_iter cursor; 234 unsigned int i, ndw, nptes; 235 struct dma_fence *fence; 236 uint64_t *pte; 237 int r; 238 239 /* Wait for PD/PT moves to be completed */ 240 dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); 241 dma_resv_for_each_fence_unlocked(&cursor, fence) { 242 dma_fence_get(fence); 243 r = drm_sched_job_add_dependency(&p->job->base, fence); 244 if (r) { 245 dma_fence_put(fence); 246 dma_resv_iter_end(&cursor); 247 return r; 248 } 249 } 250 dma_resv_iter_end(&cursor); 251 252 do { 253 ndw = p->num_dw_left; 254 ndw -= p->job->ibs->length_dw; 255 256 if (ndw < 32) { 257 r = amdgpu_vm_sdma_commit(p, NULL); 258 if (r) 259 return r; 260 261 r = amdgpu_vm_sdma_alloc_job(p, count); 262 if (r) 263 return r; 264 } 265 266 if (!p->pages_addr) { 267 /* set page commands needed */ 268 if (vmbo->shadow) 269 amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, 270 count, incr, flags); 271 amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, 272 incr, flags); 273 return 0; 274 } 275 276 /* copy commands needed */ 277 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * 278 (vmbo->shadow ? 2 : 1); 279 280 /* for padding */ 281 ndw -= 7; 282 283 nptes = min(count, ndw / 2); 284 285 /* Put the PTEs at the end of the IB. */ 286 p->num_dw_left -= nptes * 2; 287 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]); 288 for (i = 0; i < nptes; ++i, addr += incr) { 289 pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr); 290 pte[i] |= flags; 291 } 292 293 if (vmbo->shadow) 294 amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); 295 amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); 296 297 pe += nptes * 8; 298 count -= nptes; 299 } while (count); 300 301 return 0; 302 } 303 304 const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = { 305 .map_table = amdgpu_vm_sdma_map_table, 306 .prepare = amdgpu_vm_sdma_prepare, 307 .update = amdgpu_vm_sdma_update, 308 .commit = amdgpu_vm_sdma_commit 309 }; 310